Interfacing SDRAM Devices with Motorola`s MPC8xx
Contents
1. ol lt lt lt lt 5 5 5 gt 5 5 53 lt amp lt amp DESCRIPTION 5 6 7 16 17 18 19 20 21 22 23 cri CST1 0 0 0 Defi the CS stat he 90 CST3 1 1 BST4 1 1 0 1 1 11110 1 BSTI Defines the DQM state Tyry oyta 11 5 2 1 1 0 1 1 8573 GOL 14 GOL Defi the state of A10 GOH 0 1 1 1 1 111 111 6114 RAS Control 0 1 1 0 1 1 1 011 6274 1 1 0 1 1 11110 111 am ha 711 5 G33 GA4T4 DLT3_ GPL4 Control 1 1 1 G4T3 WAEN GPL4 Control 1 1 1 1 1 1111 111 G5T4 Control 1 1 1 1 1 1 111 6573 GPL5 Control 1 1 11 1 Reserved 1 Reserved 1 Loop Loop Control 0 0 EXEN Exception Bit for Reset Defines the Address Multiplexin ee AMX plenig 90 Enables address incrementing 1 Data Transfer Acknowledge 1 1 1404 1 1 Disables2. Timer LAST Defines last DRAM command in the Ram Array 010 0 101 Sigs amp RAM Array 4 5 glS 5191915 Starting Location gt S x 5 Ss 5 lt UPM RAM Array I x x x 5 lt 51 j Last Bit Figure 1a Single Bit and Burst Read Diagrams For UPM Code 1 2 2 5 6 7 4 4 4 4 1 1 L L COMMAND NOP IK READ NOP command active XX nop XX op nor T A0 A9 11 ROW X XCOLUMIN A0 A9 11 X Row W BANKS ALL BANKS 10 ROW aio ROW DISABLE AUTO PRECHARGE SINGLE BANKS DE ABLE AUTO FRECHARGE BAO 1 yY WOK BANK S BAO BANK K BANKS oe ba RRR cour DN Ooi mad _ 5 Latency CRE oon CAS Latency as 45 5 Interfacing SDRAM Devices with Motorola s MPC8xx 5 Micron Technology Inc reserves the right to change products or specifications without notice TN4812 p65 Rev 12 01 2001 Micron Technology Inc TN 48 12 Interfacing with Motorola s MPC8xx Micron Figure 2 Single Bit and Burst WRITE UPM Code Ram A
3. Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 10 ROW W ALL BANKS DISABLE AUTO PRECHARGE SINGLE BANK BAO BA1 BANK TIX DQ DINm YOK Din m 2 XZY Dn m 3 X tRCD tRAS twrR Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc TN 48 12 Micron Interfacing with Motorola s 8 Figure 3 AUTO REFRESH UPM Code Ram Array Location and Bit Location DRAM Commands PRECHARGE ALL AUTO REFRESH DESCRIPTION 1 1 1 1 1 1 1 0 1 0 1 1 1 1 WEE Control 0 1 1 1 1 1 1 ERED ER EERE 1 1 tf 1 GaT3WAEN tt tft Reserved 1 Reserved 1 lolo EXEN exception Defines the Address Multiplexing 10 WA Enables address incrementing UTA Data Transfer Acknowledge 1 Toot Disables Timer LAST Defines last DRAM command in the Ram Array 0 o o UPM RAM Array siz S Starting Location gt 5 in pa s lt UPM RAM Array x x x
4. 10 UPM 11 26 30 Reserved Valid Indicates the contents of the BRx and the ORx registers valid TN 48 12 Interfacing with Motorola s MPC8xx Macron Table 12 ORx Register Descriptions BITS NAME DESCRIPTION 0 16 AM Address Mask Used for multiple external memory bank interfaces The AM bits work in conjunction with the BRx BA register bits 0 Address is Masked 1 Address Bit is Used in the Comparison with BRx BA 17 19 ATM Address Type Mask Restricts access to desired memory addresses in the external memory bank 20 SAM Start Address Multiplex Determines the address multiplexing as defined in the MxMR AMx register Should be set to 1 for SDRAM 0 Not Multiplexed internally 1 Reflects Address the MxMR AMx Register 21 22 G5LA General Purpose Line 5 Determines the control of the GPL5 control pin on the MPC 8 is typically not used unless there is a need for control of for the SDRAM device 0 Output driven on GPL_B5 1 Output driven GPL_A5 G5LS 0 GPL5 Low on the falling edge of GCLK1_50 1 GPL5 High on the falling edge of GCLK1_50 BIH Burst Inhibit Indicates if the memory device supports burst accesses All SDRAM devices support burst access 0 Burst Support 1 No Burst Support Only used for the GPCM machine Only used for the GPCM machine Only used for the GPCM machine Only used for the GPCM machine Reserved WINI
5. 27 WLFx Write Loop Field x WLFx specifies the number of times a write loop is executed in binary similar to the RLFx 28 31 TLFx Timer Loop Field x TLFx defines the number of times a loop is executed by the UPM RAM word in binary Interfacing SDRAM Devices with Motorola s MPC8xx 9 Micron Technology Inc reserves the right to change products or specifications without notice TN4812 p65 Rev 12 01 2001 Micron Technology Inc Micron TN 48 12 Interfacing with Motorola s MPC8xx Table 7 Register Descriptions BITS NAME OP 2 7 UM 9 15 16 18 MB 20 23 MCLF gt 24 25 26 31 MAD DESCRIPTION Command Opcode OP defines the operation to be executed by the 00 WRITE 01 01 READ 10 RUN 11 Reserved Reserved Do not use User Machine UM defines which machine the command is entended 0 UPMA 1 UPMB Reserved Do not use Memory Bank MB defines which Chip Select CS pin is to used in binary CSO 000 CS1 001 Reserved Do not use Memory Command Loop Field MCLF defines how many times the UPM is executed for a run command in binary Reserved Do not use Memory array index MAD is an index to the starting location for the 64 RAM words in the array Table 8 MDR Register Descriptions DESCRIPTION Memory Data MD defines the data to be written to the RAM array BITS NAME Table 9 MAR Register Descr
6. SDRAM device and speed grade RAM array accesses from the MCR register using the RUN command is ex actly the same as the MPC8xx bus accesses Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 Interfacing with Motorola s MPC8xx TN 48 12 Table 4 Open Locations in the UPM RAM Array 0x03 to 0x07 5 locations 0x0d to 0x17 11 locations 0x1b 0x1f 5 locations 0x25 to 0 2 11 locations 0x34 to 0x3b 8 locations 0x3d 0x3f 4 locations The Mode Register setting uses both the MCR and the MAR registers on the MPC8xx The hex code needed to program the SDRAMs MODE REGISTER is loaded into the MAR register and the RUN command is initi ated in the MCR with the appropriate starting location in the UPM RAM array Another note of caution be sure to make adjustments to the value placed in the MAR to take into account whether A30 and or A31 on the MPC8xx are no connects depending on the bus width This is done by shifting the value left one or two places before loading the MAR register Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc TN 48 12 Micron Interfacing with Motorola s MPC8xx Figure 1 Single Bit and Burst Read UPM Code Ram Array Location and Bit Location
7. SDRAM is connected to GPLO on the MPC8xx for Auto Precharge control during READ and WRITE sequences Setting the MxMR bits 16 18 in the to 0b001 will mux 10 to for addressing control during ACTIVE commands pre Diagram 1 MPCxx SDRAM Hardware Interface DQ 0 31 BS 0 3 221 MT48LC8M16A2TG 75 A 29 20 18 7 8 MT48LC8M16A2TG 75 cs1 GPL1 GPL 2 GPL3 GPLO CLKOUT Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron formed by the UPM Refer to page 16 15 of the Motorola MPC860 User s Manual Rev 1 for more detailed infor mation The address multiplexing is done in a similar way for all SDRAMs regardless of the densities and or con figuration For example if the design
8. be initial ized prior to the BRx register The one exception is after hardware reset the BRO register is programmed before the ORO register when programming the boot chip se lect The MPC8xx UPM controller does not keep track of row or bank addresses for the READ and WRITE bus accesses so every access needs to start over with a new ACTIVE command This prevents any interleaving be tween internal SDRAM banks SELF REFRESH Placing the SDRAM components into Self Refresh mode can be accomplished by connecting CKE to GPL5 on the MPC8xx The CKE pin in this case should be viewed as one more command pin like the RAS or CAS pins Self Refresh is initiated by programming the UPM RAM with an AUTO REFRESH command in one of the unused locations of the RAM array which forces GPL5 low during the AUTO REFRESH com mand For exiting Self Refresh a NOP command needs to be stored in another unused area of the RAM array which forces GPL5 CKE high for that NOP command As an example starting in address 0x0d program the SELF REFRESH command as described above and its last word should include the LAST bit set In a similar way the Self Refresh Exit sequence can be stored as an example starting in address 0 1 and again its last word should include the LAST bit set Use the RUN command in the MCR register to ex ecute these UPM RAM array location for the desired command Table 5 Self Refresh SDRAM COMMAND UPM RAM WORD SE
9. of the following events takes place 1 When a bus access is automatically initiated by the MPC8xx or other external bus master 2 When a RUN command is initiated in the MCR Memory Command Register by MPC8xx soft ware The UPM RAM array can be written to or read from by issuing the appropriate command in the MCR regis ter by software This is how the RAM array as seen in Figures 1 2 and 3 is initially built using the MDR Memory Data Register as a source of data used to build the array and the WRITE command from the MCR Each SDRAM command such as ACTIVATE READ or WRITE is stored into the RAM array individually to set up the appropriate command sequence to be executed by the UPM Careful attention should be given to make sure the sequences adhere to all of the AC timing pa rameters as defined in the SDRAM data sheet In Fig ures 1 3 some of the NOP commands can be elimi nated or added depending on the speed of the SDRAM being used Please refer to the SDRAM data sheet for AC timing specifications Most SDRAM operating sequences that are pro grammed from the MCR start from a location pre defined in the UPM RAM array The operation will con tinue until the last bit command unless there is a loop programmed into the sequence The starting locations in the RAM array for the specific access types are pre defined and cannot be changed See Table 3 for a list of these accesses and their staring locations The UPM will autom
10. x x xr so Ss 5S S 5S 5S 5 Last Bit UPM Loop Interfacing SDRAM Devices with Motorola s MPC8xx 7 Micron Technology Inc reserves the right to change products or specifications without notice TN4812 p65 Rev 12 01 2001 Micron Technology Inc Micron UPM SPECIFIC REGISTERS The MPC8xx microprocessor has four specific regis ters to define the interface and functionality for the SDRAM components 1 Machine x Mode Register MxMR defines the glo bal features for each UPM MAMR and MBMR 2 Memory Command Register MCR executes READs and WRITEs to the UPM Ram array It is also used to access the UPM RAM array for op erations such as loading the SDRAMs Mode Reg ister 3 Memory Data Register MDR is programmed with data to be written to the UPM RAM array for the UPM MCR register when building the array 4 Memory Address Register is used to specify the address driven on the external bus when the RUN command is issued from the MCR register to the UPM RAM array The additional two registers are the Base Register BRx and the Option Register ORx There are eight pairs 0 7 of the BRx and ORx registers one pair for each bank of the MPC8xx Both of these registers are used with the UPM and the GPCM memory controllers The GPCM will not be covered in this document because it cannot be used to interface to SDRAM components The BRx is used to define the Base Address for the particular Bank and other gene
11. LF REFRESH Entry 0x08000200D SELF REFRESH Exit 0x08000201B Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Micron TN 48 12 Interfacing with Motorola s MPC8xx Table 6 MxMR Register Descriptions BITS NAME DESCRIPTION 0 7 Periodic Timer period bits will set the UPMs internal counter to make sure Refresh is taken care of at in the appropriate amount of time 8 PTXE Periodic Timer enable PTXE bit will enable the refresh counter in the UPM PTxE disable 0 PTXE enable 1 9 11 AMx Address Multiplex Size AMx bits set the address multiplexing refer to table 16 17 in the MPC860 users manual and Table 2 in this document In reference to the first row address in relation the MPC8xx address pin 12 Reserved Do not use 13 14 DSx Disable Timer Period DSx sets the tRAS MIN requirement in clock cycles for the UPM 00 1 clock 01 2 clocks 10 3 clocks 11 4 clocks 15 Reserved Do not use 16 18 GOCLx General Line 0 Control GOCL selects the Auto precharge pin on the SDRAM 010 A10 19 GPLx4DIS GPL out put line disable GPLx4DIS is set to either freeze the UPM or use GPL4 as the WE the SDRAM 0 defines GPL4 1 defines UPWAIT 20 23 RLFx Read Loop Field x RLFx specifies the number of times a read loop is executed in binary with 0001 1 1111 15 Note 0000 16 24
12. Micron TECHNICAL NOTE INTRODUCTION The Motorola MPC8xx integrated PowerPC microprocessor is designed for embedded solutions The interface between this device and an SDRAM is done through one of the two UPMs User Program mable Machines to provide a glueless interface The is a RAM based programmable machine control ling the external signals connected to the SDRAM sup porting both single and burst READs and WRITEs INTERFACE The hardware interface from SDRAM to the MPC8xx family requires a complete understanding of how the address multiplexing is done by the UPM Diagram 1 illustrates this interface using two MT48LC8M16A2 SDRAM devices in a 32 bit wide configuration TN 48 12 Interfacing with Motorola s MPC8xx INTERFACING SDRAM DEVICES WITH MOTOROLA S MPC8XX The addressing for the MCP8xx uses as the Most Significant Bit MSB while the MSB for the SDRAM are the bank address lines BA1 and BAO followed by 11 For the MPC8xx the Least Significant Bits LSB A31 and A30 are left unconnected when implementing a 32 bit wide bus For a 16 bit wide bus A31 is left unconnected Table 1 shows the address multiplexing for two of the MT48LC8M16A2 devices with two bank address lines 12 row addresses and 9 columns From Table 1 the physical hardware connection scheme can be derived as displayed in Table 2 Note that address pin 19 for the MPC8xx is not connected to the SDRAM Instead the pin 10 for the
13. N mj 2 w 1 N N lt Interfacing SDRAM Devices with Motorola s MPC8xx 1 2 Micron Technology Inc reserves the right to change products or specifications without notice TN4812 p65 Rev 12 01 2001 Micron Technology Inc Macron CONCLUSION There are a few key points to remember when inter facing the MPC8xx microprocessor with SDRAM The address multiplexing is one area in the imple mentations that should not deviate from the example While this was not the case with older DRAM technolo gies such as EDO or Fast Page mode DRAMs with SDRAM devices the address connections are also used to program the MODE REGISTER to define the device s operation Deviation from the standard address multi plexing can cause unknown values in the mode regis ter causing the SDRAM device to not function properly REFERENCES 1 Rick Nelson at Motorola 2 MPC860 Users Manual Rev 1 3 Motorola SDRAM MPC8xx Application Note Interfacing with Motorola s 8 TN 48 12 When dealing with multiple external SDRAM banks it is important to remember the LOAD MODE REGIS TER command needs to be done for both banks of memory The periodic timer also needs to be adjusted to compensate for the added memory When programming the UPM it is important to have the GOLO GOL1 and GOH1 bits in RAM array set low during all SDRAM ACTIVE commands This will allow the UPM to use
14. atically begin at these starting points when the memory controller detects a bus access involving the SDRAM and continue until the LAST bit is detected in the RAM word This is the reason the starting loca tions are set and cannot be changed Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Macron Table 3 Predefinded Starting Locations for the UPM RAM Array 0x00 for read single beat access 0x08 for read burst access 0x18 for write single beat access 0x20 for write burst access 0x30 for periodic timer access 0x3c for exception access The MPC860 UPM Programming Tool found on Motorola s web page is useful when developing the UPM RAM array This can be found on the Netcom Tools page http www mot com SPS RISC netcomm tools The MPC860 UPM Programming Tool has a wave editor window that graphically dis plays the internal RAM array in the UPM and how it is programmed The RAM word bit settings can be found in the MPC860 Users Manual Rev 1 on page 16 36 through 16 39 Note that any unused portion of the RAM array can be used to store any sequence to be initiated by soft ware in the MCR register to address operations such as Mode Register Settings Self Refresh and Power Down The following locations are left free in this example and illustrated in gray on Figures 1 3 This does not mean there might be more free locations depending on the
15. e RAS CAS and WE pins for the SDRAM should be connected to GPL1 GPL2 and GPL3 on the MPC8xx controller The CS for the SDRAM is con nected to one of the eight CS lines on the MPC8xx typically starting with CS1 CS0 is usually reserved for the boot ROM There are a few key points to remember when de signing an interface between the MPC8xx PowerPC and SDRAM The width of the SDRAM part is only indi rectly related to how the address multiplexing is ac complished in the MPC8xx The total width of the bus is the key Each bank in the MPC8xx Memory Controller can support an 8 16 or 32 bit wide bus from almost any combination of SDRAM components From the previ ous example the last two LSBs are left as No Connects This is always done for a total bus width of 32 For a bus width of 16 only the LSB is left as a No Connect For a bus width of 8 there are no No Connects the address ing starts with the LSB A31 Word of caution under no circumstances should the 60x Bus signals be used with the Memory Control ler signals especially the 60x R W signals Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 Interfacing with Motorola s MPC8xx TN 48 12 UPM OPERATIONS The UPM RAM array controls all of the signals con necting the MPC8xx to the SDRAM devices which in clude the Chip Selects 0 7 Byte Selects 0 3 and GPLs 0 5 The UPM will assume control over these signals when one of two
16. iptions DESCRIPTION 0 31 MA Memory Address MA specify the address driven on the external bus when the RUN command is issued from the MCR Used to define contact of the SDRAM Mode Register Table 10 MPTPR Register Descriptions BITS NAME DESCRIPTION 0 7 PTP Periodic Timer Prescaler PTP contains the division factor needed to define the Refresh interval 8 15 Reserved Do not use Interfacing SDRAM Devices with Motorola s MPC8xx 1 0 TN4812 p65 Rev 12 01 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc TN 48 12 Interfacing with Motorola s MPC8xx Macron Table 11 BRx Register Descriptions BITS NAME DESCRIPTION 0 16 BA Base Address Used for access to multiple external memory banks in conjunction with ORx AM register 7 19 AT Address Type Used to limit access to curtain address in the SDRAM if needed 20 21 PS Port Size Specifies the total external bus width 00 32 Bits Wide 01 8 Bits Wide 10 16 Bits Wide 00 Reserved PARE Parity Enable Enables parity for error detection 0 Disable 1 Enable WP Write Protect Sets a portion of the memory in a READ only state within a defined address space 0 Disable 1 Enable 24 25 MS Machine Select Selects the Memory controller that is being used 00 GPCM not used for SDRAM 01 Reserved N N Ww
17. ral addressing issues such as the selection of which controller will be used for a specific bank of memory UPMA or UPMB The refer ence to bank is not in relation to the SDRAM internal banks but to the multiple banks of memory that the MPC8xx supports The ORx is used to set up the ad dress comparison for the external bus GENERAL OPERATION General operation of the PowerPC and SDRAM is fairly straight forward once the UPM RAM array is setup and the registers are defined As described earlier the RAM array is programmed using the MCR OP and the MCR MAD register bits The binary data word to be programmed into the RAM array is loaded into the Memory Data Register MDR This would correspond to a command on the SDRAM side such as an ACTIVE command The MCR MAD bits identify the location where the data in the MDR is to be written in the RAM array The WRITE opcode field in the MCR OP is then set to 0b0 0 to initiate a WRITE transfer This is done for each SDRAM command in the RAM array word to build the timing sequences as illustrated on pages 4 through 6 Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 Interfacing with Motorola s MPC8xx TN 48 12 The MxMR register can then be programmed fol lowed by the ORx and BRx registers The ORx and BRx registers should always be programmed after all of the UPM specific registers are set up Once the UPM spe cific register are set the ORx register should
18. requires two 256Mb MT48LC16M16A2 components the only change would be adding 12 mapped to 17 for the MPC8xx which also moves the Bank Address pins on Interfacing with Motorola s MPC8xx TN 48 12 the SDRAM to A7 and This is on the hardware side only The UPM will have to be programmed for the different densities and memory configurations This is done the MxMR AMx register bits For the 128Mb x16 example in Table 2 address bits A20 A9 have to be multiplexed to A29 A18 of the MPC8xx for the Row ad dress Table 16 17 on page 16 44 of the Motorola MPC860 User s Manual Revl notes that the MxMR AMx register must be set to 0b001 Table 1 Address Multiplexing ROW ADDRESS BANK ADDRESS scorn ADDRESS ae 7 MPC8xx Address A 31 30 A 29 21 A 20 9 A 8 7 Table 2 Address Multiplexing 8xx Address SDRAM 8xx 8xx 8xx Pin SDRAM Pin 0 A1 A27 A2 A18 A27 A2 25 A4 A16 A25 4 5 22 7 A13 A22 A7 20 Row 9 11 9 19 10 10 10 1 ma o J o J a o 0 __ oo SS 9 20 BAO 7 BA1 BA1 Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc Macron Th
19. rrayLocation and Bit Location PRECHARGE ACTIVATE PRECHARGE DRAM Commands ACTIVATE DESCRIPTION Defines the CS state Defines the DQM state GOL GOL GOH GOH G1T4 G1T3 G2T4 G2T3 G3T4 G3T3 GAT4 DLT3 G5T4 G5T3 Loop EXEN Defines the state of A10 RAS Contro WE Control Loop Contro Exception Bit for Reset Defines the Address Multiplexing Enables address incrementing Data Transfer Acknowledge TODT Disables UPM Timer LAST Defines last DRAM command in the Ram Arra 2 2 Q 5555 gt wn Cyl 581500 2je 53 3 3 3 5 alalala efaj lt UPM RAM Array Starting Location UPM RAM Array Last Bit Ox0f07fc04 0x00bd7c00 Ox00fffc00 Figure 2 Single Bit and Burst WRITE Diagrams For UPM Code To Th 3 T2 5 T6 4 4 COMMAND x COMMAND X KE nor WRITE XX nor COLUMN m 9 11 ROW A0 A9 A11 X ROW W COLUMN m W ALL BANKS ato DISABLE AUTO PRECHARGE SINGLE BANK BAO BAI W 59 twr tRAS
20. the 10 line as a row address during ACTIVE command for the SDRAM Finally this document covers only one way to imple ment the MPC8xx microprocessor with SDRAM and is by no means the only way it can be done 8000 S Federal Way P O Box 6 Boise ID 83707 0006 Tel 208 368 3900 E mail prodmktg micron com Internet http www micron com Customer Comment Line 800 932 4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology Inc PowerPC is a registered trademark of IBM Interfacing SDRAM Devices with Motorola s MPC8xx TN4812 p65 Rev 12 01 13 Micron Technology Inc reserves the right to change products or specifications without notice 2001 Micron Technology Inc
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