SMT911 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. 3l 10 26 MAXIM B Register 8 Ox17 Gain enne 3l 10 27 MAXIM B Register 9 0x18 TX 32 10 206 ADDAC A Register 32 LU 29 DID AC A L UA Lesser 32 I0 250ADDAC A ROPISIGI 2 0X 32 IO SIL ADDAC A ReSISISE 33 I NS Bride Register OXID deans 33 A Register 3 e OX lE ee eee 33 e ND ede e 34 IOS NDDACOSCRSSISISE 7 e 34 I0 30 ADDAC A Register 34 Mo 35 10 250 ADDAC A ReGIStCr T0 0X2 35 36 L0 40 ADIDJAC B Reglster 0X25 36 Page 4 of 38 Last Edited 01 06 2010 10 09 00 10 41 ADDAC B Register 1 0x20 eeeeeeeeeeeeeeeeeeee nennen nennen nnn nnne nnn nnn nnn nnn nnn nis 36 10 42 ADDAC Register 2 X2 sivsarscacennscaininasedanoonsndsoien Puce t cb Hue 36 10 43 ADDAC Register 3 0 28 36 10 44ADDAC B Register 4 0X29 mc m 30 10 45 ADDAC B Register 5 OX2A ccccccccccececeeeeeeeeeeeeeeeeeeeeeeneeseseeeeeeeseseseseseenenenseseensnenenens 36 12. The application will begin by resetting the module for correct initialization then writing the default configuration settings to the registers mapped in the FPGA They are then double checked and written from the FPGA to the mezzanine via SPI at which time the module is placed in Standby and a menu is presented At this point all four LED s on the SMT351T SX50 should be on D3 MAXIM channel A good LO clock lock D4 MAXIM channel B good LO clock lock D5 DDR2 memory initialized successfully D6 Good clock lock from both AD9863 IC s to the FPGA PLL To step right through the demo using default settings press 3 to load the SINE dat file into the DDR2 memory of the SMT351T SX50 and then press 1 to place the mezzanine into TX mode and repeatedly playback the stored memory wave The buffer that is created in the DSP s memory to store the data file needs to be the same size as the number of samples in the data file If a custom waveform is to be selected for playback this can be set at the top of the header file in the DSP task by define 128 By default the sine wave stored in memory will be played onto both channels and B of the mezzanine but this can be altered in the Data_TX c file in the DSP task To adjust the gain or to select a different carrier frequency simply choose the corresponding menu option and follow the directions as presented on screen To quit the application press
3. 100 current maximum linearity 7 0 Tx VGA linearity 00 5096 current minimum linearity 01 63 current 6 0 10 78 current 11 10096 current maximum linearity Tx Upconverter Linearity 00 50 current minimum linearity 01 63 current 10 78 current 11 100 current maximum linearity 00 max base band gain 5dB 01 max base band gain 3dB 10 max base band gain 1 5dB 11 max base band gain 10 16 MAXIM A Register 8 OxOD RX Gain This register sets the RX base band gain and RF gain when MAXIM A Register 6 Bit12 EI MAXIM A Register 8 OxOD Byte 1 0 015 D14 D13 D12 DIO D9 D8 D7 D6 D5 D3 D2 DI DO Defaut 0 1 J 1 J Reconfigurable bits Rx base band and RF gain control bits Bit 6 maps to digital input pin Bit6 BitDO 0000000 corresponds to minimum gain SMT911 User Manual SMT911 Page 30 of 38 Last Edited 01 06 2010 10 09 00 o i 10 17 MAXIM A Register 9 OxOE TX VGA Gain This register sets the TX VGA gain when MAXIM A Register 7 Bit10 1 MAXIM A Register 9 OxOE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 o o
4. 0 Rx 1 Tx 2 SpiBl0n20 option for 10 or 20 bit 0 20 bit 1 10 bit 1 O SPLIO Control in conjunction with to override external TxnRx pin operation SpiClone 1 for clone mode 0 other 10 39 ADDAC A Register 11 0x24 This register is used for configuring the rest of the clock settings of ADDAC A ADDAC A Register 11 0x24 Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Defaut 0 0 0 0 Reconfigurable bits Description 5 le to IFACE2 0 IFACE2 normal 1 IFACE2 switched to PLL output clock FD 2 0 PLL Slow 0 standard 1 changes phase noise generated from PLL clock 10 40 ADDAC B Register 0 0x25 Same settings as ADDAC A See corresponding register 10 41 ADDAC B Register 1 0x26 Same settings as ADDAC A See corresponding register 10 42 ADDAC B Register 2 0x27 Same settings as ADDAC A See corresponding register 10 43 ADDAC B Register 3 0x28 Same settings as ADDAC A See corresponding register 10 44 ADDAC B Register 4 0x29 Same settings as ADDAC A See corresponding register 10 45 ADDAC B Register 5 OX2A Same settings as ADDAC A See corresponding register 10 46 ADDAC B Register 6 Ox2B Same settings as ADDAC A See corresponding register 10 47 ADDAC B Registe
5. D6 D5 D3 DI DO o 0 0 0 1 1 Reconfigurable bits 2 LSBs of the Fractional Divider Ratio Integer Divider Ratio Word Programming Bits Valid values are from 128 Bit7 BitO 10000000 to 255 Bit7 BitO 11111111 10 10 MAXIM A Register 2 0x07 Fractional Divider Ratio This register along with bit 13 and bit 12 of the integer divider ratio register controls the fractional divider ratio with 16 bit resolution Bit 13 to bit O of this register combined with bit 13 and bit 12 of the integer divider ratio register form the whole fractional divider ratio To retain the complete frequency plan please refer to the appendix tables MAXIM A Register 2 0x07 Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Defaut 0 0 1 1 1 11 Reconfigurable bits 13 BitO Bit13 refer to Appendix Frequency Plan and Divider Ratio Programming Words 8 JIi L5 a Jo O i 10 11 MAXIM A Register 3 0x08 Band Select and PLL This register configures the programmable reference frequency dividers for the SMT911 User Manual SMT911 Page 28 of 38 Last Edited 01 06 2010 10 09 00 synthesizer and sets the DC current for the charge pump The programmable reference frequency divider provides the reference
6. 27 10 9 MAXIM A Register 1 0x06 Integer Divider 28 10 10MAXIM A Register 2 0 07 Fractional Divider Ratio 28 10 11 MAXIM A Register 3 0 08 Band Select and PLL 28 10 12 A Register 4 0x09 Calibration eeeeennnnnnnnne 29 10 13 MAXIM A Register 5 OxOA Low pass Filter 29 10 14 MAXIM A Register 6 OxOB RX 550 30 10 15 MAXIM A Register 7 OxOC TX Linearity Gain eeeeeeeenn 30 10 16 A Register 8 OxOD RX Gain een 30 10 17MAXIM A Register 9 OxOE TX eren 3l 10 18MAXIM B Register 0 OxOF Standby 31 10 19MAXIM B Register 1 0 10 Integer Divider 31 10 20 MAXIM B Register 2 Ox11 Fractional Divider Ratio 3l 10 21 MAXIM B Register 0x12 Band Select and PLL 31 10 22MAXIM B Register 4 0x13 31 10 23 MAXIM B Register 5 0x14 Low pass Filter 31 10 24 MAXIM B Register 6 0x15 RX Control RSSI eene 31 10 25 MAXIM B Register 7 0 16 TX Linearity Gain
7. D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 0 0 0 0 1 1 Reconfigurable bits 1 ADOA amp Breset 1 reset 0 normal operation Transceiver A amp B Reset 1 reset 0 normal operation 10 4 Test Register 0x01 Any 16 bit word can be written and read from this register to verify proper operation of the Comport Test Register 0x01 Byte 1 0 D15 D14 D13 D12 D11 D10 D9 07 D6 D5 D3 DI DO Defaut 1 2 1 1 1 10 5 Function Register 0 0x02 This register allows the basic setup of the SMT911 transceiver card including activating MIMO operation choosing the frequency band selecting memory and defining TX or RX operation Function Register 0 0x02 TET TUNE 99 a S m e TOO Defaut 0 o 1 Reconfigurable bits 3 0 0 use memory DDR2 RAM 1 no memory direct transfer 2 0 Working mode 1 Receiver 0 Transmitter Frequency range 0 2 4 GHz 802 115 1 5 2 GHz 802 113 1 MIMO activation 0 SISO mode only path A 1 MIMO active 10 6 Function Register 1 0x03 This register controls the switching
8. frequency to the phase detector by dividing the signal of the crystal oscillator MAXIM A Register 3 0x08 Byte 1 0 D15 D14 D13 D12 D11 DIO D9 D7 D6 D5 D3 DI DO mee o 0 1 1 1 Reconfigurable bits 13 0 normal operation 1 MIMO applications 10 0 X These Bits set the VCO Sub Band when programmed by using SPI Bit8 1 00 lowest frequency band 11 highest frequency band VCO SPI Bandswitch Enable 0 disable SPI control bandswitch is done by FSM 1 bandswitch is done by SPI programming 7 0 VCO Bandswitch Enable 0 disable 1 start automatic bandswitch RF Frequency Band Select in 802 11a Mode Bit0 1 0 4 9GHz to 5 35GHz band 1 5 47GHz to 5 875GHz Band 5 0 PLL Charge Pump Current Select 0 2mA 1 4mA These Bits Set the Reference Divider Ratio 001 corresponds to 1 and 111 corresponds to R 2 X 7 1 qu O RE Frequency Band Select 0 2 4GHz Band 1 5GHz band 10 12 MAXIM A Register 4 0x09 Calibration This register configures the TX RX calibration modes MAXIM A Register 4 0x09 Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Defaut 0 0 O 1 1 Re
9. in both ADC DAC chips and provide the transceiver PLL s a reference for creating the required 2 4GHz or 5GHz carrier frequency Both of these circuits can be run for wider synchronization from these connectors or from a fixed on board oscillator output of 40MHz The maximum clocking speed of the internal ADC s is 50MHz and the maximum clocking speed of the internal DAC s is 200MHz attainable through internal PLL multiplying Last Edited 01 06 2010 10 09 00 SMT911 User Manual SM 3 1 Interface Description 4 SMA connectors 50 Ohm for dual band antennas providing TX RX e Two MMCX connectors 50 Ohm external clock input Samtec connector for 5 V and 3 3 V power supply e 120 Samtec OSH connector for all digital I O signals JTAG connector for debug access to FPGA on base board Plugs directly into a wide range Sundance SLB TIMs 3 1 1 Electrical Description Each pin on the BKT power connector 33 pins in total can carry 1 5 A Digital 5V D 5VO digital 3V3 D 3V3 and digital ground DGND are provided over this connector D 3V3 and 0 5 0 are assigned four pins each The daughter card can thus draw a total of 6A of each of these two supplies 3 2 Block Diagram The major elements of the SMT911 are shown in the block diagram below single channel shown To second channel 40MHz oscillator Clock distribution External clock V V x RF Front End Transceiver ADC DAC SiGe 2543 MA
10. 0 46 ADDAC Register 6 2 36 10 47 ADDAC B Register 7 sau uae asc ae Ec aria ca 36 Ed S ADDAC 8 eX eee Ea 36 10 49 ADDAC Register 9 0 2 nennen nnne nn nini nn nhan sanas sss s nnn na 37 10 50ADDAC Register 10 0 2 37 10 51 ADDAC B Register 11 0 e enne enne 37 15 52 37 10 53 Update RSSI Register 0 32 37 10 54RSSI Register 37 RSSI Register B 38 Introduction The SMT911 is an advanced high quality MIMO transceiver card designed to cover all features of future high speed MIMO radio systems The SMT911 comprises two complete fully configurable transceiver chains between two dual 12 bit digital interfaces and two dual band 50 Ohm antenna ports for each channel Each transceiver chain is comprised of an integrated RF frontend band switch T R switch and power amplifier up down converters with on chip PLLs and high performance analog to digital and digital to analog converters for the I Q signals and additional analog to digital converters for RSSI conversion With a single on board crystal or externally supplied common reference clock for the transceiver PLL s multiple SMT
11. 9 4 3 2 Receiver The receiver application works much the same way as the transmitter Open a Diamond Server and launch SMT911 362 SX50T RX app The mezzanine will reset and initialize the mezzanine into Standby then write all the configuration registers in the FPGA with the default settings provided from BlockofRegisters These are next double checked and written via SPI to the ADC and transceiver IC s At this point a menu similar to the transmitter application should be presented and all four LED s on the SMT351T SX50 should be on SMT911 User Manual SMT911 Page 17 of 38 Last Edited 01 06 2010 10 09 00 D3 MAXIM channel A good LO clock lock D4 MAXIM channel B good LO clock lock D5 DDR2 memory initialized successfully D6 Good clock lock from both AD9863 IC s to the FPGA PLL To step through a simple capture from the module press 1 to turn on the receiver Next press 5 to store a number of samples to the DDR2 memory of the FPGA base module and finally 6 to read the memory from the base module into a set of files in C SMT911 Data Received Data called RxA Llog RxA_Q log RxB_I log and RxB Q log The number of samples to be stored to file is changeable at the top of the header file in the DSP task as define DATALENGTH 30 1024 Keep in mind if more samples are attempted to be written to file than is stored in memory the server will halt and the application will need to be re
12. 911 cards are easily combined to build an arbitrary size 2m x 2n MIMO system with coherent LO phase All control signals data bits and the SPI bus are routed through a 120 pin OSH data connector providing for flexible application specific configuration and control during operation The SMT911 is designed to fit on and connect directly to an FPGA base module like the Sundance SMT351T or SMT368 The provided demo SMT911 Firmware Control Module permits simple and unrestricted access to all control registers from a user friendly C Language API Related Documents SiGe Se2545A23 Dual Band 802 11 Wireless LAN Front End MAX2828 2829 World Class Transceiver IC MAXIM AD9863 Analog Devices dual ADC DAC Sundance Local Bus SLB specification ftp2 sundance com TIM specification SMTIASFX Carrier with 4 Module sites SMT6048 Host side USB software interface to Sundance hardware SMT6002 Sundance Flash Programming Utility FPGA 1 1 Referenced Documents 2 Acronyms Abbreviations and Definitions 2 1 Acronyms and Abbreviations A list of acronyms etc http www sundance com web files static asp pagename acc 3 Functional Description The SMT911 is an advanced high quality MIMO transceiver card designed to cover all features of future high speed MIMO radio systems It is used in combination with Sundance base modules such as the SMT351T On the SMT911 transceiver card two single chip MIMO RF front ends SE2545A23 are applie
13. O 3 8 6 Jo 10 34 ADDAC Register 6 OX1F This register is used for DAC A offset and DAC A gain control of ADDAC A ADDAC A Register 6 Ox1F Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Defaut 0 0 0 0 Reconfigurable bits 15 0 Coarse Gain Control 00 output current scaling by 1 11 01 output current 14 0 scaling 10 and 11 no output current scaling 13 0 DACA Fine Gain 5 0 100000 Maximum positive gain adjustment 12 0 J 111111 Minimum positive gain adjustment 11 000000 default of no adjustment 10 A 000001 Minimum negative gain adjustment 011111 Maximum negative gain adjustment 0 DACA Offset 1 0 6 Jo 0 DACA Offset Direction 0 to negative diff pin 1 to positive diff pin 10 35 ADDAC A Register 7 0x20 This register is used for DAC B offset and its direction of ADDAC A ADDAC A Register 7 0x20 Byte 1 0 D15 D14 D13 D12 DIO D9 D8 D7 D6 05 D4 D3 DI DO Default 0 0 Reconfigurable bits 15 DAC Offset 1 0 14 O 8 0 DACB Offset Direction 0 to negative
14. O 13 4l Functional OVETVICW vvessivninnsnccanssantaseanacntccnessuinsantiecamesnaniavadanb scbesSinninnnndcamesaniticeaneosades 13 4 2 E ME 14 A Zack NETT 14 4 2 2 Reading and Writing Registers 14 4AL3 Register 15 DEMIO e 16 BS MEM EIE ETERNI mmm 17 LOS dec aT 17 5 19 7 E 19 BOUON VIW ae 20 6 PO 21 ETT 21 Physical PFODGPUGS nnana 24 Vni g e 24 24 10 APPEND dc 25 10 1 2 4GHz Frequency Plan and Divider Ratio Programming Words 25 10 2 5GHz Frequency Plan and Divider Ratio Programming Words 25 Miet T URO 26 10 4 Test Register 26 10 5 Function Register 0 OXO2 cccccccccccscsssssssssesseseneeseesesenenceccocscccscssssseeeeeeeesesenensesss 26 10 6 Function Register 1 0 03 26 10 7 Func on Register Au 27 10 8 MAXIM A Register 0 0x05
15. Reconfigurable bits Description 5 0 For faster Tx VGA gain setting only Bit5 BitO need to be programmed 0 Tx VGA Gain Control Bit5 maps to digital input pin B6 and maps to digital input pin 3 BI Bit5 BitO 000000 corresponds to minimum gain 10 18 MAXIM B Register 0 OxOF Standby Same settings as MAXIM A See corresponding register 10 19 MAXIM B Register 1 0x10 Integer Divider Ratio Same settings as MAXIM A See corresponding register 10 20 MAXIM B Register 2 Ox11 Fractional Divider Ratio Same settings as MAXIM A See corresponding register 10 21 MAXIM B Register 3 0x12 Band Select and PLL Same settings as MAXIM A See corresponding register 10 22 MAXIM B Register 4 0x13 Calibration Same settings as MAXIM A See corresponding register 10 23 MAXIM B Register 5 0x14 Low pass Filter Same settings as MAXIM A See corresponding register 10 24 MAXIM B Register 6 0x15 RX Control RSSI Same settings as MAXIM A See corresponding register 10 25 MAXIM B Register 7 0x16 TX Linearity Same settings as MAXIM A See corresponding register 10 26 MAXIM B Register 8 Ox17 RX Gain Same settings as MAXIM A See corresponding register SMT911 User Manual SMT911 Page 31 of 38 Last Edited 01 06 2010 10 09 00 10 27 MAXIM B Register 9 0x18 TX VGA Gain Same settings as MAXIM A See corresponding register 10 28 ADDAC Register 0 0x19 This register
16. Unit Module Number Document Issue Number Issue Date Original Author Unit Module Description Describes the demo and SMT911 operation SMT911 User Manual Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HP5 1 5 This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2009 Certificate Number FM 55022 Revision History Issue Changes Made Initials 1 0 Initial Release 15 Jan 10 CHG Table of Contents E Hae SEDE gORCRREROI LI 6 1 Related Documents 7 Ll Referenced DOCUMEN S uana Gam lana aa nit eur Fera 2 Acronyms Abbreviations and 8 Zl JXCPODVIBS alid ND O FE VIAL ONS 8 3 Fancuonal eB 9 sr ee eee 10 oL DESC DUON 10 3 2 Block DiaQram ccccccsssssssssesseeeeeeeeeeeeeeeeeseesesesssssssenaeeeseseeeeeseseseeeesesesesssssasnenseseeeess 10 5 2 Module Description eee en 11 UF Od centies ed dc EE ns TUNE 11 SP ARNPic 11 3 3 3 Antenna 12 4 FDA
17. X2829 AD9863 SLB Data Connector RSSI ADC AD7476 Low noise power supplies SLB Power Connector 3 3 Module Description 3 3 1 Clock Distribution There are two MMCX connector clock inputs for the SMT911 Clock A provides a 40MHz clock input for the MAXIM transceiver IC s Clock B is the input for both CLKINI1 and CLKIN 2 of ADC DAC A and ADC DAC B Clock distribution is achieved by two CDCV304 clock buffer drivers Because the clock inputs to both pins CLKINI and CLKIN2 of the ADC DAC s are shared the clock provided here cannot exceed 50MHz the maximum speed of the internal ADC s if switching from TX to RX is the ultimate goal To achieve higher frequencies with the DAC s the ADC DAC s internal PLL circuitry must be implemented to multiply and output the clock onto IFACE2 This is programmable via SPI up to 200MHz For ease of use a high quality 40MHz crystal has been placed on the mezzanine to provide clocking for either both MAXIM transceivers both ADC DAC s or all four IC s These configurations are selectable via jumpers 1 and 2 Clock Source Both use XTAL Both use External XTAL CLKA External CLKB External CLKA XTAL CLKB on The clock source is driven by two jumper controlled multi function gates that drive two CDCV304 clock buffers The jumper marked CLKA will select the source clock for the MAXIM chip With no jumper the defaulted clock source is the onboard 40MHz crystal With the jumper the external CLK6 jac
18. configurable bits Transmitter I O Calibration LO Leakage and Sideband Detector Gain Control Bits 00 8 dB 01 18 dB 10 24 dB 11 34 dB 1 0 TX Calibration Mode Disabled 1 TX Calibration Mode Enabled 0 0 RX Calibration Mode Disabled 1 RX Calibration Mode Enabled 10 13 MAXIM A Register 5 Low pass Filter This register allows the adjustment of the RX and TX low pass filter corner frequencies MAXIM A Register 5 Byte 1 0 D15 D14 D13 D12 DIO D9 D7 D6 D5 D3 DI DO Default 0 0 0 Reconfigurable bits 11 RSSI High Bandwidth Enable 0 2 MHz 1 6MHz 6 0 TX LPF Corner Frequency Coarse Adjustment 00 undefined 01 12MHz nominal 5 0 mode 10 18MHz turbo mode 1 11 24MHz turbo mode 2 4 O RX LPF Corner Frequency Coarse Adjustment 00 7 5MHz 01 9 5MHz nominal mode 10 14 MHz turbo mode 1 11 18MHz turbo mode 2 doc 1 RX LPF Corner Frequency Fine Adjustment Relative to the Course Setting 9 0 000 9096 001 9596 010 10096 011 10596 100 110 SMT911 User Manual SMT911 Page 29 of 38 Last Edited 01 06 2010 10 09 00 10 14 MAXIM A Register 6 OxOB RX Con
19. d containing nearly all circuitry required between the transceiver and the antenna Two transceiver chips of type MAXIM MAX2829 are used to up and down convert signals between the WLAN carrier bands and the base band The MAX2829 is specially designed for MIMO Smart Antenna application and the IEEE 802 11a g standard In order to fulfill the requirements of more simple and clever MIMO solutions the SMT911 transceiver card is equipped with two built in ADC DAC chips from Analog Devices AD9863 Each of the transceiver MAXIM chips is served by one AD9863 The AD9863 integrates dual 12 bit ADCs and dual 12 bit DACs The dual DACs convert the digital base band I Q signals to analog signals when the SMT911 card acts as a transmitter When the SMT911 card acts as receiver the dual ADCs convert the analog base band I Q signals into a digital format for the FPGA base board Two additional ADC s AD7476 are provided to enable conversion of the Receive Signal Strength Information RSSI from the MAXIM transceivers All control pins of the mentioned ICs above are routed through to the base module via the QSH connector The firmware on the base module offers the user flexibility to specify control signals and control register settings More details about the firmware are explained in the Firmware implementation section The SMT911 card has two external reference clock inputs These external clock inputs provide the reference for generating the sampling clock
20. ded The pins are grouped in banks A B C with the pin out specified in the following table For further descriptions of the pins and their function please consult the datasheet 6 Upper data pin 5 N 5 5 7 1 ADO A IFACE2 Cong ADO A SHDN Shutdown Maxim SER Serial clk Maxim ENA RX Enabel Maxim MAX A SER DIN Serial DIN Maxim A MAX A RXHP RXHP Maxim A NwComeded o 78 Norconnecea NwComeded T Dru Upper Upper daa pin 5 masua Upper dain Upper data pin massa o Lower data pin masi ower os apres Lower ata pin SMT911 User Manual SMT911 Page 22 of 38 Last Edited 01 06 2010 10 09 00 109 ADO B IFACEI IFACEI ADO B TXDWN TXDWN ADO B 111 ADQ_B_RXDWN RXDWN ADO B SER CS Serial CS Maxim B 113 IFACE3 Clock B MAX B TX ENA TX enable Maxim B ADO B IFACE2 Conf I O ADO B SHDN Shutdown Maxim MAX B SER Serial clock Maxim B RX enable Maxim MAX B SER DIN Serial DIN Maxim B 120 RXHP 7 Physical Properties Dimensions Weight Supply Voltages Supply Current 8 Safety This module presents no hazard
21. diff pin 1 to positive diff pin 7 O 1 DAC B Offset 9 2 6 5 0 4 3 o EN NENNEN 010 10 36 ADDAC Register 8 0 21 This register is used for DAC B offset gain control fine gain and gain of ADDAC A ADDAC A Register 8 0x21 se THO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO SMT911 User Manual SMT911 Page 34 of 38 Last Edited 01 06 2010 10 09 00 Defaut 2002 2 124 24 11 0 0 0 10 Reconfigurable bits TxPGA Gain 7 0 is register control for the Tx programmable gain amplifier The TxPGA provides a 20 dB continuous gain range with 0 1 dB steps linear in dB simultaneously to both Tx channels Default is 0000 0000 Minimum gain scaling 20 dB 1111 1111 Maximum gain scaling OdB DAC B Coarse Gain Control 00 output current scaling by 1 11 01 output current scaling by 5 10 and 11 no output current scaling 5 0 100000 Maximum positive gain adjustment 111111 Minimum positive gain adjustment 000000 default of no adjustment 000001 Minimum negative gain adjustment 011111 Maximum negative gain adjustment 10 37 ADDAC A Register 9 0x22 This register is used for other settings of Tx Path and I O configuration of ADDAC ADDAC A Register 9 0x22 15 0 Tx Twos Complement 0 straig
22. ed to update the detected RSSI values RSSI Update Register 0x32 Byte 1 0 015 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 O o O Reconfigurable bits a Jo 0 not updated 1 update RSSI Power Detect of Channel B 0 not updated 1 update RSSI Power Detect of Channel A 10 54 RSSI Register A 0x33 This read only register retrieves the RSSI value from channel A Channel A RSSI Register 0x33 Byte 1 0 D15 D14 D13 D12 DIO D7 D5 D3 D1 DO Defaut O 0 O 0 A 11 0 SMT911 User Manual SMT911 Page 37 of 38 Last Edited 01 06 2010 10 09 00 10 55 RSSI Register B 0x34 This read only register retrieves the RSSI value from channel B Channel B RSSI Register 0x34 Peyr TE als TUNE EHE se 0001 Defaut
23. fer in RX mode 4 2 Control Registers These registers control the complete functionality of the SMT911 transceiver mezzanine They are set up via the Comport 3 of the base module 4 2 1 Control Packet Structure The data passed to the FPGA over the Comports must conform to a certain packet structure Only after a valid packet is accepted and an update command sent will the specified settings be applied The packet structure is illustrated in the following table Packet structure for writing Byte 0 Ox10 Byte Content EL AN E AN NE RN EN Packet structure for reading Byte 0 0x20 Byte Content NUN AN o Byte of a packet must 10 for writing register or 0x20 for reading register This byte indicates the start of a packet and is required to synchronize communication Byte 1 denotes the register address to be accessed Byte 2 is the upper 8 bits of the data to the written or read and Byte 3 is the lower 8 bits of the data to be written or read creating 16 bit data words 4 2 2 Reading and Writing Registers Control packets are sent to the base module over Comport 3 This Comport is a 32 bit bi directional interface so all four control bytes are written and read as one word SMT911 User Manual SMT911 Page 14 of 38 Last Edited 01 06 2010 10 09 00 Packet Structure SMT911 4 2 3 Register Map Greater detail on each register can be fo
24. ht binary 1 twos complement 14 Rx Twos Complement 0 straight binary 1 twos complement TxPGA Slave Enable 0 immediately after register updated 1 synchronized with falling edge of a signal applied to the TxPwrDwn 4 TxPGA Fast Update 0 normal mode 1 fast mode 10 38 ADDAC Register 10 0x23 This register is used for I O configuration and clock configuration of ADDAC A ADDAC A Register 10 0x23 Byte 1 0 D15 D14 D13 D12 D11 DIO D9 D8 D7 D6 D5 D4 D3 D2 DI DO Default 0 0 Reconfigurable bits 15 0 PLL Bypass 0 PLL remains active 1 PLL bypassed 13 ADC Clock Div 0 no division 1 divides the clock by 2 12 0 Alt timing mode 0 normal timing operation 1 alternative operation mode 11 PLL Divs 0 no division 1 output of PLL divided by 5 10 0 PLL multiplication factor 000 1 001 2x 010 4 011 8x 100 16x 101 111 not used SMT911 User Manual SMT911 Page 35 of 38 Last Edited 01 06 2010 10 09 00 5 0 BDigLoop On 0 off 1 on on only in full duplex mode 0 SpiFDnHD 0 HD mode 1 FD mode 4 SpiTxnRx for toggling Tx amp Rx in HD mode
25. is used for general setting and clock mode of ADDAC A ADDAC A Register 0 0x19 Byte LODS D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 0 1 Reconfigurable bits 15 0 Clock Mode setting 000 standard FD HD10 HD20 modes 1 4 7 001 Optional FD 14 0 timing mode 2 010 not used 011 Optional HD20 timing mode 5 100 not used 101 Optional HD10 timing mode 8 110 not used 111 Clone Mode mode 10 13 19 10 0 Enable the IFACE2 port to be an output clock 8 Inv the output clock on IFACE3 OO SDIO pin 0 uni directional 1 bidirectional IE ORNA SPI Mode 0 MSB 1 LSB 5 0 Soft Reset 0 not reset 1 reset register to default value 10 29 ADDAC A Register 1 OX1A This register is used to set Power Down mode of ADDAC A ADDAC A Register 1 Ox1A Byte 1 0 D15 D14 D13 D12 D11 DIO D9 D8 D7 D6 05 D3 D2 DI DO Default 0 0 Reconfigurable bits 15 Analog Power Down 0 active 1 Power down 14 0 Rx_A DC Bias Analog Power Down 0 active 1 Power down 1 Output Disconmeck 0 connect disconnect 10 30 ADDAC Regi
26. k J6 is then the chosen input for the MAXIM clock The same arrangement exists for CLKB the clock source for the ADDAC chips If the jumper is attached an external clock source J3 is expected otherwise the crystal will output 40MHz clock to pins CLKINI and CLKIN2 of the ADDAC chips The external clock jacks are AC coupled and so do not require any DC offset to drive this logic The clock provided to the MAXIM chip if external must be 40MHz from a quality stable source The clock provided to the ADC DAC chips must be a quality clean source and not exceed 50MHz if in a switching TX RX configuration as this source clock feeds the internal ADC and DAC 3 3 2 JTAG A standard Xilinx parallel JTAG header is supplied on the mezzanine to provide access to the base modules JTAG chain SMT911 User Manual SMT911 Page 11 of 38 Last Edited 01 06 2010 10 09 00 3 3 3 Antenna Connectors Four SMA antenna jacks are connected directly to the output of two SiGe RF frontend IC s Each channel shares both band A and band G on the same TX connector and both bands on the same RX connector The antennas should be connected as described below Channel A TX Channel A RX Channel B TX Channel B RX 4 Firmware The demo firmware provided will help you get started in using the SMT911 for whatever custom applications are required It is not meant to demonstrate the hardware in its full capabilities but to provide an example use fo
27. ltra low power control of Rx path of ADDAC A in combination with asserting LO PWR pin to reduce power consumption ADDAC A Register 4 Ox1D Byte 1 0 D15 D14 D12 D11 DIO D9 D7 D6 D5 D3 D2 DI DO Defaut O0 0 0 0 0 0 0 0 Reconfigurable bits 14 J RxUltralow PowerControl 0 normal 1 set to Ultralow 13 Rx Ultralow PowerControl 0 normal 1 set to Ultralow 12 0 RxUltralow PowerControl 0 normal 1 set to Ultralow RxUltralow PowerControl 0 normal 1 set to Ultralow 12 0 RxUltralow PowerControl 0 normal 1 set to Ultralow 10 33 ADDAC A Register 5 This register is used to set Ultra low power control of Rx path and DAC A Offset of ADDAC A ADDAC A Register 5 Ox1E Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Default 0 0 O Reconfigurable bits a ki DAC A Offset 9 2 SMT911 User Manual SMT911 Page 33 of 38 Last Edited 01 06 2010 10 09 00 Rx Ultralow PowerControl 0 normal 1 set to Ultralow Rx Ultralow PowerControl 0 normal 1 set to Ultralow Rx Ultralow PowerControl 0 normal 1 set to Ultralow 10
28. of the SMT911 either active TX RX or standby Function Register 1 0x03 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 0 Reconfigurable bits SMT911 User Manual SMT911 Page 26 of 38 Last Edited 01 06 2010 10 09 00 write to memory 0 Stop write to memory T read from memory 0 don t read from memory 000000 standby 111111 active actual working mode depends on register 0x02 10 7 Function Register 2 0x04 By default the gain control is applied through the parallel digital inputs of the MAXIM chips This register is used to set these digital inputs Function Register 2 0x04 Byte 1 0 D15 D14 D13 D12 D11 DIO D7 D5 D2 DI DO Defaut 0 0 Reconfigurable bits 13 Bit 13 Bit 7 are digital gain control of MAXIM B 12 0 As Receiver B13 B12 are used for Rx LNA gain control 00 amp 01 minimum 10 medium 11 maximum B11 B7 are used for gain control 00000 0 dB minimum 11111 62 dB maximum As Transmitter B13 is not used B12 B7 is used for Tx gain control 000000 0 dB minimum 111111 30 dB maximum Bit6 BitO are digi
29. r 7 2 Same settings as ADDAC A See corresponding register 10 48 ADDAC B Register 8 0 20 Same settings as ADDAC A See corresponding register SMT911 User Manual SMT911 Page 36 of 38 Last Edited 01 06 2010 10 09 00 10 49 ADDAC B Register 9 2 Same settings as ADDAC A See corresponding register 10 50 ADDAC B Register 10 Ox2F Same settings as ADDAC A See corresponding register 10 51 ADDAC B Register 11 0x30 Same settings as ADDAC A See corresponding register 10 52 Update Register 0x31 The Update bit activates the serial interface SPI to pass registers previously written in the FPGA to the corresponding device MAXIM A and B and ADDAC A and D Update Register 0x31 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 0 j0 j 0 0 0 0 0 0 0 1 11 1 1 Reading back this register returns the Firmware version Update Register 0x31 Byte 1 0 D15 D14 D13 D12 DIO D7 D5 D2 DI DO Defaut 0 0 0 O Firmware Version Reconfigurable bits 3 1 J ADDAC B Update 0 not updated 1 updated 2 1 ADDAC A Update 0 not updated 1 updated 1 1 MAXIM B Update 0 not updated 1 updated 0 1 MAXIM A Update 0 not updated 1 updated 10 53 Update RSSI Register 0x32 This register is us
30. r the device and an example setup for configuration and control It was developed using 3L s Diamond development IDE for multiprocessor systems TX c RX c SMT control pene aM mem fsm j WO IE E MAXIM A MAXIM B ADDAC A ADDAC B RSSI ADC A DSP RSSI ADC B U L ADDAC A RSL 250 500Mb s U L ADDAC B DDR2 Ram bank A 4 1 Functional Overview SMT_control is an NGC block for receiving instructions from a Sundance DSP module and passing on these control words to the SMT911 board Some modules which are integrated in this block are e Control Comport receive instruction words and send back register contents to DSP Switching Controller run switching TX RX Standby etc of SMT911 board SPI send SPI signals to every corresponding chip on the SMT911 board e RSSI ADC convert the RSSI and Power Detection information into register words SMT data is a block for data transfer between the ADDAC data pins and a Sundance DSP module through an RSL interface Using this RSL link a sustained streaming speed of 250MB s is possible or burst transfers of 500MB s not taking overhead into consideration It also receives direct control words from the DSP module by getting the forwarded control worlds from the SMT control module This block is supported by a DDR2 RAM interface available on the SMT351T board for continuous playback in TX mode or as a buf
31. started he user is then free to analyze the data with their preferred application or the provided MATLAB script Test RX m can then be used to view the captured waveforms To adjust the gain monitor RSSI or select a different carrier frequency simply choose the corresponding menu option and follow the directions as presented on screen To quit the application press 9 5 Footprint 5 1 Top View External clock inputs and selection jumpers ADC DAC AD9863 Clock buffers IN CAKA oe ee mm jm E IN ELKB m mm T C i E NE HEN Ries Nus cut EK gt gt z Fan power connectors 5V ow noise linear FPGA JTAG RF front end SE2545 Transceiver MAX2829 TET Antenna jacks 5 2 Bottom View eo eo eo eo eo eo ee 6 Pinout 6 1 SLB Interface The SLB carries all LVTTL signals from the TIM base module to the devices on the SMT911 mezzanine The transceiver card is equipped with the 120 pin male connector with the Samtec Part Number QSH 060 01 F D DP A The corresponding female connector QTH 060 01 F D DP A is located on the base module Bank A Bank B Bank C All signals routed by this connector are single en
32. ster 2 0x1B This register is used to set Power Down of ADDAC A Lage TE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Defaut 0 o Reconfigurable bits SMT911 User Manual SMT911 Page 32 of 38 Last Edited 01 06 2010 10 09 00 15 0 Rx Analog Bias Power Down 0 active 1 Power Down 14 RxRefPower Down 0 active 1 Power Down 13 0 DiffRef Power Down 0 active 1 Power Down 12 0 VREE Power Down 0 active 1 Power Down 0 Analog Power Down 0 active 1 Power down 6 Rx_B DC Bias Power Down 0 active 1 Power down 10 31 ADDAC Register 3 Ox1C This register is used to set Rx Path of ADDAC A ADDAC A Register 3 Ox1C Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D3 D2 DI DO Defaut 0 0 0 0 Reconfigurable bits 13 Rx B 25 complement 0 straight binary 1 2 s complement 12 Clk Duty 0 disable 1 enable 0 Rx A 2 s complement 0 straight binary 1 2 s complement Rx A Clk Duty 0 disable 1 enable 10 32 ADDAC A Register 4 OXID This register is used to set U
33. tal gain control for MAXIM A As Receiver B6 B5 are used for Rx LNA gain control 00 amp 01 minimum 10 medium 11 maximum B4 BO are used for Rx VGA gain control 00000 0 dB minimum 11111 62 dB maximum a As Transmitter a lo 1 B6 is not used B5 BO is used for Tx VGA gain control 000000 0 dB minimum 111111 30 0 o dB maximum 10 8 MAXIM A Register 0 0x05 Standby Various internal blocks of the MAXIM chip can be turned on or off by setting this standby register Setting bit 13 to 1 turns the clock on while setting it to O turns the block off MAXIM A Register 0 0x05 Byte1 0 D15 D14 D13 D12 D11 D10 D9 D7 D6 D5 D3 D2 D1 DO 0 o 1 o Reconfigurable bits 13 J MIMO mode 0 normal operation 1 MIMO applications 0 Voltage Reference 10 0 Bias DAC in TX Mode SMT911 User Manual SMT911 Page 27 of 38 Last Edited 01 06 2010 10 09 00 10 9 MAXIM A Register 1 0x06 Integer Divider Ration This register contains the integer portion of the divider ratio of the synthesizer This register in conjunction with the fractional divider ratio register permits selection of a precise frequency Please refer to the appendix tables MAXIM A Register 1 0x06 Byte 1 0 D15 D14 D13 D12 D11 D10 D9 D7
34. to the user when in normal use 9 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot 10 Appendix 10 1 2 4GHz Frequency Plan and Divider Ratio Programming Words Divider Ratio 2412 1608000 1010000 2427 1618000 1010001 2442 1628000 100000 o 00 2457 163800 1 1010001 o 00 2472 164800 101000100 00 10 2 5GHz Frequency Plan and Divider Ratio Programming Words fRF fRF x 4 3 20MHz Integer Divider Ratio Fractional Divider Ratio Divider Ratio MHZ Reg 0x06 B7 BO Reg 0x07 B13 BO HEX Reg 0x06 B13 B12 1110 0000 5700 mooo 0 sz4s 2208 mooo 333 SMT911 User Manual SMT911 Page 25 of 38 Last Edited 01 06 2010 10 09 00 5805 232 2 1110 1000 0CCC 10 3 Reset Register 0x00 This register resets some of the components In order to save on power the components will remain in reset until the register is cleared Reset Register 0x00 D15 D14
35. trol RSSI This register is used to adjust the RX section and RSSI output MAXIM A Register 6 OxOB TE TONS TUNE ID J TEE 58 TQ Defaut 0 o o 0 1 1 Reconfigurable bits Enable Rx VGA Gain ae Serially O Rx VGA gain programmed with external digital inputs B7 B1 1 Rx VGA gain programmed with serial data bits in the gister Do DO RSSI Operating C RSSI disabled if 0 and enabled if RXHP 1 RSSI enabled independent of RXHP RSSI Pin Function 0 outputs RSSI signal in Rx mode 1 outputs temperature sensor voltage in Rx Tx and standby modes 100Hz 1 30kHz 10 15 MAXIM Register 7 OxOC TX Linearity Gain This register allows the adjustment of the TX gain and linearity MAXIM A Register 7 Byte 1 0 D15 D14 D13 D12 D11 DIO D9 D8 D7 D6 D5 D4 D3 D2 DI DO Default 0 0 0 Reconfigurable bits 10 Enable Tx VGA Gain Programming Serially 0 Tx VGA gain programmed with external digital inputs B6 B1 1 Tx gain programmed with data bits in the Tx gain register 05 00 9 1 PA Driver linearity 00 50 current minimum linearity 01 63 current 8 0 10 78 current 11
36. und in the Appendix 0x18 MAXIM Ox33_ RSSI ChannelA 0x19 ADDAC A 0 RW 0x34 RSSI ChannelB ADDAC A Register 1 4 3 Running Demo Launching the demo application requires 3L s Diamond software suite to be installed at the very least the Server The demo is designed to be run using the SMT148 FX carrier board with an SMT362 on TIM site 1 and an SMT351T SX50 SMT911 on TIM site 4 The comport configuration for this SMT148 FX setup is the default anti clockwise The latest SMT6048 needs to be installed to connect to the SMT148 FX and the SMT6002 will be needed if the comport configuration of the carrier needs to be changed If default clockwise is instead loaded on the carrier then the SMT351T SX50 SMT911 can be alternately moved to TIM site 2 keeping the SMT362 in the same position only T4C3 is used The SMT911 Control ngc provides a ready to use interface for configuring the registers of the mezzanine and switching between various states This should not need any modification when developing custom tasks although new tasks or the Data task can be modified any number of ways to create custom hardware processing In the DSP task is an array called BlockofRegisters which has all the default register configuration settings loaded at start up Details on the registers and the structure for writing to specific fields can be fo
37. und in the appendix The datasheets for the AD9863 and the MAXIM 2829 will offer further detailed information on what each setting in these registers will do and the format for writing to these registers can be found in the header file for this task The applications depend on a couple folders being available so these must be set up first On C drive make a new folder called SMT911 Data and in this folder create a folder called Received Data The resulting path should be C SMT911 Data Received Data Take the provided SINE dat file and place it within the SMT911 Data folder This is the sample data file which the DSP will look for when loading the DDR memory for transmit For both demo s leave the jumpers off of the mezzanine to choose the onboard crystal as the clock source otherwise a larger system can be synchronized using an external clock Page 16 of 38 Last Edited 01 06 2010 10 09 00 4 3 1 Transmitter The data file used when the module is configured as a transmitter must be formatted so that each line provides a concatenated I O pair for the dual DAC s of each channel Each line will be read into the DSP and passed to the FPGA as straight unsigned binary with the first 12 bits corresponding to the value and the next 12 bits corresponding to the T value The following figure demonstrates this To load the module as a transmitter open a Diamond Server and launch SMT911 362 SX50T
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