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7220 Group USER`S MANUAL

1. Example Note Character code Write the character code 00 16 to 7F 16 1 A16 E to addresses 1000016 to 10FFF16 H Write the character code 80 16 to FF16 to addresses 11000 16 to 11FFF16 Hi B _ E m Character Character 1 Rome 2 Y Example 101A016 b7 be bs bs be b bo Example 109 016 b7 be bs bs be b bo AE H a 2 16 16 2 0416 109 0e 2 016 3 B 3 016 4 0 1 4 016 5 E ii 5 2016 6 11 6 0 6 7 115 7 016 8 2016 8 H 816 9 2016 9 816 EEHEHE x F816 4016 E F416 4016 F416 4016 D F416 E 0016 E 016 0016 F016 3 3 6 76 7220 Group User s Manual APPENDIX 6 11 Mask ROM ordering method GZZ SH09 72B lt 5680 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37220M3 XXXSP MITSUBISHI ELECTRIC Date Section head Supervisor signature signature Note Please fill in all items marked Company Submitted by Supervisor name Customer e e Issuance signature Date issued 1 Confirmation Specify the name of the product being ordered and the type of EPROMs submitted Three EPROMs are required for e
2. 2 jo o o o o 0 0 0016 1111111111110 10 0016 0016 0016 0016 7220 Group Users Manual 6 29 APPENDIX 6 7 Control registers 6 7 Control registers Port Pi Direction Register 67 b6 b5 64 63 62 b1 bO TEL ET Port Pi direction register Di 0 1 2 Addresses 00C 116 00C3 6 00 516 S ee mee unm Port Pi direction register 0 Port Pio input mode R 1 output mode 0 Port Pit input mode 1 Port Pi output mode 0 Port input mode Riw 1 Port output mode 0 Port Pis input mode R W 1 Port Pis output mode 0 input mode Riw 1 Port output mode 0 Port Pis input mode Riw 1 Port Pis output mode 0 Port Pie input mode Ri w 1 Port Pie output mode i 0 Port Piz input mode 1 Port output mode Addresses 00 116 00 316 00 516 Fig 6 7 1 Port Pi direction register Port P3 Direction Register 67 b6 b5 64 b3 b2 b1 00 Port direction register D3 Address 00C716 8 ee 1010 Port P3 direction register 0 Port P3o input mode R 1 P3o output mode i 0 Port P31 input mode 1 Port P31 output mode 0 Port P32 input mode R 1 P32 output mode Nothing is assigned These bits are write disable bits When these bits are read
3. 6 54 7220 Group User s Manual APPENDIX 6 9 Machine instruction table Addressing mode Function BVC Branches when the contents of overflow flag is Note 4 BVS Note 4 Clears the contents of the bit specified in the accumulator or memory to 0 Clears the contents of decimal mode flag to CLI 1 0 Clears the contents of interrupt disable flag to g CLT TO Clears the contents of index X mode flag to 0 Clears the contents overflow flag to 0 When T 0 Compares the contents of accumulator and A M memory When 1 Compares the contents of the memory speci M X M fied by the addressing mode with the contents of the address indicated by index register X Forms a one s complement of the contents of memory and stores it into memory Compares the contents of index register X and memory Compares the contents of index register Y and memory Decrements the contents of the accumulator or memory by 1 Decrements the contents of index register X by 1 Yom Decrements the contents of index register Y by _ 1 DIV 22 1 Divides the 16 bit data that is the contents of Note 5 22 M zz x 1 for high byte and the contents of M S 1 s comple M zz x for byte by the accumulator ment of
4. o i o 10XX016 10XX016 80016 _ NSS WN 10XXF16 10XXF 16 80016 Fig 4 5 11 Example of display character data storing form 7220 Group User s Manual 4 21 M37220M3 XXXSP FP 4 5 Functional description The character code used to specify a display character is determined based on the address in the CRT display ROM in which that character data is stored Assume that 1 character data is stored in addresses 10XX0 e to 10XXF e XX denotes 0016 to 7Fie and 10YYO e to 10YYF e YY denotes 80016 then the character code is XXe In other words a character code is constructed with the low order second and third digits hexadecimal notation of the 5 digit address 10000 e to 107FF e where that character dat
5. Fig 4 5 3 Memory map of SFR special function register 1 4 12 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description Area addresses E016 to FF 6 Address 2016 E116 E216 E316 E416 E516 E616 E716 E816 E916 16 16 16 016 EE16 EFi6 2016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 16 FC16 2016 FE16 FFi6 Register Horizontal position register HR Vertical position register 1 CV1 Vertical position register 2 CV2 Character size register CS Border selection register MD Color register 0 COO Color register 1 CO1 Color register 2 CO2 Color register 3 CO3 CRT control register CC CRT port control register CRTP CRT clock selection register CK A D control register 1 AD1 A D control register 2 AD2 Timer 1 TM1 Timer 2 TM2 Timer 3 Timer 4 4 Timer 12 mode register T12M Timer 34 mode register T34M PWMB register PWM5 nterrupt input polarity register RE Test register TEST CPU mode register CPUM nterrupt request register 1 IREQ1 nterrupt request register 2 IREQ2 nterrupt control register 1 ICON1 nterrupt control register 2 ICON2 Bit allocation gt Name 0 jJ Function bit No function bit Fix this bit to 0 do not write 1 Fix this bit to 1 do not write 0
6. 2 45 2 7 7 Connection example for serial I O transmit receive 2 46 2 7 8 Serial data transmit receive processing sequence 2 46 7220 Group User s Manual V List of figures Fig 2 8 1 Block diagram of multi masteer I C BUS 2 48 Fig 2 8 2 12 data shift register 2 49 Fig 2 8 3 C addtess register 5 ere ets eh eade Ae eua 2 50 Fig 2 8 4 clock control register 4 nennen nennen nennen 2 52 Fig 2 8 5 Connection port control by BSELO and BSEL1 2 53 Fig 2 8 6 control register ee ro teen rrt et Ia EP 2 54 Fig 2 8 7 Interrupt request signal generating timing 2 57 2 8 8 126 Status register eee dba eat ce Le 2 57 Fig 2 8 9 START condition generation timing 2 58 Fig 2 8 10 STOP condition generation timing 2 58 Fig 2 8 11 START condition STOP condition detect timing diagram 2 59 Fig 2 8 12 Address data communication format 2 60 Fig 2 9 1 A D comparator block 2 61 Fig 2 9 2 A D control register
7. 6 60 7220 Group User s Manual APPENDIX 6 9 Machine instruction table Addressing mode Details Stores the contents of accumulator in memory Stops the oscillator Stores the contents of index register X in memory Stores the contents of index register Y in memory Transfers the contents of the accumulator to in dex register X Transfers the contents of the accumulator to in dex register Y Tests whether the contents of memory are 0 not Transfers the contents of the stack pointer to in dex register X Transfers the contents of index register X to the BA Transfers the contents of index register X to the 2 1 stack pointer Transfers the contents of index register Y to the 98 2 1 accumulator Stops the internal clock 2 211 1 The number of cycles n is increased by 3 when T is 1 2 The number of cycles n is increased by 2 when T is 1 3 The number of cycles is increased by 1 when T is 1 4 The number of cycles n is increased by 2 when branching has occurred 5 N V and Z flags are invalid in decimal operation mode 7220 Group User s Manual 6 61 APPENDIX 6 9 Machine instruction table 6 62 Addressing mode Processor status register 2 lt 300 1 0
8. 8 54 8 8 A 8 x 10481691 5 YIS Xepu yun 8 v 10 8 8 10d 8 Jejunoo 4ejunoo ejeq 2050 1050 Ae dsip 1ndino 2 104 SSANO SSA 99A 19899 19599 1 0 NIX jndino 1 9 7220 Group User s Manual CHAPTER 2 FUNCTIONAL DESCRIPTION 2 1 Central processing unit 2 2 Access area 2 3 Memory assignment 2 4 Input Output pins 2 5 Interrupts 2 6 Timers 2 7 Serial 2 8 Multi master I C BUS interface 2 9 A D comparator 2 10 PWM 2 11 CRT display function 2 12 ROM correction function 2 13 Software runaway detect function 2 14 Low power dissipation mode 2 15 Reset 2 16 Clock generating circuit 2 17 Oscillation circuit FUNCTIONAL DESCRIPTION 2 1 Central processing unit 2 1 Central processing unit The CPU of the M37221M6 XXXSP FP has six main registers The program counter PC is a 16 bit register consists of PCL both of which are 8
9. 22 2 6 30 Fig 6 7 3 Port P5 direction register teen ete Per idee 6 31 Fig 6 7 4 Port output mode control register 6 31 Fig 6 7 5 PWM output control register 1 6 32 Fig 6 7 6 PWM output control register 2 6 32 Fig 6 7 PG shift register nct ng 6 33 Fig 6 7 8 address tnnt 6 33 Fig 6 7 9 FG stat s registerz ii ado eR e a Re etes 6 34 Fig 6 7 10 C control nennen tren 6 35 Fig 6 7 11 clock contorol register 6 36 Fig 6 7 12 Serial mode register eene eene enne nns 6 37 Fig 6 7 13 DA conversion register n only 37220 3 6 38 Fig 6 7 14 Horizontal position register 6 38 Fig 6 7 15 Vertical position register n 6 39 Fig 6 7 16 Character size 6 39 Fig 6 7 17 Border selection 6 40 Fig 6 7 18 Color register trennen rss 6 41 Fig 6 7 19 CRT control nnns nter enne nennen 6 42 Fig 6 7 20 CRT port control register dien aen eaae aaa aaa aa a a enne nnne nennen nnns 6 43 Fig 6 7 21 CRT
10. P21 SCL 1 Wait 6 us P21 SCL 0 BIT COUNTER lt BIT COUNTER 1 BIT COUNTER gt 8 Bit 0 of port P2 direction register input mode Wait 6 us P21 SCL 1 Wait 6 us P20 SDA 1 P21 SCL 0 RETURN Fig 5 5 6 Flowchart of data output processing routine 5 30 7220 Group User s Manual APPLICATION 5 5 Example of PC BUS control by software M37220M3 XXXSP FP 4 START condition processing routine START condition P20 SDA 1 Bit 0 of port P2 direction register output mode Wait 6 P21 SCL P20 SDA Wait 6 P21 SCL 0 C RETURN Fig 5 5 7 Flowchart of START condition processing routine 1 0 5 STOP condition processing routine STOP condition Bit 0 of port P2 direction register output mode g 1 P20 SDA P21 SCL Wait 6 us P20 SDA 1 RETURN Fig 5 5 8 Flowchart of STOP condition processing routine 6 Bus H processing routine Bit 0 of port P2 direction register output mode P21 SCL 1 Wait 6 us P20 SDA 1 RETURN Fig 5 5 9 Flowchart of bus H processing routine 7220 Group User s Manual 5 31 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 7 Data input processing routine RAM READDATA Data intput BIT COUNTER Bit 0 of port P2 di
11. 4 5 Functional description Area addresses C016 to DF 6 Bit allocation gt State immediately after reset gt 0 immediately after reset Function bit 1 immediately after reset No function bit Undefined immediately E after reset o Fix this bit to 0 do not write 1 1 Fix this bit to 1 do not write 0 Address Register Bit allocation ate immediately after reset B6 016 Port PO PO C116 Port PO direction register DO C216 Port P1 P1 C316 Port P1 direction register D1 C416 Port P2 P2 C516 Port P2 direction register D2 C616 Port P3 P3 C716 Port P3 direction register D3 C816 C916 1 Port P5 P5 1 Port P5 direction register 05 16 CD16 Port P3 output mode control register P3S CE 16 DA H register DA H CF16 DA L register DA L 0016 register PWMO 0116 PWM register PWM1 0215 PWMe register PWM2 0316 PWWMS register PWM3 0416 PWM4 register PWM4 0516 PWM output control register 1 PW PW7 0615 PWM output control register 2 PN _____ Pno 0716 0816 0916 1 0816 16 Serial mode register SM SM3 0016 Serial I O regsiter SIO DE16 DA1 conversion register DA14 DA13 12 0 11 DA10 16 DA2 conversion register DA24 DA23 DA22 DA21 DA20
12. 8 E2PROM sisseuo sng 9 uoneorddy 9 5 614 snouoJuou s pue 24v pue 35 6 80012 22 103599014 jeus 20100 1921 sisseuo SNg Ozl 5 45 7220 Group User s Manual APPLICATION t example Ion Circul 5 6 Applicat 5 6 2 Application circuit example 2 UBD euJejxe os YOO O eq GSO 104 eu 10 sisseuo sng uoN 9 5 614 m D SSANO SSA ino NIX UH OFCINAL E c punog 77 AAO NO LNO 894 COSLN 0 VOSLN NVO3S ONASA ONASH sseudieus 101 U09 JUL 1 1 2 101 U09 20109 Wd M37220M3 XXXSP FP a ndu snouoJuou AS ndu 54v LNO viva NI VLVG 9149913 ssed euueljuy EA v a
13. Contents Contents implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode M X Special page addressing mode Carry flag 5 Zero flag Interrupt disable flag Decimal mode flag Break flag X modified arithmetic mode flag M 00 ADL Overflow Negative flag Mp OP n ADL 7220 Group User s Manual Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high order bits of program counter 8 low order bits of program counter 8 high order bits of address 8 low order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by a
14. d 1 OVERVIEW 1 1 Performance overview 1 2 Pin configuration 1 3 Pin description 1 4 Functional block diagram OVERVIEW 1 1 Performance overview 1 1 Performance overview The 8 bit microcomputers M37221M4 XXXSP M37221M6 XXXSP FP M37221M8 XXXSP M37221MA XXXSP M37220M3 XXXSP FP have their simple instruction set the ROM RAM and I O addresses are placed on the same memory to enable easy programming Furthermore they have many additional functions for tuning system for TV PWM output 14 bit and 8 bit CRT display A D comparator resistance string method Software runaway detection Multi master I C BUS interface function ROM correction function And also they can allow low power dissipation by the use of CMOS processing The M37221M6 XXXSP FP is used as a general example in describing the functions of the above microcomputers unless otherwise noted 1 2 7220 Group User s Manual OVERVIEW 1 1 Performance overview The performance overview is shown in Table 1 1 1 M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP Table 1 1 1 Performance overview 1 Parameter Number of basic instructions Performance 71 Instruction execution time 0 5 us the minimum instruction execution time at 8 MHz oscillation frequency Clock frequency 8 MHz maximum Memory size M3722
15. 5 5 1 5 5 5 1 After executing the above if addressing mode is ABS PC AD If addressing mode is SP AD If addressing mode is ZP IND C M 00 ADL 00 AD 1 Jumps to the specified address After storing contents of program counter in Stack and jumps to the specified address When T 0 When 1 M X M Load accumulator with contents of memory Load memory indicated by index register X with contents of memory specified by the addres sing mode APPENDIX 6 9 Machine instruction table Addressing mode BIT ZP Load memory with immediate value the right by one bit The tow order bit of accumulator or memory is Stored in carry 7th bit is cleared M S A AXM zz X 5 5 1 Multiplies the accumulator with the contents of memory specified by the zero page X addres sing mode and stores the high byte of the result on the stack and the low byte in the accumu lator PC PC 1 ORA Note 1 When T 0 A AVM When T 1 M X M OO VM No operation Logical OR s the contents of memory and accumulator The result is stored in the accu mulator Logical OR s the contents of memory indi cated by index register X and
16. in high impedance state INT1 pin 2048 counts Timer 3 counter 4 counter INT1 interrupt request bit S p Oper Peripheral device ating stopping Operating Oper Stopping O Operating STP interrupt 2048 counts down by timer 3 instruction signal is input Supplying internal clock INT1 interrupt to CPU is started request occurs INT1 interrupt request is accepted Oscillation starts Timer 3 count starts Fig 2 14 2 Execution sequence example at return by occurrence of INTO interrupt request 2 92 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 14 Low power dissipation mode 2 14 2 Wait mode The wait mode is set by executing the WIT instruction In the wait mode only the internal clock stops with supplying f X continuously In this case there is no need to create a wait time by timers as in the case of return from the stop mode and operation is restarted immediately after return from the wait state When reset input or interrupt is accepted supply of the internal clock is immediately started and the device is returned from the wait state Because the clock is continuously supplied in the wait state return by an internal interrupt as a timer etc can also be used Table 2 14 2 State in wait mode Item State in wait mode Oscillation Operatin
17. Mitsubishi IC catalog name Mitsubishi IC catalog BRRRRRRRRRRBHRBRHRRRHRHRRH r Customer s Parts Number Note The fonts and size of characters are standard Mitsubishi type 4 Mitsubishi IC catalog name Notei The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi lot number Mitsubishi type 6 digit or 7 digit 3 Customer s Parts Number can be up to 11 char acters Only 0 9 2 2 amp eriods commas are usable TUE UU periods 4 the Mitsubishi logo is not required check the box below Mitsubishi logo is not required 81 Note1 If the Special Mark is to be printed indicate the desired layout of the mark in the left figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and Mask ROM number 3 digit are always marked 2 If the customer s trade mark logo must be used in the Special Mark check the box below Please submit a clean original of the logo For the new special character fonts a clean font origina ideally logo drawing must be sub mitted Special logo required 3 The standard Mitsubishi font is used for all char acters except for a logo 7220 Group User s Manual 6 81 MITSUBISHI SEMICONDUCTORS USER S MANUAL 7220 Group Jul First Edition 1997 Editioned by Committee of editing of Mit
18. 2 30 2 5 5 Interrupt control register 1 address OOFE 16 se 2 31 2 5 6 Interrupt control register 2 address 00 2 31 2 5 7 Interrupt input register address 91 2 32 2 5 8 CRT port control register address 00 2 32 2 5 9 Interrupt Control system iere Ede eX deor en 2 33 25 10 Interrupt vector table eiit tote E eet ttu te eter axes 2 33 2 6 1 Timer 1 timer 2 timer and timer 4 block diagram 2 34 2 6 2 Timer overflow timing nennen nnns nnne 2 35 2 6 3 Timer 12 mode register address 00 46 2 36 2 6 4 Timer 34 mode register address 00 5 2 37 2 6 5 Example of timer System aie Le ite ade 2 38 2 7 1 Serial block diagram 2 41 2 7 2 Serial mode register address 00 0 8 4 2 41 2 7 3 Serial input output common transfer mode block diagram 2 42 2 7 4 Serial register when receiving when SM5 07 2 43 2 7 5 Serial I O register when transmitting when SM5 O 2 44 2 7 6 Timing diagram of serial
19. 1 5 clock for display is supplied by connecting the following across the pins OSC1 and OSC2 ceramic resonator only for CRT display and a feedback resistor a quartz crystal oscillator only for CRT display and a feedback resistor Note Fix these bits to 0 EH Note It is necessary to connect other ceramic resonator or quartz crystal oscillator across the pins and Xour Fig 6 7 21 CRT clock selection register Address 00 016 6 44 7220 Group User s Manual APPENDIX 6 7 Control registers A D Control Register 1 67 b6 65 64 b2 61 00 A D control register 1 AD1 Address OOEE 16 o o ht o A D1 A D2 A D3 A D4 05 rA D6 Do not set ADMO ADM1 ADM2 0 0 0 0 1 1 1 1 gt Or Oe Oa cd Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Storage bit of comparison 0 Input voltage lt reference voltage Indeterminate W result ADM4 1 Input voltage gt reference voltage 5 Nothing is assigned These bits are write disable bits S When these bits are read out the values are 0 Fig 6 7 22 A D control register 1 Address 00 16 A D Control Register 2 b7 b6 b5 b4 b3 b2 bi A D control register 2 AD2 Address OOEF 16 D A converter set bits f ADCO ADC1 ADC2 1 128 ADC3 ADC4 ADC5 52 5 123 128Vcc 125 128Vcc
20. 2 7 5 Serial data receive method when an internal clock is selected 1 Initialization First set the serial mode register address 00DCie as follows Select the synchronous clock SM2 1 SM1 SMO Set P2o as pin SM3 71 Pin P2 Sour is not used when receiving serial data However since the serial I O port selection bit SM3 is also used for setting pin Sour port P2 is automatically set as pin Sour and loses its general purpose port function Select the serial input pin by the serial input pin selection bit SM6 When SM6 0 signal is input from pin P22 Sin when SM6 1 signal is input from pin P2i Sour When pin 22 is a input pin set the port P2 direction register to input mode 0 For pins and P2 Sovr the corresponding bits of the port P2 direction register are automatically set by setting the serial I O mode register 2 Receive enable state After the above setting have been made write FF e to the serial I O register address 00DD e serial I O counter is then set to 0716 during the write cycle and receive is enabled 3 Receive operation The data from the serial data input pins Souror Sw is received one bit at a time into the serial register in synchronization with rising edges of the transfer clock Receive operation is performed according to bit 5 SM5 of the serial mode register When SM5 is s
21. RW RW 7220 Group User s Manual 6 23 APPENDIX 6 6 SFR assignment 2 Page Register Area addresses 21716 to 21816 Bit allocation gt j Function bit No function bit 0 Fix this bit to 0 do not write 1 1 Fix this bit to 1 do not write 0 Address Register Bit allocation 21716 correction address 1 high order DHT ADH16 ADHISADHI4 21816 ROM correction address 1 low order ADL17 ADL16 ADL15 ADL14 ADL13 21916 ROM correction address 2 high order 22 21A16 ROM correction address 2 low order 21816 ROM correction enable register RCR Sa EE Tolol RCRIJRCRO Note Only M37221M8 XXXSP and M37221MA XXXSP have this area Fig 6 6 3 Memory map of 2 page register including internal state immediately after reset and access characteristics 3 only M37221M8 XXXSP and M37221MA XXXSP 6 24 7220 Group User s Manual APPENDIX 6 6 SFR assignment State immediately after reset gt 0 0 immediately after reset 1 1 immediately after reset RW Read enabled write enabled 2 Undefined immediately Read enabled write disabled after reset State immediately after reset Access characteristics 60 67 60 2 RW RW RW RW 7220 Group Users Manual 6 25 APPENDIX 6 6 SFR assignment
22. hexadecimal notation EPROM type indicate the type used 27C101 EPROM address 000016 Product name ASCII code 000 1 M37221M4 00016 ROM 16 bytes 1000016 107FFi6 1080016 10FFF e 1100016 117 2216 18006 Character ROM 1 6 6 1 Set FF e in the shaded area 2 Write the ASCII codes that indicates the product name of 37221 4 to addresses 000016 to 000 16 EPROM data check item Refer the EPROM data and check in the appropriate box Do you set FF ie in the shaded area 2 Yes Do you write the ASCII codes that indicates the product name of 37221 4 to addresses 000016 to 000F 16 Yes Character ROM 1 a Character ROM 2 a Character ROM 1 b 2 Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form 42P4B for M37221M4 XXXSP and attach to the mask ROM confirmation form 3 Comments 1 3 7220 Group User s Manual 6 65 APPENDIX 6 11 Mask ROM ordering method GZZ SH10 10B lt 59 0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M4 XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 16 to 000 16 store the product name and addresses 10000 16 to 1122 21
23. 2 0 0 2Vcc V INT1 INT2 INT3 Xin OSC1 Sin lou HIGH average output current Note 1 B OUT1 D A 1 mA 1 2 2 P30 P3 loi LOW average output current Note 2 B OUT1 D A POs 2 mA Pio P1s P17 2 2 3 P32 love LOW average output current Note 2 P1 P14 6 mA lous LOW average output current Note 2 _ 5 1 mA loa LOW average output current Note P24 P27 10 mA Oscillation frequency for CPU operation Note 5 7 9 8 0 81 MHz fcnr Oscillation frequency for CRT display Note 5 OSC1 5 0 8 0 MHz fhs1 Input frequency TIM2 100 kHz fhs2 Input frequency 1 MHz fhs3 Input frequency SCL1 SCL2 400 kHz Notes 1 The total current that flows out of the IC must be 20 mA max 2 The total input current to IC loL1 1012 1013 must 30 mA or less 3 The total average input current for ports P24 P27 to IC must be 20 mA or less 4 Connect 0 1 or more capacitor externally across the power source pins 55 so as to reduce power source noise Also connect 0 1 uF or more capacitor externally across the pins VCC CNVSS 5 Use a quartz crystal oscillator or a ceramic resonator for the CPU oscillation circuit 7220 Group User s Manual 3 3 ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics Electric characteristics Vcc 5 V 10 96 Vss 0 V 8 MHz Ta 10 C to
24. 00000101 2 Border output HR address 00 0 16 XXXXXXXX 2 Set a horizontal display start position CK address OOED 16 000000102 Set display clock Line counter 0 Enable CRT interrupt in synchronized F VSYNC lt with the next VSYNC Note This routine is not interrupt processing routine Fig 5 1 3 Flowchart of initialization processing routine 7220 Group User s Manual 5 3 APPLICATION 5 1 Example of multi line display 2 Vsync interrupt processing routine The Vsync interrupt processing routine consists of multi line display start processing and multi line display correction processing The correction processing corrects erroneous multi line display due to various influences 1 ICON2 Interrupt control registers 1 2 CC CRT control register CRTE Bit 4 of interrupt control register 1 Line counter Counter RAM for line counting CRT interrupt enable bit VSYNC VSYNC flag CRTR Bit 4 of interrupt request register 1 CV1 CV2 Vertical position registers 1 2 CRT interrupt request bit V V ICON2 Back up RAM for interrupt control registers 1 2 during V SYNC interrupt Accumulator Index register X Index register Y X modified operation mode flag T Decimal operation mode flag D V lt ICON1 Push contents during V SYNC interrupt V_ICON2 lt 2 Push ICON contents during V SYNC interrupt Setting for ICON1 address 00 1
25. Bit allocation State immediately after reset gt 0 immediately after reset 1 immediately after reset Undefined immediately after reset State immediately after reset b7 60 5 HR8 HR2 HR1 HRO 0016 CV15 CV14 CV13 CV12 CV11 CV10 CV25 CV24 CV23 CV22 CV21 CV20 CS21 CS20 CS11 CS10 MD20 MD10 coz 0016 0016 cot3 012 cot CO 3 ERE vee oo ADM4 ADC3 0016 0016 0016 0016 0016 0 010 7 0 0 0 0 0016 16 0716 16 0716 0 T12M4 12 3 12 2 T12M1 T12MO prefe re 0016 0016 4 0 0 0016 1 1 ev o 0 TM4R TM2R TM1R MSR 518 1 2 2 TM1E MSE 0 S1E 1T2E 1T1E Fig 4 5 4 Memory map of SFR special function register 2 7220 Group User s Manual 4 13 M37220M3 XXXSP FP 4 5 Functional description 4 5 3 Input Output pins Table 4 5 2 shows the difference of programmable ports between M37221M6 XXXSP FP and M37220M3 XXXSP FP Table 4 5 2 Difference of programmable ports between M37221M6 XXXSP FP and 37220 3 XXXSP FP Functions except port 0 M37
26. GZZ SH09 72B lt 56 0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37220M3 XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 000016 to 000 16 store the product name and addresses 10000 1610 10FFF store the character pattern If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form the ROM processing is disabled Write the data correctly 1 Inputting the name of the product with the ASCII code Address ASCII codes M37220M3 are listed on the right 000016 4D ic The addresses and data are in hexadecimal notation 000116 3 95446 000216 7 37 16 000316 2 2 32 16 000416 2 32 16 000516 0 30 46 000616 4 000716 3 33 16 2 Inputting the character ROM Address 000816 000916 000 16 000 16 000 16 000016 000 16 000F 16 o o o o o o o Input the character ROM data by dividing it into character ROM1 and character ROM2 For the character ROM data see the next page and on 2 3 6 78 7220 Group User s Manual GZZ SH09 72B 5680 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37220M3 XXXSP MITSUBISHI ELECTRIC The structure of character ROM divided of 12 X16 dots font
27. GZZ SH11 58B 72A0 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M8 XXXSP MITSUBISHI ELECTRIC The structure of character ROM divided of 12 X16 dots font Example Note Character code Write the character code 00 16 to 7 16 16 to addreses 10000 16 to 10FFF 16 EH NH Write the character code 80 16 to FF 6 BH HH to addreses 11000 16 to 11FFF 6 E E B m _ E B E Character Character y 1 ROM2 4 Example _ 101 0 bz be bs b4 bs be bi Example _ 109A0 6 bz be bs b4 bs be b bo Wi 16 16 101AF 6 2 Dis 109AF 6 2 F016 3 H 1 3 016 4 EH OA16 4 F016 5 1116 5 F016 6 1116 6 F016 7 iiis 7 Fie F016 8 2016 8 F816 9 2016 9 n F816 A tt 57 A 816 OM 4016 B E F416 c OM 4016 F416 4016 F416 E 0016 E 016 0016 F FO16 3 3 6 70 7220 Group User s Manual
28. Specify the vertical position by the vertical position register Specify the character size by the character size register Specify the horizontal position by the horizontal position register Write the display control bit to the designated block display flag of the CRT control register When this is done the CRT starts according to the input of the Vsvwc signal The CRT display circuit has an extended display mode This mode allows multi line more than 3 lines to be displayed on the screen by interrupting each time 1 line is displayed and rewriting data in the block which display is terminated by software Figure 2 11 2 shows the CRT display circuit block diagram Figure 2 11 3 shows the control register Table 2 11 1 Outline of CRT display function Dod Parameter Performance 015 Number of display 24 characters X 2 lines character Dot structure 12 dots X 16 dots Refer to Figure 2 11 1 256 kinds 3 kinds 1 screen 4 kinds maximum 7 kinds A character Possible multi line display Possible maximum 7 kinds Possible a character unit 1 screen 4 kinds maximum 7 kinds Kinds of character Kinds of character sizes Kind of colors Coloring unit Display extension Raster coloring Character background coloring Color Fig 2 11 1 Structure of CRT display character 7
29. gt Pass gate with the others PW PWM output control register 1 PN PWM output control register 2 Note The DA L register also functions as the low order 6 bits of the DA latch Fig 2 10 1 14 bit PWM DA block diagram 7220 Group User s Manual 2 63 FUNCTIONAL DESCRIPTION 2 10 PWM PWM timing generating circuit PWM register Address 000016 U 5 5 3 25 5 2 En Selection gate Connected to black side when U e xz 2 with the others PW PWM output control register 1 PN PWM output control register 2 00 Port direction register Fig 2 10 2 8 bit PWM block diagram 2 10 1 8 bit PWM registers addresses 0000 to 0004 and 00F616 DA registers addresses 00 and 00 6 Data transfer from the 8 bit PWM registers addresses 0000 to 00D416 and OOF6 e to the 8 bit PWM circuit is executed when writing data to the registers The output signal from the 8 bit PWM output pin corresponds to the contents of this register Also data transfer from the DA registers addresses O0CE e and 00 1 to the 14 bit PWM circuit is executed when writing data to the DA L register address OOCF e The output signal from the D A output pin corresponds to the contents of the DA latch Reading from the DA register address 00 means the DA latch contents Therefore it is possible
30. 3 OUT2 output polarity 0 Positive polarity Switch bit OUT2 1 Negative polarity See note 4 OUT1 output polarity o Positive polarity switch bit OUT1 Negative polarity 5 signal output switch bit x R signal output 5 MUTE signal output G signal output switch bit 0 G signal output R iW OP6 1 MUTE signal output i 7 signal output switch bit 0 B signal output 7 1 signal output Note M37220M3 XXXSP FP Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 OUT output polarity Positive polarity R W Switch bit OUT Negative polarity Fig 6 7 20 CRT port control register Address 00 16 7220 Group User s Manual 6 43 APPENDIX 6 7 Control registers CRT Clock Selection Register b7 b6 b5 64 b3 b2 61 00 CRT clock selection register Address 00ED16 BIEN iis 0 1 CRT clock pes selection bits The clock for display is supplied by connecting RC CK0 CK1 or LC across the pins OSC1 and OSC2 1 Since the main clock is used as the clock for CRT oscillation display the oscillation frequency is limited frequency Because of this the character size in width horizontal direction is also limited In this case pins OSC1 and OSC2 also used CRT oscillation as input ports P33 and P34 respectively frequency
31. 3 2 STA RRF STY STA STX BBS SEB STY STA STX SEB won 8 era fina z van m m 0 ae is es es em STA BBC STY STA STX BEC STA CLB STA CLB wos s s A p an er 1010 LDY LDA LDX BBS LDY LDA LDX BBS TAY LDA TAX SEB LDY LDA LDX SEB IMM IND X IMM 5A ZP ZP ZP 5 ZP IMM ABS ABS ABS 5 7 LDA JMP 10 LDA LDX LDA CLB LDY LDA LDX CLB CPY BBS CPY DEC BBS CMP SEB CPY CMP DEC SEB ton r ae aw ar 1101 DEC BBC CLD CMP CLB CMP DEC CLB IND Y 6 A ZP X 2 6 2 ABS Y 6 A 5 6 7 1110 SBC INC BBS SBC SEB CPX SBC INC SEB IND X ZP ZP ZP 72 ABS ABS ABS 7ZP 1111 SBC BBC SBC INC BBC SBC CLB SBC INC CLB IND Y ZP X ZP X 7 2 5 5 5 7 ZP 7220 Group User s Manual 6 63 APPENDIX 6 11 Mask ROM ordering method 6 11 Mask ROM ordering method When placing an order please submit the information described below M37221M4 XXXSP Mask ROM Ordering Confirmation Form 1 set Please use the pages P6 65 to P6 67 M27221M8 XXXSP Mask ROM Ordering Confirmation Form 1 set Please use the pages P6 68 t
32. APPENDIX 6 11 Mask ROM ordering method GZZ SH09 46B lt 52C0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M6 XXXSP FP MITSUBISHI ELECTRIC Date Section head Supervisor signature signature Note Please fill in all items marked Submitted by Supervisor Company name Customer ste Issuance signature Date issued 1 Confirmation Specify the name of the product being ordered and the type of EPROMs submitted Three EPROMs are required for each pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM NER NU hexadecimal notation EPROM type indicate the type used 27C101 EPROM address 000016 Product name ASCII code 000 1 M37221M6 00016 16 ROM 24 bytes 1000016 107FF 6 1080016 10FFF e 1100016 117FF 6 11000 Character ROM 1 6 1FFFF e 1 16 in the shaded area 2 Write the ASCII codes that indicates the product name of M37221M6 to addresses 000016 000 1 EPROM data check item Refer the EPROM data and check in the appropriate
33. C416 Port P2 P2 2 51 Port P2 direction register D2 0016 C616 C716 Port P3 P3 Port P3 direction register D3 C816 C916 16 16 Port P5 P5 Port P5 direction register D5 16 CD16 16 16 Port P3 output mode control register P3S DA H register DA H DA L register DA L 0 0 Psos 0016 0116 0216 0316 0416 0516 0616 0716 PWMO register PWMO PWM1 register PWM1 2 register PWM2 PWMsS register PWM3 PWM4 register PWM4 PWM output control register 1 PW PWM output control register 2 PN 2 data shift register SO D6 PW4 PN4 D4 PW3 PW2 PW1 PN2 05 03 02 01 00 0816 0916 2 C address register 500 2 C status register S1 SAD5 TRX SAD4 BB SAD3 PIN SAD2 SAD1 SADO AL AAS ADO LRB 16 16 BSELO ACK BIT 2 C control register 510 2 C clock control register 52 10 BIT FAST MODE ALS CCR4 ESO 2 BC1 BCO CCR3 CCR2 CCR1 CCRO DCt1e Serial mode register SM SM6 SM5 SM3 SM2 SM1 SMO 0016 DE16 DF 6 Serial register SIO 0016 0016 Fig 2 3 3 Memory map of SFR special function register 1 7220 Group User s Manual 2 13 FUNCTIONAL DESCRIPTION 2 3 Memory assignment Area addresses E016 to FF 6 Bit allocation gt S
34. Horizontal position register Address 00 516 Border selection register Display control circuit RAM for display 9 bits X 20 characters X ROM for display 2 lines 712 bits X 16 dots X 128 characters Addresses 00 6 16 to 00 916 Color registers Shift register 12 bits Address 00EC 16 CRT port control register Fig 4 5 10 CRT display circuit block diagram 4 20 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description 1 Memory for display There 2 types of display memory CRT display ROM addresses 1000016 to 10FFFis and CRT display RAM addresses 060016 to 06B3 e Each type of display memory is described below CRT display ROM addresses 1000016 to 10FFF e CRT display ROM has a capacity of 4 K bytes Since 32 bytes are required for 1 character data the ROM can stores up to 128 kinds of characters CRT display ROM is broadly divided into 2 areas The vertical 16 dots X horizontal left side 8 dots data of display characters are stored in addresses 10000 e to 107FF e the vertical 16 dots X horizontal right side 4 dots data of display characters are stored in addresses 1080016 to 10FFF e refer to Figure 4 5 11 Note however that the high order 4 bits of the data to be written to addresses 10800 to 10FFF e must be set to 1 by writing data FX e
35. OSC2 are also used CRT oscillation f XiN 1 5 The clock for display is supplied by connecting the following across the pins OSC1 and OSC2 a ceramic resonator only for CRT display and a feedback resistor a quartz crystal oscillator only for CRT display and a feedback resistor Note Fix these bits to 0 EM Note It is necessary to connect other ceramic resonator or quartz crystal oscillator across the pins and Xour as input ports P33 and P34 respectively frequency Fig 2 11 19 CRT clock selection register 2 88 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 12 ROM correction function 2 12 ROM correction function Only the M37221M8 XXXSP and the M37221MA XXXSP have this function This can correct ROM program data in ROM Up to 2 addresses 2 blocks can be corrected a program for correction is stored in the ROM correction memory in RAM The ROM memory for correction is 32 bytes X 2 blocks Block 1 addresses 02 016 to 020 1 Block 2 addresses 02 016 to O2FF e Set an address of the ROM data to be corrected into the ROM correction address register When the value of the counter matches the ROM data address in the ROM correction address the main program branches to the correction program stored in the ROM correction memory To return from the correction program to the main program the op code and operand of the JMP instruction total of 3 bytes are necessary at the end of the correct
36. SFR Area addresses C016 to DF 6 Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 16 CD16 16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Fig 6 6 4 SFR assignment including internal state immediately after reset and access characteristics 4 Register Port PO P0 Port PO direction register DO Port P1 P1 Port P1 direction register D1 Port P2 P2 Port P2 direction register D2 Port P3 P3 Port P3 direction register D3 Port P5 P5 Port P5 direction register D5 Port P3 output mode control register P3S DA H register DA H DA L register DA L PWMO register PWMO PWM1 register PWM1 PWM register PWM2 register PWM3 PWM4 register PWM4 PWM output control register 1 PW PWM output control register 2 PN Serial I O mode register SM Serial I O regsiter SIO DA1 conversion register DA1 DA2 conversion register DA2 M37220M3 XXXSP FP 6 26 Bit allocation gt i Function bit __ No function bit Fix this bit to 0 do not write 1 Fix this bit to 1 do not write 0 Bit allocation DAIS 15 Pw Pw rns ewe wa we Pw Pw a ee sus 0 5 swe DA15 DA14 DA13 DA12 DA11 DA25 DA24 DA23 DA22
37. Status data register 8 RW mmm CONDITION Determination is completed Color system determination bit 1 SECAM 4 detection bit 0 AFTO 5 signal detection bit 1 Synchronous presence lt Without ear determination bit COINCIDENCE 1 It is synchronization 7 Frequency determination bit 50 Hz 50 60 60 Hz Fig 5 5 16 Status data register 7220 Group User s Manual 5 39 APPLICATION 5 5 Example of 5 control by software M37220M3 XXXSP FP 5 40 B Bit 0 Color system determination bit 0 CONDITION This bit indicates whether the color system is being determined or not Figure 5 5 16 shows the state of determination according to the bit when AUTO bit 5 at sub address 06 e write data is set to 1 When AUTO bit 5 at sub address 06 e write data is set to 0 bit 0 is invalid as the color system is not determined automatically Bit 1 Color system determination bit 1 SECAM Bit 2 Color system determination bit 2 NTSC These bits determine the color system Bit 3 3 58 4 43 determination bit 3 58 This bit determines whether a color signal sub carrier of the color system is 3 58 MHz or 4 43 MHz Bit 4 signal detection bit 0 AFTO Bit 5 AFT signal detection bit 1 AFT1 These bits detect the level of the auto fine tuning signal Bit 6 Synchronous presence determination bit COINCIDENCE This bit determi
38. enable bit TM1E 1 Interrupt enabled Timer 2 interrupt 0 Interrupt disabled enable bit TM2E 1 Interrupt enabled Timer 3 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled Timer 4 interrupt 0 Interrupt disabled enable bit TM4E 1 Interrupt enabled CRT interrupt enable 0 Interrupt disabled bit CRTE 1 Interrupt enabled VSYNC interrupt 0 Interrupt disabled enable bit VSCE 1 Interrupt enabled Multi master 1 C BUS interface 0 Interrupt disabled EX interrupt enable bit IICE 1 Interrupt enabled interrupt 0 Interrupt disabled enable bit IT3E 1 Interrupt enabled Fig 2 5 5 Interrupt control register 1 address OOFE Interrupt Control Register 2 b7 b6 656463 626160 Interrupt control register 2 ICON2 Address 00FF16 ST f Tec Row interrupt 0 Interrupt disabled enable bit IT1E 1 Interrupt enabled 2111 2 interrupt enable 0 Interrupt disabled i bit IT2E 1 Interrupt enabled 2 Serial I O interrupt 0 Interrupt disabled RW enable bit S1E 1 Interrupt enabled 3 Fix this bit to 0 RENE f XIN 4096 interrupt 0 Interrupt disabled RW bit MSE 1 Interrupt enabled Fix these bits to 0 EXE 7 Fig 2 5 6 Interrupt control register 2 address 00FF16 7220 Group User s Manual 2 31 FUNCTIONAL DESCRIPTION 2 5 Interrupts Interrupt Input Polarit
39. to bit 7 of the CRT control register the pin functions as CRT output pin when setting 0 the pin functions as a general purpose l O port Ports 1 14 are used as SCL1 SCL2 SDA1 and SDA2 respectively Port 15 is also used as external interrupt input pin INT3 and analog input A D1 Ports P1e and P17 are also used as analog input pins A D2 and A D3 respectively Port P2 Port P2 is an 8 bit I O port The output structure is CMOS output however only when ports P2o and P2 are used as serial pins the output structure is N channel open drain output Port P2 has basically the same function as port PO Port P2o is also used as serial I O synchronous clock input output Port P2 is also used as serial data output pin Sour Port P22 is also used as serial data input pin Sm Port P2s is also used as external clock input pin TIM3 When the timer 3 count source is supplied form an external device as set by the timer 34 mode register the input signal to this pin is the timer 3 count source The port 24 is also used as external clock input pin TIM2 When the count source for timer 2 is supplied form an external device as set by the timer 12 mode register the input signal to this pin is the timer 2 count source Ports P2s P27 has only port function Port P3 Ports P3o P3 are 3 bit I O ports ports P3s and P34 are a 2 bit input port For the output structure of ports P3o and P3 either CMOS ou
40. 7220 Group User s Manual M37220M3 XXXSP FP 4 6 Electrical characteristics A D Comparator characteristics Vcc 5 V 10 96 Vss 0 V f Xin 8 MHz 10 C to 70 C unless otherwise noted Limits Parameter Test conditions Resolution Absolute accuracy Note When Vcc 5 V 1 LSB 5 64 V D A Converter characteristics Vcc 5 V 10 96 Vss 0 V f Xin 8 MHz 10 C to 70 C unless otherwise noted Limits Parameter Test conditions Min Unit Resolution 6 bits Absolute accuracy 2 96 Setting time 3 us Ro Output resistor 1 2 5 4 7220 Group User s Manual 4 31 M37220M3 XXXSP FP 4 7 Standard characteristics 4 7 Standard characteristics The data described in this section are characteristic examples Refer to 4 6 Electrical characteristics for rated values 1 Ports POo P05 and P32 a loL VoL characteristics 100 00 80 00 5 5 60 00 40 00 LOW level output current OL mA 0 000 1 200 2 400 3 600 4 800 6 000 LOW level output voltage V OL V 2 Ports P06 and P07 IOH VOL characteristics 5 5 HIGH level output current OH mA 0 000 1 200 2 400 3 600 4 800 6 000 LOW level output voltage V OL V 4 32 7220 Group User s Manual M37220M3 XXXSP FP 4 7 Standard charact
41. Connect this pin to Vss Reset input pin RESET This pin inputs reset signal To reset the microcomputer hold the RESET pin at a LOW level for 2 us or more Reset is released when HIGH level is applied to the RESET pin For details refer to 2 15 Reset Clock I O pins Xin These pins pins of main clock f Xin Since a microcomputer has on chip clock oscillation circuit set the oscillation frequency by connecting an external ceramic resonator or a quartz crystal oscillator between pins and Xour When inputting an external clock connect the external clock to the and leave the pin open The output structure of Xour pin is CMOS output Power source input pin Vcc Vss These pins supply the power source to a microcomputer Apply voltage of 5 V 10 96 to pin Vcc and 0 V to pin Vss 7220 Group Users Manual 2 23 FUNCTIONAL DESCRIPTION 2 4 Input Output pins POo PWMO PO0 5 PWMS P32 N channel open drain output Direction register Data bus Port latch P10 OUT2 P11 SCL1 P12 SCL2 P13 SDA1 P14 SDA2 P15 A D1 INT3 P16 A D2 P17 A D3 20 5 P21 SOUT P22 SIN P23 TIM3 P24 TIM2 25 2 P30 A D5 P31 A D6 Direction register CMOS output Data bus Port latch When ports 11 14 are used as multi master I2 C BUS interface pin and when ports P20 P21 are used serial output pins their output structure is N channel open drain ou
42. Data is used to adjust the output DC level of R G and B signals EF This register performes the fine adjustments to the trap frequency of TRAP for Y C separation 7220 Group User s Manual 5 43 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP SERSW This switch is for white balance adjustments of the TV picture in the factory When SERSW is 0 it is OFF when 1 it is ON B HST This switch stops horizontal oscillation When HST is 0 the oscillation continues when 1 it stops AFCG This switch increases AFC gain When AFCG is 0 AFC gain is normal when 1 it is high 5 44 7220 Group User s Manual APPLICATION it example Ion Circul 5 6 Applicat t example Ion Circuli 5 6 Applicat 5 6 1 Application circuit example 1 19431 320915 peureiqo osje GSO JO 050 910 AAO NO punos g ONASA ONASH YAWIL NO jonuoo sseg jeun LA SSANO SSA M37221Mx XXXSP FP indui ns punog 1 7 M52340SP
43. E add W 016 subraddiess K Multi master 12C interface interrupt enable bit Bit 5 of 12C status register Write start Initialization 52 address 0008 16 11000101 2 510 address 00DA 16 lt 010010002 bit6 at address OOFE 16 0 Disable multi master 2C BUS interface interrupt 1 address 000916 000100002 Setting for outputting the START condition in data output processing routine A lt Slave address W 0 16 Ett 00 Transmit the START condition and slave address W Transmit sub address and data Note 1 Refer to 3 Data output processing routine 1 address 002816 2 110000002 S1 address 007816 lt 110100002 Transmit the STOP condition Within 10 0 Note 2 Be sure to set between S1 and S1 within machine 10 machine cycles cycles Fig 5 4 4 Flowchart of write processing routine 7220 Group User s Manual 5 23 APPLICATION 5 4 Example of I C BUS interface cont rol M37221Mx XXXSP FP 2 Read processing routine Q A A A S0 Accumulator 12 data shift register A Slave address c W 016 K A Sub address 5 R Slave address 51 52 10 12 status register 12C clock control register 2 control register Multi master 12C interface R A116 Read start Initiali
44. ROM correction function 1 Correction code 25 NOP ROM correction function 1 Correction code 26 NOP ROM correction function 1 Correction code 27 NOP ROM correction function 1 Correction code 28 EA NOP ROM correction function 1 Correction code 29 EAH NOP ROM correction function 1 Correction code 30 4CH JMP YYXXH ROM correction function 1 Correction code 31 XXH 02216 ROM correction function 1 Correction code 32 YYH see note ab a ii ii m gt gt lt m Zr Note When operating normally this instruction is not executed This is a redundant processing to reset during program runaway Fig 5 3 4 EPROM map when using ROM correction function 1 7220 Group User s Manual 5 17 APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP address Machine instruction correction program ROM correction function 2 Valid invalid 55H valid others invalid ROM correction function 2 Execution address high order ROM correction function 2 96H Execution address low order 02616 correction function 2 Correction code 1 02716 R M correction function 2 Correction code 2 SEERA 02816 ROM correction function 2 Correction code 3 02916 correction function 2 Correction code 4 o2A16 correction function 2 Correction code 5 SS INS Refer to o
45. next Vsync If CRT interrupts do not occur as many times as the number of display lines the following causes can be assumed Display position overlaps CRT interrupt processing time is too long resulting in no display of that line 2 lines after the line being displayed For example a CRT interrupt occurs at the end of the second line display in Figure 5 1 7 Within this interrupt processing setting for the 4th line display is completed However if a scanning line is over the display position of the 4th line that is in Figure 5 1 7 during this setting one CRT interrupt request is deleted or does not occur Therefore the line counter value is disordered and multi line display is not displayed correctly In such cases due to whatever causes correct the value with processing C of Vsync interrupt processing refer to Figure 5 1 4 When the CRT interrupt software processing overtime causes this state change the display positions or shorten the CRT interrupt software processing time 5 8 7220 Group User s Manual APPLICATION 5 1 Example of multi line display 5 1 7 Set of multiple interrupts 1 When not setting multiple interrupts When two or more interrupt requests occur at the same sampling point the interrupt with the higher priority refer to 2 5 Interrupts Table 2 5 1 is received This priority level is determined by hardware but various priority processing by software can be executed using the interr
46. 0 by detecting the STOP condition or START condition Bit 2 Slave address comparison flag AAS This flag indicates a comparison result of address data the slave receive mode when the 7 bit addressing format is selected this bit is set to 1 in one of the following conditions The address data immediately after occurrence of a START condition matches the slave address stored in the high order 7 bits of the 12 address register address 000816 general call is received the slave reception mode when the 10 bit addressing format is selected this bit is set to 1 with the following condition e When the address data is compared with the address register 8 bits consists of slave address and RBW the first bytes match The state of this bit is changed from 1 to 0 by executing a write instruction to the data shift register address 000716 Bit 3 Arbitration lost detecting flag AL In the master transmission mode when a device other than the microcomputer sets the SDA to LOW by any other device arbitration is judged to have been lost so that this bit is set to 1 At the same time the TRX bit is set to 0 so that immediately after transmission of the byte whose arbitration was lost is completed the MST bit is set to 0 When arbitration is lost during slave address transmission the TRX bit is set to 0 and the reception mode is set Consequently it becomes possible to re
47. 127 128Vcc Nothing is assigned These bits are write disable bits When these bits are reed out the values are 0 Fig 6 7 23 A D control register 2 Address OOEF16 7220 Group User s Manual 6 45 APPENDIX 6 7 Control registers Timer 12 Mode Register b7 b6 656463 6261 60 ECL Timer 12 mode register T12M Address 00F416 Timer 1 count source 0 XiN 16 selection bit T12MO 1 f XIN 4096 Timer 2 count source 0 Internal clock selection bit 1 External clock from T12M1 P24 TIM2 pin stop bit T12M2 1 Count stop IEEE stop 0 Count start ES T12M3 1 Count stop 4 Timer 2 internal count 0 f XiN 16 source selection bit 1 i overflow T12M4 5 Fix this bit to 0 bit to 0 D is assigned These bits are write disable bits When these bits are read out the values are Fig 6 7 24 Timer 12 mode register Address 00 416 6 46 7220 Group User s Manual APPENDIX 6 7 Control registers Timer 34 Mode Register b7 b6 656463 6261 60 Timer 34 mode register T34M Address 007516 8 Name Functions ater reset RW Timer 3 countsource 0 16 selection bit T34M0 1 External clock Timer 4 internal count 0 Timer overflow RW source selection bit 1 f XiN 16 T34M1 2 Timer 3 count 0 Count start stop bit T34M2 1 Count stop 3 Timer 4 count stop 0 Count start bit T34M3 1 Count stop 4 Timer 4 cou
48. 2 DA output polarity 0 Positive polarity R w selection bit PN3 1 Negative polarity output polarity 0 Positive polarity RW selection bit PN4 1 Negative polarity 4 DA general purpose 0 Output LOW R output bit PN5 1 Output HIGH 5 Nothing is assigned These bits are write disable bits to When these bits are read out the values are 0 Fig 2 10 7 PWM output control register 2 address 000616 2 70 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 CRT display function Table 2 11 1 shows the outline the CRT display function of the M37221M6 XXXSP FP M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP The M37221M6 XXXSP FP has the 24 characters X 2 lines CRT display circuit CRT display is controlled by the CRT control register Up to 256 kinds of characters can be displayed and colors can be specified for each character Up to 4 kinds of colors can be displayed on 1 screen A combination of up to 7 colors can be obtained by using each output signal R G and B Characters are displayed in a 12 X 16 dot structure to display smooth character patterns refer to Figure 2 11 1 How to display characters on the CRT screen is described below Write the display character code in the display RAM Specify the display color by the color register Write the color register in which the display color is set in the display RAM
49. 4 800 6 000 HIGH level output voltage V oH V 3 8 7220 Group User s Manual ELECTRICAL CHARACTERISTICS 3 2 Standard characteristics 5 Ports P24 P27 a loL VoL characteristics LOW level output current OL mA 0 000 1 200 2 400 3 600 4 800 6 000 LOW level output voltage V oL V b characteristics HIGH level output current oH mA 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V oH V 7220 Group User s Manual 3 9 ELECTRICAL CHARACTERISTICS 3 2 Standard characteristics 6 Ports P52 P55 a loL VoL characteristics LOW level output current OL mA 0 000 1 200 2 400 3 600 4 800 6 000 LOW level output voltage V oL V b characteristics HIGH level output current oH mA 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V oH V 3 10 7220 Group User s Manual CHAPTER 4 M37220M3 XXXSP FP 4 1 Performance overview 4 2 Pin configuration 4 3 Pin description 4 4 Functional block diagram 4 5 Functional description 4 6 Electrical characteristics 4 7 Standard characteristics M37220M3 XXXSP FP 4 1 Performance overview 4 1 Performance overview This chapter is described about M37220M3 XXXSP FP M37220M3 XXXSP FP has the comm
50. A NOP NOP m I m I m I Note When operating normally this instruction is not executed This is a redundant processing to reset during program runaway Fig 5 3 5 EPROM map when using ROM correction function 2 5 18 7220 Group User s Manual APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 5 3 4 General flowchart Figure 5 3 6 shows the general flowchart when using ROM correction function E7PROM addresses in the flowchart corresponds to E7PROM map refer to Figures 5 3 4 and 5 3 5 After reset release read the data from E2PROM ROM correction function 1 address 000 16 Valid invalid 5516 valid others invalid ROM correction function 2 address 023 16 Valid invalid Use ROM correction function 1 7 ROM correction address 1 high order ROM correction enable register address 021716 00116 of E2PROM 00 at address 0218 16 0 disabled ROM correction address 1 low order address 021816 00216 of E2PROM Store execution address Disable block 1 enable bit into ROM correction address 1 Store correction codes of ROM address 02C016 to 02DF 16 correction function 1 into ROM lt 00316 to 02216 of EPPROM correction memory 1 block 1 ROM correction enable register 00 at address 0218 16 lt 1 enabled Enable block 1 enable bit Use ROM correction function 2 7 ROM correction address 2 high order ROM correction enable
51. Fix of a port input level in stand by state In stand by state for low power dissipation do not make input levels of an input port and an I O port undefined especially for ports of the P channel and the N channel open drain Pull up connect the port to Vcc or pull down connect the port to Vss these ports through a resistor When determining a resistance value note the following points eG External circuit e Variation of output levels during the ordinary operation When using built in pull up or pull down resistor note on varied current values e When setting as an input port fix its input level e When setting as an output port prevent current from flowing out to external Reason Even when setting as an output port with its direction register in the following state N channel when the content of the port latch is 1 the transistor becomes the OFF state which causes the ports to be the high impedance state Note that the level becomes undefined depending on external circuits Accordingly the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and I O port are undefined This may cause power source current 2 stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction Modify of the contents of I O port latch When the port latch of an I O port is modified with the bit ma
52. HIGH input voltage POo P07 P10 P17 P2o P27 0 8Vcc Voc V 3 3 Sin Vsync RESET Xin OSC1 TIM2 TIM3 INT1 INT2 INT3 V LOW input voltage POo P07 P1o P17 20 25 0 O 4Vcc V P3o P34 LOW input voltage Vsync RESET 2 0 0 2 V TIM3 INT1 INT2 Xm OSC1 Sin HIGH average output current Note 1 B OUT D A P1o P17 1 mA 2 2 P30 lout LOW average output current Note 2 B OUT D A POs 2 mA P10 P17 20 27 2 lot LOW average output current Note 2 05 1 mA lots LOW average output current Note P24 P27 10 mA f Xw Oscillation frequency for CPU operation Note 5 7 9 8 0 81 MHz fort Oscillation frequency for CRT display Note 5 OSC1 5 0 8 0 MHz fst Input frequency TIM2 TIM3 100 kHz Input frequency 1 MHz Notes 1 The total current that flows out of the IC must be 20 mA max 2 The total input current to IC 1011 loL2 must be 30 mA or less 3 The total average input current for ports P24 P27 to IC must be 20 mA or less 4 Connect 0 1 uF or more capacitor externally across the power source pins 55 so as to reduce power source noise Also connect 0 1 uF or more capacitor externally across the pins VCC ONVSss 5 Use quartz crystal oscillator or a ceramic resonator for the CPU oscillation circuit 7220 Group Us
53. R G B can be specified by the character Display position horizontal vertical 64 levels horizontal 128 levels vertical Note Only M37221M8 XXXSP and M37221MA XXXSP have the function 1 4 7220 Group User s Manual OVERVIEW 1 2 Pin configuration 1 2 Pin configuration The pin configurations are shown in Figures 1 2 1 and 1 2 2 M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP HSYNC VSYNC POo PWMO PO1 PWM1 PO2 PWM2 P03 PWM3 PO4 PWMA P05 PWM5 POe INT2 A D4 PO7 INT1 P23 TIM3 P24 TIM2 P25 P26 P27 D A P32 CNVss XIN XOUT Vss Fig 1 2 1 Pin configuration top view 1 dSXXX VIN Lc 25 45 22250 dASXXX 9N 22250 dS OOCTIN 250 Outline 42 4 7220 Group User s Manual 52 P53 G P54 B P55 OUT1 P20 SCLK P21 SOUT P22 SIN P10 OUT2 P11 SCL1 P12 SCL2 P13 SDA1 P14 SDA2 P15 A D1 INT3 P16 A D2 P17 A D3 P30 A D5 P31 A D6 RESET OSC1 P33 OSC2 P34 Vcc OVERVIEW 1 2 Pin configuration Hsync 1100 P52 R Vsync 2 P53 G POo PWMO 3 P54 B 1 1 4 P55 OUT1 PO2 PWM2 5 20 5 6 P21 SoUT PO4 PWM4 7 P22 SIN 5 8 P10 OUT2 POs INT2 A D4 9 P11 SCL1 PO7 INT1 10 P12 SCL2 23 at P13 SDA1 24 2 12 P14 SDA2 P25 13 P15 A D1 INT3 P26 14 P16 A D2 P27 lt gt 15 P17 A D3 D A 1
54. T D m 5 5 5 7220 Group User s Manual MITSUBISHI 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 7200 SERIES Renesas Electronics www renesas com keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials information contained in these materials including product data diagrams and charts represe
55. Table 5 5 7 Data setting when changing video mute state Sub address Bit Data o MUTE Table 5 5 8 Data setting when adjusting white color balance Sub address Bit Data SERSW 5s 7220 Group User s Manual 5 35 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 5 5 6 Flowchart of data setting according to key processing Figures 5 5 13 to 5 5 15 show the flowcharts of controlling the M52340SP when there are various event inputs to the actual TV system 1 Poweron processing by power key input Power on Wait for stabilizing time to supply power source Set write data register of M52340SP To mute video and audio MUTE D6 at sub address 16 lt 1 A MUTE D6 at sub address 01 16 lt 1 Related processings OSD when power Write last data to E7PROM Wait for muting time To release mute of picture and sound MUTE D6 at sub address 16 0 A MUTE D6 at sub address 01 16 0 Fig 5 5 13 Flowchart of poweron processing 5 36 7220 Group User s Manual APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 2 CH UP DOWN key input processing CH UP DOWN To mute video and audio MUTE D6 at sub address OB 16 lt 1 MUTE D6 at sub address 01 16 lt 1 Related processings Changing CH OSD when changing CH Write last data to E7PROM elc Set the follow
56. W 0 16 NO ACK COUNTER 0 P START condition Data output No Yes ACK WRITEDATA Sub address Data output No Yes ACK START condition WRITEDATA lt Slave address R A1 16 Data output Notes 1 2 Branches according to whether the No device needs sub address or not Yes ACK Data input STOP condition READ DATA OUNTER 0 NO ACK COUNTER ACK COUNTER 1 Yes end Return NACK ACK COUNTER gt 3 No try 3 times ca Yes give up s STOP condition Return ACK Bus H READ DATA COUNTER lt READ DATA COUNTER 1 Fig 5 5 5 Flowchart of read processing routine 7220 Group User s Manual 5 29 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 3 Data output processing routine The data output the START condition the STOP condition and the bus H processing routines are the common routines within the transmit receive processing routine RAM WRITEDATA Data output BIT COUNTER Flag F ACK Bit 0 of port P2 direction register output mode COUNTER 0 Rotate WRITEDATA left with Carry flag Carry flag 1 Yes P20 SDA P20 SDA 0
57. When clearing corresponding bits to 0 positive polarity is selected when setting to 1 negative polarity is selected Refer to 2 11 7 CRT output pin control for detail Vsync signal input 8 machine cycles or more See note 4 Vsync control signal 0 125 to 0 25 us See note 2 in microcomputer Period of counting Hsync signal 3 HsvNc signal input decore T T T T Notcount 1 2 3 4 5 8 machine cycles or more See note 4 When bits 0 and 1 of the CRT port control register address 00 16 are set to 1 negative polarity Note 1 The vertical position is determined by counting falling edge of Hsvwc signal after rising edge of Vsync control signal in the microcomputer 2 At f Xin 8 MHz 3 Do not generate falling edge of Hsvwc signal near rising edge of Vsync control signal in microcomputer to avoid jitter 4 Pulse width of Vsync and of Hsync signals needs 8 machine cycles or more Fig 2 11 4 Count method of synchronous signal 2 74 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function The block 2 is displayed after the display of block 1 is completed refer to Figure 2 11 5 a Therefore set vertical display start position of block 2 to be lower than the display end position of block 1 The block 2 cannot display when the display position of block 2 is overlapped with the display position of block 1 refer to Figure 2 11 5
58. addresses 02C0 16 to 020 16 0300 Block 2 addresses 02 016 to 02 16 Internal RAM 02 0 033 OBFie 0 RAM for display soos 8000 CRT display RAM 0600 Not used 96 bytes See note 0687 ROM ROM 40 K bytes 32 K bytes for for M37221MA M37221M8 Special page 65535 1FFFF16 131071 Note Refer to Table 2 11 4 Contents of CRT display RAM Fig 6 5 2 Memory assignment of M37221M8 XXXSP and M37221MA XXXSP 6 18 7220 Group User s Manual APPENDIX 6 5 Memory assignment 5 ROM for display 000016 0 1000016 RAM CRT display ROM 00C016 SFR area 192 Zero page Special function register 10FFFi6 TN Internal 64 bytes L013F 16 319 bs for display Hexadecimal notation Decimal notation 192 bytes 4 K bytes 256 bytes 00FF16 Refer to Figures 4 5 3 and 4 5 4 255 060016 CRT display RAM 06 316 200016 Internal ROM ROM 12 K bytes FFDE16 65502 Interrupt vector area FFFF16 P 65535 FF0016 65280 Special page 1FFFF16 131071 Note Refer to Table 4 5 7 Contents of CRT display RAM Fig 6 5 3 Memory assignment of M37220M3 XXXSP FP 7220 Group User s Manual 6 19 APPENDIX 6 6 SFR assignment 6 6 SFR assignment Area addresses C016 to DF 6 Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 0016 0116 02
59. b or is higher than the display position of block 1 refer to Figure 2 11 5 c Same as above at the multiline display the next block 1 cannot be displayed until the display of block 2 is completed Therefore set the display start position of the second and later block 1 to be lower than the display position of the last block 2 refer to Figure 2 11 5 Because the block 2 is higher than the block 1 the block 2 cannot be displayed Block 1 last displayed CV1Y 7 2 2 4 1 Because the block 1 overlaps the block 1 the block 2 cannot be with the last display of block 2 Because the block 2 overlaps with displayed the block 1 cannot be displayed d Example when the block 1 overlaps with the last b Example when block 2 overlaps with block 1 display of block 2 at the multiline display Fig 2 11 5 Display position 7220 Group User s Manual 2 75 FUNCTIONAL DESCRIPTION 2 11 CRT display function The vertical position can specify 128 step positions 4 scanning lines per step for each block by setting values 00 e to 7F e to bits O to 6 of the vertical position registers the blocks 1 and 2 are assigned to addresses to OOE1 e 00 2 respectively Figure 2 11 6 shows the vertical position registers Vertical Position Register n 67 b6 65 b4 b3 b2 bi 60 Vertical position register n CV1 CV2 n 1 and 2 Addresse
60. bit CM2 1 1 page Indeterminate Note This bit is set to 1 after reset release Fig 2 1 2 CPU mode register With the stack pointer during a interrupt or subroutine call the processing is performed automatically in the following sequence refer to Figure 2 1 3 The contents of high order 8 bits of the program counter are stored at an address indicated as below high order 8 bits are the stack area value 00 e O116 The low order 8 bits are the stack pointer contents The stack pointer contents are decremented by 1 The contents of low order 8 bits of the program counter are stored at an address indicated as below high order 8 bits are the stack area value 00 e O116 The low order 8 bits are the stack pointer contents The stack pointer contents are decremented by 1 The contents of the processor status register PS are stored at an address indicated as below high order 8 bits are the stack area value 00 e O116 The low order 8 bits are the stack pointer contents The stack pointer contents are decremented by 1 7220 Group User s Manual 2 3 FUNCTIONAL DESCRIPTION 2 1 Central processing unit Storing of the processor status register in items and above is not performed during a subroutine call Execute the PHP instruction in a program to push the processor status register onto a stack To prev
61. f XIN 16 is selected as the timer 3 count source 7220 Group User s Manual 2 39 FUNCTIONAL DESCRIPTION 2 7 Serial 2 7 Serial The M37221M6 XXXSP FP has on chip clock synchronous serial I O which can receive and transmit 8 bit data serially Because pin Sout also can be used as the serial I O data input pin it can transmit and receive with only one signal line 2 7 1 Structure of serial Serial consists of Serial register Serial mode register Serial counter Clock source generating counter The serial I O register is the register which 8 bit transfer data is written into Each function of serial be controlled by setting appropriate values to the serial I O mode register Serial I O transfers data to and from the internal CPU via the data bus and it transfers data to and from external devices via ports P22 P20 When using the serial I O ports P22 P2 have the following functions P2 Serial synchronous clock input output pin P2 Serial I O data input output pin Sour P2 Serial data input Sin The functions of these ports can be selected by the serial mode register The transfer clock that determines the serial data transfer rate can selected 4 kinds of clock sources with the serial mode register Figure 2 7 1 shows the serial block diagram Figure 2 7 2 shows the serial mode register 2 40 7220 Gr
62. or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway Oscillator protection using Vss pattern As for a two sided printed circuit board print a Vss pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring Besides separate this Vss pattern from other Vss patterns Microcomputer Mutual inductance Large current Fig 6 4 7 Wiring for large current signal line Fig 6 4 8 Wiring for signal line where potential levels charge frequently An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the Vss line for oscillation from other V 55 lines Fig 6 4 9 Vss pattern on underside of an oscillator 7220 Group User s Manual APPENDIX 6 4 Countermeasures against noise 6 4 5 Setup for ports Setup ports using hardware and software as follows Hardware Ge Connect a resistor of 100 or more to an I O port in series Software As for an inpu
63. which may cause a program runaway 6 12 7220 Group User s Manual 6 4 2 Connection of a bypass capacitor across Vss line and Vcc line Connect an approximately 0 1 uF bypass capacitor across the Vss line and the Vcc line as follows e Connect a bypass capacitor across the Vss and the Vcc pin at equal length e Connect a bypass capacitor across the Vss and the Vcc pin with the shortest possible wiring e Use lines with a larger diameter than other signal lines for Vss line and Vcc line 6 4 3 Wiring to analog input pins e Connect an approximately 100 to 1 resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible e Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the analog input pin and the Vss pin at equal length Reason Signals which is input in an analog input pin such as an A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin If a capacitor between
64. 16 to FF16 Color specification 1st character 0680 16 to 24th character 0697 16 Color register specification 0 0 Specifying color register 0 0 1 Specifying color register 1 1 0 Specifying color register 2 1 1 Specifying color register 3 Block 2 Character specification 1st character 062016 to 24th character 0637 16 Character code Specify 256 characters 00 16 to FF16 Color specification 1st character 16 to 24th character 06B7 16 Color register specification 00 Specifying color register 0 0 1 Specifying color register 1 1 0 Specifying color register 2 1 1 Specifying color register 3 Fig 2 11 11 Structure of CRT display RAM 7220 Group User s Manual 2 81 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 4 Color registers A display character color can be specified by setting a color to one of 4 color registers COO to CO3 addresses 00 6 to 00 9 and then by specifying the color register with the CRT display RAM There are color outputs and B By a combination of these outputs it is possible to set 23 1 no output 7 colors However since color registers are only 4 up to 4 colors can be displayed at one time R G and B outputs are set by bits 1 to 3 of the color register Bit 5 is used to specify either a character output or blank output Figure 2 11 12 shows the color register Either character output or blank outpu
65. 21 7220 Group User s Manual APPENDIX 6 6 SFR assignment State immediately after reset gt 0 immediately after reset Read enabled write enabled 1 t immediately after reset Read enabled write disabled Undefined immediately after reset 6721818 immediately after reset Access characteristics RW 7220 Group Users Manual 6 27 APPENDIX 6 6 SFR assignment Area addresses E016 to FF 6 Bit allocation gt Function bit m No function bit Fix this bit to 0 do not write 1 Fix this bit to 1 do not write 0 Address Register Bit allocation E016 Horizontal position register HR HR3 HRO E116 Vertical position register 1 CV1 cvia evia eviz ovi evto E216 Vertical position register 2 CV2 CV24 CV23 CV22 CV21 CV20 E316 E416 Character size register CS CS10 E516 Border selection register MD E616 Color register 0 COO 003 CO02 E716 Color register 1 CO1 6013 CO12 E816 Color register 2 CO2 6023 CO22 E916 Color register 3 CO3 CO33 CO32 EA16 CRT control register CC CC2 16 CRT port control register OUT VSYC HSYC ED16 CRT clock selection register CK OJ O 0 EE16 A D control register 1 AD1 ADM ADM
66. 4 at address 0009 16 z 1 No not end Yes end Store recive data to internal RAM Waiting receive end Within 10 machine J eydes c S1 address 00F816 lt 110000002 S1 address OOF8 16 lt 110100002 0 Transmit the STOP condition Note 1 Be sure to set between S1 and 51 within 10 machine cycles End C Note 2 The timeout count is performed by software with interrupts such as timers Accordingly if receive operation is not completed due to various influences the loop continues Therefore if receive operation does not complete within a certain time I C BUS access is stopped by outputting STOP condition If 2C BUS access is stopped by timeout the obtained data is incorrect data Fig 5 4 5 Flowchart of read processing routine 5 24 7220 Group User s Manual APPLICATION 5 4 Example of I C BUS interface control M37221Mx XXXSP FP 3 Data output processing routine The data output processing routine is the common routine within the transmit receive processing routine Accumulator Data output 12C status register Communication mode specification bit Store the number of output bytes to internal RAM Arbitration lost detecting flag Multi master 2 interface interrupt enable bit SO address 0007 16 Data to be output Last receive bit The first byte Yes Output A 51 address 0009 16 111100002 PE An error
67. 5 16 CRT port control register address OOEC16 ssssssseseee 4 25 Fig 4 5 17 Internal state immediately after reset 1 4 26 Fig 4 5 18 Internal state immediately after reset 2 4 27 CHAPTER 5 APPLICATION Fig 5 1 1 Connection example nens 5 2 5 1 2 Display example ncc Hte eio Hl eee ra EE ee unn 5 2 Fig 5 1 3 Flowchart of initialization processing routine 5 3 Fig 5 1 4 Flowchart of Vsync interrupt processing routine 5 4 Fig 5 1 5 Flowchart of CRT interrupt processing 2 5 5 Fig 5 1 6 Set of display character data eene nennen 5 6 Fig 5 1 7 Example of setup timing for line counter and display character data 5 7 Fig 5 1 8 Timing of interrupt processing when not setting multiple interrupts 5 9 Fig 5 1 9 Timing when all interrupt request bits are 1 at the same sampling point 5 10 7220 Group User s Manual vii List of figures Fig 5 1 10 Flowchart of CRT interrupt processing routine when setting multiple interrupts nm 5 11 Fig 5 1 11 Flowchart of Vsvwc interrupt processing routine when setting multiple interrupts sse 5 12 Fig 5 2 1 Color register n 37221 55 5 13 Fig 5 2 2 Color register 37220 3 2 5 14 Fig 5 2 3 Border selection register M
68. 7 6 8 ella MEME E 6 8 6 9 aum dx M 6 9 morem 6 10 D ueni dM M EM 6 10 mE 6 11 6 11 6 13 T EET 6 13 BEEE E 6 14 rM x 6 15 6 4 6 Providing of wa Jog 6 16 Serene ne SAE RN tier tener 6 17 E 6 20 ontro Tii 6 30 O 6 51 6 53 6 63 ace 6 64 X 6 80 iv 7220 Group User s Manual List of figures List of figures CHAPTER 1 OVERVIEW Fig Fig Fig 1 2 1 Pin configuration top view 1 nennen nnne 1 5 1 2 2 Pin configuration top view 2 enne nnnm 1 6 1 4 1 Functional block diagram 1 9 CHAPTER 2 FUNCTIONAL DESCRIPTION Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 2 1 1 Registers configuration 2 2 2 1 2 CPU mode tete od ites 2 3 2 1 3 Sequence of push onto pop from a stack during interrupts
69. 70 C unless otherwise noted Limits Symbol Parameter Test conditions Min Max Unit lcc Power source current System operation Vcc 5 5 V CRT OFF 20 40 mA 8 MHz CRT 30 60 Stop mode Vcc 5 5 V 0 300 pA HIGH output voltage B OUT1 D A Vcc 4 5 V 2 4 V 1 1 2 2 0 5 mA P30 P3 VoL LOW output voltage OUT1 D A Vcc 4 5 V 0 4 V 0 0 lo 0 5 mA P1s P17 20 23 2 LOW output voltage P1 P12 Vcc 4 5 V lou 3 mA 0 4 lo 6 mA 0 6 LOW output voltage 24 2 Vcc 4 5 V 3 0 lo 10 0 mA Vr Vr Hysteresis RESET Vcc 5 0 V 0 5 07 V Hysteresis Note Hsync Vsync TIM2 5 0 V 0 5 1 3 INT2 5211 SCL2 SDA1 5042 Sn HIGH input leak current RESET 0 0 Voc 5 5 V 5 P1o P17 2 2 5 5 V P3o P34 Vsync liz LOW input leak current RESET POc PO Voc 5 5 V 5 P10 P17 20 25 P3o P34 Hsync Vsync loza HIGH output leak current 0 05 5 5 V 10 12V Res 120 805 805 switch connection resistor Vcc 4 5 V 130 W between SCL1 and SCL2 SDA1 and SDA2 Note P07 P15 P23 and P24 have the hysteresis when these pins are used as interrupt input pins timer input pins P20 P22 have the hysteres
70. 9 5 sisseuo 7220 Group User s Manual 5 46 6 APPENDIX 6 1 Package outlines 6 2 Termination of unused pins 6 3 Notes on use 6 4 Countermeasures against noise 6 5 Memory assignment 6 6 SFR assignment 6 7 Control registers 6 8 Ports 6 9 Machine instruction table 6 10 Instruction code table 6 11 Mask ROM ordering method 6 12 Mark specification form APPENDIX 6 1 Package outline 6 1 Package outline 42PAB Plastic 42 GOOmil SDIP EIAJ Package Code JEDEC Code Weight Lead Material 01 42 600 1 78 4 1 Alloy 42 Cu Allo Dimension in Millimeters Min Nom SEATING PLANE 42P2R A Plastic 42pin 450mil SSOP EIAJ Package Code JEDEC Code Weight g Lead Material SSOP42 P 450 0 80 0 63 Alloy 42 Allo Ere up Recommended Mount Pad Dimension in Millimeters Detail F 6 2 7220 Group User s Manual APPENDIX 6 2 Termination of unused pins 6 2 Termination of unused pins Table 6 2 1 Termination of unused pins Pin Input m M37221Mx XXXSP FP
71. A D4 External interrupt input pin Analog input pin INT1 External interrupt input pin P1o OUT2 CRT output pin P1 SCL1 Multi master I C BUS interface pin P12 SCL2 Multi master I C BUS interface pin 1 SDA1 Multi master I C BUS interface pin 14 SDA2 Multi master I C BUS interface pin 15 A D1 INTS3 Analog input pin External interrupt pin 16 A D2 Analog input pin 17 A D3 Analog input pin P2o Serial synchronous clock input output P21 Sout Serial data input output pin P22 S n Serial data input pin P23 TIM3 External clock input pin P24 TIM2 External clock input pin 25 27 Function as only programmable ports P3o A D5 Analog input pin P31 A D6 Analog input pin P32 Functions as only programmable port OSC1 CRT display clock input pin P34 OSC2 CRT display clock output pin P52 R CRT output pin 5 output 54 CRT output pin 55 OUT1 CRT output pin 2 22 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 4 Input Output pins 2 4 2 Dedicated pins 1 2 3 4 S 6 14 bit PWM output D A pin This is a 14 bit PWM signal output pin This pin also can be used for 1 bit general purpose output port The output structure is CMOS output Vertical and horizontal synchronous signal input pins Vsync Hsync These pins input the vertical and horizontal synchronous signals for CRT display Test input pin CNVss
72. ADM1 ADMO A D control register 2 AD2 ADC4 ADC3 ADC2 ADC1 ADCO 016 Timer 1 1 F116 Timer 2 TM2 F216 Timer 3 TM3 F316 Timer 4 TM4 F416 Timer 12 mode register T12M 0 T 2w4 12 12 2 T12M1 12 0 F516 Timer 34 mode register T34M T34M5 T34M4 T34M3 T34M2 T34M1 34 0 F616 PWMB register 5 F716 F816 F916 Interrupt input polarity register RE RE4 REs 0 0 FA16 Test register TEST CPU mode register CPUM Interrupt request register 1 IREQ1 CRTR TM2R ruir FD16 Interrupt request register 2 IREQ2 MsR 51 FE16 Interrupt control register 1 CRTE wt FF16 Interrupt control register 2 ICON2 Q StE 1 2 1 1 Fig 6 6 5 SFR assignment including internal state immediately after reset and access characteristics 5 M37220M3 XXXSP FP 6 28 7220 Group User s Manual APPENDIX 6 6 SFR assignment State immediately after reset gt 0 0 immediately after reset Read enabled write enabled 1 immediately after reset RO Read enabled write disabled 2 Undefined immediately after reset State immediately after reset Access characteristics b7 50 57 0016 RW Du Ses RW RW RW RW RW RW RW
73. ER E 1 8 CHAPTER 2 FUNCTIONAL DESCRIPTION Table 2 2 1 Zero page 4 2 10 Table 2 2 2 Special page 2 10 Table 2 4 1 List of programmable port functions 8 2 22 Table 2 5 1 Interrupt sources vector addresses and priority 2 26 Table 2 6 1 Memory map of timer related 2 37 Table 2 6 2 Contents of timers 3 and 4 when reset or when executing STP instruction 2 39 Table 2 7 1 Clock source nnne teneris 2 42 Table 2 8 1 Multi master I C BUS interface 2 47 Table 2 8 2 START condition STOP condition generation timing table 2 58 Table 2 8 3 START condition STOP condition detect conditions 2 59 Table 2 9 1 Relationship between contents of A D control register 2 and reference ceri uU 2 62 Table 2 10 1 PWM function performance at oscillation frequency 8 MHz 2 63 Table 2 10 2 The relation between D and tm m 0 to 68 2 65 Table 2 11 1 Outline of CRT display function 2 71 Table 2 11 2 Relationship between set value in character size register and character 2 77 Table 2 11 3 Character code table b
74. HIGH duration 0 256 to 255 256 are selected by changing the contents of the PWM register a length of entirely HIGH cannot be output 7220 Group User s Manual 2 67 FUNCTIONAL DESCRIPTION 2 10 PWM ZHN 8 sn pzOL 1 SI y indino WMd 1992 L 692 9 44 9 81 1 9 10 0 9 00 dE d cd Mo du 292 962 802 022 212 voc 96 88 081 edt 79 99 Shh vel 9 801 001 26 YSZ OSZ 9vz zvz 862 OEZ 922 222 812 1 012 902 202 861 61 061 981 281 8 1 721 0 1 991 291 851 HSI 091 ZHL SEL vEL OEL 921 221 811 HLL 011 901 ZOL 96 v6 06 98 28 BL HL OL 99 29 89 5 OS 9 20 BE vt 06 92 ZZ 8 HL OL 9 Z 992 092 ight Fig 2 10 5 Example of 8 bit PWM output Fig 2 10 4 Pulse waveforms corresponding to we of each bit of 8 bit PWM register 7220 Group User s Manual 2 68 FUNCTIONAL DESCRIPTION 2 10 PWM 2 10 4 14 bit PWM output control How to control the 14 bit PWM output is described below Set 0 to bit 0 of PWM output control register 1 address 00D5 e to supply the PWM count source this bit is cleared to 0 when reset Set the high order 8 bits of the output data to the DA H register Set the low order 6 bits of the output data to the DA L register Data is written to the 14 bit PWM circuit by writing data to the DA L
75. If a potential difference is caused by the noise between pins CNVss and Vss the processor mode may become unstable This may cause a microcomputer malfunction or a program runaway Noise CNVss CNVss Vss Vss O K N G Fig 6 4 3 Wiring for CNVss pin 4 Wiring to pin of One Time PROM version and EPROM version When the pin is also used as the CNVss Connect an approximately 5 kW resistor to Approximately the pin the shortest possible in series and sum also to the Vss pin When not connecting the CNVSS VPP resistor make the length of wiring between the Ver and the Vss pin the shortest possible refer to countermeasure example 1 of Figure 6 4 4 Vss In the shortest distance 1 When a microcomputer has the CNVss pin the pin is also used as the CNVss pin Fig 6 4 4 Wiring for Ver of One Time Note Even when a circuit which included an PROM and EPROM version approximately 5 kW resistor is used in the Mask ROM version the micro computer operates correctly Reason The pin of the One Time PROM and the EPROM version is the power source input pin for the built in PROM When programming in the built in PROM the impedance of the pin is low to allow the electric current for writing flow into the PROM Because of this noise can enter easily If noise enters the abnormal instruction codes or data are read from the built in PROM
76. M37220M3 XXXSP FP Output Termination POo PWMO P0s PWM5 POe INT2 A D4 POz INT1 1 00 2 P1o P1 SCL1 P1 P12 SCL2 P12 P13 SDA1 1 P14 SDA2 14 Set the port direction registers for the input 5 mode and pull down through a resistor P17 A D3 P2o Scik P21 Sour 22 P23 TIM3 P24 TIM2 25 27 P30 A D5 P30 A D5 DA1 P31 A D6 P30 A D6 DA2 P32 P33 OSC1 P34 OSC2 Input Pull down through a resistor HsvNc Vsync P52 R P53 G P54 B P5JOUT1 m Output Xour D A It is the same as M37221Mx XXXSP FP 7220 Group User s Manual 6 3 APPENDIX 6 3 Notes on use 6 3 Notes on use Notes on programming and equipping when using M37221M6 XXXSP FP are described below 6 3 1 Notes on processor status register 1 Initialization of processor status register The contents of processor status register PS are undefined except the flag 1 1 immediately after reset Therefore initialize the flags that affect execution of a program Especially be sure to initialize the T and D flags because they have an important effect on calculations Main program Y Fig 6 3 1 Initialization of flags in PS 2 How to refer to processor status register When referring to the processor status register PS contents execute the PHP instruction to push the processor status register contents into the stack S 1 And then read the contents
77. NISEN NAAA d EC 02CA 4C26E1 JMP 126 SSS Note In E126H is specified as the return destination address of JMP In this example since the instruction at the return destination address is RTS even if RTS is used instead of JMP the operation is the same as that of JMP As a result the number of bytes is reduced Fig 5 3 2 Correction example 1 7220 Group User s Manual 5 15 APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 2 Correction example 2 The loop processing is performed between 2 and in Figure 5 3 3 Two examples of this part are shown in detail Example A corrects in loop units and example B corrects only error instructions Examples A and B are the same operation differing in processing time and correction bytes only Depending on the contents of loop processing it may be preferable to include correct codes with the codes to be corrected simplifying the correction program and making it easier to read When omitting FE96H 9 and correcting from FE98H the program cannot move to FE96H by the BPL instruction the jump destination addresses of the BPL instruction are limited to bytes between 128 and 127 Therefore the example B is provided Example A Program before correction Correction program Address Machine Description style Address Machine Description style instructions block 2 instructions FE96 129525 SS STA 025 XON NO2E0 69525 025 X
78. OSC1 P33 OSC2 P34 Vcc 4 5 M37220M3 XXXSP FP 4 3 Pin description 4 3 Pin description The pin description of M37220M3 XXXSP FP is shown in Table 4 3 1 Table 4 3 1 Pin description 1 Pin Name ipu Functions Output Vcc Power source Apply voltage of 5 10 typical to Vcc and 0 V to Vas Vss CNVss CNVss This is connected to Vss RESET Reset input Input To enter the reset state the reset input pin must be kept at a L for 2 us or more under normal Vcc conditions If more time is needed for the quartz crystal oscillator to stabilize this L condition should be maintained for the required time Clock input Input This chip has an internal clock generating circuit To control generating frequency an external ceramic resonator or a quartz crystal oscillator Clock output Output is connected between pins Xi and If an clock is the clock source should be connected to the Xin pin the pin should be left open 0 port PO Port PO is an 8 bit I O port with direction register allowing each bit to be individually programmed as input or output At reset this port is POs set to input mode The output structure is N channel open drain output PWM5 The note out of this Table gives a full of port PO function POs INT2 PWM output Output Pins 0 05 are also used as PWM output pins PWMO PWM5 A DA respe
79. STOP condition Acknowledge bit Write bit 0 Fig 5 4 2 Byte write timing 2 Random address read In this mode the data of an arbitrary address is read To set the first read address the master sends the START condition slave address 016 and sub address 1 byte Upon receiving the acknowledge bit ACK from the E PROM the master sends the RESTART condition signal and slave address 1 6 again After is generated from the E PROM the data of the corresponding sub address is read out After the data is output no acknowledge bits are generated but the STOP condition is sent by the master completing this read operation Slave Bus operation of addere W Sub reseh Slave Address R master side Bus operation of slave side K K START condition Read bit 1 STOP condition RS RESTART condition Acknowledge bit NACK No acknowledge bit Write bit 0 z Fig 5 4 3 Random address read timing 5 22 7220 Group User s Manual APPLICATION 5 4 Example of I C BUS interface control M37221Mx XXXSP FP 5 4 4 General flowchart The processing routines which controls I C BUS devices branch to the write processing routine and the read processing routine The data output processing routine is used as the common processing routine 1 Write processing routine Accumulator 12C status register 12C clock control register ave address 12C control register
80. Serial 2 7 7 Note when selecting a synchronous clock Regardless of either an internal or external clock is selected as the serial synchronous clock source the interrupt request bit is set to 1 after 8 transfer clocks However the serial register contents will continue to be shifted as long as the transfer clock is being input to the serial I O circuit so it is necessary to stop after 8 transfer clocks When an internal clock is selected the transfer clock stops automatically after 8 clocks When an external clock is selected control the transfer clock externally Moreover use an external clock of 1 MHz or less with a duty cycle of 50 95 When selecting an external clock as the synchronizing clock write transmit data to the serial register transfer clock input level is HIGH Figure 2 7 6 shows the serial timing Synchronous clock Transfer clock Serial I O register writing signal Serial I O output SOUT Do Q X D2 D3 D4 D5 De A D7 Serial I O input SIN Se NE MES Se a Interrupt request bit is set to 1 Note When an internal clock is selected pin SOUT is at high impedance after transfer is completed Fig 2 7 6 Timing diagram of serial I O 7220 Group User s Manual 2 45 FUNCTIONAL DESCRIPTION 2 7 Serial The transmit side in Figure 2 7 7 P2 is set as the serial data output pin and 20 is set as the serial synchro
81. W result 1 Input voltage reference voltage Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 2 9 2 A D control register 1 address OO0EE A D Control Register 2 67 b6 65 64 b3 62 bi bO A D control register 2 AD2 Address 00 16 b5 b4 b3 b2 bi bO 0 0 1 128Vcc 0 1 3 128 1 0 5 128Vcc D A converter set bits 0 0 ADCO ADC1 ADC2 ADC3 ADC4 ADCS x 1 123 128Vcc 0 125 128Vcc 1 127 28Vocc Nothing is assigned These bits are write disable bits When these bits are reed out the values are 0 Fig 2 9 3 A D control register 2 address OOEFi 2 62 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 10 PWM 2 10 PWM The M37221M6 XXXSP FP has one 14 bit PWM pulse width modulator DA and six 8 bit PWM PWMO PWMS Table 2 10 1 shows the PWM function performance Table 2 10 1 PWM function performance at oscillation frequency 8 MHz Performance 14 bit PWM DA 8 bit PWM Resolution bits 14 8 Minimum resolution bit width Ls 0 25 4 Repeat cycle us 4096 1024 Figure 2 10 1 shows the 14 bit PWM block diagram and Figure 2 10 2 shows the 8 bit PWM block diagram DA H register Address 16 DA L register Note Address 00 16 DA latch 14 bits PWM timing generating circuit Selection gate Connected to black side when reset
82. When this bit is set to 0 the standard clock mode is set When the bit is set to 1 the high speed clock mode is set E Bit 6 ACK bit ACK This bit sets the SDA status when an ACK clock is generated When this bit is set to 0 the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock When the bit is set to 1 the non return mode is set The SDA is held in the HIGH status at the occurrence of an ACK clock However when the slave address matches the address data in the reception of address data at 0 the SDA is automatically made LOW is returned If there is a mismatch between the slave address and the address data the SDA is automatically made HIGH ACK is not returned clock Clock for acknowledgment B Bit 7 ACK clock bit ACK This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission When this bit is set to 0 the no ACK clock mode is set In this case no ACK clock occurs after data transmission When the bit is set to 1 the ACK clock mode is set and the master generates an ACK clock upon completion of each 1 byte data transmission The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock make SDA HIGH and receives the ACK bit generated by the data receiving device Figure 2 8 4 shows the 12 clock control register Note Do not write data
83. address and this becomes the actual address These modes are used for referencing subroutine tables and memory tables The index registers which have increment decrement comparison and data transfer functions are also used as simple accumulators 2 2 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 1 Central processing unit 2 1 3 Stack pointer S The stack pointer is an 8 bit register used for interrupts and subroutine calls The stack area can be assigned into the internal RAM The internal RAM of M37221M6 XXXSP FP is assigned in the zero page and the page 1 The both area can use for the stack area The stack area is specified with the CPU mode register address OOFBs e At reset the stack area is specified to the page 1 automatically Note Storing data in the stack area fills the RAM area with stored data in order therefore make sure the depth of interrupt levels and the subroutine nesting The stack area and stack pointer S should be specified in the initialization of software When the stack area is specified to 1 even if the value of stack pointer is over 0016 stack address is 010016 the stack area value never change to 0 automatically Therefore in this case change the stack area value by software CPU Mode Register b7 b6 656463 6261 60 uae CPU mode register CPUM CM Address 00FB16 EL ue Tee TR E Fix these bits to 0 Stack page selection 0 0 page Note Ww
84. at sub addresses 00 to 1316 2 Tuning and search related keys CH Table 5 5 1 Data setting at tuning and searching UP DOWN key CH direct selection key input Sub address Bit Data When tuning the color system data refer to 02 TRP Table 5 5 10 is set according to the determination result of the color system by DBF the status data register refer to Table 5 5 1 D1 DFA Also the corresponding data is set when the 0616 00 D1 DL TIME color system search related keys are input However note that the above mentioned setting is valid only when setting AUTO bit 5 at sub address 0616 write data to 0 When setting to 1 the data is automatically set inside the M52340SP When tuning the data is set as shown in Table 5 5 1 3 Volume UP DOWN key input Table 5 5 2 Data setting at volume UP DOWN key When the volume up down key is input the input data is set as shown in Table 5 5 2 Sub address Bit Data 0316 AUDIO 4 Screen size related keys input Table 5 5 3 Data setting at screen size related When the screen related keys are input on keys input TVs with various screen sizes wide aspect Sub address Data TV etc the screen size data and position 09 6 H PHASE data is set as shown in Table 5 5 3 Also the data of each frequency 50 Hz or 60 Hz is occasionally held 5 Picture data control key and Picture Table 5 5 4 Data setting at picture data
85. bit registers The other five registers the accumulator A index register X X index register Y Y stack pointer S and processor status register PS all have an 8 bit configuration Note The contents of registers above except the following are indeterminate after a hardware reset Therefore initialize these registers by software Interrupt disable flag of the processor status register 1 program counter the contents of addresses FFFE s and FFFF e Figure 2 1 1 shows the registers configuration diagram of M37221M6 XXXSP FP Accumulator A Index Register X X Index Register Y Y Stack Pointer S Program Counter PC Processor Status Register PS Carry Flag Zero Flag Interrupt Disable Flag Decimal Operation Mode Flag Break Flag X Modified Operation Mode Flag Overflow Flag Negative Flag Fig 2 1 1 Registers configuration diagram 2 1 1 Accumulator A The accumulator is the central register of the microcomputer and 8 bit register This general purpose register is used with considerable for arithmetic operations data transfer temporary clearing condition judgments etc 2 1 2 Index register X X index register Y Y The M37221M6 XXXSP FP has the index register X and the index register Y both of which are 8 bit registers In the addressing modes which use these index registers the register contents are added to the specified
86. box Do you set FF e in the shaded area 2 Yes Do you write the ASCII codes that indicates the product name of 37221 6 to addresses 000016 to 16 2 Character ROM 1 a Character ROM 2 a Character ROM 1 b Yes 2 Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form 42P4B for M37221M6 XXXSP 42P2R A for M37221M6 XXXFP and attach to the mask ROM confirmation form 3 Comments 1 3 7220 Group User s Manual 6 71 APPENDIX 6 11 Mask ROM ordering method GZZ SH09 46B lt 52 0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M6 XXXSP FP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 16 to 000 16 store the product name and addresses 10000 16 to 11FFF 6 store the character pattern If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form the ROM processing is disabled Write the data correctly 1 Inputting the name of the product with the ASCII code Address Address ASCII codes 37221 6 are listed on the right 000016 40 1 000816 The addresses and data are in hexadecimal notation 000116 3 33 1 000916 000216 7 37 16 000 1 000316 2 232 16 000816 000416 2 23216 0
87. character is determined based on the address in the CRT display ROM in which that character data is stored Assume that 1 character data is stored in addresses 10XX0 e to 10 XX denotes 0016 to 7F e and 10YYO e to 10YYF e YY denotes XX 80016 then the character code is In other words a character code is constructed with the low order second and third digits hexadecimal notation of the 5 digit address 1000016 to 107FFis where that character data is stored A character code is YY e in addresses 1100016 to 11FFF e Table 2 11 3 shows the character code table Table 2 11 3 Character code table be omitted partly Character code Character data stored address Left side 8 dots Right 4 side 8 dots 00 6 1000016 to 1000F e 10800 to 1080F e 01 6 1001016 to 1001F e 1081016 to 1081F e 0216 1002016 to 1002F e 1082016 to 1082F e 03 6 1003016 to 1003F e 1083016 to 1083F e 107 0 to 107 6 10FEO0 e to 10FEF e 7Fi6 107F0 e to 107EF e 10FF0 e to 10FFF e 80 6 1100016 to 1100F e 118001 to 1180F e 81 6 1101016 to 1101F e 118106 to 1181F e FDie 117D0 e to 117DF e 11FDO0 e to 11FDF e FEt6 117E0 e to 117 1 11FEO0 e to 11FEF e 117F0 e to 117EF e 11FF0 e to 11FFF e 7220 Group User s Manual 2 79 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 CRT display RAM addresses 060016 to 06876 CRT display RAM is assigned to addr
88. clock selection register sse nennen 6 44 Fig 6 7 22 CRT A D control register 1 menm 6 45 Fig 6 7 23 A D control register 2 i t terr tree t tees ene E ree 6 45 6 7 24 Timer 12 mode register ted daa Ra sic daa naa 6 46 Fig 6 7 25 Timer 34 mode register 6 47 Fig 6 7 26 Interrupt input polarity emm 6 47 Fig 6 7 2 GPU mode tegistet eec eere ta eaten ed Pere n ose er die 6 48 7220 Group User s Manual ix List of figures Fig 6 7 28 Interrupt request register 1 6 48 Fig 6 7 29 Interrupt request register 2 6 49 Fig 6 7 30 Interrupt control register a 0000 nnns 6 49 Fig 6 7 31 Interrupt control register 2 6 50 Fig 6 7 32 ROM correction enable 6 50 Fig 6 8 1 block diagram T utei dete Renten tei be e eR pent 6 51 Fig 6 8 2 pin block diagram 2 222 6 52 7220 Group User s Manual List of tables List of tables CHAPTER 1 OVERVIEW Table 1 1 1 Performance overview 1 3 Table 1 1 2 Performance overview 2 ennemi nennen nnns renes 1 4 Table 1 3 1 Pin description 1 1 7 Table 1 3 2 Pin description 2 e etit deste e e
89. contents of mem ory specified by the addressing mode The re sult is stored in the memory specified by index register X 7220 Group User s Manual 6 57 APPENDIX 6 9 Machine instruction table Addressing mode Processor status register 6 58 7220 Group User s Manual APPENDIX 6 9 Machine instruction table Addressing mode at the address indicated by the stack pointer and decrements the contents of stack pointer by 1 Saves the contents of the processor status reg ister in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1 Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer increments the contents of stack pointer by 1 and restores the processor status register from the mem ary at the address indicated by the stack pointer Shifts the contents of the memory or accumula tor to the left by one bit The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit Shifts the contents of the memory or accumula tor to the right by one bit The low order bit is shifted into the carry flag and the
90. contents of vertical position register for next display Notes 1 Set the second and later block 1 display start positions of block 1 to be lower than display position of the last block 2 2 The CRT interrupt request does not occur at the end of display when the block is not displayed In other words if a block is set to off display with the display control bit of the CRT control register at address O0EA e a CRT interrupt request does not occurs refer to Figure 2 11 14 Block 1 on display Block 2 on display 22 On display CRT interrupt request occurs at the end of block display CRT interrupt request Fig 2 11 13 Generation timing of CRT request interrupt Off display CRT interrupt request does not occur at the end of block display CRT interrupt request Fig 2 11 14 Display state of blocks and occurrence of CRT interrupt request 2 84 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 6 Character border function An border of 1 clock 1 dot equivalent size can be added to a display character in both horizontal and vertical directions The border is output from pin OUT 1 In this case set bit 5 of a color register to 0 character is output Border can be specified each block by the border selection register address OOE5 e Table 2 11 6 shows the relationship between the set values of the border selection register and th
91. control memory switching key input key and picture memory switching When changing picture data the data is set key input to the corresponding write data register as SUP addes Data shown in Table 5 5 4 04 6 DO to D5 SHARPNESS 0516 DO to 06 CONTRAST 07 6 DO to D6 TINT 08 6 DO to D6 COLOR 0 DO to 06 BRIGHT 5 34 7220 Group User s Manual 6 7 8 9 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP Data setting when changing AFT auto fine tuning state To change the state of auto fine tuning at presetting CH and ordinary tuning the bit is set as shown in Table 5 5 5 Data setting when changing audio mute state When the audio mute key is input the bit is set as shown in Table 5 5 6 If it is necessary to delete the sound while tuning with the tuning key input or presetting CH the bit is set as shown in Table 5 5 6 Data setting when changing video mute state When muting the video on screen while tuning with the tuning key input the bit is set as shown in Table 5 5 7 Data setting when adjusting white balance When adjusting the TV picture in the factory set the data shown in Table 5 5 8 to ready the service mode for adjusting the white color Table 5 5 5 Data setting when changing AFT state Sub address Bit Data 0416 06 DEFEAT Table 5 5 6 Data setting when changing audio mute state Sub address Bit Data A MUTE Ore 56
92. disable the INT1 interrupt by using an interrupt enable bit and interrupt disable flag 1 Timer 4 interrupt Timer 4 value is counted down Timer 4 interrupt request occurs when the count source next to 0016 is input f Xin 4096 interrupt A f Xin 4096 interrupt request occurs for a f Xin 4096 period This interrupt is valid when the PWM count source is supplied when bit 0 of PWM output control register 1 is 0 Vsync interrupt A Vsync interrupt request occurs synchronized with the vertical synchronous signal which is input to pin Vsvwc Positive polarity When the Vsync input polarity is positive the Input port control register bit 1 at address 00 6 is 0 an interrupt request is generated by a rising edge LOW to HIGH Negative polarity when the polarity is negative an interrupt Input transition of the Vsync input conversely request is generated by a falling edge VSYNC input pin Interrupt request is generated Fig 2 5 1 Vsync interrupt generation timing 7220 Group User s Manual 2 27 FUNCTIONAL DESCRIPTION 2 5 Interrupts 7 8 9 Timer 3 interrupt Timer 3 value is counted down Timer 3 interrupt request occurs when the count source next to 0016 is input Timer 2 interrupt Timer 2 value is counted down Timer 2 interrupt request occurs when a count source next to 0016 is input Timer 1 interrupt Timer 1 value is counted down Timer 1
93. display scanning lines 0 0 Minimum 1 Tc 1 line 0 1 Medium 2 Tc 2 lines 1 0 Large 3 Tc 3 lines 1 1 This is not available Note The display start position in the horizontal direction is not affected by the character size In other words the horizontal display start position is common to all blocks even when the character size varies with each block refer to Figure 2 11 9 7220 Group User s Manual 2 77 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 3 Memory for display There 2 types of display memory CRT display ROM addresses 10000 e to 11FFF e used to store masked character dot data and CRT display RAM addresses 0600 e to 06B7 e used to specify the colors and characters to be displayed Each type of display memory is described below 1 CRT display ROM addresses 10000 to 11FFF CRT display ROM stores dot pattern data for characters to be displayed When actually displaying characters stored in this ROM it is necessary to specify them by writing the character code inherent to each character code determined based on the addresses in CRT display ROM into CRT display RAM CRT display ROM has a capacity of 8 K bytes Since 32 bytes are required for 1 character data the ROM can stores up to 256 kinds of characters CRT display ROM is broadly divided into 2 areas The vertical 16 dots X horizontal left side 8 dots data of display characters are stored in addresses 1000016 to 107FF e and 11000
94. flag BB 0 Bus free 1 Bus busy 6 7 Communication mode b7 b6 specification bits 0 0 recieve mode 0 1 Slave transmit mode 1 0 Master recieve mode 1 1 Master transmit mode Note These bits and flags can be read out but cannnot be written Fig 6 7 9 status register Address 000916 6 34 7220 Group User s Manual APPENDIX 6 7 Control registers 12 Control Register b7 b6 65 64 b2 61 bO 12C control register 510 address 00DA 16 Bit counter Number of transmit recieve bits BCO to o o 0 0 0 0 LM OO O 4 Data format selection bit 0 Addressing mode ALS 1 Free data format 5 Addressing format selection 0 7 bit addressing format bit 10BIT SAD 1 10 bit addressing format 3 PC BUS interface use 0 Disabled enable bit ESO 1 Enabled 6 7 Connection control bits b7 b6 Connection port between FC BUS interface 0 0 None and ports 1 SCL1 SDA1 BSELO BSEL1 0 SCL2 SDA2 1 SCL1 SDA1 SCL2 SDA2 Note When using ports P11 P14 as FC BUS interface the output structure changes automatically from CMOS output to N channel open drain output However set the port direction register to 1 output mode Fig 6 7 10 control register Address 000 16 7220 Group Users Manual 6 35 APPENDIX 6 7 Control registers 2 Clock Control Register 67 b6 65 64 63 b2 b1 00
95. in decimal arithmetic operation 8 6 5 Fig 6 3 5 Execution of BBC or BBS 6 5 Fig 6 3 6 Sequence for switching an external interrupt detection 6 6 Fig 6 3 7 Initialization for serial 6 6 Fig 6 3 8 Relation between timer values and their values read timer setting value 6 7 Fig 6 3 9 Relation between timer values and their values read when two timers connected in series timers 1 and 2 are connected timer 1 setting value 2 timer 4 setting value et PR REDI HERE A HE SE be E Rast e dant 6 7 Viii 7220 Group User s Manual List of figures Fig 6 4 1 Wiring for RESET input 6 11 Fig 6 4 2 Wiring for clock pin nennen neret 6 11 Fig 6 4 3 Wiring for CNVss pin nni nennen nnne nennen 6 12 Fig 6 4 4 Wiring for Ver pin of One Time PROM and EPROM version 6 12 Fig 6 4 5 Bypass capacitor across Vss line and Voc 6 13 Fig 6 4 6 Analog signal line and resistor and capacitor 6 13 Fig 6 4 7 Wiring for large current signal line enn 6 14 Fig 6 4 8 Wiring for signal line where potential levels charge frequently 6 14 Fig 6 4 9 Vss
96. into the 12 clock control register during transmission If data is written during transmission the 2 clock generator is reset so that data cannot be transmitted normally 7220 Group User s Manual 2 51 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 Clock Control Register b7 b6 b5 64 b3 b2 61 60 ER ERI 12C clock control register 52 address 0008 16 Standard clock High speed CCR4 CCRO mode clock mode Setup disabled 400 SCL mode 55 Standard specification bit High speed clock mode FAST MODE ACK bit 0 is returned pie aqu ACK clock bit 0 clock Note At 4000kHz in the high speed clock mode the duty is as below 0 period 1 period 3 2 In the other cases the duty is as below 0 period 1 period 1 1 Fig 2 8 4 clock control register 2 52 7220 Group User s Manual 4 FUNCTIONAL DESCRIPTION 2 8 Multi master 12 interface lC Control Register 510 address 00DA16 The 126 control register address 00DA e controls the data communication format B Bits 0 to 2 Bit counter BCO BC2 These bits decide the number of bits for the next 1 byte data to be transmitted An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted When a START condition is received these bits become 00
97. is output same as a character or border output from the OUT1 pin Do not set COns 0 and 0 2 When only 1 and COns 0 there is output from the OUT2 pin 3 The portion A in which character dots are displayed is not mixed with any TV video signal 4 The wavy lined arrows in the Table denote video signals 5 0103 X 00r1 7220 Group User s Manual 2 83 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 5 Multi line display The M37221M6 XXXSP FP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions In addition it can display up to 16 lines by using a interrupt A CRT interrupt request occurs at which display of each block has been completed In other words character display of a certain block starts when a scanning line reaches the display position specified by vertical position registers for that block and an interrupt occurs when the scanning line exceeds the block For display it is necessary to enable the interrupt by clearing the interrupt disable flag to 0 and setting the CRT interrupt enable bit bit 4 at address OOFE e to 1 In a CRT interrupt processing routine the character data and vertical position of the block of which display has been completed the display as CRT interrupt cause is completed is then replaced with the character data contents of CRT display RAM and display position
98. lt State immediately after reset gt 0 0 immediately after reset 1 immediately after reset 2 Undefined immediately after reset Address Register ate immediately after reset o 016 Port PO C116 Port PO direction register DO C216 Port P1 P1 C316 Port P1 direction register D1 C416 Port P2 P2 C516 Port P2 direction register D2 C616 Port P3 P3 C716 Port P3 direction register D3 C816 C916 CA16 Port P5 P5 16 Port P5 direction register D5 16 CD16 Port P3 output mode control register P3S CE16 DA H register DA H CF16 DA L register DA L 0016 PWMO register PWMO 0116 PWM register PWM1 D216 PWMe register PWM2 0316 register PWM3 0416 PWMA register PWM4 0516 PWM output control register 1 PW 0616 PWM output control register 2 PN D716 0816 0916 1 1 DC16 Serial mode register SM 0016 Serial I O regsiter SIO DE16 DA1 conversion register DF1e DA conversion register DA2 Fig 4 5 17 Internal state immediately after reset 1 4 26 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description Area addresses E016 to FF 6 State immediately after reset gt 0 0 immediately after reset 1 1 immediately after reset 2 Undefined immediately after reset Addre
99. nnie Xan 5 0116 X 0016X nnie X 1 Writing Value Overflow signal f Interrupt request Fig 2 6 2 Timer overflow timing 1 Timer 1 Timer 1 can select one of the following count sources f Xin 16 f Xin 4096 This is a clock by f Xin 4096 interrupt and is valid only when PWM count source is supplied The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register address 00F 46 Timer 1 interrupt request occurs at timer 1 overflow 2 Timer 2 Timer 2 can select one of the following count sources f Xin 16 Timer 1 overflow signal External clock from pin 24 2 The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register address OOF 416 When timer 1 overflow signal is a count source for timer 2 timer 1 functions as 8 bit prescaler Timer 2 interrupt request occurs at timer 2 overflow 7220 Group User s Manual 2 35 FUNCTIONAL DESCRIPTION 2 6 Timers Timer 12 Mode Register 6766 656463 6261 60 Timer 12 mode register T12M Address 007416 Timer 1 count source 0 16 selection bit T12MO 1 f XIN 4096 Timer 2 count source 0 Internal clock selection bit 1 External clock from P24 TIM2 pin bit T12M2 1 Count stop T12M3 1 Count stop Es count 0 f XIN 16 M source selection bit 1 d overflow T12M4 5 Fix this bit to 0 6 7 Nothing is ass
100. out the values are 0 Fig 6 7 2 Port P3 direction register Address 00C716 6 30 7220 Group User s Manual APPENDIX 6 7 Control registers Port P5 Direction Register b7 b6 b5 b4 b3 b2 61 00 EN Port P5 direction register 05 Address 00 1 0 CRT output R RW 1 Output P52 1 0 CRT output G R W 1 Output port P53 i 0 CRT output 1 Output 54 i 0 CRT output OUT1 Riw 1 Output port P55 6 7 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 6 7 3 Port P5 direction register Address 00 16 Port P3 output mode control register b7 b6 b5 b4 b3 b2 b1 bO Port output mode control register address 00 16 Aer reset 3 output structure 0 CMOS output selection bit P30S 1 N channel open drain output 1 3 1 output structure 0 CMOS output selection bit P31S 1 N channel open drain output 2 3 Fix thes bits to 0 Jes note TNR to When these bits are read out the values are 0 7 R R R Note M37220M3 XXXSP FP R Ww Ww Ww Ww 2 1 output enable bit 0 P3o input output 1 DA1 output 3 2 output enable bit 0 P31 input output 1 DA2 output Fig 6 7 4 Port P3 output mode control register 4 Nothing is assigned These bits are write disable bits Address 00CD16 7220 Group User s M
101. pattern on underside of an 6 14 Fig 6 4 10 Setup for ports 00 200000 nennen nnne enne enne 6 15 Fig 6 4 11 Watchidog timer by 6 16 Fig 6 5 1 Memory assignment of M37221M4 XXXSP and M37221M6 XXXSP FP 6 17 Fig 6 5 2 Memory assignment of M37221M8 XXXSP and M37221MA XXXSP 6 18 Fig 6 5 3 Memory assignment of M37220M3 XXXSP FP 6 19 Fig 6 6 1 SFR assignment including internal state immediately after reset and access characteristics 1 M37221Mx XXXSP FP 6 20 Fig 6 6 2 SFR assignment including internal state immediately after reset and access characteristics 2 37221 6 22 Fig 6 6 3 Memory map of 2 page register including internal state immediately after reset and access characteristics 3 only M37221M8 XXXSP M37221MA XXXSP 6 24 Fig 6 6 4 SFR assignment including internal state immediately after reset and access characteristics 4 M37220M3 XXXSP FP 6 26 Fig 6 6 5 SFR assignment including internal state immediately after reset and access characteristics 5 M37220M3 XXXSP FP 6 28 Fig 6 731 Port Pr Gir ction register ete ele te i aee aida 6 30 Fig 6 7 2 Port direction
102. priority than V SYNC interrupt And also be sure to disable the following interrupts VSYNC interrupt all interrupts with lower priority than V SYNC interrupt Enable state of multiple interrupts Timer 1 Pop the registers X Y A c7 Disable all interrupts ICON 1 and 2 contents Disable ICON2 multiple interrupts RETURN Fig 5 1 11 Flowchart of Vsync interrupt processing routine when setting multiple interrupts during VSYNC interrupt 5 12 7220 Group User s Manual APPLICATION 5 2 Notes on programming for OSD M37220M3 XXXSP FP 5 2 Notes on programming for OSD M37220M3 XXXSP FP The emulator MCU M37221ERSS is used for programming development with the M37220M3 XXXSP FP However the functions of the M37221ERSS are compatible with those of the M37221Mx XXXSP FP and therefore has some functions which the M37220M3 XXXSP FP does not have Note the following differences when programming using the M37220M3 XXXSP FP 5 2 1 Setting of color registers The color registers of M37220M3 XXXSP FP are different from those of M37221ERSS refer to Figures 5 2 1 and 5 2 2 Character background colors can be output when programming with the M37221ERSS but not with the M37220M3 XXXSP FP mask version This character background color program does not operate on the M37220M3 XXXSP FP and therefore it cannot output character background colors except character background colo
103. register Horizontal position register CO0 to Color registers 0 to 3 F VSYNC Vsync flag m MD Border selection register Multi line display start CRT clock selection register Initialization bit4 at address 00 16 lt 0 Disable only CRT interrupt CC address OOEA 16 000000002 All blocks display off P5D address 00CB 16 lt 000000002 Select R G B OUT1 address 00 16 lt 000000002 HSYNC VSYNC input polarity positive polarity input R G B OUT1 output polarity positive polarity output 000010002 red Color register 0 red 000000102 blue Color register 1 blue COO address OOE6 16 CO1 address OOE7 16 CO2 address 00 816 000011102 white Color register 2 white 000001102 cyan Color register 3 cyan CO3 address OOE9 16 Block 1 display RAM Display character blank of block 1 addresses 0600 16 to 061716 Character color no output of block 1 addresses 0680 16 to 069716 CV1 address 00 1 16 lt Vertical display start position of the 11th line block 1 Block 2 display RAM Display character blank of block 2 addresses 0620 16 to 063716 Character color no output of block 2 addresses 06 0 16 to 06 716 CV2 address 0022 16 Vertical display start position of the 12th line block 2 CS address 0024 16 lt 000000002 Character size minimum size MD address 0025 16
104. register For this reason even when changing only the high order 8 bits of the output data be sure to write the low order 6 bits data to the DA L register again Conversely when changing low order 6 bits only it needs to only write data to the DA L register and needs not write the high order 8 bit data again Select the output polarity by bit 2 of PWM output control register 2 address 00D6 e When setting to 0 a positive polarity is selected when 1 a negative polarity is selected 14 bit PWM is output from the D A pin by clearing bit 1 of PWM output control register 1 to 0 When setting to 1 pin D A functions as a 1 bit general purpose output port In this case it is possible to specify either HIGH output 1 or LOW output 0 output by bit 4 of PWM output control register 2 PWM Output Control Register 1 6766 b5b4b3 b2b1 b0 PWM output control register 1 PW Address 000516 LB After reset DA PWM count source Count source supply selection bit PWO Count source stop DA PN4 output i DA output R w selection bit PW1 PN4 output 2 POo0 PWMO output 0 POo output IW selection bit PW2 1 PWMO output PO1 PWM1 output 0 output w selection bit PW3 1 PWM1 output 4 PO2 PWM output 0 output w selection bit PW4 1 PWM2 output P03 PWM3 output 0 P03 output w selection bit PW5 1 PWMG output P04 PWM4 output 0 P04 output Riw selection bit P
105. register 2 address OOEF e Table 2 9 1 shows the Vre values corresponding to the set values above A D comparison starts by writing to A D control register 2 This voltage comparison needs for 16 machine cycles instruction X 8 The comparison result is stored in bit 4 of the A D control register 1 address OOEEis When the input voltage value is lower than the comparison voltage value bit 4 is cleared to 0 when the input voltage value is higher than the comparison voltage value bit 4 is set to 1 refer to Figure 2 9 2 7220 Group User s Manual 2 61 FUNCTIONAL DESCRIPTION 2 9 A D comparator Table 2 9 1 Relationship between contents of A D control register 2 and reference voltage Vre A D control register 2 Internal analog voltage bit 5 bit 4 bit 3 bit 2 bit 1 comparison voltage Vret 0 0 0 0 0 1 128Vcc 0 0 0 0 0 3 128Vcc 0 0 0 0 1 5 128 1 1 1 1 0 123 128 1 1 1 1 1 125 128 1 1 1 1 1 127 128 Control Register 1 67 66 65 64 b3 62 b1 60 A D control register 1 AD1 Address 00 16 o o o A D1 A D2 A D4 A D5 amp D6 Do not set ADMO ADM1 ADM2 OO aua 3 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Storage bit of comparison 0 Input voltage reference voltage Indeterminate
106. rennen 4 8 Fig 4 5 1 ACCESS 14 erede nete aee aad 4 10 Fig 4 5 2 Memory 4 11 Fig 4 5 3 Memory of SFR special function register 1 4 12 Fig 4 5 4 Memory map of SFR special function register 2 4 13 Fig 4 5 5 Interrupt request register 1 address 00 4 16 Fig 4 5 6 Interrupt control register 1 address 00 40 4 16 Fig 4 5 7 D A converter block 4 17 Fig 4 5 8 DA n conversion register addresses and OODF 16 4 18 Fig 4 5 9 Port output mode control register address OO0CDse 4 18 Fig 4 5 10 CRT display circuit block nnne 4 20 Fig 4 5 11 Example of display character data storing 4 21 Fig 4 5 12 Structure of CRT display 4 23 Fig 4 5 13 Border selection register addresses OOE5 6 4 24 Fig 4 5 14 Color register n addresses 00 6 to OOES916 4 24 Fig 4 5 15 CRT control register address 00 4 25 Fig 4
107. serial I O interrupt request bit enable bit to 1 2 FF Set serial interrupt enable bit to 1 DATA DD Write transfer data to serial 00 Write dummy data to register serial I O register As a result of the above processing 1 byte data is transferred from the transmit side to the receive side When the transmit operation is completed interrupts occur on both sides so that completion of the data transfer can be reported After that repeating the processing after the symbol w can transmit receive more data Fig 2 7 8 Serial data transmit receive processing sequence 2 46 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 8 Multi master 2 interface The multi master I C BUS interface is a serial communications circuit conforming to the Philips 05 data transfer format This interface offering both an arbitration lost detection and a synchronous functions is useful for the multi master serial communications Figure 2 8 1 shows a block diagram of the multi master I C BUS interface and Table 2 8 1 shows multi master I C BUS interface functions The M37220M3 XXSP FP does not have this function Table 2 8 1 Multi master I C BUS interface functions Item Function In conformity with Philips IIC BUS standard 10 bit addressing format Format 7 bit addressing format High speed clock mode Standard clock mode In conformity
108. serial parallel conversion register used for data transfer This register consists of 8 bit and can be used as both transmit and receive register Serial register is assigned to address 0000 Although data transfer is performed bit by bit it is possible to specify whether the data is transferred beginning with most significant bit MSB or least significant bit LSB by using bit 5 of the serial I O mode register 1 When bit 5 of the serial mode register is 0 Receive Data is received bit by bit beginning with the MSB bit 7 of the serial I O register Transmit Data is transmitted bit by bit beginning with the LSB bit 0 of the serial register 2 When bit 5 of the serial mode register is 1 Receive Data is received bit by bit beginning with the LSB bit 0 of the serial I O register Transmit Data is transmitted bit by bit beginning with the MSB bit 7 of the serial register 2 7 3 Clock source generating circuit The clock source generating circuit can select oscillation frequency divided by 4 16 32 and 64 as the internal clock Also it can select an external clock the external clock is selected immediately after reset Bit 2 of the serial mode register specifies internal clock or external clock When bit 2 of the serial mode register is set to 0 an external clock is selected when 1 an internal clock is selected When selecting an internal clock set the division Tab
109. the slave reception mode with ALS 1 and immediately after completion of address data reception B Bit 5 Bus busy flag BB This bit indicates the status of use of the bus system When this bit is set to 0 this bus system is not busy and a START condition can be generated When this bit is set to 1 this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function Note This flag can be written by software only in the master transmission mode In the other modes this bit is set to 1 by detecting a START condition and set to 0 by detecting a STOP condition When the ESO bit of the control register address 00 is 0 and at reset the BB flag is kept in the 0 state B Bit 6 Communication mode specification bit transfer direction specification bit TRX This bit decides the direction of transfer for data communication When this bit is 0 the reception mode is selected and the data of a transmitting device is received When the bit is 1 the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL When the ALS bit of the I C control register address OOF9 e is 0 in the slave reception mode is selected the TRX bit is set to 1 transmit if the least significant bit R W bit of the address data transmitted by the master is 1
110. to 1 the 10 bit addressing format is selected all the bits of the 12 address register are compared with address data Bit 6 and 7 Connection control bits between I C BUS interface and ports BSELO BSEL1 This bits controls the connection between SCL and ports or SDA and ports When using the ports as multi master I C BUS interface set the corresponding bits of port P1 direction register to 1 output mode Figure 2 8 5 shows the connection port control by BSELO and 1 Figure 2 8 6 shows the control register 1 BSELO O SCLI P1 i SCL 1 BSEL1 Los 6 SCL2 P12 1 BSELO Multi master I C BUS interface O SDAI P1s 0 1 BSEL1 0 SDA2P14 SDA Fig 2 8 5 Connection port control by BSELO and BSEL1 7220 Group User s Manual 2 53 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 12 Control Register 67 b6 b5 64 b3 b2 b1 60 I C control register 510 address 00DA 16 Bit counter Number of transmit recieve to BC2 0 0 0 0 1 1 1 1 Wm 0 3 lC BUS interface use Disabled enable bit ESO Enabled 4 Data format selection bit Addressing mode ALS Free data format Addressing format selection gt 7 bit addressing format bit 10 SAD 10 bit addressing format 6 7 Connection control bits b7 b6 Con
111. to be displayed is determined by the line counter value Interrupt control registers 1 2 CS Character size register HR Horizontal position register Line counter Counter RAM for line counting CV1 CV2 Vertical position registers 1 2 CRT_ICON1 CRT Back for interrupt control registers 1 2 during CRT interrupt CRT interrupt processing routine Accumulator Index register X T c Index register Y D c0 modified operation mode flag CRT ICON1 lt 1 Decimal operation mode flag CRT ICON2 lt ICON2 address OOFE 16 00100001 2 k_ Enable Timer 1 interrupt and ICON address OOFF 16 lt 0000000027 Vsync interrupt c0 Push registers X Y A lt Specify jump destination by Line counter value Line counter 0 Block 1 display RAM Block 2 display lt Block 2 display lt Display character of block 1 the 1st line Display character of block 2 the 2nd line Display character of block 2 the 12th line Character color of block 1 the 1st line Character color of block 2 the 2nd line Character color of block 2 the 12th line CV1 Vertical display start position CV2 lt Vertical display start position CV2 lt Vertical display start position of the 1st line block 1 of the 2nd line block 2 of the 12th line block 2 Set CS HR Set CS HR Set CS HR Line counter 1 Line counter 212 Save the value of Line counter in interna
112. unused pins 1 2 3 6 10 Proper termination of unused pins Output ports Open B Input ports Connect each pin to Vcc or Vss through each resistor of 1 kW to 10 kW Ports that permit the selecting of a built in pull up or pull down resistor can also use this resistor As for pins whose potential affects to operation modes such as pins CNVss INT or others select the Vcc pin or the Vss pin according to their operation mode ports Set the I O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 to 10 Set the ports for the output mode and open them at L or H When opening them in the output mode the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset Thus the potential at these pins is undefined and the power source current may increase in the input mode With regard to an effects on the system thoroughly perform system evaluation on the user side Since the direction register setup may be changed because of a program runaway or noise set direction registers by program periodically to increase the reliability Incorrect termination of unused pins E input ports and I O ports Do not open in the input mode Reason The power supply current may increase depending on the first stage circuit An effect due to noise may be easily produced as compared with proper terminat
113. write processing routine and the read processing routine The START condition the STOP condition and the data output processing routine are used as the common processing routine A A K Slave address A A Write start RAM WRITEDATA NO ACK COUNTER WRITE DATA COUNTER WRITEDATA Flag F_ACK lt Slave address W BA 16 WRITE DATA COUNTER 1 number of write bytes NO ACK COUNTER 0 START condition Data output Yes WRITEDATA lt Sub address Data output STOP condition Yes ACK WRITE DATA No not yet NO ACK COUNTER _ ACK COUNTER 1 COUNTER E07 Yes end O ACK COUNTER gt 3 try 3 times Yes give up STOP condition WRITEDATA Write data Data output WRITE DATA COUNTER WRITE DATA COUNTER 1 Fig 5 5 4 Flowchart of write processing routine 5 28 7220 Group User s Manual APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 2 Read processing routine 08 FF 3 See 1 Slave address C W A016 Sub address Cls RAM WRITEDATA NO ACK COUNTER Read start READ DATA COUNTER Flag F_ACK To M52340SP See note 2 to other devices cf E2PROM Yes sub address is not necessary at reading WRITEDATA Slave address
114. 0 Same output as character output Indeterminate W border selection bit MD20 1 Border output When these bits are read out the values are 0 Fig 5 2 3 Border selection register M37220M3 XXXSP FP 5 2 3 Number of display characters The M37221ERSS can display up to 24 characters in each block However the M37220M3 XXXSP FP can display only up to 20 characters in each block Note this when programming using the M37220M3 XXXSP FP 5 14 7220 Group User s Manual APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 5 3 Usage example of ROM correction function M37221M8 MA XXXSP Application example using the ROM correction function is described below In this example it is assumed that the program must be changed by specifications modification after completion of ROM mask Also E PROM is connected to this system 5 3 1 Connection example I2C BUS dS 00C8IN dc L008lN9IN dS 00CVIN LEZZEN lt E2PROM gt lt Microcomputer gt Fig 5 3 1 Connection example 5 3 2 Correction example The following is an example when 2 addresses 2 blocks of ROM are corrected 1 Correction example 1 Program before correction Correction program Address Machine Description style Description style instructions block 1 120 900 SARE LDA 00 SN NE New AMEN SERIA 4 NETS Nosca pee m gt NEN
115. 00 16 000516 1 3 1 16 000016 000616 40 46 000E16 000716 6 3 6 16 000 16 2 the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2 see the next page and on 2 3 6 72 7220 Group User s Manual For the character ROM data 22D FF FF FF FF FF FF FF o o o jo o o o GZZ SH09 46B 5200 gt 740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC The structure of character ROM divided of 12 X16 dots font Example Example Character code 1 16 101A016 to 101AF 6 Character 1 lt bz be bs bs be b bo Example 0016 0416 i 0416 16 16 1116 1116 1116 2016 2016 4016 4016 4016 0016 0016 3 3 7220 Group User s Manual Character N 109 016 to 109AF 6 Note Write the character code 00 16 to 7 16 to addreses 1000016 to 10FFF Write
116. 00FE16 Timer 1 interrupt 0 Interrupt disabled enable bit TM1E 1 Interrupt enabled 1 Timer 2 interrupt 0 Interrupt disabled R W enable bit TM2E 1 Interrupt enabled 2 Timer 3 interrupt 0 Interrupt disabled Riw enable bit TM3E 1 Interrupt enabled 3 Timer 4 interrupt 0 Interrupt disabled RW enable bit TM4E 1 Interrupt enabled 4 CRT interrupt enable 0 Interrupt disabled RW bit CRTE 1 Interrupt enabled i 5 5 interrupt 0 Interrupt disabled Riw enable bit VSCE 1 Interrupt enabled i Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 7 INT3 interrupt 0 Interrupt disabled RiW enable bit IT3E 1 Interrupt enabled i Fig 4 5 6 Interrupt control register 1 address 00FE16 4 16 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description 4 5 5 D A converter M37220M3 XXXSP FP has 2 D A converter with 6 bit resolution Figure 4 5 7 shows the D A converter block diagram Data bus DA1 conversion register 6 address O0DE 16 Resistor ladder P30 A D5 DA1 Fig 4 5 7 D A converter block diagram D A conversion is performed by setting the value in the DA conversion register The result of D A conversion is output from the DA pin by setting 1 to the DA output enable bit of the port P3 output mode control register bits 2 and 3 at address 00 16 The output analog v
117. 02 and the address data is always transmitted and received in 8 bits B Bit 3 PC BUS interface use enable bit ESO This bit enables usage of the multi master 805 interface When this bit is set to 0 the use disable status is provided so the SDA and the SCL become high impedance When the bit is set to 1 use of the interface is enabled When ESO 0 the following is performed 1 0 and AL 0 are set they are bits of the status register at address OOF819 e Writing data to the data shift register address 00D7 e is disabled Bit 4 Data format selection bit ALS This bit decides whether or not to recognize slave addresses When this bit is set to 0 the addressing format is selected so that address data is recognized When a match is found between a slave address and address data as a result of comparison or when a general call refer to 5 lC Status Register bit 1 is received transmission processing can be performed When this bit is set to 1 the free data format is selected so that slave addresses are not recognized B Bit 5 Addressing format selection bit 10BIT SAD This bit selects a slave address specification format When this bit is set to 0 the 7 bit addressing format is selected In this case only the high order 7 bits slave address of the address register address 0008 are compared with address data When this bit is set
118. 0316 ROM correction function 1 Correction code 1 BN 00416 ROM correction function Correction code 2 SX EGG 00516 ROM correction function Correction code 3 ASM 00616 ROM correction function 1 Correction code 4 NN 5 00716 correction function 1 Correction code 5 00816 correction function 1 Correction code 6 ROM correction function 1 Correction code 7 5i ROM correction function 1 Correction code 8 N ROM correction function 1 NNCorrection code 9 NNNnnn 00 16 ROM correction function 1 Correction code 10 N N 000 ROM correction function 1 Correction code 11 QD IMP E126H NY O0E ROM correction function 1 Correction code OoF e ROM correction function 1 code J ROM correction function 1 Correction code 14 NOP see note ROM correction function 1 Correction code 15 EAH NOP ROM correction function 1 Correction code 16 EAH NOP ROM correction function 1 Correction code 17 EAH NOP ROM correction function 1 Correction code 18 EAH NOP ROM correction function 1 Correction code 19 NOP ROM correction function 1 Correction code 20 NOP ROM correction function 1 Correction code 21 NOP ROM correction function 1 Correction code 22 NOP ROM correction function 1 Correction code 23 NOP ROM correction function 1 Correction code 24 NOP
119. 0M3 XXXSP FP and M37221M6 XXXSP FP CHAPTER 5 APPLICATION This chapter describes usage and application examples of peripheral functions based mainly on setting examples of related registers CHAPTER 6 APPENDIX This chapter includes precautions for systems development using the microcomputer a list of control registers the mask ROM confirmation forms mask ROM version and mark specification forms which are to be submitted when ordering 2 Register diagram The figure of each register structure describes its functions contents at reset end attributes as follows CPU Mode Register i Bit attributes Note 2 b7b6 b5b4b3 626160 folol CPU mode register CPUM CM Address FB EN Hae page selection 0 0 page ee iW bit CM2 1 1 page ES Values immediately after reset release Note 1 Indeterminate Bit in which nothing is assigned Notes 1 Values immediately after reset release 0 0 after reset release 100061 after reset release ndeterminate after reset release 2 Bit attributes The attributes of control register bits are classified into 3 types read only write only and read and write In the figure these attributes are represented as follows WeeeeeeWrite sseeeeRead enabled W eeeeeeWrite enabled eeseesRead disabled eee Write disabled 2 0 can be set by software but 1 cannot be set Table of contents Table of contents
120. 1 address OOEE 16 ssseeeneennnn 2 62 Fig 2 9 3 A D control register 2 address 00 2 62 Fig 2 10 1 14 bit PWM DA block diagram nnns 2 63 Fig 2 10 2 8 bit PWM block 2 64 Fig 2 10 3 14 bit PWM output example f Xw 8 MHz 2 66 Fig 2 10 4 Pulse waveforms corresponding to weight of each bit of 8 bit PWM register 2 68 Fig 2 10 5 Example of 8 bit PWM enm eene rne 2 68 Fig 2 10 6 PWM output control register 1 address 00051 2 69 Fig 2 10 7 PWM output control register 2 address 00061 2 70 Fig 2 11 1 Structure of CRT display character 2 71 Fig 2 11 2 CRT display circuit block 2 2 2 2 22 00 2 72 Fig 2 11 3 CRT control register address 00 2 73 Fig 2 11 4 Count method of synchronous 9 2 74 Fig 2 11 5 Display eio Erie b e e 2 75 Fig 2 11 6 Vertical position register n addresses 00 116 and 00 216 2 76 Fig 2 11 7 Horizontal position register address 0 2 76 Fig 2 11 8 Character size register address 00 46 2 77 Fig 2 11 9 Display st
121. 1 high order ADHI ADHIGJADHIS 4 ADHI3ADHI2 ADH11 ADH10 21816 ROM correction address 1 low order ADL17 ADL16 ADL15 ADL14 ADL13 ADL12 ADL11 ADL10 21916 ROM correction address 2 high order ACH2 ADH2qADH29 ADH24 21 16 ROM correction address 2 low order 40127 ADL2G ADL2S ADL24 ADL21 ADL20 21B16 ROM correction enable register RCR Note Only M37221M8 XXXSP and M37221MA XXXSP have this area Fig 2 3 5 Memory map of 2 page register only M37221M8 XXXSP and M37221MA XXXSP 7220 Group User s Manual 2 15 FUNCTIONAL DESCRIPTION 2 3 Memory assignment 2 3 1 Internal The static RAM is assigned The internal RAM is used as a stack area for subroutine calls and interrupts as well as for storing data Both zero page and page 1 are used as a stack area At reset the page 1 is specified automatically Ordinary the stack pointer is set to the highest address in the internal RAM of the page 1 during initialization immediately after power on This stack pointer moves to lower addresses as the nesting depth increases therefore make sure the subroutine nesting and interrupt levels to prevent the stored data destroying necessary data in the RAM When the stack page is specified 1 if the value of stack pointer exceeds address 010016 the value of stack page never change to 0 automatically In this case set the stack page value to 0 and set the stac
122. 16 0316 0416 0516 0616 0716 0816 0916 16 0816 DC16 DD16 DE16 DF16 Register Port PO Port PO direction register D0 Port P1 P1 Port P1 direction register D1 Port P2 P2 Port P2 direction register D2 Port P3 P3 Port P3 direction register D3 Port P5 P5 Port P5 direction register D5 Port P3 output mode control register P3S DA H register DA H DA L register DA L PWMO register PWMO PWM1 register PWM1 2 register PWM2 PWMS register register PWM4 PWM output control register 1 PW PWM output control register 2 PN 2 C data shift register SO 2 C address register 500 2 C status register S1 2 C control register S1D 2 clock control register S2 Serial mode register SM Serial register SIO Bit allocation gt Function bit w No function bit Fix this bit to 0 do not write 1 1 Fix this bit 1 do not write 0 Bit allocation b7 PW7 PW6 PW5 PW4 PW3 PN3 7 05 04 03 SAD6 5405 SAD4 SAD3 MST TRX PIN AL BseLt BseLo Ai s psp FAST coral CCR3 sMe sM5 0 5 0016 0016 Fig 6 6 1 SFR assignment including internal state immediately after reset and access characteristics 1 M37221Mx XXXSP FP 6 20 7220 Group User s Manu
123. 1M4 XXXSP ROM 16 K bytes RAM 320 bytes M37221M6 XXXSP FP ROM 24 K bytes RAM 384 bytes M37221M8 XXXSP ROM 32 K bytes RAM 512 bytes M37221MA XXXSP ROM 40 K bytes RAM 640 bytes CRT ROM 8 K bytes CRT RAM 96 bytes Input Output ports POc P07 8 bit X 1 N channel open drain output structure can be used as PWM output pins INT input pins A D input pin P1o 15 17 4 bit X 1 CMOS input output structure be used as CRT output pin A D input pins INT input pin 1 14 4 bit X 1 CMOS input output structure can be used as multi master I C BUS interface P2 P21 2 bit X 1 CMOS input output or N channel open drain output structure be used as serial pins 2 gt 2 6 bit X 1 CMOS input output structure can be used as serial input pin external clock input pins P3o 2 bit X 1 CMOS input output or N channel open drain output structure can be used as A D input pins P32 1 bit X 1 N channel open drain output structure 3 P34 Input 2 bit X 1 can be used as CRT display clock pins 52 55 Output 4 bit X 1 CMOS output structure can be used as CRT output pins Serial I O 8 bit X 1 Multi master I C BUS interface 1 2 systems A D comparator 6 channels 6 bit resolution PWM output circuit 14 bit X 1 8 bit X 6 Timers 8 bit timer X 4 ROM correction function See note 32 bytes X 2 7220 Group User s Ma
124. 2 3 2 D A lowe Circuit current P1 P 14 0 to 6 Note 2 mA los Circuit current POc POs 0 to 1 Note 2 mA Circuit current P24 P27 0 to 10 Note 3 mA Pa Power dissipation 25 550 Operating temperature 10 to 70 Tstg Storage temperature 40 to 125 Notes 1 The total current that flows out of the IC must 20 mA max 2 The total input current to IC loL1 loL2 1013 must be 30 mA or less 3 The total average input current for ports P24 P27 to IC must be 20 mA or less 3 2 7220 Group User s Manual ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics Recommended operating conditions 10 to 70 Vcc 5 V 10 unless otherwise noted Symbol Parameter Min Typ Max Unit Vcc Power source voltage Note 4 During CPU CRT operation 4 5 5 0 5 5 V Vss Power source voltage 0 0 0 V HIGH input voltage POo P07 P10 P17 20 27 0 8 Voc V P3o P34 Sin Vsync RESET Xin OSC1 TIM2 INT1 INT2 INT3 HIGH input voltage SCL1 SCL2 SDA1 SDA2 0 7 Vcc V When using 2 05 LOW input voltage 0 0 1 1 20 25 0 0 4 V 4 Vue LOW input voltage SCL1 SCL2 SDA1 SDA2 0 0 3 V When using 2 05 LOW input voltage Vsync RESET
125. 2 40 NECNON 2 40 MEM RH 2 42 uM 2 42 OM 2 42 2 7 5 Serial data receive method when an internal clock is selected 2 43 2 7 6 Serial 1 0 data transmit method when an external clock is selected 2 44 Dicet 2 45 2 47 NEC 2 48 2 8 2 Multi master 12 interface related registers RM er ERE 2 49 a IMMUNE LUAM M 2 61 2 63 058 PWM Mr 2 70 displa mop TI Lee 2 71 El Qu uu t QU 2 74 A T 2 77 Memo E 2 78 Llc D NI et 2 82 M 2 84 2 85 H 2 86 2 11 8 Raster coloring 1 nnne 2 87 2 11 9 Clock for display 2 88 2 12 ROM correction functiony eeeeeeeeeeeee 2 89 2 13 Software runaway detect nennen nnn nnne 2 90 mun TM 2 91 auc E 2 91 2 93 NNNM 2 93 2 95 2 95 2 15 2 Internal state immediately after 2 96 R
126. 220 Group User s Manual 2 71 FUNCTIONAL DESCRIPTION 2 11 CRT display function OSC1 OSC2 VSYNC Address OOEA 16 CRT control register Display oscillation circuit Addresses 00 1 16 00E216 ____ Vertical position registers Address 00 416 Character size register Display position control circuit Address 16 Horizontal position register Address 00 516 Border selection register Display control circuit RAM for display 10 bits X 24 characters X ROM for display 2 lines 12 bits X 16 dots X 256 characters Addresses 00 6 16 to 00 916 Y Color registers Shift register 12 bits Address 00EC 16 CRT port control register Data bus B OUT1 OUT2 Fig 2 11 2 CRT display circuit block diagram 2 72 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function CRT Control Register 67 b6 65 64 63 b2 b1 60 CRT control register CC Address 00 16 Name Functions ____ After reset reset All blocks display control O All blocks display off 00 IW bit Note CCO All blocks display on Block 1 display control bit n Block 1 display off R m CC1 Block 1 display on Block 2 display control bit o Block 2 display off Riw CC2 Block 2 display on 3 Nothing is assigned These bits are write disable bits 2 When these bits are read out the v
127. 220M3 XXXSP FP M37221M6 XXXSP FP 0 05 PWMO PWM5 POs INT2 A D4 PO INT1 P1o No function OUT2 P1 No function SCL1 P12 No function SCL2 No function SDA1 14 No function SDA2 P1s x A D1 INT3 16 x A D2 P17 A D3 20 21 Sour P22 Sin P23 24 TIM2 P2s P27 A D5 DA1 A D5 A D6 DA2 A D6 P32 P33 OSC1 P34 x OSC2 P52 x R P53 G P54 B 55 OUT OUT1 It is the same as M37221M6 XXXSP FP 4 14 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description 4 5 4 Interrupts The M37220M3 XXXSP FP has 13 sources reset is included of interrupts Table 4 5 3 Interrupt sources vector addresses and priority Vector addresses Priority High order byte Low order byte HOANG 1 Reset Note FFFF e FFFE e Non maskable 2 CRT interrupt 6 FFFCie 3 INT2 interrupt Active edge selectable 4 INT1 interrupt FFF9 e FFF816 Active edge selectable 5 Timer 4 interrupt FFF5ie FFF4 e 6 f Xin 4096 interrupt FFF3 e FFF2 e 7 VSYNC interrupt FFF1 16 FFFOt6 Active edge selectable 8 Timer 3 interrupt FFEF 16 16 9 Timer 2 interrupt FFED e FFEC e 10 Timer 1 interrupt FFEB e FFEAte 11 Serial interrupt 916 FFE8 e 12 INTS3 interrupt FFE5 e FFE4t16 Active edge selectable 13 BRK instruction interrupt FFDF e FFDEte Note Reset are included in the table
128. 2cie ROM correction function 2 Correction code 7 o2Die ROM correction function 2 Correction code 8 BPL 02bE0H S O2Ew ROM correction function 2 Correction code 9 ROM correction function 2 Correction code 11 NOP see note ROM correction function 2 Correction code 12 EAH NOP EAH NOP EAH NOP ROM correction function 2 Correction code 13 ROM correction function 2 Correction code 14 ROM correction function 2 Correction code 15 EAH NOP ROM correction function 2 Correction code 16 EAH NOP ROM correction function 2 Correction code 17 EAH NOP ROM correction function 2 Correction code 18 EAH NOP ROM correction function 2 Correction code 19 EAH NOP ROM correction function 2 Correction code 20 ROM correction function 2 Correction code 21 ROM correction function 2 Correction code 22 A NOP ROM correction function 2 Correction code 23 A NOP ROM correction function 2 Correction code 24 EAH NOP ROM correction function 2 Correction code 25 EAH NOP ROM correction function 2 Correction code 26 EAH NOP ROM correction function 2 Correction code 27 EAH NOP ROM correction function 2 Correction code 28 EAH NOP ROM correction function 2 Correction code 29 EAH NOP ROM correction function 2 Correction code 30 4CH JMP YYXXH ROM correction function 2 Correction code 31 XXH gt eLreset Vector address to YYXXH 04516 ROM correction function 2 Correction code 32 YYH see note m I A
129. 3 etting of color nnnm 5 13 nens MI E i 5 14 RUNE 5 14 5 15 DM 5 15 5 15 5 17 5 19 535 Notes on 5 20 5 21 4 21 NEED 5 21 ocu mM d M 5 21 Dossenus MEM EE 5 22 4 4 General TOW CMA ce e d 5 23 n 5 26 SEDENT T 5 26 5 26 5 27 EA 5 28 5 5 5 Data setting according to key 5 34 5 5 7 Register 5 6 Application circuit example 5 45 5 6 1 Application circuit example 1 5 45 5 6 2 Application circuit example 2 5 46 7220 Group User s Manual iii Table of contents CHAPTER 6 APPENDIX PEINE 6 2 ae EE 6 3 a 6 4 6 4 6 5 on 6 5 6 6 6 3 5 Notes I Da Y 6
130. 34M3 Notes 1 HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more 2 When the external clock source is selected timers 2 and 3 are counted at a rising edge of input signal 3 In the stop mode or the wait mode external clock inputs TIM2 and TIM3 cannot be used Timer 4 latch 8 8 Timer 4 8 8 Fig 2 6 1 Timer 1 timer 2 timer 3 and timer 4 block diagram Timer 1 interrupt request Timer 2 interrupt request Reset STP instruction Timer 3 interrupt request Timer 4 interrupt request 2 34 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 6 Timers 2 6 1 Timer functions There are four timers Timer 1 Timer 2 Timer 3 Timer 4 and each timer has an 8 bit reload latch timers the count down type and when the timer latch value is the divide ratio is 1 1 0 to 255 When the valve is written to reload latch is also set to its timer simultaneously Timer value is counted down each rising edge of count source The timer overflows at the count next pulse after the count value reaches 0016 and the interrupt request occurs At the same time of timer overflow the reload latch value n is set reload to timer and timer continues to count down The divide ratio is 1 n 1 Make sure that set in the range 004 to FF e Count source 35 X
131. 37220M3 XXXSP FP 2 5 14 Fig 5 3 1 Connection example aaa enne nnne rennen nnns nnns 5 15 Fig 5 9 2 Correction example het te E ee ate alle entes 5 15 Fig 5 3 3 Correction example 2 4 nnne nnns 5 16 Fig 5 3 4 map when using ROM correction function 1 5 17 Fig 5 3 5 map when using ROM correction function 2 5 18 Fig 5 3 6 General flowchart when using ROM correction function 5 19 Fig 5 4 1 Connection example nnn neret ressent enne 5 21 Fig 54 2 Byte write timing esi eee PU RE ee pede erdt iners 5 22 Fig 5 4 3 Random address read timing enne nennen 5 22 Fig 5 4 4 Flowchart of write processing routine een 5 23 Fig 5 4 5 Flowchart of read processing routine enne 5 24 Fig 5 4 6 Flowchart of data output processing 5 25 Fig 5 51 Connection example e ierat errta e e nde De Ree e eae 5 26 Fig 5 5 2 Staus read enne eene nnne nennen nnne 5 27 Fig 5 5 3 Byte write timing aieo ini atann ia nennen 5 27 Fig 5 5 4 Flowchart of write processing 5 28 Fig 5 5 5 Flowchart of read
132. 37221 37221 8 i 00 1 11FFFi6 0218 ROM correction ROM correction memory O2FF memory RAM Block 1 addresses 02C0 16 to 02DF16 12 Block 2 addresses 02 016 to 02 16 02 016 Internal 033 16 Not used CRT display RAM 60016 Not used 96 bytes 0 for display See note 6006 800016 6B716 ROM ROM 40 K bytes 32 K bytes Internal ROM for for M37221MA 37221 8 65502 16 interrupt vector area FFFF16 65535 1FFFF16 131071 0 65280 Special page Note Refer to Table 2 11 4 Contents of CRT display RAM Fig 2 3 2 Memory assignment of M37221M8 XXXSP and M37221MA XXXSP 2 12 7220 Group User s Manual Area addresses C016 to DF 6 Bit allocation gt Name No 0 Function bit FUNCTIONAL DESCRIPTION 2 3 Memory assignment State immediately after reset gt 0 immediately after reset 1 1 immediately after reset function bit 2 Indeterminate immediately after reset Fix this bit to 0 do not write 1 Fix this bit to 1 do not write 0 Address Register Bit allocation State immediately after reset bO b7 50 016 2 116 Port PO direction register DO 0016 C216 Port P1 P1 2 C316 Port P1 direction register D1 0016
133. 4 to 117FF 6 the vertical 16 dots X horizontal right side 4 dots data of display characters are stored in addresses 1080016 to 10FFF e 1180016 to 11FFF e refer to Figure 2 11 10 Note however that the high order 4 bits of the data to be written to addresses 10800 to 10FFF e and 11800 to 11FFF e must be set to 1 by writing data FX e ES c c 10 016 11XX016 10XX016 80016 or 11XX016 80016 SS 10XXF 16 10XXF 16 or 80016 11XXF 16 or 11XXF 16 80016 Fig 2 11 10 Example of display character data storing form 2 78 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function The character code used to specify a display
134. 4B for M37221M8 XXXSP and attach to the mask ROM confirmation form 3 Comments 1 3 6 68 7220 Group User s Manual APPENDIX 6 11 Mask ROM ordering method GZZ SH11 58B lt 72 0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M8 XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 16 to 000 16 store the product name and addresses 10000 16 to 1122 216 store the character pattern If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form the ROM processing is disabled Write the data correctly 1 Inputting the name of the product with the ASCII code Address ASCII codes 37221 8 are listed on the right 000016 The addresses and data are in hexadecimal notation 000116 000216 000316 000416 000516 000616 000716 2 Inputting the character ROM Address 2 4 D 16 000816 3 33 16 000916 7 37 16 000 1 2 32 16 000 16 2 32 16 000C16 1 2 3 1 16 000016 M 2 4 D 16 000 16 8 2 38 16 000F 6 Input the character ROM data by dividing it into character ROM1 and character ROM2 see the next page and on 2 3 7220 Group User s Manual For the character ROM data 2 2D 1 FF FF 16 FF 16 FF 16 FF 16 FF 16 FF 16 6 69 APPENDIX 6 11 Mask ROM ordering method
135. 6 00000001 2 Enable only Timer 1 interrupt multiple ICON2 address OOFF 16 000000002 interrupts 0 Enable multipule interrupt set by steps Push registers X Y A Refer to 5 1 7 2 VSYNC interrupt processing routine Pass this F_VSYNC lt 0 process only CRTR bit 4 at address OOFE 16 0 once at CRTE bit 4 at address 00 16 1 Enable CRT interrupt display start address 00EA 16 0716 All blocks display on Line counter 2 erroneous multi line display Refer to 5 1 6 1 lt Vertical display start position of the 1st line block 1 CV2 lt Vertical display start position of the 2nd line block 2 CRTR bit 4 at address 00 16 0 Pop registers X Y A lt Disable all interrupts Setting Tor ICON1 Pop ICON 1 and 2 contents during multiple ICON2 ICON2 VSYNC interrupt Refer to 5 1 7 2 interrupts Note The multiple interrupt priority of this system RETURN interrupt is as below Timer 1 gt VSYNC gt CRT Fig 5 1 4 Flowchart of Vsync interrupt processing routine 5 4 7220 Group User s Manual APPLICATION 5 1 Example of multi line display 3 CRT interrupt processing routine The CRT interrupt processing routine executes the display character data setup routine for each line in order to perform multi line display The line
136. 6 and transmit is enabled 3 Transmit operation When transmit is enabled the serial counter value 07 e simultaneously the data of the serial register is transmitted from pin P2 i Sour in synchronization with falling edge of the transfer clock Transmission is performed according to bit 5 SM5 of the serial mode register When 5 5 is set to 0 data is transmitted from LSB bit 0 of the register and shifted to the right to low order bit every time new data is transmitted When SM5 is set to 1 data is transmitted from MSB bit 7 of the register and shifted to the left to high order bit every time new data is transmitted When all 8 bit data have been transmitted the serial interrupt request bit bit 2 of the interrupt request register 2 address is set to 1 Pin P2 Sour will be in after transmit operation has been completed Note programming note that the serial counter is set even by writing to the serial register with bit management instructions such as SEB and CLB 07 De Ds Da Ds D2 D Xj 07 De Ds 04 Ds 02 Di SW 07 De Ds D Do 0 _ When transmitting wee Em 07 De Ds D4 Ds 02 D1 00 UUU v ur MS Transfer clock Serial I O register Fig 2 7 5 Serial register when transmitting when SM5 0 2 44 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 7
137. 6 Color register 3 CO3 16 control register CC 16 port control register ED16 CRT clock selection register EE16 A D control register 1 AD1 control register 2 AD2 FO16 Timer 1 TM1 F116 Timer 2 TM2 2216 Timer 3 F316 Timer 4 TM4 F416 Timer 12 mode register T12M F516 Timer 34 mode register T34M PWM5 register PWM5 F716 F816 F916 Interrupt input polarity register RE FAi6 CPU mode register CPUM Interrupt request register 1 IREQ1 FD16 Interrupt request register 2 IREQ2 FE16 Interrupt control register 1 FF16 Interrupt control register 2 ICON2 Fig 2 15 3 Internal state immediately after reset 2 7220 Group Users Manual 2 97 FUNCTIONAL DESCRIPTION 2 15 Reset 2 Page Register Area addresses 21716 to 21816 State immediately after reset gt 0 0 immediately after reset 1 immediately after reset Indeterminate immediately after reset Address Register 21716 ROM correction address 1 high order 21816 correction address 1 low order 21916 ROM correction address 2 high order 21A16 ROM correction address 2 low order 21B16 ROM correction enable register RCR Fig 2 15 4 Internal state immediately after reset 3 only M37221M8 XXXSP and M37221MA XXXSP 2 98 7220 Group User s Manual FUNCTIONAL D
138. 6 P30 A D5 P32 17 P31 A D6 CNVss gt 18 RESET gt 19 OSC1 P33 20 TN OSC2 P34 Vss 21 US Vcc 2501 Outline 42P2R A Fig 1 2 2 Pin configuration top view 2 1 6 7220 Group User s Manual OVERVIEW 1 3 Pin description 1 3 Pin description The pin description is shown in Table 1 3 1 M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP Table 1 3 1 Pin description 1 Input Functions Output Vcc Power source Apply voltage of 5 V 10 typical to Vcc and 0 V to Vss Vss CNVss CNVss Connected to Vss RESET Reset input Input To enter the reset state the reset input pin must be kept at a L for 2 us or more under normal Vcc conditions If more time is needed for the quartz crystal oscillator to stabilize this L condition should be maintained for the required time Clock input Input This chip has an internal clock generating circuit To control generating frequency an external ceramic resonator or a quartz crystal oscillator is connected between pins and If an external clock is used Xour Clock output Output the clock source should be connected to the pin and the pin should be left open 0 port I O Port PO is 8 bit port with direction register allowing each bit PWMO to be individually programmed
139. 6 store the character pattern If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form the ROM processing is disabled Write the data correctly 1 Inputting the name of the product with the ASCII code Address ASCII codes 37221 4 are listed on the right 000016 The addresses and data in hexadecimal notation 000116 000216 000316 000416 000516 000616 000716 2 the character ROM Address M 4D 46 000816 3 233 16 000916 7 37 46 000A16 2 232 16 000 16 2 282 16 000 16 4 2 3 1 16 000016 40 46 000 16 34 16 000 16 Input the character ROM data by dividing it into character ROM1 and character ROM2 see the next page and on 2 3 6 66 7220 Group User s Manual For the character ROM data 2 2D 1 F F 16 FF 16 FF 16 FF 16 FF 16 FF 16 FF 16 GZZ SH10 10B 5980 gt 740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC The structure of character ROM divided of 12 X16 dots font Example Example Character code 1 1 101A016 to 101AF 6 gt AR Chara
140. 7 b6 65 b4 b3 b2 61 00 Color register n COn n 0 to 3 Addresses 00 6 16 to 002916 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 B signal output 0 No character is output Riw selection bit COn1 1 Character is output i G signal output 0 No character is output R selection bit COn2 1 Character is output R signal output 0 No character is output R 7 selection bit COn3 1 Character is output 6 7 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 5 2 2 Color register n M37220M3 XXXSP FP 5 2 2 Setting border selection register The M37220M3 XXXSP FP can output neither character background OUT nor border at the same time When setting the border selection bits bit 0 or 2 to 1 the border output takes over OUT setting of bit 5 of the color registers Therefore select either the character background output or the border output Border Selection Register b7 b6 65 64 63 b2 b1 00 Border selection register MD Address 00 5 16 Name Functions Alter reset Block 1 OUT output NN ____ Same output as character output iW border selection bit MD10 1 Border output Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 3 Nothing is assigned These bits are write disable bits to Block 2 OUT output
141. 716 F216 Timer 3 TM3 FFie F316 Timer 4 4 0716 F416 Timer 12 mode register T12M 2 3 1 T12M1 0016 F516 Timer 34 mode register T34M 34 5 T34M4 34 3 4 2 T34M1 0016 F616 PWM5 register 5 2 F716 2 F816 2 F916 Interrupt input polarity register RE RE4 0 0 0 0 0 0 0 16 PON a 0016 mode eaiser coum IJa ppi ofo 123 LET To To 16 Interrupt request register 1 IREQ1 VSCR TM2R TMAR 0016 FD16 Interrupt request register 2 IREQ2 S1R IT2R 0016 FE16 Interrupt control register 1 ICON1 VSCE 0016 Interrupt control register 2 0 o vse 0 lt 1 1725 171 0016 Fig 2 3 4 Memory map of SFR special function register 2 2 14 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 3 Memory assignment 2 Page Register Area addresses 21716 to 21816 Bit allocation gt State immediately after reset gt 0 0 immediately after reset Function bit 1 immediately after reset No function bit 2 Indeterminate immediately 28 042 ahs after reset Fix this bit to 0 do not write 1 1 Fix this bit to 1 do not write O Address Register Bit allocation State immediately after reset 7 60 21716 ROM correction address
142. CHAPTER 1 OVERVIEW PT EPOR 1 2 1 2 Pin MERCI 1 5 n OY 1 7 A 1 9 2 2 V I 2 2 Laudate Dui DI NE 2 2 MEAM EMEN 2 3 H 2 6 2 6 aa ia te 2 8 EET 2 10 2 10 2 3 Memory ODE NAT a Onde 2 11 Oe O X 2 16 Hr 2 16 MT 2 17 2 17 eae 2 17 Pr 2 17 Pc RE 2 18 mnc 2 18 TEE 2 19 2 19 2 19 2 3 14 Interrupt control registers addresses 2 19 2 19 2 19 2 19 2 19 2 20 PEE 2 20 TNR 2 23 EXNhITme 2 26 DOMINE MMC 2 27 2 29 2 34 n 2 35 2 6 2 Timers and timer 4 when reset and when executing STP instruction 2 39 7220 Group User s Manual Table of contents Table of contents
143. D A P52 R P53 G P54 B P55 OUT1 M37220M3 XXXSP FP D A P52 R P53 G P54 B P55 OUT CMOS output Internal circuit HSYNC VSYNC Schmidt input HSYNC or VSYNC O indicates a pin Fig 6 8 2 I O pin block diagram 2 6 52 7220 Group User s Manual APPENDIX 6 9 Machine instruction table 6 9 Machine instruction table Machine instructions Symbol Function ADC Note 6 When 0 Note 1 Details OP n Adds the carry accumulator and memory con tents The results are entered into the accumu lator IMP Addressing mode IMM 69 BIT A 2 2 2 When 1 Adds the contents of the memory in the M X X address indicated by index register X the con tents of the memory specified by the addres sing mode and the carry The results are en tered into the memory at the address indicated by index register X AND When T 0 AND s the accumulator and memory contents Note 1 A AAM The results are entered into the accumulator AND s the contents of the memory of the address When 1 indicated by index register X and the contents of the MOX M X AM memory specified by the addressing mode The re sults are entered into the memory at the address in dicated by index register X BBC Note 4 15 0 Ab 07 Shifts the contents of accumulator or c
144. EM 2 99 2 16 Clock generating 20404 4 4 2 100 2 101 CHAPTER 3 ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics nni aac nnn aane nb xa nu nam Enna an 3 2 3 2 Standard characteristics eec dave ru In aa exe VA Du Dun oS VR NR eu n HD 3 6 7220 Group User s Manual Table of contents CHAPTER 4 M37220M3 XXXSP FP e TAE 4 2 UL uu LE 4 4 UI 4 6 ae 4 8 Nea seas P n 4 9 bd ER reu tt acta 4 10 4 5 2 Memory nenne 4 11 m EMT 4 14 E E A 4 15 EE E E EE A ENA A 4 17 m 4 19 4 5 7 Internal state immediately after reset 4 26 M LUE EE 4 28 Or 4 32 C M 5 2 5 2 5 2 5 1 3 General flowchart 2 cci sa veta y Feste Rex ea Des rev RE aua 5 3 O P 5 6 5 7 WHERE TP 5 8 HH 5 9 5 1
145. ESCRIPTION 2 15 Reset 2 15 3 Notes for poweron reset When poweron reset set the external reset circuit so that the reset input voltage must be kept 0 6 V or less until the power source voltage reaches 4 5 V after the power is turned on Set the external reset circuit so that the reset input voltage must be kept 0 6 V or less when the power source voltage falls 4 5 V after the power is turned off Figures 2 15 5 to 2 15 7 show examples of external reset circuit M37221M6 XXXSP FP RESET Vcc 0V Power source voltage 4 5 Reset input voltage 0 6 V Fig 2 15 5 Voltage at poweron reset M37221M6 2 gt XXXSP FP Fig 2 15 6 Example of reset circuit 1 7220 Group User s Manual M37221M6 XXXSP FP Vss Fig 2 15 7 Example of reset circuit 2 2 99 FUNCTIONAL DESCRIPTION 2 16 Clock generating circuit 2 16 Clock generating circuit Oscillation circuit consists of an oscillation gate which operates as an amplifier to provide the gain required for oscillation and an oscillating control flip flop to control this Because of that it is possible to start and stop oscillating as required For details concerning start and stop of oscillation refer to 2 14 Low power dissipation mode Figure 2 16 1 shows the clock generating circuit block diagram Interrupt request S Q Q S Interrupt disable flag WT R 8 STP STP instruction I
146. Each interrupt enable bit is assigned to interrupt control registers 1 and 2 addresses OOFE e and 00FF16 3 Interrupt disable flag The interrupt disable flag 1 is assigned to bit 2 of the processor status register When the interrupt disable flag is set to 1 all interrupts except the BRK instruction interrupt are disabled when the flag is cleared to 0 interrupts are enabled However if the interrupt disable flag is cleared to 0 the interrupt cannot be accepted even when the interrupt enable bit is 0 7220 Group User s Manual 2 29 FUNCTIONAL DESCRIPTION 2 5 Interrupts Interrupt Request Register 1 b7 b6 656463 626160 Interrupt request register 1 IREQ1 Address 16 Functions After No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued No interrupt request issued Interrupt request issued interrupt request issued Interrupt request issued interrupt No interrupt request issued request bit CRTR Interrupt request issued Timer 1 interrupt request bit TMiR Timer 2 interrupt request bit 2 Timer 3 interrupt request bit Timer 4 interrupt request bit VSYNC interrupt No interrupt request issued request bit VSCR Interrupt request issued Multi master 120 05 interface 0 No interrupt request iss
147. Example Character code 1 16 Character Character 4 ROM1 ROM2 4 Example 101A0i6 D7 Be e Da Bibo Example i6 0016 101 n 0416 1 0 16 1116 1116 1116 2016 2016 BEEBE sr 4016 4016 4016 0016 0016 3 3 7220 Group User s Manual Y 109 016 10 109AF 16 gt be bs b4 bs be b E16 APPENDIX 6 11 Mask ROM ordering method FO FO FO FO FO FO FO FO F8 F8 F8 F4 F4 F4 F0 6 F016 o o o 6 79 APPENDIX 6 12 Mark specification form 6 12 Mark specification form 42P4B 42 PIN SHRINK DIP MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below A B C and enter the Mitsubishi IC catalog name and the special mark if needed A Standard Mitsubishi Mark Customer s parts number g
148. FE98 UE DEX ER EIE A note 2 E SRN GaN Lm D VEN eae LEX See note 2 ETE See 1 Example B Correction program R Address Machine Description style block 2 instructions 02 0 SN STA 0125H X X 02 SEA INC A V O2E4 DEX BMI 02EAH 5 See 2 SS FE96H _ 02 4C9BFE JMP FE9BHO See note 1 Notes 1 In FE9BH is specified as the return destination address of JMP In this example since the instruction at the return destination address is RTS even if RTS is used instead of JMP the operation is the same as that of JMP As a result the number of bytes is reduced 2 BPL and BMI as machine instructions have no absolute addresses but relative addresses as branch destinations Fig 5 3 3 Correction example 2 5 16 7220 Group User s Manual APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 5 3 3 EPROM Figures 5 3 4 5 3 5 show the E7PROM map when using the ROM correction function To store correction codes by using both ROM correction functions 1 and 2 the capacity of E7PROM needs to be approximately 70 bytes Stored data Instructions in address Machine instruction correction program ROM correction function 1 Valid invalid 55H valid others invalid ROM correction function 1 Execution address high order ROM correction 1 Execution address low order 0
149. ITITI 12C clock control register S2 address 0008 16 Functions After reset R W Setup value of High speed CCR4 CCRO mode clock mode 00 to 02 Setup disabled 03 etup disabled 333 04 Setup disabled 250 5 100 400 See note 833 500 CCR value 166 c 5 SCL mode 0 Standard clock mode specification bit 1 High speed clock mode FAST MODE ACK bit 0 ACK is returned 7 ACK clock bit 0 No ACK clock Note At 4000kHz in the high speed clock mode the duty is as below 0 period 1 period 3 2 In the other cases the duty is as below 0 period 1 period 1 1 Fig 6 7 11 clock contorol register Address 000816 6 36 7220 Group User s Manual APPENDIX 6 7 Control registers Serial Mode Register b7b6 656463 6261 60 Serial I O mode register SM Address 00DC 16 E um emt 00 0 1 Internal synchronous clock selection bits SMO 5 1 selection bit SM3 as port c port 0 P20 P21 functions 1 SCLK SOUT E Fix this bit to 0 Transfer direction 0 LSB first selection bit SM5 1 MSB first Serial input pin 0 Input signal from SIN pin selection bit SM6 1 Input signal from Sour pin 7 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 6 7 12 Serial mode register Address 00DC16 7220 Group User s Manual 6 37 APPENDIX 6 7 Control registe
150. Master Slave Fig 5 5 1 Connection example 5 26 7220 Group User s Manual APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 5 5 3 Single chip color TV signal processor function 1 Status read Status is read by sending the START condition slave address After is generated from the M52340SP the status data is read out After the status data is output any acknowledge bit is not generated but the STOP condition is sent by the master Then this read operation is completed S Bus operation of Beers address R master side Bus operation of slave side K paign START condition STOP condition Acknowledge bit Read bit 1 No acknowledge bit Fig 5 5 2 Staus read timing 2 Byte write Bytes are written by sending the START condition slave address sub address 1 byte data 1 byte and the STOP condition from the master Bus operation of master side Slave SDA signal 5 Bus operation of slave side 7 START condition STOP condition Acknowledge bit Write bit 0 Fig 5 5 3 Byte write timing 7220 Group Users Manual 5 27 APPLICATION 5 5 Example of 05 control by software M37220M3 XXXSP FP 5 5 4 General flowchart 1 Write processing routine The processing routine which controls 05 devices branch to the
151. NAL DESCRIPTION 2 1 Central processing unit 2 1 4 Program counter PC The program counter is a 16 bit counter consists of and both of which are 8 bit registers The program counter indicates the address of the program to be executed next The M37221M6 XXXSP FP uses the stored program system To start a new operation transfer the instruction and the data from the memory to the CPU Ordinary the program counter is controlled to indicate the memory address to be sent next After each instruction is executed the instruction required next is called out and this cycle is repeated until finished Note The program counter of the M37221M6 XXXSP FP is controlled automatically however make sure to avoid differences between program flow and the program counter contents when operating the stack pointer or directly changing the program counter contents 2 1 5 Processor status register PS The processor status register is an 8 bit register It consists of 5 flags which indicate the state after arithmetic operations related to the internal CPU and 3 flags which determine operation The following explains each of these flags Refer to 6 9 Machine instruction table of this USER S MANUAL or SERIES 740 SOFTWARE USER S MANUAL concerning the change of these flags 1 Carry flag C esee Bit 0 This flag stores any carry or borrow from the ALU after an arithmetic operation and is also changed by
152. ON 2 11 CRT display function Table 2 11 5 Display example of character background coloring when green is set for a character and blue is set for background color Border selection register Color register G output B output OUT1 output Character output OUT2 output MDo COn7 COne COns COn4 COns COn2 COnt No output 0 0 0 1 0 Note 2 Note 1 Same output as Video signal and character character A color green are not mixed o Bl gt I Same output as Video signal and character character A color green are not mixed Blank output Green gt No output No output 0 0 0 1 0 1 0 gt 2 TV image of character background is not displayed Blue No output 1 Noe Background TV image of character Blank output background is not displayed No output 1 0 0 1 0 2 Border output Video signal and character Black color green are not mixed jc ae 56 8 9 110 No output Note 2 Blank TV image of character ans output background is not displayed Border Green output Y Black No output 1 0 0 1 0 1 0 Blue Note 2 Background Blank output TV image of character color border background is not displayed Notes 1 When 0 and COn4 1 there
153. Remainder Stores the quotient in the accumulator and the 5 5 1 1 s complement of the remainder on the stack EOR When 0 Exclusive ORs the contents of accumulator Note 1 A A M and memory The results are stored in the accumulator When 1 Exclusive ORs the contents of the memory M X M GO XM specified by the addressing mode and the con tents of the memory at the address indicated by index register X The results are stored into the memory at the address indicated by index reg ister X Increments the contents of accumulator or memory by 1 Increments the contents of index register X by 1 Increments the contents of index register Y by 1 7220 Group User s Manual 6 55 APPENDIX 6 9 Machine instruction table Addressing mode car up oe ee B ADDE TH EE 223 6 56 7220 Group User s Manual LDA Note 2 LDM Function If addressing mode is ABS PC AD If addressing mode IND 0 ADL 1 If addressing mode is ZP IND CLM 00 00 AD 3 1 5
154. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 2 NE S AS 8 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is g
155. W6 1 PWM4 output 7 P05 PWM5 output 0 P05 output selection bit PW7 1 PWM5 output Fig 2 10 6 PWM output control register 1 address 0005 7220 Group User s Manual 2 69 FUNCTIONAL DESCRIPTION 2 10 PWM 2 10 5 8 bit PWM output control How to control the 8 bit PWM output is described below The PWMO PWM 7 output pins are also used for port 0 and Set 0 to bit 0 of the PWM output control register 1 address 00D5 e to supply the PWM count source this bit is cleared to 0 after reset Write output data to the corresponding 8 bit PWM registers addresses 00005 to 0004 and OOF6 19 Set the corresponding bit of the port PO direction register to 1 to specify the output mode Select the output polarity by bit 3 of the PWM output control register 2 address 00D6 e When this bit is cleared to 0 a positive polarity is selected when set to 1 a negative polarity is selected By setting 1 to the corresponding bits among bits 2 to 7 of the PWM output control register 1 the pins are given the PWM output function to output the PWM When clearing to 0 the pins become general purpose ports ports 0 05 PWM Output Control Register 2 b7 b6 656403 626160 PWM output control register 2 PN Address 000616 Name Funcions 12410 1 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0
156. WDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition 1 gt Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin e Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents do not change after interrupt processing The interrupt processing routine Decrements the SWDT contents by 1 at each interrupt processing Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Main routine Interrupt processing routine SWDT SWDT SWDT 1 Interrupt processing Main processing zN Return Interrupt proce
157. When the ALS bit is 0 and the R W bit is 0 the TRX bit is cleared to 0 receive The TRX bit is cleared to 0 in one of the following conditions When arbitration lost is detected When a STOP condition is detected When occurrence of a START condition is disabled by the START condition duplication prevention function Note With MST 0 and when a START condition is detected With MST 0 and when ACK non return is detected At reset 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface B Bit 7 Communication mode specification bit master slave specification bit MST This bit is used for master slave specification for data communication When this bit is 0 the slave is specified so that a START condition and a STOP condition generated by the master are received and data communication is performed in synchronization with the clock generated by the master When this bit is 1 the master is specified and a START condition and a STOP condition are generated and also the clocks required for data communication are generated on the SCL The MST bit is cleared to 0 in one of the following conditions Immediately after completion of 1 byte data transmission when arbitration lost is detected When a STOP condition is detected When occurrence of a START condition is disabled by the START condition duplication preventing function Note At reset Fig
158. a is stored A character code is YY e in addresses 1100016 to 11FFF e Table 4 5 6 shows the character code table Table 4 5 6 Character code table be omitted partly Character code Character data stored address Left side 8 dots Right 4 side 8 dots 00 6 1000016 to 10006 1080016 1080F e 01 6 1001016 to 1001F e 1081016 to 1081F e 0216 100201 to 1002F e 10820 to 1082F e 03 6 10030 to 1003F e 1083016 to 1083F e 7E 6 107E0 e to 107EF e 10FEO0 e to 10FEF e 716 107F0 e to 107EF e 10FFO0 e to 10FFF e CRT display RAM addresses 060015 to 06B3 CRT display RAM is assigned to addresses 0600 to 06B3 e Table 4 5 7 shows the contents of CRT display RAM Table 4 5 7 Contents of CRT display RAM Block number Display position from left side Character code specifying Color specifying 1st character 060016 068016 2nd character 060116 068116 3rd character 060216 068216 Block 1 18th character 061 1 6 0691 19th character 061216 069216 20th character 061316 069316 0614 0694 Not used to 061F e 069 1 151 062016 06 0 6 2nd character 0621 16 062216 06 216 2 1811 063116 06116 19th character 0632 06216 20th character 063316 06316 4 22 7220 Group User s Manual 37220 3 4 5 Functional description Figure 4 5 12 shows the structure of CRT disp
159. ach pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM LE T Sa hexadecimal notation EPROM type indicate the type used 27C101 EPROM address 000016 Product name ASCII code 000 1 37220 3 data ROM 12 K bytes D00016 1000016 Character ROM 1 107FF 6 1080016 Character ROM 2 10FFF e 1FFFF e LLLA 1 Set FF16 in the shaded area 2 Write the ASCII codes that indicates the product of M37220M3 to addresses 000016 to 000 16 EPROM data check item Refer the EPROM data and check in the appropriate box Do you set FF e in the shaded area 2 Yes Do you write the ASCII codes that indicates the product name 37220 3 to addresses 000016 to OOOF e 2 Yes 2 Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form 42P4B for M37220M3 XXXSP and attach to the mask ROM confirmation form 3 Comments 1 3 7220 Group User s Manual 6 77 APPENDIX 6 11 Mask ROM ordering method
160. al APPENDIX 6 6 SFR assignment State immediately after reset gt 0 0 immediately after reset Read enabled write enabled 1 1 immediately after reset Read enabled write disabled Indeterminate immediately after reset State immediately after reset Access characteristics 60 RW RW RW 7220 Group User s Manual 6 21 APPENDIX 6 6 SFR assignment Area addresses E016 to FF 6 Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 16 16 16 016 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 16 FC16 2016 FE16 FF 6 Register Horizontal position register HR Vertical position register 1 CV1 Vertical position register 2 CV2 Character size register CS Border selection register MD Color register 0 COO Color register 1 CO1 Color register 2 CO2 Color register 3 CO3 CRT control register CC CRT port control register CRTP CRT clock selection register CK A D control register 1 AD1 A D control register 2 AD2 Timer 1 TM1 Timer 2 TM2 Timer 4 4 Timer 12 mode register T12M Timer 34 mode register T34M PWMB register PWM5 Interrupt input polarity register RE CPU mode register CPUM Interrupt request register 1 IREQ1 Inter
161. al 4 35 5 APPLICATION 5 1 Example of multi line display 5 2 Notes on programming for OSD M37220M3 XXXSP FP 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 5 4 Example of I C BUS interface control M37221Mx XXXSP FP 5 5 Example of I C BUS interface control by software M37220M3 XXXSP FP 5 6 Application circuit example APPLICATION 5 1 Example of multi line display 5 1 Example of multi line display The M37221Mx XXXSP FP is used as a general example in describing this application for the 7220 group The M377221Mx XXXSP FP ordinarily displays 2 lines on a CRT screen by displaying 2 blocks at different vertical positions In addition to this it can display 3 lines or more multi line display by rewriting both character data and display positions during interrupt processing using CRT interrupts An example of the software processing for implemention this multi line display is described below This example is 12 line multi line display using blocks 1 and 2 For CRT display details refer to 2 11 CRT display function 5 1 1 Specifications e Pins required B OUT1 Hsync and Vsync Hsync Vsyne input polarity positive polarity input R G B OUT1 output polarity positive polarity output Ge Character colors red blue white and cyan No character background color Bordering OUT is available G Character size minimum size 12 line disp
162. al block diagram 984 294 suod jndjno ceded suod yoojq jeuonoung prt uod Ld uod Od uod 69099900 y a 9 71 149 Jopooep uononasu yeuBis 8 1 y 8 51 g 8 21 z oU L 8 LL uonoejes 69Jnos JUNOD 95 Jejuiod YES 1 4 8 x 1 131 8 Sd 25160 JeisiDeJ 8 v pue snes Jorejnuinooy JOSseo0Jd 10 8 ZL 8 19 4ejunoo ureJ604d Jejunoo sseippy 952 geq The functional block diagram is shown in Figure 4 4 1 2050 e dsip 20 Indjno ejdsip 32013 Suod jndu 1950 SSANO SSA 99A E 13534 jndui 3ndino NIX jndino 7220 Gro
163. alues are 0 P10 OUT2 pin switch bit 0 1 Riw CC7 OUT2 Note Display is controlled by logical product AND between the all blocks display control bit and each block control bit Fig 2 11 3 CRT control register address 00 6 7220 Group User s Manual 2 73 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 1 Display position The display positions of characters are specified in units called a block There are 2 blocks block 1 and block 2 Up to 24 characters can be displayed in 1 block refer to 2 11 3 Memory for display The display position of each block in both horizontal and vertical directions can be set by software The horizontal direction is common to all blocks and is selected from 64 step display positions in units of 4 Tc Tc oscillation cycle for display The display position in the vertical direction is selected from 128 step display positions for each block in units of 4 scanning lines The display position in the vertical direction is determined by counting the horizontal sync signal Hsvwc At this time it starts to count the rising edge falling edge of Hsvwc signal from after about 1 machine cycle of rising edge falling edge of Vsync signal So interval from rising edge falling edge of Hsvwc signal needs enough time 2 machine cycles or more for avoiding jitter The polarity of and Vsync signals can select by the CRT port control register address OOECte
164. an analog input pin and the Vss pin is grounded at a position far away from the Vss pin noise on the GND line may enter a microcomputer through the capacitor 7220 Group User s Manual APPENDIX 6 4 Countermeasures against noise Voc Vss Fig 6 4 5 Bypass capacitor across Vss line and Vcc line Note Microcomputer Analog Thermistor input pin Note The resistor is used for dividing resistance with a thermistor Fig 6 4 6 Analog signal line and resistor and capacitor 6 13 APPENDIX 6 4 Countermeasures against noise 6 4 4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals 1 2 3 Keeping an oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance Installing an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines
165. and 2 5 2 1 4 Contents of stack after execution of BRK 2 7 2 2 1 Access area of M37221M4 XXXSP and M37221M6 XXXSPJFP 2 8 2 2 2 Access area of M37221M8 XXXSP 37221 2 9 2 3 1 Memory assignment of M37221M4 XXXSP and 37221 6 2 11 2 3 2 Memory assignment of M37221M8 XXXSP and 7221 2 12 2 3 3 Memory map of SFR special function register 1 2 13 2 3 4 Memory map of SFR special function register 2 2 14 2 3 5 Memory map of 2 page register only M37221M8 XXXSP and UEFEAPAL SS cl 2 15 2 3 6 I O setting example of 2 040 0 0 4 6 enne snnt 2 16 2 3 7 Access to timer registers enne tenente nnns 2 18 2 4 1 I O pin block diagram 1 ssssssssseseseeeeeeeenreen nennen nennen nnne 2 24 2 4 2 I O pin block diagram 2 1 enne nennen nnne nnne en 2 25 2 5 1 interrupt generation 1 2 27 2 5 2 Interrupt control 2 29 2 5 3 Interrupt request register 1 address 00 000 2 30 2 5 4 Interrupt request register 2 address 00
166. and is used to set display on off for each block Bits 3 to 6 are not used 7 CRT port control register address 00EC16 The CRT port control register is assigned to address 00 This register consists of 8 bits and is used to set the input polarity and Vsync and the output polarity R G B OUT1 and OUT2 2 3 9 A D control registers addresses OOEEis and OOEF e The A D control register 1 is assigned to address OOEE e the A D control register 2 is assigned to address OOEF e Both registers consist of 8 bits The A D control register 1 is used to select analog input pins and hold the results of comparator operation Bits 3 and 5 to 7 are not used The A D control register 2 is used to set the internal analog voltage Bits 6 and 7 are not used 2 3 10 Timer registers addresses 00 0 6 to OOF3 e The timer registers are assigned to addresses 00 016 to OOF3 e Both the timer and timer latch are written in this area when writing but only the timer is read when reading To write data to address OOF1 e for example the data are stored to the timer 2 latch and timer 2 After that the timer 2 contents are decremented by synchronizing with the clock pulse but the timer 2 latch contents are not changed Accordingly when reading data at address OOF1 e the contents of timer 2 is read out at the time Addresses O 00 016 1 11 Ti 2 Data loading at 2 00 6 imer Data setting ever
167. ansmitter transmits data to a slave receiver with a 10 bit address Slave address Slave address Slave address El 1st 7 bits RAY 2nd byte Sr 4st 7 bits RAY Data Data 7 bits 0 8 bits 7 bits 1 1 to 8 bits 1 to 8 bits 4 A master receiver receives data from a slave transmitter with a 10 bit address START condition P STOP condition From master to slave A bit R W Read Write bit From slave to master Sr Restart condition Fig 2 8 12 Address data communication format 2 60 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 9 A D comparator 2 9 A D comparator The M37221M6 XXXSP FP has A D comparator consists of the 6 bit D A converter by resistance string method and a comparator Figure 2 9 1 shows the A D comparator block diagram Data bus Comparator control Bits 0 to 2 A D control A D control P15 A D1 INT3 register 1 Y register 2 P1e A D2 Analog A b Switch Switch tree Resistor ladder Fig 2 9 1 A D comparator block diagram The following explains A D comparison method Set 0 to corresponding bits of the direction register to use ports as analog input pins Select the analog input pin with bits 0 to 2 of A D control register 1 address OOEEis Set the comparison voltage Vre for D A conversion by bits 0 to 5 of A D control
168. anual 6 31 APPENDIX 6 7 Control registers PWM Output Control Register 1 b7 b6 656463 b2b1 bO PWM output control register 1 PW Address 000516 B Functions Atterreset DA PWM count source 0 Count source supply selection bit PWO 1 Count source stop DA PN4 output i DA output R w selection bit PW1 PN4 output POo PWMO output 0 0 output R IW selection bit PW2 1 PWMO output 3 PO1 PWM1 output 0 PO output w selection bit PW3 1 PWM1 output PO2 PWM output 0 output mi w selection bit PW4 1 PWM2 output P03 PWM3 output 0 P03 output w selection bit PW5 1 PWM3 output P04 PWM4 output 0 P04 output Riw selection bit PW6 1 PWM4 output 7 P05 PWM5 output 0 P05 output selection bit PW7 1 PWM5 output Fig 6 7 5 PWM output control register 1 Address 00D516 PWM Output Control Register 2 b7 b6 b5b4b3 626160 PWM output control register 2 PN Address 000616 DA output polarity Positive polarity R IW selection bit PN3 Negative polarity PWM output polarity 7 Positive polarity bit PN4 Negative polarity 4 DA general purpose ds Output LOW MN output bit PN5 Output HIGH 5 Nothing is assigned These bits are write disable bits to When these bits are read out the values are 0 Fig 6 7 6 PWM output control register 2 Address 000616 6 32 7220 Group User s Manual APPENDIX 6 7 Control regis
169. area These registers were called special function registers in distinction from the accumulator index registers and so on in the CPU The addressing modes as shown in Table 2 2 1 are used to specify memory RAM and special function registers in the zero page area Those modes dedicated to the zero page area are marked with a symbol This area can be accessed with shorter instructions by using these modes 2 2 2 Special page addresses 0016 to FFFF e The 256 bytes from address FF0016 to address FFFF e within the internal ROM are called special page area The addressing modes as shown in Table 2 2 2 are used to specify memory in the special page area Those modes dedicated to the special page area are marked with a symbol This area can be accessed with shorter instructions by using these modes Subroutines used with considerable frequency are ordinary assigned in this area Table 2 2 1 Zero page addressing Addressing mode Zero page Zero page Indirect Bytes required 2 Zero page X Zero page Y Zero page Bit Zero page Bit Relative Absolute Absolute X Absolute Y Relative Indirect Indirect X Indirect Y N TO IO IO Table 2 2 2 Special page addressing Addressing mode Special page Bytes required 2 Absolute Absolute X Absolute Y Relative Indirect Indirect X Indi
170. art position horizontal direction for each character size 2 77 Fig 2 11 10 Example of display character data storing form 2 78 Fig 2 11 11 Structure of CRT display RAM sse enne nnns 2 81 Fig 2 11 12 Color register n addresses 00 6 to 0 91 2 82 Fig 2 11 13 Generation timing of CRT interrupt 2 84 Fig 2 11 14 Display state of blocks and occurrence of CRT interrupt request 2 84 211 15 Border eiie deett tt ee Een ete un dne Pee eed 2 85 Fig 2 11 16 Border selection register address 0 51 2 85 Fig 2 11 17 CRT port control register address OOEC16 sss 2 86 Fig 2 11 18 MUTE signal output 2 87 Fig 2 11 19 CRT clock selection 2 88 Fig 2 12 1 ROM correction address registers 2 89 Fig 2 12 2 ROM correction enable 2 89 Fig 2 13 1 Sequence at detecting software runaway 2 90 Fig 2 14 1 Oscillation stabilizing time at return by reset 2 92 Fig 2 14 2 Execution sequence example at return by occurrence of INTO interrupt Ker 2 92 Fig 2 14 3 Reset Input time idein indere teet den ee
171. as input or output At reset this port is 05 set to input mode The output structure is N channel open drain output PWM5 POs INT2 PWM output Output Pins 0 05 are also used as PWM output pins 0 5 04 respectively The output structure is N channel open drain output POzINT1 External Input Pins POs 0 are also used as external interrupt input pins INT2 interrupt input INT1 respectively Analog input Input is also used as analog input pin A D4 1 2 port P1 lO Port P1 is an 8 bit port and has basically the same functions as P11 SCL1 port PO The output structure is CMOS output P12 SCL2 CRT output Output Pins P1o is also used as CRT output pin OUT2 The output structure P13 SDA1 is CMOS output P14SDA2 Multi master Pins 1 14 are used as SCL1 SCL2 SDA1 and SDA2 respectively P14A D1 12 when multi master 05 interface is used The output structure is INT3 interface N channel open drain output 1 2 Analog input Input Pins P1s P1 are also used as analog input pins A D1 to A D3 P17 A D3 respectively External Input P1s pin is also used as external interrupt input pin INT3 interrupt input 7220 Group User s Manual OVERVIEW 1 3 Pin description Table 1 3 2 Pin description 2 Pin Name Functions Output port P2 P2 i
172. ation method 1 2 START condition generation method When the ESO bit of the 12 control register address 00DA e is 1 execute a write instruction to the status register address 000916 to set the MST TRX and BB bits to 1 A START condition will then be generated After that the bit counter becomes 0002 and SCL for 1 byte is output The START condition generating timing and BB bit set timing are different in the standard clock mode and the high speed clock mode Refer to Figure 2 8 9 for the START condition generation timing diagram and Table 2 8 2 for the START condition STOP condition generation timing table STOP condition generation method When the ESO bit of the 12 control register address 00DA e is 1 execute a write instruction to the status register address 00D9 e for setting the MST bit and the TRX bit to 1 and the BB bit to 0 A STOP condition will then be generated The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high speed clock mode Refer to Figure 2 8 10 for the STOP condition generating timing diagram and Table 2 8 2 for the START condition STOP condition generation timing table 126 status register write signal D p SCL Setup cia une Hold time time SDA Set time for Fig 2 8 9 START condition generation timing diagram 2 status registe
173. b2 61 00 Color register n COO to n 0 to 3 Addresses 00 616 to 00 916 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 0 No character is output Riw 1 Character is outpu i 0 No character is output Riw 1 Character is outpu 0 No character is output Riw 1 Character is outpu 0 No background color is output 1 Background color is output See note 1 B signal output selection bit COn1 G signal output selection bit COn2 R signal output selection bit COn3 B signal output background selection bit COn4 OUT1 contro 0 Character is outpu 1 Blank is output signal output bit COn5 See notes 1 2 See note 3 G signal output background selection bit COn6 R signal output background 0 No background 1 Background color is output 0 No background or is output or is output selection bit COn7 1 Background color is output See note 2 Notes 1 When bit 5 0 and bit 4 1 there is output same as a character or border output from the OUT1 pin Do not set bit 5 0 and bit 4 0 2 When only bit 7 1 and bit 5 0 there is output from the OUT2 pin 3 M37220M3 XXXSP FP Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 OUT signal output control bit COn5 0 Character is output 1 Blank is output Nothin
174. be received immediately after the START condition are detected B Bit 0 Read write bit RBW Not used when comparing addresses in the 7 bit addressing mode In the 10 bit addressing mode the first address data to be received is compared with the contents SAD6 to SADO RBW of the lC address register The RBW bit is cleared to 0 automatically when the stop condition is detected B Bits 1 to 7 Slave address SADO SAD6O These bits store slave addresses Regardless of the 7 bit addressing mode and the 10 bit addressing mode the address data transmitted from the master is compared with the contents of these bits Figure 2 8 3 shows the address register 12 Address Register 67 b6 65 b4 b3 b2 61 bO 12C address register SOD Address 000816 Functions After reset R pu bit 0 Read RBW 1 Write Slave address The address data transmitted from t SADO to SAD6 the master is compared with the 7 contents of these bits Fig 2 8 3 address register 2 50 7220 Group User s Manual 3 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface lC clock control register S2 address 0008 The 12 clock control register address 000 is used to set ACK control SCL mode and SCL frequency 0 to 4 SCL frequency control bits CCRO CCR4 These bits control the SCL frequency Refer to Table 2 8 4 E Bit 5 SCL mode specification bit FAST MODE This bit specifies the SCL mode
175. because it operates in the same way as interrupts Non maskable software interrupt The different interrupt related registers from those of M37221M6 XXXSP FP are shown in the following pages 7220 Group User s Manual 4 15 M37220M3 XXXSP FP 4 5 Functional description Interrupt Request Register 1 b7 b6 656463 626160 Interrupt request register 1 IREQ1 Address 16 Timer 1 interrupt 0 No interrupt request issued request bit TM1R 1 Interrupt request issued 1 Timer 2 interrupt 0 No interrupt request issued request bit TM2R 1 Interrupt request issued 1 2 Timer 3 interrupt 0 No interrupt request issued request bit TM3R Interrupt request issued 3 Timer 4 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued 4 CRT interrupt 0 No interrupt request issued request bit CRTR 1 Interrupt request issued VsyYNC interrupt 0 No interrupt request issued request bit VSCR 1 Interrupt request issued Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 7 INT3 interrupt 0 No interrupt request issued Rik request bit 1 Interrupt request issued 0 can be set by software but 1 cannot be set Fig 4 5 5 Interrupt request register 1 address 00FCi Interrupt Control Register 1 b7 b6 b5 b4 b3 6261 bO Interrupt control register 1 ICON1 Address
176. bits are the stack area 00 e O116 The low order 8 bits are the stack pointer contents Restoring of the processor status register in items and above is not performed in this case Execute the RTS instruction to return from a subroutine Execute the PLP instruction and PLA instruction to restore the processor status register and the accumulator respectively Executing the PLP PLA instruction increments the stack pointer by 1 and restores the contents at the address indicated as below to the processor status register high order 8 bits are the stack area value 00 e or O116 The low order 8 bits are the stack pointer 2 4 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 1 Central processing unit pacco S N On going routine Interrupt request gt Execute JSR lt PCH 5 PCL S Six 6 8 1 S 5 1 S S1 MS Contents of high order 8 bits of program counter Contents of low order 8 bits of program counter Contents of processor status register Contents of stack pointer Memory Instruction for returning from interrupt routine to main routine Instruction for returning from subroutine to main routine Fig 2 1 3 Sequence of push onto pop from a stack during interrupts and subroutine calls 7220 Group User s Manual 2 5 FUNCTIO
177. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communicati
178. carry flag is shifted into the high order bit Rotates the contents of memory to the right by 4 bits zl 5 5 1 Returns from an interrupt routine to the main 5 5 routine 5 5 1 5 5 1 1 Returns from subroutine to the main routine PC M S 5 5 1 PCM 5 SBC When T 0 Subtracts the contents of memory and comple Note 1 ACA M C ment of carry flag from the contents of accumula Note 5 tor The results are stored into the accumulator When 1 Subtracts contents of complement of carry flag M X and contents of the memory indicated by the addressing mode rom the memory at the address indicated by index register X The re sults are stored into the memory of the address indicated by index register X Sets the specified bit in the accumulator or memory to 1 Sets the contents of the carry to Sets the contents of the decimal mode flag to pr 1 Sets the contents of the interrupt disable flag to 7 1 Sets the contents of the index X mode flag to 3 7220 Group User s Manual 6 59 APPENDIX 6 9 Machine instruction table Addressing mode Processor status register 76 5 4 3 2 112 112 Value saved in stack
179. ceive and recognize its own slave address transmitted by another master device Arbitration lost The status in which communication as a master is disabled 7220 Group User s Manual 2 55 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 56 Bit 4 C BUS interface interrupt request bit PIN This bit generates an interrupt request signal Each time 1 byte data is transmitted the state of the PIN bit changes from 1 to 0 At the same time an interrupt request signal is sent to the CPU The PIN bit is set to 0 in synchronization with a falling edge of the last clock including the ACK clock of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit When the PIN bit is 0 the SCL is kept in the 0 state and clock generation is disabled Figure 2 8 7 shows an interrupt request signal generating timing chart The PIN bit is set to 1 in any one of the following conditions e Executing a write instruction to the data shift register address 000716 When the ESO bit is 0 At reset The conditions in which the PIN bit is set to 0 are shown below Immediately after completion of 1 byte data transmission including when arbitration lost is detected Immediately after completion of 1 byte data reception n the slave reception mode with ALS 0 and immediately after completion of slave address or general call address reception n
180. ck I O pins 52 55 Output 4 bit X 1 CMOS output structure can be used as CRT output pins Serial 8 bit X 1 A D comparator 6 channels 6 bit resolution D A converter 2 6 bit resolution PWM output circuit 14 bit X 1 8 bit X 6 Timers 8 bit timer X 4 Subroutine nesting 96 levels maximum Interrupt External interrupt X 3 Internal timer interrupt X 4 Serial interrupt X 1 CRT interrupt X 1 f Xin 4096 interrupt X 1 Vsync interrupt X 1 BRK interrupt X 1 Clock generating circuit 2 built in circuits externally connected a ceramic resonator or a quartz crystal oscillator Power source voltage 5 V 10 4 2 7220 Group User s Manual M37220M3 XXXSP FP 4 1 Performance overview Table 4 1 2 Performance overview 2 Parameter Performance Power dissipation CRT ON 165 mW typ at oscillation frequency f Xin 8 MHz fcrt 8 MHz CRT OFF 110 mW typ at oscillation frequency 8 MHz In stop mode 1 65 mW maximum 12V withstand ports 6 LED drive ports 4 Operating temperature range 10 to 70 Device structure CMOS silicon gate process Package M37220M3 XXXSP 42 pin shrink plastic molded DIP M37220M3 XXXFP 42 pin shrink plastic molded SOP CRT display function Number of display characters 20 characters X 2 lines maximum 16 lines by software Dot s
181. clock at overflow of these timers Therefore the program can start under a stable clock 1 2 When reset When reset Timers 3 and 4 are automatically set by hardware as shown in Table 2 6 2 and immediately start counting down The counting is continued then Timer 4 overflows and the internal clock 6 is supplied the internal reset is released The program can start again When executing the STP instruction Immediately after the STP instruction is executed Timers 3 and 4 are automatically set as shown in Table 2 6 2 as in the case of reset and placed in the stop mode When the stop mode is entered the processor stops supplying the internal clock and contents of Timers and 4 are retained When the stop mode is released by reset input or external interrupt input the processor simultaneously supplies f Xw and Timers 3 and 4 start counting down The counting is continued then when timer 4 overflows and the internal clock is supplied The program can start again Table 2 6 2 Contents of timers 3 and 4 when reset or when executing STP instruction Contents Timer 4 Value FF 6 0716 Note f Xin 16 except when executing the STP instructions Count source Timer 3 overflow signal When executing the STP instruction f XIN 16 is not automatically selected as the timer 3 count source Accordingly set bit 0 of the timer 34 mode register address 00F516 to 0 before executing the STP instruction select
182. cter Character y 4 ROM1 ROM2 N bz be bs bs be bi Example 109 016 0016 to 0416 109AF 6 0416 1 0 1 1116 1116 1116 2016 2016 B e 4016 4016 4016 0016 0016 3 3 7220 Group User s Manual Note Write the character code 00 16 to 7F 16 to addreses 10000 16 to 10FFF ie Write the character code 80 16 to FF 6 to addreses 11000 16 to 11 16 mmoouuo doo ociconm oco SINGLE CHIP MICROCOMPUTER M37221M4 XXXSP bz be bs b4 bs be b bo Fis APPENDIX 6 11 Mask ROM ordering method 016 016 016 016 016 016 016 016 816 816 816 F416 F416 F416 016 016 6 67 APPENDIX 6 11 Mask ROM ordering method GZZ SH11 58B lt 72A0 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M8 XXXSP MITSUBISHI ELECTRIC Date Section head Supervisor signature signature Note Please fill in all items marked Submitted by Supervisor Company name Customer 2 D Issuance signature Date issued 1 Confirmation Specify the name of the p
183. ctively The output structure is N channel open drain output POzINT1 External Input Pins POs PO are also used as external interrupt input pins INT2 interrupt input INT1 respectively Analog input Input 06 is also used as analog input A D4 P1 P14 I O port P1 P1 is 8 bit I O port and has basically the same functions as 15 01 port PO The output structure is CMOS output Analog input Input Pins 15 17 are also used as analog input pins A D1 to A D3 P1s A D2 respectively P17 A D3 External Input P1s pin is also used as external interrupt input interrupt input 4 6 7220 Group User s Manual M37220M3 XXXSP FP 4 3 Pin description Table 4 3 2 Pin description 2 Input Pin Name Functions Output 1 port P2 I O Port P2 is an 8 bit port and has basically the same functions as P21 Sour port PO The output structure is CMOS output P22 Sin External clock Input Pins P2s P24 are also used as external clock input pins TIM3 2 23 respectively P24 TIM2 Serial P2o pin is also used as serial I O synchronous clock input output P2s P2 synchronous The output structure is N channel open drain output clock input output Serial data I O Pins P2 P22 are also used as serial data input output pins Sour input output Sin respectively Th
184. dress FFFE e as low order address Figure 2 15 1 shows this sequence Internal reset Address 32 768 counts of f XiN by timers 3 and 4 Notes 1 and f 9 are in the relation f XIN 2 0 2 A question mark indicates an undefined state that depends on the previous state 3 Immediately after a reset timer 3 and timer 4 are connected by hardware At this time FF16 is set in timer 3 and 0716 is set to timer 4 Timer counts down with f XIN 16 and reset state is released by the timer 4 overflow signal Fig 2 15 1 Timing diagram at reset 7220 Group Users Manual 2 95 FUNCTIONAL DESCRIPTION 2 15 Reset 2 15 2 Internal state immediately after reset Figures 2 15 2 to 2 15 4 show the internal state immediately after reset Area addresses C016 to DF 6 Address Register C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 16 16 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 DAt6 0816 DC16 DD16 DE16 DF16 Fig 2 15 2 Internal 2 96 Port Port PO direction register DO Port P1 P1 Port P1 direction register D1 Port P2 P2 Port P2 direction register D2 Port P3 P3 Port P3 direction register D3 Port P5 P5 Port P5 direction register D5 Port P3 output mode control register P3S DA H register DA H DA L register DA L PWMO register PWMO PWM1 register PWM1 PWM2 register PWM2 PWMS
185. dress OOFE 16 lt 0010000 12 Enable Vsync and Timer 1 interrupts to take priority than CRT interrupt And also be sure to disable the following interrupts CRT interrupt Push registers X Y A all interrupts with lower priority than CRT interrupt multiple ICON address 16 000000002 interrupts c Ej of interrupt processing multiple interrupts VSYNC Timer 1 Pop the registers X Y A ej Disable all interrupts COND d Pop ICON 1 and 2 contents e during CRT interrupt multiple interrupts RETURN Fig 5 1 10 Flowchart of CRT interrupt processing routine when setting multiple interrupts 7220 Group User s Manual 5 11 APPLICATION 5 1 Example of multi line display 4 Vsvwc interrupt processing routine when setting multiple interrupts Figure 5 1 11 shows the flowchart of Vsync interrupt processing routine when setting multiple interrupts and are the setting routines for multiple interrupts ICON1 ICON2 Interrupt control registers 1 2 V_ICON1 V ICON2 Back up RAM for interrupt control registers 1 2 during V SYNC interrupt Accumulator Index register X Index register Y X modified operation mode flag Decimal operation mode flag 2 address 00 16 lt 00000001 2 multiple ICON address 00 16 lt 000000002 Enable Timer 1 interrupt to interrupts 0 take
186. e character border function Figure 2 11 16 shows the border selection register Bl Character data dots Border dots Fig 2 11 15 Border example Table 2 11 6 Relationship between set value of border selection register and character border function Border selection register Funct 5 eo MDnO unctions xample of outpu B output 0 Ordinary OUT1 output Border including R G B output 1 OUT1 output Border Selection Register 67 b6 b5 64 63 b2 61 60 Border selection register MD Address 00 516 FS ee a rem When this bit is read out the value is 0 Block 1 OUT1 output 0 Same output as character output Indeterminate iW border selection bit MD10 1 Border output Nothing is assigned This bit is a write disable bits Block 1 OUT1 output 0 Same output as character output Indeterminate iW border selection bit MD20 1 Border output Nothing is assigned These bits are write disable bits 9 When these bits are read out the values are 0 Fig 2 11 16 Border selection register address 0025 7220 Group Users Manual 2 85 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 7 CRT output pin control CRT display output pins and OUT1 are also used for ports 5 gt 55 respec
187. e current interrupt processing routine Figure 5 1 9 shows the timing when all interrupt request bits CRT Vsync Timer 1 are 1 at the same sampling point Note When setting multiple interrupts be sure to determine priority levels to prevent occurrence of plural interrupts with the same priority level CRT interrupt request bit VSYNC interrupt request bit Timer 1 interrupt request bit E 71 CRT interrupt processing series of o series of 3 seriesof 2 lt M nr VSYNC interrupt processing Timer 1 interrupt processing Interrupt disable flag 1 Fig 5 1 9 Timing when all interrupt request bits are 1 at the same sampling point 5 10 7220 Group User s Manual APPLICATION 5 1 Example of multi line display 3 CRT interrupt processing routine when setting multiple interrupts Figure 5 1 10 shows the flowchart of CRT interrupt processing routine when setting multiple interrupts and are the setting routines for multiple interrupts ICON1 ICON2 Interrupt control registers 1 2 CRT_ICON1 Back up RAM for interrupt control registers 1 2 during CRT interrupt Accumulator CRT interrupt processing routine Index register X Index register Y X modified operation mode flag o Decimal operation mode flag CRT_ICON1 CRT ICON2 ICON2 Set routine for lt ad
188. e omitted partly 2 79 Table 2 11 4 Contents of CRT display RAM rennen nennen 2 80 Table 2 11 5 Display example of character background coloring when green is set for a character and blue is set for background color 2 83 Table 2 11 6 Relationship between set value of border selection register and character m 2 85 Table 2 14 1 State In Stop MOdE tete bo e tta baee eA dade 2 91 Table 2 14 2 State in wait 2 93 Table 2 14 3 Invalid interrupts in the wait emn 2 93 7220 Group User s Manual xi List of tables xii CHAPTER 4 M37220M3 XXXSP FP Table 4 1 1 Performance overview 1 a nnne nnn 4 2 Table 4 1 2 Performance overview 2 nennen 4 3 Table 4 3 1 Pin description 1 4 6 Table 4 3 2 Pini description 2 i ctt 4 7 Table 4 5 1 Difference between M37220M3 XXXSP FP and M37221M6 XXXSPJ FP 4 9 Table 4 5 2 Difference of programmable ports between M37221M6 XXXSP FP and 37220 3 4 14 Table 4 5 3 Interrupt sources vector addresses and 4 15 Table 4 5 4 Relationship between contents of D A conversion register and outpu
189. e output structure is N channel open drain output P30 A D5 I O port Ports 3 bit I O ports and have basically the same functions as port PO Either CMOS output or N channel open drain output structure P31 A D6 can be selected as the port P30 and P3 The output structure of port DA2 P32 P32 is N channel open drain output Analog input Input Pins 3 are also used as analog input pins A D5 A D6 respectively D A conversion Output Pins 3 are also used as D A conversion output pins DA1 DA2 output respectively P33 OSC1 Input port Input Ports P3s P3 are 2 bit input ports P34 OSC2 Clock input Input P3s pin is also used as CRT display clock input pin OSC1 CRT display Clock output for Output P3 pin is also used as CRT display clock output pin OSC2 CRT display output structure is CMOS output P52 R Output port P5 Output Ports 52 55 are 4 bit output ports The output structure is CMOS P53 G output P54 B CRT output Output Pins P52z P5s are also used as CRT output pins G B OUT respectively P5s OUT The output structure is CMOS output Hsyne input Input This is a horizontal synchronous signal input for CRT Vsync Vsync input Input This is a vertical synchronous signal input for CRT D A DA output Output This is a 14 bit PWM output pin 7220 Group User s Manual 4 7 M37220M3 XXXSP FP 4 4 Functional block diagram 4 4 Function
190. ent data from losing during interrupts and subroutine calls push the other registers onto a stack by software as described above For example execute the PHA instruction to push the accumulator contents onto a stack Executing the PHA instruction stores the accumulator contents at an address indicated as below high order 8 bits are the stack area 00 e or O116 The low order 8 bits are the stack pointer contents The stack pointer contents are then decremented by 1 Execute the RTI instruction to return from an interrupt routine When the RTI instruction is executed the processing is performed automatically in the following sequence refer to Figure 2 1 3 The stack pointer contents are incremented by 1 The contents at the address indicated as below are restored to the processor status register high order 8 bits are the stack area 00 e or 01 e The low order 8 bits are the stack pointer contents The stack pointer contents are incremented by 1 The contents at the address indicated as below are restored to low order 8 bits of the program counter PC high order 8 bits are the stack area value 00 e or O116 The low order 8 bits are the stack pointer contents The stack pointer contents are incremented by 1 The contents at the address indicated as below are restored to high order 8 bits of the program counter high order 8
191. er s Manual 4 29 M37220M3 XXXSP FP 4 6 Electrical characteristics Electric characteristics Vcc 5 V 10 96 Vss 0 V 8 MHz 10 to 70 C unless otherwise noted Limits Symbol Parameter Test conditions Min Typ Max Unit Power source current System operation Vcc 5 5 V CRT OFF 20 40 mA 8 MHz CRT ON 30 60 Stop mode Vcc 5 5 V f Xin 0 300 pA HIGH output voltage B OUT D A 4 5 V 2 4 V P1o P1z 20 27 0 5 mA P30 P3 VoL LOW output voltage B OUT D A Vcc 4 5 V 0 4 V POo PO7 P1o P17 lo 0 5 mA P2o P2s 3 3 gt LOW output voltage 24 2 4 5 V 3 0 lo 10 0 mA Vr Vr Hysteresis RESET Voc 5 0 V 05107 M Hysteresis Note Hsync Vsync 2 Vcc 5 0 V 0 5 1 3 INT1 INT2 INT3 Sn HIGH input leak current RESET POc POz 5 5 V 5 uA P1o P17 20 27 5 5 V Vsync liz LOW input leak current RESET 0 5 5 V 5 P1o P17 20 27 0V P3o P34 Vsync lozH HIGH output leak current POo POs Vcc 5 5 V 10 12V Note P07 P15 P23 and P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins 20 22 have the hysteresis when these pins are used as serial pins 4 30
192. eristics Ports 10 17 20 23 P30 P31 and D A a loL VoL characteristics LOW level output current OL mA LOW level output voltage V OL V b IOH VOH characteristics 60 00 40 00 20 00 HIGH level output current OH mA 0 000 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V OH V 7220 Group User s Manual 4 33 M37220M3 XXXSP FP 4 7 Standard characteristics 4 Ports P24 P27 a loL VoL characteristics 100 00 80 00 60 00 40 00 LOW level output current oL mA LOW level output voltage V oL V b characteristics HIGH level output current oH mA _ CE _ FERNER EL _ 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V oH V 4 34 7220 Group User s Manual M37220M3 XXXSP FP 4 7 Standard characteristics 5 Ports P52 P55 a loL Vo characteristics LOW level output current oL mA 0 000 1 200 2 400 3 600 4 800 6 000 LOW level output voltage V oL V b characteristics HIGH level output current oH mA 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V oH V 7220 Group User s Manu
193. eset circuit shortest possible wiring within 20mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET input pin the reset is released before the internal Reset state of the microcomputer is completely circuit initialized This may cause a program runaway Vss Fig 6 4 1 Wiring for RESET input pin 2 Wiring for clock input output pins eMake the length of wiring which is connected to clock pins as short as possible eMake the length of wiring within 20mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible Ge Separate the Vss pattern only for oscillation from other Vss patterns Reason If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Fig 6 4 2 Wiring for clock I O pin 7220 Group User s Manual 6 11 APPENDIX 6 4 Countermeasures against noise 3 Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring Reason The processor mode of a microcomputer is influenced by a potential at the CNVss pin
194. esses 060016 to 06B7 e and is divided into a display character code specification part and display color specification part for each block Table 2 11 4 shows the contents of CRT display RAM For example to display a character at the first character position leftmost in block 1 it is necessary to write the character code in address 06001 and the color register No to the low order 2 bits bits 0 and 1 at address 0680 e The color register No to be written here is one of the 4 color registers in which display color is set in advance For details on color registers refer to 2 11 4 Color registers Table 2 11 4 Contents of CRT display RAM Block number Display position from left side Character code specifying Color specifying 1st character 060016 068016 2nd character 060116 068116 3rd character 060216 068216 Block 1 22nd character 0615 06951 23rd character 0616 069616 24th character 0617 6 0697 6 061816 069816 Not used to 061F e 069 1 151 062016 06A016 2nd character 062116 06A1 6 3rd character 062216 06A2 6 Block 2 22nd character 063516 06B5 e 23rd character 0636 0686 24th character 063716 06B7 e 2 80 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function Figure 2 11 11 shows the structure of CRT display RAM Block 1 Character specification 1st character 060016 to 24th character 0617 16 Character code Specify 256 characters 00
195. et to 0 data is received from MSB bit 7 of the register and shifted to the right to low order bit every time new data is received 0 When SM5 is set to 1 data is received from LSB bit 0 of the register and shifted to the left to high order bit every time new data is received When all 8 bit data have been received the serial I O interrupt request bit bit 2 of the interrupt request register 2 address OOFDie is set to 1 B MSB LS ALLL 02 D1 Do 5706 65 b ps 00 Transfer clock Serial I O register Note To start receiving set FF16 to the serial register Fig 2 7 4 Serial register when receiving when SM5 0 7220 Group User s Manual 2 43 FUNCTIONAL DESCRIPTION 2 7 Serial 2 7 6 Serial data transmit method when an external clock is selected 1 Initialization First set the serial mode register address 00DCie as follows Select the synchronous clock SM2 07 Set P2 as pin 1 Since the serial I O port selection bit SM3 is also used for the setting pin Sour port P2 is automatically becomes the Sour pin is not necessary to set pin 22 as pin Sin when transmitting It can be used as general purpose input pin 2 Transmit enable state When transmit data are written to the serial register the serial I O counter is set to 071
196. g 1 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 5 Interrupts 2 5 2 Interrupt control Each interrupt can be controlled with the interrupt request bit the interrupt control bit and the interrupt disable flag Interrupt request bit Interrupt enable bit Interrupt disable flag 1 Start of Reset interrupt BRK instruction process Fig 2 5 2 Interrupt control logic 1 Interrupt request bit When an interrupt request occurs the corresponding bit of the interrupt request register is set to 1 The interrupt request is held active until an interrupt is accepted 0 is written to the relevant bit by software The bit is automatically cleared to 0 simultaneously when the interrupt is accepted Interrupt request bits are cleared to 0 to clear the interrupt request by software but are not set to 1 to generate the interrupt request by software Each interrupt request bit is assigned to interrupt request registers 1 and 2 addresses 00 OOFDie 2 Interrupt enable bit Interrupt enable bits control the acceptance of each interrupt When the interrupt enable bit is cleared to 0 to disable an interrupt the interrupt cannot be accepted Conversely when the interrupt enable bit is set to 1 to enable an interrupt the interrupt is accepted However if the interrupt disable flag is set to 1 the interrupt cannot be accepted even when the interrupt enable bit is set to 1
197. g CPU Stop Internal clock Stop at HIGH level ports State where WIT instruction is executed is held Timer CRT display functions Operating Time to hold internal reset state approximately 32768 cycles of XIN input Wait mode Oscillation stabilizing time fi Vcc 2 or more 4 gt Note Y Execute WIT instruction Returned by reset input Fig 2 14 3 Reset input time 2 14 3 Interrupts in low power dissipation mode The following 4 kinds of interrupts are invalid in the wait mode Therefore 4 interrupts below cannot be used to return from the wait mode to the ordinary mode Table 2 14 3 Invalid interrupts in the wait mode Interrupt source Condition Reason Vsync interrupt CRT interrupt Timer 2 interrupt Timer 3 interrupt The interrupt request bit cannot be set Count source is input from pin 24 2 The count source cannot be supplied Count source is input from pin 23 The count source cannot be supplied The following 2 kinds of interrupts can be used to return from the stop mode to the ordinary mode INT1 interrupt 2 INT2 interrupt INT3 interrupt Figure 2 14 4 shows a transitions of low power dissipation mode 7220 Group Users Manual 2 93 FUNCTIONAL DESCRIPTION 2 14 Low power dissipation mode Wait mode 8 MHz oscillating is stopped Ordinary mode Stop mode 8 MHz oscillating 8 MHz
198. g is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 6 7 18 Color register n Addresses 00 616 to 00E916 7220 Group User s Manual 6 41 APPENDIX 6 7 Control registers CRT Control Register b7 b6 65 b4 63 b2 61 bO CRT control register CC Address 00EA16 0 Fus After reset All blocks display control usse All blocks display off R bit Note 1 All blocks display on Block 1 display control bit 0 Block 1 display off Riw CC1 1 Block 1 display on 2 Block 2 display control bit 0 Block 2 display off R Ww CC2 1 Block 2 display on 2 Notes 1 Display is controlled by logical product AND between the all blocks display control bit and each block control bit 2 M37220M3 XXXSP FP Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 6 7 19 CRT control register Address 00 16 6 42 7220 Group User s Manual APPENDIX 6 7 Control registers Port Control Register 67 66 65 64 b3 62 61 00 CRT port control register Address 00 1 s uen Hsync input polarity 0 Positive polarity R Ww Switch bit HSYC 1 Negative polarity Vsync input polarity 0 Positive polarity Riw switch bit VSYC 1 Negative polarity i R G B output polarity 0 Positive polarity Riw switch bit R G B 1 Negative polarity
199. gnal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D comparison precision to be worse Note during an A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D comparison f Xin is 500 kHz or more e Do not execute the STP instruction and WIT instruction 6 3 7 Note on RESET pin In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin And use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following eMake the length of the wiring which is connected to a capacitor as short as possible Be sure to check the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure 6 8 7220 Group User s Manual APPENDIX 6 3 Notes on use 6 3 8 Notes on input and output pins 1 2
200. have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 424 N SAS Renesas Technology Corp
201. he character size register Character Size Register 67 b6 65 64 63 62 b1 00 Character size register CS Address 00E4 16 0 Minimum size selection bits Medium size CS10 CS11 Large size Do not set Character size of block 2 Minimum size selection bits Medium size CS20 CS21 Large size Do not set Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 2 11 8 Character size register address 0024 The character size can select three sizes minimum Size medium size and large size Each character m size is determined with the number of scanning lines pinumonisize in the height vertical direction and the oscillation cycle for display Tc in the width horizontal Medium size direction Display start The minimum size consists of 1 scanning line 1 poston Tc the medium size consists of 2 scanning lines X 2 Tc and the large size consists of 3 scanning Large size lines X 3 Tc Table 2 11 2 shows the relationship between the set values in the character size register and the character sizes Fig 2 11 9 Display start position horizontal direction for each character size Table 2 11 2 Relationship between set value in character size register and character sizes Set values in character size register i Width horizontal direction Height vertical direction 1 5 Tc oscillation cycle for
202. igned These bits are write disable bits When these bits are read out the values are Fig 2 6 3 Timer 12 mode register address 0 4 6 3 4 2 36 Timer 3 Timer 3 can select one of the following count sources e f Xin 16 External clock from pin Hsvwc External clock from pin 2 The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register address OOF5 6 Timer 3 interrupt request occurs at timer 3 overflow Timer 4 Timer 4 can select one of the following count sources f Xin 16 e f Xin 2 Timer overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register address OOF516 When timer overflow signal is a count source for timer 4 timer functions as an 8 bit prescaler Timer 4 interrupt request occurs at timer 4 overflow 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 6 Timers Timer 34 Mode Register b7 b6 656463 626160 Timer 34 mode register T34M Address 007516 Timer 3 count source 0 f XIN 16 selection bit 1 External clock Timer 4 internal count 0 Timer 3 overflow Source selection bit 1 f XiN 16 T34M1 Timer 3 count 0 Count start stop bit T34M2 1 Count stop Timer 4 count stop 0 Count start bit T34M3 1 Count stop Timer 4 count source 0 Internal clock selection bit T34M4 1 2 Timer 3 external count 0 Exter
203. illation circuit using a ceramic Fig 2 17 2 External clock input circuit example resonator The M37221M6 XXXSP FP has a display clock oscillation circuit so that display clock can be obtained simply by connecting a inductor and capacitor between pins OSC1 and OSC2 Figure 2 17 3 shows the circuit example M37221M6 XXXSP FP Refer to 2 11 9 Clock for display OSC1 OSC2 Fig 2 17 3 Clock oscillation circuit for CRT display 7220 Group User s Manual 2 101 Gh JA ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics 3 2 Standard characteristics ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics 3 1 Electrical characteristics Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Voc Power source voltage Vcc All voltages are 0 3 to 6 V Vi Input voltage CNVss based on Vss 0 3 to 6 V Vi Input voltage POc PO07 P1o P 17 2 Output transistors 0 3 to Vcc 0 3 V P27 4 OSC1 are cut off Hsync Vsync RESET Vo Output voltage POs 1 17 2 0 3 to Vcc 0 3 V P27 P3o P35 B OUT1 D A OSC2 Output voltage POo POs 0 3 to 13 V Circuit current G OUT1 1 1 0 to 1 Note 1 mA 2 2 P30 P31 D A Circuit current G B OUT1 POs 0 to 2 Note 2 mA P1o P1s P17 2
204. in series In this example timers 1 and 2 are connected in series and an overflow signal of timer 1 is used as the count source of timer 2 The timer 2 values read are counted down at the falling edge of the count source When timers 1 and 2 are used as a single 16 bit counter the timer 2 values read take the same value at timing A and B or at timing C and D as shown in Figure 6 3 9 This is because the count source of timer 2 changes at the falling edge of the count source of timer 1 eres Se oim Source count Source _ 1 0 1 0 1 os 10 1 0 1 Timer value read __2 1 o 1 0 FF 1 imer 1 Interrupt request writing to value read 2 1 re 1 Fe 1 timer 1 Timer 1 Writing to interrupt timer 1 request Timer 2 Fig 6 3 8 Relation between timer values and their Sua L L source values read timer setting value 2 Timer 2 value D Timer 2 vauereaa d 1 0 7 Timer2 Writing to interrupt timer 2 request Fig 6 3 9 Relation between timer values and their values read when two timers are connected in series timers 1 and 2 are connected timer 1 setting value 2 timer 2 setting 1 7220 Group User s Manual 6 7 APPENDIX 6 3 Notes on use 6 3 6 Notes on A D comparator 1 2 Signal source impedance for analog input Make the si
205. ing color system 3 58 D2 at sub address 09 16 NTSC D1 at sub address 02 16 SECAM DO at sub address 09 16 Wait for muting time To release mute of picture and sound MUTE D6 at sub address OB 16 lt 0 A MUTE D6 at sub address 01 16 0 Fig 5 5 14 Flowchart of CH UP DOWN key input processing 7220 Group User s Manual 5 37 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 3 Processing of picture memory switching key input Picture memory switching Related processings Read out picture data from RAM Changing picture data OSD when switching picture memory Write last data to E2PROM etc Set the following according to each picture memory mode SHARPNESS 00 D5 at sub address 04 16 CONTRAST 00 to 06 at sub address 05 16 TINT 00 to D6 at sub address 07 16 COLOR D0 to D6 at sub address 08 16 BRIGHT 00 to D6 at sub address 16 Fig 5 5 15 Flowchart of picture memory switching key input processing 5 38 7220 Group User s Manual APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 5 5 7 Register map The M52340SP has 2 kinds of registers the status data register and the write data registers 1 Status data register The status data register indicates various signal state from the M52340SP side The state is confirmed by regularly reading each bit Status data register 67 b6 b5 b4 63 b2 61 bO
206. interrupt request occurs when a count source next to 0016 is input 10 Serial interrupt The serial interrupt request is generated by detecting a rising edge of the eighth serial transfer clock after writing to the serial register 11 Multi master 2 interface interrupt A multi master interrupt request occurs synchronized with a falling edge serial clock SCL every completion of 1 byte data communication 12 INT3 interrupt An INTS interrupt request is generated by detecting a transition in the level pin INT3 external interrupt input Detecting either positive polarity LOW to HIGH transition or negative polarity HIGH to LOW transition to be detected is set with the interrupt input polarity register bit 5 at address 00 916 When is set to 0 a positive polarity is detected when is set to 1 a negative polarity is detected Pin INT3 is also used for port 15 and A D1 An INT3 interrupt by a level transition on the pin may cause software runaway Therefore when this pin is used as port P1s disable an INT3 interrupt by using an interrupt enable bit and interrupt disable flag 1 13 BRK instruction interrupt 2 28 This software interrupt has the least significant priority and generates an interrupt request is generated by executing when the BRK instruction There is no corresponding interrupt enable bit and no influence by the interrupt disable fla
207. ion 1 shown on the above ports Set for input mode and do not connect to Vcc or Vss directly Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between port and Vcc or Vss ports Set for the input mode and do not connect multiple ports in a lump to Vcc or Vss through a resistor Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between ports At the termination of unused pins perform wiring at the shortest possible distance 20 mm or less from microcomputer pins 7220 Group User s Manual APPENDIX 6 4 Countermeasures against noise 6 4 Countermeasures against noise Countermeasures against noise are described below The following countermeasures are effective against noise in theory however it is necessary not only to take measures as follows but to evaluate before actual use 6 4 1 Shortest wiring length The wiring on a printed circuit board can function an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Wiring for reset input pin Make the length of wiring which is connected to the RESET input pin as short as possible Especially connect a capacitor across the RESET input pin and the Vss pin with the R
208. ion program When the blocks 1 and 2 are used in series the above instruction is not needed at the end of the block 1 The ROM correction function is controlled by the ROM correction enable register Notes 1 Specify the first address op code address of each instruction as the ROM correction address 2 Use the JMP instruction total of 3 bytes to return from the correction program to the main program 3 Do not set the same address to ROM correction addresses 1 and 2 addresses to 021716 to 021 16 ROM correction address 1 high order 021716 ROM correction address 1 low order 021816 ROM correction address 2 high order 021916 ROM correction address 2 low order 021A16 Fig 2 12 1 ROM correction address registers ROM Correction Enable Register 67 b6 05 64 b3 b2 bi 00 ROM correction enable register RCR Address 021216 wens Fats er Block 1 enable bit RCRO 0 Disabled 1 Enabled 1 Block 2 enable bit RCR1 0 Disabled R W 1 Enabled Fix these bits to 0 4 Nothing is assigned These bits are write disable bits When to these bits are read out the values 0 7 Fig 2 12 2 ROM correction enable register 7220 Group User s Manual 2 89 FUNCTIONAL DESCRIPTION 2 13 Software runaway detect function 2 13 Software runaway detect function The M37221M6 XXXSP FP has a function to decode undefined instructions to detect a software runa
209. is when these pins are used as serial I O pins P11 P14 have the hysteresis when these pins are used as multi master I C BUS interface pins 3 4 7220 Group User s Manual ELECTRICAL CHARACTERISTICS 3 1 Electrical characteristics A D Comparator characteristics Vcc 5 V 10 96 Vss 0 V f Xin 8 MHz 10 C to 70 C unless otherwise noted Limits Parameter Test conditions Resolution Absolute accuracy Note When Vcc 5 V 1 LSB 5 64 V Multi master 2 05 bus line characteristics Standard clod mode High speed clock mode Symbol Parameter Min Max Tyo Max Unit teur Bus free time 4 7 1 3 us tHD sTA Hold time for START condition 4 0 0 6 HS LOW period of SCL clock 4 7 1 3 us tr Rising time of both SCL and SDA signals 1000 20 0 1 65 300 NS tHD DAT Data hold time 0 0 0 9 HS HIGH period of SCL clock 4 0 0 6 us tr Falling time of both SCL and SDA signals 300 20 0 1 300 NS tsu DAT Data set up time 250 100 ns tsu sTA Set up time for repeated START condition 4 7 0 6 Us tsu sro Set up time for STOP condition 4 0 0 6 us Note total capacitance of 1 bus line tHIGH tSU DAT tSU STA S Start condition Sr Restart condition P Stop condition Fig 3 1 1 Definition diagram of timing on multi master I C BUS 7220 Group User s Manual 3 5 ELECTRICAL CHARACTERISTICS 3 2 Sta
210. ister Address 00 16 Interrupt Request Register 1 b7 b6 656463 6261 60 Interrupt request register 1 IREQ1 Address 16 8 ater res RW Timer 1 interrupt 0 No interrupt request issued request bit TM1R 1 Interrupt request issued _ 1 Timer 2 interrupt 0 No interrupt request issued request bit TM2R 1 Interrupt request issued 2 Timer 3 interrupt 0 No interrupt request issued request bit TM3R 1 Interrupt request issued 3 Timer 4 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued 4 CRT interrupt 0 No interrupt request issued request bit CRTR 1 Interrupt request issued 5 Vsync interrupt 0 No interrupt request issued RA request bit VSCR 1 Interrupt request issued Multi master 20 interface 0 No interrupt request issued interrupt request bit _ 1 Interrupt request issued 598016 7 INTS interrupt 0 No interrupt request issued Ri request bit 1 Interrupt request issued 0 can be set by software but 1 cannot be set Note M37220M3 XXXSP FP Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 6 7 28 Interrupt request register 1 Address 00 16 6 48 7220 Group User s Manual APPENDIX 6 7 Control registers Interrupt Request Register 2 b7 b6 656463 62610 of Interrupt reque
211. itch bit 0 B signal output Riw OP7 1 MUTE signal output Fig 2 5 8 CRT port control register address 00 2 32 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 5 Interrupts Interrupt request bits are set to 1 by occurrence of an interrupt request even if the interrupt is disabled Therefore to disable interrupt processing clear the interrupt request bit to 0 immediately before the interrupt disable state is cancelled interrupt enable state i e the interrupt enable bit 1 and the interrupt disable flag 07 Reset FFFF16 FFFE16 CRT interrupt FFFD16 FFFC16 FFFBte FFFA16 FFF916 FFF816 FFF516 FFF416 FFF316 FFF216 FFF116 FFF016 FFEF16 FFEE16 FFED16 FFEC16 16 16 FFE916 FFE816 FFE716 FFE616 FFE516 FFE416 BRK instruction interrupt BRK FFDF16 FFDE16 Interrupt Interrupt Interrupt Interrupt request bit enable bit disable flag 1 vector Note indicates to operate together INT2 interrupt INT1 interrupt Timer 4 interrupt f XIN 4096 interrupt interrupt Timer 3 interrupt a fal lt 5 5 5 x 5 20 d 20 d 2 P Timer 2 interrupt z 2 Timer 1 interrupt Serial interrupt Multi master I2C BUS interface interrupt interrupt co m al 5 2 D 2 Fig 2 5 9 Interrupt c
212. k pointer value to the highest address by software 2 3 2 ports addresses 00 016 to 00 6 Addresses 00 01 to OOCDie are assigned to the ports port direction registers and the port output mode control register There are 5 ports PO P1 P2 P3 and P5 Ports PO P1 and P2 are the 8 bit programmable ports Port consists of 5 bits The low order bits 2 are the programmable I O ports and the high order 2 bits P3s and P34 are the input ports For ports PO P1 P2 and 2 input or output can be specified in bit units by setting the relevant values to each port direction register To specify port bits as output pins write 1 to the corresponding bit of the port direction register Conversely write 0 to the corresponding bit to specify as an input pin For example to use the even numbered bits of port P2 as output ports and the odd numbered bits as input ports write 5516 010101012 to address 00C5 e the port P2 direction register at initialization Although Port P5 is an output port it can be specified as the CRT output pins G B OUT1 or as general purpose port P52 P5s by setting each bit in the port P5 direction register When setting 0 it is used for the CRT output pins G B OUT1 and when setting 1 it is used as general purpose output ports 52 55 Note Each port direction register default is input port P5 is CRT output immediately af
213. l RAM Pop registers X Y A c Disable all interrupts COND eon Pop ICON 1 and 2 contents during CUNE CRT interrupt Refer to 5 1 7 2 RETURN Note The multiple interrupt priority of this system is as below Timer 1 VsYNC CRT Fig 5 1 5 Flowchart of CRT interrupt processing routine 7220 Group User s Manual 5 5 APPLICATION 5 1 Example of multi line display 5 1 4 Set of display character data To display the character data set the character codes 00 e to FF e in the character addresses block 1 addresses 060016 to 061716 block 2 addresses 062016 to 063716 Also set the color register specifying 002 to 112 in the color addresses block 1 addresses 068016 to 069716 block 2 addresses 06A0 e to 0687 5 Character code 0016 16 060016 060116 061616 061716 Color uv i 068016 068116 069616 069716 Color register specifying 24 characters 002 to 112 Character code 001 16 to FF 16 062016 062116 063616 063716 Color 06A016 116 068616 068716 Character addresses Color register specifying 002 to 112 24 characters Fig 5 1 6 Set of display character data 5 6 7220 Group User s Manual APPLICATION 5 1 Example of multi line display 5 1 5 Line counter The line counter determines which line of display data is to be set For example if a CRT interrupt occurs at
214. l bit 0 Block 1 display off 1 1 1 display Block 2 display control bit 0 Block 2 display off 2 1 Block 2 display Note Display is controlled by logical product AND between the all blocks display control bit and each block control bit Fig 4 5 15 CRT control register address 00 6 CRT Port Control Register 67 b6 65 64 63 62 b1 00 CRT port control register CRTP Address 00 16 input polarity 0 Positive polarity switch bit HSYC 1 Negative polarity 1 Vsync input polarity 0 Positive polarity switch bit VSYC 1 Negative polarity 2 R B output polarity 0 Positive polarity switch bit R G B 1 Negative polarity Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 4 OUT output polarity 0 Positive polarity switch bit OUT 1 Negative polarity 5 Rsignal output switch bit 0 R signal output OP5 1 MUTE signal output G signal output switch bit 0 G signal output OP6 1 MUTE signal output 7 B signal output switch bit 0 B signal output OP7 1 MUTE signal output Fig 4 5 16 CRT port control register address 00 7220 Group User s Manual 4 25 M37220M3 XXXSP FP 4 5 Functional description 4 5 7 Internal state immediately after reset Figures 4 5 17 and 4 5 18 show the internal state immediately after reset Area addresses C016 to DF 16
215. lag determines whether or not an interrupt occurred by using the BRK instruction When a BRK instruction interrupt occurs the flag B is set to 1 for all other interrupts the flag is set to 0 and pushed to the stack For the M37221M6 XXXSP FP interrupt vectors by using the BRK instruction are independent of other interrupts and it is possible to determine the cause of interrupt by jumping to the vector address inherent to each interrupt Therefore it is not specifically necessary to refer to this flag Note The BRK instruction will be used for debugging 2 6 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 1 Central processing unit S41 PS processor status register PCL low order of program counter high order of program counter Fig 2 1 4 Contents of stack after execution of BRK instruction 6 7 8 X modified operation mode flag T Bit 5 This flag determines whether arithmetic operations are performed via the accumulator or directly between memories When the flag is set to 0 arithmetic operations are performed between the accumulator and memory When 1 arithmetic operations are performed directly between memories This flag is set to 1 with the SET instruction and is cleared to 0 with the CLT instruction Since this flag directly affects calculations always initialize it after a reset When the T 0 indicates an ari
216. lay 5 1 2 Connection example 52 P53 G P54 B 55 0 1 Hsync M37221Mx XXXSP FP Color TV signal processor Monitor Fig 5 1 1 Connection example lt The 1st line Block 1 lt The 2nd line Block 2 lt 3rd line Block 1 lt The 4th line Block 2 T lt The 5th line Block 1 lt The 6th line Block 2 6 lt The 7th line Block 1 13 lt The 8th line Block 2 20 lt The 9th line Block 1 lt The 10th Block 2 lt The 11th line Block 1 442 lt The 12th line Block 2 OSS White R G B Fig 5 1 2 Display example 5 2 7220 Group User s Manual APPLICATION 5 1 Example of multi line display 5 1 3 General flowchart The multi line display processing routine consists of initialization processing routine Vsync interrupt processing routine and CRT interrupt processing routine 1 Initialization processing routine This routine is used to initialize to cause a CRT interrupt Bit 4 of interrupt control register 1 Line counter Counter RAM for line counting lt CRT interrupt enable bit gt CV1 CV2 Vertical position registers 1 2 Bit 4 of interrupt request register 1 PSD Port P5 direction register lt CRT interrupt request bit gt CRT port control register Character size register CRT control
217. lay RAM Block 1 Character specification 1st character 060016 to 20th character 061316 Character code Specify 128 characters 00 16 to 7F16 Color specification 1st character 0680 16 to 20th character 0693 16 Color register specification 0 0 Specifying color register 0 0 1 Specifying color register 1 1 0 Specifying color register 2 1 1 Specifying color register 3 Block 2 Character specification 1st character 062016 to 20th character 063316 Character code Specify 128 characters 00 16 to 7F 16 Color specification 1st character 06A016 to 20th character 0683 16 Color register specification 0 0 Specifying color register 0 0 1 Specifying color register 1 1 0 Specifying color register 2 1 1 Specifying color register 3 Fig 4 5 12 Structure of CRT display RAM 7220 Group Users Manual 4 23 M37220M3 XXXSP FP 4 5 Functional description The different CRT display function related registers from those of M37221M6 XXXSP FP are shown in the following pages Border Selection Register 67 b6 65 64 63 62 b1 00 Border selection register MD Address 0025 16 Name Block 1 OUT output border selection bit MD10 Functions Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 2 Block 1 OUT output border selection bit to Fig 4 5 13 Border selection register addres
218. le 2 7 1 Clock source selection of oscillation frequency by bits O and 1 of the serial Serial 1 0 clock Serial register mode register Bit 2 Bit 1 Bit 0 Oscillation frequency divided by 4 External clock 0 0 or 1 Invalid set both bits 1 and 0 to 0 f Xin 4 0 0 E 19s Internal X16 0 1 Oscillation frequency divided by 32 clock 32 1 9 set bit 1 1 and bit 0 0 f X n 64 1 1 Oscillation frequency divided by 64 set both bit 1 and 0 to 71 The contents of bits 0 and 1 of the serial mode register are invalid when selecting an external clock 2 7 4 Serial input output common transmission reception mode Pin 21 can also be used as the serial data input pin when the serial input pin selection bit bit 6 of the serial mode register address 0006 is set to 1 It is not necessary to set the corresponding bit of port P2 direction register to input mode With this function pin 22 can also be used as general purpose input port P2 P20 SCLK Clock Input or output Transmit mode P21 Sour Serial register 8 77 Receive mode P22 Sin gt Port P22 data Note To start receiving set FF16 to the serial I O register SM Serial 1 register Fig 2 7 3 Serial input output common transfer mode block diagram 2 42 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 7 Serial
219. lor signal and the luminance signal is delayed using the on chip delay line The DL TIME register adjusts the delay approximately and the DFA register performes the fine adjustments When DFA is 1 actual delay time is 50 ns when 0 it is 0 ns For relationship between DFA and DL TIME refer to Table 5 5 9 Table 5 5 9 Relationship between DFA and DL TIME Data DL DL DFA Actual TIME1 TIMEO delay time 0 0 0 0 170 ns 1 0 0 1 120 ns 2 0 1 0 330 ns 3 0 1 1 280 ns 4 1 0 0 410 ns 5 1 0 1 360 ns 6 1 1 0 490 ns 7 1 1 1 440 ns B DBF The M52340SP has 2 TRAP the second TRAP extends the bandwidth of the TRAP described below DBF is the ON OFF switch for the second TRAP When 1 it is on when 0 it is off DBF is used in SECAM and other methods TRAP This is the TRAP ON OFF switch for taking out the luminance signal Y signal by Y C separation Y signal color signal of the composite video signal When 1 it is on when 0 it is off AUDIO Data is set 0 to 127 to change the volume 5 42 7220 Group User s Manual APPLICATION 5 5 Example of PC BUS control by software M37220M3 XXXSP FP SHARPNESS CONTRAST COLOR BRIGHT Data is set to change the picture data Some TVs have a picture mode function such as the movie mode standard mode the fixed data is set according to the mode Accordingly it is necessary to change
220. m width 0 25 us value o atc Fundamental Waveform of smaller interval specified by low order 6 bits waveform 0 25 us X 44 0 25 us X 45 ikan Pd 14 bit PWM output 2028 2 103102101 00 PM Gud 20 28 2 E Et cocer counter FE FD 06 05 04 D3 02 01 counter FE FD 06 05 04 03 02101 00 Fundamental waveform of smaller interval tm which is not specified by low order 6 bits is not changed 0 25 us X 44 14 bit PWM output Low order 6 bit output of DA latch Repeat period T 4096 us Fig 2 10 3 14 bit PWM output example f Xw 8 MHz 2 66 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 10 PWM 2 10 3 8 bit PWM PWMO to PWM5 address 0000 0004 and The 8 bit PWM outputs waveform which is the logical sum OR of pulses corresponding to bits O to 7 of the 8 bit PWM register That is to say 8 kinds of pulses corresponding to the weight of each bit of the 8 bit PWM register are output inside the circuit during 1 cycle Among these pulses OR of pulses that correspond to bits which is set to 1 in the 8 bit PWM register to external devices as PWM output Figure 2 10 4 shows the pulse waveforms corresponding to the weight of each bit of the 8 bit PWM register Figure 2 10 5 shows the example of 8 bit PWM output As shown in the Figures 256 kinds of output
221. n length of entirely HIGH output cannot be output Figure 2 10 3 shows the 14 bit PWM output example Table 2 10 2 shows the relation between and tm m 0 to 63 Table 2 10 2 The relation between D and tm m 0 to 63 Smaller intervals that HIGH duration is longer by tm m 0 to 63 Low order 6 bit data of DA register B 000000 58 Nothing 00000 1 32 00001 0 m 16 48 00001 1 16 32 48 000100 8 24 40 56 000 10 1 8 24 32 40 56 00011 0 16 24 40 48 56 001000 12 20 28 36 44 52 60 010000 2 6 10 14 18 46 50 54 58 62 100000 1 3 5 7 9 55 57 59 61 63 101000 1 3 5 7 9 52 55 57 59 60 61 63 1 1 111 1 1 to 63 0 is not included 7220 Group User s Manual 2 65 FUNCTIONAL DESCRIPTION 2 10 PWM Set 2C16 to DA H register Set 2816 to DA L mm b7 b6 65 b4yb3 62 bi bO 67 b6 65 b4 b3 b2 bt bO DAH o ojt oj 1 1 O0 0 DA L register 1 0 1 0 0 0 D register Undefined At writing of DA L At writing of DA L b13 b6 b5 DA latch These bits decide HIGH level area These bits decido smaller interval tm in which HIGH level of fundamental waveform area is HIGH level area of fundamental waveform HIGH level area of Minimum High order 8 bit fundamental resolution bit X f DA latch undamental wavefor
222. n or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Preface This manual describes the hardware of the Mitsubishi CMOS 8 bit microcomputers 7220 group After reading this manual the user should have a through knowledge of the functions and features of 7220 group and should be able to fully utilize the product The manual starts with specifications and ends with application examples For details of software refer to the SERIES 740 lt SOFTWARE gt USER S MANUAL For details of development support tools refer to the DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS data book BEFORE USING THIS MANUAL This user s manual consists of the following chapters Refer to the chapter appropriate to your conditions such as hardware design or software development The M37221M6 XXXSP FP is used as a general example in describing the functions of the 7220 group unless other wise noted 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer pin configuration pin description functional block diagram CHAPTER 2 FUNCTIONAL DESCRIPTION This chapter describes operation of each peripheral function CHAPTER 3 ELECTRIC CHARACTERISTICS This chapter describes electric characteristics and standard characteristics CHAPTER 4 M37220M3 XXXSP FP This chapter describes differences between the M3722
223. nable register Address 021216 6 50 7220 Group User s Manual APPENDIX 6 8 Ports 6 8 Ports 5 PWMS P32 N channel open drain output Direction register Data bus Port latch M37221M4 XXXSP M37221M6 XXXSP FP M37221M8 XXXSP M37221MA XXXSP P10 OUT2 P11 SCL1 P12 SCL2 P13 SDA1 P14 SDA2 P15 A D1 INTS P16 A D2 P17 A D3 P20 SCLK P21 SOUT P22 SIN P23 TIM3 P24 TIM2 P25 P27 P30 A D5 P31 A D6 See notes 1 2 M37220M3 XXXSP FP P10 P1 4 15 P16 A D2 P17 A D3 P20 SCLk P21 Sour P22 SIN P23 TIMS P24 TIM2 25 2 P30 A D5 DA1 P31 A D6 DA2 See note 2 Direction register CMOS output Port latch Notes 1 When ports 11 14 are used as multi master 2C BUS interface and when ports P20 P21 are used as serial I O output pins their output structure is N channel open drain output 2 For the output structure of ports P30 P31 either CMOS output or N channel open drain output is selected In the case of N channel open drain output the block diagram is the same as below PO6 INT2 A D4 PO7 INT1 N channel open drain output Direction register bins gt 1 O indicates pin Fig 6 8 1 I O pin block diagram 1 7220 Group User s Manual 6 51 APPENDIX 6 8 Ports P33 OSC1 P34 Input Internal circuit M37221M4 XXXSP M37221M6 XXXSP FP M37221M8 XXXSP M37221MA XXXSP
224. naging instruction the value of the unspecified bit may be changed Reason The bit managing instructions are read modify write form instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the data register of an port the following is executed to all bits of the data register for a bit which is set for an input port The pin state is read in the CPU and is written to this bit after bit managing for a bit which is set for an output port The bit value is read in the CPU and is written to this bit after bit managing Note the following Ge Even when port which is set as an output port is changed for an input port its data register holds the output data As for a bit of which is set for an input port its value be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents 3 bit managing instructions SEB and CLB instruction 6 3 9 Note on JMP instruction When using the JMP instruction the indirect addressing mode do not specify the last address in a page as an indirect address Memory addresses 0000 e to FFFFis is separated into pages by each 256 address 7220 Group User s Manual 6 9 APPENDIX 6 3 Notes on use 6 3 10 Note on multi master I C BUS interface This function is used at 8 0 MHz of oscillation frequency 6 3 11 Termination of
225. nal clock from P23 TIM3 pin source selection bit T34M5 1 External clock from pin 6 7 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fig 2 6 4 Timer 34 mode register address 00 516 Table 2 6 1 Memory map of timer related registers Addresses Contents 00 1 1 OOF 116 Timer 2 TM2 00226 Timer 3 00F316 Timer 4 TM4 00F416 Timer 12 mode register T12M 00F516 Timer 34 mode register T34M 7220 Group User s Manual 2 37 FUNCTIONAL DESCRIPTION 2 6 Timers T12M4 T12M1 T12MO 1 T12M4 T12M1 12 0 0 0 1 p Timer 1 d Timert 1 interrupt f XiN 1 4096 i request 1 16 T12M4 T12M1 T12MO P24 TIM2 1 1 interrupt request T12M4 T12M1 T12MO Timer 1 1 0 interrupt request Fig 2 6 5 Example of timer system 2 38 7220 Group User s Manual Timer 2 Timer 2 Timer 2 interrupt request Timer 2 interrupt request Timer 2 interrupt request Timer 2 interrupt request FUNCTIONAL DESCRIPTION 2 6 Timers 2 6 2 Timer 3 and timer 4 when reset and when executing the STP instruction Timers 3 and 4 start counting down immediately after reset status is released or stop mode is released and CPU starts operating by supplying the internal
226. nd AD in AD is 8 high order bits and AD is 8 low order bits Contents of address indicated by zero page AD 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes APPENDIX 6 10 Instruction code table 6 10 Instruction code table 53 00 o 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 um 1 2 4 5 6 0000 5 ORA ASL BBS ASL SEB ORA ASL SEB IND X ZP IND 0 ZP ZP 0 7 A 0 A ABS ABS 0ZP ORA BBC ORA ASL BBC ORA DEC CLB ORA ASL CLB orn s azr on 0010 JSR AND JSR BBS BIT AND ROL BBS PLP ROL SEB BIT AND ROL SEB ABS IND X SP ZP ZP ZP 1 ZP A ABS ABS ABS 1ZP AND BBC AND ROL BBC AND INC CLB LDM AND ROL CLB 3 m ips ser m ar y Lm pesa ees m EOR BBS COM EOR LSR BBS LSR SEB JMP EOR LSR SEB moo 4 sem ar ar ic EOR BBC EOR LSR BBC EOR CLB EOR LSR CLB fr 0110 RTS ADC BBS TST ADC ROR BBS PLA ADC ROR SEB JMP ADC ROR SEB IND X ZP ZP ZP 3 7 IMM A IND ABS ABS 3ZP 0111 7 Bvs ADC BBC ADC ROR BBC ADC CLB ADC ROR CLB IND Y ZP X 2 3ZP ABS Y 5
227. ndard characteristics 3 2 Standard characteristics The data described in this section are characteristic examples Refer to 3 1 Electrical characteristics for rated values 1 Ports 00 05 and P32 a loL VoL characteristics LOW level output current OL mA 3 600 LOW level output voltage V OL V 2 Ports 06 and P07 a loH Vor characteristics HIGH level output current OH mA LOW level output voltage V OL V 3 6 7220 Group User s Manual ELECTRICAL CHARACTERISTICS 3 2 Standard characteristics 3 Ports P10 15 17 20 23 P30 P31 and D A a loL VoL characteristics LOW level output current OL mA LOW level output voltage V OL V b IOH VOH characteristics HIGH level output current OH mA 0 000 1 200 2 400 3 600 4 800 6 000 HIGH level output voltage V OH V 7220 Group User s Manual 3 7 ELECTRICAL CHARACTERISTICS 3 2 Standard characteristics 4 Ports 11 14 a loL Vo characteristics 80 00 60 00 40 00 LOW level output current OL mA LOW level output voltage V oL V b characteristics 80 00 60 00 40 00 HIGH level output current oH mA 0 000 1 200 2 400 3 600
228. nection port between FC BUS interface 0 0 None and ports 0 1 SCL1 5 1 BSELO BSEL1 1 0 SCL2 SDA2 1 1 SDA1 5212 SDA2 Note When using ports P1 P14 I C BUS interface the output structure changes automatically from CMOS output to N channel open drain output However set the port direction register to 1 output mode Fig 2 8 6 control register 2 54 7220 Group User s Manual 5 FUNCTIONAL DESCRIPTION 2 8 Multi master 12 interface status register S1 address 000916 The status register address 0009 6 controls the I C BUS interface status The low order 4 bits are read only bits and the high order 4 bits can be read out and written to E Bit 0 Last receive bit LRB This bit stores the last bit value of received data and can also be used for ACK receive confirmation If ACK is returned when an ACK clock occurs the LRB bit is set to 0 If ACK is not returned this bit is set to 1 Except in the mode the last bit value of received data is input The state of this bit is changed from 1 to 0 by executing a write instruction to the I C data shift register address 000716 Bit 1 General call detecting flag ADO This bit is set to 1 when a general call whose address data is all 0 is received in the slave mode By a general call of the master device every slave device receives control data after the general call The ADO bit is set to
229. negative and also to perform a simple bit test There are no instructions for directly setting or clearing this flag This flag has no meaning in decimal mode 7220 Group User s Manual 2 7 FUNCTIONAL DESCRIPTION 2 2 Access area 2 2 Access area The ROM RAM and various I O control registers are assigned within the same memory area Therefore the same instructions are used for data transfers and arithmetic operations without making any distinction between memory 1 0 Since the program counter is a 16 bit register 64 K byte memory area can be accessed from addresses as 000016 to FFFF e The first 256 bytes of the 64 K byte memory area are called the zero page and the last 256 bytes are called the special page These areas can be accessed with only 2 bytes by using each special addressing mode M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP 000016 CRT display ROM 1000016 x we Internal RAM 8 K bytes ROM Zero page for display RAM RAM 00 016 SFR area 384 bytes 320 bytes Special function register 41FFF16 for for 00FF16 Refer to Figures 2 3 3 and 2 3 4 M37221M6 M37221M4 Internal 01716 O1BFis _ Not used 96 bytes for display See note 060016 CRT display RAM RAM 06B716 00016 Internal ROM area for program counter ROM ROM Internal ROM 24 K bytes 16 K bytes for for M37221M6 M37221M4 1FFFF16 Note Refer t
230. nes whether Pin H OUT output is synchronized with the video signal or not Bit 7 Field Frequency determination bit 50 60 This bit determines whether the field frequency is 50 Hz or 60 Hz According to the state of this bit the display position or a vertical direction size of video can be changed 7220 Group User s Manual APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 2 Write data register Write data register ps DO DBF 4 5 6 0 No function Fig 5 5 17 Map of write data register 7220 Group User s Manual 5 41 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP B DELAY ADJ This adjusts the RF AGC delay point The output level of tuner decreases when the value increase the output level increases when the value decreases POS NEG This switch sets the VIF output signal to either the positive or the negative modulation signal When 0 the negative modulation signal is selected when 1 the positive modulation signal is selected B VCO ADJ This register changes the free running frequency of VIF VCO The frequency increases when the value increases the frequency decreases when the value decreases B A MUTE This is the audio mute ON OFF 4 5 6 0 This bit must be set to 1 when the sound carrier frequency is 4 5 MHz Set 0 when the frequency is other values E DFA DL TIME In order to adjust the co
231. nnel open drain output output structure 0 CMOS output Ri iW bit P31S 1 N channel open drain output DA1 output enable bit 0 P30 input output R W DA1S 1 DA1 output 3 DA2 output enable bit 0 P3 input output Riw DA2S 1 DA2 output Nothing is assigned These bits are write disable bits 9 When these bits are read out the values are 0 Fig 4 5 9 Port output mode control register address 00CDi 4 18 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description 4 5 6 CRT Display function Table 4 5 5 shows the outline the CRT display function of the M37220M3 XXXSP FP Table 4 5 5 Outline of CRT display function Parameter Number of display character Dot structure Kinds of character Kinds of character sizes Performance 20 characters X 2 lines 12 dots X 16 dots 128 kinds 3 kinds 1 screen 4 kinds maximum 7 kinds A character Possible multiline display Possible maximum 7 kinds Kind of colors Coloring unit Display extension Raster coloring Color 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description OSC1 OSC2 VSYNC OO Address 00EA 16 control register Display oscillation circuit Addresses 00 1 16 00 216 Vertical position registers Address 00 416 Character size register Display position control circuit Address 00 016
232. nous clock output pin by the initialization program The receive side P2 is set as the serial I O data input pin and P2 is used for the serial synchronous clock external clock input pin by the initialization program Figure 2 7 8 shows the serial data transmit receive processing sequence using the above structure Transmit Side Receive Side Serial Mode Register Serial Mode Register b7 bo b7 50 TTE Internal synchronous clock selection bits Internal synchronious clock selection bits ind WEE ees Synchronous clock selection bit Synchronous clock selection bit 1 Internal clock 0 External clock Serial I O port selection bit a Serial port selection bit 1 SCLK SOUT E 1 SOUT Fix this bit to 0 Pid Fix this bit to 0 Transfer direction selection bit ne Transfer direction selection bit Serial input pin selection bit DEI E ee Serial input pin selection bit 2222 5 1 Input signal from SOUT pin Nothig is assigned d Nothig is assigned Synchronous clock 20 5 Serial data P21 SouT M37221M6 XXXSP FP M37221M6 XXXSP FP Fig 2 7 7 Connection example for serial I O transmit receive Transmit side Receive side 0C DC Set serial mode register 48 DC Set serial mode 2 FD Reset serial interrupt register request bit 2 FD Reset serial interrupt 2 FF Set the
233. nstruction instruction Internal clock Selection gate Connected to black side at reset T T34M2 XIN T34M Timer 34 mode register Fig 2 16 1 Clock generating circuit block diagram 2 100 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 17 Oscillation circuit 2 17 Oscillation circuit The M37221M6 XXXSP FP has a internal oscillation circuits used to obtain the clocks required for operation Ordinarily the frequency on clock input pin divided by 2 is the internal clock internal timing output A quartz crystal oscillator or ceramic resonator can be connected externally to these circuits 1 Oscillation circuit using a quartz crystal oscillator or ceramic resonator Figure 2 17 1 shows the circuit example using a quartz crystal oscillator or a ceramic resonator As shown in the diagram oscillation circuit can be constructed by connecting a ceramic resonator a quartz crystal oscillator between pins Xin and Xour In this case set the circuit constants for and Cour to the values recommended by the resonator manufacturer 2 External clock oscillation circuit Supplying an external clock is possible Figure 2 17 2 shows the circuit example M37221M6 XXXSP FP M37221M6 XXXSP FP External oscillation circuit Vcc vee Note In the stop mode keep the pin input signal at an level Fig 2 17 1 Clock osc
234. nt information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials e if these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporatio
235. nt source 0 Internal clock selection bit T34M4 1 t XiNy 2 5 Timer 3 external count 0 External clock from P23 TIM3 pin source selection bit 5 1 External clock from HsYNc pin 6 7 Nothing is assigned These bits are write disable 0 bits When these bits are read out the values are Fig 6 7 25 Timer 34 mode register Interrupt Input Polarity Register 67 b6 65 64 63 62 b1 00 DU DUM Interrupt input polarity register RE Address 00F9 16 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 INT1 polarity switch bit 0 Positive polarity RE3 1 Negative polarity polarity switch bit 0 Positive polarity RE5 1 Negative polarity Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 INT2 polarity switch bit 0 Positive polarity RE4 1 Negative polarity Fix this bit to 0 ie 1 Fig 6 7 26 Interrupt input polarity register Address 00 916 7220 Group User s Manual 6 47 APPENDIX 6 7 Control registers CPU Mode Register b7 b6 656463 b2b1 b0 ahlil lolo CPU mode register CPUM CM Address 00 16 S Name Functions Afterreset_ RW T Fix these bits to 0 70 2 Stack page selection 0 0 page Note 1 Riw bit CM2 1 1 page Indeterminate Note This bit is set to 1 after reset release Fig 6 7 27 CPU mode reg
236. nual 1 3 OVERVIEW 1 1 Performance overview Table 1 1 2 Performance overview 2 Parameter Subroutine nesting M37221M4 XXXSP M37221M6 XXXSP FP Performance 96 levels maximum M37221M8 XXXSP M37221MA XXXSP 128 levels maximum Interrupt External interrupt X 3 Internal timer interrupt 4 Serial interrupt X 1 CRT interrupt X 1 Multi master BUS interface interrupt X 1 f Xin 4096 interrupt X 1 Vsync interrupt X 1 BRK interrupt X 1 Clock generating circuit 2 built in circuits externally connected to a ceramic resonator or a quartz crystal oscillator Power source voltage 5 V 10 Power dissipation CRT ON 165 mW typ at oscillation frequency f Xw 8 MHz fort 8 MHz CRT OFF 110 mW typ at oscillation frequency 8 MHz In stop mode 1 65 mW maximum 12V withstand ports 6 LED drive ports 4 Operating temperature range 10 C to 70 C Device structure CMOS silicon gate process Package M37221M4 XXXSP M37221M6 XXXSP M37221M8 XXXSP M37221MA XXXSP 42 pin shrink plastic molded DIP M37221M6 XXXFP 42 pin shrink plastic molded SOP CRT display function Number of display characters 24 characters X 2 lines maximum 16 lines by software Dot structure 12 X 16 dots Kinds of characters 256 kinds Kinds of character sizes 3 kinds Kinds of character colors Maximum 7 kinds
237. o P6 70 M37221M6 XXXSP FP Mask ROM Ordering Confirmation Form 1 set Please use the pages P6 71 to P6 73 M27221MA XXXSP Mask ROM Ordering Confirmation From 1 set Please use the pages P6 74 to P6 76 M27220M3 XXXSP FP Mask ROM Ordering Confirmation From 1 set Please use the pages P6 77 to P6 79 Data to be written to mask ROM EPROM DIP Type 27C101 Please provide 3 sets containing the identical data GMark Specification Form 1 set Please use the pages P6 80 and P6 81 6 64 7220 Group User s Manual APPENDIX 6 11 Mask ROM ordering method GZZ SH10 10B lt 5980 gt 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221M4 XXXSP MITSUBISHI ELECTRIC Date Section head Supervisor signature signature Note Please fill in all items marked Submitted by Supervisor Company name Customer DA Issuance signature Date issued 1 Confirmation Specify the name of the product being ordered and the type of 5 submitted Three EPROMSs are required for each pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM
238. o Table 2 11 4 Contents of CRT display RAM Fig 2 2 1 Access area of M37221M4 XXXSP and M37221M6 XXXSP FP 2 8 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 2 Access area 000016 1000016 Internal RAM Zero 00 016 SFR area ROM 640 bytes 512 bytes Special function register i i for for 00 16 Refer to Figures 2 3 310 2 3 5 oa T rdispl y M37221MA 4 37221 8 4 01FF16 021716 021Bie 2 Page register 11FFF16 Not used 02 016 ROM correction ROM correction memory 02FF16 memory RAM Block 1 addresses 02C0 16 to 02DF16 030016 Block 2 addresses 02E016 to 02FF16 Internal RAM 033F16 y CRT display RAM 060016 RAM 96 bytes for display 06B716 See note 6000 Internal ROM area for program counter 800016 ROM ROM 40 K bytes 32 K bytes for for M37221MA M37221M8 Internal ROM FFDE16 Speci pecial page FFFFi6 Interrupt vector area 1 Note Refer to Table 2 11 4 Contents of CRT display RAM Fig 2 2 2 Access area of M37221M8 XXXSP and M37221MA XXXSP 7220 Group User s Manual 2 9 FUNCTIONAL DESCRIPTION 2 2 Access area 2 2 1 Zero page addresses 000016 to 00FF16 The 256 bytes from address 000016 to address 00FF16 are called zero page The internal RAM ports timer serial A D comparison PWM output CRT display and interrupt related registers all present within this
239. occurs when data Preparation for judging timeout transmit does not end within a certain period TRX 0 arbitration lost is such as timeout occurs 7 AL 1 detected error bit 6 at address 0009 16 0 or AL bit 3 at address 0009 16 z 1 No error 1 Not yet PIN bit 4 at address 00D9 16 1 1 byte data transmit completes 0 Completion of 1 byte data transmit Stop judging of timeout 1 No ACK bit 0 at address 0009 16 1 2 No ACK 0 ACK Store the next data to A The last byte Fig 5 4 6 Flowchart of data output processing routine 7220 Group Users Manual 5 25 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 5 5 Example of I C BUS control by software M37220M3 XXXSP FP Althogh the M37220M3 XXXSP FP has no multi master I C BUS interface it can control single master 12 BUS by software Most TV systems can be controlled in this way This paragraph explains transmit receive control example of a single chip color TV signal processor M52340SP adaptable to the I C BUS interface 5 5 1 Specifications Single chip color TV signal processor required M52340SP Number of transfer bits 8 bits Data format addressing format Pins required P2 P2o Direction of data transfer MSB first 5 5 2 Connection example 20 5 P21 Sour SCL Serial clock SDA Serial data M37220M3 XXXSP FP M52340SP
240. of stack S 1 If necessary execute the PLP instruction to pull the pushed PS contents In that case be Pushed PS sure to execute the NOP instruction immediately after the PLP instruction c m n Fig 6 3 2 Stack contents after PHP instruction execution Execute PLP instruction Execute NOP instruction Fig 6 3 3 Note when executing PLP instruction 6 4 7220 Group User s Manual 6 3 2 1 2 6 3 3 1 Notes on decimal operation How to execute arithmetic operation instructions in decimal operation mode To calculate in decimal notation set the decimal operation mode flag D to 1 by using the SED instruction and execute the ADC and SBC instructions After that execute at least one instruction to execute the SEC CLC or CLD instruction Status flags in decimal operation mode When the ADC or SBC instruction are executed in decimal operation mode D 1 the N V and Z flags are invalid The carry flag C is set to 1 when a carry occurs as a result of an arithmetic operation or is cleared to 0 when a borrow occurs Therefore the carry flag can be used to determine whether a carry a borrow has occurred or not Be sure to initialize the C flag before each arithmetic operation Notes on Interrupts Executing BBC or BBS instruction When executing the BBC or BBS instruction to an interrupt request bit immediately after this bit is set to 0 by using a da
241. oltage V is determined with the value n n decimal number in the DA conversion register V Vcc X n 0 to 63 64 The DA output does not build in a buffer so connect an external buffer when driving a low impedance load 7220 Group User s Manual DA1 output enable bit DA2 conversion register 6 address O0DF 16 Resistor ladder DA2 output enable bit P31 A D6 DA2 Table 4 5 4 Relationship between contents of D A conversion register and output voltage V A D control register Output bit 5 bit 4 bit 3 bit 2 bit 1 voltage V 0 0 0 0 0 0 64 0 0 0 0 0 1 64 Vcc 0 0 0 0 1 2 64 1 1 1 1 0 61 64 Vcc 1 1 1 1 1 62 64 Vcc 1 1 1 1 1 63 64 4 17 M37220M3 XXXSP FP 4 5 Functional description DA n Conversion Register b7 b6 b5 b4 b3 b2b1 60 DA conversion register DAn 1 and 2 Address 16 OODF 16 0 0 64Vcc 1 1 64Vcc 0 2 64 Vcc 1 61 64Vcc 0 62 64Vcc 1 63 64Vcc Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 4 5 8 DA n conversion register addresses 000 and OODF Port P3 Output Mode Control Register 67 b6 b5 64 b3 b2 b1 50 Port output mode control register P3S address 00CD16 Name Functions Atter reset reset 71 P P3o output structure CMOS output eee iW selection bit P30S 1 N cha
242. on functions with M37221M6 XXXSP FP except for part of functions This chapter explains the differences between M37220M3 XXXSP FP and M37221M6 XXXSP FP Therefore refer to the corresponding descriptions of M37221M6 XXXSP FP about the common functions The 8 bit microcomputer M37220M3 XXXSP FP has many additional functions for tuning system for TV Table 4 1 1 Performance overview 1 Parameter Number of basic instructions Performance 71 Instruction execution time 0 5 the minimum instruction execution time at 8 MHz oscillation frequency Clock frequency 8 MHz maximum Memory size ROM 12 K bytes RAM 256 bytes CRT ROM 4 K bytes CRT RAM 80 bytes Input Output ports POoc PO7 8 bit X 1 N channel open drain output structure can be used as PWM output pins INT input pins A D input pin P1o P17 8 bit X 1 CMOS input output structure be used as A D input pins INT input pin 20 P2 2 bit X 1 CMOS input output or N channel open drain output structure can be used as serial I O pins P22 P27 6 bit X 1 CMOS input output structure can be used as serial input pin external clock input pins 3 P34 2 bit X 1 CMOS input output or N channel output structure can be used as D A conversion output pins A D input pins P32 1 bit X 1 N channel open drain output structure P34 Input 2 bit X 1 can be used as CRT display clo
243. ons equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Fu
244. ontents of memory one bit to the left The iow order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag Branches when the contents of the bit specified in the accumulator or memory is 0 BBS Note 4 Ap or 1 Branches when the contents of the bit specified in the accumulator or memory is 1 Note 4 Note 4 BEQ Note 4 Note 4 Branches when the contents of carry flag is 0 Branches when the contents of carry flag is 1 Branches when the contents of zero flag is 1 AND s the contents of accumulator and mem ory The results are not entered anywhere Branches when the contents of negative is qv BNE Note 4 Branches when the contents of zero flag is 0 BPL Note 4 Branches when the contents of negative flag is p Jumps to address specified by adding offset to the program counter 5 5 5 1 5 5 5 1 5 5 5 5 1 PC AD Executes a software interrupt 7220 Group User s Manual 6 53 APPENDIX Addressing mode oen 1 n oP o spen 2 6 9 Machine instruction table ZP Y
245. ontrol system 16 FFEF16 FFDEt16 instruction interrupt L FFF016 VSYNC interrupt 016 FFF216 FFF316 f XiN 4096 interrupt FFF416 Internal ROM area imer 4 interrupt FFF616 FFF716 FFF816 L FFF916 INT3 interrupt 16 __ Multi master 2 C BUS interface interrupt FFFCte p H PA CRT interrupt Serial interrupt L FFFE16 FFFF16 Timer 3 interrupt Internal ROM area INT1 interrupt INT2 interrupt Reset Timer 1 interrupt F F F F F F F F F F Timer 2 interrupt EL 2a Interrupt Vector Table The low order 8 bits and the high order 8 bits of jump destination address when an interrupt occurs are stored to addresses L and H respectively Fig 2 5 10 Interrupt vector table 7220 Group Users Manual 2 33 FUNCTIONAL DESCRIPTION 2 6 Timers 2 6 Timers M37221M6 XXXSP FP has four 8 bit timers with reload latch Figure 2 6 1 shows the timer block diagram 1 4096 1 2 Timer 1 latch 8 P24 TIM2 Note 3 Hsync P23 TIM3 O Note 3 E m Timer 2 latch 8 Selection gate Connected to black side at reset gt 34 1 T12M Timer 12 mode register T34M Timer 34 mode register T34M4 T
246. orts The output structure is CMOS P53 G output P54 B CRT output Output Pins 52 55 are also used as CRT output pins G B OUT1 P5s OUT1 respectively The output structure is CMOS output Hsvwc Hsvwc input Input This is a horizontal synchronous signal input for CRT Vsync Vsync input Input This is a vertical synchronous signal input for CRT D A DA output Output This is a 14 bit PWM output pin The output structure is CMOS output 1 8 7220 Group User s Manual OVERVIEW 1 4 Functional block diagram iagram ional block di 4 Funct The functional block diagram is shown in Figure 1 4 1 1 M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP SGd 2 Gd 04 1ndino ae o OO 21090969 20 yooq jeuonoung uonounj VIN LZZZEN dSXXX 8INLZZSEN AlUO suod uod uod Od uod my GOBDODOINGD 606060626 OPCO DOON uonounj 0199109 519 021 JejSeu niniw Wid WrvL 8 0d 149 Jepooep uoionJisu jeuBis
247. ot set 2 3 Character size of block 2 Minimum size Indeterminate selection bits Medium size CS20 CS21 Large size Do not set Nothing is assigned These bits are write disable bits When these bits are read out the values 0 Fig 6 7 16 Character size register Address 00E416 7220 Group User s Manual 6 39 APPENDIX 6 7 Control registers Border Selection Register 67 b6 65 64 b3 62 b1 00 Border selection register MD Address 00 516 Indeterminate R W Block 1 OUT1 output 0 Same output as character output See note border selection bit MD10 1 Border output Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Nothing is assigned These bits are write disable bits 9 When these bits are read out the values 0 2 Block 1 OUT1 output 0 Same output as character output Indeterminate See note border selection bit MD20 1 Border output H Note M37220M3 XXXSP FP Block 1 OUT output 0 Same output as character output Indeterminate R 1 W border selection bit 010 1 Border output 2 Block 2 OUT output 0 Same output as character output Indeterminate W border selection bit 020 1 Border output Fig 6 7 17 Border selection register Address 00 516 6 40 7220 Group User s Manual APPENDIX 6 7 Control registers Color Register n b7 66 65 64 b3
248. oup User s Manual FUNCTIONAL DESCRIPTION 2 7 Serial Data bus 1 1 4 31 8 31 16 Selection gate SM2 Connected to black Clock source P20 latch generating circuit Serial interrupt P20 ScLKO e Serial I O counter 8 request SM Serial mode register SM3 P21 latch SM5 LSB lt MSB P21 SouTO 5 P22 SINC Serial I O shift register 8 Address 000016 8 Note When the data is set in the serial I O register address 000016 the register functions as the serial I O shift register Fig 2 7 1 Serial block diagram Serial Mode Register b7b6 b5b4b3 6261 60 HERE Serial I O mode register SM Address 00DC 16 0 1 Internal synchronous 1 bO RW clock selection bits SMO SM1 2 Synchronous clock selection bit SM2 3 Serial port 0 P20 P21 functions selection bit SM3 as port 1 SCLK SOUT Fix this bit to 0 5 Transfer direction 0 LSB first selection bit SM5 1 MSB first Serial input pin 0 Input signal from SIN pin selection bit SM6 1 Input signal from Sour pin 7 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 2 7 2 Serial mode register address 00DC c 7220 Group User s Manual 2 41 FUNCTIONAL DESCRIPTION 2 7 Serial 2 7 2 Serial I O register address 00006 The serial register is
249. pe used 27C101 EPROM address 000016 Product name ASCII code M37221MA 600016 data FFFF e ROM 40 K bytes 1000016 107FFi6 1080016 Character ROM 1 a Character ROM 2 a 10FFF is 1100016 1417FF Character ROM 1 b 1180016 Character ROM 2 b 11 FFFt6 1 1 Set FF e in the shaded area 2 Write the ASCII codes that indicates the product name of 37221 to addresses 0000 16 to 000 16 EPROM data check item Refer the EPROM data and check in the appropriate box Do you set FF 16 in the shaded area 2 Yes Do you write the ASCII codes that indicates the product name of 37221 to addresses 0000 16 to 000F 16 2 Yes 2 Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form 42P4B for M37221MA XXXSP and attach to the mask ROM confirmation form 3 Comments 1 3 6 74 7220 Group User s Manual APPENDIX 6 11 Mask ROM ordering method GZZ SH10 46B 5ZA0 SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221MA XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 000016 to 000 16 store the product name and addresses 10000 16 to 11 store the character pattern If the name of the prod
250. processing routine 5 29 Fig 5 5 6 Flowchart of data output processing 5 30 Fig 5 5 7 Flowchart of START condition processing routine 5 31 Fig 5 5 8 Flowchart of STOP condition processing routine 5 31 Fig 5 5 9 Flowchart of bus H processing 5 31 Fig 5 5 10 Flowchart of data input processing routine 5 32 Fig 5 5 11 Flowchart of return ACK processing routine 5 33 Fig 5 5 12 Flowchart of return NACK processing routine 5 33 Fig 5 5 13 Flowchart of power on 5 36 Fig 5 5 14 Flowchart of UP DOWN key input 5 37 Fig 5 5 15 Flowchart of picture memory switching key input processing 5 38 Fig 5 5 16 Status data 5 39 Fig 5 5 17 Map of write data register 5 41 Fig 5 6 1 Application circuit example 1 IPC BUS 5 45 Fig 5 6 2 Application circuit example 2 Non BUS chassis 5 46 CHAPTER 6 APPENDIX Fig 6 3 1 Initialization of flags in rennen nnns 6 4 Fig 6 3 2 Stack contents after PHP instruction execution 6 4 Fig 6 3 3 Note when executing PLP instruction 6 4 Fig 6 3 4 Note
251. r write signal SCL oe ee Hold time SDA Reset time for L BB flag Fig 2 8 10 STOP condition generation timing diagram Table 2 8 2 START condition STOP condition generation timing table Item Standard clock mode High speed clock mode Setup time 5 0 20 cycles 2 5 s 10 cycles Hold time 5 0 20 cycles 2 5 5 10 cycles Set reset time for BB flag 3 0 us 12 cycles 1 5 us 6 cycles Note Absolute time at 4 MHz The value in parentheses denotes the number of 4 cycles 2 58 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 3 START STOP condition detect conditions The START STOP condition detect conditions are shown in Figure 2 8 11 and Table 2 8 3 Only when the 3 conditions of Table 10 are satisfied a START STOP condition can be detected Note When a STOP condition is detected in the slave mode MST 0 an interrupt request signal IICIRQ is generated to the CPU SDA START condition SDA po om STOP condition Fig 2 8 11 START condition STOP condition detect timing diagram Table 2 8 3 START condition STOP condition detect conditions Standard clock mode 6 5 26 cycles lt SCL release time 3 25 s 13 cycles Setup time 0 5 us 2 cycles lt Setup time 3 25 s 13 cycles lt Hold time 0 5 2 cycles lt Hold time Note Absolute time at 4 MHz The value in parenthese
252. ranted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
253. rect Y 2 10 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 3 Memory assignment 2 3 Memory assignment Figures 2 3 1 2 3 2 show the memory assignment The ROM RAM and assigned in this memory area are described below M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP Hexadecimal notation Decimal notation 000016 0 Internal RAM SFR area Special function register Refer to Figures 2 3 3 and 2 3 4 Internal RAM Not used RAM for display 1000016 CRT display ROM 8 K bytes Zero page ROM for display RAM 320 bytes for M37221M4 4 384 bytes for M37221M6 00 016 11FFF16 00 16 010016 017 16 01 16 060016 06 716 A00016 CRT display RAM 96 bytes See note Not used 00016 Internal ROM ROM 24 K bytes for M37221M6 ROM 16 K bytes for M37221M4 65280 65502 65535 Interrupt vector area Special page Note Refer to Table 2 11 4 Contents of CRT display RAM 1FFFF16 131071 Fig 2 3 1 Memory assignment of M37221M4 XXXSP and M37221M6 XXXSP FP 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 3 Memory assignment Hexadecimal notation Decimal notation 00016 0 1000016 Internal Zero page 640 bytes 512 bytes Special function register for displa ud a OOFF 16 Refer to Figures 2 3 3 to 2 3 5 8 K bytes
254. rection register input mode COUNTER 0 P21 SCL 1 Wait 6 us P20 SDA 1 Carry flag 1 Carry flag 0 gt Rotate READDATA with Carry flag to left P21 SCL 1 BIT COUNTER lt BIT COUNTER 1 BIT COUNTER gt 8 Fig 5 5 10 Flowchart of data input processing routine 5 32 7220 Group User s Manual APPLICATION 5 5 Example of PC BUS control by software M37220M3 XXXSP FP 8 Return ACK processing routine Return ACK Bit 0 of port P2 direction register output mode P20 SDA 0 Wait 6 P21 SCL 1 Wait 6 P21 SCL 0 Fig 5 5 11 Flowchart of return ACK processing routine 9 Return NACK processing routine Return NACK Bit 0 of port P2 direction register output mode P20 SDA 1 Wait 6 P21 SCL 1 Wait 6 P21 SCL 0 RETURN Fig 5 5 12 Flowchart of return NACK processing routine 7220 Group User s Manual 5 33 APPLICATION 5 5 Example of I C BUS control by software M37220M3 XXXSP FP 5 5 5 Data setting according to key processing Examples of the M52340SP settings corresponding to each actual TV set key input are described below 1 Power ON OFF key input When power supply is supplied to the M52340SP by this input the data is set to all registers
255. register PWM3 PWM4 register PWM4 PWM output control register 1 PW PWM output control register 2 PN data shift register 50 address register SOD 2 status register 51 control register 510 clock control register 52 Serial mode register SM Serial register SIO state immediately after reset 1 State immediately after reset gt 0 0 immediately after reset 1 t immediately after reset Indeterminate immediately after reset State immediately after reset b7 50 2 0016 2 0016 2 0016 01010 1 0016 2 2 2 2 0016 2 0016 2 2 2 2 2 2 0016 0016 2 00 6 1 1012 0016 0016 0016 2 0016 0016 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 15 Reset Area addresses E016 to 16 State immediately after reset gt 0 immediately after reset 1 1 immediately after reset Indeterminate immediately after reset Address Register T State immediately after 19581 E016 Horizontal position register HR 116 Vertical position register 1 CV1 E21e Vertical position register 2 CV2 E316 E416 Character size register CS E516 Border selection register MD E616 Color register 0 COO E716 Color register 1 CO1 E816 Color register 2 CO2 E91
256. register address 021916 02416 of 01 at address 0218 16 lt 0 disabled ROM correction address 1 low order address 021 16 lt 02516 of E2PROM execution address Disable block 2 enable bit into ROM correction address 2 address 02 016 to O2FF 16 Store correction codes of ROM lt 02616 to 04516 of E2PROM correction function 2 into ROM correction memory 2 block 2 ROM correction enable register 61 at address 0218 16 1 enabled Enable block 2 enable bit Fig 5 3 6 General flowchart when using ROM correction function 7220 Group User s Manual 5 19 APPLICATION 5 3 Usage example of ROM correction function M37221M8 MA XXXSP 5 3 5 Notes on use When using the ROM correction function note the following OG Specify the first address op code address of each instruction as the ROM correction address e Use the RTS RTI or JMP instruction total of bytes to return from the correction program to the main program e Do not set the same address to ROM correction addresses 1 and 2 addresses 02176 to 021 5 20 7220 Group User s Manual APPLICATION 5 4 Example of I C BUS interface control M37221Mx XXXSP FP 5 4 Example of I C BUS interface control M37221Mx XXXSP FP The M37221Mx XXXSP FP has multi master 5 interface This interface offering both arbitration lost detection and synchronous functions is useful for the multi master serial communica
257. register the address register the status register control register and the clock control register are assigned to addresses 0007 000816 000916 000 and OODBi respectively registers consist of 8 bits The 120 data shift register is 8 bit shift register to store receive data and write transmit data The address register consists of a 7 bit slave address and a read write bit The C status register controls the I C BUS interface status The low order 4 bits are read only bits and the high order 4 bits can be read out and written to The control register controls data communication format The clock control register is used to set ACK control SCL mode and SCL frequency 2 3 7 Serial I O related registers addresses 000 0000 serial mode register is assigned to address 00 and the serial I O register is assigned to address O0DD e Both registers consist of 8 bits The serial mode register is used to select the synchronous clock and the serial port function by its low order 4 bits Bit 5 selects the transfer direction and bit 6 selects the serial data input pin Bit 4 is set to 0 Bit 7 is not used The serial I O register is used to write transfer data 2 3 8 CRT display related registers addresses 00 016 to OOECi 1 Horizontal position register address 00E016 The horizontal position register is assigned to address OOEO e This register con
258. roduct being ordered and the type of EPROMs submitted Three EPROMSs are required for each pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM el hexadecimal notation EPROM type indicate the type used 27C101 EPROM address 000016 Product name ASCII code 000 1 M37221M8 800016 data FFFF ie ROM 32 K bytes 1000016 107FFi6 1080016 10FFF e 1100016 117FF 6 1180016 Character ROM 1 b 11 1 Set FFs in the shaded area 2 Write the ASCII codes that indicates the product name of 37221 8 to addresses 000016 to 000 16 EPROM data check item Refer the EPROM data and check in the appropriate box Do you set FF ie in the shaded area 2 Yes Do you write the ASCII codes that indicates the product name of 37221 8 to addresses 000016 to 000F 16 Yes Character ROM 1 a Character ROM 2 a Character ROM 1 b 2 Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form 42P
259. rol register 2 status register Other control circuits The data transfer with the internal CPU is performed via data bus the data transfer with an external device is performed via ports 11 14 When using multi master I C BUS interface these ports 11 14 are assigned to the following functions P1 Multi master 12 interface Synchronous clock input output 1 SCL1 Multi master I C BUS interface Synchronous clock input output pin 2 SCL2 P1 Multi master I C BUS interface data input output pin 1 SDA1 P14 Multi master I C BUS interface data input output 2 SDA2 The shift clock to determine the transfer speed of serial data is selected by the I C clock control register refer to Figure 2 8 4 A serial data and a serial clock is referred as SDA SCL respectively hereafter 2 48 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 8 2 Multi master 5 interface related registers 1 data shift register S0 address 000716 The data shift register SO address 00716 is an 8 bit shift register to store receive data write transmit data When transmit data is written into this register it is transferred to the outside from bit 7 in synchronization with the SCL clock and each time one bit data is output the data of this register are shifted one bit to the left When data is received it is inp
260. rrupt enable bit 1 Interrupt enabled INT3 interrupt 0 Interrupt disabled enable bit IT3E 1 Interrupt enabled Note M37220M3 XXXSP FP Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 6 7 30 Interrupt control register 1 Address 00 16 7220 Group User s Manual 6 49 APPENDIX 6 7 Control registers Interrupt Control Register 2 b7 b6 656463 b2b1b0 olojo ol Interrupt control register 2 ICON2 Address OOFF 16 211201 BT Nee Funcions eres RI INT1 interrupt 0 Interrupt disabled enable bit IT1E 1 Interrupt enabled INT2 interrupt enable 0 Interrupt disabled bit IT2E 1 Interrupt enabled Fix this bit to 0 f XiN 4096 interrupt 0 Interrupt disabled enable bit MSE 1 Interrupt enabled Fix these bits to 0 R Serial I O interrupt 0 Interrupt disabled enable bit S1E 1 Interrupt enabled 7 Fig 6 7 31 Interrupt control register 2 Address OOFF16 ROM correction enable register b7 b6 b5b4b3 520100 ROM correction enable register RCR Address 021216 ee Block 1 enable bit RCRO 0 Disabled 1 Enabled 1 Block 2 enable bit RCR1 0 Disabled 1 Enabled Fix these bits to 0 EH Nothing is assigned These bits are write disable bits When these bits are read out the values 0 Fig 6 7 32 ROM correction e
261. rs DA n Conversion Register b7 b6 b5 b4 b3 b2b1 bO EM DA n conversion register DAn n 1 and 2 Address 000 16 OODF 16 0 0 64Vcc 1 1 64Vcc 0 2 64Vcc 1 61 64Vcc 0 62 64Vcc 1 63 64Vcc Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Horizontal Position Register b7 b6 65 64 b3 62 b1 00 Horizontal position register HR Address 00 016 Name Fue After reset reset Rw Horizontal display start NEL MM steps 0016 to 3F 16 positions HRO to HR5 Nothing is assigned These bits are write disable bits When thses bits are read out the values are 0 Fig 6 7 14 Horizontal position register Address 00 016 6 38 7220 Group User s Manual APPENDIX 6 7 Control registers Vertical Position Register n 67 b6 65 04 b3 b2 61 bO Vertical position register n 1 2 n 1 and 2 Addresses 00E1 16 00 216 Vertical display start positions 128 steps 0016 to 7F16 Indeterminate CV1 CV10 to CV16 CV2 CV20 to CV26 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fig 6 7 15 Vertical position register n Addresses 00 116 00 216 Character Size Register b7 b6 65 64 63 62 b1 00 Character size register CS Address 00E416 Minimum size Indeterminate R W selection bits Medium size CS10 CS11 Large size Do n
262. rs by OUT signal bit 5 Color Register n b7 b6 65 64 b3 b2 bi 00 Color register n COO to n 0 to 3 Addresses 00 16 to 00E916 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 B signal output 0 No character is output selection bit COn1 1 Character is outpu G signal output 0 No character is output R selection bit COn2 1 Character is outpu B signal output background 0 No background color is output selection bit COn4 1 Background color is output See note 1 OUT signal output 0 Character is outpu control bit 5 1 Blank is output See notes 1 2 signal output background 0 No background color is output selection bit COn6 1 Background color is output signal output background 0 No background color is output selection bit COn7 1 Background color is output See note 2 R signal output 0 No character is outpu R selection bit COn3 1 Character is outpu Notes 1 When bit 5 0 and bit 4 1 there is output same as a character or border output from the OUT pin Do not set bit 5 0 and bit 4 0 2 When only bit 7 1 and bit 5 0 there is output from the OUT2 pin Fig 5 2 1 Color register n M37221ERSS 7220 Group User s Manual 5 13 APPLICATION 5 2 Notes on programming for OSD M37220M3 XXXSP FP Color Register n 6
263. rther Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you
264. rupt request register 2 IREQ2 Interrupt control register 1 Interrupt control register 2 ICON2 Bit allocation gt Function bit No function bit o Fix this bit to 0 do not write 1 Fix this bit to 1 do not write 0 Bit allocation CV16 CV15 CV14 CV13 CV26 CV25 CV24 CV23 CO07 CO06 CO05 CO04 CO17 CO16 CO15 CO14 C027 CO26 CO25 CO24 CO37 CO36 CO35 CO34 0072 R G B ADC3 lo T12M4 12 Tt2M2 Tt2M1 12 0 34 5 2 T34M1 34 0 Fig 6 6 2 SFR assignment including internal state immediately after reset and access characteristics 2 M37221Mx XXXSP FP 6 22 7220 Group User s Manual State immediately after reset gt 0 0 immediately after reset 1 1 immediately after reset 2 Indeterminate immediately after reset State immediately after reset 7 60 20211917971 ee e o oe 0 0 0 0 2 2 21 oro o o o 0 0016 01000200010 0016 APPENDIX 6 6 SFR assignment Read enabled write enabled RO Read enabled write disabled Access characteristics RW RW RW RW RW RW RW RW
265. s 00E116 00E216 et display start positions 128 steps 0016 to 7F 6 Indeterminate R IW CV1 CV10 to CV16 CV2 CV20 to CV26 ME is assigned This bit is a write disable bit BE this bit is read out the value is 0 Fig 2 11 6 Vertical position register n addresses 00 116 and 00E2 e The horizontal direction is common to both blocks and can specify 64 step display positions 4 Tc per step Tc oscillation cycle for display by setting values 00 e to SF e to bits O to 5 of the horizontal position register address 00 016 Figure 2 11 7 shows the horizontal position register Horizontal Position Register 67 b6 65 b4 63 62 b1 00 Horizontal position register HR Address 00 016 ET ce Teen IE 6 7 Nothing is assigned These bits are write disable bits When thses bits are read out the values are 0 __ O Horizontal display start 64 steps 0016 3F 6 9 positions HRO to HR5 Fig 2 11 7 Horizontal position register address 00 016 2 76 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 2 Character size The size of characters to be displayed can select from 3 sizes for each block Set a character size by the character size register address OOE4 e The character size in block 1 can be specified by bits 0 and 1 of the character size register the character size in block 2 can be specified by bits 2 and 3 Figure 2 11 8 shows t
266. s an 8 bit port and has basically the same functions as 21 port PO The output structure is CMOS output 2 gt 5 External clock Input Pins 2 P24 also used as external clock input pins TIM3 TIM2 P23 TIM3 respectively P24 TIM2 Serial 2 pin is also used as serial synchronous clock input output pin 25 27 The output structure is N channel open drain output clock input output Serial data I O 21 P22 are also used as serial I O data input output pins Sour input output Sin respectively The output structure is N channel open drain output P3o A D5 port Ports 3 bit ports and have basically the same functions DA1 as port PO Either CMOS output or N channel open drain output structure P31 A D6 can be selected as the port P30 and P3 The output structure of port DA2 P32 P32 is N channel open drain output Analog input Input Pins are also used as analog input pins A D5 A D6 respectively P33 OSC1 Input port Input Ports P3s P3 are 2 bit input ports P34 OSC2 Clock input Input P3s pin is also used as CRT display clock input OSC1 CRT display Clock output for Output pin is also used as CRT display clock output OSC2 CRT display output structure is CMOS output P52 R Output port 5 Output Ports 52 55 are 4 bit output p
267. s denotes the number of cycles High speed clock mode 1 0 us 4 cycles lt SCL release time 7220 Group User s Manual 2 59 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 4 Address Data Communication There are two address data communication formats namely 7 bit addressing format and 10 bit addressing format The respective address communication formats is described below 7 bit addressing format To meet the 7 bit addressing format set the 10BIT bit of the control register address 00DA e to 0 The first 7 bit address data transmitted from the master is compared with the high order 7 bit slave address stored in the address register address 000816 At the time of this comparison address comparison of the RBW bit of the 2 address register address 0008 is not made For the data transmission format when the 7 bit addressing format is selected refer to Figure 2 8 12 1 and 2 Q 10 bit addressing format To meet the 10 bit addressing format set the 10BIT SAD bit of the I C control register address 00DA e to 1 An address comparison is made between the first byte address data transmitted from the master and the 7 bit slave address stored in the I C address register address 000816 At the time of this comparison an address comparison between the RBW bit of the address register address 0008 and the R W bit which is the last bit of the address data transmi
268. ses 0025 Color Register n 67 b6 b5 b4 b3 b2 61 00 Color register n COn n 0 to 3 Addresses 00 6 16 to 00 916 Nothing is assigned These bits are write disable bits 7 When these bits are read out the values are 0 After reset Indeterminate R W 0 Same output as character output 1 Border output 0 Same output as character output Indeterminate W 20 1 Border output 2 71070 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 B signal output selection bit COn1 2 Gsignal output selection bit COn2 R signal output selection bit COn3 OUT signal output control bit COn5 Nothing is assigned These bits are write disable bits 0 No character is 1 Character is ou 0 No character is 1 Character is ou 0 No character is 1 Character is ou 0 Character is ou 1 Blank is output output put output put output put When these bits are read out the values are 0 Fig 4 5 14 Color register addresses 00 1 to 0 9 6 4 24 7220 Group User s Manual ER RE R M37220M3 XXXSP FP 4 5 Functional description CRT Control Register b7 b6 65 b4 b3 b2 b1 00 CRT control register CC Address 16 ST reme 70107 All blocks display control 0 All blocks display off bit Note CCO 1 All blocks display on Block 1 display contro
269. signal output R OP6 1 MUTE signal output i 7 B signal output switch bit 0 B signal output Riw OP7 1 MUTE signal output Fig 2 11 17 CRT port control register address 00 2 R G B output polarity 0 Positive polarity switch bit R G B 1 Negative polarity 2 86 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 8 Raster coloring function R G B and OUT1 output can be switched to MUTE output MUTE output can color all displaying area raster of screen For example the case that pin B is specified for MUTE signal output is shown in Figure 2 11 18 When the MUTE signal is output from pin B the background of the entire screen is colored BLUE Then a character data is output from for example When B and signal outputs set to character is output by the color register at the character I output the output character is colored YELLOW RED mixed BLUE regardless of the OUT1 signal output When outputting the character O the output character is colored only RED that is not mixed BLUE by setting only R signal output to character is output However in this case set pin OUT1 to blank is output The TV image can be also erase by setting the all R G and B pins to MUTE output The MUTE signal is output from pin OUT1 output regardless of setting CRT display RAM for pin OUT1 Whether ordinary video signal o
270. sists of 8 bits and is used to specify the horizontal position of CRT display Bits 7 and 6 are not used 2 Vertical display position registers addresses 00 1 and 0022 The vertical display position register 1 is assigned to address 00 1 and the vertical display position register 2 is assigned to address 00 216 These registers are corresponded to blocks 1 and 2 and used to set the vertical position to start display Bit 7 of each register is not used 3 Character size register address OOE4 e The character size register is assigned to address 00 41 This register consists of 8 bits and is used to specify one of the three sizes of display characters Bits 4 to 7 are not used 7220 Group User s Manual 2 17 FUNCTIONAL DESCRIPTION 2 3 Memory assignment 4 Border selection register address O0E5 The border selection register is assigned to address 00256 This register consists of 8 bits and is used to set the border for blocks 1 and 2 by using one bit each Bits 1 and 3 to 7 are not used 5 Color registers addresses 00 to 00 916 Color registers 0 to are assigned to addresses 0 to 0029 6 color registers consist of 8 bits and are used to set character output blank output and character background color by CRT output B OUT1 Bit 0 is not used 6 CRT control register address 00 6 The CRT control register is assigned to address 00 1 This register consists of 8 bits
271. ss Register ate immediately after reset E016 Horizontal position register HR E116 Vertical position register 1 CV1 E216 Vertical position register 2 CV2 E316 E416 Character size register CS E516 Border selection register MD E616 Color register 0 COO E716 Color register 1 CO1 E816 Color register 2 CO2 E916 Color register 3 CO3 16 control register CC 16 CRT port control register CRTP EDie CRT clock selection register CK EE 6 A D control register 1 AD1 16 A D control register 2 AD2 F016 Timer 1 TM1 F116 Timer 2 TM2 2216 Timer F316 Timer 4 4 F416 Timer 12 mode register T12M F516 Timer 34 mode register T34M F616 PWMB register PWM5 F716 F816 F916 Interrupt input polarity register RE FA16 Test register TEST 6 CPU mode register 1 1 1 1 1 1 0 0 Interruptrequestregister1 IREQ1 0066 FD16 Interrupt request register 2 IREO2 0066 FE16 Interrupt control register 1 0 16 Interrupt control register 2 ICON2 Fig 4 5 18 Internal state immediately after reset 2 7220 Group User s Manual 4 27 M37220M3 XXXSP FP 4 6 Electrical characteristics 4 6 Electrical characteristics Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Vcc Power source voltage Vcc
272. ssing Main routine routine errors errors Fig 6 4 11 Watchidog timer by software 6 16 7220 Group User s Manual APPENDIX 6 5 Memory assignment 6 5 Memory assignment Hexadecimal notation Decimal notation 000016 0 lt 7 4 Internal RAM i CRT display RoM 1000016 8 K bytes Zero page ROM for display RAM 384 bytes for M37221M6 RAM 320 bytes for M37221M4 CRT display RAM ROM 24 K bytes for M37221M6 96 bytes See note ROM 16 K bytes for M37221M4 00C016 00FF16 010016 017F16 01BF16 060016 06B716 A00016 00016 Special function register Refer to Figures 2 3 3 and 2 3 4 Internal RAM Not used RAM for display Internal ROM 11FFF16 Not used 65502 65535 Interrupt vector area 65280 Special page 1FFFF16 131071 Note Refer to Table 2 11 4 Contents of CRT display RAM Fig 6 5 1 Memory assignment of M37221M4 XXXSP and M37221M6 XXXSP FP 7220 Group User s Manual 6 17 APPENDIX 6 5 Memory assignment Hexadecimal notation Decimal notation 20000 6 1000016 Internal P Zero page RAM RAM 00CO SFR area CRT display ROM ROM 640 bytes 512 bytes Special function register for displa or d fus 00 16 Refer to Figures 2 3 3 to 2 3 5 8 K bytes isp ay M37221MA 1 M37221M8 w me 1FF 11FFF16 021B eee ROM correction ROM correction memory 02FF memory RAM Block 1
273. st register 2 IREQ2 Address 007016 INT1 interrupt 0 No interrupt request issued ERES request bit ITIR 1 Interrupt request issued 1 INT2 interrupt 0 No interrupt request issued request bit IT2R 1 Interrupt request issued i request bit S1R 1 Interrupt request issued 3 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 f XIN 4096 interrupt 0 No interrupt request issued Rx request bit MSR 1 Interrupt request issued 5 6 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 Fix this bit to 0 k 0 can set by software but 1 cannot be set Fig 6 7 29 Interrupt request register 2 Address 00FD16 Interrupt Control Register 1 b7 b6 b5b4b3 6261 60 Interrupt control register 1 ICON1 Address 16 E re interrupt Interrupt disabled enable bit TM1E Interrupt enabled Timer 2 interrupt Interrupt disabled enable bit TM2E 1 Interrupt enabled Timer 3 interrupt 0 Interrupt disabled enable bit TM3E 1 Interrupt Timer 4 interrupt 0 Interrupt disabled enable bit TM4E 1 Interrupt enabled CRT interrupt enable 0 Interrupt disabled bit CRTE 1 Interrupt enabled Vsync interrupt 0 Interrupt disabled enable bit VSCE 1 Interrupt enabled Multi master I C BUS interface 0 Interrupt disabled inte
274. stopped Timer operating 2 __pSX _ 9 4 MHz is stopped Note 1 at f Xin 8 MHz Notes 1 The following interrupts are invalid in the wait mode 1 Vsync interrupt 2 CRT interrupt 3 Timer 2 interrupt that count source is supplied from pin P24 TIM2 4 Timer 3 interrupt that count source is supplied from pin P23 TIM3 Fig 2 14 4 State transitions of low power dissipation mode 2 94 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 15 Reset 2 15 Reset To reset the microcomputer applied LOW level to pin RESET for 2 us or more Reset is released when HIGH level is applied to pin RESET and the program starts from the address indicated with the reset vector table 2 15 1 Reset operation If pin RESET is returned to an HIGH level after being held LOW for 2 us or more when the power source voltage is within the recommended range 4 5 V to 5 5 V timers 3 and 4 are connected by hardware with internally reset state internal timing signal is not supplied At this time FF e is set to timer and 0716 is set to timer 4 Timer counts down f Xin 16 as its count source timer 4 counts down the timer 3 overflow signal even when the device is in internally reset state is continuously supplied to timer 3 The internal reset is released by timer 4 overflow and the program is started from an address determined with the contents of address FFFF e as high order address and contents of ad
275. subishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1997 MITSUBISHI ELECTRIC CORPORATION 7220 Group User s Manual 241 NE SAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REVISION DESCRIPTION LIST 7220 GROUP USER S MANUAL Rev Revision Description Rev No date First Edition 9708 Information about copywright note revision number release date added last page 971130 1 1
276. t 2 93 Fig 2 14 4 State transitions of low power dissipation mode 2 94 vi 7220 Group User s Manual List of figures Fig 2 15 1 Timing diagram at 2 95 Fig 2 15 2 Internal state immediately after reset 1 2 96 Fig 2 15 3 Internal state immediately after reset 2 2 97 Fig 2 15 4 Internal state immediately after reset 3 only M37221M8 MA XXXSP 2 98 Fig 2 15 5 Voltage at poweron reset nennen ennt nennen 2 99 Fig 2 15 6 Example of reset circuit eene nenne nnnm 2 99 Fig 2 15 7 Example of reset circuit 2 2 99 Fig 2 16 1 Clock generating circuit block 2 100 Fig 2 17 1 Clock oscillation circuit using a ceramic 2 101 Fig 2 17 2 External clock input circuit 2 101 Fig 2 17 3 Clock oscillation circuit for CRT 2 101 CHAPTER 3 ELECTRICAL CHARACTERISTICS Fig 3 1 1 Definition diagram of timing on multi master I C BUS sss 3 5 CHAPTER 4 M37220M3 XXXSP FP Fig 4 2 1 Pin configuration top view 1 4 4 Fig 4 2 2 Pin configuration top view 2 eene nnns 4 5 Fig 4 4 1 Functional block diagram uu eee ene i reer nre
277. t Note The fonts and size of characters are standard Mitsubishi type Mitsubishi IC catalog name Mitsubishi iot number 6 digit or 7 digit UUUUUUUUUUUUUUUUUUUUUC Note1 The mark field should be written right aligned 2 The fonts and size of characters are standard Mitsubishi type 3 Customer s parts number can be up to 15 characters Only 0 9 A Z amp period comma are usable 4 f the Mitsubishi jogo is not required check the box on the right Mitsubishi logo is not required C Special Mark Required Note If the special mark is to be printed indicate the desired layout of the mark the upper figure The layout will be duplicated as close as possible Mitsubishi lot number 6 digit or 7 digit and mask ROM number 3 digit are always marked 2 the customer s trade mark logo must be used in the special mark check the box below Please submit a clean original of the logo For the new special character fonts a clean font original ideally logo drawing must be submitted Special logo required The standard Mitsubishi font is used for all characters except for a logo 6 80 7220 Group User s Manual APPENDIX 6 12 Mark specification form 42P2R A 42 PIN SHRINK SOP MARK SPECIFICATION FORM Please choose one of the marking types below A B C and enter the Mitsubishi catalog name and the special mark if needed A Standard Mitsubishi Mark
278. t When displaying a character block with the CRT display function the CRT interrupt request occurs at the completion of the display INT2 interrupt An INT2 interrupt request is generated by detecting a level transition on pin INT2 external interrupt input Detecting either positive polarity LOW to HIGH transition or negative polarity HIGH to LOW transition is set with RE4 the interrupt input polarity register bit 4 at address 9 6 When is set to 0 a positive polarity is detected when RE4 is set to 1 a negative polarity is detected The INT2 pin is also used for port POs and pin A D4 An INT2 interrupt by a level transition on the may cause software runaway Therefore when this pin is used as port POs disable an INT2 interrupt by using an interrupt enable bit and the interrupt disable flag 1 INT1 interrupt An INT1 interrupt request is generated by detecting a level transition on pin INT1 external interrupt input Detecting either positive polarity LOW to HIGH transition or negative polarity HIGH to LOW transition to be detected is set with RES the interrupt input polarity register bit at address 00 916 When is set to 0 a positive polarity is detected when is set to 1 a negative polarity is detected Pin INT1 is also used for port P07 An INT1 interrupt by a level transition on the may cause software runaway Therefore when this pin is used as port PO
279. t is selected as the OUT1 pin output Whether blank output or not is selected as the OUT2 pin output Color Register n 67 b6 65 64 63 b2 61 00 Color register n COO to 0 to Addresses 00 616 to 00 916 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 B signal output 0 No character is output Riw selection bit COn1 1 Character is output G signal output 0 No character is output R w selection bit COn2 1 Character is output signal output 0 No character is output R Ww selection bit COn3 1 Character is outpu B signal output background 0 No background color is output Riw selection bit COn4 1 Background color is output See note 1 i OUT1 signal output 0 Character is outpu R Ww control bit COn5 1 Blank is output See notes 1 2 G signal output background 0 No background color is output selection bit COn6 1 Background color is output signal output background 0 No background color is output selection bit COn7 1 Background color is output note 2 Notes 1 When bit 5 0 and bit 4 1 there is output same as a character or border output from the OUT pin Do not set bit 5 0 and bit 4 0 2 When only bit 7 1 and bit 5 0 there is output from the OUT2 pin Fig 2 11 12 Color register n addresses 00 6 to 00 916 2 82 7220 Group User s Manual FUNCTIONAL DESCRIPTI
280. t port read data several times by a program for checking whether input levels are equal or not As for an output port since the output data may reverse because of noise rewrite data to its data register at fixed periods Rewrite data to direction registers and pull up control registers only the product having it at fixed periods When a direction register is set for input port again at fixed periods a several nanosecond short pulse may be output from this port If this is undesirable connect a capacitor to this port to remove the noise pulse Fig 6 4 10 Setup for I O ports 7220 Group User s Manual 6 15 APPENDIX 6 4 Countermeasures against noise 6 4 6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing The main routine Assigns a single byte of RAM to a software watchdog timer S
281. t the interrupt request bit to 1 interrupt enabled Fig 6 3 6 Sequence for switching an external interrupt detection edge 6 3 4 Notes on serial 1 Initialization for the serial For the serial interrupt initialize as Figure 6 3 7 Clear the serial interrupt enable bit to 0 interrupt disabled 2 Write transmit data to transmit buffer When an external clock is used as the synchronous clock for the clock synchronous Select the serial I O mode serial I O write the transmit data to the serial set the serial I O port selection bit to 1 shift register at HIGH of the transfer clock input level or more instructions Clear the serial I O interrupt request bit to 0 no interrupt request issued Set the serial I O interrupt enable bit to 1 interrupt enabled Fig 6 3 7 Initialization for serial 6 6 7220 Group User s Manual APPENDIX 6 3 Notes on use 6 3 5 Notes on timer When a timer value is read the timer value at read timing 1 may be read Reason Figure 6 3 8 shows the relation between timer values and their values read Timer values are changed at the rising edge of the count source but the values read are counted down at the falling edge of the count source Therefore the timer value 1 may be read in some read timings Figure 6 3 9 shows the relation between timer values and their values read when two 8 bit timers are connected
282. t voltage Fade Ra dea 4 17 Table 4 5 5 Outline of CRT display function enne 4 19 Table 4 5 6 Character code table be omitted 4 22 Table 4 5 7 Contents of CRT display 4 22 CHAPTER 5 APPLICATION Table 5 5 1 Data setting at tuning and 2 5 34 Table 5 5 2 Data setting at volume UP DOWN key 5 34 Table 5 5 3 Data setting at screen size related keys 5 34 Table 5 5 4 Data setting at picture data control key and picture memory switching key eme 5 34 Table 5 5 5 Data setting when changing AFT state 5 35 Table 5 5 6 Data setting when changing audio mute state 5 35 Table 5 5 7 Data setting when changing video mute state 5 35 Table 5 5 8 Data setting when adjusting white 5 35 Table 5 5 9 Relationship between DFA and DL 5 42 Table 5 5 10 Setting of color system at sub address 091 write data 5 43 CHAPTER 6 APPENDIX Table 6 2 1 Termination of unused PINS 6 3 7220 Group User s Manual
283. ta transfer instruction execute one or more instructions before executing the BBC or BBS instruction Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 the value of the interrupt request bit before being cleared to 0 is read 1 data transfer instructions LDM LDA STA STX and STY instructions APPENDIX 6 3 Notes on use Set the decimal mode flag D to 1 Execute ADC SBC instruction Execute NOP instruction Execute SEC CLC or CLD instruction Fig 6 3 4 Note in decimal arithmetic operation Clear the interrupt request request distinguish bit to 0 no interrupt issued NOP one or more instructions Execute BBC or BBS instruction Fig 6 3 5 Execution of BBC or BBS instruction 7220 Group User s Manual 6 5 APPENDIX 6 3 Notes on use 2 How to switch an external interrupt detection edge For the products able to switch the external interrupt detection edge switch it as Figure 6 3 6 Clear an interrupt enable bit to 0 interrupt disabled Reason The interrupt circuit recognizes the switching Switch the detection edge of the detection edge as the change of external input signals This may cause an unnecessary Clear an interrupt request bit to 0 interrupt d no interrupt request issued Se
284. tate immediately after reset gt 8 Function bit 0 0 immediately after reset 1 immediately after reset No function bit 2 Indeterminate immediately tact after reset Fix this bit to 0 do not write 1 Fix this bit to 1 do not write O Address Register Bit allocation TT State immediately after bere 7 b7 E016 Horizontal position register HR 4 HR2 HR1 HRO 0016 116 Vertical position register 1 CV1 feviecvisevidovisiovidoviilovio 0 2 2122 2 2 2 E216 Vertical position register 2 CV2 cvee cves cved cvescvzzovasi ovo 0 2 2 2 2 2 2 EB E416 Character size register CS 0 11 510 0 0101 017 2 21 2 2 E516 Border selection register MD 0 0 72 0 2 E616 Color register 0 COO CO07 006 CO05 CO04 0016 E716 Color register 1 CO1 15 014 0016 E816 Color register 2 CO2 027 CO26 025 024 CO22 0016 E916 Color register C037 CO36 035 034 032 0016 EA16 CRT control register CC CC2 0016 16 2 16 CRT port control register 6 OPS OUT OUT2 R G B 0016 ED16 CRT clock selection register 010000010 0016 16 A D control register 1 0 1 0 21 01 01 0 EF16 A D control register 2 AD2 ADC5 ADC4 ADC3 0016 FO1e Timer 1 1 FF 6 F116 Timer 2 TM2 0
285. ter reset release Write 5516 to port P2 direction register 00C416 Port P2 Port P2 direction register 00 516 Port P2 direction register Fig 2 3 6 setting example of port 2 16 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 3 Memory assignment 2 3 3 DA registers addresses and 00 6 The DA H register is assigned to address 00 and the DA L register is assigned to address OOCF e Both registers consist of 8 bits The DA H register is used to set the high order 8 bits of 14 bit PWM output data The DA L register is used to set the low order 6 bits of 14 bit PWM output data set to bits O to 5 Bits 7 is not used 2 3 4 PWM registers addresses 0000 00D4 e and 00 6 The PWMO to PWMA registers are assigned to addresses 0000 to 00D4 e and PWM5 register is address OOF6 e All registers consist of 8 bits These registers are used to set the output data corresponding to six 8 bit PWM PWMO PWM5 2 3 5 PWM output control registers addresses 0005 5 and 000616 The PWM output control register 1 is assigned to address 00D5 e and the PWM output control register 2 is assigned to address 00D6 e Both registers consist of 8 bits and used to select the PWM count source etc The high order 3 bits and the low order 2 bits of the PWM output control register 2 are not used 2 3 6 Multi master I C BUS related registers addresses 0007 to 00086 The 1 data shift
286. tern stored in one address In other words two addresses 16 bits are used for one character The ROM can store up to 256 kinds of characters 7220 Group User s Manual 2 19 FUNCTIONAL DESCRIPTION 2 4 Input Output pins 2 4 Input Output pins The M37221M6 XXXSP FP has 33 programable ports I O ports input ports output ports The double function ports function as ports and as pins for internal peripheral devices M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP Double function ports lt ports POo PO0 P1o P 17 2 24 P30 P3 Input ports 3 P34 Output ports 52 55 port only ports lt ports 25 27 P32 And also the M37221M6 XXXSP FP has 9 pins with only the dedicated function Dediated 5 Vcc Vss RESET Xin CNVss Xour D A Hsync Vsync 2 4 1 Programmable ports 1 Port PO 2 20 Port PO is an 8 bit input output port This is an N channel open drain output Port PO is assigned to memory at address 00 016 on zero page Port PO has the direction register at address 00C1 e on zero page so that it is possible to program each bit whether the port is used for input or output The pins of which the direction register is programmed to 0 are set for input when programmed to 1 the pins are set for output When pins are programmed as output pins the output data are wri
287. terrupt control register 2 are not used 2 3 15 2 page register addresses 0217 to 0218 only M37221M8 XXXSP and M37221MA XXXSP 1 ROM correction addresses address 021716 to 021 A16 Addresses 0217 e to 021A e are assigned to ROM correction address The ROM data addresses to be corrected are set to the ROM correction addresses 2 ROM correction enable register address 021 The ROM correction enable register is assigned to address 021B e This register consist of 8 bits and controls the ROM correction function Bits 2 to 7 are not used 2 3 16 CRT display RAM addresses 060016 to 06B716 The display RAM is used to specify the character to be displayed on the and its color Two addresses are used for one character one address 8 bits to specify each character code and the other 8 bits to specify the color of the character 2 3 17 ROM addresses 00016 to FFFF s The mask ROM is assigned In this internal ROM addresses FFDE e FFDF e FFE416 FFF5 e and FFF8 e to FFFFie are assigned to vector area for reset and for interrupts A vector jump destination storage address 16 bits are stored in 2 addresses by the 1 interrupt source 2 3 18 CRT display ROM addresses 10000 to 11FFFic The display ROM stores masks character patterns of each character to be displayed on the CRT Although one character consists of 16 vertical x 12 horizontal dots it is divided into a 16 x 8 dot and a 16 x 4 dot pattern with each pat
288. ters C Data Shift Register 67 66 65 6463 b2 6160 data shift register 50 Address 000716 s e Pr DO to D7 This is an 8 bit shift register to store Indeterminate R W receive data and write transmit data Note write data into the data shift register after setting the MST bit to 0 slave mode keep an interval of 8 machine cycles or more Fig 6 7 7 data shift register Address 00D716 12 Address Register b7 b6 b5 b4 b3 b2 b1 bO 2 address register SOD Address 000816 Functions After reset R W E Read write bit 0 Read RBW 1 Write 1 Slave address The address data transmitted from to SADO to SAD6 the master is compared with the 7 contents of these bits Fig 6 7 8 address register Address 000816 7220 Group Users Manual 6 33 APPENDIX 6 7 Control registers 2 Status Register b7 b6 b5 b4 b3 b2 b1 bO 2 status register 51 Address 000916 Last receive bit LRB 0 Last bit 0 See note 1 Last bit 1 General call detecting flag 0 No general call detected ADO See note 1 General call detected Slave address comparison 0 Address mismatch flag AAS See note 1 Address match 3 Arbitration lost detecting flag 0 Not detected AL See note 1 Detected I2C BUS interface interrupt Interrupt request issued request bit PIN interrupt request issued Bus busy
289. the Shift instruction or Rotate instruction This flag is set to 1 by using the SEC instruction and is cleared to 0 by using the CLC instruction 2 Zero flag Z inti Bit 1 This flag is set to 1 when the result of an arithmetic operation or a data transfer is 0 and is cleared to 0 by any other result This flag has no meaning in the decimal mode 3 Interrupt disable flag 1 Bit 2 This flag disables interrupts When this flag is 1 all interrupts except the interrupt and reset are disabled This flag immediately becomes 1 when an interrupt is received This flag is set to 1 by using the SEI instruction and is cleared to 0 by using the CLI instruction 4 Decimal operation mode flag D Bit 3 This flag determines whether addition and substruction are performed in binary or decimal notation Binary arithmetic is performed when this flag 1 0 and decimal arithmetic is performed with treating each word as a 2 digit decimal when this flag is 1 Decimal adjust is performed automatically at this time This flag is set to 1 by using the SED instruction and is cleared to 0 by using the CLD instruction Only the ADC and SBC instructions are used for decimal arithmetic Since this flag directly affects calculations always initialize it after a reset 5 Break flag B esee Bit 4 This f
290. the character code 80 16 to FF 6 to addreses 11000 16 to 11FFF e gt SINGLE CHIP MICROCOMPUTER M37221M6 XXXSP FP b7 be bs bs 62 b bo H D APPENDIX 6 11 Mask ROM ordering method F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 6 73 APPENDIX 6 11 Mask ROM ordering method GZZ SH10 46B lt 5740 gt SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221MA XXXSP MITSUBISHI ELECTRIC Date Section head Supervisor signature signature Note Please fill in all items marked Submitted by Supervisor Company name Customer ok Issuance signature Date issued 1 Confirmation Specify the name of the product being ordered and the type of EPROMs submitted Three EPROMs are required for each pattern If at least two of the three sets of EPROMs submitted contain identical data we will produce masks based this data We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data Thus extreme care must be taken to verify the data in the submitted EPROMs Checksum code for entire EPROM vei hexadecimal notation EPROM type indicate the ty
291. the end of the first line display the line counter value will be 2 Therefore the 3rd line display data must be set from the end of the 1st line display to the start of the 3rd line display Then the line counter value is incremented and becomes 3 Figure 5 1 7 shows the example of the setup timing for the line counter and the display character data Line counter value End of the 1st line display The 1st line block 1 interrupt T ine counter value Set 3rd line display data by the start of 3rd line display The 2nd line block 2 p The 3rd line block 1 Line counter value 3 Start of the The 4th line block 2 3rd line display The 11th line block 1 The 12th line block 2 Fig 5 1 7 Example of setup timing for line counter and display character data 7220 Group User s Manual 5 7 APPLICATION 5 1 Example of multi line display 5 1 6 Processing time When setting display data by a CRT interrupt the processing time is limited As shown in Figure 5 1 7 a CRT interrupt occurs at the end of the first line block 1 display and setting for the 3rd line display is started This setting must be completed before a scanning line reaches to the 3rd line display position If the setting is not completed display characters flicker or rewriting is looked And also for multi line display of 12 lines be sure that CRT interrupts occur 12 times from a Vsvwc to the
292. the picture data when changing the picture mode B DEFEAT This switch turns DEFEAT off when AFT is on and vice versa B TV EXT This selects either a TV s signal or an external device s signal This bit should be set to 0 when TV s signal is selected and set to 1 when an external device s signal is selected B AUTO This determines whether the automatic determination of the color system is used or not When AUTO is 0 manual determination is set when 1 determination is performed automatically 3 58 NTSC SECAM When setting AUTO bit 5 at sub address 06 e write data to 1 these bits are automatically set inside the M52340SP When setting AUTO to 0 it is necessary to set the data shown in Table 5 5 10 according to the color system Table 5 5 10 Setting of color system at sub address 0916 write data Color system D2 D1 DO 3 58 NTSC SECAM PAL 0 0 0 SECAM 0 0 1 NTSC3 58 1 1 0 NTSC4 43 0 1 0 PHASE The picture s horizontal position is adjusted Data is given every 50 Hz or 60 Hz and the data is set when frequency changes For wide TVs etc data is given for each screen size mode and the data is set when the screen size mode changes DRIVE DRIVE Data is used to adjust the output amplitude ratio of R G and B signals Since G is the fixed data its ratio is adjusted by R and B MUTE This is the video mute ON OFF switch CUT OFF CUT OFF CUT OFF
293. thmetic operation accumulator contents M contents of the memory specified by the addressing of the arithmetic operation When the T 1 M1 M 1 M2 indicates arithmetic operation m contents of memory specified directly with index register X M2 contents of the memory specified by the addressing of the arithmetic operation Overflow flag V eere Bit 6 This flag is set to 1 when an overflow occurs in the result of an arithmetic operation involving signs An overflow occurs when the result of an addition or subtraction exceeds 127 7F e or 128 8046 The CLV instruction clears the overflow flag to 0 There is no instruction for setting this flag to 1 When the BIT instruction is executed except the above bit 6 of the memory executed by the BIT instruction is set to the overflow flag This flag has no meaning in decimal mode Note Overflows do not occur when the result of an addition or subtraction is smaller than the above numerical values or an addition is performed between different signs Negative flag een Bit 7 This flag is set to 1 when the result of a data transfer or arithmetic operation is negative bit 7 is 1 When the BIT instruction is executed bit 7 of the memory executed by the BIT instruction is set to the negative flag This flag can be used to determine whether the results of arithmetic operations are positive or
294. ting in such a way execute the STP instruction The stop mode is set by executing the STP instruction In this mode the address to fetch the instruction next to the STP instruction is output to the address bus and the oscillation stops with HIGH state of the internal clock At this time the timer overflow signal is further connected to timer 4 Value FF e is automatically set to timer 3 value 07 e is automatically set to timer 4 Immediately before executing the STP instruction process the following sequence Store registers accumulator index registers etc in the CPU to internal RAM Disable timers and 4 interrupts TM4E 0 Clear timers and 4 count stop bits to 0 T34M2 T34M3 0 When an interrupt is used for return from the stop mode enable that interrupt by clearing the interrupt disable flag to 0 and setting the interrupt enable bit to 1 Set bit 0 of the timer 34 mode register address OOF5 e to 0 TM34MO0z 0 to select f Xin 16 as the timer 3 count source Oscillation is restarted return from the stop mode by accepting reset input or interrupt request of INT1 INT2 or INT3 When the interrupt request is accepted the interrupt processing routine is executed Note however that the internal clock is not supplied to the CPU until timer 4 overflows after the interrupt request is accepted This is because a finite time is required for stabili
295. tions This paragraph explains transmit receive control example of E7PROM M6M80012P adaptable to the I C BUS interface For details on the I C BUS interface refer to 2 8 Multi master I C BUS interface 5 4 1 Specifications E PROM required M6M80012P Synchronous clock internal clock Standard clock mode 100 kHz Number of transfer bits 8 bits Data format addressing format Pins required SCL1 SDA1 Direction of data transfer MSB first 5 4 2 Connection example P11 SCL1 P13 SDA1 SCL Serial clock SDA Serial data M37221Mx XXXSP M6M80012P lt Master gt lt Slave gt Fig 5 4 1 Connection example 7220 Group User s Manual 5 21 APPLICATION 5 4 Example of I C BUS interface control M37221Mx XXXSP FP 5 4 3 functions 1 Byte write Bytes are written by sending the START condition slave address 016 sub address 1 byte data 1 byte and the STOP condition from the master Writing to the E7PROM will be started after the master sends the STOP condition that is in synchronization with a rising edge of the SDA signal This writing will be automatically terminated by the on chip sequential controller In this period no acknowledge bits are generated Figure 5 4 2 shows the byte write timing Bus operation of Slave master side address W Sub address n Data n m m SDA signal S W Bus operation of slave side K START condition
296. tiow 007316 Counting down count At read access Reading the contents of timer 2 Fig 2 3 7 Access to timer registers 2 18 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 3 Memory assignment 2 3 11 Timer mode registers address 00 416 and 00F516 The timer 12 mode register is assigned to address OO0F4 e and the timer 34 mode register is assigned to address OOF5 e Both registers consist of 8 bits They select the count source of timer and control the count stop bit Bits 5 to 7 of the timer 12 mode register and bits 6 7 of the timer 34 mode register are not used 2 3 12 CPU mode register address 00FB16 The CPU mode register is assigned to address OOFBis This register consists of 8 bits and specifies the stack page Set bits O and 1 are set to 0 and set bits 3 to 7 to 0 2 3 13 Interrupt request registers addresses 00 and OOFDi The interrupt request register 1 is assigned to address 00 16 and the interrupt request register 2 is assigned to address OO0FD e Both registers consist of 8 bits and hold content of each interrupt request bit Bits 3 and 5 to 7 of the interrupt request register 2 are not used 2 3 14 Interrupt control registers addresses OOFEis and 00FF16 The interrupt control register 1 is assigned to address OOFE e and the interrupt control register 2 is assigned to address OOFF e Both registers consist of 8 bits and sets enable disable of interrupts Bits 7 to 5 and 3 of the in
297. tively When clearing the corresponding bits of the port P5 direction register address O0CB e to 0 the pins are set for CRT output pins when setting to 1 the pins are set for general purpose port P5 Pin PUT2 is also used for port 1 When clearing bit 7 of the CRT control register address OOEAte to 0 the pin is set for port when setting to 1 the pin is set for pin OUT2 Immediately after reset release because the port P5 direction register is reset they become output pins R G B and OUT Bits 0 to 4 of the CRT port control register address O0EC e can determine Hsvwc and Vsync input polarity and B OUT1 and OUT2 output polarity When clearing corresponding bits to 0 positive polarity is selected when setting to 1 negative polarity is selected Figure 2 11 17 shows the port control CRT Port Control Register 67 b6 65 64 63 b2 61 60 CRT port control register CRTP Address 16 ST m te Te Hsync input polarity d Positive polarity Switch bit HSYC Negative polarity Vsync input polarity Positive polarity switch bit VSYC Negative polarity OUT2 output polarity 0 Positive polarity Switch bit OUT2 1 Negative polarity OUT output polarity 0 Positive polarity Switch bit OUT1 1 Negative polarity R signal output switch bit 0 signal output 5 1 MUTE signal output G signal output switch bit 0 G
298. to confirm the data being output from the D A output pin by reading the DA register The contents of the 8 bit PWM register and DA register are indeterminate after reset 2 64 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 10 PWM 2 10 2 14 bit PWM DA output The 14 bit PWM automatically outputs a PWM rectangular waveform from the D A pin by writing high order 8 bits of the output data to the DA H register and the low order 6 bits to the DA L register Data of the DA H register are transferred to the 14 bit PWM circuit when writing to the DA L register The following explains the output operation of 14 bit PWM rectangular waveform when 8 MHz The repeat cycle 4 096 us of output waveform is divided into 25 64 smaller interval t t 64 us The t is further divided into the minimum resolution bit of 28 256 x 0 25 ps HIGH duration of the fundamental waveform is determined by the high order 8 bits of the DA latch HIGH duration time X when f Xw 8 MHz 0 25Du ps Because the values are 0 to 255 the HIGH duration can be selected a total of 256 The smaller interval tm with a longer HIGH level area by t is specified by the low order 6 bits of the DA latch The t is specified from among 64 smaller intervals to to tes Therefore a rectangular waveform consisted of 2 kind waveforms with different HIGH duration are output from pi
299. tput For the output structure of ports P30 P31 either CMOS output or N channel open drain output is selected In the case of N channel open drain output the block diagram is the same as below PO6 INT2 A D4 PO7 INT1 N channel open drain output Direction register Data bus Port latch O indicates a pin Fig 2 4 1 I O pin block diagram 1 2 24 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 4 Input Output pins P33 OSC1 P34 Input Internal circuit D A P52 R P53 G P54 B P55 OUT1 CMOS output Internal circuit HSYNC VSYNC Schmidt input HSYNC or VSYNC O indicates a pin Fig 2 4 2 I O pin block diagram 2 7220 Group Users Manual 2 25 FUNCTIONAL DESCRIPTION 2 5 Interrupts 2 5 Interrupts Interrupts are used in the following cases When there is a request to execute a higher priority routine than current processing routine When it is necessary to process according to a certain timing The M37221M6 XXXSP FP has 14 interrupt sources including reset These are vector interrupts with a fixed priority sequence Table 2 5 1 shows the interrupt sources vector addresses and the interrupt priority sequence M37220M3 XXXSP FP Refer to CHAPTER 4 M37220M3 XXXSP FP Table 2 5 1 Interrupt sources vector addresses and priority 22 44 Vector addresses Priority Interrupt sources High order byte Low order b
300. tput or N channel open drain output structure can be selected by bit 0 or 1 of the port output mode control register address 00CD e When 1 N channel open drain output structure is selected when 0 CMOS output structure is selected Port P32 has only port function The output structure is N channel open drain output Port P3 has basically the same function as port PO Ports P30 and are also used as analog input pins A D5 and A D6 respectively Ports P3s and P34 are also used as CRT display clock input pins OSC1 and 0502 respectively Pin OSC1 is a clock input for CRT display OSC2 is a clock output for CRT display The output structure of pin OSC2 is CMOS output Port P5 Ports P52 P5s are 4 bit output ports The output structure is CMOS output Ports 52 55 are also used as CRT output pins R B OUT1 respectively Pins R G B and OUT1 are CRT output pins When setting each bit of the port P5 direction register to 0 the pins function as CRT output pins when setting to 1 the pins function as general purpose output ports The output structure of CRT output pin is CMOS output structure 7220 Group User s Manual 2 21 FUNCTIONAL DESCRIPTION 2 4 Input Output pins Table 2 4 1 List of programmable port functions Ports Functions except port 0 05 0 5 PWM output POs INT2
301. tructure 12 X 16 dots Kinds of characters 128 kinds Kinds of character sizes 3 kinds Kinds of character colors Maximum 7 kinds R G B can be specified by the character Display position horizontal vertical 64 levels horizontal X 128 levels vertical 7220 Group User s Manual 4 3 37220 3 4 2 Pin configuration 4 2 Pin configuration The pin configurations are shown in Figures 4 2 1 and 4 2 2 HSYNC P52 R VSYNC P53 G POo PWMO P54 B PO1 PWM1 P55 OUT PO2 PWM2 38 P20 SCLK P21 SOUT PO4 PWMA P22 SIN P05 PWM5 Pio PO6 INT2 A D4 P11 PO7 INT1 P12 P23 TIM3 P13 P24 TIM2 P14 P25 P15 A D1 INT3 P26 P16 A D2 P27 P17 A D3 D A P30 A D5 DA1 P32 P31 A D6 DA2 dSXXX EINOCCZEIN CNVss XIN XOUT Vss Fig 4 2 1 Pin configuration top view 1 4 4 Package type 42P4B 7220 Group User s Manual RESET OSC1 P33 OSC2 P34 Vcc HSYNC VSYNC POo PWMO PO1 PWM1 PO2 PWM2 P04 PWM4 P05 PWMS5 POe INT2 A D4 PO7 INT1 P23 TIM3 P24 TIM2 P25 P26 P27 D A P32 CNVss XIN XOUT Vss M37220M3 XXXSP FP 4 2 Pin configuration d4xXxXX NOccZEIN Package type 42P2R A Fig 4 2 2 Pin configuration top view 2 7220 Group User s Manual 52 P53 G P54 B P55 OUT P20 SCLK P21 SOUT P22 SIN P10 P11 P12 P13 P14 P15 A D1 INT3 P16 A D2 P17 A D3 P30 A D5 DA1 P31 A D6 DA2 RESET
302. tted from the master is made In the 10 bit addressing mode the R W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit When the first byte address data matches the slave address the AAS bit of the 1 C status register address 0009 6 is set to 1 After the second byte address data is stored into the I C data shift register address 00D7 e make an address comparison between the second byte data and the slave address by software When the address data of the 2nd byte matches the slave address set the RBW bit of the address register address 00081 to 1 by software This processing can match the 7 bit slave address and R W data which are received after a RESTART condition is detected with the value of the 12 address register address 00086 For the data transmission format when the 10 bit addressing format is selected refer to Figure 2 8 12 3 and 4 Slave address R W Data Data 7 bits 0 1 to 8 bits 1 to 8 bits 1 A master transmitter transmits data to a slave receiver Slave address R W Data Data 7 bits vale 1 to 8 bits 1 to 8 bits 2 A master receiver receives data from a slave transmitter Slave address Slave address _ 1517 bits RAY 2nd byte Data Data 7 bits 0 8 bits 1 to 8 bits 1 to 8 bits aster tr
303. tten into the port latch and then output When reading data from the output pins the output pin level is not read but the port latch data is read This allows a previously output value to be read correctly even if the output LOW voltage has risen for example because a light emitting diode was directly driven The input pins float so the values of the pins can be read When writing data into the input pin it is written only into the port latch while the pin remains floating Ports 0 05 are also used as PWM output pins 5 respectively Port POs is also used as external interrupt pin 2 and analog input A D4 The pin is also used as external interrupt input pin INT1 When external interrupts INT1 and INT2 are enabled an interrupt is processed according to transition in the level on these pins Ports POs and P0 have the schmit characteristics when they are used as INT input pins In this case set these pins for input by the port PO direction register 7220 Group User s Manual 2 3 4 5 FUNCTIONAL DESCRIPTION 2 4 Input Output pins Port P1 Port P1 is an 8 bit I O port The output structure is CMOS output however only when ports 1 P14 are used as multi master I C BUS interface the output structure is N channel open drain output Port P1 has basically the same function as port PO Port P1o is also used as CRT output pin OUT2 Pin OUT2 is a output pin When setting 1
304. uct contained in the does not match the name on the mask ROM confirmation form the ROM processing is disabled Write the data correctly 1 Inputting the name of the product with the ASCII code Address Address ASCII codes 37221 are listed on the right 000016 M 4 D se 00086 2D e The addresses and data are in hexadecimal notation 00016 S9 3316 000916 FF 16 000216 D 37 16 000 1 FF 46 000316 2 23216 00016 000416 2 293216 000 16 FF 46 000516 17 231 16 000016 FF 46 000616 4016 000 1 FF 16 000716 4 1 16 000F 16 FF 46 2 Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2 For the character ROM data see the next page and on 2 3 7220 Group User s Manual 6 75 APPENDIX 6 11 Mask ROM ordering method GZZ SH10 46B 52 0 gt SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE CHIP MICROCOMPUTER M37221MA XXXSP MITSUBISHI ELECTRIC The structure of character ROM divided of 12 X16 dots font
305. ued interrupt request bit _ 1 Interrupt request issued ES interrupt No interrupt request issued request bit IT3R 1 Interrupt request issued 0 can be set by software but 1 cannot be set Fig 2 5 3 Interrupt request register 1 address 6 Interrupt Request Register 2 b7 b6 656463 626160 DEM BN Interrupt request register 2 IREQ2 Address 00 t6 INT1 interrupt 0 No interrupt request issued EM request bit ITIR 1 Interrupt request issued 1 INT2 interrupt 0 No interrupt request issued request bit IT2R 1 Interrupt request issued 3 Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 4 f XiN 4096 interrupt 0 No interrupt request issued request bit MSR 1 Interrupt request issued 2 Serial I O interrupt 0 No interrupt request issued request bit S1R 1 Interrupt request issued 5 6 Nothing is assigned These bits are write disable bits When these bits are read out the values are 0 0 can be set by software but 1 cannot be set Fig 2 5 4 Interrupt request register 2 address 00 6 2 30 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 5 Interrupts Interrupt Control Register 1 b7 b6 656463 6261 60 Interrupt control register 1 ICON1 Address 16 8 Fonos ter eset RW Timer 1 interrupt 0 Interrupt disabled
306. up User s Manual 4 8 M37220M3 XXXSP FP 4 5 Functional description 4 5 Functional description Functions of M37220M3 XXXSP FP are partially different from those of M37221M6 XXXSP FP Table 4 5 1 shows the difference between M37220M3 XXXSP FP M37221M6 XXXSP FP Table 4 5 1 Difference between M37220M3 XXXSP FP and M37221M6 XXXSP FP Paramater M37220M3 XXXSP FP M37221M6 XXXSP FP Programmable ports 33 33 Port PO 8 bits 8 bits Port P1 8 bits 8 bits Functions except port are partially different Port P2 8 bits 8 bits Port P3 8 bits 8 bits Functions except port are partically different Port P5 4 bits 4 bits Interrupts No multi master I C BUS There is multi master 05 interface interrupt interface interrupt Priority level is the same as M37221M6 XXXSP FP D A converter Included Multi master 5 interface 2 6 bit resolution Included 1 2 systems CRT disp lay function Number of display characters 20 characters X 2 lines 24characters X 2 lines Kinds of characters 128 kinds 256 kinds Kinds of character back ground colors Not available 7220 Group User s Manual Possible It can be specified by the character Maximum 7 kinds 4 9 M37220M3 XXXSP FP 4 5 Functional description 4 5 1 Access area Figure 4 5 1 shows the M37220M3 XXXSP FP access area 192 bytes 4 K bytes ROM Zero page ytes for displa
307. upt enable bit and each interrupt disable flag 1 Assume for example that all interrupts CRT Vsync Timer 1 are enabled When the multiple interrupt is not set these interrupt request bits are set to 1 and the interrupts are determined by hardware as follows CRT interrupt Vsyne interrupt Timer 1 interrupt Figure 5 1 8 shows the timing of interrupt processing when not setting multiple interrupts The flag is set to 1 all interrupts are disabled automatically by hardware as soon as the interrupt processing starts Unless the flag is cleared to 0 other interrupt will not occur during the interrupt processing interrupt request bit VSYNC interrupt request bit Timer 1 interrupt request bit CRT interrupt processing VSYNC interrupt processing Timer 1 interrupt processing Interrupt disable flag 1 Fig 5 1 8 Timing of interrupt processing when not setting multiple interrupts 7220 Group User s Manual 5 9 APPLICATION 5 1 Example of multi line display 2 When setting multiple interrupts Various priority processings are executed by enabling multiple interrupts and by setting priorities by software For example to set the priority listed below 1 interrupt interrupt CRT interrupt execute the following process Set only interrupt enable bits ICON1 ICON2 whose priorities are higher than the current interrupt and enable the interrupt disable flag 1 in only th
308. ure 2 8 7 shows the interrupt request signal generating timing Figure 2 8 8 shows the status register Note The START condition duplication prevention function disables the START condition generation reset of bit counter reset and SCL output when the following condition is satisfied a START condition is set by another master device sec p qq dq M PIN IICIRQ Fig 2 8 7 Interrupt request signal generating timing 2 Status Register 67 b6 65 64 b2 bi 60 2 status register S1 Address 000916 Last receive bit LRB 0 Last bit 0 See note 1 Last bit 1 General call detecting flag 0 No general call detected ADO See note 1 General call detected Slave address comparison 0 Address mismatch flag AAS See note 1 Address match 3 Arbitration lost detecting flag 0 Not detected AL See note 1 Detected 4 12 interface interrupt 0 Interrupt request issued 1 request bit PIN 1 No interrupt request issued 5 Bus busy flag BB 0 Bus free 1 Bus busy 6 7 Communication mode b7 b6 specification bits 0 Slave recieve mode TRX MST 0 1 Slave transmit mode 1 0 Master recieve mode 1 1 Master transmit mode Note These bits and flags can be read out but cannnot be written Fig 2 8 8 status register 7220 Group User s Manual 2 57 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 8 3 START condition STOP condition gener
309. ut to this register from bit 0 in synchronization with the SCL clock and each time one bit data is input the data of this register are shifted one bit to the left C data shift register is a write enable status only when the ESO bit of the 2 control register address 00DA e is 1 The bit counter is reset by a write instruction to the 2 data shift register When both the ESO bit and the MST bit of the status register address OOF9 e are 1 the SCL is output by a write instruction to the data shift register Reading data from the I C data shift register is always enabled regardless of the ESO bit value Figure 2 8 2 shows the data shift register I C Data Shift Register 67 06 65 64 63 62 bi bd data shift register S0 Address 000716 DO to D7 This is an 8 bit shift register to store Indeterminate R IW receive data and write transmit data Note i write data into the data shift register after setting the MST bit to slave mode keep an interval of 8 machine cycles or more Fig 2 8 2 data shift register 7220 Group User s Manual 2 49 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 2 PC address register SOD address 000816 12 address register address 00D8 e consists of a 7 bit slave address and a read write bit In the addressing mode the slave address written in this register is compared with the address data to
310. utputs or MUTE signal outputs from pins R G and B is controlled by bits 5 to 7 of the CRT port control register refer to Figure 2 11 17 RED BLUE Signals across A A Fig 2 11 18 MUTE signal output example 7220 Group User s Manual 2 87 FUNCTIONAL DESCRIPTION 2 11 CRT display function 2 11 9 Clock for display As a clock for display to be used for CRT display it is possible to select one of the following 4 types Main clock supplied from the pin Main clock supplied from the Xin pin divided by 1 5 Clock from the LC or RC supplied from the pins OSC1 and OSC2 Clock from the ceramic resonator or quartz crystal oscillator supplied from the pins OSC1 and OSC2 This clock for display can be selected by the CRT clock selection register address OOED e When selecting the main clock set the oscillation frequency to 8 MHz CRT Clock Selection Register b7 b6 b5 b4 b3 b2 b1 bO CRT clock selection register CK Address 00ED16 gt i forfora selection bits The clock for display is supplied by connecting RC CKO CK1 or LC across the pins OSC1 and OSC2 1 Since the main clock is used as the clock for CRT oscillation display the oscillation frequency is limited frequency Because of this the character size in width f Xin horizontal direction is also limited In this S case pins OSC1
311. voltages 0 3106 V Vi Input voltage CNVss based on Vss 0 3 to 6 V Vi Input voltage P0c P0 P1o P17 P2c Output transistors 0 3 to Vcc 0 3 V P27 P30 P34 OSC1 are cut off Hsync Vsync RESET Vo Output voltage POs P07 P1o P17 0 3 to Vcc 0 3 V P27 P3c P35 B OUT D A OSC2 Vo Output voltage 0 05 0 3 to 13 V lou Circuit current B OUT 1 17 0 10 1 1 2 2 P31 D A lout Circuit current B OUT1 POs PO 0 to 2 Note 2 mA P1o P1 2 2 3 P32 D A love Circuit current 0 05 0 to 1 Note 2 mA lous Circuit current P24 P27 0 to 10 Note 3 mA Pa Power dissipation 550 mW Operating temperature Ta 25 10 1070 C Storage temperature 40 to 125 C Notes 1 The total current that flows out of the IC must be 20 mA max 2 The total input current to IC 101 1012 must be 30 mA or less 3 The total average input current for ports P24 P27 to IC must be 20 mA or less 4 28 7220 Group User s Manual M37220M3 XXXSP FP 4 6 Electrical characteristics Recommended operating conditions Ta 10 to 70 C Vcc 5 V 10 unless otherwise noted Symbol Parameter Min Typ Max Unit Voc Power source voltage Note 4 During CPU CRT operation 4 5 5 0 5 5 V Vss Power source voltage 0 0 0 V
312. way When an undefined op code is input to the CPU as an instruction code during operation of the M37221M6 XXXSP FP the following processing is done The CPU generates an undefined instruction decoding signal The device is internally reset because of occurrence of the undefined instruction decoding signal As a result of internal reset the same reset processing as in the case of ordinary reset operation is done and the program restarts from the reset vector Note however that the software runaway detecting function cannot be invalid Address Reset sequence Undefined instruction decoding signal occurs 7 TT Internal reset signal occurs Undefined instruction decode Invalid PC counter S Stack pointer ADL ADH Jump destination address of reset Fig 2 13 1 Sequence at detecting software runaway detection 2 90 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 14 Low power dissipation mode 2 14 Low power dissipation mode The M37221M6 XXXSP FP has 2 low power dissipation modes the stop mode and the wait mode 2 14 1 Stop mode The M37221M6 XXXSP FP allows the oscillation of to be stopped with keeping all states of registers except timers 3 and 4 input output ports and internal RAM Therefore the M37221M6 XXXSP FP can be restarted with the same state where oscillation was stopped and as a result the power dissipation can be greatly reduced To stop oscilla
313. with Philips IIC BUS standard Master transmission Master reception Slave transmission Slave reception 16 1 kHz to 400 kHz at 2 4 MHz Communication mode SCL clock frequency System clock f Xin 2 Note We are not responsible for any third party s infringement of patent rights or other rights attributable to the use of the control function bits 6 and 7 of the 120 control register at address 00DA16 for connections between the I C BUS interface and ports SCL1 SCL2 SDA1 SDA2 7220 Group User s Manual 2 47 FUNCTIONAL DESCRIPTION 2 8 Multi master l C BUS interface 12C address register Ss ran a It mill circuit IICIRQ Address comparator EN Serial Noise ii Data data elimination control SDA circuit circuit w 12 data shift register spen MST TRX BB PIN AL 12 status circuit register Internal data bus Noise Clock elimination control b7 b d b7 4 ircui ircui 10BIT srt cit js fee 2 12 clock control register 510 control register Clock division System clock 0 Fig 2 8 1 Block diagram of multi masteer I C BUS interface 2 8 1 Construction of multi master interface The multi master l C BUS interface consists of the following address register data shift register 2 clock control register cont
314. y 00 016 SFR area Special function register OOFF Refer to Figures 4 5 3 and 454 Internal RAM 64 bytes 013 16 7 060016 CRT display 256 bytes 000016 1000016 Internal RAM CRT display ROM 80 bytes for display Note D00016 068316 Internal ROM area for program counter Internal ROM ROM 12 K bytes FFDE16 FFFF16 Interrupt vector area 006 Special page 1FFFF16 131071 Note Refer to Table 4 5 7 Contents of CRT display RAM Fig 4 5 1 Access area 4 10 7220 Group User s Manual M37220M3 XXXSP FP 4 5 Functional description 4 5 2 Memory assignment Figure 4 5 2 shows the memory assignment M37220M3 XXXSP FP Hexadecimal notation Decimal notation 000016 0 1000016 Internal RAM 192 bytes CRT display ROM 4 K bytes 00 016 SFR area 192 Zero page Special function register 10 16 5 ROM for display d RAM 256 bytes 00FF16 Refer to Figures 4 5 3 and 4 5 4 255 NG Internal RAM 5 64 bytes L013F 6 9 CRT display RAM 060016 RAM 80 bytes for display Note 068316 200016 Internal ROM ROM 12 K bytes erga remet vector area Interrupt vector area FFFF16 TRO 65535 FF00 65280 Special page 1FFFFi6 131071 Note Refer to Table 4 5 7 Contents of CRT display Fig 4 5 2 Memory assignment 7220 Group User s Manual 4 11 37220 3
315. y Register 67 b6 65 64 63 62 b1 00 Interrupt input polarity register RE Address 007916 Nothing is assigned This bit is a write disable bit Indeterminate When this bit is read out the value is 0 INT1 polarity switch bit 0 Positive polarity 1 Negative polarity INT2 polarity switch bit 0 Positive polarity REA 1 Negative polarity R INT3 polarity switch bit 0 Positive polarity R RE5 1 Negative polarity Nothing is assigned This bit is a write disable bit When this bit is read out the value is 0 Fix this bit to 0 Fig 2 5 7 Interrupt input polatiry register address 00 916 port control register 67 b6 65 64 b3 b2 61 00 CRT port control register CRTP Address 00EC 16 CET ees em Hsync input polarity 0 Positive polarity R Switch bit HSYC 1 Negative polari 1 Vsync input polarity 0 Positive polarity switch bit VSYC 1 Negative polari 2 B output polarity 0 Positive polarity switch bit R G B 1 Negative polari 3 OUT2 output polarity 0 Positive polarity switch bit OUT2 1 Negative polari 4 1 output polarity 0 Positive polarity Switch bit OUT1 1 Negative polarity 5 Rsignal output switch bit 0 R signal output Riw 5 1 MUTE signal output signal output switch bit 0 G signal output R OP6 1 MUTE signal output 7 signal output sw
316. yte Remarks 1 Reset Note FFFF e FFFE e Non maskable 2 interrupt FFFD e FFFC e 3 INT2 interrupt FFFB e FFFA Active edge selectable 4 INT1 interrupt FFF9 e FFF8 e Active edge selectable 5 Timer 4 interrupt FFF5 e FFF4 e 6 f Xin 4096 interrupt FFF3 e 216 7 Vsync interrupt 116 FFFO0 e Active edge selectable 8 Timer 3 interrupt FFEF e FFEE e 9 Timer 2 interrupt FFEDis 10 Timer 1 interrupt FFEB e 11 Serial interrupt FFE9 e FFE8 e 12 Multi master l C BUS interface interrupt FFE7 e FFE6 e 13 INT3 interrupt FFE5i6 FFE416 Active edge selectable 14 BRK instruction interrupt FFDF e Non maskable software interrupt Note Reset are included in the table because it operates in the same way as interrupts These 14 source 14 vector interrupts have the priority sequence as shown in Table 2 5 1 reset has a higher priority than interrupts When two or more interrupt requests occur at the same sampling point the interrupt with the higher priority in order of 1 to 14 is received This priority sequence is determined by hardware but priority processing is possible to be varied by software by using the interrupt enable bit and the interrupt disable flag 2 26 7220 Group User s Manual FUNCTIONAL DESCRIPTION 2 5 Interrupts 2 5 1 Interrupt sources The following explains interrupt sources in order of priority except reset 1 2 3 4 S 6 CRT interrup
317. zation 52 address 0008 16 110001012 510 address 00DA 16 010010002 bit6 at address OOFE 16 lt 0 51 address 0009 16 000100002 A lt Slave address W A0 16 Data output 1 address 0009 16 lt 001000002 address 1 16 Data output TRX bit 6 at address 000916 60 ACK BIT bit 6 at address 00DB 16 lt 0 mmediately before he last receive byte ACK BIT bit 6 at address 0008 16 lt 1 S0 address 0007 16 lt FF16 Preparation for judging of timeout To Timeout See note 2 interrupt enable bit Bus busy flag Communication mode specification bit ACK bit I2C BUS interface interrupt request bit Restart condition BB TRX ACK BIT PIN Disable multi master 2C BUS interface RS Setting for outputting the START condition in data output processing routine 009 Transmit the START condition slave address W and sub address Transmit the RESTART condtion and slave address Set to receive mode Set ACK return mode Set to non ACK return mode End of reception of he last receive byte Yes After data is received no acknowledge bits are generated but the STOP condition is sent by the master completing this read operation Input start Set dummy data to generate clock No PIN bit
318. zing of oscillation when an external quartz crystal oscillator etc is used When the internal clock is supplied to the CPU the CPU executes the interrupt routine At this time the address for the first byte of the instruction next to the STP instruction is pushed to the stack as a return address Also note that the timers 3 and 4 interrupt request bits are remained setting to 1 Therefore clear each bit to 0 in the interrupt routine Enable one of the INT1 INT2 and interrupts to use interrupts for restarting oscillation before the executing STP instruction described in amp above Table 2 14 1 State in stop mode Item State in stop mode Oscillation Stops CPU Stops Internal clock Stops at HIGH level ports State where STP instruction is executed is held Timer CRT display functions Stops 7220 Group User s Manual 2 91 FUNCTIONAL DESCRIPTION 2 14 Low power dissipation mode Time to hold internal reset state approximately 32768 cycles of XIN input Stop mode Oscillation stabilizing time 2 us or more 4 Note Y Execute STP instruction Returned by reset input Fig 2 14 1 Oscillation stabilizing time at return by reset input IWhen returning from stop mode by using INT1 interrupt rising edge selected Oscillation stabilizing time Stop mode 32768 oes XIN System clock Ula UU

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