IPI, PLC CPU Module, GFK
Contents
1. 00 00 00 00 00 00 00 00 00 00 43 50 55 4C 49 4E CPULIN 4B 2E 43 4F 44 00 2D 62 00 36 34 00 2D 74 00 32 K COD b 64 t 2 30 30 00 00 43 50 55 4C 49 4E 4B 2E 44 43 42 00 O00 CPULINK DCB 00 4E 55 4C 4C 3A 00 4E55 4C 4C 3A 00 4E 55 4C NULL NULL NUL 4C 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 L 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Le eee 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee Once the binary file CPU ENV above is created use termf to load CPU ENV to the PCM Then execute a soft reset of the PCM After executing the soft reset the PCM s backplane communications timeout should be 10 seconds Note A copy of the above CPU ENV file can be obtained from the Electronic Bulletin Board Service BBS CPU ENV can be found in the conference library of PLC PCM and is named CPU ENV CAUTION The CPU ENV file will not be used when a hard reset is performed on the PCM With the CPU ENV file resident in the PCM a soft reset must be per formed after every hard reset of the PCM Be aware that it is possible to is sue a soft reset COMMREQ from the Ladder Diagram application there fore the application can be modified to handle the required reset of PCMs after a power cycle of the PLC system Important Product Information PLC CPU Module GFK 1289B July 15 1996 Notice to Upgrade GBC Hardware With the introduction of new features in CPU Release 5 00 timings w2. 12 Important Product Information PLC CPU Module July 15 1996 GFK 1289B FIP Device Status References F_rsnnn With the addition of FIP I O to the Release 6 00 IC697 CPU FIP device status references are included These FIP device status references are analogous to the Module status references provided for use with IC66 bus based devices M_rsbmm FIP device status references take the form F_rsnnn where F indicates this is a FIP device status reference r indicates the VME rack number of the FIP Bus Controller s indicates the VME slot number of the FIP Bus Controller nnn indicates the node id of the FIP I O nest The FIP device status references are to be used with the FAULT and NOFLT contacts to determine if an I O nest on the FIP I O network has a fault condition Interrupt Blocks Calling Other Blocks Previous releases of the IC697 PLC CPU have not permitted calls to other blocks from within an LD block configured as an I O or Timed Interrupt Block This restriction has been removed with Release 6 00 14 P oint Interrupt Module Support for the IC697 14 point Interrupt Module has been incorporated into the Release 6 00 IC697 PLC CPU Use of the 14 point Interrupt Module with prior versions of the IC697 PLC CPU required application support from within the user s logic program to interface with and control the 14 point Interrupt module This support is now in the CPU firmware Note When upgrading to IC697 CPU Release 6 00
3. must be scheduled and complete execution every sweep Programs with intervals greater than 1 are scheduled based on their interval but execution of any given program need only complete prior to its next interval time to be scheduled A program with interval 2 does not necessarily run 1 2 the program in one sweep and 1 2 in the next and a program with interval 3 does not necessarily run 1 3 of its execution across 3 sweeps Note The prior execution of a given program must complete before that same program can be scheduled for its next execution If the program did not complete its prior execution then at the time is to be scheduled a fault will be logged and the program will not be scheduled on this interval Multiple SNP Sessions The Release 6 00 IC697 PLC CPU now supports multiple logical connections through the CPU s built in serial port This functionality is provided in conjunction with the Host Communications Toolkits to permit multiple user applications running in the same host computer to communicate serially SNP with the IC697 CPU via the Host Communications Toolkits and an SNP driver One Megabyte User Logic Memory The CPM790 CPU provides 1 Megabyte 1024 kilobytes of User Logic memory This CPU supports multiple programs with the restrictions that no single program can be larger than 512 Kbytes and only one LDSFC program is permitted IC641 programming software Release 6 00 or later is required to configure this CPU model
4. take any time to integrate out thereby reducing overshoot Page 4 241 of the Programmable Logic Controller Reference Manual provides a description of the defined bits in the PID configuration word This bit definition is contained in Table 4 4 PID Function Block Data The configuration word has been enhanced in version 6 02 firmware to include support for an anti reset windup action as described above and Table 4 4 on the following page shows the version 6 02 firmware definitions for the PID function Block configuration word Important Product Information PLC CPU Module 15 GFK 1289B July 15 1996 Table 4 4 PID Function Block Data Config Word A word value with the following format bit 0 Error Term When this bit is set to zero the error term is SP PV When this bit is set to 1 the error term is PV SP bit 1 Output Polarity When this bit is set to zero the CV output represents the output of the PID calculation When it is set to 1 the CV output represents the negative of the output of the PID calculation bit 2 Derivative action on PV When this bit is set to zero the derivative action is applied to the error term When it is set to 1 the derivative action is applied to PV All remaining bits should be zero Deadband action When the Deadband action bit is set to zero then no deadband action is chosen If the error is within the deadband limits then the error is forced to zero Otherwise the error is not affected by
5. the PLC logic associated with supporting the 14 point Interrupt Module MUST be removed from the application program prior to placing the Release 6 00 CPU into RUN mode If this support logic is not removed incorrect operation of the 14 point Interrupt Module the application program and the IC697 PLC CPU firmware will result PID Function Block Version 6 02 firmware now provides support based upon the PID function block configuration word for anti reset windup action The PID configuration word permits you to select whether PID should back calculate the result DEFAULT action or pre clamp reset hold Refer to Additions to the PLC Reference Manual for a detailed description of the updated PID function block configuration word Important Product Information PLC CPU Module 13 GFK 1289B July 15 1996 Restrictions and Open Problems 1 If an expansion rack powers up while the CPU in the main rack is in the RUN mode the slot fault contacts will prematurely indicate that the modules in the expansion rack are not faulted before they complete their power up 2 Ina multi rack system false LOSS OF RACK faults may occur when the system loses power If this fault is configured to be fatal the system will power up in STOP mode 3 When there is no logic stored ina CPU module the Q and M tables will be cleared when the CPU is placed in RUN mode In this context no logic stored means that no program had ever been stored or that the clear f
6. 2 924 915 782 771 772 Size Relational Bit AND WORD Operation OR WORD XOR WORD NOT WORD NOT DWORD MCMP WORD SHL WORD SHR WORD ROL WORD ROR WORD MOVE BIT BPOS WORD BPOS DWORD Kira ARRAY_RANGE y WORD ARRAY_RANGE DWORD Control SVCREQ 23 25 32 1 Time in microseconds is based on Release 6 0 of IC641 programming software software indicates value not available not applicable or not supported with Release6 0 2 For table functions increment is in units of length specified For bit operation functions microseconds bit For data move functions microseconds the number of bits or words 3 Enabled time is for single length units of type R I O Interrupt Rate Limits Table A 13 and A 14 below contain updated information for the IC697 CPU interrupt rate limits These updates apply to those numbers given in the IC697 Programmable Controller Reference Manual in Appendix A Table A 13 I O Interrupt Performance 781 782 914 915 790 924 925 MaximumInterrupt Rate 450 interrupts 900 interrupts 2250 interrupts 2250 interrupts withIOMs persecond persecond persecond persecond MaximumlInterruptRate 750interrupts 1600interrupts 3750 interrupts 3750 interrupts withoutlOMs persecond persecond persecond persecond Table A 14 Event Triggered Interrupt Program Performance 771 7721 781 782 914 915 790 924 925 MaximumlInterruptRate n a 750 interrupts 2150 interrupts 2
7. 250 interrupts withIOMs persecond persecond persecond MaximumlInterruptRate n a 1300interrupts 3600 interrupts 3750 interrupts withoutlOMs persecond persecond persecond 1 Values are based upon release 5 00 PLC CPU firmware Important Product Information PLC CPU Module 17 GFK 1289B July 15 1996 Sweep Impact Timing Test Results CPU781 782 CPM914 915 CPM790 924 925 Disabled Enabled Disabled Enabled J Disabled Enabled Base Sweep Time 702 5 207 4 207 4 152 5 152 5 Rack Setup per expansion Rack 0 5 0 5 T O Scan Overhead 196 9 138 2 148 0 134 8 141 2 Per Discrete I O module in main rack 28 3 10 5 15 6 13 6 Per Discrete I O module in expansion rack 39 8 11 0 18 3 i 14 9 Per Discrete Fault 425 6 157 0 118 9 Per Analog I O module in main rack 30 8 A 22 3 20 7 Per Analog I O module in expansion rack 76 1 52 3 46 4 Per Analog Input Expander in main rack in 275 25 9 j 24 2 same segment Per Analog Input Expander in same segment in expansion rack n gt 85 6 83 6 Per Analog Input Expander in new segment in 51 4 32 4 main rack Per Analog Input Expander in new segment in 104 7 4 93 4 expansion rack Per Analog Fault 18 Important Product Information PLC CPU Module July 15 1996 GFK 1289B GBC Open System Comm Window per GBC polling for Background Messages per GBC I O Scan Genius I O Block per I O block scan segment Genius I O Block per byte discrete I O
8. July 15 1996 GFK 1289B IMPORTANT PRODUCT INFORMATION READ THIS INFORMATION FIRST Product PLC CPU Module 1C697CPM790 BB This is the production release of the IC697 PLC CPU module Model 790 version 6 02 which is used in IC66 IC660 or IC661 Modular Redundancy GMR systems This release sup ports Phase III of the GMR system It also fixes the problems listed under Problems Resolved by This Upgrade In addition several of the features provided in release 6 00 of the standard 1C697 CPU modules are also available in the GMR CPU s see New Features and Functionality Table 1 Catalog Numbers 1IC697CPM790 BB IC697CPM790AA BA Identification Hardware and software identification is summarized in the following tables Table 2 Hardware Identification Board Catalog Number Identification Board Revision IC697CPM790 BB CPVA1 444732261601 R04 or later mother board CMVA1 44 4735200G01 R03 or later memory board Table 3 Firmware Identification EPROM Catalog Number Location EPROM Diskette Label X n a 44S750522 G01 R02 3 Packaging Note The user manual is not shipped with every product User manuals are provided as a complete set in a library with IC641 Programming Software products are available on CD ROM or can be ordered as individual manuals 2 July 15 1996 Important Product Information PLC CPU Module GFK 1289B Update Information No update kits are available for this product For those c
9. Type Long Short Value PLC Fault Table 00 8 bytes short 01 24 bytes long I O Fault Table 02 5 bytes short pS d O 2 ytes Ton IC697 Instruction Set PID The PID function block has been enhanced in version 6 02 to make the anti reset windup mechanism configurable Prior to this release the IC697 CPU would back calculate the reset term whenever the output is clamped In version 6 02 this is now the DEFAULT mechanism Alternatively you can now choose to simply hold the reset term at its pre clamp value The advantage of the new mechanism is to reduce overshoot caused by the reset term as a result of a step change to the SP Note The described changes in the PID config word were actually provided but not documented in version 6 01 IC697 CPU firmware If you currently have version 6 01 firmware the described anti reset windup action of the PID function block is available Example A process is in steady state with PV 58 degrees A batch is turned on and SP is jumped to 200 degrees The output clamps high and with the default anti reset back calculation the reset term is driven low to prevent the output from exceeding the clamp When the PV comes up near the SP the reset term is large and negative because of the back calculation This term must be integrated out which takes times so the process overshoots The new method if configured would simply hold the original pre clamp reset term presumably small so it does not
10. acts were set When the corresponding Addition of Device fault was logged ALL of the F_rsmmm FAULT contacts were cleared This only happened with station address 127 7F hexadeci mal Rack and Slot Fault Locating References did not reflect the state of any FIP Locating References EVENT TRIGGERED programs using I memory as the trigger point set the wrong l reference when the trigger occurs This was not a problem for I O interrupt blocks Important Product Information PLC CPU Module 9 GFK 1289B July 15 1996 16 In rare circumstances the PLC logged a fatal PLC failure fault group 0x87 error code 4 during a stopped mode store When this occurred the CPU had to be cleared by powering up with the battery disconnected 17 Transitional contacts and coils occurring in rungs solved following a MOVE_BIT instruction occasionally did not pass power flow This occurred when the reference was within eight points below and eight points above the Q output parameter range of the MOVE_BIT instruction 18 Faults on FIP station address 127 caused all FIP device locating references to be set 19 When an SFC_RESET function in an LD block was called from an SFC MAIN block and EN received power the reset was NOT executed because it was in an LD block but the OK output was enabled 10 July 15 1996 Important Product Information PLC CPU Module GFK 1289B New Features and Functionality The New Features and Functionality listed belo
11. d to change the PLC Sweep Modes or timers Constant Sweep Time Program Window Times etc while the program window is closed Use Service Requests 1 through 4 to perform these functions CPM790 Ambient Temperatures Due to the high power dissipation of the CPM790 CPU microprocessor this module s ambient temperature during operation must be kept at or below 40 C 104 F With Forced air cooling the module can operate at 60 C 140 F Rack Fan Assemblies IC697ACC721 120 VAC and IC697ACC724 240 VAC for forced air cooling are available for direct mounting on the IC697 rack SFC RESET Function When programming using SFC no logic can appear to the right of an SFC_RESET function block External Devices Writing to CPU Memory At CPU power up the CPM790 CPU prohibits external devices PCMs Ethernet boards CMMs and others from having write access into PLC memory config data program code R P L I Q WAI WAQ T M G including GA GE and so forth The only devices that are permitted write access are parallel 1C641 programming software anything through the built in CPU serial port and IC66 bus controllers If external devices require write access to portions of memory these writable areas may be made available by the application using Service Request 31 This new Service Request 31 permits a range within each memory reference type to be defined as writable by external devices Service Request 31 does n
12. data main 3 1 3 1 7 rack Genius I O Block per byte discrete I O data exp rack 15 3 Genius I O Block per word analog I O data main rack 42 1 1 Genius I O Block per word analog I O data exp rack 13 1 ww D oO je a a m b gt A p i a oO n a bW oO p FIP I O Block per I O block scan segment 29 0 FIP I O Block per byte discrete I O data main rack FIP I O Block per byte discrete I O data exp rack FIP I O Block per word analog I O data main rack FIP I O Block per word analog I O data exp rack 98 13 1 PLC Memory Access from IOMs Read Write 1 to 3 445 words ma an an P o0 N P o Ke N Ke ee 0 lon A P N an 5 i OS bo N P oo aj co A W Aj gt N SO PLC Memory Access from IOMs Read Write 4 to 128 words 579 PLC Memory Access from IOMs Read Write each additional 128 words Clock Refresh Rate LAN module I O Scan Time Important Product Information PLC CPU Module 19 GFK 1289B July 15 1996 CPU781 782 CPM914 915 CPM790 924 925 Block Block Block ns ns ns ns ns ns Timed Interrupt Maximum Response Time 4 This time does not include the overhead attributed to the GMR application program that runs at the beginning and end of each sweep Refer to the GMR System User s Manual for further information 9 63 1 72 7 1 85 14 9 1 6 27 08 3 63
13. dule 11 GFK 1289B July 15 1996 provides the User Interface program for controlling the embedded debugger and the required communications drivers Communications between the User Interface and the IC697 CPU is with SNP on the CPU s built in serial port Note Debugger communications drivers and User Interface program are DOS based applications FIP I O The Release 6 00 IC697 CPU now supports FIP I O a new type of I O network and the FIP Bus Controller FBC For more information on FIP I O and the FIP Bus Controller please refer to the FIP Bus Controller User s Manual Microcycle Sweep Mode Microcycle is a new Sweep Mode of the Release 6 00 IC697 PLC CPU In microcycle mode each sweep begins at an absolute time relative to the STOP to RUN transition time Programs are configured by the user to run at whole number intervals of the base cycle time In microcycle mode the overall sweep is much like that of Constant Sweep however program execution can be time sliced over several sweeps Higher priority must run often programs are given smaller intervals of the base cycle time whereas lower priority run less often programs are given larger intervals The interval defines how often the program will be scheduled for execution for example an interval of 1 indicates that this program must execute every sweep an interval of 3 indicates that the program should be scheduled for execution every third sweep Programs with interval 1
14. e Release 6 00 1C697 CPU Of the 16 only one can be a Ladder Logic SFC program Therefore a Release 6 00 PLC CPU can take a maximum of one LD SFC program and 15 Standalone C programs or 16 Standalone C programs The PLC CPU must still contain sufficient available User RAM to store all programs Embedded Debugger for C Applications The IC697 CPU beginning with Release 6 00 now includes a C debugger embedded in the CPU firmware The embedded debugger is for use in debugging C applications running in the IC697 PLC CPU Some of the capabilities provided by the embedded debugger include the setting of hardware and or software breakpoints establishing watch variables display edit C application data single step execution of the C application and step over step intoexecution control The embedded debugger can be used to debug C EXE blocks and Standalone C programs in the Release 6 00 IC697 PLC CPU Only one debug session is permitted at any time When debugging a C application start stop control of the program is controlled through the embedded debugger however the IC697 PLC continues to execute its sweep executing any other program in the CPU scanning I O communicating with IC641 programming software if connected and communicating with any option modules if present A new C Toolkit the PLC C Toolkit Professional IC641SWP719A is required to use the embedded debugger The new C Toolkit Important Product Information PLC CPU Mo
15. em performance 4 July 15 1996 FILE OFFSET 0000 0010 0020 0030 0040 0050 0060 0070 Important Product Information PLC CPU Module GFK 1289B PCM to CPU Communications Timeout The PCM has a default backplane communications timeout value of 5 seconds After the PCM has sent a request to the IC697 CPU the PCM applies this timeout while waiting on a response back from the CPU In most cases the CPU will respond well within the 5 second timeout however in certain instances the CPU can take longer than 5 seconds to respond These cases are limited to LOADs and or STOREs of program and or configuration especially if blocks in the program are larger than 8 KBytes Folders containing EXE blocks again with EXE files gt 8 KBytes are most likely to cause problems Beginning in Release 6 00 Standalone C programs larger than 8 Kbytes also cause this to happen Note This problem may be encountered when using the CPM790 CPU ina TUV approved system The GMR application code is a Standalone C program that is larger than 8 Kbytes Beginning in Release 5 50 of the IC697 CPUs the CPU is guaranteed to respond within 8 seconds To ensure that the PCMs do not observe backplane timeouts a file must be loaded using termf to the PCM The file must be named CPU ENV and is a binary file The contents of this file are as follows all values are specified in hexadecimal DATA 4C 5A 01 01 00 00 00 00 00 00 00 00 01 00 00 00 LZ
16. ersion will be shipped Read this document before installing or attempting to use the IC697CPM790 PLC CPU Module For more information refer to the applicable Programmable Controller Installation manual Programming Software User s Manual Programmable Controller Reference Manual and the IC66 Modular Redundancy Flexible Triple Modular Redundant TMR System Important Product Information PLC CPU Module GFK 1289B July 15 1996 Special Operation Notes 1C641 Compatibility This release of the PLC Model 790 CPU module requires IC641 programming software version 6 02 or later to gain access to all of the CPU s features and functionality CPU Model 1C641 Programming Software 1C697CPM790 Version 6 02 or later If Release 6 02 PLC CPU firmware is used with IC641 programming software Release 4 01 or 4 02 the PLC Sweep Control and Monitor screen F3 F8 should ONLY be used to change tune the constant window or constant sweep time Any other use may result in the background window time being incorrectly set to 255 milliseconds For those IC641 programming software releases used with a Release 6 02 CPU the configuration package must be used to set the desired sweep modes or window times Microcycle Mode and First Output Scan Microcycle mode is a new sweep mode beginning with Release 6 00 CPUs In this mode the PLC keeps the time interval between I O scans constant for a further description of Microcycle mode see New Feature
17. gram is stored to the PLC and the PLC is placed in RUN mode then a power cycle of the PLC will result in the CPU performing its full power up diagnostic tests 9 Care must be taken when using continuation coils contacts in the main LD program execution and also in interrupt block execution There is only one location in Bit Cache memory for storing the continuation coil value Because of this do not use continuation coils contacts in both main LD program and in interrupt blocks 10 Anincorrectly formatted COMMREQ for example incorrect task id field directed to a PCM or CMM module does not result in an error being logged in the PLC fault table Correctly formatted COMMREQs operate normally 14 Important Product Information PLC CPU Module July 15 1996 GFK 1289B Additions to the PLC Reference Manual IC697 Instruction Set SVCREQ 15 Page 4 214 of the G version of the Programmable Logic Controller Reference Manual provides a description of the returned data when a SVCREQ 15 is executed read last fault The number of bytes of meaningful fault specific data varies depending on whether the logged fault is long or short and also whether it is an I O fault or a PLC fault Referring to the fault table descriptions on page 4 213 and 4 214 the Long Short indicator in the least significant byte of word address 1 defines the number of bytes of meaningful fault specific data present in the fault memory Defined values are Fault Table
18. ith the IC66 Bus Controllers GBCs NE s have changed this has uncovered a problem in the GBC NE firmware GBCs NB s in expanded racks could be lost if the system is fully configured and only the main rack cycles power Also in previous versions of the GBC NEC there was a problem with input data coherency Ina system with a large CPU sweep time and a short IC66 bus scan time a problem could be seen if a device is lost Input data could be defaulted off while the CPU is reading the data from the GBC NEe It is recommended to update existing GBC NBC hardware to IC697BEM731M or later when used with the CPM790 CPU Operation of the IC697BEM731M will result in a slight in crease to the I O scan time of the PLC when compared to previous versions of the GBC NBC hardware Third Party VME Modules IC641 programming software Release 5 00 and later allows Third Party VME modules to be configured for six modes NONE INTERRUPT ONLY BUS INTERFACE FULL MAIL I OSCAN and REDUCED MAIL However CPU Release 6 02 only supports NONE BUS INTERFACE FULL MAIL andI OSCAN modes The other modes should not be configured Maximum PLC Sweep In systems configured for IC66 Bus Redundancy a complete PLC sweep must be executed every 500 milliseconds or less even though it is possible to configure the watchdog timer to higher limits This also means that resetting of the watchdog timer with Service Request 8 cannot be done indefinitely Serial Communica
19. k containing a PCM was then powered up the PCM was given sufficient time to complete its self tests then timed out the CPU and proceeded into PCM standalone mode If the CPU was then powered up the PCM was not reset but no indication was given to the user that the PCM was not configured The CPU did not verify that interrupt trigger declarations in the program correctly corresponded to interrupt generating modules declared in the I O configuration The Time of Day clock incorrectly handled leap year Attempting to read from an external device the L memory associated with an EXE block resulted in the CPU lights going out Subsequent power up showed a PLC CPU Software Fault error code 8D hex in the PLC fault table When using SVCREQ function 20 to read the PLC or I O fault tables occasionally the header information returned and the current state of the fault tables was inconsistent Pre release revision 6 00 CPUs occasionally did not always work with new IC697 power supplies Problems could be observed when using PWR710E PWR710EF and PWR724A The symptoms were typically a loss of option module s in expansion rack s After a power cycle of an expansion rack containing IC660 661 Bus Controllers occasionally the IC697 CPU would timeout the reconfiguration of the GBC NECs that were powering up When the FIP Bus Controller logged a Loss of Device fault for a remote FIP subscriber at station address 127 ALL of the F_rsmmm FAULT cont
20. ng to the RUN mode since the serial port is currently configured for printf commands from C blocks or Standalone C programs 1C641 WSI Attach Do not connect or disconnect the WSI BTM cable while the programmer host is powered on This action may cause a running PLC to Stop Expansion Rack ID The expansion racks for the IC697 PLC are shipped with the rack ID strapped for rack 0 the main rack If the rack jumper is not changed the PLC will not recognize the rack at all and may not properly identify the error Expansion Rack Cable Do not connect or disconnect the expansion rack cable while the CPU is running This will cause the PLC to go to the STOP HALT mode Expansion Rack Power Expansion racks should be powered up at the same time that the main rack is powered up or they should be powered up after the main rack has completed its power up initialization Do not power up an expansion rack while the CPU is running power up diagnostics Memor y Usage A general rule of thumb for memory usage is 48 bytes per I O point plus register memory in bytes Timer Operation Care should be taken when timers ONDTR TMR and OFDTR are used in program blocks that are NOT called every sweep The timers accumulate time across calls to the sub block unless they are reset This means that they function like timers operating in a program with a much slower sweep than the timers in the main program block For program blocks that are inactive fo
21. ot require that every memory reference type have a writable area but does limit the writable area to a single contiguous range in each memory reference type that is specified Note This restriction prevents the use of any Ethernet version of IC641 programming software to store and or modify application programs The serial or WSI versions of IC641 programming software must be used to store and or modify application programs 8 July 15 1996 Important Product Information PLC CPU Module GFK 1289B Problems Resolved by This Upgrade 1 10 11 12 13 14 15 The Service Request function block when processing request 20 took an exceptionally long time to complete 10 milliseconds Occasionally the CPU would not perform its full power up diagnostic checks even when powering up into STOP mode The Service Request function block function code 21 incorrectly permitted use of error codes greater than 800h Such error codes are interpreted by the PLC CPU as being Remote Scanner alarms AnIC660 661 Bus Fault could have set the fault condition for the M_rsbmm r rack s slot b bus mm SBA of GBC NE fault and nofault contacts This fault condition would persist until either the fault tables were cleared or the GBC NBC s rack was power cycled Expansion rack Analog Input Expander cards were reset lights out during a run mode reconfiguration In cases when a CPU rack was powered off and an expansion rac
22. r large periods of time the timers should be programmed in such a manner as to account for this catch up feature Similar to this are timers that are skipped because of the use of the JUMP instruction Timers that are skipped will NOT catch up and will therefore not accumulate time in the same manner as if they were executed every sweep 1O Link Interface When powering up the PLC CPU without a battery and I O Link Interface boards are present an incorrect Loss of Module fault will be logged for each I O Link Interface board but the PLC CPU will not consider these boards as lost and the boards will continue to operate properly Important Product Information PLC CPU Module GFK 1289B July 15 1996 COMMREGQs with Retentive Memory When powering up the PLC CPU with a program being retrieved from Retentive Memory and proceeding to RUN mode any COMMREQs to a PCM should be delayed for 5 seconds Constant Sweep Constant Sweep time when used should be set to about 10 milliseconds greater than the normal sweep time to avoid any oversweep conditions when monitoring or performing on line changes with the programmer The smallest valid constant sweep time setting is 10 milliseconds for the CPM790 CPU Window completion faults will occur if the constant sweep setting is not high enough Interaction of 1C641 Programming Software with Closed Programming Window The IC641 programming software Sweep Control and Monitor screen cannot be use
23. s and Functionality Microcycle Sweep Mode actually the start of sweep time is maintained as a fixed interval In keeping the time interval between I O scans constant the CPU must know the amount of the sweep to be allocated to the output scan Under normal operating situations the amount of time required to complete the previous sweep s output scan is used to estimate the amount of time required to complete this sweep s output scan Obviously this manner of estimating the amount of time required for the output scan does not work for the first output scan of the IC697 PLC Since no previous sweep s output scan time is available the Release 6 xx CPU will estimate the output scan time based upon the configured base cycle time The first output scan will be estimated as one third of the configured base cycle time for example if the base cycle time is configured to be 60 milliseconds then the first output scan will be estimated as requiring 20 milliseconds When programming for first scan ensure that the logic to be performed in a given program will complete prior to the next execution time for that same program PCM and BTM Compatibility With the introduction of timing improvements and new features in Release 5 00 it is highly recommended that systems using PCMs use IC697PCM 711J or later It is also highly recommended that systems using BTMs use IC697BEM713B or later Use of boards of an earlier revision may result in lower syst
24. the deadband limits If the Deadband action bit is set to 1 then deadband action is chosen If the error is within the deadband limits then the error is forced to be zero If however the error is out side the deadband limits then the error is reduced by the deadband limit error error deadband limit bit 4 Anti reset windup action When this bit is set to zero the anti reset windup action uses a reset back calculation When the output is clamped this replaces the accumulated Y term with whatever value is necessary to produce the clamped output exactly When the bit is set to one this re places the accumulated Y term with the value of the Y term at the start of the calculation In this way the pre clamp Y value is held as long as the output is clamped NOTE The anti reset windup action bit is only available on release 6 01 or later CPUs IC697 Instruction Timing Table A 1 on the following page contains updated information for several of the IC697 CPU instruction timings These updates apply to those numbers given in the Programmable Controller Reference Manual in appendix A 16 July 15 1996 Important Product Information PLC CPU Module GFK 1289B Table A 1 Instruction Timing Enabled Disabled Increment Function 790 914 781 731 732 790 914 781 731 732 790 914 781 731 732 Group Function 924 915 782 771 772 924 915 782 771 77
25. tions The following operating restrictions exist for the Serial Communications feature 1 Serial communications can add up to 5 milliseconds of time to any given sweep This should be taken into account when setting the watchdog timer 2 The following procedure is recommended when changing baud rates in the PLC and the WSI board First enter the configuration package and change the baud rate on the PLC then store the new configuration Now power off the PLC and then go to the WSI setup screen and change the WSI baud rate Finally power the PLC back on 3 The link idle time setting in IC641 programming software Config for Serial Com munications should be set to 10 seconds or greater Otherwise a communications failure will occur when storing the config to the PLC Serial Port Mode Configuration There is a serial port configuration parameter under software configuration for the PLC CPU called MODE This configuration parameter can be one of two values SNP to indicate that the serial port will be used for SNP communications or MSG to 6 July 15 1996 Important Product Information PLC CPU Module GFK 1289B indicate that the serial port will be used to send printf commands from a C block or Standalone C program to the connected device If you have configured MODE to be MSG and are also using serial IC641 programming software as a means of communicating with the PLC communications with IC641 programming software is lost when goi
26. unction on the IC641 pro gramming software had been used to clear logic and configuration 4 When the Bit Sequencer sequences from one step to another the negative transition al contact that corresponds to the original step is not set The transition contact for the new step is set and remains set until the sequencer sequences to the next step This operation is identical to the operation of the previous versions of the CPU firm ware 5 If multiple faults exist in an IC697 PLC remote drop and one of them is corrected a FAULT contact that uses the remote drop s module reference will incorrectly indicate that no faults exist at the remote drop 6 An Analog Input Base module and its expander modules may not come online if they are configured in an expansion rack that is missing when the main rack powers up Power up the expansion rack first then power up the main rack 7 If the main rack loses power during PLC configuration analog input base boards IC697ALG230 in expansion racks that do not lose power may fail The failure would occur on the subsequent configuration PLC configuration occurs during power up store of configuration and reads from Retentive Flash Memory To prevent the failure tie all racks to a common power source To correct the failure power cycle the expan sion racks 8 If the CPU is to power up into RUN mode the full power up diagnostic tests are sup posed to be skipped If only an I O configuration no pro
27. ustomers who purchased a version 6 01 CPM790 a version 6 02 upgrade is available on the Electronic Bulletin Board The files necessary for a CPM790 upgrade have been ZIP ed into a single self extracting EXE file and placed in the PLC PUBLIC conference and the PLC Series 90 70 directory The Bulletin Board entry for this update file contains information explaining what the file is and how to create a master update diskette using the file For those customers who have access to the Electronic Bulletin Board updates for the CPM790 CPU can be obtained by downloading the appropriate EXE file There is no charge for updates obtained in this manner Table 5 Bulletin Board Filename for CPM790 Firmware Updates Upgrade Kit For Upgrading CPM79602 EXE IC697CPM790AA BA 1IC697CPM790 BB Note Ensure that you download the correct EXEfile CPM914 915 924 925 firmware will not work on a CPM790 Documentation The following table lists the applicable documentation for the IC697CPM790 CPU Table 6 User Documentation Catalog Number Data Sheet 1C697CPM790 BB GFK 1215 Full Documentation Sets Full documentation sets are also available in either printed bound form or in electronic form CD ROM Refer to the following table for ordering information for full documentation sets Table 7 Full Documentation Set 1C697LBR701 Paperlibrary full set of printed manuals IC690CDRO02 CD ROM full set of manuals in electronic format Current v
28. w are those that first appeared in Release 6 00 and are also provided in Release 6 02 of the CPM790 Standalone C Program 1C697 CPU Release 6 00 provides the ability to have PLC CPU applications written exclusively in the C language A standalone C program is called from the operating system directly no Ladder Logic is required Each standalone C program code and data can be a maximum of 512 Kbytes providing there is sufficient RAM available on the PLC CPU A standalone C program can have up to eight input specifications and up to eight output specifications Each input or output specification is defined as a start PLC memory reference and a data length The input specifications are copied into the standalone C program when the standalone is scheduled for execution by the operating system Output specifications are copied back to the specified PLC global memory upon completion of the standalone C program s execution Each of the input output specifications are defined by the user through IC641 programming software Release 6 00 Standalone C programs are created using the C Programmer s Toolkit for IC697 PLCs v3 00 For more information on Standalone C programs please consult the Programmable Controller Reference Manual or C Programmer s Toolkit for PLCs User s Manual Multiple Programs Release 6 00 of the IC697 PLC CPU now supports the storing of multiple programs to a single PLC A maximum of 16 programs can be stored to th
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