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NXP 8xC51MA2, 8xC51MB2, 8xC51MB2/02, 8xC51MC2

1. BRGCON Address 85h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h S S SOBRGS BRGEN BIT SYMBOL FUNCTION BRGCON 7 2 Reserved for future use Should be set to O by user programs BRGCON 1 SOBRGS For UART 0 only Used in combination with the RCLK and TCLK in deciding the receive and transmit baud rates to UART 0 in modes 1 amp 3 see Table 13 for details BRGCON O BRGEN 0 Disable Baud Rate Generator 1 Enable Baud Rate Generator Baud rate SFRs BRGR1 and BRGRO can only be written when BRGEN is 0 Figure 41 BRGCON Register Timer 1 Overflow Oo RCLK 0 UART 0 Receive Baud Rate Modes 1 and 3 SMOD1 0 RCLK 1 TCLK 0 SOBRGS 1 Baud Rate Generator o 9 6 Uu 0 Transmit Baud Rate Modes 1 and 3 Timer 2 Overflow rof TCLK 1 SOBRGS 0 UART 1 Receive and Transmit Baud Rate Modes 1 2 and 3 Figure 42 Baud Rate Generations for UART 0 Modes 1 3 and UART 1 Modes 1 2 3 54 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 SnCON SOCON Address 98h Conventional SFR Space S1CON Address 80h MX Extended SFR Space Bit addressable Reset Value 00h BIT SnCON 7 SMO_n FE_n SnCON 6 SM1_n SMO n SM1 n 00 01 10 11 SnCON 5 SM2_n SnCON 4 REN_n SnCON 3 TB8 n SnCON 2 RB8 n SnCON 1 TI n SnCON 0 RI n
2. T2EX Pi Su ato l CONTROL EXEN2 Figure 36 Timer 2 in Auto Reload Mode DCEN 0 49 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 TOGGLE DOWN COUNTING RELOAD VALUE EXF2 C T2 0 Lo re et e OVERFLOW Timer 2 O gt kA TR2 P Interrupt A C T2 1 CONTROL VE T2Pin dd TR2 A COUNT DIRECTION 1 UP 0 DOWN RCAP2L RCAP2H UP COUNTING RELOAD VALUE T2EX PIN Figure 37 Timer 2 in Auto Reload Mode DCEN 1 C T2 0 des TX RX Baud Rate See section Baud Rate Generator and Selection A C T2 1 T2Pin__________ Transition Detector CONTROL EXEN2 Figure 38 Timer 2 in Baud Rate Generator Mode 50 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 UARTS The P87C51Mx2 includes two enhanced UARTs with one independent Baud Rate Generator They are compatible with the enhanced UART based on the 8xC51Rx except the baud rate generator The first UART UART 0 can select using Timer1 overflow Timer2 overflow or the independent Baud Rate Generator The second UART UART 1 only uses the independent Baud Rate Generator to generate its baud rate Besides the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition se
3. Figure 48 Transmission with and without Double Buffering 8 Bit Case The 9th Bit Bit 8 in Double Buffering If double buffering is disabled DBMOD_n i e SnSTAT 7 0 TB8 can be written before or after SnBUF is written as long as TB8 is updated some time before that bit is shifted out TB8 must not be changed until the bit is shifted out as indicated by the Tx interrupt If double buffering is enabled TB8 MUST be updated before SnBUF is written as TB8 will be double buffered together with SnBUF data The operation described in the section Transmit Interrupts with Double Buffering becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SnBUF The SnBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately If there is more data go to 7 else continue on 6 If there is no more data then If DBISEL_n is 0 no more interrupt will occur If DBISEL n is 1 and INTLO_n is 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL nis 1 and INTLO nis 1 UART mode 1 2 or 3 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SnBUF again Then DAWNI 61 Preliminary 2002 June 28 Philips Semiconductors P
4. 96 KB or 64 KB of on chip OTP 3 KB or 2 KB of on chip RAM Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 1 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Programmable Counter Array PCA Two full duplex enhanced UARTs KEY BENEFITS Increases program data address range to 8 MB each Enhances performance and efficiency for C programs Fully 80C51 compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base investment knowledge and peripherals amp ASICs Supported by 80C51 development and programming tools The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time to market COMPLETE FEATURES Fully static Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 KB or 64 KB of on chip OTP 3 KB or 2 KB of on chip RAM 23 bit program memory space and 23 bit data memory space Four interrupt priority levels 32 I O lines 4 ports Three Timers TimerO Timer1 and Timer2 Two full duplex enhanced UARTs with baud rate generator Framing error detection Automatic address recognition Power control modes Clock can be stopped and resumed Idle mode Power down mode Second DPTR register Asynchronous port reset Programmable Counter Array PCA compatible with 8xC51Rx with five Capture Compare modules Low EMI inhibit AL
5. SYMBOL 7 6 5 4 3 2 1 0 SM0 nrE n SM1_n SM2_n REN_n TB8 n RB8_n TI n RI n FUNCTION The usage of this bit is determined by SMODO in the PCON register If SMODO 0 this bitis SMO n which with SM1 n defines the serial port mode If SMODO 1 this bit is FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note It is recommended to set up UART mode bits SMO n and SM1 n before setting SMODO to 1 With SMO n defines the serial port mode see table below UART Mode UART 0 Baud Rate UART 1 Baud Rate 0 shift register CPU clock 6 CPU clock 6 1 8 bit UART Variable see Table 13 Baud Rate Generator see Table 14 2 9 bit UART CPU clock 32 or CPU clock 16 Baud Rate Generator see Table 14 3 9 bit UART Variable see Table 13 Baud Rate Generator see Table 14 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 nis set to 1 then RI n will not be activated if the received 9th data bit RB8_n is 0 In Mode 1 if SM2_n 1 then RI n will not be activated if a valid stop bit was not received In Mode 0 SM2 n should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In Modes 2 and 3 is the 9
6. The table below shows function of Port 4 37 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 P4 0 RXD1 Serial input port 1 with pull up P4 1 TXD1 Serial output port 1 with pull up 6 3 P87C51MX2 LOW POWER MODES 6 3 1 STOP CLOCK MODE The static design enables the clock speed to be reduced down to O MHz stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power Down mode is suggested 6 3 2 IDLE MODE In the idle mode see Table 9 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode The idle mode can be terminated either by any enabled interrupt at which time the process is picked up at the interrupt service routine and continued or by a hardware reset which starts the processor in the same manner as a power on reset Idle mode is entered by setting the IDL bit in the PCON register 6 3 3 POWER DOWN MODE To save even more power a Power Down mode see Table 9 can be in
7. 0033h EC IEN0 6 IPOH 6 IPO 6 Serial Port 1 Tx and Rx TI 1 amp RI 18 5 0053h ES1 IEN1 0 IP1H 0 IP1 0 0 lowest Serial Port 1 Rx Serial Port 0 Tx 003Bh EMO IEN1 1 IP1H 1 IP1 1 Serial Port 1 Tx 0043h El11 IEN1 2 IP1H 2 IP1 2 e Ne SOSTAT 5 0 selects combined Serial Port 0 Tx and Rx interrupt SOSTAT 5 1 selects Serial Port 0 Rx interrupt only and TX interrupt will be different see Note 3 below S1STAT 5 0 selects combined Serial Port 1 Tx and Rx interrupt S1STAT 5 1 selects Serial Port 1 Rx interrupt only and TX interrupt will be different see Note 4 below This interrupt is used as Serial Port 0 Tx interrupt if and only if SOSTAT 5 1 and is disabled otherwise This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT 5 1 and is disabled otherwise If SOSTAT O 1 the following Serial Port O additional flag bits can cause this interrupt FE 0 BR 0 OE O If S1STAT O 1 the following Serial Port 1 additional flag bits can cause this interrupt FE 1 BR 1 OE 1 Table 8 Summary of Interrupts 30 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 IENO Address A8h 7 6 5 4 3 2 1 0 EE EA EC ET2 ESQESOR Er EX1 ETO EXO Reset Value 00h BIT SYMBOL FUNCTION IENO 7 EA Interrupt Enable Bit IENO 6 EC PCA Interrupt Enable bit IENO 5 ET
8. EPTR Memory Location 01 1034h Accumulator 0 01 1034h Figure 11 External Data Memory Access using Indirect Addressing with EPTR 13 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 6 PROGRAM MEMORY CODE The 80C51 and thus the 51MX are Harvard architectures meaning that the code and data spaces are separated If there is a single byte of executable code above 64 KB EAM bit in MXCON sfr must be set to EAM 1 Also if there is constant in CODE space above 64 KB boundary that is read by the application EAM must be set to EAM 1 too The 51MX expands the 80C51 Program Counter to 23 bits providing a contiguous unsegmented linear code space that may be as large as 8 MB On chip space begins at code address 0 and extends to the limit of the on chip code memory Above that code will be fetched from off chip The 51MX architecture allows for an external bus which supports Mixed mode some code and or data memory off chip Single chip operation no external bus connection e ROMIess operation no use of on chip code memory In some cases code memory may be addressed as data Extended instruction address modes provide access to the entire code space of 8 MB through the use of indexed indirect addressing The currently active DPTR the EPTR a Universal Pointer or the Program Counter may be used as the base address Examples of the various code mem
9. Figure 34 Timer 2 Mode T2MOD Control Register 6 5 4 BAUD RATE GENERATOR MODE FOR UART 0 SERIAL PORT 0 When serial port 0 UART 0 doesn t use the independent baud rate generator SOBRGS 0 SOBRGS is BRGCON 1 bits TCLK and or RCLK in T2CON allow the serial port O UART 0 transmit and receive baud rates to be derived from either Timer 1 or Timer 2 Refer to the section on UARTS for details Assume that SOBRGS 0 when TCLK 0 Timer 1 is used as the UART 0 transmit baud rate generator when TCLK 1 Timer 2 is used as the UART 0 transmit baud rate generator RCLK has the same effect for the UART 0 receive baud rate With these two bits the serial port can have different receive and transmit baud rates Timer 1 Timer 2 or baud rate generator Figure 38 shows Timer 2 in baud rate generator mode The baud rate generation mode is like the auto reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in modes 1 and 3 are determined by Timer 2 s overflow rate given below Modes 1 and 3 Baud Rates Timer 2 Overflow Rate 16 The timer can be configured for either timer or counter operation In many applications it is configured for timer operation C T2 0 Timer operation is different for Timer 2 when it is being used as a baud rate generator Usually as a timer it would increment every machine cy
10. JNB 20h 2 LABEL1 sets bit 1 at address 20 hex complements bit 2 in the same byte then branches if the second bit is not equal to 1 In an actual program these bits would normally be given names and referred to by those names in the bit manipulation instructions 2 2 3 EXTENDED DATA MEMORY EDATA The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic 80C51s This space can be used as an extended or alternative processor stack space or can be used as general purpose storage under program control Other than Stack Pointer based access to this space which is automatic if Extended Stack Memory Mode is enabled see the following Stack section this memory is addressed only using the new Universal Pointer feature Universal Pointers are described in a later section Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory 2 2 4 STACK The processor stack provides a means to store interrupt and subroutine return addresses as well as temporary data The stack grows upwards from lower addresses towards higher addresses The current Stack Pointer always points to the last item pushed on the stack unless the stack is empty Prior to a push operation the Stack Pointer is incremented then data is written to memory When the stack is popped the reverse procedure is used First data is read from memory then the Stack Pointer is decremented The default configurat
11. PR0 3 A PRO 3 A 1 C EMOV ADD A PR1 0 OPRAO A PR1 4 5D EZ EMOV ADD A PR1 1 QPRIA A PR1 1 5E EZ EMOV ADD A PR1 2 OPRI A PR1 2 5F EZ EMOV ADD A PR1 3 PAra A PR1 3 Table 6 51MX Operation Code Chart Part 3 26 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 90 5 4 A0 3 3 BO 3 3 CO 3 3 DO 3 3 EO 2 4 FO 2 4 MOV ORL ANL PUSH POP MOVX MOVX EPTR d23 C bit C bit dir dir A EPTR EPTR A A A EPTR 85 4 3 95 3 2 B5 4 3 C5 3 2 D5 4 3 E5 3 2 F5 3 2 MOV SUBB CJNE XCH DJNZ MOV MOV dir dir A dir A dir rel8 A dir dir rel8 A dir dir A 86 3 3 A6 3 3 MOV MOV dir R0 RO dir 87 3 3 A7 3 3 MOV MOV dir OR1 QR1 dir 88 3 3 A8 ee MOV MOV dir RO RO dir 89 3 3 A9 3 3 MOV MOV dir R1 R1 dir 8A 3 3 AA 3 3 MOV MOV dir R2 R2 dir 8B 3 3 AB 3 3 MOV MOV dir R3 R3 dir 8C 3 3 AC 3 3 MOV MOV dir R4 R4 dir 8D 3 3 AD 3 3 MOV MOV dir R5 R5 dir 8E 3 3 AE 3 3 MOV MOV dir R6 R6 dir 8F 3 3 AF 3 3 MOV MOV dir R7 R7 dir Table 7 51MX Operation Code Chart Part 4 27 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 4 EXTERNAL BUS The external bus provides address information to external devices and initiates code read data rea
12. it will continue to be stored as shown on in figures 4 and 5 The Extended Stack Memory Mode is enabled by setting the ESMM bit in the MXCON register If the Stack Pointer is not initialized by software the stack will begin at on chip RAM address 8 just as for the 80C51 Also note that in Extended Stack Memory Mode both MB2 and MC2 parts have 1KB of RAM on the top of DATA IDATA space available for the stack The stack mode bits ESMM and EIFM are shown in Figure 6 Note that the stack mode bits are intended to be set once during program initialization and not altered after that point Changing stack modes dynamically may cause stack synchronization problems MXCON Address FFh 51MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h EAM ESMM EIFM BIT SYMBOL FUNCTION MXCON 7 3 Reserved Programs should not write a 1 to these bits MXCON 2 EAM Enables Extended Addressing Mode in connection with a non volatile user configuration bit The logical OR of the SFR bit and the non volatile configuration bit determines whether code and data addressing beyond 64 KB is allowed The same logical OR value will be read from this bit by software When 0 all addressing on chip and off chip is limited to 64 KB each of code and data When 1 51MX addressing capabilities are extended beyond boundary of 64 KB to 8 MB each of code and data and upper address bits are multiplexed on Port
13. it will return a 1 like other unimplemented bits in SFRs Use of the EPTR allows access to the entire HDATA space including XDATA 12 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 At any point in time one specific Data Pointer is active and is used by instructions that reference the DPTR The active DPTR may be changed by altering the Data Pointer Select DPS bit The DPS bit occupies the bottom bit of the AUXR1 register The DPS bit applies only to the two DPTRs not to the EPTR In the indirect addressing mode the currently active DPTR or the EPTR provides a data memory address for accessing the XDATA and HDATA space respectively When the DPTR is used for addressing only the XDATA space is available When the EPTR is used for addressing the entire HDATA space which includes the XDATA space may be accessed If the EPTR value exceeds 7E FFFF the limit of HDATA data accesses using EPTR will yield undefined results The reason for limiting HDATA addresses is to keep the addressing uniform for EPTR addressing and Universal Pointer addressing which is explained in a later section of this document Example Instruction External Data MOVX DPTR A Memory Data Pointers Manes Location 0 AT7Ch 00 00 A17Ch Accumulator 1 2962h Figure 10 External Data Memory Access using Indirect Addressing with DPTR Example Instruction External Data MOVX A
14. 1Eh nor Elh 5 WDTRST SFR 1Eh WDT enabled Wait for next write to the WDTRST SFR Ti t ime ou gt Ehh ritten OEIh to the Neither 1Eh nor Elh WDTRST SFR Elh Restart WDT Figure 49 Watchdog Timer State Transitions 65 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 7 3 WDT CONTROL The P87C51Mx2 has a control register in the MX extended SFR space It has a 3 bit prescaler control to select the prescale factor for the watchdog timer clock WDCON should be loaded with selected value before WDT is turned on Writing to WDCON while WDT is enabled will result in unpredictable behavior 6 7 4 WATCHDOG RESET WIDTH When the WDT times out a reset will occur and the external reset RST pin will be driven high for 98 clock cycles WDCON Address 8Fh MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h R WDPRE2 WDPRE1 WDPREO BIT SYMBOL FUNCTION WDCON 7 3 Reserved for future use Should be set to 0 by user programs WDCON 2 0 WDPRE2 0 Select WDT presecale factor Note that the value written to these bits will not be immediately available to be read until after a WDT feed sequence Figure 50 WDCON Register WDPRE2 WDPRE1 WDPREO Prescale Factor Table 15 WDT Prescale Selection 6 7 5 READING FROM THE WDCON SFR It should be noted that value w
15. 2 for external code and or data accesses Refer to the External Bus section for additional details EAM must be set to EAM 1 if at least one of the next two statements is true there is executable code or constants in CODE space are above 64 KB address of data byte that has to be accessed in HDATA is above 64 KB MXCON 1 ESMM Enables the Extended Stack Memory Mode When ESMM 0 the Stack Pointer is 8 bits in width and the stack is located in the IDATA memory space When ESMM 1 the Stack Pointer is increased to 16 bits in width and the stack may be located anywhere in the EDATA space ESMM is independent of EAM and EIFM bits MSCON 0 ElFM Enables the Extended Interrupt Frame Mode When EIFM 0 an interrupt service will cause only the lower 16 bits of the PC to be pushed onto the stack and an RETI instruction will restore only the lower 16 bits of the PC When EIFM 1 an interrupt service will cause all 23 bits of the PC to be pushed onto the stack while an RETI instruction will restore all 23 bits of the PC EIFM must be set to one if the application allows execution beyond the first 64 KB of code memory Figure 6 MX Configuration Register MXCON 9 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 2 5 GENERAL PURPOSE RAM Portions of the internal data memory that are not used in a particular application as registers stack or bit addressable lo
16. Bit IPO 5 PT2 Timer 2 Interrupt Priority Low Bit IPO 4 PSO PSOR Serial Port 0 Combined Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority Low Bit IP0 3 PT1 Timer 1 Interrupt Priority Low Bit IP0 2 PX1 External Interrupt 1 Priority Low Bit IPO 1 PTO Timer 0 Interrupt Priority Low Bit IP0 0 PXO External Interrupt O Priority Low Bit Figure 22 Interrupt Priority Register IPO IPOH Address B7H Not bit addressable Reset Value 00h BIT IPOH 7 IPOH 6 IPOH 5 IPOH 4 IPOH 3 IPOH 2 IPOH 1 IPOH O SYMBOL PPCH PT2H PSOH PSORH PT1H PX1H PTOH PXOH 7 6 5 4 3 2 1 0 PPCH PT2H PSOHPSORH PT1H PX1H PTOH PXOH FUNCTION Reserved for future use Should be set to 0 by user programs PCA Interrupt Priority bit High Bit Timer 2 Interrupt Priority High Bit Serial Port 0 Combined Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority High Bit Timer 1 Interrupt Priority High Bit External Interrupt 1 Priority High Bit Timer 0 Interrupt Priority High Bit External Interrupt O Priority High Bit Figure 23 Interrupt Priority High Byte IPOH 32 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 d Address F8H 7 6 5 4 3 2 1 0 Bit addressable PS1T PSOT PSY PSIR Reset Value 00h BIT SYMBOL FUNCTION IP1 7 3 Reserv
17. Bit Addressable SFRs Figure 9 Extended SFRs Map for the P87C51Mx2 2 4 EXTERNAL DATA MEMORY XDATA The XDATA space on the 51MX is the same as the 64 KB external data memory space on the classic 80C51 On chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register Accesses above implemented on chip XDATA will be routed to the external bus If on chip XDATA memory is disabled all XDATA accesses will be routed to the external bus P87C51MB2 has 768 bytes of on chip XDATA while P87C51MC2 has 1792 bytes of on chip XDATA memory 2 5 HIGH DATA MEMORY HDATA The 51MX architecture supports up to an 8 MB data memory space using 23 bit addressing The entire 8 megabyte space except for the 64 KB EDATA space is called HDATA The XDATA space comprises the lower 64 KB of HDATA Data Pointers The 51MX adds an additional 23 bit Extended Data Pointer EPTR in order to allow a simple method of extending existing 80C51 programs to use more than 64 KB of data memory If we want to access a single data byte from HDATA RAM located above the first 64 KB EAM bit in MXCON sfr must be set to EAM 1 All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR The 23 bit EPTR is comprised of in order EPH EPM and EPL Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR respectively Since the EPTR is a 23 bit value the 8th bit of EPH is not used If read
18. CAPP for that module must be set The external CEX input for the module on port 1 is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter registers CH and CL into the module s capture registers CCAPnL and CCAPnH 72 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated 6 9 2 16 BIT SOFTWARE TIMER MODE The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register The PCA timer will be compared to the module s capture registers and when a match occurs an interrupt will occur if the CCFn CCON SFR and the ECCFn CCAP Mn SFR bits for the module are both set 6 9 3 HIGH SPEED OUTPUT MODE In this mode the CEX output on port 1 associated with the PCA module will toggle each time a match occurs between the PCA counter and the module s capture registers To activate this mode the TOG MAT and ECOM bits in the module s CCAPMn SFR must be set 6 9 4 PULSE WIDTH MODULATOR MODE All of the PCA modules can be used as PWM outputs The frequency of the output depends on the source for the PCA timer All of the modules will have the same frequency of output because they all share the PCA timer The duty cycle of each module is independent
19. CCF1 CCFO Bit addressable Reset Value 00h BIT SYMBOL FUNCTION CCON 7 CF PCA Counter Overflow Flag Set by hardware when the counter rolls over CF flags an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software CCON 6 CR PCA Counter Run Control Bit Set by software to turn the PCA counter on Must be cleared by software to turn the PCA counter off CCON 5 Reserved for future use Should be set to 0 by user programs CCON 4 CCF4 PCA Module 4 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 3 CCF3 PCA Module 3 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 2 CCF2 PCA Module 2 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 1 CCF1 PCA Module 1 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software CCON 0 CCFO PCA Module 0 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software Figure 56 PCA Counter Control Register 71 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CCAPMn 7 6 5 4 3 2 1 0 Address CCAPMO ODAH ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPM1 ODBH CCAPM2 ODCH CCAPM3 ODDH CCAPM4 ODEH Not bit addres
20. MODULEI IE 6 IE 7 Eod NES EC EA TO i L a INTERRUPT MODULE2 MODULE3 t PRIORITY i SOME SES DECODER Hf eo foro gt MODULE4 CMOD 0 ECF CCAPMn 0 ECCFn Figure 54 PCA Interrupt System CMOD Address D9H Not bit addressable Reset Value 00h BIT SYMBOL CMOD 7 CIDL CMOD 6 WDTE CMOD 5 3 G CMOD 2 1 CPS1 CPSO CMOD 0 EC T 7 6 5 4 3 2 1 0 CIDL WDTE E S CPS1 CPSO ECF FUNCTION Counter Idle Control CIDL 0 programs the PCA Counter to continue functioning during Idle Mode CIDL 1 program it to be gated off during idle Watchdog Timer Enable WDTE 0 disables watchdog timer function on module 4 WDTE 1 enable it Reserved for future use Should be set to 0 by user programs PCA Count Pulse Select CPS1 CPSO Select PCA Input 0 0 O Internal Clock fosc 6 0 1 1 Internal Clock fosc 2 1 0 2 Timer 0 Overflow 1 1 3 External Clock at ECI P1 2 pin max rate fosc 4 PCA Enable Counter Overflow Interrupt ECF 1 enables CF bit in CCON to generate an interrupt ECF 0 disabled that function Figure 55 CMOD PCA Counter Mode Register 70 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 CCON 7 6 5 4 3 2 1 0 Address 0D8H CF CR CCF4 CCF3 CCF2
21. P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Slave O SADDR 1110 0000 SADEN 1111 1001 Given 21110 0XX0 Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 21110 0X0X Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 21110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 6 7 WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution over a longer period of time by causing a system reset when the watchdog timer underflows as a result of a failure of
22. R6 R6 dir R6 E S A R6 R6 rel8 A R6 3 suse CJNE XCH DJNZ MOV dir n A R7 Az dir R7 d8 rel8 A R7 R7 rel8 A R7 P87C51Mx2 User Manual P87C51Mx2 1 2 FO 1 2 MOVX MOVX A DPTR DPTR A 2 2 ACALL Mur 1 addr11 MOVX MOVX A RO QRO A 1 2 MOVX vous R1 A A R1 A A Ki rela A p M MOV dir A F6 17 MOV RO0 A F7 1 MOV R1 A E7 MOV A R1 XCH DJNZ MOV A RO RO rel8 A RO MOV RO A 2 2 E9 XCH DJNZ MOV MOV A R1 R1 rel8 A R1 R1 A 2 2 2 C9 CJNE R1 td8 rel8 MOV R2 A 3 2 DJNZ R2 E ep R2 rel8 Re 3 2 XCH DJNZ MOV R3 E ep A R3 R3 rel8 A R3 2 MOV R3 A 2 2 EC 1 1 XCH DJNZ MOV MOV A R4 R4 rel8 DD 2 2 DJNZ A R4 R4 A 1 1 MOV R5 rel8 R5 A 1 1 MOV R6 A 1 1 MOV R7 A Table 5 51MX Operation Code Chart Part 2 25 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 10 4 3 20 4 3 30 4 3 JBC JB JNB bit rel8 bit rel8 bit rel8 02 5 4 12 5 4 3 2 52 3 2 62 3 2 72 3 3 EJMP ECALL ORL ORL addr23 addr23 dir A ai A ae A C bit 4 3 53 4 3 63 73 2 2 XRL JMP di jus dir p dir d8 A EPTR 3 2 3 2 25 3 2 35 Ge 45 3 2 55 3 2 65 3 2 75 INC MOV dir A a hi A y A Ze dir d8 2 4 58 2 4 EMOV EMOV ADD A OPRO 0 PRO0 0 A PRO 4 59 2 4 EMOV EMOV ADD A OPRO 1 PR0 1 A PRO 1 5A ns EMov ADD A OPRO 2 GROS A PRO 2 5B 2 4 EMov EMOV ADD A OPRO 3
23. WATCHDOG TIMER MODULE 4 ONLY Figure 53 Programmable Counter Array PCA In the CMOD SFR there are three additional bits associated with the PCA They are CIDL which allows the PCA to stop during idle mode WDTE which enables or disables the watchdog function on module 4 and ECF which when set causes an interrupt and the PCA overflow flag CF in the CCON SFR to be set when the PCA timer overflows The watchdog timer function is implemented in module 4 The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer CF and each module To run the PCA the CR bit CCON 6 must be set by software The PCA is shut off by clearing this bit The CF bit CCON 7 is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set The CF bit can only be cleared by software Bits 0 through 4 of the CCON register are the flags for the modules bit O for module 0 bit 1 for module 1 etc and are set by hardware when either a match or a capture occurs These flags can only be cleared by software All the modules share one interrupt vector The PCA interrupt system is shown in Figure 54 Each module in the PCA has a special function register associated with it These registers are CCAPMO for module 0 CCAPM1 for module 1 etc The registers contain the bits that control the mode that each module will operate in The ECCF bit CCAPMn 0 where n 0 1 2 3 or 4 depending on the m
24. follows MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read Special Function Registers E7 E6 E5 E4 E3 E2 E1 EO AA AA A Auxiliary Function Register 1 9 a ee SA E F7 F6 F5 F4 F3 F2 F1 FO Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module O Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low CCAPM2 Module 2 Mode ECOM 2 2 CAPP_2 2 CAPN_2 2 MAT 2 2 TOG 2 2 PWM 2 2 ECCF 2 2 34 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value EN E AAA E DF DE DD DC DB DA D9 D8 PCA Counter High PCA Counter Low Data Pointer 2 bytes Data Pointer High Data Pointer Low Extended Data Pointer Low Extended Data Pointer Middle Extended Data Pointer High AF AE AD AC AB AA A9 A8 EF EE ED EC EB EA E9 ES Interrupt Enable 1 ES1 Interrupt Priority PSO PSOR Interrupt Priority 0 High NEN PPCH PT2H EN PTiH PxiH P
25. linear unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes KB limit to support up to 8 megabytes MB of program memory and 8 MB of data memory lt retains full program code compatibility to enable design engineers to reuse 80C51 development tools eliminating the need to move to a new unfamiliar architecture The 51 MX core retains 80C51 bus compatibility to allow for the continued use of 80C51 interfaced peripherals and Application Specific Integrated Circuits ASICs However by entering the Extended Addressing Mode in order to access either data or code beyond 64 KB the bus interface changes The 51MX core is completely backward compatible with the 80C51 code written for the 80C51 may be run on 51MX based derivatives with no changes Summary of differences between the classic 80C51 architecture and the 51MX core Program Counter The Program Counter is extended to 23 bits Extended Data Pointer A 23 bit Extended Data Pointer called the EPTR has been added in order to allow simple adjustment to existing assembly language programs that must be expanded to address more than 64 KB of data memory Stack Two independent alternate Stack modes are added The first causes addresses pushed onto the Stack by interrupts to be expanded to 23 bits The second allows Stack extension into a larger memory space Instruction set A small number of instructions have extended addressing modes to allow full us
26. only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 41 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 4 4 MODE 3 When Timer 1 is in Mode 3 it is stopped holds its count The effect is the same as setting TR1 O Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 32 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P87C51MB2 MC2 can look like it has an additional Timer Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt TCON Address 88h 7 6 5 4 3 2 1 0 Bit addressable TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION TCON 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when th
27. section Double Buffering INTLO n behaves in the same manner regardless of single of double buffering but the first interrupt occurs different It is also explained in the section Double Buffering CIDIS_n is not related to double buffering 56 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 SnSTAT SOSTAT Address 8Ch MX Extended SFR Space S1STAT Address 84h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h DBMOD n INTLO_n CIDIS_n DBISEL n FE n BR_n OE n STINT n BIT SYMBOL FUNCTION SnSTAT 7 DBMOD n 0 Double buffering disabled 1 Double buffering enabled SnSTAT 6 INTLO n Transmit interrupt position for UART mode 1 2 or 3 0 Tx interrupt issued at beginning of stop bit 1 Tx interrupt issued at end of stop bit Must be 0 for mode O SnSTAT 5 CIDIS n 0 Combined Tx Rx interrupt for Serial Port n 1 Rx and Tx interrupts are separate SnSTAT 4 DBISEL_n Double buffering transmit interrupt select used only if double buffering is enabled DBMOD n set to 1 must be 0 when double buffering is disabled 0 There is only one transmit interrupt generated per character written to SnBUF 1 One transmit interrupt is generated after each character written to SnBUF and there is also one more transmit interrupt generated at the STOP bit of the last character sent e no more data in buf
28. the Program Counter The Program Counter is loaded with the value formed by the sum of the Accumulator and the EPTR Code memory is accessed using the address formed by the sum of the Accumulator and the EPTR The EPTR points to an address anywhere in HDATA memory not DATA IDATA or EDATA The EPTR points to an address anywhere in HDATA memory not DATA IDATA or EDATA Increment the 23 bit EPTR Load a 23 bit value into the EPTR Load a 23 bit address into the Program Counter from the Stack Load the Accumulator with the value from the Universal Memory Map at the address formed by PRO or PRiplus the displacement a value from 0 to 3 Load the Universal Memory Map address formed by PRO or PR1 plus the displacement a value from 0 to 3 with the contents of the Accumulator Add an immediate data value from 1 to 4 to the specified Universal Pointer This is a 24 bit addition Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 1 INSTRUCTION SET SUMMARY The following table summarizes the entire 51 MX instruction set The instructions are grouped by type and instructions that share operand formats are combined 51MX extended instructions and operand combinations are designated by bold text Data Movement Arithmetic 8 Logic Program Control Bit Operations A Rn A Rn SETB C A direct A direct CLR Bit A ORI A ORI CPL A data A data A
29. the bottom of this new address map The HDATA space continues above XDATA The standard internal data memory spaces DATA and IDATA are above HDATA followed by the remainder of the EDATA space Finally the code memory occupies the top of the map Thus the most significant bit of the Universal Pointer determines whether code or data memory is accessed By placing the XDATA space at the bottom of the Universal Memory Map Universal Pointer addresses 00 0000 through 00 FFFF can correspond to the classic 80C51 external data memory space This allows for full backward compatibility for code that does not need more than 64 KB of external data space The Universal Memory Map is shown in Figure 16 while the standard view of the memory spaces and how they relate to Universal Pointer values are shown in Figure 17 The Universal Pointers are used only by a new 51MX instruction called EMOV The EMOV instruction allows moving data via one of the Universal Pointers into or out of the accumulator In either case a displacement of 0 1 2 or 3 may also be specified which is added to the pointer prior to its use The displacement allows C compiler access of variables of up to 4 bytes in size e g Long Integers without the need to alter the pointer value An example of Universal Pointer usage is shown in Figure 18 Note that it is not possible to store a value to the CODE area of the Universal Memory Map Another new instruction is added to allow incrementing one
30. the previous character If double buffering is disabled the UART is compatible with the conventional 80C51 UART Double buffering is enabled by setting the DBMOD n SnSTAT 7 SFR bit to 1 If disabled DBMOD n 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Transmit Interrupts with Double Buffering Without double buffering the transmit interrupt can be selected to occur at either the beginning or the end of the Stop Bit The purpose of the interrupt is to let the user program know when the UART can accept another character As a result the timing of the interrupt has been changed when double buffering is enabled An interrupt is generated each time data is transferred from the buffer register to the transmit shift register Thus if the UART transmit is idle an interrupt will be generated as soon as the buffer register is loaded If the UART is transmitting a character when the buffer register is loaded an interrupt will not occur until the beginning of the Stop Bit of the current character Note that if the buffer is loaded anytime before the end of the Stop Bit characters will be transmitted without extra Stop Bit time Also if a character is loaded into the buffer during the stop bit the interrupt will occur when the buffer is loaded There is one additional feature with respect to the occurrence of interrupts when double buffering is enabled
31. via external interrupt the core automatically clears the PD bit and thus enables a new entry into Power Down Mode Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down Mode In Power Down mode the power supply voltage may be reduced to the RAM keep alive voltage Vram This retains the RAM contents at the point where Power Down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vrawm therefore it is recommended to wake up the processor via Reset in this case since Reset redefines all SFRs including PD bit but doesn t change on chip RAM Vpp must be raised to within the operating range before the Power Down mode is exited 38 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 MODE Program Memory PSEN PORTO PORT 1 PORT 2 PORT 3 we mer 31 CI CI Dm Dus Due Emma 1 o p Rem Bem omes Das Teen mew s s om om Dm Dm eem Sea s s ree ome Ome Dm Table 9 External Pin Status During Idle and Power Down Modes PCON Power Control Register Reset Value Reset Value 000 0000B See description below for PCON 4 reset value BIT SYMBOL FUNCTION PCON 7 SMOD1 Baud Rate Control bit for serial port UART When 0 the baud rate for UART is the input rate T1 timer or baud rate generator as dete
32. 1MX Enhancement these instructions use the prefix byte 51MX Effect 80C51 Instruction Without Prefix P87C51Mx2 User Manual P87C51Mx2 51MX Effect with Prefix Load a 16 bit address into the Program Counter Load a 16 bit address into the Program Counter The lower 16 bits of the Program Counter are replaced with the sum of the Accumulator and the active DPTR Code memory is accessed using the address formed by replacing the lower 16 bits of the Program Counter with the sum of the Accumulator and the active DPTR The active DPTR points to an address in the 64 KB XDATA memory LCALL addr16 ECALL addr23 LJMP addr16 JMP A DPTR MOVC A A DPTR EJMP addr23 JMP A EPTR MOVC A A EPTR MOVX EPTR A The active DPTR points to an MOVX DPTR A address in the 64 KB XDATA MOVX A QDPTR memory Increment the active Data Load a 16 bit value into the MOV DPTR data16 active Data Pointer m Load a 16 bit address into the R MOVX A EPTR INC EPTR MOV EPTR data23 Program Counter from the ERET Stack Logically OR Register n to the Accumulator EMOV A PRi disp Logically AND Register n to the Accumulator EMOV PRi disp A Exclusive OR Register n to the 1 ORL L ABE Accumulator E R A Rn Table 2 Enhancements to the 80C51 Instruction Set Enabled by the Prefix Byte ADD PRi data2 21 Load a 23 bit address into the Program Counter Load a 23 bit address into
33. 2 Timer 2 Interrupt Enable IENO 4 ESO ESOR Serial Port 0 Combined Interrupt Enable SOSTAT 5 0 Serial Port O Receive Interrupt Enable SOSTAT 5 1 IENO 3 ET1 Timer1 Overflow Interrupt Enable IENO 2 EX1 External Interrupt 1 Enable IENO 1 ETO Timer 0 Overflow Interrupt Enable IENO O EXO External Interrupt O Enable Figure 20 Interrupt Enable Register IENO IEN1 Address E8h Bit addressable Reset Value 00h BIT SYMBOL IEN1 7 3 IEN1 2 ES1T IEN1 1 ESOT IEN1 0 ES1 ES1R 2 4 0 ES1T ESOT ESYESIR FUNCTION Reserved for future use Should be set to O by user programs If S1STAT 5 1 it is Serial Port 1 Transmit Interrupt Enable If S1STAT 5 0 this interrupt is disabled anyway If SOSTAT 5 1 it is Serial Port O Transmit Interrupt Enable If SOSTAT 5 0 this interrupt is disabled anyway Serial Port 1 Combined Interrupt Enable S1STAT 5 0 Serial Port 1 Receive Interrupt Enable S1STAT 5 1 Figure 21 Interrupt Enable Register IEN1 31 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 IPO Address B8h Bit addressable Reset Value 00h PPC PT2 PSOPSOR PT1 PX1 PTO PXO BIT SYMBOL FUNCTION IPO 7 Reserved for future use Should be set to O by user programs IP0 6 PPC PCA Interrupt Priority bit Low
34. 6 Reset Start Bi DO X DT X D2 X D3 X D4 X D5 X D6 CY Stop Bi Shift fl D D fl fl l Receive RI Figure 46 Serial Port Mode 1 Only Single Transmit Buffering Case Is Shown TX Clock fl 1 1 1 1 I JL I1 TL T T TL TL IL Write to SBUF l Shift I Jl JL IL A m m Y A Transmit DE Start Bit D XDI X 02 X D3 X D4 X DS X 06 X D7 X 188 Y Stop Bi TI q INTEO_n 0 INILO n 1 polos STE E AE M E M MO A MO O A MO A O M M RxD 16 ResetStart DA DO X Di X D2 X D3 X D4 X DS X D6 X D7 X_RB8_y Stop Bit so o NONO mm AN ALAN E RI Receive SMODO 0 SMODO 1 Figure 47 Serial Port Mode 2 or 3 Only Single Transmit Buffering Case Is Shown 59 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 11 DOUBLE BUFFERING Each of the P87CMx2 s UARTS optionally has the ability to buffer the next character to be transmitted while the current character is still being shifted out of the transmit shift register The advantage of double buffering comes when it is desired to transmit a string of characters with only a single Stop Bit between characters In order to accomplish this on the original 80C51 UART the next character be loaded while the Stop Bit of the previous character was being sent Double buffering allows the next character to be loaded at any time from the beginning of the Start bit to the end of the Stop Bit of
35. 87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 If INTLO_n is 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur rently in the shifter If INTLO_nis 1 UART mode 1 2 or 3 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 4 Note that if DBISEL_nis 1 and when the CPU is writing to SNBUF about the same time the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 6 6 12 MULTIPROCESSOR COMMUNICATIONS UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8_n The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8_n 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data
36. A MEE A Moa 8 EE Il Table 12 SFR Extended SFR Locations for UARTs 6 6 6 BAUD RATE GENERATOR AND SELECTION The P87C51Mx2 enhanced UARTs have one associated independent Baud Rate Generator The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs in the extended SFR space BRGR1 7 0 BRGRO 7 4 together form a 12 bit baud rate divisor value BRATE1 1 0 that works in a similar manner as Timer 1 2 but if the baud rate generator is used Timer 1 2 can be used for other timing functions UART 0 can use either Timer 1 2 see T2CON 5 4 or the baud rate generator output as determined by BRGCON 2 1 in the extended SFR space while UART 1 only uses the baud rate generator Note that in UART 0 Timer T1 is further divided by 2 if the SMOD bit PCON 7 is cleared T2 for UART 0 and the independent Baud Rate Generator for both UARTs will be used as is without the divided by 2 option see Figure 42 BRGRO Address 86h MX Extended SFR Space Not bit addressable V 6 5 4 3 2 1 0 Reset Value 00h BRATES3 BRATE2 BRATE1 BRATEO BIT SYMBOL FUNCTION BRGRO 7 4 BRATE3 0 Baud rate divisor bits 3 0 BRGRO 3 0 Reserved for future use Should be set to 0 by user programs Figure 39 BRGRO Register 52 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 BRGR1 A
37. B8 the 8 data bits go into SBUF and RI is activated 6 6 10 MORE ABOUT UART MODES 2 AND 3 Reception is performed in the same manner as in mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF s se si n s6 s1 m se s se s1 se s Se s 2 se s se s1 se s1 Y se s1 S sel i sel se Write to SBUF 1 Shift 1 1 1 m 1 1 1 1 TxD Shift Clock TI E TAE cac c r Transmit Write to SCON Clear RI RI l Shift l l l l l l 1 1 Receive RxD DO D1 D2 D3 D4 D5 D6 D7 Data In i i i i i TxD Shift Clock Figure 45 Serial Port Mode 0 Only Single Transmit Buffering Case Is Shown 58 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 TX Clock l fl l fl 1 I JI III Tm dL IL Write to SBUF l En Shift l l JL NA m nm n n mnm Transmit me Start Bi BOX Di X D2 X D3 X D4 X D5 X D6 X D7 Y Stop Bit TI INTE n 0 INTCO_n 1 RX Clock l 1 fl l 1 1 l l I l 1 l 1 Il RxD 1
38. D ADDC ORL ANL XRL MOV R1 A R1 A R1 A R1 A R1 A R1 R1 d8 ADD ADDC ORL ANL XRL MOV A R2 A R2 A R2 A R2 A R2 R2 d8 6B 2 1 ES ADD ADDC ORL XRL MOV A R3 A R3 A R3 f R3 d8 1 1 E 5 E B iN T E Ha x T S ne D D D 3C 1 4 4C 1 1 1 11 1 1 7C 2 1 D ADD ADDC ORL MOV E A R A R4 A R4 R4 d8 1 1 1 1 1 1 7D 2 1 DEC ADD ADDC ORL MOV R A R5 A R5 R5 d8 1 1 1 1 111 7E 2 1 D ADD ADDC ORL MOV A R6 A R6 R6 d8 1 1 4F 1 1 1 1 14 7F 2 1 B D ADD ADDC ORL MOV A R7 A R7 R7 d8 Table 4 51MX Operation Code Chart Part 1 24 Preliminary 2002 June 28 Philips Semiconductors Extended Address Range Microcontroller 3 2 SUMP rel8 DP di 6 ae AJMP addr11 ter 2 2 B2 ANL MOV C bit AC C C bit app A d8 1 2 MO MOVC A A PC A A DPTR MOV SUBB dir dir A dir M SUBB dir RO A RO SUBB A RO dir RO SUBB 2 2 99 din o A R1 SUBB 2 2 9C dir nA A R4 A4 1 MX extension A8 erm MOV o RO dir MOV R1 dir DA dir MOV R5 dir 2 2 3 2 C6 1 1 1 1 OV CJNE XCH XCHD MOV RO d8 rel8 A RO A RO A RO A7 2 2 3 2 1 1 1 11 MOV SUBB MOV XCHD dir R1 A R1 R1 dir ORT 408 rel8 re OR A OR 3 OV NE 3 2 2 2 CJ RO d8 rel8 2 2 V 2 2 9A AA o R2 dir AB oy 2 2 3 2 CC R4 PM on mA c 2 MOV din 2 2 SUBB MOV din 3 A R3 R3 dir MOV 5 6 7 d 3 2 SUBB MOV XCH DJNZ MOV dir Re A
39. E Watchdog timer with programmable prescaler for different time ranges compatible with 8xC66x with added prescaler 80C51 COMPATIBILITY FEATURES OF THE 51MX CORE 100 binary compatibility with the classic 80C51 so that existing code is completely reusable Linear program and data address range expanded to support up to 8 MB each Program counter and data pointers expanded to 23 bits Stack pointer extended to 16 bits 2 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 1 3 P87C51MX2 LOGIC SYMBOL Address Bus 0 7 Data Bus P87C51Mx2 Address Bus 16 22 a 1 o6 a 3 ke 9 a D Mo ke lt EA Vpp PSEN ALE PROG Figure 1 P87C51Mx2 Logic Symbol 3 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 1 4 P87C51MX2 BLOCK DIAGRAM High Performance 80C51 CPU 51 MX Core 96KB 64KB Code OTP 4 gt t Internal Bus 3KB 2KB Baud Rate Data RAM Generator i gt UART 1 Port 3 Port 2 Timero MU PCA Programmable Counter Array Crystal or f 3 Ec Ta EA Oscillator Timer i C Figure 2 P87C51Mx2 Block Diagram 4 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 MEMORY ORGANIZATION 2 1 PROGRAMMER S MOD
40. ELS AND MEMORY MAPS The P87C51Mx2 retains all of the 80C51 memory spaces Additional memory space has been added transparently as part of the means for allowing extended addressing The basic memory spaces include code memory which may be on chip off chip or both external data memory Special Function Registers and internal data memory which includes on chip RAM registers and stack Provision is made for internal data memory to be extended allowing a larger processor stack The P87C51Mx2 programmer s model and memory map is shown in Figure 3 7F FFFFh Two 24 bit Universal Pointers 7E FFFFh HDATA includes XDATA 23 bit Program Counter 23 bit Extended Data Pointer Two 16 bit DPTRs 16 bit Stack Pointer EDATA includes DATA amp IDATA On Chip and or Ger Off Chip Off Chip y Data Memory Code Memory stack and indirect addressing Extended SFRs IDATA includes DATA ls E 256 Byte On Chip egisters Data Memory 00 07FFh directly addressable stack and indirect 00 06FFh addressing DATA Data Memory P87C51MC2 128 Byte On Chip 00 0300h Data Memory 00 02FFh stack direct and indirect addressing 768 Bytes On Chip Data Memory Four Register Banks P87C51MB2 00 0000h HO Hz 00 0000h 8 MB Code Data Memory Space 8 MB 64 KB External Memory Space DATA IDATA EDATA Data Memory Space XDATA HDATA Figure 3 P87C51MB2 C2 Programmer s Model and Memory Map 5 Preliminary 2002 June 28 Philips
41. EN1 The IENO register also contains a global disable bit EA which disables all interrupts at once Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the IPO IPOH IP1 and IP1H registers An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source So if two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level Table 8 summarizes the interrupt sources flag bits vector addresses enable bits priority bits polling priority and whether each interrupt may wake up the CPU from Power Down mode Flag Bit s Address Enable Bit s Priority Priority Wakeup Exema merupo E0 ooon EXOUENO0 Tea Poo 1 tiones Yes mero mert mo 908 Tee Pona Por No ar E ACE EES Serial Port 0 Tx and Rx TI_08 RI E 0023h ESO IENO 4 IPOH 4 IPO 4 Serial Port 0 Rx RO Timer 2 Interrupt TF2 EXF2 002Bh ET2 IENO 5 IPOH 5 IPO 5 PCA interrupt CF CCFn
42. INTEGRATED CIRCUITS USER S MANUAL P87C51MB2 P87C51MC2 80C51 8 bit microcontroller family with extended memory 64KB 96KB OTP with 2KB 3KB RAM Preliminary 2002 June 28 Version 0 95 Philips Semiconductors PHILIPS Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 DL INTRODUCTION uni cubiaasnsnsucenssveerensssoenudonsssuaeis oaas Sr oneee E aaae ea a SESS EEEo EESE 1 1 1 The SINE CPU EE 1 1 2 REN e 1 1 3 PSTCSTMX2 Logle TEE 3 LA P87C51Mx2 Block Diagram pili EEGENEN Edge 4 2 Memory Organiza a 5 2 1 Programmer s Models and Memory Maps inocentada aene 5 2 2 Data Memory DATA IDATA and EDATA ENNER 6 2 2 1 Registers RO quu alias eos 6 22 2 Bit Addressable RAM coto tae ie r t a d tt i s n SS 7 223 Extended Data Memory CEDATA o ssscc3scsccecasehecionesssnateqnsscassecouasiepeoncsevaaaneatere ncedss 7 ZPO E EE EE T 2 2 3 General Purpose RAIN ed Sen A I Rs 10 2 9 Special Function Registers SERS comicios acre rs sat exeun recia e anda Pe be v se dean eo ug 11 2 4 External Data Memory CADATA birria rn eoe regu EEN ere 12 2 5 High Data Memory HDAT A nieto ee toan e Ree ag TY e Pe e NER LN PVP e PEE SEE EVER RES 12 20 Program Memory CODEN oea hir Ee 14 2 7 BK 15 3 gt SIMX Instructions A Seet 20 3 1 Instruction Set Summary a ere ne ene din etica 22 3 27 SEX Operation Codo Cs de a es ce do 23 4 Externa
43. If the DBISEL_n SFR bit is a 0 an interrupt occurs only when data is transferred from the buffer to the transmit shift register Thus each character generates a single interrupt The operation is identical if DBISEL n is a 1 As long as the buffer register is filled before the stop bit is reached If DBISEL n is a 0 and the INTLO n SFR bit is a 1 an interrupt will occur at the end of the Stop Bit of the last character if the buffer register is empty If If DBISEL_n is a 0 and the INTLO n SFR bit is a 0 an interrupt will be generated at the beginning of the Stop Bit if the transmit buffer register is empty Note that in this case if the transmit buffer is loaded before the end of the stop bit another interrupt will be generated and the UART will transmit this new character without lengthening the Stop Bit 60 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Write to 1 n n n l SnBUF Tx Interrupt 1 ji 1 i Single Buffering DBMOD_n SnSTAT 7 0 Early Interrupt INTLO n SnSTAT 6 0 is Shown Write to M if 4 l SnBUF Tx Interrupt 1 1 1 1 Double Buffering DBMOD n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown No Ending Tx Interrupt DBISEL_n SnSTAT 4 0 it i 1 Tx Interrupt 1 1 1 1 i Double Buffering DBMOD_n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown With Ending Tx Interrupt DBISEL_n SnSTAT 4 1
44. N 1 C T2 Timer or counter select Timer 2 0 Internal timer fosc 6 1 External event counter falling edge triggered external clock s max rate fosc 12 T2CON 0 CP RL2 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 33 Timer Counter 2 T2CON Control Register RCUGTOLK cz 39m wo ANA LL s Table 10 Timer 2 operating mode 46 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 T2MOD Address C9h Not bit addressable 7 6 5 4 3 2 1 0 Reset Value XXXXXX00B T2OE DCEN BIT SYMBOL FUNCTION T2MOD 7 2 Reserved for future use Should be set to O by user programs T2MOD 1 T20E Timer 2 Output Enable bit T2MOD 0 DCEN Down Count Enable bit When set this allows timer2 to be configured as an up down counter User software should not write 1s to reserved bits These bits may be used in future 8051 family products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 The value read from a reserved bit is indeterminate
45. N 6 EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Microcontroller s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 1 in the first machine cycle pin T2EX has to be sampled as 1 in the second machine cycle it has to be sampled as 0 and in the third machine cycle EXF2 will be set to 1 T2CON 5 RCLK Receive clock flag When set causes the serial port O UART 0 to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 RCLK 0 causes Timer 1 overflow to be used for the receive clock See section on UARTS T2CON 4 TCLK Transmit clock flag When set causes the serial port O UART 0 to use Timer 2 overflow pulses for its transmit clockN in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 TCLK 0 causes Timer 1 overflows to be used for the transmit clock See section on UARTS T2CON 3 EXEN2 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX T2CON 2 TR2 Start stop control for Timer 2 A logic 1 enables the timer to run T2CO
46. NL C bit Rn A A ORL C bit Rn direct Rn bit rel Rn data direct MOV C bit direct A Ri bit C direct Rn direct direct DPTR A DPTR direct Ri EPTR A EPTR direct data Ri A PRi data2 A direct rel Ri direct A data rel Ri data AB Rn data rel DPTR data16 Ri data rel EPTR data23 Rn rel A A DPTR direct rel A A PC A A EPTR addr11 A Ri addr16 A Rn addr23 EPTR A A direct A Ri A PRi disp A data PRi disp A direct A direct data direct A Ri Table 3 51MX Instruction Set Summary 22 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 2 51MX OPERATION CODE CHARTS This 51MX opcode chart consists of four pages The first two pages are identical to a classic 80C51 opcode chart except that the A5h opcode is marked as the MX extended instruction prefix value The third and fourth pages show instruction encoding that follows the A5h prefix These instructions are unique to the 51MX and are divided into several types as shown below Contents of Each Table Entry opcode bytes cycles instruction mnemonic operand s 51MX Extended Instruction Types Unmodified 80C51 Instruction These instructions are identical to classic 80C51 instructions and thus appear only on the first two pages of the opcode chart New MX These instructions are new to the 51MX All are related to the Universal Instructions Pointers Extend
47. R Loot RESET CH F9H CL E9H PCA TIMER COUNTER 0 0 1 X 0 X Figure 58 PCA Watchdog Timer Module 4 only In order to hold off the reset the user has three options 1 periodically change the compare value so it will never match the PCA timer 2 periodically change the PCA timer value so it will never match the compare values or 3 disable the watchdog by clearing the WDTE bit before a match occurs and then re enable it The first two options are more reliable because the watchdog timer is never disabled as in option 3 If the program counter ever goes astray a match will eventually occur and cause an internal reset The second option is also not recommended if other PCA modules are being used Remember the PCA timer is the time base for all modules changing the time base for other modules would not be a good idea Thus in most applications the first solution is the best option The following shows the code for initializing the watchdog timer INIT WATCHDOG MOV CCAPM4 04Ch Module 4 in compare mode MOV CCAP4L 0FFh Write to low byte first MOV CCAP4H 0FFh Before PCA counts up to FFFFh these compare values must be changed ORL CMOD 040h Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD CALL the following WATCHDOG subroutine periodically CLR EA Hold off interrupts MOV CCAP4L 00 Next compare value is within 255 counts of current PCA t
48. Range Microcontroller P87C51Mx2 MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0E1h Feed sequence second part SETB EA Enable interrupts Note that Upon a power up or any reset including WDT reset the watch dog timer is disabled Executing the feed sequence once will start the WDT Once started it cannot be disabled until reset again The watchdog is enabled by a write of 1Eh followed by a write of E1h to the WDTRST register Before the first 1Eh is written to WDTRST a write of any pattern other than 1Eh will not cause a reset Once an 1Eh is written to the WDTRST register any write of a pattern other than 1Eh or E1h to the WDTRST register will cause a watchdog reset The triggering event to restart the WDT is the second part writing E1h to the WDTRST SFR of the feed sequence Refer to Figure 49 for details of WDT operations including effects of illegal feed patterns to the WDTRST SFR 64 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Any Reset WDT disabled Wait for next write to the WDTRST SFR ritten 01Eh to the WDTRST SFR es WDT disabled Wait for next write to the WDTRST SFR Neither 1E h nor El WDT Reset 1Eh alue written to the WDTRST SFR Elh Start WDT WDT enabled Wait for next write to the WDTRST SFR Ti t ime ou gt Elh alue written to the Neither
49. Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it EDATA Extended Data This is a superset of DATA and IDATA areas Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory The added area may be accessed only as Stack and via indirect addressing using Universal Pointers The Stack may reside in the extended area if enabled to do so SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing addresses in range 80h FFh This includes the new 51MX extended SFRs XDATA External Data Duplicates the classic 80C51 64 KB memory space addressed via the MOVX instruction using the DPTR RO or R1 On chip XDATA can be disabled under program control Also XDATA may be placed in external devices P87C51MB2 has 768 bytes of on chip XDATA memory space and P87C51MC2 has 1792 by
50. TOH PXOH ia id coded IEEE et PSiT PSOT PSIR ric E Ze E em PS1TH PSOTH PS1RH 35 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value A7 A6 AS A4 A3 A2 Al AO AD14 ADA13 AD11 AD10 AD9 AD8 ADS AD22 AD21 AD19 AD18 AD17 AD16 B7 B6 B5 B4 B3 B2 B1 BO m wi m m wr wm moo mo c7 cet cst c4t c3t cat CO cot Port 4 E RS A E E A Power Control Register ERAN eae ea EA REA EA OM PSW Program Status Word RS1 RSO OV RCAP2H Timer2 Capture High RCAP2L Timer2 Capture Low 9F 9E 9D 9C 9B 9A 99 98 SOCON Serial Port 0 Control SMo Bie SEH AO re REN mo mo SOBUF Serial Port 0 Data Buffer Register SOADDR Serial Port 0 Address Register SOADEN Serial Port 0 Address Enable SOSTAT Serial Port 0 Status DBMOD_ NTLO 0 cipis o peisEL o STINT O Serial Port 1 Control x EE ee alee IORA Serial Port 1 Data buffer Register Serial Port 1 Address Register Serial Port 1 Address Enable Serial Port status Ree INTLO_1 CIDIS_1 DBISEL1 STINT 1 Stack Pointer or Stack Pointer Stack Pointer High Timer Control Register 36 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Special Function Registers Co
51. This addressing mode allows access to any of the on chip or off chip code and data spaces using one instruction without the need to know in advance which of the different spaces the data will reside in This includes the DATA IDATA EDATA XDATA HDATA and CODE spaces The SFR space is the only space that may not be accessed using the Universal Pointer mode 15 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The Universal Pointer addressing mode uses a new set of pointer registers for two reasons The first is that 24 bit pointers are needed in order to allow addressing both the 8 MB code space and the 8 MB data space The other reason is that itis much more efficient to manipulate multi byte pointer values in registers than it is in SFRs C compilers typically already perform pointer manipulation in registers then move the result to a Data Pointer for use Two Universal Pointers are supported PRO and PR1 The pointer PRO is composed of registers R1 R2 and R3 of the current register bank while PR1 is composed of registers R5 R6 and R7 of the current register bank as shown in Figure 15 Figure 15 Universal Pointer Registers In order to access all of the various memory spaces in a single unified manner they must all be mapped into a new view that allows 16 MB of total memory space This new view is called the Universal Memory Map The XDATA space is placed at
52. applications where Vcc lt 4V reduces power consumption AUXR1 3 GF2 General purpose user defined flag AUXR1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register AUXR1 1 Reserved for future use Should be set to O by user programs AUXR1 0 DPS Data Pointer Select Chooses one of two Data Pointers for use by the program See text for details Figure 52 AUXR1 Register 6 8 2 DUAL DATA POINTERS The dual Data Pointer DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are e INC DPTR Increments the Data Pointer by 1 e JMP EA DPTR Jump indirect relative to DPTR value e MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move data byte from data memory relative to DPTR to the accumulator e MOVX DPTR A Move data byte from the accumulator to data memory relative to DPTR Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS Bit 2 of AUXR1 is permanen
53. ate INTn Pin Figure 30 Timer Counter 0 or 1 in Mode 1 16 Bit Counter Osc 6 nO og Tn Pin C T 21 Overflow TFn Interrupt TRn Gate INTn Pin Figure 31 Timer Counter 0 or 1 in Mode 2 8 Bit Auto Reload 43 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Osc 6 C T 0 e Be TLO Overflow 0 8 bits TFO gt Interrupt TO Pin Cff 1 Control TRO Gate INTO Pin THO Overflow Osc 2 e o 8 bits p gt Interrupt Control TRI Figure 32 Timer Counter 0 Mode 3 Two 8 Bit Counters 6 5 TIMER 2 Timer 2 is a 16 bit Timer Counter which can operate as either an event timer or an event counter as selected by C T2 in the special function register T2CON Timer 2 has three operating modes Capture Auto reload up or down counting and Baud Rate Generator which are selected by bits in the T2CON as shown in Figure 33 6 5 1 CAPTURE MODE In the capture mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the timer 2 overflow bit This bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IE register If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition a
54. byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes SM2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit although this is better done with the Framing Error flag In a Mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 6 6 13 AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one
55. cations may be considered general purpose RAM and used in any desired manner The lower 128 bytes of the internal data memory DATA may be accessed using either direct or indirect addressing Direct addressing incorporates the entire address within the instruction For example the instruction MOV 31h 10 will store the value 10 decimal in location 31 hex Direct addresses above 128 will access the Special Function Registers rather than the internal data memory Indirect addressing takes an address from either RO or R1 of the current register bank and uses it to identify a location in the internal data memory The entire 256 byte internal data memory space IDATA may be accessed using indirect addressing For example the instruction sequence MOV RO 90h MOV A RO will cause the contents of location 90 hex to be loaded into the accumulator It is typical with the classic 80C51 to cause the stack to be located in the upper area leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect addressing With the 51MX the stack may be extended and moved completely out of the lower 256 bytes of memory Undedicated Area Bit Addressable Segment Register Banks Figure 7 Internal Data Memory Lower 128 Bytes 10 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 3 SPECIAL FUNCTION REGISTERS SFRS Sp
56. ck for Timer Counter 2 or 2 To output a 50 duty cycle clock ranging from 122Hz to 8 MHz at a 16MHz operating frequency To configure the Timer Counter 2 as a clock generator bit C T2 in T2CON must be cleared and bit T20E in T2MOD must be set Bit TR2 T2CON 2 also must be set to start the timer The Clock Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in this equation OscillatorFrequency 2x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer The 6 in the denominator of the above equation indicates six oscillator cycles per machine cycle In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously Note that the equations for baud rate and the Clock Out frequency are different 45 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 T2CON Address C8h Bit addressable Reset Value 00h 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 BIT SYMBOL FUNCTION T2CON 7 TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK or TCLK 1 T2CO
57. cle i e 1 6 the oscillator frequency As a baud rate generator it increments at the oscillator frequency Thus the baud rate formula is as follows Modes 1 and 3 Baud Rates Oscillator Frequency 16 X 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L The content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer The Timer 2 as a baud rate generator mode is valid only if RCLK and or TCLK 1 in T2CON register Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Thus the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Also if the EXEN2 T2 external enable flag is set a 1 to 0 transition in T2EX Timer counter 2 trigger input will set EXF2 T2 external flag but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Therefore when Timer 2 is in use as a baud rate generator T2EX can be used as an additional external interrupt if needed When Timer 2 is in the baud rate generator mode one should not try to read or write TH2 and TL2 Under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be written to because a 47 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 r
58. d or data write operations In 51MX devices the external bus duplicates the classic 80C51 multiplexed external bus but allows increasing the address output to 23 bits 4 1 MULTIPLEXED EXTERNAL BUS The 51MX external bus supports 8 bit data transfers and up to 23 address lines The number of address lines available is configurable and depends on the setting of the EAM bit in the MXCON register The default for an unprogrammed part following reset is 16 address bits This provides drop in compatibility in existing 80C51 sockets A non volatile configuration bit allows pre selecting a 23 bit address size at the time that the part is programmed Software may later enable the extended addressing mode even if the pre programmed configuration does not The non volatile address configuration is implemented using EPROM technology The configuration is comprised of a single bit that enables multiplexing of the 7 extended address bits on Port 2 If the non volatile configuration bit is not programmed extended addressing may be enabled at run time via the EAM bit in the MXCON SFR Software may write a 1 to MXCON changing the default configuration Typically this would be done a single time If software reads the EAM bit in MXCON the value will be the logical OR of the non volatile configuration bit and the MXCON EAM bit value It is not recommended to change the address configuration dynamically during program execution for example changing EAM 1 to EAM 0 c
59. ddress 87h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h BRATE11BRATE10 BRATE9 BRATE8 BRATE7 BRATE6 BRATE5 BRATE4 BIT SYMBOL FUNCTION BRGR1 7 0 BRATE11 4 Baud rate divisor bits 11 4 Figure 40 BRGR1 Register Updating the BRGR1 and BRGRO SFRs The effective baud rate is a 16 bit value The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value when only one of BRGR1 and BRGRO is written to the baud rate generator CAUTION If any of BRGRO or BRGR1 is written if BRGEN 1 result is unpredictable T2CON 5 4 RCLK Receive TCLK Transmit BRGCON 1 SOBRGS Receive Transmit Baud Rate for UART 0 X fosc 6 T1 rate 32 T1 rate 16 T2 rate 16 fosc BRATEx16 16 T1_rate 32 T1_rate 16 T2_rate 16 Receiver and transmit clocks can be different Table 13 Baud Rate Generation for UART 0 Use T2CON 5 RCLK in Receive Baud Rate Selection T2CON 4 TCLK in Transmit Baud Rate Selection 53 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 S1CON 7 S1CON 6 SMO_1 SM1_1 Baud Rate for UART 1 ee ESTAS foso BRATEX16 16 UART 1 has the same receive and transmit baud rate Table 14 Baud Rate Generation for UART 1
60. e of extended code and data addressing Addressing Modes A new addressing mode Universal Pointer mode is added that allows accessing all of the data and code areas except for SFRs using a single instruction This mode produces major improvements in size and performance of compiled programs Six clock cycles per machine cycle The 51MX core is described in more details in the 51MX Architecture Reference 1 2 P87C51MX2 MICROCONTROLLERS The P87C51Mx2 represents the first microcontroller based on the 51MX core The P87C51MC2 features 96 KB of OTP program memory and 3 KB of data SRAM while the P87C51MB2 has 64 KB of OTP and 2 KB of RAM In addition both devices are equipped with a Programmable Counter Array a watchdog timer that can be configured to different time ranges as well as two enhanced UARTs The P87C51Mx2 provides greater functionality increased performance and overall lower system cost By offering an embedded memory solution combined with the enhancements to manage the memory extension the P87C51Mx2 eliminates the need for software workarounds The increased program memory enables design engineers to develop more complex programs in a high level language like C for example without struggling to contain the program within the traditional 64 KB of program memory These enhancements also greatly improve C language efficiency for code sizes below 64 KB KEY FEATURES 23 bit program memory space and 23 bit data memory space
61. e processor vectors to interrupt routine or by software TCON 6 TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TCON 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to interrupt routine or by software TCON 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off TCON 3 1E1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software TCON 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts TCON 1 IEO Interrupt O Edge flag Set by hardware when external interrupt O edge is detected Cleared by hardware when the interrupt is processed or by software TCON 0 ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts Figure 28 Timer Counter Control Register TCON 42 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Overflow x e dal Interrupt 5 bits 8 bits Tn Pin e Cff 1 TRn Gate INTn Pin Figure 29 Timer Counter 0 or 1 in Mode 0 13 Bit Counter Overflow ME n Trin Interrupt a 8 bits 8 bits Tn Pin Lo C f 21 TRn G
62. ecial Function Registers SFRs provide a means for the processor to access internal control registers peripheral devices and I O ports An SFR address is always contained entirely within an instruction The standard SFR space is 128 bytes in size SFRs are implemented in each 51MX device as needed in order to provide control for peripherals or access to CPU features and functions Undefined SFRs are considered reserved and should not be accessed by user programs Sixteen addresses in the SFR space are both byte and bit addressable The bit addressable SFRs are those whose address ends in Oh or 8h i e 80h 88h F8h Bit addressing allows direct control and testing of bits in those SFRs All 51MX devices also have additional 128 bytes of extended SFRs as discussed in the 51MX Architecture Reference Figures 8 and 9 show the SFR and the Extended SFR maps for P87C51MB2 C2 parts 2 A 3 B 4 C 5 D Pi GH GORPOH OGAPTA E TTT ewer E E E E ss B RON guo bcd cus NN Oo M EES Bee ag E We e DEE ES WE L TI eee WT 500 l JEN A 1 LL EM GEN TI WW A y M PEA ee AA T 9d NN Bremen L 9 MM T Bit Addressable SFRs Figure 8 Standard SFR Map for the P87C51Mx2 Figure 9 shows the extended SFR map for the P87C51Mx2 11 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 T
63. ed These instructions incorporate extended addressing and are modified Addressing versions of classic 80C51 instructions Instructions These instructions allow access to the expanded SFR space These are not actually new instructions but are classic 80C51 instructions whose function are altered by the A5h opcode Extended SFR Addressing Operand Definitions Used in the Tables addr11 11 bit address bit addressable bit d8 8 bit immediate data addri6 16 bit address dir direct address d16 16 bit immediate data addr23 23 bit address rel8 8 bit relative address d23 23 bit immediate data 23 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 2 3 2 3 2 2 2 2 2 2 2 JBC JNZ bit rel8 S GI bie Ze Ge pi Ge rel8 Be ee is pee Bree AJMP ACALL ACALL addr1 1 addr11 art 1 So i art 1 SCC i sean 1 addr11 3 2 1 2 1 2 52 LJMP LCALL ORL ANL XRL ORL addr16 addr16 dir A dir A dir A C bit 3 2 3 2 RAG a JMP diras dir bap di pas A DPTR 44 IN DEC ADD ADDC ORL ANL XRL MOV A d8 A d8 A d8 A d8 A d8 A d8 INC DEC ADD ADDC ORL ANL XRL MOV dir dir A dir A dir A dir A dir A dir dir d8 1 4 46 6 INC DEC ADD ADDC ORL ANL XRL MOV ORO ORO A ORO A ORO A RO A ORO A ORO RO d8 INC DEC ADD ADDC ORL ANL XRL MOV ORI R1 A R1 A R1 A R1 A R1 A R1 R1 d8 es ADD ADDC ORL ANL XRL MOV A RO A RO A RO A RO A RO RO d8 1 4 49 9 DEC AD
64. ed for future use Should be set to 0 by user programs IP1 2 PS1T Serial Port 1 transmit Interrupt S1STAT 5 1 Priority Low Bit 1P1 1 PSOT Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority Low Bit IP1 0 PS1 PS1R Serial Port 1 combined Interrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority Low Bit Figure 24 Interrupt Priority Register 1 IP1H Address F7H 7 6 5 4 3 2 1 0 Not bit addressable i y PS1TH PSOTH PS1HPSIRH Reset Value 00h BIT SYMBOL IP1H 7 3 2 IP1H 2 PS1TH IP1H 1 PSOTH IP1H 0 PS1H PS1RH FUNCTION Reserved for future use Should be set to 0 by user programs Serial Port 1 transmit Interrupt S1STAT 5 1 Priority High Bit Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority High Bit Serial Port 1 combined Interrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority High Bit Figure 25 Interrupt Priority Register 1 High Byte 33 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 P87C51MX2 PORTS POWER CONTROL AND PERIPHERALS 6 1 SPECIAL FUNCTION REGISTERS Note Special Function Registers SFRs accesses are restricted in the following ways 1 User must NOT attempt to access any SFR locations not defined 2 Accesses to any defined SFR locations must be strictly for the functions for the SFRs 3 SFR bits labeled 0 or 1 can ONLY be written and read as
65. egisters Table 11 shows commonly used baud rates and how they can be obtained from Timer 2 6 5 5 SUMMARY OF BAUD RATE EQUATIONS Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Baud Rate Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally the baud rate is Baud Rate fosc 16 x 65536 RCAP2H RCAP2L Where fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as RCAP2H RCAP2L 65536 fosc 16 x Baud Rate 6 5 6 TIMER COUNTER 2 SET UP Except for the baud rate generator mode the values given for T2CON do not include the setting of the TR2 bit Therefore bit TR2 must be set separately to turn the timer on RCUGTOLK cem 5 Mo Baud rate generator for UART 0 if SOBRGS BRGCON 1 0 off Timer 2 RCAP2H RCAP2L Table 11 Timer 2 Generated Commonly Used Baud Rates 48 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 C T2 0 A C T2 1 T2Pin________ Timer 2 Interrupt ET CAPTURE Transition Detector T2EX Pi rS o 6 CONTROL EXEN2 Figure 35 Timer 2 in Capture Mode E C T2 0 TL2 8 bit GA RCAP2L TH2 O 8 bit C T2 1 T2 Pi Timer 2 Interrupt RELOAD Transition Detector RCAP2H
66. er O and Timer 1 have four operating modes from which to select The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD These two Timer Counters have four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timers Counters Mode 3 is different The four operating modes are described in the following text 40 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 TMOD Address 89h 7 6 5 4 3 2 1 0 Not bit addressable TiGATE T1C T TiM1 TIMO TOGATE TOC T TOM1 TOMO Reset Source s Any source Reset Value 00000000B T1 TO Bits controling Timer1 TimerO GATE Gating control when set Timer Counter x is enabled only while INTx pin is high and TRx control pin is set when cleared Timer x is enabled whenever TRx control bit is set C T Gating Timer or Counter Selector cleared for Timer operation input from internal system clock Set for Counter operation input from Tx input pin M1 MO OPERATING 0 0 8048 Timer TLx serves as 5 bit prescaler 0 1 16 bit Timer Counter THx and TLx are cascaded there is no prescaler 0 8 bit auto reload Timer Counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer 0 TLO is an 8 bit Timer Counter controlled by the sta
67. es in RCAP2L and RCAP2H are preset by software means 44 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 If EXEN2 1 then a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 is 1 In Figure 37 DCEN 1 Timer 2 is enabled to count up or down This mode allows pin T2EX to control the direction of count When a logic 1 is applied at pin T2EX Timer 2 will count up Timer 2 will overflow at OFFFFH and set the TF2 flag which can then generate an interrupt if the interrupt is enabled This timer overflow also causes the 16 bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2 When a logic 0 is applied at pin T2EX this causes Timer 2 to count down The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H Timer 2 underflow sets the TF2 flag and causes OFFFFH to be reloaded into the timer registers TL2 and TH2 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed 6 5 3 PROGRAMMABLE CLOCK OUT A 50 duty cycle clock can be programmed to come out on P1 0 This pin besides being a regular I O pin has two additional functions lt can be programmed 1 To input the external clo
68. exceeding 64 KB and thus having EAM 1 and if an old 51 bus interface has to be preserved instead of using MOVX Ri A the instruction EMOV PRi A should be used If we load the content of P2 sfr to R3 and R2 execution of instruction EMOV PRO A will have exactly the same output in a system with EAM 1 as it is in case of MOVX QRO A in a design with standard 51bus interface Some 51MX applications may use extended addressing and rely on software setting the EAM bit in MXCON i e the non volatile address configuration bit is not programmed If such an application is set up such that the first code executed upon reset is off chip then the instruction that sets the EAM bit in MXCON must be located at or below address OOFBh This is to prevent the external bus from supplying a 16 bit address when a 23 bit address is required If the Program Counter were to reach address 0100h while EAM 0 the apparent address to external hardware that is expecting a 23 bit address would become 01 0100 28 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 _ instruction V E g _ instruction A low data in data in address Figure 19 Example of External Code Memory Read Cycles using 23 Address Bits The standard control signals and their functions for the external bus are as follows Signal name Function ALE Address Latch Enable This signal directs an external address latch to store
69. fer Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO_n When the first character is written the transmit interrupt is generated immediately after the SnBUF is written SnSTAT 3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame It is also set with BR n if a break is detected Cleared by software SnSTAT 2 BR n Break Detect flag is set if a character is received with all bits including STOP bit being logic 0 Thus it gives a Start of Break Detect on bit 8 for Mode 1 and bit 9 for Modes 2 and 3 The break detect feature operates indpendently of the UARTs and provides the START of Break Detect status bit that a user program may poll Cleared by software SnSTAT 1 OE n Overrun Error flag is set if a new character is received in the receiver buffer while it is still full i e when bit 8 of a new byte is received while RI in SnCON is still set If an overrun occurs SnBUF retains the old data and the new character received is lost Cleared by software SnSTAT O STINT_n Status Interrupt Enable 0 FEn BR n OE_n cannot cause any interrupt 1 FE n BR n OE ncan cause interrupt The interrupt used is shared with RI n CIDIS_n 1 or combined TI n RI n CIDIS n 0 Figure 44 Serial Port Status Register SnSTAT 6 6 9 MORE ABOUT UART MODE 1 Reception is initiated by a detected 1 to 0 transi
70. g PR1 and PR2 Figure 17 Mapping of other Addressing Modes to Universal Pointer Addressing 18 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Example Instruction Universal EMOV WPRO 1 A Memory Map Location 12 C340h 12 C341h 12 C341h Accumulator Figure 18 Memory Access using Universal Pointer Addressing Universal Pointers are designed primarily to facilitate addressing in Extended Addressing Mode with the EAM bit in MXCON set to one However Universal Pointers may still be used when EAM 0 In this case Universal Pointer addressing can access only the bottom 64 KB of the Code space the 64 KB XDATA space and the 64 KB EDATA space The Universal Pointer values that point to these areas do not change When EAM 0 Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex 19 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 3 51MX INSTRUCTIONS The 51MX instruction set is a a true binary level superset of the classic 80C51 designed to be fully compatible with previously written 80C51 code The changes to the instruction set are all related to the expanded address space Some details of existing instructions have been altered and some instructions have had an extended mode added In the latter case the alternate mode of the ins
71. hanges external memory bus interface and prevents core from executing code above the 64 KB boundary The encoding of the configuration bit is such that an unprogrammed device is configured for 16 address lines When the full 23 bit address is multiplexed on Port 2 when the EAM bit in MXCON 1 the high order address information bits A22 through A16 must be latched externally in the same manner as the low order bits A7 through AO on Port 0 The middle address bits A15 through A8 appear on Port 2 after ALE goes low If extended addressing is not enabled Port 2 behaves just as on a classic 80C51 An example of Port 2 address multiplexing is shown in Figure 19 There are two special cases for Port 2 multiplexing when extended addressing is enabled MOVX Ri and MOVX DPTR These instructions do not supply a source for a full 23 bit external address Where program memory is involved jumps and MOVC any missing address bits are supplied by the Program Counter see Table 1 For MOVX the additional bits are forced to zeroes to complete the address So MOVX Ri will output a 23 bit address composed of seven zeroes for the upper address Port 2 SFR contents for the middle byte of the address and Ri contents for the bottom byte Similarly MOVX DPTR will output a 23 bit address composed of seven zeroes for the upper address and the current DPTR contents for the middle and bottom bytes of the address If we have a single chip application with code
72. hout notice in the products including circuits stan dardcells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors 811 East Arques Avenue P O Box 3409 Sunnyvale California 94088 3409 Telephone 800 234 7381 1 H e Copyright Philips Electronics North America Corporation 2002 All rights reserved Printed in U S A Date of preliminary release 06 02 76 Preliminary 2002 June 28 PH ups I
73. imer value MOV CCAP4H CH SETB EA Re enable interrupts RET 74 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Module 4 can be configured in either compare mode and the WDTE bit in CMOD must also be set The user s software then must periodically change CCAP4H CCAP4L to keep a match from occurring with the PCA timer CH CL This code is given in the WATCHDOG routine shown above This routine should not be part of an interrupt service routine because if the program counter goes astray and gets stuck in an infinite loop interrupts will still be serviced and the watchdog will keep getting reset Thus the purpose of the watchdog would be defeated Instead call this subroutine from the main program within 2 18 count of the PCA timer 75 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such appli cations do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes wit
74. ing in a reduced supply current This bit should be set ONLY for applications that operate at a Vcc less than 3 6 V If LPEP 1 with Voc greater than 3 6 V readings from internal RAM will be invalid and the part itself can be damaged 6 4 TIMERS COUNTERS 0 AND 1 The two 16 bit Timer Counter registers Timer O and Timer 1 can be configured to operate either as timers or event counters see Figure 27 In the Timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 6 oscillator periods the count rate is 1 6 of the oscillator frequency In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register in the machine cycle following the one in which the transition was detected Since it takes 2 machine cycles 12 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full cycle In addition to the Timer or Counter selection Tim
75. ion of the 51MX stack is identical to the classic 80C51 stack implementation When interrupt or subroutine addresses are pushed onto the stack only the lower 16 bits of the Program Counter are stored This default 80C51 mode stack operation is shown in Figure 4 7 Preliminary 2002 June 28 Philips Semiconductors Extended Address Range Microcontroller This figure applies to the ACALL and LCALL instructions in all modes In 80C51 stack mode it also applies to interrupt processing PCH PC 15 8 PCL PC 7 0 P87C51Mx2 User Manual P87C51Mx2 0083h 0082h 0081h Final SP Value after ACALL 0080h LCALL or Interrupt 007Fh lt Initial SP Value before ACALL LCALL or interrupt Figure 4 Return Address Storage on the Stack 80C51 Mode There are two configuration options for the stack For purposes of backward compatibility with the classic 80C51 both alternate modes are disabled by a chip reset The first option Extended Interrupt Frame Mode causes interrupts to push the entire 23 bit Program Counter onto the stack as three bytes and the RETI instruction to pop all 23 bits as a return address as shown in Figure 5 The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a 1 to be consistent with Universal Pointer addressing Storing the full 23 bit Program Counter value is a requirement for systems that include more than 64 KB of program
76. l Dis backs E ensued I aeui GRE NOE RIS IK 28 4 1 Multiplexed External BUS ca il 28 5 Interrupt Processi cido canino aca Sian Acacia lactancia 30 6 P87C51Mx2 Ports Power Control and Peripherals ooooooomsss aeta 34 6 1 Special Euneion Regl Sters seo tvi eI m Bt M cui tet md cd ed 34 Qu PSC TIN RU ee fits A tede DL aC ta 37 6 2 1 Potts 0 1 59 EE 37 6 2 2 Port 37 6 3 PRTCSTMX2 Low Power Modes iii de E ueber ii 38 6 3 1 SOP Clock MOE Ee 38 6 327 Wile Mode dos 38 6 3 3 POWer 0 E 38 6 3 4 Power On Flag uva cota 40 6 3 5 DEI Consideration e dee 40 6 3 6 ONCE MOE is 40 6 3 7 Low Power Eprom Operation LPEP a 40 Gab Timers Cou nters 0 nd eiae esax rios 40 6 4 1 Mod sortsen cates sien ed Sc tudo ado 41 642 Mode Rc giaa 41 1 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 ou e 4 DS BN Fa EE 42 6 5 dree E II M 44 6 5 1 Capture Moderada 44 6 5 2 Auto Reload Mode Up or Down Counter eese 44 6 5 3 Programmable Clock Ult A 45 6 5 4 Baud Rate Generator Mode For UART 0 Serial Port 0 47 6 5 5 Summary Of Baud Rate BquatiOnis a 48 6 5 6 Tim r Counter2 35 6C Up osos ttd dp sion ui ma abc a a R ut D pus 48 XU c as ei 51 6 6 1 Mode 0 c 51 6 6 2 O eeh 51 6 6 3 Mode Zas 51 6 04 Nee 51 6 6 5 SER and Extended SER Spaces tetti e
77. lectable double buffering and several interrupt options The two UARTS are called UARTs 0 and 1 to correspond to the serial port assignments Each serial port can be operated in 4 modes 6 6 1 MODE 0 Serial data enters and exits through RxD_n TxD_n outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1 6 of the CPU clock frequency 6 6 2 MODE 1 10 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8_0 RB8_1 in Special Function Register SOCON S1CON For UART 0 the baud rate is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection The Baud Rate Generator is the only source for baud rate for UART 1 6 6 3 MODE 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SOCON S1CON while the stop bit is ignored For UART 0 the baud rate is programmable to either 1 16 or 1 32 of the CPU clock freq
78. ly variable using the module s capture register CCAPnL When the value of the PCA CL SFR is less than the value in the module s CCAPnL SFR the output will be low when it is equal to or greater than the output will be high When CL overflows from FF to 00 CCAPnL is reloaded with the value in CCAPnH this allows updating the PWM without glitches The PWM and ECOM bits in the module s CCAPMn reg ister must be set to enable the PWM mode 6 9 5 PCA WATCHDOG TIMER An on board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count Watchdog timers are useful for systems that are susceptible to noise power glitches or electrostatic discharge Module 4 is the only PCA module that can be programmed as a watchdog However this module can still be used for other modes if the watchdog is not needed Figure 58 shows a diagram of how the watchdog works The user pre loads a 16 bit value in the compare registers Just like the other compare modes this 16 bit value is compared to the PCA timer value If a match is allowed to occur an internal reset will be generated This will not cause the RST pin to be driven high 73 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 WRITE TO RESET CIDL WDTE CPS1 CPSO ECF me CCAP4L L WRITE O CCAP4H CCAP4H FEH CCAP4L EEH MODULE 4 l 0 MATCH INTERNAL 16 BIT COMPARATO
79. ndard Timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter 1 stopped Figure 27 Timer Counter Mode Control Register TMOD 6 4 1 MODE 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 29 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either GATE 0 or INTn 1 Setting GATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Figure 28 The GATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer O and Timer 1 see Figure 29 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 6 4 2 MODE 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 30 6 4 3 MODE 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 31 Overflow from TLn not
80. ntinued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value imer2 Control Register Timer2 Mode Control Timer O High Timer 1 High Timer 2 High Timer O Low Timer 1 Low Timer 2 Low Watchdog Timer Reset Notes SFRs are bit addressable SFRs are modified from or added to the 80C51 SFRs Extended SFRs accessed by preceeding the instruction with MX escape opcode A5h Reserved bits must be written with 0 s amp Power on reset is 10H Other reset is OOH 96 The unimplemented bits labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown for these bits are Oe although they are unknown when read 96 The unimplemented bits labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown for these bits are Oe although they are unknown when read 6 2 P87C51MX2 PORTS 6 2 1 PORTS 0 1 2 3 Ports 0 1 2 3 are the same as the ports in a conventional 80C51 device They are located at the same bit addressable locations of 80H 90H AOH and BOH in the conventional SFR space 6 2 2 PORT 4 The P87C51Mx2 has an additional port called Port 4 This port is currently not available as general purpose l O
81. odule enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module PWM CCAPMn 1 enables the pulse width modulation mode The TOG bit CCAPMn 2 when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module s capture compare register The match bit MAT CCAPMn 3 when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module s capture compare register The next two bits CAPN CCAPMn 4 and CAPP CCAPMn 5 determine the edge that a capture input will be active on The CAPN bit enables the negative edge and the CAPP bit enables the positive edge If both bits are set both edges will be enabled and a capture will occur for either transition The last bit in the register ECOM CCAPMn 6 when set enables the comparator function There are two additional registers associated with each of the PCA modules They are CCAPnH and CCAPnL and these are the registers that store the 16 bit count when a capture occurs or a compare should occur When a module is used in the PWM mode these registers are used to control the duty cycle of the output 69 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 PCA TIMER COUNTER MODULEO CF CR CCF4 CCF3 CCF2 CCFI CCFO CCON D8h loo
82. of code memory and executes in two machine cycles Indirect addressing further requires setup of the pointer register etc These registers are banked There are four groups of registers any one of which may be selected to represent RO through R7 at any particular time This feature may be used to minimize the time required for context switching during an interrupt service or a subroutine or to provide more register space for complicated algorithms The registers are no different from other internal data memory locations except that they can be addressed in shorthand notation as RO R1 etc Instructions addressing the internal data memory by other means such as direct or indirect addressing are quite capable of accessing the same physical locations as the registers in any of the four banks 6 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 2 2 2 BIT ADDRESSABLE RAM Internal data memory locations 20 hex through 2F hex may be accessed as both bytes and bits This allows a convenient and efficient way to manipulate individual flag bits without using much memory space The bottom bit of the byte at address 20h is bit number 00h the next bit in the same byte is bit number 01h etc The final bit bit 7 of the byte at address 2Fh is bit number 7Fh 127 decimal Bit numbers above this refer to bits in Special Function Registers This code SETB 20h 1 CPL 20h 2
83. of the Universal Pointers by a value from 1 to 4 This allows the pointer to be advanced past the last data element accessed to the next data element 16 Preliminary 2002 June 28 P87C51Mx2 User Manual P87C51Mx2 Philips Semiconductors Extended Address Range Microcontroller Addressing Modes Memory Space Up to 8 MB on Chip and or off Chip program memory Up to 64 KB 256 bytes on chip and or off chip data accessed as Stack and via Universal Pointer only Upper 128 bytes on chip indirectly addressed RAM Lower 128 bytes on chip directly amp indirectly addressed RAM Up to 8 MB 128 KB data accessed via MOVX generally off chip data Up to 64 KB on chip and or off chip data accessed via MOVX 7F 0100h 7F 00FFh 7F 0080h 7F 007Fh 7F 0000h 7E FFFFh Figure 16 Universal Memory Map 17 PC PC relative addressing DPTR lower 64 KB of Code EPTR Universal Pointers PRO PR1 Stack SPE SP Universal Pointers PRO PR1 RO R1 Stack SPE SP Universal Pointers PRO PR1 Direct addressing RO R1 indirect Stack SPE SP Universal Pointers PRO PR1 RO R1 lower 256 bytes on chip lower 64 KB off chip via use of P2 DPTR XDATA access only EPTR HDATA access Universal Pointers PRO PR1 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 meza E Standard Memory Map 24 bit Addressing usin
84. or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave O SADDR 1100 0000 SADEN 1111 1101 Given 21100 00X0 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 21100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires aO in bit O and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit O 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 62 Preliminary 2002 June 28 Philips Semiconductors
85. ory addressing modes are shown in figures 12 through 14 Following a reset the 51MX begins code execution like a classic 80C51 at address 00 0000h Similarly the interrupt vectors are placed just above the reset address starting at address 00 0003h It is important to note that first instruction located at address 0 should not be an EJMP instruction EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt O vector address Example Instruction MOVC A A PC Accumulator Location 3E 97FFh 3E 98D2h 3E 98D2h Accumulator Figure 12 Code Memory Access using Indexed Indirect Addressing with the Program Counter 14 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 Example Instruction MOVC A A DPTR executed at address 01 59B3 Accumulator Upper 7 bits of Program Counter 01h Data Pointers Location 0 C340h 01 FFAEh Accumulator 1 FFOCh 01 FFAEh Figure 13 Code Memory Access using Indexed Indirect Addressing with DPTR Example Instruction MOVC A A EPTR Accumulator Location 12 B109h 12 B1D6h 12 B1D6h Accumulator Figure 14 Code Memory Access using Indexed Indirect Addressing with EPTR 2 7 UNIVERSAL POINTERS A new addressing mode called Universal Pointer mode has been added to the 51MX specifically for the purpose of greatly enhancing C language code density and performance
86. r on or a warm start after powerdown 6 3 5 DESIGN CONSIDERATION When the idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycles before the internal reset algorithm takes control On chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by reset the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory 6 3 6 ONCE MODE The ONCE On Circuit Emulation Mode facilitates testing and debugging of systems without the device having to be removed from the circuit The ONCE Mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE Mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored when a normal reset is applied 6 3 7 LOW POWER EPROM OPERATION LPEP Microcontroller contains some analog circuits that are not required when V g is less than 3 6 V but are required for a Vcc greater than 3 6 V The LPEP bit AUXR 4 when set will powerdown these analog circuits result
87. ritten to the WDCON register will not be immediately available to be read until after a successful feed sequence Any read before a feed sequence will fetch the old value 6 7 6 SOFTWARE RESET VIA WATCHDOG TIMER FEED SEQUENCE The following instructions will result in a software reset via the watchdog timer reset even if one or more interrupts occur during those instructions MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0AAh Any pattern other than 1Eh or Eth not necessarily AAh will perform a WDT reset 66 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 This software reset will be performing the same function as a WDT reset where a reset pulse will also be generated to reset external circuitries 6 8 ADDITIONAL FEATURES AUXR Address 8EH 7 6 5 4 3 2 1 0 Not bit addressable EXTRAM AO Reset Value 00h BIT SYMBOL FUNCTION AUXR 7 2 Reserved for future use Should be set to 0 by user programs AUXR 1 EXTRAM Internal External RAM access using MOVX Ri DPTR When 0 internal XRAM access is selected When 1 external data memory is selected Refer to 51MX Architecture Reference AUXR 0 AO Disable Enable ALE When 0 ALE is emitted at a constant rate of 1 3 the oscillator frequency When 1 ALE is active only during a MOVX or MOVC instruction that is targeting Figure 51 AUXR Regis
88. rmined by the BRGCON extended SFR divided by two When 1 the baud rate for UART is the input rate T1 timer or baud rate generator PCON 6 SMODO Framing Error Location When 0 bit 7 of SCON functions as SMO for the UART When 1 bit 7 of SCON is the framing error status for the UART This bit also determines the location of the UART reception interrupt RI occurs see description on RI in Figure 43 PCON 5 Reserved for future use Should be set to 0 by user programs PCON 4 POF Power On Flag Reset value 1 for power on reset only PCON 3 GF1 General purpose flag 1 May be read or written by user software but has no effect on operation PCON 2 GFO General purpose flag 0 May be read or written by user software but has no effect on operation PCON 1 PD Power Down control bit Setting this bit activates Power Down mode operation Cleared when the Power Down mode is terminated see text PCON 0 IDL Idle mode control bit Setting this bit activates Idle mode operation Cleared when the Idle mode is terminated see text Figure 26 Power Control Register PCON 39 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 3 4 POWER ON FLAG The Power On Flag POF is set by on chip circuitry when the Vpp level on the P87C51Mx2 rises from OV The POF bit has to be cleared by software allowing a user to determine if the reset is the result of a powe
89. s some control bits DBMOD_n n 0 1 The enhanced UART includes double buffering In order to be compatible with existing 80C51 devices this bit is reset to 0 to disable double buffering INTLO_n For modes 1 2 and 3 the UART allows Tx interrupt to occur at the beginning or end of the STOP bit This bit is reset to 0 to select Tx to be issued at the beginning of the STOP bit Note that in the case of single buffering if Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit For UART mode 0 this bit must be cleared to 0 CIDIS_n n 0 1 The UART can issue combined Tx Rx interrupt conventional 80C51 UART or have separate Tx and Rx interrupts This bit is reset to 0 to select combined interrupt DBISEL n n 0 1 This is only used when the corresponding DBMOD n 1 If DBMOD n 0 this bit must be cleared to 0 for future compatibility This bit controls the number of interrupts that can occur when double buffering is enabled If 0 the number of Tx interrupts must be the same as the number of characters sent If 1 an additional interrupt is sent at the beginning INTLO n 0 or the end INTLO n 1 of the STOP bit when there is no more data in the double buffer This last interrupt can be used to indicate that all transmit operations are over STINT n n 0 1 If 1 FE n BR_n and OE ncan cause interrupt refer to Figure 44 The bits DBMOD n and DBISEL n are discussed further in
90. sable Reset Value 00h BIT SYMBOL FUNCTION CCAPMn 7 Reserved for future use Should be set to O by user programs CCAPMn 6 ECOMn Enable Comparator ECOMn 1 enables the comparator function CCAPMn 5 CAPPn Capture Positive CAPPn 1 enables positive edge capture CCAPMn 4 CAPNn Capture Negative CAPNn 1 enables negative edge capture CCAPMn 3 MATn Match When MATn 1 a match of the PCA counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt CCAPMn 2 TOGn Toggle When TOGn 1 a match of the PCA counter with this module s compare capture register causes the CEXn pin to toggle CCAPMn 1 PWMn Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to be used as a pulse width modulated output CCAPMn 0 ECCFn Enable CCF Interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt Figure 57 CCAPMn PCA Modules Compare Capture Registers Eau cAPPn cams Mata Toen Pwmn ECCRn Module Function re fof oy of oo 0 NoOperaion T 4 x 16 bit capture by a positive edge trigger on CEXn x 4 x 16 bit capture by a negative edge trigger on CEXn T 4 16 bit capture by any transistion on CEXn LARA REM eme EE Ae 7 pax ICI CI T CTA Table 16 PCA Module Modes CCAPMn Register a II REE ERES ETE E 6 9 1 PCA CAPTURE MODE To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and
91. since an interrupt could occur at any point in the program The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruction only while other calls and returns are not affected Special extended call and return instructions allow large programs to traverse the entire code space with full 23 bit return addresses The Extended Interrupt Frame Mode is enabled by setting the EIFM bit in the MXCON register This figure applies to interrupt services in Extended Interrupt Frame Mode as well as the ECALL instruction in all modes The upper bit of the byte containing PCE is forced to a 1 in order to be consistent with Universal Pointers PCE PC 22 16 PCH PC 15 8 PCL PC 7 0 0083h 0082h 8 Final SP Value after 0081h 0080h ECALL or interrupt 007Fh 48 Initial SP Value before ECALL or interrupt Figure 5 Extended Return Address Storage on the Stack Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The second stack option Extended Stack Memory Mode allows for stack extension beyond the 256 byte limit of the classic 80C51 family Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory Stack extension has no effect on the data that is stored on the stack
92. software to feed the timer prior to the timer reaching its terminal count For the P87C51Mx2 the watchdog timer is compatible with the watchdog timer in 89C51Rx2 In addition it has a prescaler of up to 1024 times default without prescaling that support longer watchdog timeout The WDT consists of a 14 bit counter and Watchdog Timer Reset WDTRST SFR The prescaler is determined by the watchdog control WDCON SFR in the MX extended SFR space 6 7 1 WATCHDOG FUNCTION The time interval of the watchdog timer can be calculated as timeoutperiod 16383 x prescalefactor x 6 fosc In other words after a feed sequence the watchdog timer time out will occur after 16383 x prescalefactor machine cycles and will cause a watchdog reset unless the next feed sequence occurs before the time out 6 7 2 FEED SEQUENCE WDT is disabled after reset of the microcontroller To enable the WDT user must write 01EH and OE1H in sequence to the WDTRST register Once the WDT is enabled user must feed the watchdog in by writing 01EH and OE1H to WDTRST before a WDT timeout to avoid WDT overflow When WDT overflows it will drive an reset HIGH pulse at the RST pin After WDT is enabled it cannot be disabled unless reset The following code is recommended for a feed sequence CLR EA Disable all interrupts avoid interrupt in between two parts of feed sequence 63 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address
93. t external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt The capture mode is illustrated in Figure 35 There is no reload value for TL2 and TH2 in this mode Even when a capture event occurs from T2EX the counter keeps on counting T2EX pin transitions or osc 6 pulses 6 5 2 AUTO RELOAD MODE UP OR DOWN COUNTER In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter via C T2 in T2CON then programmed to count up or down The counting direction is determined by bit DCEN Down Counter Enable which is located in the T2MOD register see Figure 34 When reset is applied DCEN 0 and Timer 2 will default to counting up If the DCEN bit is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 36 shows Timer 2 counting up automatically DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The valu
94. t neta eege ee IEEE DE 51 6 6 6 Baud Rate Generator and Selection cnn cccnnn nc cnnaccnnnnos 52 6 6 7 Framing De EE 55 6 6 8 EE odios O 56 6 6 9 More About UART Mode Loto ca 57 6 6 10 More About UART Modes 2 and 3 Aender edd anette 58 DES Double Business 60 6 6 12 Multiprocessor Communications nono eene 62 6 6 13 Automatic Address Recogmton ENEE 62 GI WeatC dos KE 63 6 7 1 Watchdog PUC A A ee A E deum gt 63 6 1 2 Feed RE 63 6 7 3 WDT Control ad 66 6 14 WatchDog Reset Wii is 66 6 7 5 Reading from the WDCON SER eiie eter eerte t og Poe tono p ekz ve ne e Ye ao 66 6 7 6 Software Reset Via WatchDog Timer Feed Sequence esses 66 6 8 Additional E 67 6 8 1 Expanded Data RAM Adres Sime s epi o ERE b Pv eei udin uk Rp a 67 65 2 Dual Data EIER g eegente E 68 6 9 Programmable Counter Array PCA kee 68 6 9 1 PEA Capture Mode eode vitet toe oia T2 6 9 2 16 bit Software Timer Mode en trot hb v UM E i P BEER EE 73 6 9 3 Fhehospeed Output Moden xou tuteltetuado tu to 73 6 9 4 Pulse Width Modulator IV he ce Geer he ova Hue Maa e spacaseoasesaesceass 13 6 9 5 PCA Watchdog Timer iii tii 13 2 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 1 INTRODUCTION 1 1 THE 51MX CPU CORE Philips Semiconductor s 51 MX Memory eXtension core is based on an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices The
95. ter 6 8 1 EXPANDED DATA RAM ADDRESSING The P87C51Mx2 has expanded data RAM addressing capability Details of the data memory structure are explained in 51 MX Architecture Reference The device has on chip data memory that is mapped into the following segments Address 0000H 007FH are directly and indirectly addressable DATA memory Address 0080H 00FFH are indirectly addressable as RAM IDATA memory Note When 000080H 0000FFH is directly addressed SFRs will be accessed Address 0100H 04FFH for MB2 MC2 are extended indirectly addressable RAM part of EDATA memory There are also 768 bytes of XDATA memory locations 000000H 0002FFH for MB2 and 1 792 bytes of XDATA memory locations 000000H 0006FFH for MC2 If EXTRAM 0 this internal XDATA memory location is selected in a MOVX instruction to from locations 000000H 0002FFH for MB2 or 000000H 0006FFH for MC2 and external memory will be accessed above these locations If EXTRAM 1 the internal XDATA RAM will not be used all MOVX instructions will access external data memory 67 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 AUXR1 Address A2h 7 6 5 4 3 2 1 0 Not bit addressable LPEP GF2 0 DPS Reset Value 00h BIT SYMBOL FUNCTION AUXR1 7 5 Reserved for future use Should be set to O by user programs AUXR1 4 LPEP LPEP can be set to one for
96. tes of on chip XDATA memory space HDATA High Data This is a superset of XDATA and may include up to 8 323 072 bytes 8 MB 64 KB of memory space addressed via the MOVX instruction using the EPTR DPTR RO or R1 Non XDATA portion of HDATA is placed in external devices CODE Up to 8 MB of Code memory accessed as part of program execution and via the MOVC instruction All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV instruction This feature is detailed in a subsequent section 2 2 DATA MEMORY DATA IDATA AND EDATA The standard 80C51 internal data memory consists of 256 bytes of DATA IDATA RAM and is always entirely on chip In this space are the data registers RO through R7 the default stack a bit addressable RAM area and general purpose data RAM On the top of the DATA IDATA memory space is a 1 KB block of RAM that can be accessed as stack or via indirect addressing Alltogether this forms EDATA RAM of 1280 bytes The different portions of the data memory are accessed in different manners as described in the following sections 2 2 1 REGISTERS RO R7 General purpose registers RO through R7 allow quick efficient access to a small number of internal data memory locations For example the instruction MOV A RO uses one byte of code and executes in one machine cycle Using direct addressing to accomplish the same result as in MOV A 10h requires two bytes
97. th data bit that was received In Mode 1 it SM2_n 0 RB8 n is the stop bit that was received In Mode 0 RB8 n is undefined Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the the stop bit see description of INTLO bit in SnSTAT register in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO 0 itis set near the middle of the 9th data bit bit 8 if SMODO 1 itis set nearly the middle of the stop bit See SM2 n for exceptions Must be cleared by software Figure 43 Serial Port Control Register SnCON 6 6 7 FRAMING ERROR Framing error FE n is reported in the status register SnSTAT In addition if SMODO PCON 6 is 1 framing errors for UARTs 0 and 1 can be made available to the SOCON 7 and S1CON 7 respectively If SMODO is 0 SOCON 7 and S1CON 7 are SMO for UARTS 0 and 1 respectively It is recommended that SMO n and SM1_n SnCON 7 6 are set up before SMODO is set to 1 It should also be noted that a break detect setting of BR n also sets FE n 55 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 6 6 8 STATUS REGISTER Each of the enhanced UARTS contains a status register The status register also contain
98. the multiplexed portion of the address for the next bus operation This may be either a data address or a code address PSEN Program Store Enable Indicates that the processor is reading code from the bus Typically connected to the Output Enable pin of external EPROMs or other memory devices External bus addresses for code memory may range from 00 0000 through 7F FFFF In the Universal Memory Map these correspond to addresses 80 0000 through FF FFFF RD Read The external data read strobe Typically connected to the RD pin of external peripheral devices WR Write The write strobe for external data Typically connected to the WR pin of external peripheral devices External bus addresses for data memory may range from 00 0000 through 7E FFFF which matches Universal Memory Map addresses If on chip XDATA is enabled it will cause an addressing discontinuity in the external data address space The DATA and IDATA spaces are always on chip and therefore always create such an addressing discontinuity 29 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 5 INTERRUPT PROCESSING The P87C51Mx2 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P87C51Mx2 has ten interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IENO or I
99. tion at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed 57 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 The signal to load SBUF and RB8 RB8_0 for UART 0 or RB8_1 for UART 1 and to set RI RI 0 for UART 0 or RI_1 for UART 1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 SM2_0 for UART 0 or SM2_1 for UART 1 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into R
100. tly wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 6 9 PROGRAMMABLE COUNTER ARRAY PCA The Programmable Counter Array available on the P87C51Mx2 is compatible with 89C51Rx2 The PCA includes a special 16 bit Timer that has five 16 bit capture compare modules associated with it Each of the modules can be programmed to operate in one of four modes rising and or falling edge capture software timer high speed output or pulse width modulator Each module has a pin associated with it in port 1 Module 0 is connected to P1 3 CEX0 module 1 to P1 4 CEX1 etc The PCA timer is acommon time base for all five modules and can be programmed to run at 1 6 the oscillator frequency 1 2 the oscillator frequency the Timer 0 overflow or the input on the ECI pin P1 2 The timer count source is determined from the CPS1 and CPSO bits in the CMOD SFR see Figure 55 68 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 HL 16BITS MODULEO P1 3 CEXO MODULEI P1 4 CEX1 L 16BITS J PCA TIMER COUNTER MODULE2 P1 5 CEX2 TIME BASE FOR PCA MODULES MODULE3 bi P1 6 CEX3 MODULE FUNCTIONS 16 BIT CAPTURE 16 BIT TIMER MODULE4 PL7 CEX4 16 BIT HIGH SPEED OUTPUT 8 BIT PWM
101. truction is activated by preceding the instruction with a special one byte prefix code A5h An important goal in the implementation of the 51 MX was to keep the same timing relationship of existing 80C51 instructions to existing devices Any 80C51 instruction executed on the 51 MX will take the same number of machine cycles to execute 80C51 Instruction Effect of Extended Addressing Includes SJMP and all conditional branches These instructions may cross a 64 KB boundary if they are located within branch range of the boundary ACALL addrii This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence AJMP addri1 is across the boundary The lower 16 bits of the Program Counter are replaced with the value formed by the sum of the JMP A DPTR Accumulator and the active DPTR This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary The address formed by replacing the lower 16 bits of the Program Counter with the value formed MOVC A A DPTR by the sum of the Accumulator and the active DPTR is used to access code memory The PC value used is that of the instruction following MOVC MOVC A A PC The sum of the Accumulator and the 23 bit Program Counter forms the 23 bit address used to read the code memor
102. uency as determined by the SMOD1 bit in PCON For UART 1 the baud rate is from the Baud Rate Generator 6 6 4 MODE 3 11 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate For UART 0 the baud rate in Mode 3 is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection Baud Rate Generator is the only source for baud rate for UART 1 In all four modes transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register Reception is initiated in Mode O by the condition RI_0 RI_1 0 and REN O REN 1 1 Reception is initiated in the other modes by the incoming start bit if REN O REN 1 1 6 6 5 SFR AND EXTENDED SFR SPACES The regular UART 0 SFRs and control bits are in the regular SFR space However extended control and UART 1 registers are in the MX extended SFR space 51 Preliminary 2002 June 28 Philips Semiconductors P87C51Mx2 User Manual Extended Address Range Microcontroller P87C51Mx2 MN CS 9 BL wow mens 98 eeleren TO sw COEN AN EC A EEC 9 MES E TO MECO EII TO MEA CET TO EEC 0 8 EE TO sister warme A
103. voked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The Power Down mode stops the oscillator in order to absolutely minimize power consumption Power Down mode is entered by setting the PD bit in the PCON register The processor can be made to exit Power Down mode via Reset or one of the external interrupt inputs INTO INT1 configured to be level sensitive only This will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress While having the MX part in Power Down Mode and driving Reset high or external interrupt line low the oscillator dedicated analog subsystem inside of microcontroller will be enabled However only when the wake up pulse on reset external interrupt line is ended the rest of microcontroller will be supplied with the system clock and continue to operate The duration of an input pulse on reset external interrupt pin in order to wake the part from Power Down Mode depends solely on external oscillator s circuit components At the end of wake up procedure reset external interrupt line can be brought to non active level as soon as input at XTAL1 pin achieves stable frequency duty cycle and amplitude If an external interrupt caused the part to wake up execution of forced jump that directs code execution to the proper interrupt service routine will end Power Down Mode By exiting Power Down mode
104. y The PC value used is that of the instruction following MOVC All relative branches MOVX DPTR A The active DPTR points to an address in the 64 KB XDATA memory MOVX A DPTR The active DPTR points to an address in the 64 KB XDATA memory Replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This RET instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary When the extended interrupt frame mode is not enabled this instruction replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This will cause a 64 KB boundary to RETI be crossed if the instruction is located such that the next instruction in sequence is across the boundary If the extended interrupt frame mode is enabled a 23 bit address is loaded into the PC from the stack LCALL addri6 Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary LJMP addri6 Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary Table 1 Instructions Affected by Extended Address Space 20 Preliminary 2002 June 28 Philips Semiconductors Extended Address Range Microcontroller 5

NXP 8xC51MA2, 8xC51MB2, 8xC51MB2/02, 8xC51MC2

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