SuperH 32-Bit RISC Microcontroller Family Shortform
Contents
1. On board programming modes Automatic bit rate adjustment Flash memory real time emulation by overlapping a part of RAM e Protect modes Table 3 SH 2 Series Microcontroller Overview 1 Part names differ for 5V and 3 3V devices for different package types and for different temperature ranges 2 When cache is used SH7060 Series Based on the SH DSP CPU core Hitachi is currently developing a new lineup of it s SH 2 embedded microcontrollers Members of this series will feature a high clock frequency FLASH memory 256kB FLMCR1 FLMCR2 EBR1 EBR2 RAMER 3 Typical 3 3V F 16 7 MHz temperature range 20 to 75 C 4 Typical 5V F 20 MHz temperature range 40 to 85 C 5 Preliminary data please contact your local Sales Office for availability ROM kByte Part name Product Name ROM type RAM kByte Cache kByte Internal address bus lt temaldatabus 32bi Frequency MHz integrated flash memory and other peripherals dedicated to specific markets The SH7060 series will offer an upgrade path from the SH7040 series Figure 24 SH7040 7050 Series Flash Memory Block Diagram FLASH memory control register 1 FLASH memory control register 2 Block specification register 1 Block specification register 2 RAM emulation register External Current Bus Width Consumptive mA Package SH7011 HD6417011Fxx SH7014 HD6417014R xx SH7016 HD6437016Fxx2. i Address 16 bit integrated timer pulse unit Data address Internal upper data bus 16 bits B Internal lower data bus 16 bits Figure 17 Functional Block Diagram of the SH7020 SH7030 series 1 see selection guide for details 2 only SH7030 series Table 2 SH 1 Series Microcontroller Overview 1 Part names differ for 5V and 3 3V devices for different package types and for different temperature ranges 2 Temperature range 20 to 75 C 3 Temperature below 50 C Product Name Part name 1 ROM ROM type RAM Frequency Typ Typ Sleep Typ Standby Package kByte kByte MHz MIPS Power Current Current mW 2 mA 2 uA 3 5V 3 3V 3 3V SH7020 HD6417020xx 1 20 12 5 215 30 0 01 100 TQFP HD6437020Sxx 16 Mask ROM SH7021 HD6477021xx 22 OTP HD6437021Sxx 32 Mask ROM SH7032 HD6417032xx 8 198 40 0 01 112 5 7034 HD6417034xx 4 120 TOFP HD6477034xx 64 OTP HD6437034Axx 64 Mask ROM SH Family Device Core Vcc V Max Clock MHz External Bus Width On chip ROM kByte Mask ROM Version ZTAT OTP Version On chip RAM kByte Interrupts Internal External DMA Controller channels Watch Dog Timer channel Serial Communication Interface UO Ports including input only Timing Pattern Controller Integrated Timer Unit Bus State Controller User Break Controller Clock Pulse Generator A D Converter bits x channels Data Book Package Part Name Devices SH 1 Family
3. 64 SH7017F HD64F7017Fxx 128 SH7040A HD6437042Axx 64 SH7041A HD6437041Axx SH7042A HD6437042Axx 128 HD6477042Axx SH7043A HD6437043Axx HD6477043Axx SH7044A HD6437044Axx 256 HD6477044Axx SH7044AF HD64F7044Axx SH7045A HD6437045Axx HD6477045Axx SH7045AF HD64F7045Axx 5V 4 1 3 1 28 7 MASK FLASH 2 1 4 2 28 33 MASK PROM MASK PROM MASK PROM FLASH 28 MASK PROM FLASH 3 3V 20 16 16 TQFP100 QFP 112 gun 32 QFP 144 16 QFP112 32 QFP144 16 QFP112 32 QFP144 Development Tools The development of applications based on the SH 2 family 1s supported by evaluation boards and emulators Hitachi provides the EVB7045F featuring a SH7045F device and the E6000 in circuit emulators The E6000 emulators feature Zero wait state real time emulation Emulation memory 256 PC breakpoints Complex Event System CES Up to 12 hardware breakpoints using the event and range channels in the CES Trace buffer acquisition filtering using the CES Execution time measurement e 4 user logic probes for triggering Events in the CES Automatic tracking of the target system power supply e Multiple target clock selection The development support comprises a C compiler and debugger A wide variety of third party tools and software are also available for the SH 2 series Application Examples The SH 2 family has been specifically designed for advanced 32 bit embedded control
4. Design Win Overview by Product Classification 22 20 18 16 14 7 199 1995 1998 1997 Figure 5 SuperH Shipments over the years HMSE provides our customers with locally designed and supported tools ranging from low cost evaluation boards to fully featured real time emulators based on IBM compatible PC s at a very competitive price Software ranges from Assembler an ANSI C Compiler via a C level debugger to MakeApp a tool that sets up peripherals and creates driver routines on the click of a mouse HMSE also offers support and engineering resources for customers wishing to use Hitachis ASIC capabilities This also applies to our uCBIC program enabling our customers to select one of Hitachi s CPU cores and combine it with peripherals from our library and adding customer specified logic via VHDL or Verilog In addition Hitachi is also establishing strategic partnerships with other key players in the embedded world to ensure the future success and evolution of the product lines in the growing embedded marketplace But after all we do not forget it is the customer who decides if a microprocessor line is successful More than 2000 design wins illustrate that the SuperH is the right choice for a huge variety of applications Hitachi 15 committed to further extend the product line to stay at the forefront of the business and technology of tomorrow Figure 7 Strategic Alliances for SuperH S
5. SuDerH RISC engine 32 bit microcontrollers and microprocessors System Solutions HITACHI SuperH RISC engine SH DSP Reader s Guide This document provides an overview of Hitachis 32 bit SuperH embedded microcontrollers and microprocessors This document includes 3 main sections The 1st covers general overviews and some background information The 2nd introduces the SuperH CPU architecture providing an overview of the most relevant technical details Finally section 3 provides in depth discussions of the individual SuperH series You will also find tables helping you to select the right SuperH device for your application We strongly recommend you read all sections before making your decision Welcome SuperH Architecture Evolution SuperH Family of 32 bit Microcontrollers and Microprocessors SuperH 32 bit Embedded Controllers SuperH 32 bit Embedded Processors SuperH Market View SuperH CPU Architecture Overview SH 1 Low cost Highly integrated 32 bit Embedded Controllers SuperH Family Devices SH 2 Advanced 32 bit Embedded Controllers SH 3 High performance Cost effective 32 bit Embedded Processors SH 4 The Next Wave of Embedded Computing 13 15 19 24 27 Welcome Creating the information society with all its new products and services 1s one of the biggest challenges of this decade As one of the major players 1n the global elect
6. and a cache memory block Multiply and accumulate MAC registers high and low MACH MACL Stores the results of multiply and Procedure register PR Stores a return address from a Program counter PC Indicates the fourth byte second instruction after the current instruction 0 0 0 Figure 20 SH 2 System Registers SH7040 el The SH7040 series offer different versions with a variety of different A D FLASH ROM PROM mask ROM RAM cache converters different on chip memory 256kbytes 4kbytes 1kbytes 128kbytes 64kbytes Interrupt break controller in common with on chip RAM 2 kbytes of on chip RAM are used for Serial communication address data array when cache is interface 2 channels sizes and types Throughout the SH7040 series you will find the following additional peripherals offering you system solution support and an overall Access BOE Bus state controller 1 Multifunction timer pulse unit x cost reduction for a wide range of o n o o P o Se 3 lt t o applications Cache memory 1 kbyte instruction cache and PC relative read data used enabled direct map method 256 entry cache tags 4 byte lines cache Power Ground can be disabled for full use of on chip Locum i RAM E Bus State Controller BSC memory mmm address space is divided into 5 areas 1 area
7. 256Kx16 EDO DRAM display memory interface standby mode PC Card Controller v2 1 compliant control of 2 slots simultaneously supports IC memory card I O and memory card interface external buffer control signals General Purpose I O GPIO 2 channel 16 bit Timer IrDA interface Standard 16550 compatible UART Interrupt Controller l Palette RAM LCD Controller Development Tools A complete set of development tools for the SH7709 is directly available from Hitachi Hitachi provides the EBX7709 development board as a hardware platform which 1s also available as Windows CE ready to go version The EBX7709 also supports the Hitachi Debugger Interface HDI An additional LCD kit is available which interfaces to the EBX7709 board drivers for Windows CE are available Other Operating System support for the SH7709 is being provided by Accelerated Technologies Nucleus Wind River Systems VxWorks and other Integrated Systems pSOSTM High level language C compilers are available from Hitachi Cygnus Gnu C and Greenhills The Visual C C Touch Screen 5 are TE vane 12 12 5 F PC104 ISA Bus wess 2 wire development and debug environment for Windows CE is available from Microsoft Derivatives The SH 3 family includes also some reduced versions such as the SH7708 device which has compared to the SH7709 less I O ports no DMAC a reduced INTC a single cha
8. 32 bit embedded control market Thus the SH 32 bit embedded controller line focuses on integrated memory integration of peripherals and cost optimised system design The members of the embedded controller line are available with up to 256 kBytes of integrated FLASH ROM and up to 10 kBytes of RAM Also PROM mask ROM and ROMless versions are available Figure 3 SuperH Microcontroller Family Tree SH1 Core 16x16 42 bit MAC 64k 4k ROM RAM ITU TPC DMAC x 4 A D SCI x 2 112 pin 20MIPS 5V 12 5MIPS 3 3V SH1 Core 16x16 42 bit MAC ROMless 8k RAM ITU TPC DMAC x 4 A D SCI x 2 INTEGRATION 112 pin 20MIPS 5V 12 5MIPS 3 3V 32 bit SH1 Core 16x16 42 bit MAC 128k 64k ROM TURIS RN 4k RAM or 1k 1k DMAC x 4 RAM Cache MTU CMT DMAC x 4 SCI x2 100 pin 20MIPS 5V 12 5MIPS 3 3V Cost plays the decisive role throughout the embedded controller line A set of peripherals integrated into the members of the series provides glueless connection to a huge variety of external devices or even makes external devices obsolete in many cases Several members of the SH 2 series have been designed for dedicated applications to even improve the performance and to reduce the system costs for special applications Figure 3 shows the various members of the SH 1 and SH 2 series The SH 2 series has been extended by SH7050F Embedded SH2 Core 32x32 64 bit MAC 256k 128k FLASH 10 6k
9. BSCP Multiplication operations 16x16 32 32x32 32 and multiplication accumulation operation 16x16 64 64 32x32 64 64 executed in 1 5 cycles 64 bit accumulator Peripheral address bus 2 16 bit peripheral data bus 2 29 bit physical address bus 1 32 bit data bus 1 29 bit physical address bus 2 32 bit data bus 2 Processing states program execution exception processing bus release reset sleep mode standby External bus interface Figure 27 SH7709 Functional Block Diagram SH7709 Peripherals The peripheral mix of the SH7709 includes out of the following modules e 8 kByte of mixed instruction data cache memory 128 entry 4 way associative TLB cache can be divided into 4 kByte 2 way cache plus 4 kByte RAM Memory Management Unit MMU supporting 4 Gbytes of address space 256 address spaces page unit sharing Interrupt Controller INTC with 7 external interrupt pins e 3 x Serial Communication Interfaces SCD 2 with 16 byte FIFO for transmit receive including IrDA 1 0 interface smart crad interface support User Break Controller UBC simplifying debugging of user programs Clock Pulse Generator CPG PLL supplying the LSI and external devices with clock pulses from a connected crystal resonator or an external clock a PLL provides clock multiplication Real Time Clock RTC with calendar and alarm functions on chip 32 kHz crystal oscillator 3 channel
10. Infinite Impulse Response Filters FIR IIR or the Fast Fourier Transform FFT Based on such basic algorithms DSP processors are for example especially useful for modem algorithms and audio or image processing software The classical approach using a microcontroller and a dedicated DSP processor leads to complex systems with very often 2 operating systems and several heterogeneous bus systems which often make system design and debugging very difficult Within the SuperH family a new and innovative approach has been designed offering an integrated combined CPU DSP architecture approach Based on the SH 2 CPU core Hitachi added dedicated DSP capabilities resulting 1n the SH DSP core concept The same is being done with the SH 3 core resulting in the advanced SH3 DSP CPU core Users now have 2 cores integrated in a single architecture with a single instruction stream This simplifies system design and offers an overall cost reduction This approach makes the utilisation of additional and expensive accelerator hardware superfluous in most cases Figure 14 illustrates the advances of the integrated CPU DSP approach over traditional approaches In the SH DSP and SH3 DSP architecture Hitachi added mainly an additional X Y on chip bus structure loop hardware fixed point arithmetic support e DSP oriented addressing modes an DSP oriented instruction set extension The SH DSP architecture offers objec
11. addressing Indirect GBR addressing with displacement Indirect indexed GBR addressing Indirect PC addressing with displacement PC relative addressing mmediate addressing Figure 11 illustrates an example of the various addressing modes This set of addressing modes allows an efficient code generation of modern compilers 10 Description The effective address is the content of register Rn A constant is added to the content of Rn after the instruction is executed 1 is added for a byte operation long word operation 1 2 4 2 for a word operation and 4 for a Equation Rn After the instruction is executed Byte 1 Rn Word 2 gt Longword 4 gt Figure 11 Postincrement indirect register addressing mode Applicable Class Data transfer Arithmetic operations Logic operations Branch System control Total Table 1 SH Instruction set overview Operation Code MOV MOVA MOVT SWAB XTRCT ADD ADDC ADDV CMP cond DIV1 DIVOS DIVOU EXTS EXTU MAC MULU MULS NEG NEGC SUB SUBC SUBV MUL DMULS DMULU DT AND NOT OR TAS TST XOR ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD BF BT BRA BSR JMP JSR RTS BRAF BSRF BF S BT S CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA LDTLB PREF SETS CLRS Instructions SH SH SH Instruction Func
12. autoreload 32 bit timer with input capture function maximum resolution of 2 MHz 4 channel DMA Controller DMAC burst mode and cycle steel mode I O ports up to 16 bits A D Converter ADO 8 channels 10 bits D A Converter DAC 2 channels 8 bits Bus State Controller BSC for glueless connection of external devices physical address space 1s divided into 6 areas maximum pof 64 Mbytes bus size of 8 16 32 bits number of wait cacles settable direct connection of SRAM DR AM SDRAM and burst ROM 2 channel PCMCIA interface support DRAM SDRAM controller usable as little and big endian machine Pin Function Controller PFC is composed of registers for selecting the function of multiplexed pins HD64461 Companion Chip To give full system solution support a companion chip has been developed The HD64461 also features a set of power saving stand by modes The typical power consumption of the HD64461 1s about 1 0 Port PCMCIA 50 mA at 3 3V The HD64461 device can be connected to the SH7709 directly and has the following main features Interface T Figure 28 HD64461 Functional Block Diagram Power Management Unit Colour monochrome STN LCD Controller up to 64 grey scales 256 256K and 64K colours CRT interface support maximum resolution 640x480 10 types of hardware BitBLT hardware acceleration solid line drawing rectangular solid colour fill function
13. systems Target applications of the SH 2 series are for example phones radio equipment motor control robotics control terminals printers scanners music instruments audio applications cameras plotters and projectors User bus Host D15 a Host A Event Detector X gt f Range Detector CH1 Tracestop Block TstampD31 6 Timestamp counter overflow Figure 25 E6000 CES Block Diagram Decoder 82C250 CAN Port SH7045F User Port FLASH Programming Board Monitor Port MAX232 Figure 26 EVB7045F Block Diagram Related Documents SH7040 Series User s Manual Document No 19 033A SH 1 SH 2 Programming Manual Document No 19 005B SH7040 Series On chip supporting modules Document No 19 032 SH C o Embedded The SH 3 architecture 1s a further development of the SH 1 and SH 2 architecture featuring Memory Management Unit MMU support and additional units for high performance cost optimised embedded processor systems In the centre of the SH 3 family is the SH7700 series with a focus on the SH7709 embedded processor The SH7709 device 1s the first choice for st effective Processors High performance 32 bit SH7709 Embedded Processor The SH7709 32 bit embedded processor is based on the SH 3 CPU core and provides a set of peripherals making system design cost effective The S
14. x 32 bit general registers e 8x32 bit shadow registers 7 x 32 bit control registers 4 x 32 bit system registers Integrated Floating Point co processor FPU 3D graphics instructions e 2 way superscalar instruction execution of Integer Unit with FPU 2 instructions cycle at maximum SH7750 Series Based on the SH 4 architecture Hitachi will introduce SH7750 devices running with a clock frequency of up to 200 MHz and a typical power consumption of about 1 5 W at full speed A seperated instruction and data cache will provide the throughput necessary for optimal utilization of the resources The SH7750 features an 64 bit external bus interface and will come in a 256 pin BGA package A further set of peripherals will be integrated simplifying systemdesign A peak performance of 360 Dhrystone MIPS and 1 4 GFLOPs offers the performance needed for next generation multimedia applications Application examples are video game consoles and sub notebook devices Hitachi optimised the SH7750 MMU cache size and peripheral mix for Windows CE applications Besides Microsoft s Windows CE operating system a set of other third party support tools will be available SH7750 Companion Chips Similar to the SH 3 s HD64461 companion chip Hitachi is developing devices suitable for complete system design based on the SH7750 featuring LCD controller embedded DRAM and a set of advanced interfaces and peripherals Als
15. yes yes yes yes yes 10x8 10x8 10x8 QFP 112 QFP 112 QFP 112 HD6417014RFxx HD6437016Fxx HD64F7017Fxx 1 Contact your local sales office for availability SH7011 SH 2 592020 16 ROM less yes yes 10x7 QFP 100 HD6417011Fxx SH7040A SH 2 91203 3a 1G 16 64 yes yes yes yes 10x8 19 033A QFP 112 HD6437040Axx SH7041A SH 2 5533 35 3 16 22 64 yes yes yes yes 10 8 19 033A QFP 144 HD6437041Axx SH7042A SH 2 3 9 39 16 16 128 yes yes yes yes yes 10x8 19 033A QFP 112 HD64x7042Axx SH7043A SH 2 50 2233 3I 1E 22 128 yes yes yes yes yes 10 8 19 033A QFP 144 HD64x7043AFxx SH7044A SH 2 5 33 3 3 16 16 256 yes yes yes yes 10x8 19 033A QFP 112 HD64x7044Afxx SH7045A SH 2 5 33 32 256 yes yes yes 10x8 19 033A QFP 144 HD64x7045Axx SH7044F SH 2 57528 16 256 yes yes yes 10 8 19 033A QFP 112 HD64F7044Fxx SH7045F SH 2 ZO 39 256 yes yes yes yes 10x8 19 033A QFP 144 HD64F7045Fxx SH 3 Family Devices Device Core Vcc V Max Clock MHz External Bus Width On chip RAM kByte Cache kByte if RAM mode is used Memory Management Unit Interrupt Controller External Interrupt Pins DMAC channels Watch Dog Timer channel Serial Communication Interface IrDA 1 0 Support Smart Card Support PCMCIA Interface Support UO Ports including input only 32 bit Timer cha
16. 3 7 79 Central Germany Friedrich List Str 42 D 70711 Leinfelden Echterdingen Tel 49 7 11 9 90 85 5 Fax 49 7 11 9 90 85 99 South Germany Austria Dornacher Str 3 D 85622 Feldkirchen Tel 49 089 9 91 80 Fax 49 089 9 91 80 266 Italy Via Tommaso Gulli 39 1 20147 Milano Tel 39 2 48 78 61 Fax 39 2 48 78 63 91 Via F D Ovidio 1 00135 Roma Tel 39 6 82 00 18 24 Fax 39 6 82 00 18 25 South Africa 7th Floor Nedbank Gardens 33 Bath Avenue Rosebank 2196 Jb Tel 27 11 44 290 80 Fax 27 11 442 9745 Spain c Bunganvilla 5 E 28036 Madrid Tel 34 91 7 67 27 82 92 Fax 34 91 83 85 11 HITACHI The vital component Nissei Sangyo GmbH Nissei Sangyo GmbH Deutschland Germany Dorncher Str 3 D 85622 Feldkirchen Tel Local O 89 9 91 300 INT 49 89 9 91 300 Fax Local O 89 9 29 11 85 INT 49 89 9 29 11 85 Kurfurstendamm 115b D 10711 Berlin Tel 49 30 89 36 81 0 Fax 49 30 8 91 10 31 Hungary East West Business Center Rakoczi UT 1 3 H 1088 Budapest Tel 36 1 2 66 66 58 Fax 36 1 2 66 49 27 Spain Gran Via Carlos Ill 101 1 E 08028 Barcelona Tel 34 34 90 78 01 Fax 34 33 39 78 39 Nissei Sangyo France S A R L France Immeuble Ariene 18 rue Grange Dame Rose F 78140 Velizy Cedex Tel 33 1 30 70 69 70 Fax 33 1 34 65 77 28 Nissei Sangyo Co Ltd United Kingdom Whitebrook Park Lower Coo
17. Devices SH7020 SH7020S SH7021 SH7032 SH7034 ROMless ROMless SH 1 SH 1 SH 1 SH 1 SH 1 5 20 5 20 5 20 5 20 O SE APS SW M AE 16 16 16 16 16 16 32 64 yes yes yes yes yes 1 1 1 8 4 13779 1397 9 oU SAS 4 4 4 4 4 1 1 1 1 1 2 2 2 2 2 40 40 40 40 40 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes 10 x8 10x8 19 015A 19 015A 19 015A 19 011B 19 011B TQFP 100 TQFP 100 TQFP 100 QFP 112 QFP 112 TQFP 120 HD6437020xxx HD6417020xxx HD64x7021xxx HD6417032xxx HD64x7034xxx Vcc V Max External E On chip ROI Mask RON ZTAT OTP F ZTAT Flash On chip RAI if cache Cach Interrupts Internal DMA Controller Watch Dog Timer Serial Communication UO Ports including in Multifunction Tin Unit t Compa Timer e Advanced Pulse Advanced T Bus State User Break Clock Pulse C A D Converter bits x D P Device Core ck MHz ius Width M kByte Version Version Version VI kByte gt is used e kByte External channels channel Interface put only ner Pulse channels re Match channels ontroller imer Unit ontroller ontroller enerator channels ata Book Package art Name SH 2 Family Devices SH7014 SH7016 SH7017F ROM less SH 2 SH 2 SEI 2 5297 27 5 oe 16 16 16 128 64 yes yes 5 3 1 4 2 1 1 2 AD um ASA T ADA T 2 2 P 1 1 1 2 D 2 43 82 82 3 3 3 2 D P yes
18. H7709 features 8 kByte of Cache a Windows CE compliant Memory Management Unit MMU a Bus State Controller The SH7709 is available with 80 MHz internal clock frequency and provides a set of power down mechanisms and modes especially useful for battery powered handheld systems At full speed the SH7709 has a typical power consumption of 100 mA at 3 3V The SH7709 interfaces glueless to the HD64461 companion chip which includes a set of further interfaces and a colour LCD graphics controller The SH7709 can be used with and without the HD64461 device Windows CE powered systems The dedicated companion chip HD64461 for the SH7709 makes optimised system BSC featuring also SDRAM support and an optimised mix of further peripherals simplifying system design and design for Windows CE applications reducing overall system costs possible Hitachi is a system solutions provider for Windows CE applications SH 3 Architecture 32 bit virtual address bus 32 bit data bus 1 e 32 bit internal data path e 16 bit fixed length RISC type instruction set e oad Store architecture e 5 stage pipeline 4 Gbyte address space Peripheral address bus 1 ei Y 2 im o amp amp E ei 16 x 32 bit general registers e 8x32 bit shadow registers 5 x 22 bit control registers 4 x 32 bit system registers e Basic instructions are executed in 1 cycle
19. Monitor Port Port Figure 19 EVB7032 Block Diagram Related Documents SH7020 SH7021 Hardware Manual Document No 19 015A SH7032 SH7034 Hardware Manual Document No 19 011B SH 1 SH 2 Programming Manual Document No 19 005B SH7000 Series CPU Application Note Document No 19 026 TARGET HARDWARE Header Assembly Target IF 32k x 8 32k x 8 128 x 8 128 x 8 RAM RAM SH Bus Connector SH 2 Advanced 32 bit Embedded Controllers Based on the SH 2 architecture two basic types of device have been introduced the SH7040 and the SH7050 series Both series offer a leading edge price performance ratio integrated peripherals and the advantage of being object code upward compatible from the SH 1 family In addition several peripherals are similar to program thus the SH 2 family provides a straight forward upgrade path from SH 1 solutions SH 2 Architecture e 32 bit internal data path e 16 bit fixed length RISC type instruction set e Load Store architecture e 5 stage pipeline 4 Gbyte address space 16 x 32 bit general registers e 3 x 32 bit control registers 4 x 32 bit system registers e Basic instructions are executed in 1 cycle Multiplication operations 16x16 32 32x32 32 and multiplication 1 1 1 m 3 3 accumulation operation 16x16 64 64 32x32 64 64 executed in 1 4 cycles 64 bit accumulator Processing states program execution exception processing
20. RAM ATU SCI x 3 CMT APC 16ch A D DMAC x 4 Automotive ASSP 168 pin 20MIPS 5V SH2 Core 32x32 64 bit MAC 128k 64k ROM 4k RAM or 1k 1k RAM Cache MTU CMT DMAC x 4 A D SCI x 2 DTC Motor Control ASSP 144 pin 28MIPS 5V 16MIPS 3 3V SH2 Core 32x32 64 bit MAC A D SCI x 2 DTC Motor Control ASSP 112 pin 28MIPS 5V 16MIPS 3 3V CU 42 bit MAC 16k 1k ROM RAM MAC Resolution i S ROM RAM DMAC x 4 Peripherals SCI x 2 CMT 100 pin 20MIPS 5V 12 5MIPS 3 3V _ Analogue to digital converter 10 bit resolution Advanced Pulse Controller ATU Advanced Timer Unit Compare Match Timer DMAC Direct Memory Access Controller DTC Data Transfer Controller H UDI Hitachi user Debug Interface Embedded Controllers the SH DSP series offering an extended instruction set to serve the need for additional DSP performance with a single architecture SH DSP Core FLASH RAM Multiple Timers ADC SCI s LZ 176 pin GOMIPS SH7055F SH 2E Core 32 x 32 64 bit MAC 512k FLASH 32k RAM FPU ATU II APC HCAN x 2 CMT DMAC x 4 SCI x 5 A D x 3 7 AUD H UDI 256 pin 40MIPS 5 3 3V SH2 Core 32x32 64 bit MAC 64k ROM 128k FLASH rd 3k 4k RAM Cache MTU CMT DMAC x 2 SCI x 2 A D SH2 Core 32x32 r 64 bit MAC 4k 1k RAM Cache 256k FLASH z MTU CMT 112 pin DMAC x 4 28MIPS 5V A D SCI
21. SC instruction pipeline The address space is uniform and unsegmented The instruction set has been carefully chosen to provide a high level language orientation thus simplifying programming of the individual devices All basic SH CPU cores feature the integration of power saving strategies and implement methods to control the power consumption of peripherals o 1 e o 1 e o 1 e SH3 SH3 DSP SH4 Figure 8 SH Architecture General Purpose Register Bank Control Registers and System Registers Overview Register Configuration In case of the SH architecture arithmetic and logical instructions operate normally on the 32 bit general purpose registers Special load store instructions are provided to transfer data from memory to registers and vice versa Figure 8 below shows the basic General Purpose 32 bit register bank which 15 used for source and destination operands The SH 3 SH3 DSP and the SH 4 architecture feature in addition to the basic 16 registers 8 32 bit shadow registers which can be accessed in the so called privileged mode Besides the general purpose registers the SH architecture provides 4 System Registers providing a Program Counter PC Procedure Register PR and 2 32 bit Multiply and Accumulate Registers MACH MACL A block of Control Registers finally completes the set of registers in the basic SH architecture The Control Register Block contains the Status Registe
22. bus release reset sleep mode standby Common SH 2 Peripherals The SH7040 and SH7050 series have the following peripherals in common Interrupt Controller INTC for 8 1 external and a set of internal interrupt sources up to 16 priority levels can be programmed User Break Controller UBC simplifying debugging of user programs Clock Pulse Generator CPG PLL supplying the LSI and external devices with clock pulses from a connected crystal resonator or an external clock a PLL provides clock multiplication Watchdog Timer WDT for monitoring system operations 4 Channel DMA Controller DMAC accumulate operations subroutine procedure Compare Match Timer CMT configured of 16 bit timers for 2 channels includes 16 bit counters and can generate interrupts at set intervals I O Ports several I O ports have been integrated into SH 2 devices Bus State Controller BSC A D Converters ADC for details see below Serial Communication Interface SCD at least 2 channels supporting clocked synchronous and asynchronous mode selectable bit rates via on chip baud generator full duplex communication multiprocessor communication function Pin Function Controller PFC is composed of registers for selecting the function of multiplexed pins Single cycle access on chip ROM and RAM 32 bit amount of on chip ROM and RAM varies some devices SH7040 series can be configured to split the RAM into a RAM block
23. d SH7010 series This series features very cost effective ROMless devices SH7011 and SH7014 the SH7016 derivative with 64 Kbyte on chip mask ROM and 3 Kbyte RAM as well as a pin compatible FLASH derivative This SH7017F device with 128 Kbyte on chip FLASH memory and 4 Kbyte RAM allows high intergrated solutions for different applications The SH7010 series offers a lot of integrated peripheral functions These Compact versions are featuring the modifications compared to the SH7040 series illustrated 1n the subsequent tables SH7014 ROMless 3 KB RAM 1 KB Cache 43 I O ports 3 channels MTU Ich S amp H ADC Sch SCI 2 channels no DTC no UBC 28 7 MHz 5v QFP 112 pin SH7016 7017F 64 KB ROM 128 KB FLASH 3KB 4KB 1 KB 2 KB Cache 82 I O ports 3 channels MTU Ich S amp H ADC Sch SCI 2 channels no DTC no UBC 28 7 MHz 5v QFP 112 pin SH7011 ROMless 4 RAM 11 I O ports 3 channels MTU 8 bit Timer x 2 1ch S amp H ADC 7ch SCI 1 channel no DTC no UBC 20 MHz 3 3v TQFP 100 pin Flash Memory Several devices of the SH7040 and SH7050 series integrate 256 kbytes of Hitachi s flash memory F ZTAT technology providing an increased flexibility for system design The integrated flash memory features 4 flash memory operating modes program erase program verify erase verify e 32 bytes at a time programming with typical programming time of 10 ms 300 us typical per byte
24. dressed area 1 up to 16 Mbyte when set to DR AM The BSC supports the following features 8 16 bit external data bus On chip ROM and RAM can be accessed in 1 cycle 32 bit e Wait states can be inserted using the WAIT pin Direct interface to DRAM SRAM and ROM Control signals Access control Supports parity check and generation for data bus Refresh counter can be used as 8 bit interval timer SH7020 Series The SH7020 series includes 1 Kbyte of RAM and is available with 16 and 32 Kbyte of ROM also a ROMless version is available The SH7020 series includes all the above mentioned peripherals SH7030 Series The SH7030 series is available with 4 and 8 Kbyte of RAM It either has 64 Kbyte of ROM or comes as ROM less D PROM or masked ROM ROMless s 2 im En s A x o Serial communication interface 2 channels 5 e o Programmable A timing pattern a controller E B Peripheral address bus 24 bits B Peripheral data bus 16 bits Internal address bus 24 bits version In addition to the above introduced peripherals the SH7030 series features A D Converter 10 bits x 8 channels e 8 bit input port additional register for storing pin data Individual SH7020 7030 devices are available in extended temperature range qualification Direct Memory Access Controller Bus state controller
25. echnology memory devices and LCD displays The next pages will guide you through the most important features of Hitachi SuperH 32 bit embedded microcontroller and microprocessor family and will provide useful background information TM SuperH Choosing a microprocessor leads to a long term relationship between user and microprocessor provider Thus several criteria play a decisive role for the success of a microprocessor architecture It is not only the technical leadership it is also the support environment as well as the processor roadmap where users have to co operate with the provider for a long time The facility to switch from low cost to a very high performance device with a minimum of redesign effort can be a crucial factor for the future success This is not restricted to but especially true for the 32 bit embedded domain Maybe the most important feature of the SuperH processor family is the availability of a series of upward compatible architectures being optimised for a lot of different applications and markets The SuperH also simply called SH provides even object code upward compatibility throughout the family Based on a common 32 bit RISC architecture Hitachi developed the SH 1 architecture further extended by SH 2 SH 3 and SH 4 The SH 1 architecture Architecture has been created for 32 bit embedded control applications requiring a high performance at very low costs combined
26. for ROM mode 3 areas Input Port of up to 4 Mbytes linear address E Peripheral address bus 24 bits Internal upper data bus 16 bits E Peripheral data bus 16 bits B Internal lower data bus 16 bits space 1 area up to linear 16 Mbytes of DRAM dedicated space DRAM controller 8 16 32 bit external data bus size 32 bit only for 144 pin Internal address bus 24 bits Figure 21 SH7040 Series Functional Block Diagram See selection guide for details devices number of wait cycles can be set 1 cycle on chip RAM and ROM e Data Transfer Controller DT C access performing data transfers activation Multifunction Timer Pulse Unit by interrupts or software several MTU up to 16 types of waveform transfer modes outputs or up to 16 types of pulse A D Converter ADC 10 bits x 8 I O processing based on 16 bit timer channels sample and hold function 5 channels capture registers 16 with 2 on chip units multiple comparators counter input clock conversion modes 8 data registers input capture pulse output mode PWM mode phase calculation 2 Channel Serial Communication Interface SCT I O Port 5 ports for general purpose I Os 1x10 bits 2x16 bits 112 pin 2x16 bits 144 pin 1x24 bits and 1x32 bits and 1 port as general 8 bit input port SH7010 SH 2 Compact Version Hitachi is introducing a set of SH7040 compact derivatives offering an application oriented line up name
27. ign or learning curves to a minimum SuperH represents a family of devices which focused right from the start and across all family members on low power consumption high code density high level of integration and system cost reduction Thus members of the SuperH product family are leaders in the 32 bit embedded arena in terms of power consumption MIPS Watt code density and system costs While spanning a range from 10 to 360 32 bit nd MIPS the SuperH family offers devices for nearly all 32 bit embedded applications Besides offering standard devices such as the SH7040 line see below Hitachi is also a leader in ASIC technology With the CBIC and uCBIC approach Hitachi created the basics to enable efficient ASIC design and system on a chip solutions based on the SuperH CPU core family A library of state of the art modules and an open system design approach enables Hitachi together with customers to provide optimised controller solutions in a very early stage of the overall product design cycle The uCBIC approach is not restricted to the 32 bit SuperH CPU core family also 16 bit H8 300H and H8S cores are available for further integration Figure 2 SuperH CPU Family Overview SuperH Embedded Controllers need a clear focus on high integration high code density as well as low power consumption The SH 1 SH 2 and SH DSP have been designed and are continuosly further developed for the
28. ith 5 channels up to 12 different pulse outputs and 10 different pulse inputs can be 31 0 31 0 Figure 16 SH 1 System registers Integrated processed compare match waveform input capture counter clearing PWM mode phase counting DMAC activation Watchdog Timer WDT for monitoring system operations Programmable Timing Pattern Controller TPC maximum output of 16 bit data output can be enabled on a bit by bit basis Serial Communication Interface SCI 2 channels supports clocked synchronous and asynchronous mode selectable bit rates via on chip baud generator full duplex communication 4 Channel DMA Controller DMAC Parallel I O Ports 2 16 bit input output ports each port has a register for storing pin data Bus State Controller BSC for details see below Pin Function Controller PFC 1s composed of registers for selecting the function of multiplexed pins Single cycle access on chip ROM and RAM 32 bit Multiply and accumulate MAC registers high and low MACH MACL Store the results of multiply and accumulate operations MACH is sign extended when read because only the lowest 10 bits are valid Procedure register PR Stores a return address from a Program counter PC Indicates the fourth byte second instruction after the current instruction Bus State Controller BSC The BSC divides the address space into 8 areas A maximum of 4 Mbyte of linear address space for each area can be ad
29. its and other peripherals Members of the embedded processor line have been designed for consumer applications such as PC companions or other handheld devices Other application areas are telecommunication multimedia and automotive applications Figure 4 gives an overview of the various members of the embedded processor line The Processors SuperH embedded processor line is a leader in the Windows CE area offering optimised and complete system solutions for PC companions as well as other Windows CE based systems SH7750 SH4 Core Superscaler 8 16 32 64 bit Bus FPU Graphics MAC 8k 16k Cache MMU SCI x 2 RTC DMAC SDRAM Bus Interface SH7729 SH3 DSP Core PCMCIA Timer 8 16 32 bit Bus DSP Unit 16k Cache 256 pin MMU SCI x 3 RTC SH3 Core 360MIPS 1 8V DMAC SDRAM 8 16 32 bit Bus PCMCIA 32x32 Bus Interface 64 bit MAC Timer 8k Cache MMU SCI x 3 RTC 133MIPS DMAC SDRAM 208 pin PCMCIA 133MIPS 266 MOPS Bus Interface A D D A Timers SH3 uCBIC Core SH3 Core Single Precision Floating Point 8k Cache SH 3E Core Single Precision FPU 208 pin 80MIPS 3 3V A e MAC SDRAM 5 Multiply and Accumulate Synchronous DRAM Serial Communications Interface Direct Memory Access Controller Real Time Clock Memory Management Unit DMAC RTC MMU Designed for WindowsCE Desigrar Io SuperH RISC PROCESSOR ENC INE Mic
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31. n state e Power down state CPU halts operation and power consumption is reduced e Bus released state the CPU has released the bus to a device that requested it All SH devices have built in power down modes Sleep on chip peripherals still run Standby on chip peripherals halt Module stand by only SH 3 SH3 DSP SH 4 specified modules halt The SH 3 SH3 DSP and SH 4 architecture incorporate 2 processor modes user mode and privileged mode Normal program execution is done in Address Address Address Address A A 1 A 2 A 3 m E 15 E 0 Address Address Address Address A 11 A 10 A 9 A 8 7 Byteo Bytes Byte2 Byte3 Address E A 4 Address Nm A Longword Longword Big endian Little endian Figure 12 Memory data formats Byte Word and Longword Alignment only SH 3 SH 3 DSP SH 4 31 Figure 13 Longword Register Operand user mode privileged mode is normally Peripherals entered when an exception occurs Also the shadow registers see Figure 8 are All SH processors feature around the basic CPU core a set of peripherals Details of the individual SH families and then accessible Exception series are listed below Processing Nevertheless all SH devices feature a set of common peripherals such as The SH family provides a single uniform Interrupt Controller INTC mechanism for handling all exceptions e Watchdog Timer WDT wether caused b
32. names H ITACH http www hitachi eu com hel ecg Hitachi Europe Ltd Electronic Components Group Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA UK Tel Local 01628 585000 INT 2 44 1628 585000 Fax Local 01628 585160 INT 44 1628 585160 Sales Offices Denmark Egebaekvej 98 2850 Neerum Tel 45 45 80 77 11 Fax 45 45 80 77 54 Finland Tap House Tapiolan Keskustorni 11 krs 02100 Espoo Tel 358 9 455 2488 Fax 358 9 455 2152 Norway PO Box 153 stre Strandvei 4B N 3482 Tofte Tel 47 32 79 51 11 Fax 47 32 79 52 30 Sweden Haukadalsgaten 10 Box 1062 16421 Kista Stockholm Tel 46 85 62 712 00 Fax 46 87 51 50 73 Eire Odeon House Eyre Square Galway Eire Tel 353 91 56 20 20 Fax 353 91 56 20 14 France Hitachi Europe France S A 18 rue Grange Dame Rose B P 134 F 78148 Veliz Cedex France Tel 33 1 34 63 05 00 Fax 33 1 34 65 34 31 Hitachi Europe GmbH Electronics Components Group Continental Europe Sales Offices Germany Dornacher Str 3 D 85622 Feldkirchen Postfach 2 01 D 85619 Feldkirchen Tel Local O 89 9 91 800 INT 49 89 99 1800 Fax Local O 89 9 29 30 00 INT 49 89 929 3000 North Germany Benelux Am Seestern 18 D40547 Dusseldorf Postfach 11 05 36 D 40505 Dusseldorf Tel 49 O2 11 52 83 0 Fax 49 02 11 52 8
33. nnel SCI and does not have ADC or DAC The SH7708 1s also capable of running Windows CE SH 3 DSP Hitachi is also currently developing more enhanced derivatives based on an extended SH 3 architecture The SH 3 DSP featuring additional instructions and units for Digital Signal Processing DSP Full SIR FIR SH3 SH7709 EPROM or SRAM 128 KBytes max DRAM SIMM 72 pin FLASH 0 4 8 16 MBytes support The SH 3 provides instruction set upward compatibility to the SH 3 DSP architecture also code running on the aforementioned SH DSP is upward compatible to the SH 3 DSP A first member of the enhanced SH 3 DSP family will be widely compatible to the SH7709 thus providing a simple and fast upgrade path Application Examples The SH 3 embedded processor family has been designed for applications such as handheld PC companions multimedia phones internet appliances car information systems navigation systems multimedia equipment and terminals B PC Card Mem amp 1 0 m PC Card D Memory LCD FPC LCD Adapter J Vee Generator Plug in daughter cards shown outlined in red E Uncommitted 1 0 x22 bits Figure 29 EBX7709 Development Board Functional Block Diagram Related Documents SH7709 Hardware Manual Doument No 19 036 SH7700 Series Programming Manual Document No 19 027 SH7708 Hardware Manual Document No 19 029C SH 4 The N Embedded Hitachis SH 4 architecture in
34. nnels Real Time Clock Bus State Controller SDRAM Interface User Break Controller Clock Pulse Generator A D Converter bits x channels D A Converter bits x channels Litte endian Support Big endian Support Data Book 19 029C 19 036 Package LQFP 144 QFP 208 Part Name SH7709 SH 3 3 3 80 22 12 x 8 bit 3 yes yes yes yes yes 10x8 O RZ yes yes 19 036 QFP 208 HD6417709F80B Development Tools The development of applications based on the SH 1 family is supported by evaluation boards and emulators Hitachi provides the EVB7032 evaluation board featuring a SH7032 device and PCE low cost in circuit emulators The PCE Emulators feature Zero wait state real time emulation Emulation memory e PC breakpoints Hardware comparison breakpoints Trace buffer e Oscilloscope trigger facility Multiple clock selection e Performance analysis The development support comprises of a C compiler and debugger A wide variety of third party tools are also available for the SH 1 series Application Examples The SH 1 series focuses on embedded control applications such as printers fax machines motor control cameras musical instruments household appliances card reader phones radio equipment inverter security systems robotics PC Break Point System Level Shifters Microcontroller Figure 18 PCE Emulator Block Diagram 64k x 8 ROM User
35. o this set of companion chips will provide efficient power saving mechanisms especially suitable for battery driven handheld devices Hitachi Hitachi Components Databook 16 007 CD ROM Electronic This CD ROM is available free of charge from Hitachi or our authorised distributors Please ring 49 0 89 99180 245 to order your copy or send a fax to 49 0 89 99180 265 It contains approx 20 000 pages of Hitachi documentation about microcontrollers memories and packages This includes the actual hardware manuals for almost all our microcontrollers as well as application notes programming manuals and overviews A powerful selection tool allows you to run a selection to find out which Hitachi microcontrollers are suitable for your application The CD ROM is usable under Windows and Macintosh Internet access WWW Under Hitachi s Electronic Components Group ECG homepage address URL http www hitachi eu com hel ecg index htm you have access to detailed technical product information about Hitachi s microcontrollers memory displays ASIC discretes amp power modules and optoelectronic components For memory and microcontroller products each user can download complete data sheets and application notes 1n PDF format You will also find a complete overview over Hitachi s European Microcontroller development tools with a short description the package contents and the ordering information part
36. on Set Upward Compatibility Slot Instruction A IF ID Next instruction IF ID Third instruction in series gt Slot PMULS W FD MA mmmm Next instruction IF Third instruction IF ID EX MA WB ID EX MA WB 6 6 Slot Instruction A ID EX Next instruction IF ID Third instruction in series Instruction Fetch Instruction Decode Execution Memory Access multiplier can occur Figure 10 Instruction Pipelining Write Back Multiplier Operation If instruction also uses the pipeline contention Examples does not need all stages and extended if an instruction needs some more latency cycles to be completed or if pipeline contention occurs To reduce pipeline penalties a delay slot mechanism has been provided reducing pipeline breakages The instruction set can be classified into the following operation categories e Data transfer e Arithmetic Logical e Shift Branch System control Extended such as Floating Point or DSP operations not for SH 1 SH 2 and SH 3 The data transfer instructions can be used with following addressing modes e Direct register addressing e Indirect register addressing e Postincrement indirect register addressing e Predecrement indirect register addressing Indirect register addressing with displacement e Indirect indexed register
37. r SR the Global Base Register GBR the Vector Base Register VBR and in case of SH 3 SH3 DSP and SH 4 the Saved Status Register SSR and the Saved Program Counter SPC The General Purpose Register RO functions as index register for indirect indexed addressing modes see below In the case of SH 1 SH 2 and SH DSP the register R15 1s also used as a hardware stack pointer SP Register operands are always 32 bit longwords When the memory operand is only a byte or a 16 bit word it is sign extended into a longword when loaded into a register Instruction Set One main strength of the SH processor family is the instruction set upward com patibility of the various CPU cores Figure 9 gives an overview of the instruction set compatibility The basic SH instructions are all 16 bits long and thus tentatively offer a twice as efficient code density compared to conventional 32 bit RISC architectures SH3 DSP 160 types MMU amp DSP instructions SH DSP 154 types DSP instructions SH 1 56 types The advantage of the used RISC approach can be seen by pipeline mechanism allowing very high clock frequencies The SH pipelining mechanism provides a single cycle peak throughput for the basic instructions 2 in case of the superscalar SH 4 For that purpose the SH architecture is using a basic 5 stage pipeline see Figure 10 The pipeline is automatically reduced if an instruction Figure 9 Instructi
38. rH Architecture Evolution ouperH M i M i The previously introduced SuperH family 1s defined by the main line SH 1 to SH 4 and includes a sub line the SH DSP and SH3 DSP architecture line These architectures can be separated into a major embedded controller line and an embedded processor line The embedded controller line is based on the SH 1 SH 2 and SH DSP architectures the embedded processor line on the SH 3 SH3 DSP and SH 4 architecture Figure 2 provides an overview of the individual implementations separated into the aforementioned controller and processor line and gives a first indication of the performance of the individual devices Several lines have been designed to offer cost reductions by integrating special application oriented peripherals for dedicated markets Users can chose from a huge number of compatible devices and derivatives Thus users will find SH5 CORE 1000 MIPS SH4 CORE 360 MIPS SH3 DSP CORE 133 MIPS 266 MOPS SH DSP CORE 60 133 MIPS SH DSP CORE 60 MIPS 120 MOPS SH2 CORE 28 MIPS SH1 CORE 20 MIPS Family crocontrollers a croprocessors of members of the SuperH family for industrial automation as well as for multimedia applications such as video game consoles and lots of other applications Because of the compatibility across the family users have the security of finding the right device for different applications while reducing the costs of redes
39. rectly Operates on memory locations The result is stored as before in the system registers This 1s especially useful as the MAC instruction operates normally on a big linear set of data General Purpose registers are used for storing the current memory addresses which are automatically updated upon completion of a MAC instruction Immediate Data The SH architecture provides a very efficient mechanism to process immediate data values Byte immediate data are directly located 1n the 16 bit instruction code Word or longword immediate data are stored in a memory table which can be accessed by an immediate data transfer instruction When the immediate data is loaded the value 1s transferred to the register bank Data Format Memory data formats are classified into bytes words Address A ds The SH and longwords The Address architecture is basically a 4 vw big endian machine but ica SH 3 SH3 DSP and SH 4 devices also support little endian mode see Figure 12 Figure 13 illustrates the data format of registers When the memory operand is only a byte or a 16 bit word it is sign extended into a longword when loaded into a register Processor States and Modes The SH architecture provides a set of processor states Reset state Exception handling state transient state during which the CPU s processor state flow is altered by a reset general or interrupt exception Program executio
40. ronic industry Hitachi is committed to play a very active role to build this information society Hitachi general strategy is working closely together with its customers at the leading edge for all of its products and services while providing a maximum of quality and reliability Advanced and next generation microprocessors play a very important role 1n products and services for the information society Hence Hitachi developed an advanced 32 bit RISC processor family called SuperH This 32 bit processor family 15 based on a broad range of devices optimised for a wide variety of applications It is not sufficient just to provide leading edge technology to make processors a success With this in mind Hitachi also offers technical support software and tools helping customers and partners get their products on the market What is more Hitachi even establishes global partnerships to enhance support and quality of products and services This explains that the SuperH 32 bit processor family is one of the leading architectures 1n the world Currently offering devices from 10 to 360 MIPS the SuperH series can be used as basis for low end embedded control applications up to high end products with stringent performance requirements When offering SuperH solutions to our customers we benefit from the wide knowledge we collected by developing and marketing 4 8 and 16 bit embedded controllers LCD controllers ASIC t
41. rosoft Wanders CE Part Number CPU Core Bus Width MAC Resolution Cache Peripherals TM SuperH The SuperH CPU family is one of the most successful architectures in the 32 bit embedded domain With shipments of roughly 20 million units per year based on 1997 data the SuperH family has a broad customer base using these devices in a huge variety of applications Mar ket View At Hitachi we went even further by setting up a European engineering and tool design subsidiary 12 years ago Hitachi Microsystems Europe HMSE based in Maidenhead UK Shipments SuperH M units Hitachi is also the second biggest supplier of 16 bit microcontrollers to the European market according to Dataquest as well as the third for 4 bit sixth for 8 bit Hitachi produces and ships over 12 million H8 microcontrollers every month this includes almost 4 million H8 Flash devices Hitachi semiconductor products are used all over the world and Hitachi offers services and support in nearly all corners of the world This ensures a proper worldwide sales and support service helping the customers to shorten the design cycle and to get the right support in time Hitachi partner s providing third party assistance and support can also be found throughout the world providing additional resources and capacities for your system design based on SuperH Communication 696 Industrial 4996 Figure 6 SuperH
42. st and high integration while offering the performance of a 32 bit controller The SH 1 series integrates on chip RAM and ROM All SH 1 implementations incorporate a 16 bit hardware multiplier which produces a 32 bit result What is more all SH 1 devices implement a 42 bit accumulator for 16 bit data giving you the performance needed in most of the 32 bit applications of today SH 1 Architecture e 32 bit internal data path e 16 bit fixed length RISC type instruction set e Load Store architecture e 5 stage pipeline e 4 Gbyte address space e 16 x 32 bit general registers e 32 bit control registers 4 x 32 bit system registers Basic instructions are executed in 1 cycle sign extended Low cost Embedded Controllers Highly e Multiplication operations 16x16 32 executed in 1 3 cycles multiplication accumulation operation 16x16 42 42 executed in 2 3 cycles 42 bit accumulator Processing states program execution exception processing bus release reset sleep mode standby Common SH 1 Peripherals Interrupt Controller INTC for 8 1 external and a set of internal interrupt sources up to 16 priority levels can be programmed User Break Controller UBC simplifying debugging of user programs Clock Pulse Generator CPG supplying the LSI and external devices with clock pulses from a connected crystal resonator or an external clock e 16 bit Integrated Timer Pulse Unit ITU w
43. t code upward compatibility from the SH 1 and SH 2 architecture the SH3 DSP from the SH 1 SH 2 SH DSP and SH 3 architecture providing an easy upgrade path for future products Ge DSP vs MAC Functionality For several applications it 1s sufficient to use the SH 5 integrated MAC functionality and accelerator respectively As this MAC has been optimised for memory accesses it 1s especially useful for running filter algorithms This already offers enough performance for several DSP algorithms With the SH DSP and SH3 DSP the SH family will offer alternatives to run DSP algorithms if a higher performance is required Figure 14 Conventional vs Integrated Program single instruction stream CPU DSP System Solution Approach Register Bank Register Bank Control panel display Bnalo panel display and other 5 and other functions ee others functions uL DSP Analog others 32 SH DSP Address l Figure 15 Main TAG 16 x 32 bit SH DSP Integrated Sus DSP Unit Functional 16 IEEE Block Diagram RISC RISC Data or or Eg DSP Y DSP X Memory Memory Flexible Memory for Data Program DECS Control ROM or RAM Signal 16 32 Prefetch Unit ALU Barrel Shifter SH 1 32 bit The SH 1 series forms the basis of the SuperH embedded controller family The members of this family have been optimised for low co
44. tion 1 2 3 s Types Data transfer 4 4 4 SH 1 39 5 SH 2 39 5 SH 3 40 6 Add Subtract Multiply 4 4 4 SH 1 26 17 Divide initialize and SH 2 33 21 step SH 3 34 21 Multiply And Accumulat e Negate Extract Double Length Multiply 4 4 Decrement and Test Bitwise logic operations 4 4 4 14 6 Memory Test And Set Bit Test Rotate Shitt one bit Y 4 4 SH 1 14 10 arithmetic logical SH 2 14 10 Shift n bits logical SH 3 16 12 n 1 2 8 or 16 Shift n bits dynamic Y arithmetic logical 325 lt n lt 31 Conditional branch Y 4 Y SH 1 7 7 unconditional SH 2 11 9 branch calLjump return SH 3 11 9 with delayslot Far branch call 4 4 conditional branch with delayslot Clear T bit 4 Y 4 SH 1 31 11 SH 2 31 11 SH 3 74 14 4 SH 1 133 56 SH 2 142 62 SH 3 189 66 Instruction Fetch Besides optimising the costs for storage media the fixed 16 bit instruction length also solves the bottleneck problem of conventional 32 bit RISC architectures On a 32 bit memory access 2 instructions can be loaded in parallel reducing the necessary memory accesses by a factor of 2 MUL MAC Operation The SH architecture and thus all SH devices include a hardware multiplier providing a very high arithmetic performance The multiply instruction MUL operates on register contents and stores the data in the dedicated system registers MACL MACH The multiply accumulate instruction MAC di
45. troduces the next wave of embedded computing processors With superscalar features very high clock frequencies advanced power saving mechanisms an integrated floating point unit and extended high performance graphics support SH 4 devices are the basis for next generation multimedia consumer applications ext Wave of omputing The SH 4 series will be supported by Windows CE version 2 1 and higher The SH 45 instruction set is a superset of the SH 1 SH 2 and SH 3 instruction set thus still providing upward compatibihty This feature will provide a simple and useful upgrade route for customers using for example already SH 3 devices 32 bit Data Store it Data Instruction 2 bit Address Data 32 bit Data Load 32 bit Address Instruction 3 32 bi I Cache 8KB TLB Controller 29 bit Address 32 bit Data 32 bit Data Peripheral Address Lia 64 bit Data 64 bit Data External Bus Interface 26 bit Address Lower 32 bit Data Lower 32 bit Data Upper 32 bit Data 64 bit Data Store 29 bit Address 32 bit Data 32 bit Data 64 bit Data Figure 30 SH7750 Functional Block Diagram SH 4 Architecture The SH 4 architecture has the following main features e 32 bit internal data path e 16 bit fixed length RISC type instruction set e Load Store architecture e 5 stage pipeline 4 Gbyte address space 16
46. uperH All devices in all families in the SuperH series employ a common 32 bit RISC Reduced Instruction Set Computer architecture designed specifically by Hitachi to meet the needs of next generation applications This architecture is implemented in the SH 1 series The SH 2 SH 3 and SH 4 feature upwardly compatible extensions Typically RISC architectures feature e Load Store approach Register orientation e Simple instruction set Uniform instruction issuing Instruction pipelining These basic features have been extended by Hitachi to meet the requirements of modern embedded applications For example Hitachi introduced in the SH architecture a fixed 16 bit instruction length offering a very high code density and thus saving memory and instruction fetch bandwidth Basic SH Features 31 vunner MA o PURPOSE R1 RR R14 31 Casters SR status Register REGISTERS GBR Global Base Register 31 Severe MACH Multiply and Add Accumulator High REGISTERS MACL Multiply and Add Accumulator Low 31 counter O EC Program Counter COUNTER ALL CPU Architecture The SH architecture has the following basic features e Load Store architecture e 32 bit internal data path General Purpose 32 bit Register bank e 32 bit Control Registers e 32 bit System Registers e RISC type instruction set e 16 bit fixed length instruction set 4 Gbyte address space Basic 5 stage RI
47. with an integration of peripherals and on chip RAM and ROM The SH 2 enhances the SH 1 mainly by offering an extended instruction set and a cost optimised cache mechanism The higher performance SH 3 features an extended SH 2 instruction set a memory management unit additional register banks extended cache mechanisms and dedicated peripherals The SH 4 is currently introduced to give the user a maximum of throughput and performance for next generation high end embedded multimedia applications When writing code for the SH 1 it can be re used in object code format even for the SH 4 This kind of software re usability helps Hitachi to shorten the design cycle of new products and helps partners to stay at the forefront of application development while reducing the overall costs Evolution Based on these architectures Hitachi offers leading edge 32 bit microcontrollers and processors and is steadily developing further products to ensure that you are always at the leading edge Hitachi is also a forerunner in combined CPU and Digital Signal Processor DSP architectures The SH DSP and SH3 DSP architectures feature an integrated single architecture approach for general purpose microcontroller and DSP tasks While the SH DSP extends the instruction set of the SH 1 and SH 2 the SH3 DSP s instruction set is a superset of SH 1 SH 2 SH 3 and SH DSP also offering instruction set upward compatibility Figure 1 Supe
48. x 2 Motor Control ASSP 112 144 pin SH2 Core 32x32 16MIPS 3 3V ROMless 4k RAM 8 bit timers x 2 SH2 Core 32x32 SCI A D 64 bit MAC ROMIess 100 pin 3k 1k RAM Cache 20MIPS 3 3V MTU CMT DMAC x 2 SCI x 2 112 pin 28MIPS 5V 16MIPS 3 3V Integrated Timer Unit 5 channels x 16 bits Multiply and Accumulate Multifunction Timer Unit Serial Communications Interface Serial Input Output Timing Pattern Control PERFORMANCE TM SuperH The SuperH embedded processor line of Hitachi has been designed to match the needs of advanced embedded computing requirements Starting with the SH 3 architecture extended by the SH3 DSP and the SH 4 CPU core a set of compatible devices has been created for the needs of embedded processor applications of today The SuperHTM embedded processor line features for example high performance cache mechanisms or Memory Management Figure 4 SuperH Embedded Processors Family Tree mx SH3 Core 8 16 32 bit Bus 32x32 64 bit MAC 8k Cache MMU SCI x 1 RTC Timers SDRAM PCMCIA Bus Interface 144 pin 60MIPS 3 3V 100MIPS 3 3V SH3 Core 8 16 bit Bus 32x32 64 bit MAC 7 2k Cache MMU SCI x 1 RTC Timers SDRAM PCMCIA SH2 Core Bus Interface 8 16 32 bit Bus 32x32 120 pin 60MIPS 3 3V 64 bit MAC 4k Cache Hardware divider SDRAM Interface DMAC x 2 SCI x 1 Timers 144 pin 25MIPS 5V 16 6MIPS 3 3V 32 bit Embedded Un
49. y hardware or software e Serial Communication Interface SCI conditions Exception handling is e Bus State Controller BSC resolved around a single table the User Break Controller UBC Excpetion Vector Table The Vector Base The implementation may differ between Register VBR points to the beginning individual devices In addition to these of that table Exception conditions are peripherals various devices in the series prioritized by dedicated hardware An provide for example Exception Handler which is a kind of DMA Controller DMAC hardware dispatched subroutine call e Parralel I O Ports automatically stores and restores registers Real Time Clock RTC The details of the exception processing A D Converter ADC depends on the individual architecture And a lot more other peripherals implementation and by the implemented Interrupt Controller INTC for further details see below DSP Extensions In more and more embedded control applications 1t 1s necessary to include so called Digital Signal Processing DSP capabilities In traditional approaches this has been solved by adding to the microcontroller system a dedicated DSP processor which differs a lot from traditional microcontrollers and microprocessors The architecture of DSP processors is normally memory oriented includes special addressing modes and the DSP processors instruction set 1s focusing on the processing of DSP algorithms such as Finite or
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