87C196KT Microcontroller
Contents
1. Table 1 Special purpose Memory Addresses Hex Address Description 207F 205E Reserved each byte must contain FFH 205D 2040 PTS vectors 203F 2030 Upper interrupt vectors 202F 2020 Security key 201F Reserved must contain FFH 201E Reserved must contain FFH 201D Reserved must contain FFH 201C Reserved must contain FFH 201B Reserved must contain 20H 201A CCB1 2019 Reserved must contain 20H 2018 CCBO 2017 2016 OFD flag see page 13 12 and page 16 8 2015 2014 Reserved each byte must contain FFH 2013 2000 Lower interrupt vectors Affected Docs 87C196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual order number 273178 3 P2_DIR description change Issue In the 87C196Kx SXC196Jx 87C196CA Microcontroller Family User s Manual the P2 DIR register is incorrectly described The correct description is shown in the following table Mnemonic Address Description Port Direction Register Each bit controls the configuration of the corresponding pin P2 DIR 1FCBH Clearing a bit configures the corresponding pin as a complementary output setting a bit configures the corresponding pin as an open drain output or a high impedance input Affected Docs 87C196Kx 8SXC196Jx 87C196CA Microcontroller Family User s Manual order number 273178 18 87C196KT Microcontroller Specification Update2. 87C196KT Microcontroller Specification Update November 1998 Notice The 87C196KT microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are documented in this specification update Order Number 272862 004 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intels Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Contact your local Intel sales office or your distributor to obtain the lates
3. Clarifications Steppings No Page Status SPECIFICATION CLARIFICATIONS A B Cc 1 X 13 EPA Timer Reset Write Conflict 2 X 13 Valid Time Matches 3 X 13 P6_REG 4 7 Not Updated Immediately 4 X 13 Write Cycle During Reset 5 X 13 Indirect Shift Count Value 6 X 13 Port 4 Address Behavior F X 13 EPA Overruns 8 X 15 Indirect Addressing With Autolncrement 9 X 16 CLKOUT During RESET Documentation Changes No Document Revision Page Status DOCUMENTATION CHANGES 1 272258 002 17 Doc ie inputs to the low EPROM should be 2 272258 002 18 Doc Addresses 201DH and 201FH should contain FFH 3 272258 002 18 Doc P2 DIR description change 87C196KT Microcontroller Specification Update E Identification Information l ntel Identification Information Markings C step devices are identified by the letter C following the eight digit FPO number 10 87C196KT Microcontroller Specification Update intel Errata Errata Problem Implication Workaround Status 2 Problem Implication Workaround Status Executing Routines in the User s ROM While the Device is Operating in Serial Programming Mode All code fetches above the first 8K bytes of user ROM while the device is operating in serial port programming mode will be directed to external memory Therefore if the user wants to call any routines in the user ROM the e
4. ansferred to EPAx TIME This prevents overruns by ignoring new input capture events when both the capture buffer and EPAx TIME contain valid capture times The OVRx pending bit in EPA PEND is set to indicate that an overrun occurred Enable the OVRx interrupt and read the EPAx TIME register within the ISR If an overrun occurs the overrun OVRx interrupt will be generated The OVRx interrupt will then be acknowledged and its interrupt service routine will read the EPAx TIME register After the CPU reads the EPAx TIME register the buffered data moves from the buffer to the EPAx TIME register This sets the EPA interrupt pending bit Check for pending EPAx interrupts before exiting an EPAx ISR Another method for avoiding this situation is to check for pending EPA interrupts before exiting the EPA interrupt service routine This is an easy way to detect overruns and additional interrupts It can also save loop time by eliminating the latency necessary to service the pending interrupt However this method cannot be used with the peripheral transaction server PTS Refer to Summary Table of Changes to determine the affected stepping s 87C196KT Microcontroller Specification Update in 8 Problem Specification Clarifications Indirect Addressing With Autolncrement For indirect addressing with autoincrement a pointer that points to itself results in an access to the incremented pointer address rather than the original pointer add
5. ler Specification Update Preface n Preface As of July 1996 Intel s Computing Enhancement Group has consolidated available historical device and documentation errata into this new document type called the Specification Update We have endeavored to include all documented errata in the consolidation process however we make no representations or warranties concerning the completeness of the Specification Update This document is an update to the specifications contained in the Affected Documents Related Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Related Documents Title Order 87C196KT Advanced 16 Bit CHMOS Microntroller Automotive datasheet 273178 8XC196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual 272258 6 87C196KT Microcontroller Specification Update intel Preface Nomenclature Errata are design defects or errors These may cause the Product Name s behavior to deviate from published specifications Hardware and software designed to be used with an
6. ntire routine must be within the first 8K bytes of memory OA000 OBFFFH in serial port programming mode For example if the RISM GO command is used with a target address of OCOOOH the device will attempt to fetch code from external memory rather than the on board ROM This errata only affects code fetches from the user ROM Data fetches to the entire ROM work correctly It is not possible to execute code from above the first 8K byte of user ROM while the device is operating in Serial Port Programming mode None NoFix Refer to the Summary Table of Changes to determine the affected stepping s A D Conversion Error on First Conversion The first A D conversion performed after a reset of the device may produce a result that is less accurate than the accuracy specification in the datasheet The amount of error is dependent on several environmental conditions including process variation light exposure temperature and Vcc VREF differential If the application is sensitive to A D accuracy an error in the application may occur as a result of the first conversion error Do not compare for the A D result on the first conversion All subsequent conversions should produce accurate results NoFix Refer to the Summary Table of Changes to determine the affected stepping s 87C196KT Microcontroller Specification Update 11 BE Specification Changes ntel Specification Changes None for this revision of this specification upda
7. nts of 1CH into temp register 1CH 1EH increment the contents of 1CH 40H 1DH load the contents of temp into 40H Status Refer to Summary Table of Changes to determine the affected stepping s 9 CLKOUT During RESET Problem For all steppings of the 87C196KT KS the CLKOUT function during reset P2 7 differs from the 87C196KR C step During reset on the 87C196KT KS CLKOUT does not toggle it remains in the high state During reset on the 87C196KR C step CLKOUT continues to toggle 16 87C196KT Microcontroller Specification Update BE intel Documentation Changes Documentation Changes 1 High address inputs to the low EPROM should be A14 8 Issue In the 87C196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual the block diagram for a 16 bit system with EPROM incorrectly listed the high address inputs to the low EPROM as A15 8 The correct inputs are A14 8 as reflected in the following figure Figure 1 16 bit System with EPROM Voc BUSWIDTH AD15 8 ADV 8XC196 AD7 0 A3095 02 Affected Docs 87C196Kx 8SXC196Jx 87C196CA Microcontroller Family User s Manual order number 273178 87C196KT Microcontroller Specification Update 17 Documentation Changes l ntel 2 Addresses 201DH and 201FH should contain FFH Issue In the 87C196Kx 8SXC196Jx 87C196CA Microcontroller Family User s Manual Table 4 2 addresses 201DH and 201FH should contain FFH as shown in the following table
8. ome of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted This table uses the following notations Codes Used in Summary Table Stepping X Frrata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Fix This erratum is intended to be fixed in a future step of the component Fixed This erratum has been previously fixed NoFix There are no plans to fix this erratum Eval Plans to fix this erratum are under evaluation Row Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document 8 87C196KT Microcontroller Specification Update Summary Table of Changes Errata Steppings No Page Status ERRATA A B C Executing Routines in the User s ROM While the Z 3 M NOEN Device is Operating in Serial Programming Mode 2 X X X 11 NoFix A D Conversion Error on First Conversion Specification Changes Steppings No Page Status SPECIFICATION CHANGES A B C None for this revision of the specification update Specification
9. ress The CPU stores the pointer s value in a temporary register increments the pointer then accesses the operand at the address contained in the temporary register as shown in the following flowchart Get Indirect Address Pointer Copy Indirect Address Pointer to Temporary Register Increment Indirect Address Pointer Get Operand from Address in Temporary Register Continue Execution of Instruction A4378 01 Therefore if the pointer points to itself the CPU accesses the operand at the incremented address contained in the pointer For example assume ax 1CH and bx 40H The following code causes the CPU to access the operand at the incremented address ld ax ax ldb bx ax ld 1CH 1CH 1CH 1CH load location 1CH with value 1CH ldb 40H 1CH temp 1CH save 1CH into temp register 1CH 1DH increment the contents of 1CH 40H 1DH load the contents of location 1CH Location 1CH now contains the value 1DH into 40H 87C196KT Microcontroller Specification Update 15 _ Specification Clarifications l ntel R Workaround Avoid using an indirect address pointer that points to itself For example assume ax 1CH bx 1DH and cx 40H The following code causes the CPU to access the operand at the intended unincremented address ld ax bx where bx ax 1db cx ax ld 1CH 1DH 1CH 1DH load location 1CH with value 1DH ldb 40H 1CH temp 1DH save 1DH conte
10. rocontroller Specification Update 13 _ Specification Clarifications l ntel i Workaround Status 14 where both the capture buffer and the EPAx_TIME register contain data and no EPA interrupt pending bit is set an input signal with a frequency high enough to cause overruns is present on an enabled EPA pin and the overwrite bit is set EPAx_CON 0 1 old data is overwritten on overrun and the EPAx TIME register is read at the exact instant that the EPA recognizes the captured edge as valid The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors Unless the interrupt service routine includes a check for overruns this situation will remain the same until the device is reset or the EPAx_TIME register is read The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME This clears the buffer and allows another event to be captured Remember that the act of transferring the buffer contents to the EPAx_TIME register is what actually sets the EPAx interrupt pending bit and generates the interrupt Any one of the following methods can be used to prevent or recover from an EPA overrun situation Clear EPAx_CON 0 When the overwrite bit EPAx CON 0 is zero and both the EPAx TIME register than the buffer are full the EPA does not consider a captured edge until the EPAx TIME register is read and the data in the capture buffer is tr
11. structions function correctly with count values 0 31 inclusive However a shift count value of XX100000B causes 32 shifts which results in no shift taking place With all other count values the upper 3 bits are masked off and the remaining bits specify the number of shifts Also a shift count value of XX1XXXXXB causes the overflow flag and the overflow trap flag to be set Customers using SHRL and SHLL instructions with a count value greater than 31 will be affected Ensure that the count value never exceeds 31 Refer to Summary Table of Changes to determine the affected stepping s Port 4 Address Behavior For bus timing modes 1 and 2 specified only on the 87C196KS C step port 4 does not retain the address during the data portion of the bus cycle Designs using an 8 bit external memory system in bus mode 1 or mode 2 require an external latch on port 4 to retain the address during the data portion of the bus cycle Designs using an 8 bit external memory system in mode 0 or mode 3 do not require an external latch Designs using 16 bit external memory systems require external latches on both port 3 and port 4 in all bus timing modes EPA Overruns The EPA can lock up if overruns are handled incorrectly Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA interrupt service routine If no overrun handling strategy is in place and if the following three conditions exist a situation may occur 87C196KT Mic
12. t specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1998 Third party brands and names are the property of their respective owners 87C196KT Microcontroller Specification Update intel Contents Revision History uussmevuespundksteamnt i viniebnsjmsmgtbl et 5 ENE eS A EE EE EE 6 Summary Table of Changes rnnnnnnnnnnrvnnnnnnnnnnnnnrrnnnnnnnrnnrrnnnnnnnnnnnnrnnnessennn 8 Identification Information sssonororrnnnnrnnnnnrrrnnnnnrnnnrrnnnnnnnannnnrrnnnnnnnnnnnnennn 10 EE cdaarsdceem ee E 11 Specification Changes rrrrnnnnvnnnnnnnnnnvvnnnnnnnnnnnnnnnnnnnnnnnannnnnnnnannnnnnneneenee 12 Specification Clarifications ccccccceccceeeeeeeeeeeeeeeeneeeeeeeeeeeeeneeeeeeeeeeenaees 13 Documentation Changes ennrnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnenennnnnnnvennnnnennnnnn 17 87C196KT Microcontroller Specification Update intel Revision History Revision History Date Version Description 11 11 98 004 Added errata 2 04 07 97 003 Added errata 1 01 08 96 002 Added documentation change 1 3 This is the new Specification Update document It contains all identified errata 07 01 36 001 published prior to this date 87C196KT Microcontrol
13. te 12 87C196KT Microcontroller Specification Update intel Specification Clarifications Specification Clarifications 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem Implication Workaround Status 6 Problem Fa Problem EPA Timer Reset Write Conflict If software writes to the EPA timer at the same time that an EPA channel resets that timer it is indeterminate which action will take precedence Software should not write to a timer that is being reset by EPA signals Valid Time Matches A timer must increment or decrement to the compare value in order for a match to occur Loading a timer with a value that is equal to an EPA compare value does cause a match Likewise with an EPA compare value of 0 a timer reset does not cause a match P6_REG 4 7 Not Updated Immediately A value written to any of the upper four bits of P6_REG is temporarily held in a buffer until the corresponding P6 MODE bit is cleared at which time the value is loaded into the P6 REG bit A value read from a P6_REG bit is the value currently in the register not the value in the buffer Therefore any change to a P6 REG bit can be read only after the corresponding P6 MODE bit is cleared Write Cycle During Reset If a reset occurs while the microcontroller is writing to an external memory device the contents of the external memory device may be corrupted Indirect Shift Count Value The SHRL and SHLL in
14. y given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification Note Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc 87C196KT Microcontroller Specification Update 7 E Summary Table of Changes l ntel Summary Table of Changes The following table indicates the errata specification changes specification clarifications or documentation changes which apply to the Product Name product Intel may fix s
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