VTOS DDR (QorIQ P4/P5) Addendum
Contents
1. Specifies the value written to the DDRx DDR ZQ CNTL register Specifies the value written to the DDRx DDRCDR 1 register Example QorlQ P5 register settings are shown below In this example only the DDR2 controller is configured FALSE gt ddri enabled TRUE gt ddr2 enabled 0xeoo000FF gt ddr2 csO bnds 0xei10001FF gt ddr2 csi bnds 0x00000000 gt ddr2 cs2 bnds 0x00000000 gt ddr2 cs3 bnds 0x80044402 gt ddr2 csO0 config 0x80044402 gt ddr2 csi config 0x00000000 gt ddr2 cs2 config 0x00000000 gt ddr2 cs3 config 0x00000000 gt ddr2 csO0 config 2 0x00000000 gt ddr2 csi config 2 0x00000000 ddr2 cs2 config 2 0x00000000 ddr2 cs3 config 2 OxE7040000 gt ddr2 config 0x24401110 ddr2 config 2 0x0e0000000 gt ddr2 rcw 1 0x00000000 gt ddr2 rcw 2 Copyright Kozio Inc 2014 17 Ah koZi0 wv AN130 VTOS DDR QorlQ P4 P5 Processor Addendum 0x00441c70 gt ddr2 mode 0x00180000 gt ddr2 mode 2 0x00001c70 gt ddr2 mode 3 0x00180000 gt ddr2 mode 4 0x00001c70 gt ddr2 mode 5 0x00180000 gt ddr2 mode 6 0x00001c70 gt ddr2 mode 7 0x00180000 gt ddr2 mode 8 0x18600100 gt ddr2_interval 0x02800000 gt ddr2 cLR cntL 0x8675f608 gt ddr2_wrlvl_cntl exeoo00000 gt ddr2_wrlvl_cntl_2 exeoo00000 gt ddr2 wrlvL cntL 3 0x50550104 gt ddr2 timing cfg 0O xbcb58c56 ddr2 timing cfg 1 OxOfcOc8d2. Click Next to display the Import Projects dialog 4 Import the VTOS DDR project a From the Import Projects dialog select the Select archive file radio button and click Browse Import Projects Select a directory to search for existing Eclipse projects Select root directory Q Select archive file Projects Browse Copyright Kozio Inc 2014 Deselect All dh KOZIO b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum b Inthe File name field enter SKOZIO VTOS DDR HOMESNetc and click Open Select archive containing the projects to import JOQ J keith codewarrior workspace gt v Search codewarrior_wor 2 Organize New folder A Favorites Name Date modified Type WE Desktop JL metadata 2 17 2015 815 AM File folder J Downloads Recent Places I Libraries 3 Documents Music Pictures B videos vil ES m File name KAKOA OMALADINA jar zip tar targz tgz v aR Lie manereun c Now select the correct CodeWarrior project archive for the processor family you are using Select the file cwide vtos ddr p4 tgz orcwide vtos ddr p5 tgz when using a QorlQ P4 or QorlQ P5 processor respectively Click Open F Select archive containing the projects to import QGO gt keith Kozio VTOS DDR etc s f Search etc Organize 7 New folder
3. for additional information about loading ELF and SREC file types Copyright Kozio Inc 2014 O VTOS DDR HOMES directory for the QorlQ Ah n aKozio x AN130 VTOS DDR QorlQ P4 P5 Processor Addendum DDR Board Files Please see the VTOS DDR User manual for a detailed description on how to create and use board files This document details the parameters that are specific to the QorlQ P4 P5 processor family Tip When first determining valid DDR settings for a board design it is recommended that you disable ECC and the data initialization features of the DDR controller If the DDR settings are not stable enabling ECC or the data initialization features can cause the QorlQ P4 P5 processor to hang Once you have settings that pass all DDR tests with ECC disabled then you can enable ECC and re run the DDR configuration and tests Timing Based Files In the current release of VTOS DDR for the QorlQ P4 P5 family Timing Based board files are not supported You must use a register based board file Register Based Files Use a Register Based DDR board file if you want to explicitly specify all register values programmed into the DDR controllers of the QorlQ P4 P5 processor VTOS DDR supports configuring the DDR1 controller the DDR2 controller or configuring both DDR controllers in the QorlQ P4 P5 processor When both DDR controllers are enabled VTOS DDR automatically detects whether controller interleaving is enabled and configure
4. Base OxF FE000000 physical address OxFEO00000 virtual address Using Freescale CodeWarrior Development Studio The VTOS DDR installation includes example projects for CodeWarrior Development Studio that you use to configure the CPC memory load the VTOS DDR firmware image and start the processor execution The example projects are located under the default installation directory KOZIO VTOS DDR HOMES Netc CodeWarrior Development Studio Walkthrough 1 Download and install CodeWarrior Development Studio for Power Architecture from Freescale Note that you will need to purchase a license from Freescale in order to run CodeWarrior Development Studio past the evaluation period 2 Launch CodeWarrior Development Studio Copyright Kozio Inc 2014 3 d b atozio b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum a Ifthis is the first time you have started CodeWarrior Development Studio you will be presented with the Welcome Screen as shown below File Edit Source Refactor Navigate Search Project Run Window Help e New Project Wizard lt gt What s New Product Release Notes Project Importer e Web Resources Service Packs Updates Patches ee Example Projects Tutorials L Go to Workbench Copyright Kozio Inc 2014 4 d b KOZIO b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum b Click on Go to Workbench to display the C C perspective as shown below rv G GO S 2 Fvliv RvB
5. E I9 x Favorites Name Date modified Type EE Desktop 8 cwide_vtos_ddr_p4 tgz 2 17 2015 8 08 AM tgz Archive J Downloads a cwide_vtos_ddr_p5 tgz 2 17 2015 8 08 AM tgz Archive lt gt Recent Places 7 I Libraries LJ lt 4 Documents Music Pictures A Videos adb Unmanraun vA u r File name cwide_vtos_ddr_p4 tgz v jar zip tar targz tgz v Copyright Kozio Inc 2014 7 Ah atozio b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum d The Import dialog should now show the VTOS DDR project under the Projects view Ensure the VTOS DDR project is selected and click Finish 3 import Import Projects Select a directory to search for existing Eclipse projects Select root directory Browse Q Select archive file C Users keith Kozio VTOS_DDR etc cwide_vtos_ddr_ Browse Projects VTOS DDR P4080 VTOS DDR P4080 Deselect All 4 Copy projects into workspace Working sets C Add project to working sets Working sets v Select Finish Came Copyright Kozio Inc 2014 8 d b KOZIO b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum e The VTOS DDR project should now be shown under the CodeWarrior Projects tab File Edit Source Refactor Navigate Search 2 1874 oF Ej 1 wow Y Cp ow Na jects 3 a a B SP File Name File Name Size Type p u 5 The final configurati
6. MHz SYSCLK source raw binary format VTOS DDR Firmware image for P5 boards using an 83 MHz SYSCLK source ELF object file format VTOS DDR Firmware image for P5 boards using an 83 MHz SYSCLK source SREC file format VTOS DDR Firmware image for P5 boards using a 100 MHz SYSCLK source raw binary format VTOS DDR Firmware image for P5 boards using a 100MHz SYSCLK source ELF object file format VTOS DDR Firmware image for P5 boards using a 100MHz SYSCLK source SREC file format VTOS DDR Firmware image loaded by the VTOS DDR application The VTOS DDR application always uses this file regardless of whether your P5 board uses an 83 MHz CLKIN or a 100 MHz SYSCLK source Select the VTOS DDR firmware image that matches processor type and the SYSCLK setting for your board The general process for loading and executing the VTOS DDR firmware image is as follows 1 Configure CPC memory as SRAM as described in the previous section 2 Loadthe VTOS DDR firmware image into SRAM The load address is OXFFFO 0000 if using a raw binary file 3 Change the program counter PC register to the VTOS DDR firmware entry point OXFFFO 4000 This step is optional when loading ELF or SREC files 4 Resume operation of the processor It is recommended that use your JTAG debugger to load either an ELF file or an SREC file Both of these file types provide load address information and start address information Consult your JTAG debugger documentation
7. configured as SRAM before attempting to load the VTOS DDR firmware image onto a QorlQ P4 or QorlQ P5 Follow the instructions below to enable CCSR register space access and to configure the CPC CoreNet Platform Cache memory as SRAM The VTOS DDR installer provides an example JTAG configuration files for the BDI3000 debugger from Abatron under the SKOZIO_VTOS_DDR_HOME etc directory 1 Create a TLB1 entry to enable access to the CCSR Configuration Control and Status Register space The physical address of the CCSR space from reset is OxXO FEO0 0000 Register MASO MAS1 MAS2 MAS3 MAS7 MASA MAS5 MAS6 MASS8 Settings 0x10000000 0x80000500 OxFE00000A OxFE00003F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 CCSR TLB1 Initial Setting translate OXFEOO 0000 to Ox0 FEOO 0000 Field Description TLBSEL 1b select TLB1 ESEL 0x00 select TLB1 entry O V 1b TLB entry is valid TID 0x00 match all process IDs TS 0 TSIZE 0x5 1 MiB EPN OxFEOOOO Effective virtual address OXFE000000 1b Caching inhibited M Ob memory coherency not required G 1b Guarded memory E Ob big endian byte order RPN OxFEOOOO lower 32 bits of real address OxFEOOO000 Permissions Ox3F read write execute permission for user and supervisor RPN 0x0 upper 4 bits of real address Default value Default value Default value Default value 2 Write the DCFG BRR register with a value of 0x00
8. 000 0x00000000 CCSR TLB1 Final Setting translate OXFEOO 0000 to OxF_FEOO 0000 Field Description TLBSEL 1b select TLB1 ESEL 0x00 select TLB1 entry O V 1b TLB entry is valid TID 0x00 match all process IDs TS 0 TSIZE 0x7 16 MiB EPN OxFEOOOO Effective virtual address OXFE000000 1b Caching inhibited M 0b memory coherency not required G 1b Guarded memory E Ob big endian byte order RPN OxFEOOOO lower 32 bits of real address OXFE000000 Permissions Ox3F read write execute permission for user and supervisor RPN OxF upper 4 bits of real address Default value Default value Default value Default value 6 Create a TLB1 entry to access SRAM Register MASO MAS1 MAS2 MAS3 MAS7 Settings 0x10010000 0x80000500 OxFFF0000A 0x0000003F 0x00000008 Copyright Kozio Inc 2014 SRAM TLB1 Final Setting translate OXFFFO 0000 to Ox8 0000 0000 Field Description TLBSEL 1b select TLB1 ESEL 0x01 select TLB1 entry 1 V 1b TLB entry is valid TID 0x00 match all process IDs TS 0 TSIZE 0x5 1 MiB EPN OxFFFOOO Effective virtual address OxFFFO0000 1b Caching inhibited M 0b memory coherency not required G 1b Guarded memory E Ob big endian byte order RPN 0x000000 lower 32 bits of real address Ox00000000 Permissions Ox3F read write execute permission for user and supervisor RPN 0x8 upper 4 bits of real address 13 dh KOZI
9. 000001 to release core 0 from reset Write DCFG_BRR OxFEOEOOE4 0x00000001 3 Configure the CPC as SRAM by following this sequence This configures the CPC as SRAM for physical address Ox8 0000 0000 leaving space for up to 32 GiB of DDR memory Action Description Write CPC1 CPCCSRO OxFE010000 0x00200400 Flash invalidate the CPC and clear all locks Delay 500 microseconds to allow flash invalidate to complete Write CPC1 CPCHDBCRO OxFEO10F00 0x081E0000 Disable speculative read requests Write CPC1_CPCSRCR1 0xFE010100 0x00000008 SRBARU Ox4 Set the upper 4 bits of the SRAM base address to 0x8 Write CPC1_CPCSRCRO OxFE010104 0x0000000B SRBARL 0x0000 set lower 32 bits of SRAM base Copyright Kozio Inc 2014 address to 0x00000000 SRAMSZ 00101b SRAM size 1 MiB dh KOZIO WW AN130 VTOS DDR QorlQ P4 P5 Processor Addendum SRAMEN 1b SRAM mode enable 4 Move the CCSR base to physical address OxF_FEOO_OOOO Action Write LCC CCSRBARH OxFEO00000 0x0000000F Write LCC CCSRBARL OxFEO00004 OxFE000000 Write LCC CCSRAR OxFE000008 0x80000000 Description BASE ADDR HIGH OxF BASE ADDR LOW OxFEO00000 Commit 1 5 Modify the TLB1 entry created in step 1 to change the physical address of the CCSR to OxF FEOO 0000 Register MASO MAS1 MAS2 MAS3 MAS7 MASA MAS5 MAS6 MASS8 Settings 0x10000000 0x80000700 OxFE00000A OxFE00003F 0x0000000F 0x00000000 0x00000000 0x00000
10. 8 gt ddr2 timing cfg 2 0x010c1000 gt ddr2 timing cfg 3 0x00000001 gt ddr2 timing cfg 4 0x00001400 gt ddr2 timing cfg 5 OxDEADBEEF ddr2 data init 0x89080600 gt ddr2 zq cntL exseeooo00 gt ddr2 cdr 1 Tip When using a register based board file it is recommended that you copy one of the reference board register files provided under the directory KOZIO VTOS DDR HOMES boards qoriq p5 Copy and rename an example board file to the directory KOZIO VTOS DDR HOMES boards user DDR Clock Tuning The DDR controller provides two parameters that finely control the clocking on the DDR interface DDRx DDR SDRAM CLK CNTL CLK ADJUST and DDRx DDR WRLVL CNTL WRLVL START For a specific board design there is a range of values for both parameters that will operate successfully Freescale recommends that you identify all valid values for both parameters and then select the center value to provide the best margins VTOS DDR provides the command ddr tune clocks which automatically tries all possible settings for both the CLK ADJUST and WRLVL START parameters and then generates a report of the optimal settings found Executing the DDR Clock Tuning Once working settings for the DDR controller on your design are known run the command ddr tune clocks to find the valid operating window for the CLK ADJUST and WRLVL START parameters The command can take several minutes to complete Example output when run on the P5O
11. AORDB reference board from Freescale is shown below kozio ddr tune clocks Testing CLK ADJUST 5 Copyright Kozio Inc 2014 18 ch KOZIO wv AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Testing CLK ADJUST 5 WRLVL START 8 Configuring DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller DRAM data initialization is complete emory configuration complete memory size 8 GiB SDRAM Full burst 64 bit 00000000 00000000 00000000 OOffffff Passed Testing CLK ADJUST 5 WRLVL START 9 Configuring DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller DRAM data initialization is complete emory configuration complete memory size 8 GiB SDRAM Full burst 64 bit 00000000 00000000 00000000 OO0ffffff Passed Testing CLK ADJUST 5 WRLVL START 10 Configuring DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller DRAM data initialization is complete emory configuration complete memory size 8 GiB SDRAM Full burst 64 bit 00000000 00000000 00000000 OO0ffffff Passed output truncated Testing CLK ADJUST 6 WRLVL START 13 Configuring DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller DRAM data initialization is complete emory configuration complete memory size 8 GiB SDRAM Full burs
12. Application Note 130 VTOS DDR QorIQ P4 P5 Processor Addendum February 17 2015 P N KOZIO y Ah o aKozio Nw AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Table of Contents NJ 3 Loading the VTOS DDR image onto your board eee esses esee esee eee nennen nenas unn aaa a essen sens ana snas 3 Using Freescale CodeWarrior Development Studio eeeeeeeeee eese ee eee eene ee eene een totes nsns ensure n 3 Manually Configuring CPC Memory eee eee einen eee esee eene enne nnns nnn tat t nets sss sna nost tests sss sana seta nets essa naso 12 Loading VTOS DDR firmware images o s oo eo anao os ooa naa aea has oo sean RR SS SERERE See ERAN SNR S BERE Se NRR RSEN E Ea E aaa auES 14 EIE c 16 DI UDhr A LHIIPRHI nee 16 Register Based Files 5 toot to enean oo ean ia eua a E28 Goa eaa o RYE R RES EOS SEESE ERR Eoo E RR TENE REREDS S NR AN TNR Ros Ea saa saES 16 DDR COCK TORING T ESSE 18 Executing the DDR Clock T nihg wsis ccccccsccsccesesccesccceussasececnoscccacesssscesesccussdsaseesessecoadessssesensseaceesascecesnevccossases 18 Interpreting the tuning FreSUItS 5 cccccccsccsssossescecscscsssoeseedssscsscosssasad ssccscosssassasssscescsssasaassdsssscsssesaassesesssssssuaess 20 Additio
13. C C application field to the desired VTOS DDR firmware file Click Apply For more details on the firmware image available see the Loading VTOS DDR firmware images section Edit launch configuration properties Q Debug or run an application to a target Name VTOS DDR firmware download B Main Arguments Debugger Trace and Profile amp Source 88 Environment i Common Debug session type Es Choose a predefined debug session type or custom type for maximum flexibility Download Connect Attach Custom C C application Project VTOS DDR P4080 Browse Application KOZIO_VTOS_DDR_HOME vtos gorig_p4_ddr clkin_100 elf Search Project Browse Variables gt Build if required before launching d Tochange the CodeWarrior connection type select the Main tab and under Target Settings select Edit Edit launch configuration properties Q Debug or run an application to a target Name VTOS DDR firmware download B Main _ 9 Arguments ka Debugger Trace and Profile Source BS Environment l E Common Debug session type il Choose a predefined debug session type or custom type for maximum flexibility Download Connect D Attach Custom C C application Project VTOS DDR P4080 Browse a Application S KOZIO VTOS DDR HOME Wtos qoriq p4 ddr clkin 100 elf S
14. DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller Once the DDR clock tuning procedure completes update your board file with the optimum values reported Note that some combinations of the CLK ADJUST and WRLVL START parameters can cause a hard hang in the QorlQ P5 processor If this happens please reset your board reload your board file and try the clock tuning procedure again Interpreting the tuning results Run the command tuning map to display the results from the last execution of the DDR clock tuning kozio tuning map WRLVL START 0 4 8 12 16 20 24 28 CLK ADJ 0x00 0000 0000 0000 0000 0000 0000 0000 0000 0x01 0000 0000 0000 0000 0000 0000 0000 0000 0x02 0000 0000 0000 0000 0000 0000 0000 0000 0x03 0000 1111 1100 0000 0000 0000 0000 0000 0x04 0000 0011 1110 0000 0000 0000 0000 0000 0x05 0000 0111 1111 0000 0000 0000 0000 0000 0x06 0000 0000 1111 1000 0000 0000 0000 0000 0x07 0000 0001 1111 1000 0000 0000 0000 0000 0x08 0000 0000 0000 0000 0000 0000 0000 0000 Optimal setting CLK ADJUST 5 WRLVL START 8 If using a timing based file copy and paste the following lines into your board file 5 gt ddr memctrl clk adjust 8 gt Sddr memctrl wrlvl start If using a register based file copy and paste the following lines into your board file 0x02800000 gt S ddr2 clk cntl 0x8675F608 gt Sddr2 wrlvl cntl Each row of the tuning map corresponds to a si
15. DRAM MODE 4 register ddrx mode 5 Specifies the value written to the DDRx DDR SDRAM MODE 5 register ddrx mode 6 Specifies the value written to the DDRx DDR SDRAM MODE 6 register ddrx mode 7 Specifies the value written to the DDRx DDR SDRAM MODE 7 register ddrx mode 8 Specifies the value written to the DDRx DDR SDRAM MODE 8 register ddrx intervaL Specifies the value written to the DDRx DDR SDRAM INTERVAL register ddrx cLR cntL Specifies the value written to the DDRx DDR SDRAM CLK CNTL register ddrx wrlvL cntL Specifies the value written to the DDRx DDR WRLVL CNTL register ddrx wrlvL cntL 2 Specifies the value written to the DDRx DDR WRLVL CNTL 2 register ddrx wrlvL cntL 3 Specifies the value written to the DDRx DDR WRLVL CNTL 3 register ddrx timing cfg 0 Specifies the value written to the DDRx TIMING CFG Oregister ddrx timing cfg 1 ddrx timing cfg 2 Specifies the value written to the DDRx TIMING CFG 1 register Specifies the value written to the DDRx TIMING CFG 2 register ddrx timing cfg 3 Specifies the value written to the DDRx TIMING CFG 3 register ddrx timing cfg 4 ddrx timing cfg 5 Specifies the value written to the DDRx_TIMING_CFG_4 register Specifies the value written to the DDRx TIMING CFG 5 register ddrx data init Specifies the value written to the DDRx DDR DATA INIT register ddrx zq cntL ddrx cdr 1
16. Gr livery H rOvrawr esy amp Ei c c 8 1 E CodeWarrior Project x 7 O O 20u XN OM B amp SPI File Name v An outline is not available File Name Size Type Project Creation s Import project Y CodeWarrior Bareboard Proje Build Debug EL Problems 2 A Tasks E Console 1 Properties a Remote Systems Ez v el 0 items Description Resource Location 3 Import a VTOS DDR download project This can be done in one of two ways a Method 1 Click on the Import project icon in the Command window as shown below to display the Import Projects dialog proceed to step 4 Project Creation s Import project Y CodeWarrior Barehaard Proje ALT BI v Build Debug 9 f Copyright Kozio Inc 2014 5 dh kozio WwW AN130 VTOS DDR QorlQ P4 P5 Processor Addendum b Method 2 Select File gt Import Project to bring up the Import dialog Expand the General folder and select Existing Projects into Workspace Import Select Create new projects from an archive file or a directory Select an import source type filter text 4 amp General 5 Archive File Existing Projects into Workspace C3 File System E Preferences gt amp C C gt amp CodeWarrior gt amp CVS gt amp Install Finish
17. O WW MAS4 0x00000000 Default value MAS5 0x00000000 Default value MAS6 0x00000000 Default value MASS8 0x00000000 Default value 7 Create a local access window LAW for SRAM Action Write LAW LAWBARHO OxFEOO00COO 0x00000008 Write LAW LAWBARLO OxFEOO00CO04 0x00000000 Write LAW LAWARO OxFE010100 0x81000013 8 Final step enable the CPC Action Write CPC1 CPCCSRO OxFE010000 0x80000000 AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Description BASE_ADDR_HIGH 0x8 BASE_ADDR_LOW 0x00000000 EN 1b enable local access window TRGT_ID 0x10 target identifier memory complex 1 CSC_ID 0x00 SIZE 0x13 1 MiB Description CPCE 1 enable the CPC array as cache or memory mapped SRAM Note that the process for creating TLB1 entries varies for each JTAG debugger Consult your JTAG debugger documentation for additional information You can verify CPC has been correctly configured for SRAM by using your JTAG debugger to read and write memory starting at address OxFFFO 0000 Loading VTOS DDR firmware images After configuring the CPC memory as SRAM on your QorlQ P5 platform you are ready to load the VTOS DDR firmware image into the CPC memory The VTOS DDR installer provides the following files under KOZIO VTOS DDR HOMES directory for the QorlQ P4 processor family Filename Description 83 MHz SYSCLK Files vtos qoriq p4 ddr clkin 83 bin VTOS DDR Firmware image for P4 boards using an 83 MHz SYSCLK sou
18. RLVL START 9 output truncated Testing CLK ADJUST 7 WRLVL START 12 Configuring DDR3 memory controller Command aborted returning to main task kozio tuning map WRLVL START 0 4 8 12 16 20 24 28 CLK ADJ 0x00 0000 0000 0000 0000 0000 0000 0000 0000 0x01 0000 0000 0000 0000 0000 0000 0000 0000 0x02 0000 0000 0000 0000 0000 0000 0000 0000 0x03 0000 0000 0000 0000 0000 0000 0000 0000 0x04 0000 0000 0000 0000 0000 0000 0000 0000 0x05 0000 0111 1111 0000 0000 0000 0000 0000 0x06 0000 0000 1111 1000 0000 0000 0000 0000 0x07 0000 0000 0000 0000 0000 0000 0000 0000 0x08 0000 0000 0000 0000 0000 0000 0000 0000 Optimal setting CLK ADJUST 5 WRLVL START 8 If using a timing based file copy and paste the following lines into your board file 5 gt ddr memctrl clk adjust 8 Sddr memctrl wrlvl start If using a register based file copy and paste the following lines into your board file 0x02800000 gt ddr2 clk cntl 0x8675F608 gt Sddr2 wrlvl cntl Copyright Kozio Inc 2014 21 t b i KOZIO Ww AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Additional Contact Information Kozio Inc 1 303 776 1356 x1 sales kozio com www kozio com http www kozio com About Kozio Inc Kozio Inc provides software solutions delivering Embedded Verification IP refined over the years Kozio s Verification and Test OS VTOS is targeted for a specific SoC VTOS provides a verification plat
19. earch Project Browse Variables i Build if required before launching I Target settings Connection 4 P4080 Download VTOS DDR td New Execute reset sequence Execute initialization script s The ennnertinn ic for a multicnre tarnet Dleace celert a care nr miiltinle cnrec in the race nf SMD Copyright Kozio Inc 2014 10 Ah KOZIO b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum e Click the Connection type pull down to select a different hardware connection type Hardware or Simulato Hardware or Simulator Connection HIC Ad Sr Parent profile MERLIN2 Name P4080 Download VTOS DDR Description Connection to P4080 using CodeWarrior USB Tap Template None Apply Defaults Target E P4080 Download VTOS DDR Target ti Ne CCSSIM2 ISS CodeWarrior TAP Connection LAd Ethernet TAP USB TAP Gigabit TAP Trace i n NI USB serial n aa d imics TCF JTAG settings USB TAP JTAG clock s i 7 Tolaunch the VTOS DDR firmware image select Run gt Run Configurations In the left hand pane select CodeWarrior gt VTOS DDR firmware download and click Run Create manage and run configurations Q Debug or run an application to a target E E x oi Name VTOS DDR firmware download type hiter don E Main Arguments Debugger amp Trace and Profile amp Source 88 Environment E C
20. form with deterministic test results low level commands for direct hardware access and built in system level tests It is a light weight easily configurable bare metal verification platform VTOS is a reusable SoC verification solution for RTL simulation emulation prototyping virtualization and first articles For board level verification and validation VTOS provides at speed functional test tools and high speed programming tools used to quickly verify new embedded designs for design correctness and to quickly validate product during production runs Quickly identify and troubleshoot hardware failures with direct hardware access and a powerful scripting language Kozio products extend coverage provide fast booting fast test execution and high speed programming saving up to 75 of your test program development costs 2014 Kozio Inc All rights reserved Kozio VTOS Integration Workbench and vAccess are trademarks or registered trademarks of Kozio Inc All other trademarks and products are the property of their respective owners Copyright Kozio Inc 2014 22
21. nal Contact INJOMNGHON Mem 22 ADOUE KOZIO UN Ciiecssccssssecivcctessceocseseuebasnuetaevchsnseelaceuuedseunueseuscesuavnsesdisebevsucbandeussatusssenseccegsarsiusbavesdiivess 22 Copyright Kozio Inc 2014 2 Ah o KOZIO Nw AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Overview This addendum describes the VTOS DDR features specific to the QorlQ P4 and QorlQ P5 processor families manufactured by Freescale The QorlQ P4 processor is based on the e500mc microprocessor core and runs in 32 bit mode only The e500mc microprocessor supports a 36 bit physical address space The QorlQ P5 processor is based on the e5500 microprocessor core capable of running in 32 bit mode or 64 bit mode The e5500 microprocessor supports a 36 bit physical address space The VTOS DDR firmware image only supports 32 bit operation of the e5500 microprocessor core For both microprocessor core types the VTOS DDR firmware enables the Memory Management Unit MMU and supports testing of the entire 36 bit address space up to 64 GiB of memory Loading the VTOS DDR image onto your board The VTOS DDR image is configured to run directly from the CoreNet platform cache CPC memory of the QorlQ P4 and QorlQ P5 The default interface used for communication is through the UART1 SOUT and UART1 SIN pins on the processor VTOS DDR Image Information QorlQ P4 P5 Load Address OxFFF00000 Entry Point OxFFFO4000 also specified by the ELF file CCSR
22. ngle setting of the CLK ADJUST parameter At each CLK ADJUST setting VTOS DDR tries all possible settings for the WRLVL START parameter At each combination of CLK ADJUST and WRLVL START if configuration of the DDR memory controllers was successful and the memory test passed the map displays a 1 If configuration failed or the memory test failed the map displays a 0 Copyright Kozio Inc 2014 20 Ah KOZIO Ww AN130 VTOS DDR QorlQ P4 P5 Processor Addendum In the example above VTOS DDR determined that CLK ADJUST settings of 3 7 had atleast one WRLVL START setting that passed all tests VTOS DDR then selects CLK ADJUST setting of 5 as the middle of the CLK ADJUST window Atthe CLK ADJUST setting of 5 the WRLVL START operating window is from setting 5 to 11 with the middle of the window at 8 Even on incomplete runs of the DDR clock tuning you can retrieve the results from the clock parameter search In the example below the DDR clock tuning was prematurely halted by typing CTRL C in the VTOS DDR command console kozio ddr tune clocks Testing CLK ADJUST 5 Testing CLK ADJUST 5 WRLVL START 8 Configuring DDR3 memory controller Creating local access window for DDR2 Enabling the DDR2 controller DRAM data initialization is complete emory configuration complete memory size 8 GiB SDRAM Full burst 64 bit 00000000 00000000 00000000 OOffffff Passed Testing CLK ADJUST 5 W
23. ommon E CodeWarrior Debug session type VTOS DDR firmware dc Choose a predefined debug session type or custom type for maximum flexibility Launch Group mn Q Download Connect KB Target Communication Fr Attach Custom C C application Project VTOS DDR P4080 V Application S KOZIO VTOS DDR HOME wtos qoriq p4 ddr clkin 83 elf Search Project gt Build if required before launching Target settings Connection P4080 Download VTOS DDR 7 Execute reset sequence Execute initialization script s lt uw The connection is for a multicore target Please select a core or multiple cores in the case of SMP Filter matched 4 of 4 items Target Filter by Project Z P4080 I i2 VTOS DDR P4080 8 Confirm that the VTOS DDR firmware image started Launch the VTOS DDR application and Copyright Kozio Inc 2014 11 dh kozIio WW AN130 VTOS DDR QorlQ P4 P5 Processor Addendum Manually Configuring CPC Memory When the QorlQ P4 or P5 processor is brought out of reset the processor operates in 32 bit mode and only the last 4 KiB of the 32 bit address map is accessible address range OxFFFF_FOOO to OxFFFF FFFF This means that out of reset the CCSR Configuration Control and Status Register register space is not accessible In addition the CoreNet Platform Cache is disabled and must be
24. on step is to verify the VTOS DDR Debug Run settings By default the project is configured as follows If your CodeWarrior hardware and board settings match those listed above proceed to step 7 a Connection type USB TAP b C C download application VTOS DDR firmware image for boards using a 100 MHz SYSCLK vtos qoriq p4 ddr clkin 100 elf or vtos qoriq p5 ddr clkin 100 elf 6 Optional step changing the VTOS DDR firmware image or changing the connection type a Select Project gt Properties Run Window Help Open Project Close Project 4 Build All Ctrl B Build Configurations r Build Project Build Working Set gt Clean Build Automatically Make Target gt Generate Makefiles Ctrl 6 Properties Copyright Kozio Inc 2014 9 d b aozio b AN130 VTOS DDR QorlQ P4 P5 Processor Addendum b Select Run Debug Settings in the left hand pane select the VTOS DDR firmware download launch configuration in the right hand pane and click Edit Properties for VTOS DDR lak type filter text Run Debug Settings VTOS DDR P4080 civ as Resource Builders This page allows you to manage launch configurations associated with the currently selected resource C C Build Launch configurations for VTOS DDR P4080 C C General ia VTOS DDR firmware download New Run Debug Settings Duplicate Delete Edit se c Tochange the VTOS DDR firmware file select the Main tab and modify the
25. pecifies the value written to the DDRx CS2 CONFIG register ddrx cs3 config Specifies the value written to the DDRx CS3 CONFIG register ddrx csO config 2 Specifies the value written to the DDRx CSO CONFIG 2 register ddrx cs1 config 2 Specifies the value written to the DDRx CS1 CONFIG 2 register ddrx cs2 config 2 Specifies the value written to the DDRx CS2 CONFIG 2 register ddrx cs3 config 2 Specifies the value written to the DDRx CS3 CONFIG 2 register Copyright Kozio Inc 2014 16 dh KOZIO WW AN130 VTOS DDR QorlQ P4 P5 Processor Addendum ddrx config Specifies the value written to the DDRx DDR SDRAM CFG register ddrx config 2 Specifies the value written to the DDRx DDR SDRAM CFG 2 register ddrx rcw 1 Specifies the value written to the DDRx_DDR_SRAM_RCW_1 register Note that this register is only used with registered DIMMs and if the DDR SRAM CFG 2 RCW EN field is enabled ddrx rcw 2 Specifies the value written to the DDRx DDR SRAM RCW 2 register Note that this register is only used with registered DIMMs and if the DDR SRAM CFG 2 RCW EN field is enabled ddrx mode Specifies the value written to the DDRx DDR SDRAM MODE register ddrx mode 2 Specifies the value written to the DDRx DDR SDRAM MODE 2 register ddrx mode 3 Specifies the value written to the DDRx DDR SDRAM MODE 3 register ddrx mode 4 Specifies the value written to the DDRx DDR S
26. rce raw binary format vtos qoriq p4 ddr clkin 83 elf VTOS DDR Firmware image for P4 boards using an 83 MHz SYSCLK source ELF object file format vtos qoriq p4 ddr clkin 83 srec VTOS DDR Firmware image for p4 boards using an 83 MHz SYSCLK source SREC file format 100 MHz SYSCLK Files vtos qoriq p4 ddr clkin 100 bin VTOS DDR Firmware image for P4 boards using a 100 MHz SYSCLK source raw binary format vtos qoriq p4 ddr clkin 100 elf VTOS DDR Firmware image for P4 boards using a 1OOMHz SYSCLK source ELF object file format vtos qoriq p4 ddr clkin 100 srec VTOS DDR Firmware image for P4 boards using a 1OOMHz SYSCLK source SREC file format Copyright Kozio Inc 2014 14 dh KOZIO WW Common Files vtos qoriq p4 ddr elf The VTOS DDR installer provides the following files under KOZ1 P5 processor family Filename 83 MHz SYSCLK Files vtos qoriq p5 ddr clkin 83 bin vtos qoriq p5 ddr clkin 83 elf vtos qoriq p5 ddr clkin 83 srec 100 MHz SYSCLK Files vtos qoriq p5 ddr clkin 100 bin vtos qoriq p5 ddr clkin 100 elf vtos qoriq p5 ddr clkin 100 srec Common Files vtos qoriq p5 ddr elf AN130 VTOS DDR QorlQ P4 P5 Processor Addendum VTOS DDR Firmware image loaded by the VTOS DDR application The VTOS DDR application always uses this file regardless of whether your P4 board uses an 83 MHz CLKIN or a 100 MHz SYSCLK source Description VTOS DDR Firmware image for P5 boards using an 83
27. s the Local Access Window to match the interleaving setting Two variables control whether a DDR controller is initialized ddr1 enabled and ddr2_enabLed VTOS DDR provides two sets of variables to initialize all DDR controller registers Variables used to initialize the DDR1 controller are prefixed with ddri_ and variables used to initialize the DDR2 controller are prefixed with ddr2 The table below lists all parameters required on the QorlQ P5 processor For all variables listed below replace x with either 2 or 2 to configure the DDR1 and DDR2 controllers respectively Parameter Description ddri enabLed Set to TRUE if your board connects DDR memory chips to the DDR1 memory controller Set to FALSE if the DDR1 memory controller is not used by your board ddr2 enabLed Set to TRUE if your board connects DDR memory chips to the DDR2 memory controller Set to FALSE if the DDR2 memory controller is not used by your board ddrx_cs _bnds Specifies the value written to the DDRx CSO BNDS register ddrx cs1 bnds Specifies the value written to the DDRx CS1 BNDS register ddrx cs2 bnds Specifies the value written to the DDRx CS2 BNDS register ddrx cs3 bnds Specifies the value written to the DDRx CS3 BNDS register ddrx csO config Specifies the value written to the DDRx CSO CONFIG register ddrx csi config Specifies the value written to the DDRx_CS1_CONFIG register ddrx cs2 config S
28. t 64 bit 00000000 00000000 00000000 OO0ffffff 6 tac Sa ene bs E Me be Be Bad value at address 0x00000000_00000c80 expected 0x00000000_00000c80 actual 0x00000200_00000c80 Too many memory errors detected gt 256 errors ending test Test failed with error code 0x00080030 FAILED output truncated TEE HEH EH HE HEH HE EE ER HE EE EE EEE EE HE ERE HE ERE E EH CLK_ADJUST and WRLVL_START tuning completed TEE ERE EEG HE EE EE HE EE ERE HE HE HE EE ERE EE HH EE HE ERE HEH EH WRLVL_START 0 4 8 12 16 20 24 28 CLK_ADJ 0x00 0000 0000 0000 0000 0000 0000 0000 0000 0x01 0000 0000 0000 0000 0000 0000 0000 0000 0x02 0000 0000 0000 0000 0000 0000 0000 0000 Copyright Kozio Inc 2014 19 dh R KOZIO Ww AN130 VTOS DDR QorlQ P4 P5 Processor Addendum 0x03 0001 1111 1100 0000 0000 0000 0000 0000 0x04 0000 0011 1110 0000 0000 0000 0000 0000 0x05 0000 0111 1111 0000 0000 0000 0000 0000 0x06 0000 0000 1111 1000 0000 0000 0000 0000 0x07 0000 0001 1111 1100 0000 0000 0000 0000 0x08 0000 0000 0000 0000 0000 0000 0000 0000 Optimal setting CLK ADJUST 5 WRLVL START 8 If using a timing based file copy and paste the following lines into your board file 5 gt ddr memctrl clk adjust 8 gt S ddr memctrl wrlvl start If using a register based file copy and paste the following lines into your board file 0x02800000 gt ddr2 clk cntl 0x8675F608 gt S ddr2 wrlvl cntl Configuring
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