M16C Family, R8C Family I2C-bus Interface Using UARTi Special
Contents
1. I Transmit data T UiTB register 01XXh Release Hi Z Figure 5 2 Byte Data Transmission REJ05B1349 0102 Rev 1 02 134 NE SAS Page 11 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 5 2 Byte Data Reception When receiving byte data the SDAi pin is released for the first to eighth bits to receive data and an acknowledgement is generated for the ninth bit NACK is generated as an acknowledgement when the last byte data is received in master mode or when the slave address does not match in slave mode In all other cases ACK is generated In 12C mode by setting 9 bit data to the UiTB register data can be received and an acknowledgment can be generated In 9 bit data set FFh to bits b7 to bO to release the SDAi pin and set bit b8 to 0 to generate ACK or 1 to generate NACK By setting OOFFh or 01FFh as 9 bit data to the UiTB register the SDAi pin becomes high impedance for the first to eighth bits and data can be received ACK or NACK is generated for the ninth bit depending on the setting The received data can be read from the UiRB register When the clock delay function is used data transfer to the UiRB register occurs twice and each UiRB register value is different Refer to 4 3 CKPH Bit Setting Clock Delay for details UARTi Transmit Buffer Register UiTB b15 b8 b7 Set these bits to 1 to release the SDA pin2. 0 ACK generated 1 NACK generated Figure 5 3 UiTB Register Setting ACK Receiver SDA Release Hi Z ACK generated low level UiTB register 00 NACK Receiver SDA Release Hi Z d UiTB register 01FFh NACK generated Hi Z Figure 5 4 Byte Data Reception REJ05B1349 0102 Rev 1 02 134 NE SAS Page 12 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 5 3 SWC Bit and SWC9 Bit Settings SCL Wait Function To secure the necessary amount of time for generating an acknowledgement or preparing data the SCL wait function forces other devices to wait Use the SCL wait function in slave mode Set the SWC bit in the UISMR2 register to insert a wait for acknowledgement generation When the SWC bit is 1 after 8 bit receive SCLi pin low hold the SCLi pin becomes fixed low at the falling edge of the eighth bit of the SCL clock When the SWC bit is set to 0 disabled the SCLi pin is released Set the SWC9 bit in the UISMR4 register to insert a wait to judge the received acknowledgement When the CKPH bit in the UiISMR4 register is 1 with clock delay and the SWC9 bit is set to 1 after 9 bit receive SCLi pin low hold the SCLi pin becomes fixed low at the falling edge of the ninth bit of the SCL clock When the SWC9 bit is set to 0 SCL low hold disabled the SCLi pin is released Refer to 7 2 Receive Transmit Interrupts for
3. Page 16 of 23 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 7 2 1 Receive Interrupt A receive interrupt is generated at the falling edge of the eighth bit of the SCL clock When the CKPH bit in the UISMR3 register is 1 with clock delay by reading the UiRB register in the receive interrupt handler the bit position of the received data is changed see Figure 4 3 Clock Delay Function Examples of receive interrupt handling are below Additional processing can be added as needed Slave transmission and reception 1 First byte slave address Read the slave address When slave address is matched Generate ACK ACKD is 0 ACKC is 1 Fix SCL low after receiving 9 bits SWC9 is 1 Release SCL after receiving 8 bits SWC is 0 When slave address does not match Generate NACK ACKD is 1 ACKC is 1 Receive and transmit interrupts disabled Start condition and stop condition interrupts enabled e SCL low hold disabled after receiving 9 bits SWCO9 is 0 Release SCL after receiving 8 bits SWC is 0 7 2 2 Transmit Interrupt In I2C mode set the UiIRS bit in the UiC1 register to 1 UARTi transmit interrupt source is transmission completed TXEPT is 1 When the CKPH bit in the UISMR3 register is 1 with clock delay a transmit interrupt is generated at the falling edge of the ninth bit of the SCL clock Examples of transfer interrupt handling are below Additional processing can be adde
4. 1 02 134 NE SAS Page 9 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 4 4 SCLHI Bit Setting SCL Output Stop In master mode the SCLHI bit must be set when generating a start condition Refer to Figure 4 2 Register Setting Procedures for Condition Generation for details In slave mode set the SCLHI bit to 0 disabled REJ05B1349 0102 Rev 1 02 ztENESAS Page 10 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 5 Data Transmission Reception Including Slave Address Transmission 5 1 Transmitting Byte Data When transmitting byte data the SDAi pin outputs transmit data for the first to eighth bits and it is released to receive an acknowledgement for the ninth bit In I2C mode by setting the UiTB register to 9 bit data transmit data can be output and the SDAi pin can be released In 9 bit data set the transmit data to bits b7 to bO and set b8 to 1 to release the SDAi pin By setting the UFORM bit in the UiCO register to 1 MSB first and 9 bit data to the UiTB register transmit data is output from the SDAi pin in the following order b7 b6 b5 b4 b3 b2 b1 bO and b8 By setting b8 to 1 the SDAi pin becomes high impedance for the ninth bit and an acknowledgement can be received UARTi Transmit Buffer Register UiTB b15 Set to 1 to release the SDAi pin Figure 5 1 UiTB Register Setting E
5. 12C Mode 8 1 Setting Procedure for UiTB Register Data at Slave Transmit Receive 8 2 Electrical Characteristics 8 2 1 Low High level Input Voltage and Low level Output Voltage 8 2 2 Set up and Hold Time in When Detecting a Condition 8 2 3 Set up and Hold Times When Generating a Condition 8 3 Maximum Transfer Speed Using the UiBRG Count Source 8 4 Function Limitations 8 4 1 SWC2 bit in the UISMR2 Register SCL Wait 8 4 2 SDHI bit in the UiSMR2 Register SDA Output Disable 8 4 3 Restart Condition in Slave Mode REJ05B1349 0102 Rev 1 02 ztENESAS Page 2 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 3 Initialization 3 1 12C Mode Setting Set the IICM bit in the UiSMR register to 1 I2C mode and then set bits SMD2 to SMDO in the UIMR register to 010b 12C mode to enter I2C mode 3 2 SCL Clock Generation 3 2 1 SCL Clock in Master Mode When using master mode first set the SCL clock transfer rate After writing data to the UiTB register the SCL clock is output from the SCLi pin within 1 5 cycles SCL clock internal clock UiBRG count source Sampling clock of digital delay circuit n UiBRG register setting value Figure3 1 Internal Clock Configuration 3 2 2 SCL Clock in Slave Mode When using slave mode set the CKDIR bit in the UiMR register to 1 e
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8. low hold SWC9 bit is 0 enable the SCL low hold SWC9 bit is 1 after receiving 9 bits from the next byte Slave reception 1 First byte slave address Disable ACK data output set by the receive interrupt handling ACKC is 0 Set the second byte of ACK data prepare for next reception e Immediately after disabling SCL low hold SWC9 bit is 0 enable the SCL low hold SWCS bit is 1 after receiving 9 bits from the second byte 2 From second byte on Set the next byte of ACK data prepare for next reception Immediately after disabling SCL low hold SWC9 bit is 0 enable the SCL low hold SWC9 bit is 1 after receiving 9 bits from the next byte REJ05B1349 0102 Rev 1 02 ztENESAS Page 18 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 8 Notes on Using UARTi Special Mode 1 I2C Mode 8 1 Setting Procedure for UiTB Register Data at Slave Transmit Receive Write data to the UiTB register at slave transmit receive according to the following procedure When receiving the first byte data slave address 1 Write the second byte data to the UITB register in the receive interrupt handling 2 Write the third byte data to the UiTB register in the transmit interrupt handling When receiving the second byte data onwards Each time a transmit interrupt handling occurs write 1 byte data sequentially to the UiTB register starting with the fourth byte 8 2 Electrical Characteristic
9. of an SCL clock calculation Example of an actual SCL clock calculation at 384 6 kbps e UiBRG count source f1 20 MHz e UiBRG register setting value n 26 1 e SCL clock rise time ta 100 ns e SCL clock fall time tp 0 ns e Noise filter width typ 100 ns 1 e Sampling delay tgp 1 cycle fac theoretical value f1 2 n 1 20 MHz 2 25 1 384 6 kbps tiow 1 2fg theoretical value 1 2 x 384 6 kbps 1 3 ms tian 1 2fsc theoretical value tye tgp x 1 f1 1 2 x 384 6 kbps 100 ns 1 x 1 20 MHz 1 45 ms fac actual value 1 te toy ty thigh 1 0 ns 1 3 ms 100 ns 1 45 ms 350 8 kbps Note 1 Maximum 200 ns To be compatible with SCL low hold from another device the high time count starts after high is determined 1 2fsc theoretical value 1 2fsc theoretical value L L L i I LI I i SCL clock i Noise filter width 1 to 1 5 cycles high determined delay thigh Figure 3 3 SCL Clock REJ05B1349 0102 Rev 1 02 ztENESAS Page 4 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 3 3 Other Bits Settings 3 3 1 IICM2 Bit Setting Selecting an Interrupt Source The IICM2 bit in the UiSMR2 register is the 12C mode interrupt source select bit In general set the IICM2 bit to 1 UART transmit receive interrupt 3 3 2 STAC Bit Setting UARTi Initialization UARTI initialization a
10. 434 NE SAS APPLICATION NOTE M16C Family R8C Family PH I2C bus Interface Using UARTi Special Mode 1 Rev 1 02 Dec 20 2010 1 Abstract This document describes the functions and usage of UARTi special mode 1 to provide I2C bus interface using the M16C Family and R8C Family serial interface UARTI special mode 1 12C mode 2 Introduction The application example described in this document applies to the following microcomputers MCUs MCUs M16C Family R8C Family In this document i e g UARTi UIMR register indicates the number of serial interface channels available in special mode 1 The number of UARTi channels that can be used in special mode 1 is dependent on the MCU Refer to individual hardware manuals for details The simplified I2C bus communication is enabled by controlling additional functions for I2C bus communication added to the UARTi clock synchronous circuit for 12C bus interface using UARTi special mode 1 The 12C bus interface using UARTi special mode 1 has more limitations for software processing time and timing than the 12C bus interface hardware module Careful verification and evaluation of your system are recommended including the interaction between the I2C bus communication program and programs other than the 12C bus communication program REJ05B1349 0102 Rev 1 02 ztENESAS Page 1 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 Quick
11. AS Page 5 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 3 3 3 DL2 to DLO Bit Settings SDA Digital Delay When transferring data with the I2C bus change the data while the SCL clock is a low If SDA is changed when the SCL clock is a high the change is recognized as one of the corresponding conditions see 8 2 3 Set up and Hold Times When Generating a Condition The SDA digital delay function delays output from the SDAi pin By delaying the change of the SDA the change in data can be read while the SCL clock is low The SDA digital delay function is enabled by setting bits DL2 to DLO in the UISMR3 register to 001b to 111b and no delay by setting them to 000b SCL 1 I UiBRG count source i L u I When DL2 to DLO are 000b no delay SDA Y l When DL2 to DLO are 001b 1 to 2 cycles of UIBRG count source SDA When DL2 to DLO are 111b 7 to 8 cycles of UiBRG count source SDA DL2 to DLO Bits in the UiSMRS register Figure 3 4 SDA Output Selection by Setting Bits DL2 to DLO 3 3 4 CSC Bit Setting Clock Synchronization In master mode set the CSC bit in the UISMR2 register to 1 enabled to enable clock synchronization In slave mode set the CSC bit to 0 disabled Clock synchronization enters a wait state automatically by the low hold of the SCLi pin from another device and leaves the wait state by releasing the low hold of the SCLi pin When using cl
12. Byte Data REJ05B1349 0102 Rev 1 02 134 NE SAS Page 14 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 7 Interrupts 7 1 Start and Stop Condition Interrupts The interrupt request generation timing of the start condition interrupt depends on the setting of the STSPSEL bit in the UISMR4 register When the STSPSEL bit is O start and stop conditions not output an interrupt request is generated when a start condition or stop condition is detected When the STSPSEL bit is 1 start and stop conditions output an interrupt request is generated when a start condition is generated or a stop condition is detected In master mode set the STSPSEL bit to 0 in the start and stop condition generation interrupt handler The BBS bit in the UiSMR register is changed to 1 start condition detected at the falling edge of SDA in a start condition The BBS bit is changed to 0 stop condition detected at the rising edge of SDA in a stop condition When an interrupt request is generated read the BBS bit and execute start condition or stop condition processing While in slave mode and while using the UARTI initialization function UARTi is automatically initialized when a start condition is detected so an interrupt is not necessary when detecting a start condition see 3 3 2 STAC Bit Setting UARTi Initialization 1 Slave mode STSPSEL bit in the UiSMR4 register BBS bit in the UiSMR regi
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14. Reference by Title Refer to the corresponding master or slave column depending on use Master Master Slave Slave Transmitter Receiver Transmitter Receiver 3 Initialization 3 1 12C Mode Setting Yes Yes Yes Yes 3 2 SCL Clock Generation 3 2 1 SCL Clock in Master Mode Yes Yes N A N A 3 2 2 SCL Clock in Slave Mode N A N A Yes Yes 3 2 3 Counting SCL Clock Yes Yes Yes Yes 3 2 4 SCL Clock Frequency Yes Yes N A N A 3 3 Other Bits Settings 3 3 1 IICM2 Bit Setting Selecting an Interrupt Yes Yes Yes Yes Source 3 3 2 STAC Bit Setting UARTi Initialization N A N A Yes Yes 3 3 3 DL2 to DLO Bit Settings SDA Digital Delay Yes Yes Yes Yes 3 3 4 CSC Bit Setting Clock Synchronization Yes Yes N A N A 4 Condition Generation and Detection 4 1 Condition Generation in Master Mode Yes Yes N A N A 4 2 Start Condition and Stop Condition Detection in N A N A Yes Yes Slave Mode 4 3 CKPH Bit Setting Clock Delay Yes Yes Yes Yes 4 4 SCLHI Bit Setting SCL Output Stop Yes Yes N A N A 5 Data Transmission Reception Including Slave Address Transmission 5 1 Transmitting Byte Data Yes Yes 5 2 Byte Data Reception N A Yes 5 3 SWC Bit and SWC9 Bit Settings SCL Wait N A N A Function 6 ACK and NACK Generation and Detection 6 1 Generating ACK and NACK 6 2 Detecting ACK and NACK 7 Interrupts 7 1 Start and Stop Condition Interrupts 7 2 Receive Transmit Interrupts 7 2 1 Receive Interrupt 7 2 2 Transmit Interrupt 8 Notes on Using UARTi Special Mode 1
15. ansmit Receive added as 8 1 Dec 20 2010 3 1 12C Mode Setting revised All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied I
16. ave address does not match In this case the SDAi pin becomes high impedance when the UiTB register is set to 01FFh or when using the SDA output disable function The SDA output disable function changes the SDAi pin to a high impedance state Set the SDHI bit to 1 disabled to enable this function When the SDHI bit is set to O enabled the value set to the UiTB register is output from the SDAi pin 8 4 3 Restart Condition in Slave Mode In 12C mode the restart condition detection in slave mode is not supported REJ05B1349 0102 Rev 1 02 134 NE SAS Page 22 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 9 Reference Documents M16C Family R8C Family User s Manual Hardware The latest versions can be downloaded from the Renesas Electronics website Technical News Technical Update The latest information can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com inquiry REJ05B1349 0102 Rev 1 02 134 NE SAS Page 23 of 23 Dec 20 2010 Bavicion Histor M16C Family R8C Family y I2C bus Interface Using UARTi Special Mode 1 Description Summary First edition issued R8C Family added Sentences revised Sep 1 2010 3 2 3 Counting SCL Clock added and Figure 3 2 added 6 2 the ninth bit b8 revised as b8 Setting Procedure for UiITB Register Data at Slave Tr
17. ck delay function is enabled by setting the CKPH bit in the UISMR3 register to 1 with clock delay When using the clock delay function data is transmitted twice from the receive shift register to the UiRB register For contents of UiRB register refer to Figure 4 3 Clock Delay Function In master mode set the CKPH bit when the STSPSEL bit in the UiSMR4 is 1 start and stop conditions output Before generating a start condition set the CKPH bit to 0 no clock delay After generating a start condition set the CKPH bit to 1 before setting the STSPSEL bit to 0 start and stop conditions not output After generating a stop condition is generated set the CKPH bit to 0 before setting the STSPSEL bit to 0 Receive interrupt Transmit interrupt Transfer to UiRB register 1st time Transfer to UiRB register 2nd time b15 b9 b8 b7 bO b15 b9 b8 b7 bO L pol oz pe ps os os pz o1 _ pe pz pe ps pa ps pa e po UiRB register contents UiRB register contents The above assumes the following The IICM2 bit in the UISMR2 register is 1 UART transmit UART receive interrupt The CKPH bit in the UiSMR3 register is 1 with clock delay Figure 4 3 Clock Delay Function CKPH bit in the UiSMRS register STSPSEL bit in the UiSMR4 register Start condition generation interrupt Stop condition detection interrupt Note 1 Set to 0 or 1 by a program Figure 4 4 CKPH Bit Setting in Master Mode REJ05B1349 0102 Rev
18. cles of the UiBRG count source Therefore the maximum transfer speed of an I2C bus connectable to the M16C Family and R8C Family is limited by the main clock frequency and speed of the UiBRG count source which is selected by setting bits CLK1 and CLKO in the UiCO register There is a possibility of bit slippage if not used with a transfer speed that meets the following conditions I2C bus interface maximum transfer speed Hz lt UIBRG count source Hz 3 Example 1 When the source frequency is 10 MHz and f32 is selected as the UiBRG count source Maximum transfer speed without bit slippage Hz 10 MHz 32 3 104 kbps In this case the maximum transfer speed of the I2C bus is 104 kbps Example 2 When the source frequency is 10 MHz and f8 is selected as the UiBRG count source Maximum transfer speed without bit slippage Hz lt 10 MHz 8 3 416 kbps In this case the maximum transfer speed of the I2C bus is 400 kbps maximum value of Fast mode 8 4 Function Limitations 8 4 1 SWC2 bit in the UISMR2 Register SCL Wait In general the SWC2 bit is not needed When the SWC2 bit is set to 1 low level output the SCLi pin can be fixed low while transmitting receiving When the SWC2 bit is set to 0 transmit receive clock the SCLi pin is released and an SCL clock is output 8 4 2 SDHI bit in the UiSMR2 Register SDA Output Disable In general the SDHI bit is not needed In slave mode disable SDAi pin output when the sl
19. d as needed Master transmission 1 First byte slave address Read ACK and NACK check slave address matching Set second byte transmit data when ACK Generate a stop condition or restart condition when NACK 2 From second byte on Read ACK and NACK Set next byte transmit data when ACK Generate a stop condition or restart condition when NACK restart or last byte REJ05B1349 0102 Rev 1 02 134 NE SAS Page 17 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 Master reception 1 First byte slave address Read ACK and NACK check slave address matching Set second byte of ACK data when ACK prepare for next reception Generate a stop condition or restart condition when NACK 2 From second byte on Set next byte of ACK data prepare for next reception 3 Last byte 1 byte Set next byte of NACK data prepare for next reception 4 Last byte Generate a stop condition or restart condition Slave transmission 1 First byte slave address Disable ACK data output set by the receive interrupt handling ACKC is O Set the second byte of transmit data e Immediately after disabling SCL low hold SWC9 bit is 0 enable the SCL low hold SWCS bit is 1 after receiving 9 bits from the second byte 2 From the second byte on Read ACK and NACK Set the next byte of the transfer data when ACK Immediately after disabling SCL
20. details on transmit and receive interrupt timing 1 First byte slave address SCL Master SDA Master SCL Slave SDA Slave 1 Fixed low i SWC9 is 1 Fixed low SWC is 1 R When STAC is 1 The SWC bit automatically becomes 1 Program STAC is 1 SWO9 is 1 fixed low SWC9 is 0 Released processing SWC is 0 Released SWO9 is 1 Next fixed low 2 From the second byte on 3 4 SCL Master SDA Gas T geri he RN GR WC IGGL T cos A AT Y Master 4 D5 e A D3 De n Bl xe e n SCL Fixed low Slave when SWC9 is 1 SDA 8 quem mmm emm em emm m Ex Slave x D5 x D4 Xx D3 X D2 D1 X DO Xx AA 4 Geeewed bewwnd beewad beewaed bewewnd beewnd Lewwed Program SWC9 is 0 Released processing SWC9 is 1 Next fixed a low level The above assumes the following The CKPH bit in the UiSMR3 register is 1 with clock delay Figure 5 5 SCL Wait Function REJ05B1349 0102 Rev 1 02 ztENESAS Page 13 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 6 ACK and NACK Generation and Detection 6 1 Generating ACK and NACK When receiving data that includes a slave address the receiver generates an acknowledgement at the ninth bit An acknowledgement is generated by setting bits ACKD and ACKC in the UiSMRA register When the ACKC bit set to 1 ACK data output the UiTB register setting is not output and the ACKD bit setting is output When th
21. ditions output the conditions corresponding to the above bits are generated When generating a condition set bits STAREQ STPREQ and RSTAREQ to 1 before setting the STSPSEL bit to 1 Figure 4 2 shows the Register Setting Procedures for Condition Generation For details on set up and hold times when generating start and stop conditions refer to 8 2 3 Set up and Hold Times When Generating a Condition STSPSEL bitinthe 1 UiSMR4 register SCL SDA ABE C CA EK ADAU AE 1 4 STAREQ is 1 2 RSTAREQ is 1 STPREQ is 1 li Start condition generation interrupt Stop condition detection interrupt Set to 0 or 1 by a program However bits STAREQ RSTAREQ and STPREQ become 0 automatically when each of the conditions is generated When generating a start condition after a stop condition is generated set the STSPSEL bit in the UiSMR4 register to 0 wait half an SCL clock or more then set the STAREQ bit to 1 Figure 4 1 Operation Example of Bits STAREQ RSTAREQ STPREQ and STSPSEL REJ05B1349 0102 Rev 1 02 134 NE SAS Page 7 of 23 Dec 20 2010 M16C Family R8C Family Start condition generation See Note 1 UiSMR4 0x09 End Restart condition generation UiSMR4 lt 0x02 UiSMR4 0x3A Stop condition generation UiSMR4 0x04 UiSMR4 0x3C The above assumes the following I C bus Interface Using UARTi Special Mode 1 Wait bus releas
22. e Set the STSPSEL bit to 0 Select 1 C mode and internal clock Set the UiBRG fastest value for shortest waiting time Executing this command requires at least one half of an SCL clock 62 5 ns Reset the UiBRG value to target transfer rate Set the STAREQ bit to 1 Set the STSPSEL bit to 1 Set the RSTAREQ bit to 1 Set the STSPSEL bit to 1 Set the STPREQ bit to 1 Set the STSPSEL bit to1 XIN 16 MHz main clock divided by 1 no division UIBRG count source f1 Note 1 After a stop condition is generated when generating the next start condition after setting the STSPSEL bit in the UiSMR4 register to 0 and waiting at least half of an SCL clock then set the STAREQ bit to 1 Figure 4 2 REJ05B1349 0102 Rev 1 02 Dec 20 2010 134 NE SAS Register Setting Procedures for Condition Generation Page 8 of 23 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 4 2 Start Condition and Stop Condition Detection in Slave Mode In slave mode start and stop conditions can be detected by start and stop condition detecting interrupts Refer to 7 1 Start and Stop Condition Interrupts for details When detecting a start condition or stop condition the set up and hold times may differ from the I2C bus specification Refer to 8 2 2 Set up and Hold Time in When Detecting a Condition for details 4 3 CKPH Bit Setting Clock Delay Use the clock delay function in 12C mode The clo
23. e ACKD bit is 0 ACK the SDAi pin outputs a low When the ACKD bit is 1 NACK the SDAi pin becomes high impedance If ACK and NACK are generated after data reception ACK is generated when the ACKD bit set to 0 and the ACKD bit set to 1 at the falling edge of the eighth bit of the SCL clock NACK is generated when the ACKD bit set to 1 and the ACKC bit set to 1 Set ACKC bit set to 0 serial interface data output at the falling edge of the ninth bit of the SCL clock see Figure 6 1 ACKC Bit and ACKD Bit Settings When ACK or NACK is determined before data receive starting time acknowledge is generated by the UiTB register set to OOFFh ACK or 01FFh NACK see 5 2 Byte Data Reception At this point set the ACKC bit to 0 In slave mode ACK or NACK is generated according slave address matching in the receive interrupt handler set the ACKD bit to 0 or 1 and the ACKC bit to 1 see 7 2 Receive Transmit Interrupts ACKC bitinthe 1 UiSMR register y soa Jj or X06 A Ds X D4 A D3 A D2 A D A DO ANA Receive interrupt Transmit interrupt Note 3 1 Set to 0 or 1 by a program ACKD bit setting output Figure 6 1 ACKC Bit and ACKD Bit Settings 6 2 Detecting ACK and NACK When transmitting data that includes a slave address the transmitter receives an acknowledgement at the ninth bit In the transmit interrupt handler read b8 in the UiRB register to determine the received acknowledgement see 5 1 Transmitting
24. ends on the MCU type In Fast mode the minimum time is 600 ns and is within the I2C bus specification when using the UiBRG count source operated at 10 MHz but it becomes out of spec when operated at less than 10 MHz In Standard mode the minimum time is 4 0 us and is within the I2C bus specification when using the UiBRG count source operated at 1 5 MHz but it becomes out of spec when operated at less than 1 5 MHz 6 cycles of UIBRG count source lt Set up time 6 cycles of UiBRG count source lt Hold time Set up time Hold time SCLi NEN SDAi Start condition i SDAi t Stop condition 1 Note 1 The number of cycles depends on MCU type Refer to the hardware manual for details Figure 8 1 Set up and Hold Times When Detecting Start and Stop Conditions REJ05B1349 0102 Rev 1 02 134 NE SAS Page 20 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 8 2 3 Set up and Hold Times When Generating a Condition When generating a start condition the hold time typ STA is a half cycle of the SCL clock When generating a stop condition the set up time tgy STO is a half cycle of the SCL clock When the SDA digital delay function is enabled delay time must be taken into consideration see 3 3 3 DL2 to DLO Bit Settings SDA Digital Delay The following shows a calculation example of hold and set up times when generating a condition Calculation example when
25. his document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 5 When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations 6 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 7 Renesas Electronics products are classified according to the following th
26. n a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm
27. ncluding but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 10 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 341 N SAS SALES
28. ock synchronization the actual SCL clock is delayed compared despite the setting of the SCL clock Refer to 3 2 4 SCL Clock Frequency for details Internal SCL clock N x eh n t Even when an internal SCL clock becomes high Usually ihe internal SCL COUR outputs a high since the SCLi pin is low this high count is stopped but a low is output at the falling edge of the SCLi during this period pin and the low count starts i SCL clock The internal SCL clock becomes high but the SCLi pin is low and the SCL clock keeps a low A low held by another device Figure 3 5 Clock Synchronization REJ05B1349 0102 Rev 1 02 ztENESAS Page 6 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 4 Condition Generation and Detection 4 1 Condition Generation in Master Mode In master mode start stop and restart conditions are generated by hardware A start condition is generated by setting the STAREQ bit in the UISMR4 register to 1 start A stop condition is generated by setting the STPREQ bit in the UISMRA register to 1 start after the SCLi pin has been released A restart condition is generated by setting the RSTAREQ bit in the UiSMRA register to 1 start after the SCLi pin has been released Bits STAREQ STPREQ and RSTAREQ automatically become 0 when their respective conditions are generated When the STSPSEL bit in the UISMR4 register is set to 1 start and stop con
29. ree quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety
30. s The electrical characteristic of the M16C Family and R8C Family and the I2C bus electrical specifications differ 8 2 1 Low High level Input Voltage and Low level Output Voltage The low level input voltage high level input voltage and low level output voltage may differ from the I2C bus specification Each MCU Series electrical characteristics differ Refer to individual hardware manuals for details M16C 62P Group When Vcc 2 7 to 5 5 V High level input voltage Vip min 0 8 Vcc guaranteed value Low level input voltage Vi max 0 2 Vcc guaranteed value When Voc 5 V and lo 5 mA Low level output voltage VoL max 2 0 Vcc guaranteed value I2C bus specification High level input voltage Vi min 0 7 Vec Low level input voltage Vj max 0 3 Voc When loj 6 mA Low level output voltage VoL max 0 6 V REJ05B1349 0102 Rev 1 02 134 NE SAS Page 19 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 8 2 2 Set up and Hold Time in When Detecting a Condition In slave mode set up and hold times in the start and stop condition detection may differ from the 12C bus specification In the I2C bus specification Fast mode set up and hold times in the start and stop condition are a minimum of 600 ns minimum of 4 0 us in Standard mode In contrast the set up and hold times of the M16C Family are a minimum of six cycles of the UiBRG count source the cycle count dep
31. setting 100 kbps e UIBRG count source f1 20 MHz e UiBRG register setting value n 100 1 SDA digital delay setting value DL2 to DLO are 101b 5 or 6 cycles of UIBRG count source fsc theoretical value f1 2 n 1 20 MHz 2 x 99 1 100 kbps tp delay cycle count f1 6 20 MHz 0 3 us tup srA theoretical value 1 2fsc theoretical value 1 2 x 100 kbps 5 us teu sro theoretical value 1 2fgc theoretical value 1 2 x 100 kbps 5 us fup srA actual value tup srA theoretical value tp 5 us 0 3 us 4 7 us fsu sro actual value tgy sTo theoretical value tp 5 us 0 3 us 5 3 us 1 fag theoretical value theoretical value I 1 2fg theoretical value 1 2fsa I I I I I Internal clock UiBRG output tup sta tsusto theoretical value theoretical value tsu sto actual value fag SCL clock tp SDA digital delay time tup sta Hold time when generating a start condition tgy sto Set up time when generating a stop condition Figure 8 2 Set up and Hold Times When Generating Start and Stop Conditions REJ05B1349 0102 Rev 1 02 134 NE SAS Page 21 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 8 3 Maximum Transfer Speed Using the UiBRG Count Source The time necessary to recognize the SCL clock level is dependent on the sampling frequency with a maximum of three clock cy
32. ster Start condition detection Stop condition detection interrupt request generated interrupt request generated 2 Master mode when CKPH is 1 STSPSEL bit inthe 1 UiSMR4 register BBS bit in the UiSMR register STAREQ is 1 STAREQ is 1 4 Start condition generation Stop condition detection interrupt request generated interrupt request generated Note 1 Set to 0 or 1 by a program Figure 7 1 Start and Stop Condition Interrupts REJ05B1349 0102 Rev 1 02 134 NE SAS Page 15 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 7 2 Receive Transmit Interrupts Figure 7 2 shows the Receive Transmit Interrupt Timing 1 First byte slave address SCL Master SDA Master SCL Slave SDA Slave Receive interrupt generation only in slave mode 2 From the second byte on 2 SCL Master SDA bt ahaha E aana 7 zi cisik camion T acque f kell F x D4 X D3 X D2 X D1 X DO X Master 4 aX cI J ezozsd Geese eonzed ooscr E SCL Slave N qnm mmm mtm amm aem m y qmm Jm x D4 X D3 X D2 X D1 X DO X AA Ceres Ceecee ee Coses ee en V22 2 J Cond t Transmit interrupt generation Transmit interrupt generation The above assumes the following The CKPH bit in the UiSMR3 register is 1 with clock delay Figure 7 2 Receive Transmit Interrupt Timing REJ05B1349 0102 Rev 1 02 RENESAS Dec 20 2010
33. that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Notice 1 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website 2 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 3 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part 4 Descriptions of circuits software and other related information in t
34. utomatically initializes UARTi when a start condition is detected Use this function in slave mode Set the STAC bit in the UiSMR2 register to 1 to enable this function or 0 to disable it While using the UARTi initialization function in slave mode UARTi is automatically initialized when a start condition is detected Therefore an interrupt is not necessary when a start condition is detected When the STAC bit is 1 and a start condition is detected the following initialization procedure is executed 1 The transmit shift register is initialized and the UiTB register value is transferred to a transmit shift register Consequently there is no need to reset data to the UiTB register when receiving data and transfer starts with the next input clock as the first bit As the transmit data is the same as the last data transmitted set the ACKD bit in the UISMR4 register to 1 NACK and the ACKC bit to 1 ACK data output to disable the transmit data from being output 2 The receive shift register is initialized and slave address reception starts with the next input clock as the first bit Even if UARTi is initialized and data reception starts before the UiRB register is read an overrun error will not occur 3 The SWC bit in the UISMR2 register automatically becomes 1 enabled Consequently the SCL wait function is enabled and the SCLi pin becomes fixed low at the falling edge of the eighth bit of the SCL clock REJ05B1349 0102 Rev 1 02 ztENES
35. xternal clock This setting disables the UiBRG register Since the UiBRG count source is used as a sampling clock of the digital delay circuit set bits CLK1 and CLKO in the UiCO register see 3 3 3 DL2 to DLO Bit Settings SDA Digital Delay 3 2 3 Counting SCL Clock Counting the SCL clock in this application note is shown in Figure 3 2 SCL ibt gt Example 1 shows the falling edge of the first bit Figure 3 2 Counting th SCL Clock REJ05B1349 0102 Rev 1 02 134 NE SAS Page 3 of 23 Dec 20 2010 M16C Family R8C Family I2C bus Interface Using UARTi Special Mode 1 3 2 4 SCL Clock Frequency The SCL clock duty generated in I2C mode is 50 The low level width of the SCL clock is 1 25 us when the I2C bus setting is Fast mode maximum SCL clock 400 kbps This value does not satisfy the Fast mode I2C bus specification fj oy Min 1 3 us Set the SCL clock to 384 6 kbps or less to satisfy the SCL clock low level width of 1 3 us or more When the clock synchronous function is enabled there is a sampling delay of the noise filter plus 1 to 1 5 cycles of UiBRG count source There is also a delay of the SCL clock when high is determined and the SCL clock high width is extended Therefore the actual SCL clock becomes slower than SCL clock transfer rate setting To calculate the actual SCL clock the SCL clock rise time tg also needs to be taken into consideration The following is an example
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