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Guidelines for integrating device drivers - dit/UPM

1. us POLIT CNICA Reference VMLAB UPM TRI Date 15 09 2009 Issue 7 5 Page I of 85 ESTEC Contract No 21392 08 NL JK Guidelines for integrating device drivers in the ASSERT Virtual Machine Output of WP 300 Written by Organization Date Juan Zamorano Jorge L pez Juan A de la Puente UPM 15 09 2009 Revised by Organization Date Juan A de la Puente UPM 15 09 2009 Tullio Vardanega UPD 15 09 2009 Accepted by Organization Date Maxime Perrotin ESTEC 22 09 2009 Reference VMLAB UPM TR1 d Date 15 09 2009 Issue 7 5 Document Change Record Issue Revision Date Change Author 1 0 22 12 2008 First version for review J Zamorano J L pez 1 1 15 01 2009 Revised as per review comments J Zamorano J L pez 1 2 06 05 2009 Minor changes in section 2 J Zamorano J L pez 1 3 24 07 2009 Draft version for final review J A de la Puente J Zamorano 1 4 29 07 2009 Revised version for final review J A de la Puente J Zamorano 1 5 15 09 2009 Final version for acceptance review J A de la Puente J Zamorano VMlab UPM TRI Last Modified on September 23 2009 page 2 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Abstract This document contains a set of guidelines for extending the ASSERT Virtual Machine kernel with device drivers The real time kernel is a versi
2. Set PCI Target Page Address Register ACTA PCI_Target_Page_Address_Aux TPAl 16 40 PCI Target Page Address Aux TPA2 16 60 PCI Target Page Address Aux Reservedl others gt False PCI Target Page Address Aux Reserved2 others gt False PCI Target Page Address PCI Target Page Address Aux Set fields in Status Command Register PCISC PCI Status Command Aux PCI Status Command PCI Status Command Aux coml True Enable target memory command response PCI Status Command Aux com2 True Enable PCI master PCI Status Command AU COME True Enable parity check PCI Status Command PCI Status Command Aux Set the latency timer in PCI bus clock to 64 PCIBHLC BIST Header Latency Cache Siz Latency Timer gt 64 Cache Line Size gt 0 BIST gt others gt False Header gt others gt False Sete fieles im DCH Imitiator Comiiqureaciom PCE PECL MWinilicieicere Com uejWiceic loa ube g PECI mulr lara Comic d e ola PONIA oras Ontur ona CIMO True PCI Initiator Configuration Aux Mode True CAL neto onisstqum ation B ICI Waele oie Coie leurs Loja UIS VMlab UPM TRI Last Modified on September 23 2009 page 68 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
3. 10 record 11 Reference Switch Turntable Type Switch 12 Reference Switch Horizontal Axis Type Switch 13 Reference Switch Vertical Axis Type Switch 14 Reference Switch Gripper Type Switch 15 Pulse Counter Turntable Type Switch 16 Pulse Counter Horizontal Axis Type Switch 17 Pulse Counter Vertical Axis Type Switch 18 Pulse Counter Gripper Type Switch 19 end record 20 21 type Type Robot Control Register is 22 record VMlab UPM TRI Last Modified on September 23 2009 page 30 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 23 Motor Turntable Type Motor Turntable 24 Motor Horizontal Axis Type Motor Horizontal Axis 25 Motor Vertical Axis Type Motor Vertical Axis 26 Motor Gripper Type Motor Gripper 21 end record 28 29 private 30 31 for Type_Switch use On gt 0 Off gt 1 32 for Type Switch size use 1 33 34 for Type Motor Turntable use Stop gt 0 Counterclockwise gt 1 Clockwise gt 2 35 for Type Motor Turntable size use 2 36 37 for Type Motor Horizontal Axis use Stop 0 Backward 1 Forward 2 38 for Type Motor Horizontal Axis size use 2 39 40 for Type Motor Vertical Axis use Stop gt 0 Upward gt 1 Downward gt 2 41 for Type_Motor_Vertical_Axis size use 2 42 43 for Type_Motor_Gripper use Stop gt 0 Open gt 1 Close gt 2 44 for Type_Motor_Gripper size use 2 45 46 for Type_Robot_Status
4. 4 20 Interrupt names The names of the interrupts as well as their respective priorities are declared in the Ada standard package Ada Interrupts Names The names are taken from the interrupt list of the Rad Hard 32 bit SPARC V8 Processor AT697E manual Listing 4 2 Package Ada Interrupts Names with Ada Interrupts Use OGNI CUSTO SEN IEID 3 with System OS Interface 4 Used for names and priorities of interrupts 5 6 package Ada Interrupts Names is 7 8 9 External Interrupts 0 1 VMlab UPM TRI Last Modified on September 23 2009 page 38 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 12 External_Interrupt_3 constant Interrupt_ID 13 Interrupt ID System OS Interface External Interrupt 3 14 External Interrupt 3 Priority constant System Interrupt Priority 15 System OS Interface External Interrupt 3 Priority 16 17 External Interrupt 2 constant Interrupt ID 18 Interrupt ID System OS Interface External Interrupt 2 19 External Interrupt 2 Priority constant System Interrupt Priority 20 System OS Interface External Interrupt 2 Priority 21 22 External Interrupt 1 constant Interrupt ID 23 Interrupt ID System OS Interface External Interrupt 1 24 External Interrupt 1 Priority constant System Interrupt Priority 25 System OS Interface External Interrupt 1 Priori
5. The GRSPW core can be split into three main parts e The link interface which consists of the receiver transmitter and the link interface FSM e The AMBA interface which consists of the DMA engines the AHB master interface and the APB interface VMlab UPM TRI Last Modified on September 23 2009 page 43 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 e The RMAP handler is an optional part of the GRSPW and handles incoming packets which are determined to be RMAP commands See section 5 1 4 for details Figure 5 2 shows a block diagram of the internal structure of the GRSPW module pou D 1 0 SEND TRANSMITTER TRANSMITTER 4 a le ii S 1 0 i A AMAR p TRANSMITTER 4 GE ES DMA ENGINE m FSM MASTER INTERFACE gt RECEIVER gt DMA ENGINE Y x DO RECEIVERO RMAP RECEIVER L RXCLK RXCLK APB S0 L RECOVERY RECEIVER AHB FIFO REGISTERS INTERFACE E i A A A M C RXCLK RXCLK RECEIVER1 J N CHAR RECEIVER DATA S1 RECOVERY FIFO H gt PARALLELIZATION Figure 5 2 GRSPW block diagram reproduced from D11 5 1 1 Link interface The link interface handles the communication on the SpaceWire network and consists of a transmitter a receiver a FSM and FIFO interfaces FIFO interfaces are provided to the DMA engines and
6. 15 09 2009 Issue 5 The Receive operation is always blocking i e the calling thread is suspended until a data packet is received On the other hand Send can be invoked as either a blocking or non blocking operation A blocking send suspends the calling thread until the data packet has been sent through the SpaceWire device link e Parameters contains the definitions of all the parameters that can be configured by the application program mer The parameters are the sizes of receive and transmit packets the number of SpaceWire core devices and the number of entries in the receiver and transmitter descriptor tables e Core contains all the code that interacts with the device registers in order to implement the I O operations This component exports a set of interface operations which are used to implement the HLInterface op erations The component implements all the device operations in terms of the device registers and other hardware characteristics e Handler contains the device interrupt handler which is invoked on the completion of I O operations There is a single interrupt for all the three SpaceWire devices and a synchronization object for each of the transmit and receive sections of each SpaceWire hardware device Each occurrence of the interrupt is signalled to the appropriate synchronization object by identifying the device and function that has caused the interrupt e Registers contains register and bit fie
7. 31 subtype IO BAR Type is Interfaces Unsigned 32 32 Used for IO Bank Address Register 33 34 Vendor codes 35 Vendor Invalid constant AMBA Vendor Type 16404 VMlab UPM TRI Last Modified on September 23 2009 page 71 of 85 Reference VMLAB UPM TRI Date 15 09 2009 Issue 5 36 Vendor Gaisler constant AMBA Vendor Type 1614 37 Vendor ESA constant AMBA Vendor Type 16444 38 39 Gaisler Research device id s 40 Gaisler APB Master constant AMBA Device Type 164614 41 Gaisler Spacewire constant AMBA Device Type 16 1F 42 Gaisler APB UART constant AMBA Device Type 16 C 43 Gaisler AHB UART constant AMBA Device Type 16474 44 Gaisler CANBus constant AMBA Device Type 164344 45 Gaisler IROMP constant AMBA Device Type 16 D 46 Gaisler PIOPORT constant AMBA Device Type 16 1A 47 Gaisler PCIFBRG constant AMBA Device Type 164144 48 49 50 Device record type 51 52 53 AMBA APB Plug amp play record 54 type AMBA Device is 55 record 56 IRQ B IRO Ive 57 Interrupt routing information 58 Version AMBA Version Type 59 Version number 60 Device AMBA Device Type 61 Device ID 62 Vendor AMBA Vendor Type Vendor Invalid 63 Vendor ID 64 IOBar IO BAR Type 65 IO BAR Bank Address Register contains the start address 66 for an area allocated to the device 67 end record 68 69 AMBA Max APB Slaves co
8. is the higher level computer program that interacts with the communication device by means of the device driver Detailed knowledge of the computer bus is also needed for driver development The buses of the GR RASTA development platform are used in the document as an example Notwithstanding the notional use of a particular driver and bus as a case study the guidelines provided in the document are generic in nature and are intended to help developers build a large variety of device drivers and integrate them in the ASSERT Virtual Machine GR RASTA is a modular system based on a LEON2 or LEON3 computer using a cPCI compact Peripheral Component Interconnect backplane bus See http www gaisler com doc gr rasta product sheet pdf for detailed information VMlab UPM TR1 Last Modified on September 23 2009 page 9 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 1 3 Scope The target audience for this document are software engineers who are in charge of writing the lower level compo nents of onboard computer software 1 3 Glossary 1 3 4 Acronyms and abbreviations AHB ALRM AMBA APB API ASB ASSERT AVM BAR cPCI CCSDS CPU DMA DSU ECSS EISA EEP EOP FCT FIFO FPGA FSM GPS GR GRSPW GNU HI VO IMASK IOREQ IRQ ISR Advanced High performance Bus Ada Language Reference Manual Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Application Programming Interface
9. 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 EA MS CAI USE CAPTA PCI_Interrupt_Enable Reserved gt others gt False others gt True The AT697 initialization is complete at this point Scan the PCI bus and find the RASTA board Scan board slots in bus 0 for Slot in Unit Type Range loop Hc Read Config Dword 0 Slot 0 Config Header Vendor ID Vendor To Vendor Code Id and 16 FFFF if Vendor Gaisler Vendor ID then DeviceID To Device Code Interfaces Shift Right Id 16 and 164FFFF1 RastaBoard Vendor ID Vendor RastaBoard Device ID DeviceID Header Read Config Byte 0 Slot 0 Config Header Header Format if Header and Multi Function 1 then TODOS acol uml WAC ELOM STAJICE null else Num Functions i i gt end if jpslinel Ceta Lor Lll 3euupxenrshoyp s Sha CAS Ioen for func in 0 Num Functions 1 loop Id Read Config Dword 0 Slot func Config Header Vendor ID Vendor To Vendor Code Id and 16 FFFF if Vendor Invalid Vendor ID and Id 0 then NECK BS Reael Comro IDwwoxsel 0 Slot ser Config Header Revision Aux Interfaces Shift Right Aux 16 if Device Class Aux Class Bridge PCI then RastaBoard Bus ge p RastaBoard Unit ge Slot RastaBoard Device Function func configure address regions VMlab UPM TRI Last Modified on Septe
10. Conf Area 47 48 GRLIB APB slaves contain a plug amp play identification register 49 word which is included in the APB records These records are 50 combined into an array which is connected to the APB bridge 51 for j in Max APB Slaves Devices loop 52 53 PointerID Read _ AMBA Identification To Pointer 54 System To Address CFG AreaAPB 55 ConfWordAPB PointerID all 56 57 if ConfWordAPB Vendor 0 then 58 Pointer Read Memory Word To Pointer 59 System To Address CFG AreaAPB Word Size 60 IOBar Pointer all 61 62 Devices j Vendor ConfWordAPB Vendor 63 Devices j Device ConfWordAPB Device 64 Devices j Version ConfWordAPB Version 65 Devices j IRQ ConfWordAPB IRO 66 gt Interrupt routing information 67 Devices j IOBar IOBar Start APBMaster IOBar 68 IO BAR Bank Address Register contains the start 69 address for an area allocated to the device 70 end if 71 CFG AreaAPB CFG AreaAPB AMBA APB Conf Words Word Size 72 end loop 73 end if 74 end if 75 CFG Area CFG Area AMBA AHB Conf Words x Word Size 76 end loop TI 78 return Devices 79 end Scan AMBA Bus VMlab UPM TRI Last Modified on September 23 2009 page 74 of 85 Reference VVLAB UPM TRI d Date 5 09 2009 Issue 7 5 Chapter 6 Build process To produce an executable file from application level user files the compiler performs a three step
11. Other data definitions and local operations 41 42 end SpaceWire Core The Initialize operation takes care of all the initialization steps that are required to make the Space Wire devices operational so that data can be sent and received over the SpaceWire links Figure 5 7 summarizes the initialization sequence steps An internal procedure SPW Startup initializes the registers and descriptor tables in a SpaceWire device The Set Node Addres operation must be invoked after successful initialization in order to assign a SpaceWire node address to every SpaceWire device which is to be subsequently used to receive and transmit packets in a network The Send and Receive operations perform the actual data transfers on SpaceWire devices Figures 5 8 and 5 9 summarize the actions performed by these operations See the source code for the details VMlab UPM TRI Last Modified on September 23 2009 page 56 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 7 5 init processor board scan PCI configure memory controller configure interrupt controller locate IP cores devices vendor ID IRQ base address reset test computer link configure DMA channel init T R buffers enable reception send message set address enable interrupt handle interrupt receive message handle interrupt check flags get the message F Figure 5 7 SpaceWire driver initializa
12. Pending_Interrupt UART_1 then UART_Callback 2 Registers Write Interrupt Clear Register VMlab UPM TRI Last Modified on September 23 2009 page 61 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 31 32 33 34 35 36 37 RastaBoard To Unsigned 32 RastaBoard RastaBoard MBar0 Address Reserved16 gt others gt True UART 1 gt True others gt False end if end if 38 end Handle IRQ 5 3 5 PCI Package PCI provides functions for initializing the PCI bus and locating the interface board where the Space Wire devices are found No DU BuyNnN Listing 5 9 Package PCI This version of the package is for the GR RASTA system with Interfaces with System package PCI is PCI configuration space codes Boards in a PCI bus can be addressed in configuration space by means of an 8 bit bus number a 5 bit device number and a 3 bit funciton number The configuration space is 256 bytes for each devic type Bus Type is range 0 2xx8 1 type Unit Type is range 0 2x xx5 1 type Device Function Type is range 0 2xx3 1 For standard operation the PCI interface only works in a limited address range The address range for such initiator transaction is limited to addresses between 0xA0000000 and OxF0000000 PCI addresses outside of this predefined range can be accessed only via DMA transactions Any access to a mem
13. Register Initial Values 3 Mee 4 begin 5 xA 6 Byte Wide Device Control Register Mirror Reset True 7 Byte Wide Device Control Register Byte Wide Device Control Register Mirror 8 It must be noticed that updates may in principle be performed by several tasks in a concurrent way so that race condition situations may consequently arise Therefore both updates must be atomic and thus a protected object should be used to encapsulate them 3 4 Example As an example consider a 3 axis robotic arm with a grabber claw 4 DC motors 4 limit or reference switches and 4 pulse counter switches for travel measurement The robotic arm is connected through 8 digital inputs to read the status of the 8 switches and 8 digital output to command the 4 digital motors There are 3 different motor commands and one unused code The digital inputs and outputs are grouped in bytes mapped onto the I O address space and it can thus be considered the status and control register of the robot The following Ada package is a self explanatory abstraction of the robot Listing 3 1 Register layout definition 1 package Robot is 2 3 type Type Switch is On Off 4 type Type Motor Turntable is Stop Counterclockwise Clockwise 5 type Type Motor Horizontal Axis is Stop Backward Forward 6 type Type Motor Vertical Axis is Stop Upward Downward 7 type Type Motor Gripper is Stop Open Close 8 9 type Type Robot Status Register is
14. VMlab UPM TRI Last Modified on September 23 2009 page 75 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 However in order to avoid common building problems there are several tools that can be used to generate builds in a repeatable and consistent manner such as GNU Make or better the GNAT tools for project management GNAT provide an Integrated Development Environment called GPS that can be configured for using ORK There is also a GNAT command based tool called GPRBuild Though GNU Make is simple widely known and can also be used to manage the build process of ORK applications GNAT tools are recommended for the construction of large multilanguage such as Ada assembler C applications The remaining sections in this chapter will explain how to define an automated build process for ORK driver development using GNAT tools 6 1 Source code arrangement The driver source directory tree can be placed in any location on your system Let us suppose that it is usr local gnatforleon src drivers grspw The application which uses the driver will be also located in any location Let us suppose that itis home projects spw communication grspw test A valid ORK cross compilation system needs to be installed and the ORK bin directory must be added to the search path usually the PATH environment variable For more details of ORK installation see the GNATforLEON ORK User Manual R3 6 1 1 ORK w
15. are used to transfer a number of normal characters N Chars between the AMBA and SpaceWire domains during reception and transmission The low level protocol handling is done by the transmitter and receiver while the FSM in the host domain handles the exchange level N Chars are sent when they are available from the transmitter FIFO and there are credits available The credit counter is automatically increased when FCTs are received and decreased when N Chars are transmitted Received N Chars are stored to the receiver N Char FIFO for further handling by the DMA interface The link interface FSM is controlled through the control register The link can be disabled through a link disable bit which depending on the current state either prevents the link interface from reaching the started state or forces it to the error reset state When the link is not disabled the link interface FSM is allowed to enter the started state Transmitter The state of the FSM credit counters and requests from the DMA interface are used to decide the next character to be transmitted LA normal character is defined in S3 as a data character or control character EOP or EEP that is passed from the exchange level to the packet level VMlab UPM TRI Last Modified on September 23 2009 page 44 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 A transmission FSM reads N Chars for transmission from the transmitter FIFO
16. build process e Compilation phase Each compilation unit is examined in turn checked for consistency and compiled or recompiled when necessary The recompilation decision is based on dependency information that is typically produced by a previous compilation e Post compilation phase or binding During this phase objects are grouped into static libraries e Linking phase All units or libraries are processed by a linker tool specific to the set of tool chains being used Let us consider that driver sources and a test program called spacewiretest adb are in the same directory Then these steps can be performed using gnatmake sparc elf gnatmake spacewiretest You can also compile bind and link separately Sparc aos Up cues den Seea cUPs Ep allen cup cups Up cops Up 00 G P sparc sparc sparc sparc sparc sparc sparc sparc sparc sparc Sparc sparc f gcc c spacewiretest adb f gcc c spacewire hlinterface adb f gcc c spacewire core handler adb sparc sparc el elf gcc c spacewire ads ell elf gcc c spacewire core adb elf gcc c spacewire parameters ads ele Cee sas taboarsad jad ell elf gcc c amba adb elf gcc c spacewire registers adb elt gec e pel culo slr gee wasiralooeiecl lnaimcller aclo elf gcc c rastaboard registers adb lf gcc c pci registers ads elf gnatbind x spacewiretest ali elf gnatlink spacewiretest ali
17. detected by the hardware or the system software Interrupts are said to occur An occurrence of an interrupt is separable into generation and delivery Generation of an interrupt is the event in the underlying hardware or system that makes the interrupt available to the program Delivery is the action that invokes part of the program as response to the in terrupt occurrence Between generation and delivery the interrupt occurrence or interrupt is pending Some or all interrupts may be blocked When an interrupt is blocked all occurrences of that interrupt are prevented from being delivered Certain interrupts are reserved The set of reserved interrupts is implementation defined A reserved interrupt is either an interrupt for which user defined handlers are not supported or one which already has an attached handler by some other implementation defined means Program units can be connected to non reserved interrupts While connected the program unit is said to be attached to that interrupt The execution of that program unit the interrupt handler is invoked upon delivery of the interrupt occurrence While a handler is attached to an interrupt it is called once for each delivered occurrence of that interrupt While the handler executes the corresponding interrupt is blocked While an interrupt is blocked all occurrences of that interrupt are prevented from being delivered Whether such occurrences remain pending or are lost is implementation defin
18. received with the incorrect address are discarded 47 NOTE Initialize sets a default node address of 254 for all devices 48 49 procedure Send Device SpaceWire Device 50 Address Node Address 51 Data Transmitter Data Packet Type 52 Blocking Boolean 53 Send a data packet to a node through a SpaceWire device 54 If Blocking true the calling thread is suspended until the device 55 signals the transmission has been completed Otherwise the call 56 returns immediately 57 Data transmission integrity should be checked at application level 58 59 procedure Receive Device SpaceWire Device 60 Data out Receiver Packet Type 61 Length out Receiver Packet Size Type 62 Receive a data packet from a SpaceWire device 63 The calling thread is blocked until a packet is received 64 65 end SpaceWire HLInterface The operations are implemented in the body of the package as direct calls to core operations Space Wire Registers This is a private package that contains the definitions of all the data types that are needed to specify the Space Wire device registers including those that are used to interface with the AMBA bus as well as the definition of the register structure The fields of the registers and the registers themselves are named as in the document RASTA Interface Board FPGA User s Manual D 10 See this document for the details Operations for reading and writing interrupt registers a
19. representation clauses can be included in the private part of the package In this way implementation details are hidden and readability is improved VMlab UPM TRI Last Modified on September 23 2009 page 25 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 POLIT CNICA Table 67 Interrupt Mask and Priority Register ITMP Address 0x80000090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o imask 15 1 v 2 E ilevel 15 1 olo olo o T INTI S 203 3 2l 8 2 8 BRIBISB E EIS gdi amp g gila ld E E S S S S lt lt 5 SS 3 3 r IF 3 34 r w r w r w rw XXXX XXXX XXXX XXX x XXXX XXXX XXXX XXX x Bit Number Mnemonic Description Interrupt level Str ilevel 15 1 indicates whether an interrupt belongs to priority level 1 ILEVEL n 1 or level 0 ILEVEL n 0 Interrupt mask 15 4 imask 15 1 indicates whether an interrupt is masked or enabled 0 masked 1 enabled Figure 3 1 Interrupt mask register of the AT697E LEON processor reproduced from D7 3 1 2 Register layout After defining the required types the LEON interrupt mask register can be defined in the following way 1 type Interrupt_Mask_Register is 2 record 3 Reservedl Interrupt_Status 4 Correctable Error In Memory Inte
20. the proper values after reset The declared object has to correspond in layout to the actual interrupt mask register which has a fixed address in the address space This is achieved with the following declarations 1 Interrupt_Mask_Register_Address constant System Address 2 System To Address 1648000 00904 3 for Interrupt Mask Address use Interrupt Mask Register Address In this way the object is allocated exactly at the hardware register address The compiler can attempt to optimize the code by reading or writing a local copy of the object instead of the memory address To prevent such optimizations and force the compiler to generate read and write operations at the actual memory address the following pragma must be included 1 pragma Volatile Interrupt_Mask The above representation clauses and pragmas should be enough in the general case However the memory controller MEC of the LEON2 processors raises memory exceptions when undesirable instructions such as STH store half word are generated because accessing the whole word is mandatory The workaround is to use pragma Atomic instead Of pragma Volatile together with using auxiliary or mirror objects in order to always read and update the whole object see next section This is a clean solution although with some small semantic differences 1 pragma Atomic Interrupt_Mask In this way the compiler back end generates word instructions when writing the object because an u
21. 0 can be retrieved from the first 15 Region Map of the Rasta PCI Device 16 17 function Read Interrupt Pending Register 18 Bar0 Interfaces Unsigned 32 return Interrupt Register 19 Used for read which interrupts are currently pending 20 21 procedure Write Interrupt Level Register 22 Bar0 Interfaces Unsigned 32 Data Interrupt Register 23 Used for set the interrupt level register 24 25 procedure Write Interrupt Clear Register 26 Bar0 Interfaces Unsigned 32 Data Interrupt Register 27 Used for clear pendings interrupts 28 29 procedure Write Interrupt Mask Register 30 Bar0 Interfaces Unsigned 32 Data Interrupt Register 31 Used for set the interrupt mask 32 33 end RastaBoard Registers 5 3 4 RastaBoard Handler This is a private package that contains a common interrupt handler for the GR RASTA board devices Upon occurrence of an interrupt the interrupt source is identified and the appropriate device interrupt handler e g the IRQ procedure in SpaceWire Core Handler is invoked The following listing shows a configuration including a serial line driver in addition to the sample SpaceWire driver VMlab UPM TRI Last Modified on September 23 2009 page 60 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 No DU Bun Roa ho 12 NN 0 DUO WNONNNNNNNND A RR a a gt e CSCOmMWAIADMNMPWNrF TO ANANIAHADUNHPWNFY O Listing 5 7 Package RastaB
22. 2 1 Bus architecture Although there are other ways for CPU main memory and I O subsystem to communicate with each other most commonly these subsystems are connected by means of a computer bus or more often a computer bus hierar chy Therefore the bus structure for accessing the I O module interfaces has to be defined before starting the development of device drivers A key issue is the allocation of device registers in the bus address space I O addresses for a single device are always allocated in a contiguous region and all that is needed is to set the so called base address for the device Some modular buses such as VME or EISA provide jumpers or micro switches for manually setting the base addresses However setting up a system wide base on several boards is error prone and must be done carefully Other modular buses such as PCI do not provide such low level mechanisms and the base address is written in registers by using a separate configuration address space The configuration address space uses a so called geographical addressing scheme i e boards are addressed by their physical location which is where the boards are inserted in the bus backplane Locations or slot numbers are hard wired into the backplane It must be noticed that this approach forces a predefined number of addresses for boards and thus can only be used for configuration As a result as part of system startup a routine must initialize the configuration registers in
23. 3 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 end case end record There may be up to 6 different regions in each PCI board type Region Number Type is range 0 5 type Region Map Type is array Region Number Type of Region Device record type type Device Identity is Anonymous Concrete type Device Identity Device Identity Anonymous is record Vendor ID Vendor Code Type Device ID Device Code Type case Identity is when Concrete gt Bus gt Bus Dyoer Umass Unit_Type Device Function Device Function Type Region Map Region Map Type when Anonymous gt null end case end record decur us yeso procedure Initialize PCI Initialize the PCI bus controller in the processor board and then scan the PCI bus in order to locate the RASTA peripheral board function Find RastaBoard return Device Returns a concrete device record with the RASTA board parameters if present or an anonymous device record otherwise This function must be called after the PCI bus has been initialized procedure Set Parity Error Bus Sus JUGE Diada SU mE CIT Device Function Device Function Type Enable parity error detection on a PCI device procedure Set Master Enable Bus SEEDS C Unit 8s miit_ oe VMlab UPM TRI Last Modified on September 23 2009 p
24. 4 2 Interrupt names si s 22 9 mmo a op RR A e ex Re UR RR PUR Res 36 43 Priority ceiling sospes goth a 9x e Red ee Re a oe RR ere dA 38 4 4 Interrupt handlers e script bMS Ru ee AA Ree ow So 38 5 Sample driver 41 24 GRSPW Spacewite ins edes rs Se Roue E Uus qna YU ox Bae Gl eee amp Bey 41 5 Ll Link terface ooo koc REOR Eo Robo oA ee eA a Ro 42 Transmitter PC TT 42 RECOVER a boom So EO d E POP ETE Ce cR IR eos ree WI eae Re 43 2 1 2 Receiver DMA engine i xke RCRUM BOR a A EUER EUR RU 43 Receive descriptor table 2 200 000 0 000 a a 0000 43 Status bits 3 oa Robo n OR a EU em RUE E EUER EL 45 5 1 3 Transmitter DMA engine 45 Transmit descriptor table e 45 5 L4 RMAP esc da a A RAE de DRE n 45 5 41 AMBA interface ss noce ck a ak eA ew a po 47 23 2 DrnyerarchitectUEe e iuo noe sexo ko s Y Y RORIS AR RUNS a RA E AA 47 5 21 Space Wire driver s ox ose a SS ko Eee SOR E E e RR eos RR EG Y E ey SORA 47 23 2 3 RastaBOoamd i BS Sas be ORE Ru RUE y RS eS E RERO TS Re ee Re eo 49 3 4 3 JPGLdnvert o Re RUE RU RUE ee a Re ERREUR EUR UA CR e EUR 49 5 2 4 AMBA driver s boce coina o Ro dom oko SUR eee hee REESE 49 2 9 3900ICe C0d6 okt xe pe S ded xus ca pog dh oe e PREIS ES RP S eg a 50 ll SpacewWite sic fidwts pat bebe Eos d bet S RUD ELS PE Sus SA 50 SpaceWire Parameters ss llle 50 SpaceWire HLTnterface ee u 52 SpaceWire RegistefS nee sy megi ERE HEED RAR 53 SpaceWie COfe
25. Advanced System Bus Automated proof based System and Software Engineering for Real Time applications ASSERT Virtual Machine Base Address Register Bank Address Register APB Compact Peripheral Component Interconnect Consultative Committee for Space Data Systems Central Processing Unit Direct Memory Access Debug Support Unit European Cooperation on Space Standardization Enhanced Industry Standard Architecture Error End of Packet End Of Packet Marker Flow Control Token First In First Out Field Programmable Gate Array Finite State Machine GNAT Programming Studio Gaisler Research Gaisler Research SpaceWire GNU is not Unix High Integrity Input Output Interrupt Mask Register I O request Interrupt request Interrupt Service Routine VMlab UPM TRI Last Modified on September 23 2009 page 10 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 LANCE Local Area Network Controller for Ethernet MEC Memory Controller N Chars Normal characters data characters EOP or EEP OBDH On Board Data Handling ORK Open Ravenscar real time Kernel PCI Peripheral Component Interconnect PO Ada Protected Object RASTA Reference Avionics System Testbench Activity RMAP Remote Memory Access Protocol SOIS CCSDS Spacecraft Onboard Interface Services SVAP Software Validation Plan SVEP Software Verification Plan SVVP Software Verification amp Validation Plan VM Virtual Machine VME Versa Module Euro
26. HC EP IE WR EN PACKET LENGTH 31 0 0x4 PACKET ADDRESS Figure 5 4 SpaceWire receive descriptor reproduced from D11 e 24 0 Packet Length The number of bytes received to this buffer Only valid after EN has been set to 0 by the GRSPW e 25 Enable EN Set to one to activate this descriptor This means that the descriptor contains valid control values and the memory area pointed to by the packet address field can be used to store a packet e 26 Wrap WR If set the next descriptor used by the GRSPW will be the first one in the descriptor table at the base address Otherwise the descriptor pointer will be increased with 0x8 to use the descriptor at the next higher memory location The descriptor table is limited to 1 kB in size and the pointer will be automatically wrap back to the base address when it reaches the 1 kB boundary e 27 Interrupt Enable IE If set an interrupt will be generated when a packet has been received if the receive interrupt enable bit in the DMA channel control register is set e 28 EEP Termination EP This packet ended with an Error End of Packet character e 29 Header CRC HC If a CRC error was detected for the header and 0 otherwise e 30 Data CRC DC 1 if a CRC error was detected for the data and O otherwise e 31 Truncated TR Packet was truncated due to maximum length violation e 31 0 Packet Address The address pointing at the buffer which will be used to store the re
27. It is given packet lengths from the DMA interface and appends EOPs EEPs or RMAP CRC values if requested When it is finished with a packet the DMA interface is notified and a new packet length value is given Receiver The receiver detects connections from other nodes and receives characters as a bit stream on the data and strobe signals The receiver is activated as soon as the link interface leaves the error reset state Then after a NULL descriptor is received it can start receiving any characters It detects parity escape and credits errors which causes the link interface to enter the error reset state 5 1 2 Receiver DMA engine The receiver DMA engine reads N Chars from the N Char FIFO and stores them on a DMA channel Reception is based on descriptors located in a consecutive area in memory that hold pointers to buffers where packets should be stored When a packet arrives it reads a descriptor from memory and stores the packet to the memory area pointed by the descriptor Before reception can take place a few registers need to be initialized such as the node address register which needs to be set to hold the address of this SpaceWire node The link interface has to be put in the run state before any data can be sent Also the descriptor table and control register must be initialized Receive descriptor table The GRSPW reads descriptors from an area in memory pointed by the receiver descriptor table address register The register c
28. Mindshare Inc fourth edition 1999 Jos Emilio Salazar Desarrollo de un driver para un sistema espacial de alta integridad Master s thesis Facultad de Inform tica UPM November 2008 In Spanish W Stallings Computer Organization and Architecture Prentice Hall seventh edition 2006 Willis J Tompkins and John G Webster Interfacing Sensors to the IBM PC Prentice Hall 1987 A J van de Goor Computer Architecture and Design Addison Wesley 1989 A D Wilcox 68000 Microcomputer Systems Designing and Troubleshooting Prentice Hall Interna tional Inc first edition 1987 VMlab UPM TRI Last Modified on September 23 2009 page 87 of 85
29. RMAP commands will not be performed in the order they arrive This can happen if a read arrives before one or more writes Since the command handler stores replies in a buffer with more than one entry several commands can be processed even if no replies are sent Data for read replies is read when the reply is sent an thus write coming after the read might have been performed already if there was congestion in the 3A complete description of the protocol can be found in the RMAP Standard S2 VMlab UPM TRI Last Modified on September 23 2009 page 47 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 31 16 15 14 13 12 11 8 7 0 0x0 CC LE 18 wR EN NON CRC BYTES HEADER LENGTH 31 0 0x4 HEADER ADDRESS 31 24 23 0 0x8 DATA LENGTH 31 0 OxC DATA ADDRESS Figure 5 5 SpaceWire transmitter descriptor reproduced from D11 e 7 0 Header Length Header Length in bytes If set to zero the header is skipped e 11 8 Non CRC bytes Sets the number of bytes in the beginning of the header which should not be included in the CRC calculation This is necessary when using path addressing since one or more bytes in the beginning of the packet might be discarded before the packet reaches its destination e 12 Enable EN Enable transmitter descriptor When all control fields address length wrap and crc are set this bit should be set While the bit is set the descri
30. Size clause guarantees that at least 32 bits are used for objects of the type The Alignment clause guarantees that aliased imported or exported objects of the type will have addresses divisible by 4 In order to avoid compiler optimizations that can lead to an improper layout the following pragma must be included 1 pragma Pack Interrupt_Mask_Register VMlab UPM TRI Last Modified on September 23 2009 page 27 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Pragma Pack specifies that storage minimization should be the main criterion when selecting the representation of the composite type The components should be packed as tightly as possible subject to their sizes and subject to the record representation clauses The GNAT compiler generates initialization procedures for objects of packed Boolean array types and record types that have components of these types Therefore the following specific GNAT pragma must be used in order to avoid undesirable initialization which would result in improper values being set in the hardware register 1 pragma Suppress Initialization Interrupt Mask Register 3 2 Device registers mapping Now that the type has been completely defined it is possible to define the object for the actual register This is done with an Ada object declaration 1 Interrupt_Mask Interrupt_Mask_Register As above explained initialization is usually undesirable because the hardware sets
31. _Register use 47 record 48 Reference Switch Turntable at 0 range 0 0 49 Reference Switch Horizontal Axis at 0 range 1 1 50 Reference Switch Vertical Axis at 0 range 2 2 51 Reference Switch Gripper at 0 range 3 3 52 Pulse Counter Turntable at 0 range 4 4 53 Pulse Counter Horizontal Axis at 0 range 5 5 54 Pulse Counter Vertical Axis at 0 range 6 6 55 Pulse Counter Gripper at 0 range 7 7 56 end record 57 58 pragma Pack Type Robot Status Register 59 pragma Suppress Initialization Type Robot Status Register 60 61 for Type Robot Control Register use 62 record 63 Motor Turntable at 0 range 0 1 64 Motor Horizontal Axis at 0 range 2 3 65 Motor Vertical Axis at 0 range 4 5 66 Motor Gripper at 0 range 6 7 67 end record 68 69 pragma Pack Type Robot Control Register 70 pragma Suppress Initialization Type Robot Control Register 71 72 end Robot VMlab UPM TRI Last Modified on September 23 2009 page 31 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 If the address of the status and control register is 1648000 80004 the registers can be defined in the following child library unit Listing 3 2 Register mapping with System 2 package Robot Registers is 3 4 Robot Control Register Address constant System Address 5 System To Address 16480 008 000 4 6 7 Robot Status Register Address constant System Address 8 System To Address 16480 008 000 9 10 R
32. age 66 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 232 233 234 235 Device Function Device Function Type Enable master mode for a PCI device end PCI The most important operation in this package is Initialize PCI The body of this operation performs the following initialization operations figure 5 7 1 Initialize the PCI controller on the processor board 2 Scan the PCI bus in order to find the interface board where the SpaceDrivers are located 3 Initialize the memory base addresses for the board Listing 5 10 illustrates how the PCI bus initialization is performed See the document Rad Hard 32 bit SPARC V6 Processor AT697E 7 for the meaning of the register fields wv 00 10 tn ONE WNONNNINNNNND e BR RR RR a A COMA DMPWNrFP TO ANANIAHDUNAHRWNF CO Listing 5 10 Initialize_PCI procedure Initialize_PCI is Local shadows for PCI configuration registers on processor board PCI Initiator Configuration Aux PCI Initiator Configuration Register Memory Base Address 1 Aux Memory Base Address Register Memory Base Address 2 Aux Memory Base Address Register PCI Target Page Address Aux PCI Target Page Address Register PCI Status Command Aux PCI Status Command Register Other local declarations for PCI bus scanning Id Interfaces Unsigned 32 Vendor Vendor Code Type DeviceID Device Code Type Header Interfaces Unsigned 8 Num F
33. age 78 of 85 far Reference VMLAB UPM TR1 a Date 15 09 2009 Issue 5 File Edit Navigate VCS Project Build Debug Tools Window Help O DGAXO sSse l The project contains no scenario variables home projects spw communication grspw testSpaceWire_Test gpr _ project SpaceWire_Test is 2 Project View E x 3 for Languages use Ada v E SpaceWire Test 4 for Source Dirs use home projects spw communication grspw test gt 5 usr local gnatforleon src drivers grspw mer 6 for Object_Dir use home projects spw communication grspw test obj b E usr local gnatforleon src drivers grspw 7 for Exec_Dir use home projects spw communication grspw test exec exec 8 for Source Files use spacewiretest adb 9 amba adb amba ads pci adb pci ads obj 10 pci definitions ads spacewire ads 11 spacewire core adb spacewire core ads 12 spacewire core handler ads a Insert Writable Unmodified 11 aaaaaaa Could not compute predefined paths for this project Subprojects might be incorrectly loaded please make sure they are in your ADA P Pies View pine Ven Figure 6 1 GPS initial window VMlab UPM TRI Last Modified on September 23 2009 page 79 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 7 5 AdaCore The GNAT Pro Company Welcome to GPS 4 3 1 20090114 O Start with default project in directory momerprojects Br w
34. all levels inside a computer system In particular LEON processors use the AMBA bus hierarchy which is shown in figure 2 1 High performance High bandwidth ARM processor on chip RAM B UART Timer y R High bandwidth AHB or ASB APB External Memory D Interface G E Keypad PIO DMA bus master AHB to APB Bridge or ASB to APB Bridge Figure 2 1 A typical AMBA system reproduced from D13 The AMBA specification D13 defines three kinds of buses Advanced High performance Bus AHB this is a high bandwidth bus intended to be used at the top of the hierarchy i e to connect processors with main memory and fast DMA I O devices Advanced System Bus ASB this is also a high bandwidth bus intended for use at the top of the hierarchy However it does not support burst transfers and therefore there is a performance penalty when using it to connect cache memories or burst DMA devices such as GR SpaceWire Advanced Peripheral Bus APB this is a simpler and slower bus intended to be used at the lower levels of the bus hierarchy It usually connects slow I O devices and it communicates with the AHB or ASB through a bridge The ATMEL AT697E LEON2 FT processor has the structure shown in figure 2 2 It uses AHB as the local bus APB as the system bus and PCI as an expansion bus System software is usually unaware of the bus hierarchy aside from the configuration of t
35. allow the usage of the floating point unit within protected proce dure handlers because it was not considered a useful feature as it increases the interrupt handling latency This makes saving and restoring the floating point context unnecessary in interrupt handlers thus making their execution more efficient It is quite unlikely that an interrupt handler needs to use floating point operations However floating point support can be easily added if needed Earlier versions of ORK had a configurable option for building a kernel with floating point support in interrupt handlers It must be noticed that GNAT uses the so called proxy model for servicing entry calls With this approach the task exiting a protected operation executes all the waiting entry calls whose barriers are open on behalf the awaiting tasks re evaluating the barriers every time The proxy model saves context switching and allows a simpler implementation of the kernel However it also requires the floating point unit not to be used in an entry of a protected object containing interrupt handlers The reason is that the entry body is executed as part of the interrupt handler if there is a task awaiting on the entry and the handler opens the entry barrier Should that happen in fact and the interrupt handler used floating point operations the floating point context of the task might be corrupted before the task operation in the entry is executed VMlab UPM TRI Last Modified on Sept
36. ant Config Address 16 0B 84 85 Config Header Cache Line Size constant Config Address 16 0C 86 This is the cache line size of the CPU This is CPU dependant 87 It is important that devices which do DMA have this value 88 89 Config Header Latency constant Config Address 16 0D 90 Specifies the maximum number of PCI cycles the bus master can 91 retann Comezol ito cas lows 92 93 Config Header Header Format constant Config Address 16 0E 94 Single Multi funtion device flag 95 96 Config Header Built In Self Test constant Config Address 16 0F 97 Specifies if the device is BIST Built In Selft Test capable 98 99 These are base addresses for memory maped io maped communications 100 with the device 101 Config Header Base Address 0 constant Config Address 164104 102 Config Header Base Address 1 constant Config Address 164144 103 Config Header Base Address 2 constant Config Address 164184 104 Config Header Base Address 3 constant Config Address 16 1C 105 Config Header Base Address 4 constant Config Address 164204 106 Config Header Base Address 5 constant Config Address 164244 107 108 Config Header Expansion ROM Address constant Config Address 164304 109 Address that the expansion ROM of the device is mapped in 110 111 Config Header Interrupt Line constant Config Address 16 3C 112 The IRQ this device is routed through 113 114 Config Header Interrupt Pi
37. avoid this the RMAP buffer disable bit can be set to force the command handler to only use one buffer which prevents this situation 5 1 5 AMBA interface As described in chapter 2 LEON processors use the Advanced Microcontroller Bus Architecture AMBA bus hierarchy It consists of an APB interface an AHB master interface and DMA FIFOs The APB interface provides access to the user registers The DMA engines have 32 bit wide FIFOs to the AHB master interface which are used when reading and writing to the bus as described in 5 1 2 and 5 1 3 sections The transmitter DMA engine reads data from the bus in bursts which are half the FIFO size in length A burst is always started when the FIFO is half empty or if it can hold the last data for the packet The burst containing the last data might have shorter length if the packet is not an even number of bursts in size The receiver DMA works in the same way except that it checks if the FIFO is half full and then performs a burst write to the bus which is half the FIFO size in length The last burst might be shorter 5 2 Driver architecture Figure 5 6 contains a diagram of the software organization of the GRSPW driver which is an instance of the generic architecture described in chapter 2 The driver has four main components e The PCI driver component which provides data type definitions and operations for reading and writing the PCI configuration registers e The AMBA driver component which provi
38. ceived packet VMlab UPM TRI Last Modified on September 23 2009 page 46 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Status bits When the reception of a packet is finished the enable bit in the current descriptor is set to zero When enable is zero the status bits are also valid and the number of received bytes is indicated in the length field The DMA control register contains a status bit which is set each time a packet has been received Also an interrupt for this event can be generated as mentioned before 5 1 3 Transmitter DMA engine The transmitter DMA engine reads data from the AHB bus and stores them in the transmitter FIFO for transmission on the SpaceWire network Before transmissions can be done the descriptor table address register needs to be written with the address to the descriptor table Also one or more descriptors must be enabled in the table Finally the DMA control register must be enabled by setting the Transmitter Enable TE bit Transmit descriptor table Transmission is based on the same type of descriptors as for the receiver and the descriptor table has the same alignment and size restrictions However the transmit descriptors are 16 B in size so the maximum number in a single table is 64 To transmit packets one or more descriptors have to be initialized in memory which is done by setting the number of bytes to be transmitted and a pointer to the data There are two diffe
39. ch December 2005 D13 ARM AMBA TM Specification Rev 2 0 ARM Limited 1999 1 5 Overview The rest of this document is organised as follows e Chapter 2 recalls basic foundations of computer structure to introduce the device drivers functionality and the proposed software architecture e Chapter 3 describes the mechanisms to define map and access device registers in Ada and the peculiarities of the GNATforLEON tool chain e Chapter 4 shows how to handle interrupts in Ada with the restrictions imposed by the Ravenscar Profile and the characteristics of the ORK kernel VMlab UPM TRI Last Modified on September 23 2009 page 12 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 e Chapter 5 describes a sample device driver for the SpaceWire chip of the GR RASTA system e Chapter 6 provides guidance about organising device driver source code as well as about compilation and testing e Chapter 7 concludes the report VMlab UPM TRI Last Modified on September 23 2009 page 13 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TRI Last Modified on September 23 2009 page 14 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Chapter 2 Driver architecture The development of a device driver requires a thorough knowledge of the underlying hardware device as well as the supporting facilities of the target operatin
40. common that status and control registers share the same address in the I O address space In this way a read operation on the shared address returns the status register and when writing the control register is updated This may result in some statements causing undesirable effects For example consider the following statement 1 Byte Wide Device Control Register Reset True AsByte Wide Device Control Register has a byte size the compiler generates instructions to read and write the whole register without the need of an auxiliary object The code generated by the compiler is 1 Idub g2 3 g1 2 or g1 64 g1 3 stb g1 g2 3 As a result the complementary status register that shares the address is read the corresponding bit is set to 1 and the status register is written with the result of the or operation In the general case the bit codes are updated with improper values In such cases a mirror object has to be kept with the actual values that have been written to the hardware register In this way updating the hardware register requires updating the mirror object and then updating the hardware register with the mirror object contents 1 gcc 4 1 3 in the current version VMlab UPM TRI Last Modified on September 23 2009 page 29 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 1 Byte Wide Device Control Register Mirror 2 Type Byte Wide Device Control Register Control
41. cular device It is allocated by the 147 eulos c 148 149 Vendor and device codes for the GR RASTA I O board 150 Gaisler Vendor ID constant Vendor Code Type 16 1AC8 151 Rasta Device ID constant Device Code Type 16 0010 152 153 Invalid Vendor ID constant Vendor Code Type 16 FFFF 154 An invalid ID is returned when trying to address an empty PCI slot 155 156 157 Device address region 158 159 160 The device registers can be mapped to memory address space or I O 161 address space 162 type Region Mapping Mode is Memory Mapped IO Mapped Not Mapped 163 164 This type contains the mapping of the board address space to either 165 the memory or the I O address space in the processor 166 The LEON2 processor only allows memory mapped regions 167 type Region Mapping Mode Region Mapping Mode Memory Mapped is 168 record 169 case Mapping Mode is 170 when Memory Mapped IO Mapped gt 171 Size Interfaces Unsigned 32 172 case Mapping Mode is 173 when Memory Mapped gt 174 Memory Address System Address 175 when IO Mapped gt 176 IO Address System Address 177 when Not Mapped gt 178 null 179 end case 180 when Not Mapped gt 181 null VMlab UPM TRI Last Modified on September 23 2009 page 65 of 85 Reference VMLAB UPM TRI Date 15 09 2009 Issue 5 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 20
42. des data type definitions and operations for scanning the AMBA configuration records e The RastaBoard driver component which provides a common interface for drivers using the GR RASTA board as well as hooks for interrupt handlers to be called upon reception of the single hardware interrupt issued by the board e The SpaceWire driver component which provides all the software items required by application programs to initialize and use the SpaceWire cores included in the GR RASTA computer platform The functionality of these components is described in more detail in the rest of this section Section 5 3 contains a description of the main features of the implementation source code 5 2 4 SpaceWire driver As explained in section 2 3 the components of the SpaceWire driver are e HLinterface contains the higher level interface for application programs The SpaceWire interface consists of Type definitions for the device and node addresses and for receive and transmit data packets Operations for initializing the SpaceWire devices setting their node addresses and sending and receiv ing data packets VMlab UPM TRI Last Modified on September 23 2009 page 49 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 SpaceWire Parameters HLinterface Figure 5 6 Space Wire driver architecture VMlab UPM TR1 Last Modified on September 23 2009 page 50 of 85 Reference VVLAB UPM TRI Date
43. e board has three SpaceWire devices VMlab UPM TRI Last Modified on September 23 2009 page 51 of 85 Reference VVLAB UPM TRI VS Date 5 09 2009 Issue 7 5 5 3 Source code The implementation source code of the SpaceWire driver is organized as a set of Ada packages There are four root packages namely SpaceWire RastaBoard PCI and AMBA from which the internal components of each subsystems are defined as package hierarchies The rest of this section contains a description of the specification and implementation of every package Only segments of code that are significant for the description are shown here The reader is referred to the source files for the full details 5 3 1 SpaceWire The SpaceWire package provides a root name for the SpaceWire package hierarchy It is declared as Pure which means that the package can be preelaborated i e its declaration is elaborated before any other library units in the same partition and has no internal state Notice that this package contains no further declarations and therefore has no state Listing 5 1 Package SpaceWire This is the root package of the GR SpaceWire driver implementation pragma Restrictions No Elaboration Code package SpaceWire is pragma Pure SpaceWire end SpaceWire AUN SpaceWire Parameters This package contains the definitions of some parameters that can be configured by the application programmer The first set
44. ec Dir use home projects spw communication grspw test exec 8 for Source Files use spacewiretest adb 9 tambo toda aras M caeli Et eile a elm 10 WOCGl Cagqistercs ack als Pol coa Si 11 rastaboard adb rastaboard handler ads 12 rastaboard registers adb 13 rastaboard registers ads spacewire ads 14 spacewire core adb spacewire core ads 15 spacewire core handler ads 16 spacewire core handler adb 17 spacewire hlinterface ads 18 spacewire hlinterface adb 19 spacewire parameters ads 20 spacewire registers ads 21 spacewiretest adb 22 for Main use spacewiretest adb 23 24 package Ide is 25 for Compiler_Command ada use sparc elf gnatmake 26 for Gnatlist use sparc elf gnatls 27 for Gnat use sparc elf gnat 28 for Debugger_Command use sparc elf gdb 29 end Ide 30 31 package Builder is 32 for Default Switches ada use s m 33 end Builder 34 35 package Compiler is 36 for Default Switches ada use gnatylaAbcdefhilklnprsStux 37 Wai YWacimaicw e ene U epaveieie p 38 end Compiler 39 40 end SpaceWire Test This project file indicates e The languages used for source files In this example only Ada is used but other languages such as C or assembler may be also used e The directory containing the sources e The directory for the objects e The directory for the executables e The complete list of source files which includes driver source files a
45. ed Each interrupt has a default treatment which determines the system s response to an occurrence of that interrupt when no user defined handler is attached The set of possible default treatments is implementation defined as is the method if one exists for configuring the default treatments for interrupts An interrupt is delivered to the handler or default treatment that is in effect for that interrupt at the time of delivery An exception propagated from a handler that is invoked by an interrupt has no effect VMlab UPM TRI Last Modified on September 23 2009 page 35 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 If the Ceiling Locking policy see D 3 is in effect the interrupt handler executes with the active priority that is the ceiling priority of the corresponding protected object 4 1 Interrupt support in the ORK kernel The Ravenscar profile only permits the static attachment of interrupt handlers In Ravescar interrupt handlers are statically attached to interrupt sources at program elaboration time by using pragma Attach Handler In general Ada instead interrupt handlers may be dynamically attached to interrupt sources by using Ada Interrupts facilities The use of those facilities is considered dangerous in high integrity systems because incorrect programs may lead to improper interrupt handling Interrupt handlers are declared as parameterless protected procedures attached to an in
46. ember 23 2009 page 41 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TRI Last Modified on September 23 2009 page 42 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Chapter 5 Sample driver As an example a device driver for the GR RASTA SpaceWire device is provided in order to illustrate the use of concepts of the ORK driver development summarized in the previous chapters GR RASTA is a development evaluation platform for LEON2 and LEON3 based spacecraft avionics Pro cessing is provided by the Atmel AT697 LEON2 FT device The GRSPW SpaceWire core interface is provided on a separate FPGA I O board Communication between the boards is done via the Compact PCI cPCI bus as described in section 2 2 2 of this manual For a detailed description of the SpaceWire protocol see the SpaceWire standard S3 5 1 GRSPW Spacewire The GRSPW core provides an interface between an AHB bus and a Space Wire network It is configured through a set of registers accessed through an APB interface and data is transferred through DMA channels using an AHB master interface as shown in figure 5 1 i i 1 Spacewire signals gt AHB master AMBA AHB gt Spacewire CODES e RMAP Ctt l 1 l l 1 Registers APB slave 9 9 AMBA APB Figure 5 1 GRSPW Core reproduced from D11
47. ementation shall document for each interrupt which interrupts are blocked from delivery when a handler attached to that interrupt executes either as a result of an interrupt delivery or of an ordinary call on a procedure of the corresponding protected object The implementation shall document any interrupts that cannot be blocked and the effect of attach ing handlers to such interrupts if this is permitted The SPARC v8 architecture has 15 processor interrupt priority levels and does not have any non maskable hardware interrupts i e interrupt requests will be processed if and only if current processor interrupt priority level is lower than interrupt request priority The System Interrupt Priority range of ORK has 15 priority values corresponding to the LEON2 hardware interrupt priorities i e if a task runs within System Interrupt Priority range the correspond ing lower priority interrupts are blocked because the processor interrupt priority level is set accordingly Those interrupts will be delivered as soon as the running priority is lowered VMlab UPM TRI Last Modified on September 23 2009 page 37 of 85 Reference VMLAB UPM TR1 Date 75 09 2009 Issue 7 5 As ORK is not a threaded kernel kernel operations are performed in the context of the calling task Therefore the only way to make the application run at interrupt priority levels is by specifying a pragma Interrupt Priority for an applicati
48. er can start operating Figure 2 8 provides a general view of the required initialization steps The initialization steps for a sample communications driver are explained in detail in chapter 5 2 5 Integrating drivers in the ASSERT Virtual Machine Device drivers interact with low level hardware and kernel features Therefore they have to be integrated with the real time kernel component of the AVM To this end the source code of all the components of the driver including the bus modules has to be compiled and linked with the kernel code and also with the application code using the GNATforLEON compilation system See R3 for the details Detailed compilation instructions for the sample Space Wire driver are given in chapter 6 VMlab UPM TRI Last Modified on September 23 2009 page 23 of 85 POLIT CNICA Reference VMVLAB UPM TRI Date 15 09 2009 Issue 5 Initialize PCI Configure PCI AMBA bridge Scan AMBA bus Configure device Operate device Figure 2 8 Device initialization VMlab UPM TRI Last Modified on September 23 2009 page 24 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Chapter 3 Device register management A device interface consists of a set of registers which are read loaded from or written stored into with proper values in order to interact with the hardware devices For the sake of program abstraction and readability device reg
49. f general utility The language provides means whereby individual organizations can construct their own libraries All libraries are structured in a hierarchical manner this enables the logical decomposition of a subsystem into individual components The text of a separately compiled program unit must name the library units it requires ALRM Introduction VMlab UPM TRI Last Modified on September 23 2009 page 22 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Driver Parameters HLInterface Interrupt Handler Figure 2 7 Generic driver decomposition HLInterface contains the higher level interface for application programs Parameters contains the definitions of all the parameters that can be configured by the application programmer Core contains all the code that interacts with the device registers in order to implement the I O opera tions Handler contains the device interrupt handler which is invoked on the completion of I O operations Since the GR RASTA board provides a single hardware interrupt this handler is invoked by the board handler at the receipt of an interrupt occurrence Registers contains register and bit field definitions as well as other definitions that can be required to interact with the device 2 4 Bus configuration As explained in the previous sections the peripheral buses must be properly configured and initialized before a device driv
50. f setting proper values in I O module registers but setting up the memory structures for linked I O operations as well Local Area Network Controller for Ethernet VMlab UPM TRI Last Modified on September 23 2009 page 16 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 2 2 Device interface The I O modules or devices have several registers which need to be allocated and make them accessible to the processor Processors may use the same instructions for accessing device registers as for main memory or may have special instructions for accessing device registers Processors with special instructions for accessing device registers have different address spaces for memory locations and for I O device registers This scheme is commonly referred to as isolated I O map additional bus lines typically I O request IOREQ lines are needed to access the I O map Bus cycles using these lines are generated when I O instructions are executed typically named in and out On the other hand the most common approach is to share a single address space for memory locations and VO device registers This is commonly known as memory mapped I O Under this approach load and store instructions are used for accessing both memory and I O devices SPARC processors use memory mapped I O and thus it is possible to use Ada representation clauses see section 3 1 to access I O module registers as shown in chapter 3 2
51. g system or kernel This chapter deals with the underlying hardware devices and gives a description of general hardware devices and the peculiarities of the GR RASTA system Then the functionality of a device driver is summarized and a general software architecture is described 2 1 VO subsystem Computer systems are composed of three mayor subsystems that interact with one another CPU Central Process ing Unit main memory and I O Input Output subsystem The I O subsystem includes the so called peripheral devices or peripherals for short which permit the system to interact with the outside environment or provide auxiliary functions such as timing or additional storage Modern CPUs are general purpose devices and the logic needed to deal with peripherals is typically placed in separate devices called I O modules or I O devices In this way the CPU only includes the logic needed to communicate with the I O modules in a uniform way and leaves the peripherals management to the I O modules The CPU capabilities required to communicate with the I O modules are limited to the ability of reading and writing the I O module registers which make up the I O module interface As a result the I O subsystem of a modern digital computer is built up from the set of I O modules connected to the computer 2 1 1 I O modules Peripheral devices are attached to computers by links to I O modules These links are used to exchange data as well as control and s
52. ge 1 Parameters Number Of Spacewire Cores 11 SpaceWire Cores in the GR Rasta GR CPCI XC4V System 12 13 subtype Byte is Interfaces Unsigned 8 14 15 subtype Node Address is Interfaces Unsigned 8 16 Address of SpaceWire nodes 17 18 type Receiver Packet Size Type is 19 range 1 Parameters Receiver Packet Max Size 20 The size of a receive packet 21 22 type Receiver Packet Type is 23 array Receiver Packet Size Type range lt gt of Byte 24 Receive packet typ 25 26 type Transmitter Packet Data Size Type is 27 range 1 Parameters Transmitter Packet Data Max Size 28 The size of a transmit packet 29 30 type Transmitter Data Packet Type is 31 array Transmitter Packet Data Size Type range lt gt of Byte 32 Transmit packet type 33 34 procedure Initialize Success out Boolean 35 Find and set up all Spacewire devices 36 Returns 37 Success true if devices were found and properly set up 38 Success false otherwis 39 40 procedure Set Node Address Device SpaceWire Device 41 Address Node Address VMlab UPM TRI Last Modified on September 23 2009 page 54 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 42 Set the address of one of the SpaceWire devices 43 This procedure should be called for every device after a succesful 44 MELINA EE Om 45 for those device that are to be used to receive packets 46 Subsequent packets
53. ge 22 22 13 Unused 1 at 0 range 21 21 14 DSU at 0 range 20 20 15 Unused_2 at 0 range 19 19 16 Unused_3 at 0 range 18 18 17 Ee at 0 range 17 17 18 Unused 4 at 0 range 16 16 19 Interrupt Level at 0 range 0 15 20 end record The bit fields are specified by ranges which correspond with the actual position and size of the hardware register Notice that the SPARC v8 architecture has a big endian representation which means that the first byte of a 32 bit word is the most significant one i e the leftmost byte in figure 3 1 The ALRM 13 5 3 defines the numbering of bits in the following way IfWord Size Storage Unit the default bit ordering is implementation defined If word Size gt Storage Unit the default bit ordering is the same as the ordering of storage elements in a word when interpreted as an integer Consequently since the order of the storage elements in SPARC is big endian the default bit ordering in Ada is such that bit O is the leftmost bit in figure 3 1 This is contrary to the usual practice and to the bit numbering in the SPARC manual D6 and the AT697E manual D7 This explains the difference between the numbering of bits in the above listing and the figure The following representation clauses are also needed to specify the total size and the alignment of the register in the I O address space 1 for Interrupt Mask Register Size use 32 2 for Interrupt Mask Register Alignment use 4 The
54. gister as in the following procedure Listing 3 4 Proper register usage with Robot Registers use Robot Registers use Robot procedure Upward is Robot Control Mirror Type Robot Control Register Stop Stop Stop begin while Robot Status Reference Switch Vertical Axis Off loop Robot Control Mirror Motor Vertical Axis Upward ROW Oem Oliets ME ROO RS Omnia Ol ME Oia end loop Robot_Control_Mirror Motor_Vertical_Axis Stop ollo COOL gc Ol em Oita a EMIO end Upward Stop VMlab UPM TRI Last Modified on September 23 2009 page 33 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TRI Last Modified on September 23 2009 page 34 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Chapter 4 Interrupt handling Hardware devices indicate events requiring attention from the CPU by issuing interrupt requests Therefore a key part of device drivers has to deal with interrupt handling Interrupts can be handled in Ada by attaching parameterless protected procedures to hardware interrupt sources In this way parameterless protected procedures are executed when the hardware signals the associated interrupts The dynamic semantics of Ada interrupt handling is fully supported by the ASSERT Virtual Machine The ALRM C 3 defines the dynamic semantics as follows An interrupt represents a class of events that are
55. he plug and play feature However it is important to take into account the endianness of the different buses of the hierarchy as it has a strong influence on the definition of device registers Endianness has to do with byte ordering in multibyte scalar values Some machines store the least significant byte in the lowest byte address this disposition is known as little endian Other machines store the most significant byte in the lowest byte address this arrangement is known as big endian The SPARC v7 and v8 architectures and therefore LEON are big endian This is also the the byte ordering of the AMBA buses in LEON processors However the PCI bus is little endian as it was mainly developed for Intel x86 processors In this way I O device multibyte registers will suffer byte twisting as shown in figure 2 3 This issue must be taken into account for PCI I O device multibyte registers as well as for DMA transfers Accordingly PCI hosts and PCI DMA I O devices must be properly initialized Both terms come from Gulliver s Travels by Jonathan Swift and refer to the ways of slicing boiled eggs open for English breakfast VMlab UPM TRI Last Modified on September 23 2009 page 18 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 AT697 D Cache Memo Controller AMBA Controller AMBA bridge H H Clock H Generator APB Jestemeeees interrupt H E Interrupt Con
56. hed to the specified interrupt When a handler is attached to an interrupt the interrupt is blocked subject to the Implementation Permission in C 3 during the execution of every protected action on the protected object containing the handler The above specification is fulfilled by the ASSERT VM ORK However the following clause ALRM C 3 1 is not supported by the ASSERT VM compiler GNATforLEON A check is made that the corresponding interrupt is not reserved Program Error is raised if the check fails and the existing treatment for the interrupt is not affected In the ASSERT VM Timer 1 and Timer 2 interrupts are reserved for ORK usage They are used to im plement Ada Real Time Clock and timing services Application programs must not attach any handler to these interrupts as it would jeopardize the real time kernel internal operation Since the compiler is not aware of this usage it cannot check this possible error However the static nature of the Ravenscar computational model makes it easy to detect violations of this rule by application programmers The ALRM C 3 1 allows some implementation permissions and the ORK takes advantage of the following one When the pragmas Attach Handler or Interrupt Handler apply to a protected procedure the implementation is allowed to impose implementation defined restrictions on the corresponding protected type declaration and protected body The default configuration of ORK does not
57. ing Languages C ISO IEC 9899 1999 S6 ISO SC22 WGI15 Portable Operating System Interface POSIX ISO IEC 9945 2003 1 44 Other documents D1 ISO IEC Guide for the use of the Ada programming language in high integrity systems Technical report ISO IEC TR 15942 2000 D2 ISO IEC Guide for the use of the Ada Ravenscar Profile in high integrity systems Technical report ISO IEC TR 24718 2005 Based on the University of York Technical Report YCS 2003 348 2003 D3 Christine Ausnit Hood Kent A Johnson Robert G Petit IV and Steven B Opdahl Ada 95 Quality and Style Springer Verlag LNCS 1344 1995 D4 AdaCore GNAT GPL User s Guide 2007 D5 AdaCore GNAT Reference Manual 2007 D6 The SPARC architecture manual Version 8 Revision SAV080SI9308 1992 D7 ATMEL Rad Hard 32 bit SPARC V8 Processor AT697E Rev 4226E AERO 09 06 With errata sheet Rev 4409C AERO 05 08 D8 GR CPCI AT697 Development Board User Manual Version 1 1 June 2005 Gaisler Research Pender Elec tronic Design 2005 D9 GR RASTA Board User Manual Gaisler Research Pender Electronic Design 2007 D10 RASTA Interface Board FPGA User s Manual Version 1 0 0 June 2006 Gaisler Research 2006 D11 GRLIB IP Core User s Manual Version 1 0 16 June 2007 Jiri Gaisler Edvin Catovic Marko Isom ki Kritoffer Glembo Sandi Habinc Gaisler Research 2007 D12 GRSPW Spacewire Codec IP Core User s Manual Gaisler Resear
58. isters have to be represented in an abstract way In this chapter the facilities of the Ada programming language are used to specify the implementation of data types that correspond to the various kinds of device registers which can be found in a particular architecture These facilities are the so called representation clauses which can be used to specify the way Ada objects and types are mapped onto the underlying device registers 3 1 Device register definition In order to illustrate the use of representation clauses the 32 bit LEON interrupt mask register IMASK will be used Its 16 most significant bits can be used to enable or disable the corresponding interrupt in the LEON2 processor figure 3 1 3 1 1 Internal codes The first step is to define an enumeration type that corresponds to the enable and disable status of each IMASK bit 1 type Interrupt_Status is Disabled Enabled In order to ensure that the internal code representation for Disabled and Enabled is 0 and 1 respectively the following enumeration representation clause should be used 1 for Interrupt_Status use Disabled gt 0 Enabled gt 1 Notice that the predefined Boolean type could be used in this case because the language defines the low level representation of False and True to be 0 and 1 respectively However defining an enumeration type provides better readability and is required for multi bit internal codes Furthermore the corresponding
59. ith built in drivers There is a ORK binary distribution which includes a driver library This arrangement has the advantage that users only need to deal with their own sources since the SpaceWire PCI and AMBA hierarchies are included in the ORK run time library For the above mentioned example only the test source file spacewiretest is required to build the test application It can be build by using gnatmake or it can also be compiled bound and linked separately sparc elf gcc c spacewiretest adb sparc elf gnatbind x spacewiretest ali sparc elf gnatlink spacewiretest ali It must be noticed that only the user source files are compiled because the driver files are precompiled and already included in the ORK libraries 6 2 Project file GNAT project management tools require one or more project files describing the characteristics of the user project For a project which uses the Ada driver with the described code arrangement the following project file can be used Listing 6 1 GRPBuild SpaceWire Test Project File l project SpaceWire Test is 3 for Languages use Ada VMlab UPM TRI Last Modified on September 23 2009 page 76 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 4 for Source Dirs use home projects spw communication grspw test 5 usr local gnatforleon src drivers grspw 6 for Object Dir use home projects spw communication grspw test obj 7 for Ex
60. ld definitions as well as other data definitions that may be required to interact with the device 5 2 2 RastaBoard The interface of the RastaBoard component includes a type definition with an operation for attaching the particular driver handlers to the board hardware interrupt handler as well as initialization and configuration operations for the board including the PCI and AMBA bus initialization This component has are two internal components e RastaBoard Registers contains register and bit fields definitions for interrupt support which are common to all devices in the board e RastaBoard Handler contains a first level handler for the board interrupts Upon each interrupt occurrence the particular device handler e g SpaceWire Core Handler is invoked depending on the source that can be identified for the interrupt 52 3 PCI driver The interface of the PCI driver includes data type definitions and operations for initializing the PCI bus and locating the boards connected to it There is an internal component PCI Registers with additional data types and register declarations related to the operation of the PCI bus 5 2 4 AMBA driver The interface of the AMBA bus driver includes a single operation for initializing and scanning the bus as well as some data definitions required to use the bus 4See the companion document 21392 08 UPD TR 01 The ASSERT Virtual Machine for a discussion on blocking calls 5The GR RASTA interfac
61. lhost 2222 gdb load gdb continue While attached normal GRMON commands can be executed using the gdb monitor command Output from the GRMON commands such as the trace buffer history is then displayed on the GDB console VMlab UPM TRI Last Modified on September 23 2009 page 84 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Chapter 7 Conclusions Guidelines for writing device drivers for the ASSERT VM kernel GNATforLEON ORK have been given in the document A sample SpaceWire driver for the GR RASTA board has been described as an example The Space Wire driver has been implemented and tested on real hardware a GR RASTA system VMlab UPM TRI Last Modified on September 23 2009 page 85 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TRI Last Modified on September 23 2009 page 86 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Bibliography Ber05 Mor95 SA99 Sal08 Sta06 TW87 vdG89 Wil87 Daniel Berj n Desarrollo de un subsistema fiable de comunicaci n para sistemas de tiempo real Mas ter s thesis Escuela T cnica Superior de Ingenieros de Telecomunicaci n UPM June 2005 In Spanish Diego Sergio Morilla Programaci n en ada del lance am7990 Master s thesis Facultad de Inform tica UPM May 1995 In Spanish Tom Shanley and Don Anderson PCI System Architecture
62. mber 23 2009 page 69 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 153 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 for Pos in Region_Number_Type Range loop Pos_Aux Config_Address Interfaces Shift Left Interfaces Unsigned 32 Pos 2 Wire Comite Dorel 0 Sls 3e Config Header Base Address 0 Pos Aux l64FFFFFFFFE4 4 Suze ws sReaduContigubword 0r Silo sume Config_Header_Base_Address_0 Pos_Aux if Size 0 or Size 16 FFFFFFFF or Size and 16 FF 0 then Mises CO mite Dorcel 00 Silo Eume Config_Header_Base_Address_0 Pos_Aux 0 else Size not Size 1 Write_Config_Dword 0 Slot func Config_Header_Base_Address_0 Config Address Pos x 4 Addr Addr Addr Size Set latency timer to 64 Aux Read Config Dword 0 Slot func l16 C Aux Aux or 1610004 Write Config Dword 0 Slot func 164Cf Aux Enable response in memory space Aux Read Config Dword 0 Slot func Config Header Command Aux Aux or Interfaces Unsigned 32 Command Memory Write Config Dword 0 Slot func Config Header Command Aux RastaBoard Region Map Pos Size Size RastaBoard Region Map Pos Memory Address System To Address Addr Size end if end lo
63. n constant Config Address 16 3D 115 Which line this device raises interrupts on 116 117 Config Header Minimum Grant constant Config Address 1643Ef 118 A read only register informing of how long the device would like 119 maintain control of the bus as a bus master 120 121 Config Header Maximum Latency constant Config Address 16 3F 122 Specifies how often the device needs to access the PCI bus 123 124 Specifies if this is a multifunction PCI Device 125 Multi Function constant Interfaces Unsigned 8 164801 126 127 Type of devic 128 Class Network constant Device Class 16 02 129 Class Network Ethernet constant Device Class 16 0200 130 Class Network Other constant Device Class 16 0280 131 Class Bridge constant Device Class 16 06 VMlab UPM TRI Last Modified on September 23 2009 page 64 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 132 Class Bridge Host constant Device Class 16406004 133 Class Bridge PCI constant Device Class 16 0604 134 135 136 PCI boar JD 137 138 139 The board ID is stored in the configuration space of the board 140 141 type Vendor Code Type is range 0 16 FFFF 142 This code identifies the manufacturer of the device It is allocated 143 by the PCI SIG 144 145 type Device Code Type is range 0 16 FFFF 146 This code identifies the parti
64. n be downloaded from http libre adacore com libre as part of the GNAT GPL edition As the current version of ORK is based in GNAT GPL 2008 using GNAT GPL 2008 or GNAT GPL 2009 is recommended For more details on GPS see http www adacore com home products gnatpro toolsuite gps After installing GPS 1t can be launched by calling gps SpaceWire Test gpr If the code arrangement corresponds with the project file and ORK bin is in the PATH GPS will start without errors as shown in figure 6 1 It is also possible to launch GPS without any project file and create a new one from scratch In this case the welcome window is shown in figure 6 2 This welcome window is followed by the one shown in figure 6 3 which will query about the type name languages code arrangement etc of the new project After filling all the subsequent query windows the window shown in figure 6 1 is reached The properties of the project have to be modified in order to make GPS use the ORK tool chain instead of the native one To this purpose the name of the native tools must be replaced by the GNATforLEON tools as shown in figure 6 4 The properties window can be reached by clicking on Project and then on Edit Project Properties and finally selecting the Languages tab in the pop up window Now GPS can use the GNATforLEON ORK tool chain as required to develop and build the application VMlab UPM TRI Last Modified on September 23 2009 p
65. nd application source files In this case there is just one application source file containing the test spacewiretest adb VMlab UPM TRI Last Modified on September 23 2009 page 77 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 e The main entry point of the system is in the application source file e The default tool chain that will be used by the Integrated Development Environment GPS as well as the compiler and builder switches GNATMAKE can be used for compiling and building the whole application by using this project file The following command builds the application sparc elf gnatmak PSpaceWire Test gpr The output of the gnatmake execution will show the three steps described at the beginning of this chapter e Several sparc elf gcc commands for compiling the sources files which correspond to the compilation phase e The sparc elf gnatbind command corresponds to the post compilation phase e The sparc elf gnatlink command corresponds to the final link This project file is distributed together with the driver source files In this way it can be adapted to different code arrangements and projects as needed This can be done by using a text editor but it is much more convenient to use GPS for creating or adapting a project This project file was generated with GPS 6 2 1 GPS Integrated Development Environment GPS GNAT Programming Studio is not distributed with ORK but it ca
66. ng I O operations Synchronization can be done by polling I O module status registers However a high amount of processor time may be wasted on waiting until the I O modules are ready to receive or transmit data busy waiting The common alternative is to make I O modules signal their asynchronous events by interrupting the processor through dedicated bus lines interrupt request lines When interrupts are used after the processor issues a command for a peripheral device it switches to doing something else typically switching to another thread of execution When the command is completed the I O module signals an interrupt The processor reacts to the interrupt by saving the execution context of the current thread and transferring control to an Interrupt Service Routine ISR which completes the I O operation possibly by transferring additional data to or from the main memory The ASSERT Virtual Machine kernel provides a mechanism for setting user defined procedures as ISR for the 11 interrupt sources available in the LEON processor The standard Ada interrupt support approach is used for this purpose as explained in chapter 4 2 1 3 DMA I O operations An I O operation on a block peripheral device implies transferring a large amount of data typically several hun dreds or even thousands of bytes In these cases it is more effective to directly transfer the data between the I O module and the memory without any intervention from the CPU This
67. ng the languages and tool chains to be used and one or more project files describing the characteristics of the user project For more details about GPRbuild see http www adacore com home products gnatpro toolsuite gprbuild The configuration file can be created automatically by calling gorconfig with the proper ORK switches The following command creates a configuration file named ork cgpr for cross compiling Ada with the full run time and C for the SPARC LEONG processor gprconiig baten target sparc elf config Ada 2008 full usr local gnatforleon bin GNAT N config C 4 1 3 usr local gnatforleon bin GCC 0 Orik END The following command triggers the interactive mode of gprconfig listing all the languages supported by GNATforLEON ORK O Gee i target sparc elf o ork cgpr The above defined SpaceWire Test project can be built by doing gprbuild config ork cgpr PSpaceWire Test 6 3 Test program In order to test a program on the target platform a debug monitor for LEON processors such as GRMON is required GRMON communicates with the LEON debug support unit DSU and enables non intrusive debugging of the complete target system It is started by entering the grmon command in a terminal window By default GRMON communicates with the target using the first UART port of the host This behaviour can be overridden by specifying an alternative device Use the baud option if you need to use a differen
68. nstant Interfaces Unsigned 32 16 10 70 The GR RASTA AMBA AHB APB bridge is an APB bus master according 71 the AMBA 2 0 standard The controller supports up to 16 slaves 72 73 type Max APB Slaves Devices is range 0 AMBA Max APB Slaves 1 74 type AMBA Devices is array Max APB Slaves Devices Range of AMBA Device 75 76 71 AMBA bus operations 78 79 80 function Scan AMBA Bus IOArea Interfaces Unsigned 32 81 return AMBA Devices 82 Scans AMBA Plug amp Play Information 83 IOArea address of AMBA Plug amp Play information 84 85 end AMBA VMlab UPM TRI Last Modified on September 23 2009 page 72 of 85 Issue 5 Reference VVLAB UPM TRI Date 15 09 2009 The Scan AMBA Bus function first finds an APB master device and then scans the slave devices connected to 1t For each slave device found the configuration parameters vendor and device codes IRQ number and IO BAR Bank Address Register are stored into a device description record See reference D11 for the details Listing 5 12 Function Scan AMBA Bus function Scan AMBA Bus IOArea Interfaces Unsigned_32 return AMBA Devices is Pointer Read Memory Word Object Pointer PointerID Read AMBA Identification Object Pointer ConfWord AMBA APB Identification Register ConfWordAPB AMBA APB Identification Register MBar Interfaces Unsigned 32 IOBar Interfaces Unsigned 32 Interfaces Unsigned 32 Inte
69. oard Handler private package RastaBoard Handler is SPW_Callback Handler_Callback UART_Callback Handler_Callback SPW_Handler_Defined Boolean False UART_Handler_Defined Boolean False procedure Hook_SpaceWire_Interrupts Callback Handler_Callback procedure Hook_UART_Interrupts Callback Handler_Callback end RastaBoard Handler Listing 5 8 illustrates the way hardware interrupts are redirected to the appropriate driver handler Listing 5 8 Procedure RastaBoard Handler Handle IRQ procedure Handle IRQ is Pending Interrupt Registers Interrupt Register begin Pending Interrupt Registers Read Interrupt Pending Register RastaBoard To Unsigned 32 RastaBoard RastaBoard_MBar0_Address if SPW Handler Defined then if Pending Interrupt SPW 0 then SPW Callback 1 end if if Pending Interrupt SPW 1 then SPW Callback 2 end if if Pending Interrupt SPW 2 then SPW Callback 3 end if Registers Write Interrupt Clear Register RastaBoard To Unsigned 32 RastaBoard RastaBoard MBar0 Address Reservedl6 gt others gt True SPW 0 gt True SPW 1 gt True SPW_2 gt True others gt False end if if UART Handler Defined then if Pending Interrupt UART 0 then UART Callback 1 Registers Write Interrupt Clear Register RastaBoard To Unsigned 32 RastaBoard RastaBoard MBar0 Address Reservedl16 gt others gt True UART_0 gt True others gt False end if if
70. obot Control Type Robot Control Register 11 for Robot_Control Address use Robot_Control_Register_Address 12 pragma Atomic Robot Control 13 14 Robot Status Type Robot Status Register 15 for Robot Status Address use Robot Status Register Address 16 pragma Atomic Robot Status 17 18 end Robot Registers Now a main procedure for moving the arm upward until the limit in a polling based manner can be coded in the following naive way oo DA Bu 129 Listing 3 3 Naive register usage with Robot Registers use Robot Registers use Robot procedure Upward Naive is begin while Robot Status Reference Switch Vertical Axis Off loop Robot Control Motor Vertical Axis Upward end loop Robot Control Motor Vertical Axis Stop end Upward Naive VMlab UPM TRI Last Modified on September 23 2009 page 32 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 une oo DU Bu n Rh Du huUnNnN 0w0 It must be noticed that the code shown in listing 3 3 commands the vertical axis motor properly but the other 3 motors are also inadvertently commanded with the corresponding bit codes of the Robot_Status register As a result undesirable actions could be performed because the following assembly code is generated by the compiler to start the motor Idub g2 g1 and g1 13 g1 or g1 4 g1 stb g1 g2 The proper way to circumvent the problem is to use a mirror re
71. of configurable parameters is the sizes of the receive and transmit buffers Other parameters are directly related to the GR RASTA hardware configuration and should not be changed unless the hardware configuration is modified VMlab UPM TR1 Last Modified on September 23 2009 page 52 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Listing 5 2 Package Space Wire Parameters This package defines basic parameters used by the SpaceWire driver 2 This is the Rasta GR CPCI XC4V version of this package 3 4 pragma Restrictions No Elaboration Code 5 package SpaceWire Parameters is 6 7 8 Spacewire packet sizes 9 10 11 Receiver_Packet_Max_Size constant Integer 1024 12 Maximum length of receive packet in bytes 13 Must be less than 2xx24 14 15 Transmitter Packet Header Max Size constant Integer 4 16 Maximum length of transmit packet header in bytes 17 Must be less than 2xx8 18 19 Transmitter Packet Data Max Size constant Integer 20 Receiver Packet Max Size Transmitter Packet Header Max Size 21 Maximum length of transmit packet data in bytes 22 23 24 CR CREI KCAV CREAMOS 25 26 27 The following are GR Rasta definitions 28 They must not be modified as long as a GR Rasta board is used 29 30 Number Of Spacewire Cores constant Integer 3 31 Number of Space
72. on of ORK the Open Ravenscar real time Kernel which supports the Ada Raven scar profile as defined in the current Ada 2005 standard It is integrated with the GNATforLEON compilation system and provides full support for the Ada Ravenscar subset including low level and system programming facilities The document shows how to develop device drivers in Ada using such facilities The guidelines are il lustrated with the development of a communications driver for a SpaceWire device which is part of the GR RASTA LEON2 computer board VMlab UPM TR1 Last Modified on September 23 2009 page 3 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TRI Last Modified on September 23 2009 page 4 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Contents 1 Introduction 7 Ll Purpose 2 9 o9 nsncs9 x BRR eee RR Gode Rome we e Eee le ba 7 1 2 Scope 9 opo EE pup Rom RE NU EURO EERE SEG RPE Eee be aE aes SS 8 13 GIOSSHEy s o tradere eub es dud A SIX Es 8 1 3 1 Acronyms and abbreviations e 8 1 4 Applicable and reference documents 2 en 9 1 4 1 Applicable documents lees 9 1 4 2 Reference documents 9 143 Standards 4 mk bauogos n a a e 590460548 Pacem a S babes B OR 9 1 4 4 Otherdocuments se us ek ee k a Ron RR BR a RO S RR Es 10 lo OVCIVIEW uu eue vetet ehe xe Sup quede heb aE Be MS eser BS dew i du 10 2 Driver architecture 13 2 IOsubsys
73. on task or protected object which is of course not recommended The implementation shall document the treatment of interrupt occurrences that are generated while the interrupt is blocked i e whether one or more occurrences are held for later delivery or all are lost The default response to an interrupt is to deliver it to the default handler The default handler is a null operation i e it does nothing but return back to the interrupted task It must be noticed that if the hardware does not clear the interrupt request automatically when the processor acknowledges it the interrupt will be delivered again As a result the default handler will be executed forever The implementation shall document whether the interrupted task is allowed to resume execution before the interrupt handler returns Interrupt handlers are called directly from the hardware and are executed as if they were directly invoked by the interrupted task but using the interrupt stack Therefore the interrupted task cannot resume before the handler returns There is the following implementation advice It is a bounded error to call Task Identification Current Task see C 7 1 from an inter rupt handler The ORK kernel raises Program Error as is recommended for detected bounded errors It must be noticed that an exception propagated from an interrupt handler has no effect This rule is modelled after the rule about exceptions propagated out of task bodies
74. onsists of a base address and a descriptor selector The base address points to the beginning of the area and must start on a kB aligned address It is also limited to be 1 kB in size which means that the maximum number of descriptors is 128 The descriptor selector points to individual descriptors and is increased by 1 when a descriptor has been used figure 5 3 When the selector reaches the upper limit of the area it wraps to the beginning Each descriptor is 8 B in size and is enabled by setting the address pointer to a location where data can be stored and then setting the enable bit An interrupt will be generated when a packet has been received if the receive interrupt enable bit in the DMA channel control register is set and if the Interrupt Enable IE field is set in the descriptor The contents of the receive descriptor can be seen in figure 5 4 2Packets received with the incorrect address will be discarded VMlab UPM TRI Last Modified on September 23 2009 page 45 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 63 127 SpaceWire Receive descriptor o eo n e 126 SpaceWire Receive descriptor 63 f 0 descriptor selector r F gt 2 SpaceWire Receive descriptor 63 0 1 SpaceWire Receive descriptor 63 0 base address z z z 0 SpaceWire Receive descriptor Figure 5 3 SpaceWire receive descriptor table 31 30 29 28 27 26 25 24 0 0x0 TR DC
75. op end if end if end loop end if end loop end Initialize PCI VMlab UPM TRI Last Modified on September 23 2009 page 70 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 PCI Registers This is a private package that contains field and register type definitions for the PCI controller of the GR RASTA system processor board AT697 The details on the register structure can be found in the RASTA Interface Board FPGA User s Manual D 10 5 3 6 AMBA This package contains data type definitions for accessing the devices connected to the AMBA bus in the RASTA interface board The only operation provided by this package is the function Scan AMBA Bus which returns an array of devices connected to the bus Listing 5 11 Package AMBA 1 2 with System 3 with Interfaces 4 5 package AMBA is 6 7 use type Interfaces Unsigned 8 8 use type Interfaces Unsigned 16 9 use type Interfaces Unsigned 32 10 11 12 Data Envases 13 14 15 type AMBA_Vendor_Type is mod 2 xx 8 16 for AMBA Vendor Type Size use 8 17 Used for vendor ID 18 19 type AMBA Device Type is mod 2 xx 12 20 for AMBA Device Type Size use 12 21 Used for device ID 22 23 type AMBA Version Type is mod 2 xx 5 24 for AMBA Version Type Size use 5 25 Used for version number 26 27 type IRO Type is mod 2 xx 5 28 for IRQ Type Size use 5 29 Used for interrupt routing information 30
76. order to properly set up the system I O configuration This capability is usually known as plug and play The cPCI modular bus of the GR RASTA system has a set of configuration registers that are accessed by geographical addressing and therefore a plug and play routine has to be developed in order to initialize the operation of I O devices On the other hand the the Advanced Microcontroller Bus Architecture AMBA bus which is also part of the GR RASTA subsystem uses a centralized address decoding scheme and therefore the AMBA plug and play routine does not have to set up any address registers Its main function is to explore the AMBA configuration records of the devices in order to find their preassigned base addresses It is worth mentioning that other bus configuration features such as interrupt request lines bus request lines etc are also set up in the same way 2 2 3 Bus hierarchy Computer systems with a large number of devices with transfer speeds several orders of magnitude apart use multiple buses instead of a single bus interconnecting all the devices These buses are generally laid out in a VMlab UPM TRI Last Modified on September 23 2009 page 17 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 hierarchy with the higher speed bus at the top and the lower speed buses at the bottom In this way there is no loss of performance due to bus length and saturation Bus hierarchies can be found at
77. ory address in the PCI address range is automatically translated by the interface into the appropriate PCI transaction In this configuration the PCI bus is accessed by the same instructions as the main memory The SPARC instruction set foresees various load store instruction types The PCI bus foresees 32 bit wide transactions with byt nables for each byte lane VMlab UPM TRI Last Modified on September 23 2009 page 62 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 POLIT CNICA 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 PCI_Mem Start constant Interfaces Unsigned 32 16 A0000000 PCI Mem End constant Interfaces Unsigned 32 16 F0000000f type Config Address is range 0 2597 Allows the system to identify and control the device type PCI_Command is new Interfaces Unsigned_32 PCI Commands to control the device type Device Class is new Interfaces Unsigned 16 Identifies the type of devic E PCI Configuration Headers Config Header Vendor ID constant Config Address 16 00 A unique number describing the originator of the PCI device Config Header Device ID constant Config Address 16 02 A unique number describing the device itself Config Header Command constan
78. pa IEEE 1014 1 4 Applicable and reference documents 1 4 1 Applicable documents A1 Lab activities Improvement and documentation of the ASSERT Virtual Machine ESTEC Statement of Work TEC SWE 07 104 MP IIR3 3 September 2007 A2 Improvement and Documentation of the ASSERT Virtual Machine Proposal for ESA Statement of Work Ref TEC SWE 07 104 MP University of Padova cole Nationale Sup rieure des T l communications Universidad Polit cnica de Madrid I1 R4 7 January 2008 1 4 23 Reference documents R1 ASSERT D3 3 2 2 Virtual Machine Architecture Definition 11R1 July 2007 R2 ASSERT D3 3 2 3 Virtual Machine Components Specification I1 R1 July 2007 R3 GNATforLEON ORK User Manual Version 1 1 18 November 2008 Available at http www dit upm es ork R4 PolyORB HI User s Guide Available at http aadl enst fr 1 4 3 Standards S1 ECSS E ST 40C Space engineering Software March 2009 S2 ECSS E 50 11 Draft F Remote Memory Access Protocol RMAP December 2006 S3 ECSS E ST 50 12C SpaceWire Links nodes routers and networks July 2008 S4 ISO SC22 WG9 Ada Reference Manual Language and Standard Libraries Consolidated Standard ISO IEC 6652 1995 E with Technical Corrigendum 1 and Amendment 1 2005 VMlab UPM TRI Last Modified on September 23 2009 page 11 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 S5 ISO SC22 WG14 Programm
79. pdate of an atomic object is indivisible from a concurrency point of view Nothing is said in ALRM C6 about the reading of the object however tests have shown that reading the object is also atomic when using the pragma VMlab UPM TRI Last Modified on September 23 2009 page 28 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 3 3 Device registers access 3 3 1 Mirror objects In the general case accessing a hardware register is just a matter of using the corresponding object which can be included in general Ada statements However the ASSERT Virtual Machine compiler can generate instructions that access a half word or a byte when reading the registers This would cause the MEC to raise a storage error exception In order to avoid such incorrect behavior an auxiliary mirror object has to be used in order to read and update the register as illustrated in the following example 1 Noes 2 Interrupt_Mask_Mirror Interrupt_Mask_Register Interrupt_Mask 3 Declaration of a mirror object initialized with 4 the actual value of the register 5 T 6 begin 7 ees 8 if Interrupt_Mask_Mirror External_Interrupt_2 Disabled then 9 Interrupt_Mask_Mirror External_Interrupt_2 Enabled 10 Interrupt_Mask Interrupt_Mask_Mirror 11 Compiler generates word instructions for updating 12 the object due to pragma Atomic 13 end if 14 3 3 2 Shared addresses It is quite
80. procedure Unmask SpaceWire Interrupts Unmask SpaceWire interrupts in the IOBoard interrupt mask register SpaceWire interrupts will come in to AT697 through External Interrupt 1 procedure Unmask UART Interrupts Unmask APB UART interrupts in the IOBoard interrupt mask register UART interrupts will come in to AT697 through External Interrupt 1 procedure Hook SpaceWire Interrupt Callback Handler Callback Set the SpaceWire interrupt handler procedure Hook UART Interrupt Callback Handler Callback Set the UART interrupt handler private 42 end RastaBoard VMlab UPM TRI Last Modified on September 23 2009 page 59 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 5 3 3 RastaBoard Registers This is a private package that contains field and register type definitions for the interrupt registers of the GR RASTA board AT697 The details on the register structure can be found in the RASTA Interface Board FPGA User s Manual D 10 Listing 5 6 Package RastaBoard Registers private package RastaBoard Registers is 2 3 field and register type definitions 4 5 6 7 Interrupt register operations 8 9 10 The Gaisler Research Multi processor Interrupt Ctrl is configured 11 through a set of registers accessed through the APB interface 12 These registers can be accesed from Bar0 IRQ Offset 13 14 In the GR RASTA System Bar
81. ptor should not be touched since this might corrupt the transmission The GRSPW clears this bit when the transmission has finished e 13 Wrap WR If set the descriptor pointer will wrap and the next descriptor read will be the first one in the table at the base address Otherwise the pointer is increased with 0x10 to use the descriptor at the next higher memory location e 14 Interrupt Enable IE If set an interrupt will be generated when the packet has been transmitted and the transmitter interrupt enable bit in the DMA control register is set e 15 Link Error LE A link error occurred during the transmission of this packet e 16 Calculate CRC CC If set two CRC values according to the RMAP specification will be generated and appended to the packet The first CRC will be appended after the data pointed to bye the header address field and the second is appended after the data pointed to by the data address field e 31 0 Header Address Address from where the packet header is fetched Does not need to be word aligned e 23 0 Data Length Length of data part of packet If set to zero no data will be sent If both data and header lengths are set to zero no packet will be sent e 31 0 Data Address Address from where data is read Does not need to be word aligned VMlab UPM TRI Last Modified on September 23 2009 page 48 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 transmitter To
82. re also provided by this package SpaceWire Core This private package contains all the functionality required to operate the SpaceWire devices Listing 5 4 Package SpaceWire Core This version of the package is for the GR RASTA Interface board with SpaceWire Parameters with SpaceWire HLInterface Du hu nr with AMBA VMlab UPM TRI Last Modified on September 23 2009 page 55 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 with Ada Unchecked_Conversion 10 with Interfaces 11 with System 12 13 private package SpaceWire Core is 14 15 16 Interface operations 17 18 19 function Initialize return Boolean 20 Initialize all SpaceWire devices 21 22 procedure Set Node Address SPWDevice HLInterface SpaceWire Device 23 Address HLInterface Node Address 24 Set the node address of a SpaceWire Device 25 26 procedure Send SPWDevice HLInterface SpaceWire Device 27 Address HLInterface Node Address 28 Data HLInterface Transmitter Data Packet Type 29 Blocking Boolean 30 Send a data packet through a SpaceWire device link 31 32 procedure Receive SPWDevice HLInterface SpaceWire Device 33 Data out HLInterface Receiver Packet Type 34 Length out HLInterface Receiver Packet Size Type 35 Receive a data packet from a SpaceWire device link 36 Receive is always blocking 37 38 private 39 40
83. rectable Error In Memory Priority constant System Interrupt Priority 67 System OS Interface Correctable Error In Memory Priority 68 69 DSU constant Interrupt ID 70 Interrupt ID System OS Interface DSU 71 DSU_Priority constant System Interrupt_Priority 72 System OS_Interface DSU_Priority 73 74 PCI constant Interrupt ID 75 Interrupt ID System OS Interface PCI 76 PCI Priority constant System Interrupt Priority 77 System OS Interface PCI Priority 78 79 end Ada Interrupts Names 4 3 Priority ceiling ORK supports Ada programs that are compliant with the Ravenscar computational model The Ravenscar profile requires the Ceiling Locking policy to be in effect when protected objects are accessed The standard defines a specific dynamic semantics for interrupt handlers ALRM C 3 1 If the Ceiling Locking policy see D 3 is in effect then upon the initialization of a protected object for which either an Attach Handler or Interrupt Handler pragma applies to one of its procedures a check is made that the ceiling priority defined in the protected definition is in the range of System Interrupt Priority If the check fails Program Error is raised If the Ceiling Locking policy see D 3 is in effect and an interrupt is delivered to a handler and the interrupt hardware priority is higher than the ceiling priority of the corresponding protected object the execution of the program is erroneous In order to a
84. rent length and address fields in the transmit descriptors because there are separate pointers for header and data The maximum header length is 255 B and the maximum data length is 16 MB 1 When the pointer and length fields have been set then the enable field should be set to 1 to enable the descriptor The internal pointer which is used to keep the current position in the descriptor table can be read and written through the APB interface This pointer is set to zero during reset and is incremented each time a descriptor is used It wraps automatically when the 1 kB limit for the descriptor table is reached The contents of the transmit descriptor is shown on figure 5 5 5 1 4 RMAP The Remote Memory Access Protocol RMAP is used to implement access to resources in the node via the SpaceWire Link The aim of the RMAP protocol is to standardize the way in which SpaceWire units are configured and to pro vide a low level mechanism for the transfer of data between two SpaceWire nodes It has been designed to provide remote access via a SpaceWire network to memory mapped resources on a SpaceWire node It provides three operations write commands read commands and read modify write commands These are posted operations which means that a source does not wait for an acknowledge or reply It also implies that any number of operations can be outstanding at any time and that no time out mechanism is implemented in the protocol There is a possibility that
85. rfaces Unsigned 32 APBMaster CFG AreaAPB Word Size constant Interfaces Unsigned 32 4 AMBA Conf Area constant Interfaces Unsigned 32 164FF0004 AMBA AHB Slave Conf Area constant Interfaces Unsigned 32 1648004 AMBA AHB Conf Words constant Interfaces Unsigned 32 16 8 AMBA APB Conf Words constant Interfaces Unsigned 32 16424 MaxLoops Integer 64 Max 64 devices CFG Area Interfaces Unsigned 32 Devices AMBA Devices begin Address to configuration area IOArea or AMBA Conf Area or AMBA AHB Slave Conf Area CFG Area Scan bus for a maximum of 64 devices MaxLoops 1 loop for i in 0 PointerID ConfWord Read AMBA Identification To Pointer System To Address CFG Area PointerID all if ConfWord Vendor 0 then Pointer Read Memory Word To Pointer System To Address CFG Area Word Size x 4 MBar g Pointer all if ConfWord Vendor Vendor_Gaisler and ConfWord Device Gaisler_APB_Master then Decoding of APB slaves is done using the plug amp play method explained in the GRLIB IP Library User s Manual A slave can VMlab UPM TRI Last Modified on September 23 2009 page 73 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 42 occupy any binary aligned address space with a size of 43 256 lw tes so i Miete 44 45 APBMaster Address From MemBar Start MBar 46 CFG AreaAPB APBMaster or AMBA
86. rrupt Status 5 UART 2 RX TX Interrupt Status 6 UART 1 RX TX Interrupt Status 7 External Interrupt 0 Interrupt Status 8 External Interrupt 1 Interrupt Status 9 External Interrupt 2 Interrupt Status 10 External Interrupt 3 Interrupt Status 11 Timer 1 Interrupt Status 12 Timer 2 Interrupt Status 13 Unused 1 dbsuecesewyelE TShbcuciSp 14 DSU Interrupt Status 15 Unused 2 Toco Sicaicws p 16 Unused_3 Interrupt_Status 17 PCI Interrupt_Status 18 Unused_4 Interrupt_Status 19 Interrupt_Level Unsigned_16 20 end record Where the Unsigned_16 type is assumed to be represented as a 16 bit unsigned integer The order position and size of the basic components must match the actual register layout Ada provides the record representation clause to specify the representation of records The layout of the interrupt mask register can VMlab UPM TRI Last Modified on September 23 2009 page 26 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 be defined as follows 1 for Interrupt_Mask Register use 2 record 3 Reservedl at 0 range 31 31 4 Correctable Error In Memory at 0 range 30 30 5 UART 2 RX TX at 0 range 29 29 6 UART 1 RX TX at 0 range 28 28 7 External Interrupt 0 at 0 range 27 27 8 External Interrupt 1 at 0 range 26 26 9 External Interrupt 2 at 0 range 25 25 10 External Interrupt 3 at 0 range 24 24 11 Timer 1 at 0 range 23 23 12 Timer 2 at 0 ran
87. s The ALRM also sets implementation and documentation requirements C 3 Some of them are applicable to the ORK kernel and are clarified in this section The implementation shall provide a mechanism to determine the minimum stack space that is needed for each interrupt handler and to reserve that space for the execution of the handler This space should accommodate nested invocations of the handler where the system permits this The implementation shall document which run time stack an interrupt handler uses when it exe cutes as a result of an interrupt delivery if this is configurable what is the mechanism to do so how to specify how much space to reserve on that stack In ORK interrupt handlers are always executed using their own interrupt stacks The default size of an interrupt stack is 4 KB but it can be modified by the user by changing the value of System BB Parameters Interrupt Stack Size The procedures for tailoring the kernel and changing this and other parameters is described in the GNATforLEON and ORK user s guide R3 The dynamic semantics of interrupts in Ada implies that the only way that nested invocations of a handler can occur is by calling the handler from the handler itself This kind of self call is allowed by the language but it is dangerous If the hardware or the underlying system holds pending interrupt occurrences the implementation shall provide for later delivery of these occurrences to the program The impl
88. schema called Direct Memory Access DMA is widely used with block devices such as communication devices or disk drives It should be noticed that the I O module must issue an interrupt in order to signal the completion of the I O operation to the CPU The interrupt service routine polls the status registers so as to check if the operation has been successfully completed It is possible to go further in reducing processor involvement in performing I O operations DMA I O oper ations need little processor attention when an operation finishes but issuing commands to I O modules implies transferring not only the command itself but the memory address of the buffer and the amount of data involved as well Therefore it is effective to create a structure in memory with several linked buffers and then send an access to it to the concerned I O module at initialization time In this way the processor only has to command the operation and service the completion interrupt routine Furthermore bidirectional peripheral devices usually manage two sets of linked buffers for input and output operations Some I O modules such as LANCEs awake periodically and check for new output operations by polling the status of the output buffers which in this case are usually called rings Communication devices usually have the ability to deal with so called linked DMA I O operations As a result the initialization procedure is more complex because it is not just a matter o
89. se O Open existing project 10me projects spw communication grspw test SpaceWire Test gpr Y Browse Always show this dialog when GPS starts iis Figure 6 2 GPS welcome window VMlab UPM TRI Last Modified on September 23 2009 page 80 of 85 Reference VMLAB UPM TRI j Date 75 09 2009 Issue 1 5 Select the type of project s to create Project type Naming the project Figure 6 3 GPS create project window VMlab UPM TR1 Last Modified on September 23 2009 page 81 of 85 Reference VVLAB UPM TRI Y Date 15 09 2009 Issue 7 5 Languages Apply changes to d L Show as hierarchy p ject vcs O Autoconf pue C Awk SpaceWire_Test Source dirs f Ele Source files O CH Objects O Changelo gelog Main files O Fortran 90 Library O Gnatdist Make I X Naming Tools TEEN languages compier Click to edit 4 Ada sparc elf gnatmake Scenario compiler Gnatls arcet gnats v Gnat oar tt ma T he gnat driver used to run the variou Debugger sparc elf gdb commands associated with the GNAT E Aceptar Cancelar Figure 6 4 GPS project properties window VMlab UPM TRI Last Modified on September 23 2009 page 82 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 6 2 2 GPRBuild configuration GPRbuild requires a configuration file describi
90. t Config Addres 16 041 Command IO constant PCI Command 16 1 Enable response in I O space Command Memory constant PCI Command 16424 Enable response in Memory space Command Master constant PCI Command 16 4 Enable bus mastering Command Special constant PCI Command 16484 Enable response to special cycles Command Invalidate constant PCI Command 1641014 Use memory write and invalidate Command VGA Palette constant PCI Command 1642014 Enable palette snooping Command Parity constant PCI Command 1644014 Enable parity checking Command Wait constant PCI Command 1648014 Enable address data stepping Command SERR constant PCI Command 16 100 Enable SERR Command Fast Back constant PCI Command 1642004 Enable back to back writes Config Header Status constant Config Address 164061 Status register Config Header Revision constant Config Address 16 08 Revision of the device Class Code Register Diva oee micos Class Config_Header_Class_Prog_Iface specifies which type of device it is Code SubClass Code and Prog I F constant Config Address g T6509 VMlab UPM TRI Last Modified on September 23 2009 page 63 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 82 Config Header Class Subclass constant Config Address 16 0A 83 Config Header Class Basic const
91. t baud rate for the DSU serial link than the default 115200 baud The example below shows how to execute programs with GRMON and a common list of start up switches 9 grmon dsu uart dev ttyS0 baud 115200 Once you get the GRMON console use the 1oad command to download the application and then go to start it The output from the application appears on the normal LEON UARTS and thus cannot be seen on the GRMON console unless the program is started with the u switch You can use terminal emulators such as tip minicom or kermit to display the output The GNATforLEON ORK installation directory is assumed to be usr 1ocal gnatforleon although it can be installed at any other location as well 2GRMON is not free software and it is not part of GNATforLEON 3Device names depend on the host operating system In Unix systems serial devices are named dev ttyXX VMlab UPM TRI Last Modified on September 23 2009 page 83 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 6 4 Debugging Debugging support is available with the GDB version that comes with the GNATforLEON ORK distribution To initiate GDB communications start the monitor with the gdb switch G canoa esu ueute Jokes bauc 115200 ecls Now the debugging session can be started using the extended remote protocol By default GRMON listens on port 2222 for the GDB connection sparc elf gdb hello gdb target extended remote loca
92. tatus information between I O modules and peripheral devices In turn I O modules are connected to the computer through the system bus and their interface to the CPU side consists of several registers Device registers can be classified as Status registers store the status of the attached device The CPU can check the status of a device by reading its status registers Control registers accept commands from the CPU which are decoded by the I O module in order to issue the corresponding request to the peripheral device VMlab UPM TRI Last Modified on September 23 2009 page 15 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Data registers perform data buffering in order to decouple the different transfer rates of the main memory and the peripheral device 2 1 2 VO operations The aim of I O modules is to provide a simple interface to perform I O operations on peripheral devices An I O operation consists in transferring data from main memory to a peripheral device or vice versa The amount of data involved in an I O operation depends on the nature of the peripheral device For instance it can be a byte or character for a keyboard or a fixed length block for a disk drive The key issue is that the timing of I O operations depends on the individual peripheral device and therefore device related events occur arbitrarily As a result the I O modules and the processor need to be synchronized when performi
93. tem ue xh ee ge Row ox dee voe xU x d nex UR Uy e Row odo s 13 2 45 1 VO modules lt s som oe e e Be oe Os O3 b 9 EU YOR A 13 2 4 l Ooperations 22 sos RR RR E RR RT ER ERR RR RE 14 2 3 DMA VO Operations i dev RUE SUPE BA A EX dA 14 2 2 D vicednteiface 2 sos do a m Be RA A a eS 15 2 4 1 Busarchit ctute sls b EE Rn EO ERR Nd EUR be ERO OR m E 15 2 22 Busdbueramchy 2042224 56 ee 2 EGS Se CER xd SIE SUE A S Yu 15 2 2 3 Bus hierarchy in the GR RASTA system ees 18 2 3 Software architecture for device drivers 2 oaoa e ee 20 2 44 Bus configuration 6 es xem e xoxo RR RR eX Vu RR we Ur RON RU e A 21 2 5 Integrating drivers in the ASSERT Virtual Machine llle 21 3 Device register management 23 3 1 Device register definition o s ss es 23 3 1 1 Intemnalcodes our rr a ee ERU 23 3 1 2 Register layout aos A sx O SESS Ned e equ 24 3 22 Device registers mapping ooo a 26 3 3 Dewvicex gisters ACCESS ie o o parena Roy RR e RI X a a L 27 33 1 JMIrtOEODJeCIs us ti Di dete Bate a BE A uy que de RUE amp A n des 27 3 3 2 Shared addresses ee o oe y mom mh oe 27 344 Example ou o YR ose A E EGRE OX A RA E AA 28 VMlab UPM TRI Last Modified on September 23 2009 page 5 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 4 Interrupt handling 33 4 1 Interrupt support in the ORK kernel 2 2 ee 34 4 1 1 Implementation details e 35
94. terrupt source Interrupt sources are identified in the Ada Interrupts Names package In the case of the GNATforLEON compiler this package contains the identifiers of the LEON interrupts A general template is shown in listing 4 1 Listing 4 1 Template for interrupt handlers with Ada Interrupt Names use Ada Interrupt Names 2 EAS eco 3 cena acen 0 4 External Interrupt 0 Priority 5 6 protected Interrupt is 7 8 public protected operations 9 10 private 11 The handler need not be visible outside the protected object 12 procedure Handler 13 Attach the protected handler to an interrupt name 14 pragma Attach Handler Handler External Interrupt 0 15 Set the priority ceiling of the Protected Object 16 As pragma Interrupt Priority is used instead of pragma Priority 17 hardware interrupts are disabled to that level when executing 18 the protected operations 19 pragma Interrupt Priority External Interrupt 0 Priority 20 21 22 other private operations and data 23 24 end Interrupt A ceiling priority must be assigned to the protected object with pragma Interrupt Priority Priorities in the System Interrupt Priority range should only be used for protected objects that contain interrupt handlers The interrupt priority of such a protected object must be equal to or greater than the hardware priority of the interrupt source ALRM C 3 1 The corresponding hardware priority le
95. ting device drivers for the ASSERT Virtual Machine Device drivers need not contain protocols and algorithms They are to be made of simple short and time effective actions Protocols and algorithms are realized in the application code and to fit the ASSERT methodology are to respect the Ravenscar restrictions The Wikipedia gives a good definition of what a device driver is n computing a device driver or software driver is a computer program allowing higher level com puter programs to interact with a hardware device A driver typically communicates with the device through the computer bus or communications sub system to which the hardware is connected When a calling program invokes a routine in the driver the driver issues commands to the device Once the device sends data back to the driver the driver may invoke routines in the original calling program Drivers are hardware dependent and operating system specific They usually provide the interrupt handling required for any necessary asynchronous time dependent hardware interface Writing device drivers requires an in depth understanding of the hardware functionality In order to better illustrate the issues related to hardware and software integration this document includes an example of a phys ical communications driver that can be integrated with the logical communication layer of the ASSERT Virtual Machine The logical communication layer which is part of the ASSERT VM middleware
96. tion sequence VMlab UPM TRI Last Modified on September 23 2009 page 57 of 85 Reference VVLAB UPM TRI Date 75 09 2009 Issue 7 5 blocking Figure 5 8 Send packet Receive Figure 5 9 Receive packet VMlab UPM TRI Last Modified on September 23 2009 page 58 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 5 3 2 RastaBoard Package RastaBoard provides a high level interface for the PCI and AMBA initialization as well as a common support for discriminating between different intrerrupt sources in the GR RASTA board VNo0 DU BuNnN 38 39 40 41 Listing 5 5 Package RastaBoard This package defines a common interface for the PCI and AMBA buses in a board This is the Rasta GR CPCI XC4V version of this package with AMBA with Ada Unchecked_Conversion with Interfaces with System package RastaBoard is type Handler_Callback is access procedure Device Integer Used for calling a device specific interrupt handler procedure Initialize PCI Initialize the PCI bus controller in the processor board and then scan the PCI bus in order to locate the RASTA peripheral board procedure Configure IOBoard Configure memory controller and set the mapping between PCI Master s AHB memory address space and PCI address space function Scan AMBA Bus return AMBA AMBA Devices Scans AMBA Plug amp Play Information
97. to handle peripheral devices and buses Figure 2 6 shows a generic architecture for a communications driver It is modelled after other software ar chitectures that have been successfully implemented for other communications devices Mor95 Ber05 Sal08 A sample driver built on this architecture is described in chapter 5 driver Figure 2 6 Generic driver architecture As shown in the figure there are four components which support the communications device itself the I O board mechanisms the PCI functionality and the AMBA bus respectively It must be noticed that the functionality provided by the PCI hierarchy as well as the AMBA bus exploration can be used by all the drivers to configure and locate PCI and AMBA devices and therefore both PCI and AMBA have their own hierarchy e The AMBA component provides data type definitions and operations for scanning the AMBA configuration records e The PCI component provides data type definitions and operations for reading and writing the PCI configu ration registers e The Board component provides a higher level interface for AMBA and PCI bus initialization as well as hooks for redirecting the board interrupt mechanism to the driver interrupt handler e The Driver component provides all the data and operations that are required to operate the communications device It contains several internal parts fig 2 7 3 An Ada program will normally make use of a library of program units o
98. troller H IPIO H Rs232 E Watchdog 2 l Timers los b e Figure 2 2 AT697 Block Diagram reproduced from D7 AHB bus 31 24 23 16 15 8 7 0 Address 0 Address 3 GRPCI Address 3 Address 0 PCI off chip bus 31 24 23 16 15 8 7 0 Figure 2 3 AMBA bus to PCI byte twisting reproduced from D11 VMlab UPM TRI Last Modified on September 23 2009 page 19 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 JTAG I F UART amp PIO I F cg LEON2 FT m AT69 7 E CONNECTOR DUUE TRANSCEIVER POWER AND REGULATION ETHERNET TRANSCEIVER 5V 2 ao m e n 32 BIT PCI INTERFACE ETHERNET I F PCI VF Figure 2 4 GR CPCI AT697 CPU Board Block Diagram reproduced from D8 2 2 3 Bus hierarchy in the GR RASTA system The GR RASTA is a computer system built on a cPCI backplane bus This modular computer has two cPCI boards GR CPCI AT697 this is the processor board It includes an Atmel AT697 LEON2 FT device as well as memory a debug support unit and some I O devices Its structure is shown in figure 2 4 It has a PCI AMBA bridge to access the cPCI backplane bus GR CPCI XC4V this is an interface board based on a FPGA which has several I O modules including three SpaceWire links Its design is based on an AMBA AHB to which the high bandwidth units are connected Low bandwidth
99. ty 26 27 External_Interrupt_0 constant Interrupt_ID 28 Interrupt ID System OS Interface External Interrupt 0 29 External Interrupt 0 Priority constant System Interrupt Priority 30 System OS Interface External Interrupt 0 Priority 31 32 33 Timers Interrupts 34 35 36 Timer 2 constant Interrupt ID 37 Interrupt ID System OS Interface Timer 2 38 Timer 2 Priority constant System Interrupt Priority 39 System OS Interface Timer 2 Priority 40 4 Timer 1 constant Interrupt ID 42 Interrupt ID System OS Interface Timer 1 43 Timer 1 Priority constant System Interrupt Priority 44 System OS Interface Timer 1 Priority 45 46 47 WARS Ie ESES 48 49 50 UART 1 RX TX constant Interrupt ID 51 Interrupt ID System OS Interface UART 1 RX TX 52 UART 1 RX TX Priority constant System Interrupt Priority 53 System OS Interface UART 1 RX TX Priority 54 55 UART 2 RX TX constant Interrupt ID 56 Interrupt ID System OS Interface UART 2 RX TX 57 UART 2 RX TX Priority constant System Interrupt Priority 58 System OS Interface UART 2 RX TX Priority 59 60 61 Miscelaneous Interrupts VMlab UPM TRI Last Modified on September 23 2009 page 39 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 62 63 64 Correctable Error In Memory constant Interrupt_ID 65 Interrupt ID System OS Interface Correctable Error In Memory 66 Cor
100. unctions Device Function Type Aux Interfaces Unsigned 32 Pos Aux Config Address Size Interfaces Unsigned 32 Addr Interfaces Unsigned 32 PCI Mem Start begin Initialize the PCI configuration on the AT697 processor board Sei PCI Initiator Comtiguraciona Ne PCI_Initiator_Configuration_Aux Reserved2 gt others gt True CMDO gt True VMlab UPM TRI Last Modified on September 23 2009 page 67 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CMD1 gt True Reserved24 gt others gt True others gt True PCI Toiciator Conr ictrarcion s PECL Imilitiecor Comi iewat Lola JURO Set Memory Base Address Registers MBARI amp MBAR2 emory Base Address 1 Aux Base Address 16440000004 emory Base Address 1 Aux MSI False emory Base Address 1 Aux Type Address others gt False Memory Base Address 1 Aux Pref False emory Base Address 1 Memory Base Address 1 Aux emory Base Address 2 Aux Base Address 16460000004 emory Base Address 2 Aux MSI False emory Base Address 2 Aux Type Address others gt False Memory Base Address 2 Aux Pref False emory Base Address 2 Memory Base Address 2 Aux
101. units are connected to the APB It also has a PCI AMBA bridge to access the cPCI backplane bus It must be noticed that I O modules in the GR CPCI XC4V board are accessed through a PCI AMBA bridge As a result data going from I O modules to main memory or CPU cross two PCI AMBA bridges and suffer two byte twists to revert to the original byte order VMlab UPM TRI Last Modified on September 23 2009 page 20 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 LVDS I F LVDS I F LVDS I F SpaceWire SpaceWire SpaceWire Logic AMBA Link Link Link Analyzer Trace Interface Interface Interface Buffer 32 bit AMBA APB 32 bit AMBA APB Memory CAN Mil Std 1553 UART UART GPIO GPIO IRQ Controller 2 0 BC RT MT iti 1 2 1 2 CTRL Interface Controller Interface i i FLASH PROM cay TD SLAM SDHAM CAN 2 0 MIL STD 1553 PCI RS232 JTAG RS232 RS232 VO VO PCIIRQ Figure 2 5 RASTA Interface Board Block Diagram reproduced from D10 VMlab UPM TRI Last Modified on September 23 2009 page 21 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 2 3 Software architecture for device drivers According to the hardware organization described in the previous section a device driver has to deal with peripheral buses in addition to device control data registers and interrupts The software architecture should ideally reflect this organization by providing separate components
102. uxo Roos Peek de e SOROR iR cR RSS OS RP VR ee SB 53 53 2 RastaBoard i sos sa no o mox pm KEE RR EERE OR Rob S OR ER Se E 57 5 3 3 RastaBoard RegisSterS gt ss 22e RR ERR ERR E RE 58 5 3 4 RastaBoard Handler 4 42463 Y RR A A A Oe ws 58 23 PCH desse uu ul x LE quar IN er REO EET UA A 60 PCLROPISIOIS eii Soo P LPS bu Su aes SOR OEIL aded uem ob 18 69 5 3 0 AMBA ore teest be haa ee EROR Ra oup E MER x RN PORTE D EUR does 69 6 Build process 73 6 1 Sourcecodearrangement gt s spo llle ee 74 6 1 1 ORK with built in drivers ers 74 6 2 Projeet less e Grae es Bd ark EB et S e CAR Bure E Ble bth domo ia 74 6 2 1 GPS Integrated Development Environment 0 76 6 2 2 GPRBuildconfiguration 0 0 0 0200000000000 0 0004 81 6 3 Test program daca ean ee dem A ESO GR ME Se ee wee Te ee 81 64 IDEDUSSIO Sin e ha e E VR BOS ee gw amp Ae a Se eee Se 82 VMlab UPM TRI Last Modified on September 23 2009 page 6 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 7 Conclusions 83 Bibliography 85 VMlab UPM TRI Last Modified on September 23 2009 page 7 of 85 Reference VMLAB UPM TRI Date 5 09 2009 Issue 7 5 VMlab UPM TR1 Last Modified on September 23 2009 page 8 of 85 Reference VVLAB UPM TRI im Date 5 09 2009 Issue 7 5 Chapter 1 Introduction 1 1 Purpose This document provides guidelines for wri
103. vels are declared in the package Ada Interrupt Names VMlab UPM TRI Last Modified on September 23 2009 page 36 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 The ORK kernel has 15 priority levels in the System Interrupt Priority range corresponding to the LEON interrupt levels The kernel provides a nested interrupt schema i e a lower priority interrupt handler can be interrupted by a higher priority one Lower priority interrupts are blocked while the application executes within the System Interrupt Priority range On the contrary higher priority interrupt occurrences are delivered to the processor In this way the latency of higher priority interrupts is minimized If the active priority of a running task is equal to or greater than the an interrupt priority the interrupt is not recognized by the processor and thus becomes blocked The interrupt remains pending until the active priority of the running task becomes lower than the priority of the interrupt and only then will the interrupt be recognized by the processor and delivered An important implication of this interrupt model is that users should always use distinct priorities for tasks and interrupt handlers otherwise tasks could delay the handling of interrupts The implication of this correct and important recommendation is that the user should not assign priorities in the Interrupt Priority range to software tasks 4 1 1 Implementation detail
104. void this kind of error the ceiling priority of the object containing the interrupt handler should be made equal to the hardware interrupt priority as defined in Ada Interrupts Names In this way the resulting program is compliant with the Ada dynamic semantics and priority interrupt nesting is enabled It must however be noticed that it is also possible to set the ceiling priority of all protected objects contain ing interrupt handlers to System Interrupt Priority Last However this setting would disable priority interrupt nesting 4 4 Interrupt handlers The Ravenscar profile only allows static attachment of interrupt handlers and thus calls to any of the opera tions defined in package Ada Interrupts are forbidden These operations are 1s Reserved Is Attached Current Handler Attach Handler Exchange Handler Detach Handler and Reference VMlab UPM TRI Last Modified on September 23 2009 page 40 of 85 Reference VVLAB UPM TRI Date 5 09 2009 Issue 7 5 Therefore the only means of attaching interrupt handlers to interrupts is by use of pragma Attach Handler as shown in listing 4 1 page 34 The ALRM C 3 1 defines the following dynamic semantics for protected procedure handlers The expression in the Attach Handler pragma as evaluated at object creation time specifies an interrupt As part of the initialization of that object if the Attach Handler pragma is specified the handler procedure is attac
105. wire Cores in the GR Rasta GR CPCI XC4V System 32 33 Receiver Descriptor Max Entries constant Integer 128 34 The GRSPW core reads descriptors from a area in memory pointed to by the 35 receiver descriptor table address register The register consists of a 36 base address and a descriptor selector The base address is limited to be 37 1 kB in size which means the maximum number of descriptors is 128 Each 38 receiver descriptor is 8 Bytes in size 39 40 Transmitter Descriptor Max Entries constant Integer 64 41 The transmit descriptors are 16 Bytes in size and thus the maximum 42 number of descriptors in a table is 64 43 44 end SpaceWire Parameters VMlab UPM TRI Last Modified on September 23 2009 page 53 of 85 Reference VVLAB UPM TRI Date 15 09 2009 Issue 5 Space Wire HL Interface This package defines the API of the SpaceWire driver Its main elements are the procedures for initializing the SpaceWire configuration Initialize and Set Node Address and for transmitting and receiving data Send and Receive Listing 5 3 Package SpaceWire HL Interface rhis is the High Level Interface of the GR SpaceWire driver implementation 2 Ihis version of the package is for the GR Rasta GR CPCI XC4V board 3 4 with SpaceWire Parameters 5 with Interfaces 6 7 package SpaceWire HLInterface is 8 9 type SpaceWire Device is 10 ran

Guidelines for integrating device drivers - dit/UPM

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