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PQ2FADS-ZU Users Manual - Freescale Semiconductor

1. equations MOTOROLA PQ2FADS ZU User s Manual 143 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IntReg clk SYSCLK IntReg ar 20 IntReg ap 2 0 state diagram SlotOIntA state SlotOlntA Active if HardReset B 2 0 amp Slot lInt PON DEFAULT Slot0IntA_Active HardReset B 0 amp PCI INTA B amp Slot0IntAMask fb SlotOIntAM ask fb then ISlotOlntA Active else SlotOlntA Active state SlotOIntA Active if HardReset B 0 amp Slot lnt PON DEFAULT Slot0IntA_Active HardReset B 0 amp INTA amp Slot0IntAMask fb then SlotOlntA Active else ISlotOlntA Active a state diagram SlotOIntB state Slot0IntB_ Active if HardReset B 2 0 amp Slot0IntB_ PON DEFAULT SlotOlntB Active HardReset B 0 amp B amp SlotOlntBMask fb S
2. OE HHHH HEEE E E HE EHE UE E HHH E EHEHEHE MOTOROLA PQ2FADS ZU User s Manual 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HHH HHHH f f HH 4 HHH HE E HHHH HHHH System Hard Reset Configuration DataOeNODE istype data bus output enable read DataP CIOeNODE istype data bus output enable on PCI read Control Register Enable Protection
3. Device declaration TIARA ARIA RIKKI k x dE GHHHHE OE d HHH x dE f g dg HE HHHH g GG og Ht x EHE HHHH dt x dE Hg g f HH 4 dg UFGHHHHHHE E E HHHH RRR KK Pins declaration System pins TOORAK AIR ARAKI SYSCLK PIN 124 IntContCs B 48 PCI INterrupt Controller CS BrdContRegCs B 47 BCSR CS DVal B PIN 53 RBW 46 BCTLO signal 1 PIN Alternate Buffers Enable source A7 PIN 69 forflash support 104 PQ2FADS ZU User s Manual MOTO
4. Ijoleloleleleteretetetetetetetelelerererererererererererererererererereletelerelelerelerelereleretetetetetetetetetetetetetetereterererererererererererererek k BCSR1 State Machines 134 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information state diagram AtmEn B state ATM ENABLED if WRITE BCSR 16 ENABLE DATA ENABLED 6 RESET ENABLE PON DEFAULT ENABLED RESET ENABLE PON DEFAULT then ENABLED else ATM_ENABLED state ENABLED WRITE BCSR 16 ENABLE DATA ENABLED 6 RESET ENABLE PON DEFAULT ENABLED RESET ENABLE DEFAULT then ENABLED else
5. Power On Reset definitions PON RESET 0 PON RESET 5 PORIn B fb RESET ACTIVE Register Access definitions TRIO KAKA IKARIA RAIA RAIA KARA AAR II AAR AIR BCSRO ADD 0 BCSR1 ADD 1 BCSR2 ADD 2 118 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information BCSR3 ADD 3 BCSR4_ADD 4 WRITE BCSR 0 BrdContRegCs_ amp DVal 61427 amp IA28 amp 1429 VGR_WRITE_BCSR_1 IBrdContRegCs B amp IDVal B amp R amp 1427 61428 amp A29 I WRITE BCSR 2 BrdContRegCs B amp DVal_B amp R_B_W amp A27 amp A28 amp A29 I WRITE BCSR 3 IBrdContRegCs B amp IDVal B amp R_B_W amp IA27 amp A28 amp A29 Li WRITE BCSR 4 BrdContRegCs B amp B amp R B W amp A27 amp A28 6 A29 I READ BCSR 0 BrdContRegCs_B amp R B amp A27 amp A28 amp A29 READ BCSR 1 BrdContRegCs amp A27 amp 1428 amp A29 READ BCSR 2 BrdContRegCs_ amp A27 amp A28 amp A29 READ BCSR 3 IBrdContRegCs B amp W amp A27 6 A28 amp
6. state diagram AtmRst_B state ATM RESET ACTIVE if WRITE BCSR 16 RESET DATA RESET ACTIVE 6 RESET RESET PON DEFAULT RESET RESET amp RESET PON DEFAULT RESET then RESET ACTIVE else ATM RESET ACTIVE state RESET ACTIVE if WRITE BCSR 16 MOTOROLA PQ2FADS ZU User s Manual 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information RESET DATA RESET 6 RESET ATM RESET PON DEFAULT ATM RESET PON RESET RESET PON DEFAULT RESET then ATM RESET ACTIVE else IATM RESET ACTIVE state diagram FEthEn1 B state FETH1 ENABLED iff VGR WRITE BCSR 16 FETH1 ENABLE DATA BIT pin FETH1 ENABLED amp RESET FETH1 ENABLE PON DEFAULT FETH1 ENABLED PON RESET 6 FETH1 ENABLE PON DEFAULT FETH1 ENABLED then IFETH1 ENABLED else FETH1 ENABLED state IFETH1 ENABLED iff VGR WRITE BCSR 16 FETH1 ENABLE DATA FETH1 ENABLED am
7. Slot0IntA_ DATA 00 Slot0IntB_ DATA D1 Slot0IntC_DATA_BIT D2 Slot0IntD_DATA_BIT D3 SlotlIntA_DATA_BIT D4 SlotlIntB DATA D5 SlotlIntC_DATA_BIT D6 SlotlIntD_ DATA D7 Slot2IntA D8 Slot2IntB_ DATA D9 Slot2IntC_DATA_BIT D10 Slot2IntD DATA BIT D11 RAIA ARAKI AAA KARA PCI Interrupt Mask Register definitions TERROR KAKA Slot lntAMask Active 1 PCI Slot 0 Interrupt A Masked Slot lntBMask Active 1 PCI Slot 0 Interrupt Masked Slot lntCMask Active 21 PCI Slot 0 Interrupt C Masked Slot lntDMask Active 21 PCI Slot 0 Interrupt D Masked SlotlIntAMask Active 21 PCI Slot 1 Interrupt A Masked SlotlIntBMask Active 21 PCI Slot 1 Interrupt B Masked SlotlIntCMask Active 21 PCI S
8. AR AKA AAA AR Generating Interrupt Request to the 2 Ijoleloleleletereteretetetetetelererererererererererererererererererereletelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek equations PCI Interrupt SlotOIntA SlotOIntB SlotOIntC SlotOIntD SlotlintA SlotlintB SlotlintC SlotlintD Slot2IntA Slot2IntB Slot2IntC Slot2IntD PCI IRQ B oe PCI Interrupt Open Drain output 166 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IPCI IRQ B Interrupt Interrupt Request shows after OE Auxiliary functions equations KeepP insConnected B amp BCTL1 KeepPinsConnected com m HHH
9. P ower On Defaults Assignments 9 USB ENABLE DEFAULT USB ENABLED USB SPEED PON DEFAULT USB SPEED HIGH USB VCCO PON DEFAULT 058 FETH2 ENABLE PON DEFAULT FETH2 ENABLED FETH2 RESET PON DEFAULT FETH2_ RESET ACTIVE ATM16 ENABLE PON DEFAULT ATM16 ENABLED SINGLE PHY ENABLE PON DEFAULT SINGLE PHY ENABLED Ijolelolelelelereteletereteretererererererererererererererererererelerelerelerelelelek mee Data Bits Assignments rr 05 DATA BIT 00 05 5 DATA D1 USB VCCO DATA BIT D2 FETH2 ENABLE DATA BIT D3 FETH2 RESET DATA BIT D4 ATM16 ENABLE DATA BIT D5 SINGLE PHY ENABLE DATA D6 LOCAL BUS DATA BIT D7 122 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Ijoleloleleletereteretetetetetelererererererererererererererererereretelerelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek PCI Interrupt Register Access definitions TOKO AKAROA AAA ARAKI AR RAHA IntReg ADD 0 In
10. KAKA II AKA IIA ARIK IK equations ClockedContReg clk SYSCLK ClockedC ontR eg ar 0 ClockedC ontR eg ap 0 DrivenContR eg oe hffff 130 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information TOORAK AIR ARAKI KKK IR IR IR IRI KK Ijoleloleleleteretetetetetetetelererererererererererererererererereterelerelerelelerelerelereleretetetetetetetetetetetetetetetetetererererererererererererek BCSR 0 Ijoleloleleleteretetetetetetetelerererererererererererererererereretereletelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek Ijoleloleleleleletetetetetetetelelerererererererererererererererereterelerelerelelerelerelereleletetetetetetetetetetetetetetetetetererererererererererererek equations EKEK EEK state diagram L2Inh_B state L2CACHE INHIBITED if WRITE 06 L2CACHE INH DATA BIT pin L2CACHE INHIBITED amp RESET L2CACHE INH PON DEFAULT L2CACHE_INHIBITED PON RESET 6 L2CACHE INH PON DEFAULT L2CACHE_INHIBITED then 2 INHIBITED else L
11. ATX Power Declarations MOTOROLA PQ2FADS ZU User s Manual 171 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information PowerOn 0 PowerOff 21 KK Equations state diagrams 3 TOKIO OKA AKAROA ARAKI AAA AR AKA AAR GHHHHHHE x dE HH Hh HHH E HHH x dE f ff f ff ff EF x HHH gH ggg HAR x H HHHH go gp gg x dE HEH AEH HEEE HHH AIA ARIK equations TOKO AOKI AKAROA AAR AAA Generating PowerOn signal to the ATX Power Supply
12. EEEE EKEK Read Registers All registers have read capabilty BCSR2 and BCSR4 are read externally MOTOROLA PQ2FADS ZU User s Manual 159 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information TICKERS EEE EEA AICCCR ARR RK equations DataOe VGR READ BCSR 0 VGR READ BCSR 1 READ BCSR 3 HRESET BCSR amp CSO ASSERTED amp DSyncHardReset B fb Data oe DataOe fb when VGR READ BCSR 0 then Data ReadBcsr0 else when VGR READ BCSR 1 then Data ReadBcsrl else when VGR READ BCSR 3 then Data ReadBcsr3 else when FIRST CFG BYTE READ then Data C fgB yte0 elsewhen SCND_CFG_BYTE_READ then Data CfgByte1 else when THIRD CFG BYTE READ then Data CfgByte2 else when FORTH CFG BYTE READ then Data C fgB yte3 DataP 2VGR READ IntReg VGR READ IntMaskR eg DataP Cl oe DataP ClOe fb when READ IntReg then DataP CI IntR eg fb 160 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Fre
13. 4 Be E ja 5 5 E 2 8 5 lets lo 34 14444 gt g 5 g a s E 5 af a S s s 3 8 2 2 2 9 8 PI E gt 485214 d x 2 Sele Bile Sg 578 508 Se 573 T d N 4 999 d q EI gt 22222 gt 22222 57 555 ERRES 507 552 EPERE ERE 5 5 5 B 8 2 E 2 l zzz e zzz 855388 Bos s ERE 88 28993 8 5 d 25888 20 R20UTB 19 18 1 3 22 cue 100nFL__24 2 14 13 2 gt 21L RiourB 2 20 19 48 Xs vpp 24 i 100nF L_ 14 13 2 Rt 10 10k Bl p Bloe b Bs BS P 28 28 8 je E 8 38 8 dt Zd g E 7 MOTOROLA PQ2FADS ZU User s Manual 189 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 4 190 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to w
14. PSHHHHH d m jd m HHH HHH HHHH HHHH d d HEHE HH ii HHHH d f d HHH H HHH T D ifdef SIMULATION 7 3 Schematics Bill Of Materials This sectoin shows the schematicds of the PQ2FADS ZU and the Bill Of Materials 7 3 1 Schematics Following are the schematics of the board 174 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc pierog nz sav4dcod HH ee Bpur vials F CES AER EGER IUS PLUR Y Sd kipana ty sd nam x 5 eed n3 iH k See 54 urge ay ER lt mum qum Fie ied p Yida Dnaz gods i P DE Hw Ta
15. D D mil 1 ja i 1 Rm 10 0 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product o to www freescale com 193 Freescale Semiconductor Inc Support Information g ini m Freescale Semiconductor Inc T ee Terr aW B UEM hE EE Ad 44 I 194 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Freescale Semiconductor Inc MOTOROLA PQ2FADS ZU User s Manual 195 For More Information On This Product o to www freescale com Freescale Semiconductor Inc Support Information rS PRESE TTE Bun a Ia kusa Freescale Semiconductor Inc 196 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product o to www freescale com Support Information Freescale Semiconductor Inc z p sus 002 SI uow Kepung SNMOQ sdn Vind ev jueumoog en 33vusl yy jeyueus 18 viu 9 souy 5
16. equations inv1 inv5 com generating internal clock oscilator inv2 invl com inv3 linv2 com inv4 linv3 com 172 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information inv5 linv4 com counter ar 0 counter ap 0 counter clk 5 when counter fo 255 then counter 0 else counter counter 1 countera ar 0 countera ap 0 countera clk counter fb 0 when countera fb 255 then countera 0 else countera countera 1 counterb ar 0 counterb ap 0 counterb clk countera fb 0 when counterb fb 255 then counterb 0 else counterb counterb 1 Power Buffer ar 0 Power Buffer ap 0 Power Buffer clk counterb fb 0 Power Buffer ChasisPowerln_B H PowerOn 0 0 PowerOn B clk counterb fb 0 PowerOn Power_Buffer fb MOTOROLA PQ2FADS ZU User s Manual 173 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Ijoeloleleleleleteretetetetetelererererererererererererererererereretelerelerelelerelerelerelejetetetetetetetetetetetetetetetetetererererererererererererek m SHHHHHHE x HHH OA k GS ge d
17. x BCSR3 State Machines EKEK state diagram USBEn state USB ENABLED if WRITE BCSR 36 USB ENABLE DATA BIT pin USB ENABLED 6 RESET USB ENABLE PON DEFAULT 058 ENABLED PON RESET amp USB ENABLE PON DEFAULT USB_ENABLED then IUSB ENABLED else 138 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information USB ENABLED state USB ENABLED WRITE BCSR 3 amp Atm16 B USB ENABLE DATA BIT pin USB ENABLED 6 RESET USB ENABLE PON DEFAULT USB ENABLED PON RESET amp USB ENABLE PON DEFAULT USB_ENABLED then USB ENABLED else IUSB ENABLED state diagram USBHiSpd B state USB SPEED HIGH WRITE BCSR 36 USB SPEED DATA BIT pin USB_ SPEED HIGH 6 RESET USB SPEED PON DEFAULT USB SPEED HIGH PON RESET amp USB SPEED PON DEFAU
18. rad MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 179 Freescale Semiconductor Inc Support Information 180 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information T sri cn in His fele z d L zr Jm m dii ru mn Fais mmis mis nas mui 1 HH Hi MOTOROLA PQ2FADS ZU User s Manual 181 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Freescale Semiconductor Inc 182 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Support Information Freescale Semiconductor Inc Sul 40JONPUODIWIIS 22059941 183 PQ2FADS ZU User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information LE a d 1 o Ras fre 2 Freescale Semiconductor Inc eee P me P GOLIE ins dam 4 a EET pibus ini SE 184 PQ2FADS ZU User s Manual
19. 29 3 2 31 Ethernet Port 1 LINK Indicator 19 25 3 2 32 Fast Ethernet Port 2 Full Duplex Indicator 920 25 3 2 33 General Purpose Led 1 Indicator 021 26 3 2 34 Fast Ethernet Port 2 100Base Tx Indicator 1022 26 3 2 35 USB Enabled Indicator 1023 26 3 2 36 Ethernet Port 2 LINK Indicator 024 26 3 2 37 Ethernet Port 2 Tx Rx Indicator LD25 26 PQ2FADS ZU User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 3 2 38 VDDL Indication 2026 nS Me iis 3 2 39 Parallel Port connection LD27 Si SENE PA XE uS 3 2 40 External Debugger Connection Indicator 1028 Section 4 Functional Description 4 1 4 2 4 3 44 4 5 4 6 4 7 4 8 4 9 Reset amp Reset 4 11 Power On ResetPQ2 5 ide ecu pe Qa 4 1 1 1 Power On Reset Configuration 41 2 Hard RESET s as 4 1 2 1 COP JTAG Port Hard Reset 4 1 2 2 Manual Hard Reset
20. Te Sieg ar 2 wauu m m ue 175 PQ2FADS ZU User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information 4 da 1 Ep M a X 176 7 ae phe 2 4 cH 1 x Dg E i il annes E i r d 1 a 4 a i Z Hi 1299 400 1 Dpoc abppoocoanoppcunt as ooo 8 2 IT i im x rr n 5 4 tim Maui MS TIT E lai jo d t 1 ii i PQ2FADS ZU User s Manual k ii LI t inaunnunununno 1 EE zm 5 TR a H asan i sitit m i cO a gum ooo d a E Scol nan ie hers Lira dns aso Bud EEL La us nk For More Information On This Produ
21. ZHNOdOW OHXOQON 12d 3 N35323u 1997 nn 71071997 5 Sot 1949 104 Ur aan lt J 5 RR I Nijngdu AE N33nediu 5 99 zN3 suu Suu AE ZSO1001U 15010011 SOWxsgSTu 5 8048980 5 3 WOG SIMU WOC ET oam noa 00 590710 lt ogxu 3 9 58 lt gt Ls lt gt i 2 lt gt lt gt AA 1531 197 PQ2FADS ZU User s Manual For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Support Information id ded colic i Fy ji m 198 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information T 3 3
22. Ijoleloleleletereteretetetetetelerererererererererererererererererereteletelerelelerelerelerelereletetetetetetetetetetetetetetetetererererererererererererek Reset amp Interrupt Logic Pins TOKO AOKI AKAROA RstDeb1NODE istype keep com reset push button debouncer AbrDeb1NODE istype keep com abort push button debouncer HardResetEnNODE istype enables T S hard reset pin SoftR esetEnNODE istype com enables T S soft reset pin x data buffers enable KAKA IAA IIR SyncHardReset_B NODE istype reg buffer synchronized hard reset DSyncHardReset NODE istype reg buffer double synchronized hard reset HoldO ffCnt2 HoldOffC nt1 HoldOffCntO NODE istype reg buffer data buf en hold off counter 110 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HoldOffTc NODE istype terminal count for that counter x Power On Reset S PORIn B NODE istype reg buffer synced pon reset PCI Interrupt
23. 40 60x SDRAM Connection Scheme NoL2 Cache 43 SDRAM 60x Bus Connection Scheme with L2 Cache 43 60x SDRAM Data Parity Support 42 44244008 3 SR AER 3 e 45 Local Bus SDRAM Connection Scheme 46 Local Bus SDRAM Data Parity 48 FLASH SIMM Connection Scheme 49 E2PROM Connection scheme 51 PET Bus Scheme scared Seba ite edem ede ad 52 RS232 Serial Ports Connector 56 Debug Station Connection Schemes 66 COP JTAG Port Connecter 522 ET FER 67 PO2PFADS ZU Power Scheme xz Rh RR Ee 80 PQ2FADS ZU Bill of Materials 203 PQ2FADS ZU User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures PQ2FADS ZU User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 General Information 1 1 Introduction This document is an operation guide for PQ2FADS ZU board It contains operational functional and general information about the PQ2FADS ZU This board is meant to serve as a platform for s w and h w development for the
24. State_diagram Slot2IntAMask State Slot2IntAMask_Active if VGR_WRITE_IntMaskReg amp Slot2IntAMask DATA BIT pin Slot2IntAMask Active amp HardReset B 2 0 Slot2Int AMask PON DEFAULT Slot2IntAMask_Active HardReset B 0 amp Slot2Int AMask DEFAULT Slot2IntAMask_Active then ISlot2IntAMask Active else Slot2IntAMask_ Active 156 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information State Slot2IntAMask Active if VGR WRITE IntMaskReg amp Slot2IntAMask DATA BIT pin Slot2IntAMask_ Active amp HardReset B 0 Slot2IntAMask_ PON DEFAULT Slot2IntAMask_Active HardReset B 0 amp Slot2Int AMask PON DEFAULT Slot2IntAMask_ Active then Slot2IntAMask Active else ISlot2IntAMask Active state diagram Slot2IntBMask state Slot2IntBMask Active WRITE IntMaskReg amp Slot2IntBMask DATA BIT pin Slot2IntBMask Active amp HardReset 0 Slot2IntBMask PON DEFAULT Slot2IntBMask_Active HardReset B 0 amp Slot2IntBMask PON DEFAULT Slot2IntBMask_Active then Slot2IntB Mask_Active else Slot2IntBMask Active state Slot2IntBMask Active
25. f OF Hh HH HHH dg 112 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information i HEHEHHE HH X d GHHHHE 4 Ro X RdHHHHHE GHHHHHE HHH GHBHHHE H 4 4 GHBHHE HH 4 4 S EHE H IEICE EEE EEE AAR AAA ARICA H L X Z 1 0 Aw Z C D U C D U EEE ERA CCAR SIMULATION 1 Signal groups Add A27 A29 Data 00 07 DataP CI 00 011 ContReg L2Inh_B MOTOROLA PQ2FADS ZU User s Manual 113 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information L2Flush_B L2Lock_B L2Clear B SignaLampO B SignaLampl B AtmEn B AtmRst B Atm16 AtmSinglePHY B FEthEn1l FEthRstl B FEthEn2 B FEthRst2 B RS232Enl 5232 2 USBEn USBHiSpd USBVccO ReadBcsr0
26. PON RESET amp ATM SINGLE PHY ENABLE PON DEFAULT ATM SINGLE PHY ENABLED then ATM SINGLE PHY ENABLED 142 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information else IATM SINGLE PHY ENABLED equations AtmDis B AtmEn_B Atm8 B Atm16 AtmMultiPHY B AtmSinglePHY USBDis B USBEn USBLowSpd IUSBHiSpd FEthDisl_B FEthEn1 FEthDis2 FEthEn2_B FEthMDSell IFEthEnl B IFEthEn2 amp IAtm16 B USBEn FEthMDSel2 IFEthEn1 IFEthEn2 B Atm16_B USBEn RS232Dis1_B RS232En1 RS232Dis2 B 5232 2 Local Bus Mode PCI Interrupt Register
27. M ask fb then ISlotOlntB Active else 144 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotOlntB Active state Slot0IntB_ Active if HardReset B 0 amp Slot0IntB_ PON DEFAULT SlotOIntB Active HardReset 0 amp INTB B amp SlotOIntBMask fb then SlotOlntB Active else ISlotOlntB Active state diagram SlotOIntC state SlotOlntC Active if HardReset B 0 amp Slot0IntC_PON DEFAULT Slot0IntC_Active HardReset B 0 amp B amp Slot0IntC Mask fb SlotOIntC Mask fb then ISlotOlntC Active else SlotOlntC Active state SlotOlntC Active if HardReset B 2 0 amp Slot0IntC_PON DEFAULT Slot0IntC_Active HardReset B 0 amp B amp Slot0IntC Mask fb then SlotOlntC Active else ISlotOlntC Active RAIA ARAKI ARIA state diagram SlotOIntD state SlotOlntD Active if HardReset B 0 amp Slot lIntD PON DEFAULT 15 Active HardReset B 0 amp INTD B amp SlotOlntDMask fb Slot0IntDMask fb
28. 17 2 43 COPHTAG Connector P15 18 2 4 4 Terminal to PQ2FADS ZU RS 232 Connection 18 2 4 5 10 100 Base T Ethernet Ports Connection 19 MOTOROLA PQ2FADS ZU User Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 2 4 6 Section 3 Memory Installation 0 0 0 cee eee IIIA 19 2 4 6 1 Flash Memory SIMM Installation 19 Operating Instructions 3 1 Introduction 3 dE 21 3 2 Controls and Indicators sh Re NIU IE SM BUY oe ee 21 3 2 1 Power On RESET Switch SW1 21 3 2 2 ABORT Switehi SW gt doe Fee m ce ro pie oe e eO et 21 323 SORT RESET Switch SW3 uvas tate x er RA 2 3 24 HARD RESET Switches SW2 65 3 21 325 SW3 Reset Configuration Switch 22 3 2 6 SW4 Software Options Switch 22 32 7 P24 VDDL Voltage Level Range Selection 22 3 2 8 JP13 IDDL Measurement 22 32 9 JP5 Thermal Sense Connector 22 3 2 10 JP12 IDDH Measurement 23 3 2 11 JP14 VPP So
29. 5232 port 1 enable RS232Disl PIN 56istype RS232 port 1 Disable RS232bEn2 B PIN 3istype RS232 port 2 enable RS232Dis2 B PIN 8istype RS232 port 2 Disable 106 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information PIN 19 Local Bus PCI Select Local Bus B PIN 98istype Local Bus SDRAM Select ModckHO 67 MODCKHO ModckH1PIN 65 1 ModckH2 61 MODCKH2 ModckH3 59 MODCKH3 PCI IRQ B PIN 100istype com buffer PCI Interrupt to PQ2 o d PCI INTA B 97 PCI Interrupt from PCI card PCI INTB B 126 PCI Interrupt from PCI card PCI INTC B 125 PCI Interrupt from PCI card PCI INTD B 120 Interrupt from PCI card Board Status Registers Chip S elects TOKIO ORRICK AKAROA AAA AAA AR AAA AKA AAA AAA AAR Bcsr2Cs 89istype Bcsr4Cs 8listype Ijoleloleleleteretetetetetetetelerererererererererererererererererererelerelerelelerelerelereleretetetetetetetetetetetetetetereterererererererererererererek Flash EEPROM Associated Pins PD1 PIN 57 PD2 PIN 55 45 4
30. HardReset 2 0 51000 PON DEFAULT Slot0IntAMask_Active HardReset B 0 amp Slot0IntAMask_ PON DEFAULT Slot0IntAMask_ Active then Slot0IntAMask_Active else Slot0InthMask_ Active state diagram 5 Mask state 5 Active if VGR_WRITE_IntMaskReg amp Sloto lntBMask DATA Slot0IntBMask_ Active amp HardReset lt lt 0 100 DEFAULT Slot0IntBMask_Active MOTOROLA PQ2FADS ZU User s Manual 151 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HardReset B 0 amp Slot0IntB Mask DEFAULT Slot0IntBMask_Active then Slot0IntB Mask_Active else Slot0IntBMask_Active state Slot0IntBMask_Active if VGR_WRITE_IntMaskReg amp Slot0IntBMask_DATA_BIT pin Slot0IntBMask_ Active amp HardReset B 0 5 0 01 DEFAULT Slot0IntBMask_Active HardReset B 0 amp Slot0IntB Mask DEFAULT Slot0IntBMask_ Active then Slot0IntBMask_Active else Slot0IntBMask_Active TORO KAKA RAIA ARIA RARER AKA state diagram Slot0IntC Mask state Slot0IntCMask_ Active if VGR_WRIT
31. MOTOROLA PQ2FADS ZU User s Manual 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information then Slot0IntD_ Active else SlotOlntD Active state SlotOlntD Active if HardReset B 0 amp 5 0 01 PON DEFAULT Slot0IntD_Active HardReset B 0 amp INTD B amp Slot0IntDMask fb then SlotOlntD Active else Slot0IntD_ Active RAIA RAIA state diagram SlotlIntA state SlotllntA Active if HardReset B 2 0 amp SlotllInt PON DEFAULT 5 Active HardReset B 0 amp PCI INTD B amp SlotlIntAMask fb S ot1IntAM ask fb then ISlotlintA Active else SlotlintA Active state SlotlIntA Active if HardReset B 0 amp SlotlInt PON DEFAULT SlotllntA Active HardReset B 2 0 amp INTD B amp SlotlIntAMask fb then SlotlintA Active else ISlotllntA Active RAIA RAIA KARA state diagram SlotlIntB state SlotllntB Active 146 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information if HardReset B 0 a
32. Table 4 6 100 MHz SDRAM Mode Register Programming SDRAM DRAMM Address 5 ode Value Meaning a Reg Field Line A11 MSB Reserved 0 10 Reserved 0 9 0 1 0 Burst Read amp Burst Write Copy Back data cache 1 Burst Read amp Single Write Write Through Data cache A8 Reserved 0 Reserved 0 A6 4 CAS Latency 011 Data Valid 3 Clocks cycles after CAS Asserted A3 Burst Type 0 Sequential Burst A2 Burst Length 010 4 Operand Burst Length a Actually SDRAMs AO is connected to PQ2s A28 and so on 4 7 2 SDRAM Refresh The SDRAM is refreshed using its auto refresh mode I e using SDRAM machine one s periodic timer an auto refresh command is issued to SDRAM every 8 2 usec so that all 4096 SDRAM rows are refreshed within specified 34 msec while leaving an interval of 30 msec of refresh redundancy within that window as a safety measure to cover for possible delays in bus availability for the refresh controller 4 7 3 L2 Cache Support Influence On SDRAM Design To support an optional L2 Cache on the PQ2FADS ZU the following measures need to be taken 1 Optional Latches Multiplexers are added over selected address lines See Figure 4 6 These Latches Multiplexers are normally by passed by 0 resistors that are not assem 44 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com
33. 3 2 9 JP5 Thermal Sense Connector There are 2 dedicated pins THERM 0 1 which provide a way to take internal temperature measurements of the PQ2 These pins should be connected to GND for normal operation JP5 is factory set with a jumper on its 2 3 positions so that THERMI is connected to GND 22 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions JP2 3 Dx GND 2 1 THERMO Figure 3 2 JP5 Therm Connector 3 2 10 J P12 Measurement JP12 resides in IDDH s main current flow To measure IDDH JP12 should be removed using a solder tool and a current meter should be connected with as wires as short and thick as possible Warning The job of removing JP12 and soldering current meter connections instead is very delicate and should be done by a skilled technician If this process is done by unskilled hand or re peated more than 3 times permanent damage might be inflicted to the PQ2FADS ZU 3 2 11 J P14 VPP Source Selector JP14 selects the source for VPP programming voltage for the Flash SIMM When a jumper is located between pins 2 3 of JP14 the VPP is connected to the VCC plane of the board providing 5V VPP When a jumper is located between positions 1 2 of JP14 VPP is drawn from the 12V plane that provides 12V VPP JP14 options are shown in Figure 3 3 JP14
34. C300 C301 C 302 C306 C 309 C310 C311 C314 C315 C 316 C317 C318 C319 C320 C 321 C322 C323 C324 C325 C 328 C329 C330 C331 C 332 C333 C334 C335 C336 C337 C 338 C339 C340 C341 C342 C 343 C344 C345 C346 C347 C 348 C349 C350 C351 C352 C 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 C369 C370 C371 C372 C373 C374 C375 C376 C379 C 380 C381 C382 C383 C384 C 385 C386 C387 C388 C 389 C 392 C393 C394 C395 C 396 C 397 C398 C399 C400 C401 C 402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 C417 418 419 420 421 422 423 424 443 445 446 19 10 11 26 27 28 29 30 34 51 76 77 100 155 164 170 307 327 C444 C447 10uF TAJ C106K025R AVX 55 C25 C143 C144 C147 C 154 C162 C163 C165 C166 C171 C172 C192 C193 C214 C215 C216 C217 C223 C224 C225 C226 C243 C244 C245 C247 C248 C249 C250 C264 C265 C266 C267 C278 C279 C284 C285 C286 C289 C290 C291 C297 C298 C299 C303 C 304 C305 C308 C312 C313 C 377 C378 C390 C391 C 441 C 442 10nF 06035C103KAT2A AVX C78 100uF TAJ D107K016R AVX C82 68uF 16V TAJ D686M020R AVX C99 luF B45196H5105K 109 SIEMENS 24 C121 C122 C123 C124 C125 C126 C127 C139 C425 C426 C427 C428 C429 C430 C431 C432 C433 C434 C435 C436
35. m LUE THHHH HHH d x m d A HHH HHRHH HHHQ HHHH EE x HHHH dod d yg d y A HRE HEE H HHH D MOTOROLA PQ2FADS ZU User s Manual 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 7 2 2 941 Power switch debounce MODULE Power_Debouncer TITLE MPC8280 Power Debouncer Device declaration EKEK EEKE EKEK EKK K HHE x dE GHHHHE HHH d HHH x f gg 2 K HHH HE HHHH Gg og Gg og Ht x 44 HHHH d x dE Hg g f HH UFGHHHHHHE E HHHH HHHH Ijoleloleleleteleteretetetetetelelerererererererere
36. 0 0 L2lInh B L2Flush B L2Lock B L2Clear B SignaLampO B 1 B ReadBcsr1 bcsrConfE n boot device B AtmEn B 114 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information AtmRst_B fb FEthEn1_B FEthRstl_B fb RS232En1_B RS232En2_B ReadBcsr3 USBEn_B USBHiSpd_B USBVccO FEthEn2_B FEthRst2 B fb Atm16 AtmSinglePHY B PCI Mode DrivenContReg L2Inh_B L2Flush_B L2Lock_B L2Clear B SignaLampO 1 B AtmEn B Atm16 AtmSinglePHY FEthEnl B FEthEn2 B 5232 5232 2 USBEn USBHiSpd B USBVccO MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 115 Freescale Semiconductor Inc Support Information ClockedContReg L2Inh_B L2Flush_B L2Lock_B L2Clear B SignaLampO SignaLampl AtmEn B AtmRst Atm16 AtmSingleP HY FEthEnl FEthEn2 B FEthRstl B FEthRst2 B 5232 RS232En2 USBEn USBHiSpd_B USBVccO IntReg Slot0IntA S lotOIntB S lotOIntC S lotOIntD SlotlIntA SlotlIntB Slotlintc SlotlIntD Slot2IntA 116 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information S lot2IntB S lot2In
37. 14 12V VPP VPP Factory Set Figure 3 3 JP14 VPP Source Selection 3 2 12 GND Bridges There are 7 GND bridges PQ2FADS ZU These bridges are meant to assist general measurements and logic analyzer connection MOTOROLA PQ2FADS ZU User s Manual 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions Warning When connecting to a GND bridge use only IN SULATED GND clips Otherwise un insulated clips may cause short circuits touching HOT points around them Failure in doing so might result in permanent damage to the PQ2FADS ZU 3 2 13 Power O K Indicator LD1 The green Power O K LED indicator lights if the ATXpower supply is generating all the voltages 3 2 14 12V Indicator LD2 The green 12V led LD2 indicates the presence of the 12V supply on the board 3 2 15 UTOPIA 16 Bit Indicator LD3 The green UTOPIA16 led LD3 indicates that the UTOPIA is in 16 bit mode When off the UTOPIA is in 8 bit mode 3 2 16 UTOPIA Multi PHY Indicator LD4 The green Multi PHY led LD4 indicates that the UTOPIA is in Multi PHY mode When off the UTOPIA is in single PHY mode 3 2 17 5V Indicator LD5 The green 5 led LDS indicates the presence of the 5V supply the board 3 2 18 3 3V Indicator LD6 The green 3 3V led LD6 indicates the presence of the 3 3V supply on the board 3 2 19 USB Power Indicator
38. ATM port is disabled these lines may be used for any B10 ATMTXD3 PA22 available respective function Bll ATMTXD4 PA21 B12 5 20 B13 ATMTXD6 PA19 14 ATMTXD7 18 15 ATMRXD7 PA17 T S Receive Data 720 When the ATM port is enabled this bus carries the cell octets read from the PM5350 receive FIFO This lines B16 ATMRXD6 PA16 are updated on the rising edge of ATMRFCLR B17 ATMRXDS 15 When the ATM port is disabled these lines are tristated and may be used for any available respective function B18 ATMRXD4 PA14 B19 ATMRXD3 PA13 B20 2 PA12 B21 ATMRXDI PA11 B22 PA10 MOTOROLA PQ2FADS ZU User s Manual 89 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description B23 9 T S PQ2 s Port A 9 0 Parallel I O or dedicated CPM lines May be used for any of their available functions B24 PA8 B25 PA7 B26 PA6 B27 PAS B28 PA4 B29 PA3 B30 PA2 B31 B32 PAO FETHTXER PB31 T S Fast Ethernet Transmit Error H When the Ethernet port is enabled this signal will be asserted High by the PQ2 when an error is discovered in the transmit data stream When the port is operation at 100 Mbps th
39. O D PQ2 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the PQ2 During that sequence asserted by the 2 for 512 system clocks Pulled Up on the ADS using a 1KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the PQ2 and or to ADS logic 14 N C Not Connected 15 XBR3 CKSTOP_OUT I O Normally configured as XBR3 which has no function with this connector May be configured as CKSTP_OUT Check Stop Out L When asserted Low indicates that the PQ2 core has entered a Check Stop state 16 GND Digital GND GND plane 7 1 4 P7 CPM Expansion Connector P7 is a 128 pin 90 DIN 41612 connector which allows for convenient expansion of the PQ2 s serial ports This connector contains all CPM pins plus power supply pins to provide for easy tool connection as described in Table 7 4 86 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description Al RS RXDI PD31 T S When RS232 port 1 is enabled this signal is the receive data line for that port When this port is disabl
40. OF Hh HH HHH HHH d SHHHHHE 4 HHH d THEO HHHH d ii HHHH HHHH x 170 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HH 4 Ik HHH d T dH dg HF T dod FHF dod Ht dod Ijolelolelelelereteretetetetetelererererererererererererererererereterelerelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek H L X Z 1 0 X Z CD U C D U SIMULATION 1 k Signal groups counter counter7 counter6 counter5 counter4 counter3 counter2 counterl counter0 countera countera7 countera6 countera5 countera4 countera3 countera2 counteral countera0 counterb counterb7 counterb6 counterb5 counterb4 counterb3 counterb2 counterb1 counterb0
41. C437 C438 C439 C440 1nF AVX12065C102KA AVX 10 141 448 100nF 500V 501S43W104MV4E JOHANSON 11 C293 1500pF 12065 152 00 204 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 12 3 D1 D2 D3 LL4004 LL4004G TSC 13 1 Fl SMD150 33 2 SMD150 33 2 RAYCHEM 14 5 P1 P6 8 P12 P13 GND_Bridge254 PD 999 11 11010 PRECIDIP 15 9 P2JP3JP4JP5JP7JP9 UMPER1x3 87156 0303 MOLEX 10 P 11 P 14 16 7 1 2 3 4 5 6 7 GND_Bridge PD 999 11 11210 PRECIDIP 17 18 LD1 LD2 LD3 LD4 LD5 LD6 LED_GREEN KPT 3216SGD KING BRIGHT LD7 LD8 LD9 LD16 LD17 LD21 LD22 LD23 LD25 LD26 LD27 LD28 18 7 LD10 LD11 LD12 LD13 LD15 LED_YELLOW KPT 3216YD KINGBRIGHT LD19 LD24 19 2 LD14 LD20 LED_RED 321610 KINGBRIGHT 20 1 LD18 LED_RED KPT 3216YD KINGBRIGHT 21 2 241 BEAD_FERRITE 2743021447 FAIR RITE 22 4 L3 L4 L21 L22 NFM60R30T222T1 NFM60R30T222T1 MURATA 23 17 L5 L6 L7 L8 L9 L 10 L 11 BLM18AG121SN1 BLM18AG121SN1 MURATA L12 L13 L14 L15 L16 L17 L18 L19 L20 L23 24 1 1 RS232 PORT2 8LE009009D306H EDA 25 1 P2 787616 1 787616 1 AMP 26 2 P4 P 3 RJ 45 43202 8110 MOLEX 27 2 P5 P 6 QSE 020 01 L D A QSE
42. Functional Description register selection BCSRO BCSR7 are duplicated inside that region The following functions are controlled monitored by the BCSR PBI 2 L2 Cache Inhibit 3 L2 Cache Flush 4 L2 Cache Lock 5 L2 Cache tag Clear 6 ATM Port Control which includes Transceiver Enable Disable Transceiver Reset UTOPIA 8 16 bit UTOPIA single multi PHY 7 Fast Ethernet Ports Control which includes Transceiver Initial Enable Transceiver Reset 8 RS232 port 1 Enable Disable 9 RS232 port 2 Enable Disable 10 USB Port Control which includes Transceiver Initial Enable USB Speed USB Power 11 Flash Size Delay Identification 12 CSO assignment after hard Reset to FLASH SIMM E PROM 13 External off board tools Support which include Tool Identification Tool Revision Tool Status Information 14 S W Option Identification 15 Board revision code 16 Power on Reset via JTAG optional 17 PCI cards Present Detect and card type 18 Local Bus Mode Since part of the PO2FADS ZUs modules are controlled by BCSR and since they may be disabled in favor of external hardware the enable signals for these modules are presented at the CPM expansion connectors so that off board hardware may be mutually exclusive enabled with on board modules 4 14 1 BCSRO Board Control Status Register O The BCSRO is a control register on the PQ2FADS ZU It is accessed at offset 0 from BCSR base 58 PQ2FAD
43. LD7 The green USB Power led LD7 indicates the presence of 5V in the USB cable 3 2 20 12V Indicator LD8 The green 12V led LD8 indicates the presence of 12V supply on the board 3 2 21 RUN Indicator 109 When the green RUN led LD9 is lit it indicates that the PQ2 is performing cycles on the PPC Bus When dark the PQ2 is either running internally or stuck 3 2 22 ATM ON LD10 When the yellow ATM ON led is lit it indicates that the ATM UNI transceiver the PM5384 is enabled for communication When it is dark the ATM UNI transceiver is disconnected from the 2 enabling the use of its associated pins off board via the expansion connectors ATM ON led is controlled by BCSRI 24 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions 3 2 23 Fast Ethernet Port 2 Enabled LD11 When the yellow ETH2 ON led is lit it indicates that the fast ethernet port 2 transceiver the DM9161 is connected to FCC3 When it is dark it indicates that the DM9161 is in power down mode and disconnected from FCC3 enabling the use of its associated FCC3 pins off board via the expansion connectors The state of LD11 is controlled by BCSRI 3 2 24 Fast Ethernet Port 1 Enabled 1012 When the yellow ON led is lit it indicates that the fast ethernet port 1 transceiver the DM9161 is connected to FCC2 When it i
44. The internal registers of the PQ2 must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in Hexadecimal base For more information on the following initializations see the PQ2 User s Manual 5 2 1 System Initializations The Power On Reset Configuration word is set in the BCSR or FLASH or in the E PROM There are two configuration words one for the BCSR and FLASH when it is assigned to CSO and the other to the E7PROM when it is assigned to CS0 The two configurations are detailed in Table 5 3 and Table 5 4 respectively Table 5 3 BCSR FLASH Power On Reset Configuration Flash Init Address Value hex Description hex 0 0C 1 Internal arbitration Internal memory controller Core enabled Single PQ2 60X Bus mode 32 Bit boot port size Exceptions vectored to OxFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configured as BADDRx lines DP 1 7 configured as L2 cache and IRQ 6 7 Initial internal space OxOF000000 10 32 369 Boot memory space OxFE000000 OxFFFFFFFF ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as Local bus in BCSR or PCI in FLASH PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 45 CS10 configured as BCTL1 a Programmed into the Flash E7PROM memory in
45. e usasqa uqaqa aa dy 4 1 2 3 Internal Sources Hard Reset 4 1 24 Hard Reset Configuration AAS eee A Re D D pa ne 4 1 3 1 COP JTAG Port Soft Reset 41 32 Manual Sotte Reset A Aro Ua ed 4 1 3 3 Internal Sources Soft Reset AVA ReSeb bee en ted rat Local Interrupt r 4 245222 ok iiA 421 ABORT Interrupt ea Gees tee ce Eus IOS 42 2 AONE UNI Interrupt y y I Re a 4 2 3 Fast Ethernet PHY Interrupt 24 POCLIEIEDE ie us Clock Generator 22 eens eee POZ Clock z S eer 4 5 2 a BON ud Bus mirese ise eed ead heb ee eee Simsle PO2 Mode stes ad a a BS SEV ERE 442 600XBusMode RR een erate RE IER EX EMI Chip Select Generator E AA E EAE Synchronous Dram
46. 130 3 U56 U60 U64 CY 2309ZC 1H CY 2309ZC 1H Cypress 131 1 U58 PI3B33X257B P13B33X257B Pericom 132 3 U72 U73 U74 MT48LC4M32B2TG 6 MICRON 210 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 133 2 U76 U75 74ALVT16245 74ALVT16245DL PHILIPS 134 2 U79 U80 74ALVT16373 74ALVT16373DL PHILIPS 135 1 X1 M216TCN50 00 M216TCN50 00 M TRON 136 1 X2 M218TCN 19 44MHz M218TCN 19 44MHz M TRON 137 1 X3 M216TCN 48 00MHz M216TCN 48 00MHz M TRON 138 1 X4 66MHz 3V3 M3H16FCD 3V3 M TRON 66MHz 139 1 X5 40MHz 3V3 M3H16FCD 3V3 M TRON 40MHz 140 1 X6 1 10933E 12 1 10933E 12 PRECIDIP MOTOROLA PQ2FADS ZU User s Manual 211 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 212 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com
47. 2 of P24 a level range of 2 3V to 2 7V on VDDL is selected This level matches the specification for the MPC8260 Hip3 2 When jumper is placed between positions 3 4 of P24 a level range of 1 7V to 1 9V on VDDL is selected This level matches the specification for the PQ2 Hip4 3 When a jumper is placed between positions 5 6 of P24 a level range 1 3V to 1 7V is selected for VDDL This level matches the specification for MPC8280 Hip7 4 When a jumper is misplaced for P24 a level range of 1 8V to 2 0V is selected for VDDL This level matches the specification for the faster 83MHz bus speed PQ2 Hip4 P24 24 5 I o T 3 gt 3 403 x 4 04 09 1 3V 1 7V 1 7V 197 2 3V 2 7V 1 8V 2 0V Figure 2 2 VDDL Range Selection P24 WARNING P24 is Factory Set according to the revision of PQ2 with which it is assembled Prior to chang ing a PQ2 device Extra Care should be taken with P24 setup If a selected Voltage Range is above the specification for the newly inserted PQ2 PERMANENT DAMAGE might be inflicted to the device P24 selects only a range of Voltage levels on VDDL The actual level is selected by RP2 See next paragraph 2 3 2 Setting VDDL Supply Voltage Level After VDDL s Voltage Level Range is selected via P24 the actual level of VDDL is tuned via RP2 VDDL may be measured upon JP13 using a DVM or any other high input impedance vo
48. 43 50 54 chip select input MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 54 94 eeprom flash chip select input EEpromCs B 137istype com EEPROM chip select FlashCs1 PIN 144istype Flash bank1 chip select FlashCs2 138istype Flash bank2 chip select FlashCs3 143istype Flash bank3 chip select FlashCs4 B 140istype Flash bank4 chip select 5384 ATM UNI Associated Pins AtmUniCsIn B PIN 119 AtmUniCsOut B PIN 62istype com remove if short of pins Reset amp Interrupt Logic Pins PORIn_B PIN 41 RstConf B PIN istype Hard Reset master select RstO PIN 33 connected to N C of Reset P B Rstl PIN 31 connected to of Reset HardReset B PIN 18istype com Actual hard reset output
49. ATM Transmit Enabled L When this signal is asserted Low while the ATM port is enabled and is rising an octet of data ATMTXD 7 0 is written into the transmit FIFO of the PM5350 When the ATM port is disabled this line may be used for any available function of PA31 B2 ATMTCA PA30 T S ATM Transmit Cell Available H When this signal is asserted High while the ATM port is enabled it indicates that the transmit FIFO of the 5350 is empty and ready to except a new cell When negated it may show either that the transmit FIFO is Full or close to Full depending on 5350 internal programming When the ATM port is disabled this line may be used for any available function of PA30 B3 ATMTSOC PA29 T S ATM Transmit Start Of Cell H When this signal is asserted High by the PQ2 while the ATM port is enabled it indicates to the PM5350 the start of anew cell over ATMTXD 7 0 i e the 1 st octet is present there When the ATM port is disabled this line may be used for any available function of PA29 88 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description B4 ATMRXEN PA28 T S ATM Receive Enable L When this
50. EE Eos al um pn nd gem Freescale Semiconductor Inc MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product o to www freescale com 199 Support Information Freescale Semiconductor Inc 200 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 4 ml 5 l 4 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com w w de w w OR t R OO CoA Bi EE 201 Freescale Semiconductor Inc Support Information 202 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 7 3 2 Bill of Materials The following is the Bill Of Materials for the PQ2FADS ZU including L2Cache option Support Information Figure 7 1 PQ2FADS ZU Bill of Materials Item Quan tity Reference Value Part Number Manufacturer C1 C2 C3 C6 0 01UF 2KV 2025 49W 103KV4E J OHANSON DIELECTRIC 19 4 5 9 18 23 35 39 41 42 53 84 97 98 106 138 140 282 287 326 47uF D476K016 AVX 321 C7 C8 C
51. FETH1 RESET PON DEFAULT FETH1 RESET ACTIVE RS232 1 ENABLE PON DEFAULT RS232 1 ENABLE RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE EKE EKK Data Bits Assignments rrr TORII RAIA ARIA CONF WORD DATA BOOT DEVICE DATA BIT D1 ENABLE DATA BIT D2 RESET DATA BIT D3 FETH1 ENABLE DATA BIT D4 FETH1 RESET DATA D5 5232 1 ENABLE DATA 06 5232 2 ENABLE DATA D7 CCCI RRR RK x BCSR definitions MOTOROLA PQ2FADS ZU User s Manual 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information EKEK EEK USB ENABLED 20 USB SPEED HIGH 0 USB VCCO ON 1 FETH2 ENABLED 0 FETH2 RESET ACTIVE 0 ATM16 ENABLED 20 SINGLE PHY ENABLED 0
52. IntContCs B amp R BW end of PCI Interrupt Controller read cycle 128 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information END READ DVal_B amp AtmUniCsIn B amp R B end of atm uni m p i f read cycle END OF OTHER CYCLE DVal_B amp 50 B amp Cs4 B amp AtmUniCsIn B IntContCs B B amp AtmUniCsIn B amp R B W IDVal B amp 51 B IDVal amp 52 B amp R B W B amp ICs0 B 54 IDVal B amp IntContCs B amp R another access or atm uni write or tool 1 write or tool 2 write or flash eeprom write P CI int cont write k Hard Reset Configuration Logic RA AKA KAKA II AKA AIR HRESET CFG IN BCSR bcsrConfEn 1 HRESET Conf Word in BCSR HRESET BOOT IN FLASH bcsrConfEn 0 amp boot device B 0 HRESET Conf Word and Boot Code in FLASH BOOT IN FLASH bcsrConfEn 1 amp boot device B 0 HRESET Conf Word in BCSR and Boot Code in FLASH HRESET BOOT IN EEPROM bcsrConfEn 0 amp boot device 1 HRESET Conf Word
53. It is assumed that the stabilization time for both linear regulators see also Section 6 1 Power Supply are about the same Power On Reset may be generated manually as well by an on board dedicated push button SW1 Power On Reset can also be generated by the JTAG logic which is integrated with BCSR 4 1 1 1 Power On Reset Configuration At the end of Power On reset sequence MODCK 1 3 are sampled by the PQ2 to configure the various clock modes of the PQ2 core cpm bus PCI Selection between the MODCK 1 3 combination options is done by means of dip switches Section 2 3 3 on the mother board while PCI MODCKH 0 3 are obtained from the relevant dedicated pins by means of dip switches Section 2 3 6 when the PQ2 is in active PCI mode determined by the state of PCI MODE pin If the PCI is set to be inactive the MODCKH 0 3 bits are obtained from the Hard Reset Configuration Word in the Flash or in the E PROM depends on who is the boot device or from PCI MODCKH 0 3 dip switches if the Hard Reset Config Word is sourced from the BCSR The configuration master is determined upon the rising edge of PORST according to the state of RSTCONF Section 2 3 5 signal driven low on this board to set the PQ2 as a configuration master After power on reset negates the hard reset sequence starts during which many other different options are configured see Section 4 1 2 4 Hard Reset Configuration on page 29 among MOTOROLA PQ2F
54. W controlled UPM waits D10 EXPGL3 D11 EXPGL4 D12 EXPGLS D13 GND Digital Ground Connected to main GND plane of the ADS D14 EXPALE Expansion Address Latch Enable This is the buffered PQ2 s ALE provided for expansion board s use 015 EXPCTLO Expansion Control Line 0 This line is a buffered version of PQ2 s BCTLO Bus Control Line 0 which serves as W R provided for expansion board s use D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 GND Digital Ground Connected to main GND plane the ADS a MS Bit 102 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 7 1 10 P2 USB Connector This is a four pin standard USB connector type A The pinout is shown in Table 7 9 P2 USB Connector Pin No Signal Name Description 1 5V Power Power line of the USB cable 2 D Twisted Pair Transmit Data negative 3 D Twisted Pair Receive Data positive 4 GND Ground connection 7 2 Programmable Logic Equations There are 4 programmable logic devices on board 1 035 BCSR and PCI Interrupt Controller 2 041 Power switch debounce 7 2 1 135 BCSR Code MODULE PQ2HipXBCSR TITLE MPC82xx ads
55. the Hard Reset Configuration source is the BCSR See Figure 2 5 FLASH EEPROM is Hard Reset BCSR is Hard Reset Configuration Source Configuration Source Factory Setup Figure 2 5 Hard Reset Configuration Source Selection JP7 2 3 5 Setting Boot Source The Hard Reset configuration word read by the PQ2 while HRESET is asserted may be taken from three sources 1 Flash Memory SIMM 2 EEPROM 3 BCSR For additional information as for the contents of the Hard Reset configuration word see 4 1 2 4 Hard Reset Configuration on page 29 SW5 1 actually assigns CSO to the FLASH default when booting from the BCSR or to the EEPROM When SWS 1 is OFF the Hard Reset configuration word is taken from EEPROM when it is ON the Hard Reset configuration word is taken from the Flash SIMM See Figure 2 6 1 0 EEPROM BOOT FLASH BOOT PCI_ARBITER OFF PCI_ARBITER ON PCI_DLL ON PCI_DLL OFF PCI CONFIG 3 PCI CONFIG 3 SW5 Factory Set Figure 2 6 SW5 Description 1 In fact 8 Hard Reset configuration words are read by a configuration master however only the first is rel evant for a single PQ2 12 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 2 3 6 Setting MODCKH 0 3 for PLLs Multiplication Factors When the Hard Reset configuration word i
56. 0 SyncHardReset_B ap 0 162 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information DSyncHardReset_B clk SYSCLK DSyncHardReset_B ar 0 DSyncHardReset_B ap 0 S yncHardReset B HardReset DS yncHardReset B SyncHardReset B fb DataBufEn B oe H IDataBufEn B 50 B covers also hard reset config ICs4 B IBrdContRegCs B IIntContCs B IAtmUniCsOut provides data hold for write IToolCs1 IToolCs2 B amp HOLD OFF ToolDataBufEn B oe H IToolDataBufEn 51 B IToolCs2 B amp BUFFER HOLD OFF local data buffers disable data contention protection Since with Voyager hard reset conf is read from flash eeprom during HRESET asserted and since these are all consequitive read cycles and since the cycles following hard reset are also reads boot the hold off state machine may leftin NO HOLD OFF for HRESET asserted duration MOTOROLA PQ2FADS ZU User s Manual 163 For More Information On This Produc
57. 0 Present 0 1 This field holds code that tells whether a PCI 11 expansion board is pluged PCI slot 0 the total power requirements the board according to the PCI spec The different expansion board types are listed in Table 4 21 2 3 PCI1 PRSNT 0 1 PCI Slot 1 Present 0 1 This field holds a code that tells whether a PCI 11 R expansion board is pluged in PCI slot 1 and the total power requirements of the board according to the PCI spec The different expansion board types are listed in Table 4 21 4 5 PCI2 PRSNT 0 1 PCI Slot 2 Present 0 1 This field holds a code that tells whether a PCI 11 R expansion board is pluged in PCI slot 2 and the total power requirements of the board according to the PCI spec The different expansion board types are listed in Table 4 21 6 M66EN 66MHz Enable This field shows if one of the expansion boards used is not 1 R capable of operating in 66MHz mode 1 All expansion boards are 66MHz capable 0 One of the expansion boards is not 66MHz capable 7 PCI MODCK PCI MODCK This field shows the PCI bus clock settings R 8 31 Reserved un implemented Table 4 21 PCI Board Present Signal Definitions PCIx_PRSNT 0 1 Hex Expansion Configuration 0 Expansion board present 7 5W maximum 1 Expansion board present 25 maximum 2 Expansion board present 15W maximum 3 No expansion board present 4 14 6 BCSR
58. 60X LII SDRAM Prosr imminsg u ct ES 4312 SDRAM Refresh ERE guy ee ei 4 7 3 L2 Cache Support Influence SDRAM Design 4 7 4 SDRAM Error Correction Support Synchronous Dram Local Bus 4 8 1 Local Bus SDRAM Programming 462 SDRAM Refresh 2245 Anaad ea Reet E ERES aed eae 4 8 3 Local Bus SDRAM Functionality 4 8 4 Local SDRAM Error Correction Support Flash Memory SIMM tase ora ne yas need eee eras her vs 491 Flash Programming Voltage MOTOROLA PQ2FADS ZU User Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 49 2 Flash and L2Cach he braces 50284 RR BEER 4 10 E2PROM Memory 225 aeons us 4 1 esa ee 4 12 1 2 Support 221 ob a E 4 12 1 L2 Cache Configuration amp Control 4 13 Communication Ports e
59. 7 42953 po 0 63 L SYSCLK gt CLK MT48LC4M32B2 6 Figure 4 5 60x SDRAM Connection Scheme L2 Cache The SDRAM connection scheme when L2 cache is installed is shown in Figure 4 6 MT48LC4M32B2 6 52 cso SDRAS SDCAS CAS SDWE WE LATCH BANKSEL 1 2 1 0 A 28 21 SDRMAII All PSDA10 A 6 28 SDRMA9 gt A9 ALE LE SDRMA 8 0 A 18 6 gt A 8 0 5 0 07 pemB 7 0 63 DQ 0 63 PSDAMUX CKE CLK Figure 4 6 SDRAM 60x Bus Connection Scheme with 12 Cache MOTOROLA PQ2FADS ZU User s Manual 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 7 1 SDRAM Programming After power up the SDRAM needs to be initialized by means of programming to establish its mode of operation The SDRAM is programmed according to the following procedure 1 Issue Precharge All command 2 Issue 8 CBR refresh commands 3 Issue MODE SET command An SDRAM is programmed by issuing a Mode Register Set command During that command data is passed to the Mode Register through the SDRAMs address lines This command is fully supported by the SDARM machine of the PQ2 Before that can take place the SDRAM machine of the PQ2 has to be initialized Mode Register programming values are shown in Table 4 6
60. CFFFFFFF MByte 0000000 Local Bus 8MByte 32 8 MByte DO7FFFFF SDRAM D0800000 Empty Space 1 GByte FFFFDFFF FFF00000 2 28 64 8 32 KByte FFFFFFFF MOTOROLA a The device appears repeatedly in multiples of its port size in bytes X depth E g BCSRO appears at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size that may be controlled by the GPCM is 32 KBytes Initially at hOF000000 hOFOOFFFF set by hard reset configuration Refer to the PQ2 User s Manual for complete description of the PQ2 s internal memory map e An 8 Kbyte device is used 16 Kbyte and 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from FFF00000 5 2 PQ2 Register Programming The 2 provides the following functions PQ2FADS ZU 1 System functions which include PPC Bus SDRAM Controller Local Bus Host to PCI Bridge or SDRAM Controller e Chip Select generator 2 Communication functions which include _ SAR Dual Fast Ethernet controller UART for terminal or host computer connection USB Controller PQ2FADS ZU User s Manual 73 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization
61. DLL That clock output is feeding an on board low skew and fast low propagation delay PLL clock distributor which distributes the PCI clock to all on board PCI devices One of the outputs is fed back to the PCI clock to the PQ2 through CLKIN2 input This clock input is driven to the DLL which synchronizes the DLL output clock to CLKIN2 input clock and thus maintains low skew between the DLL output and CLKIN2 input All PCI bus timings are referenced to the CLKIN2 input clock Special care was taken when the board layout was done to keep all copper traces away from the Clock Distributor outputs at the same lengths including the output that is fed back to CLKIN2 This is in compliance with the PCI standard to achieve bus synchronization and low skew The PCI clock scheme is shown in MOTOROLA PQ2FADS ZU User s Manual 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Figure 4 4 Low Skew PLL PQ2 PCI Device CLOCK GEN DLLOUT gt IN 66 MHZ l CLKINI OUT2 PCI CLKIN2 4 OUT4 OUT3 J evice 3 Figure 4 4 Clock Generator Scheme 44 Bus Configuration The PQ2 may be configured in 2 possible bus modes depending on the presence of L2 cache on board 1 Single PQ2 Mode 2 60X Bus Mode 4 4 1 Single PQ2 Mode When a L
62. Drain gate Failure to do so might result in permanent damage to the PQ2 and to ADS logic IRQ6 I Interrupt Request 6 L Connected to PQ2 s DP6 CSEO IRQ6 signal Pulled up on the ADS with a 10 KQ resistor This line is shared with the ATM UNI s interrupt line and therefore when driven by an external tool MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to the PQ2 or to ADS logic 100 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description C12 IRQ7 I Interrupt Request 7 L Connected to PQ2 s DP7 CSE1 IRQ7 signal Pulled up on the ADS with a 10 resistor This line is shared with the Fast Ethernet transceiver s interrupt line and therefore when driven by an external tool MUST be driven with an Open Drain gate Failure to do so might result in permanent damage to the PQ2 and or to ADS logic C13 GND Digital Ground Connected to main GND plane of the ADS 14 T S Expansion Data 04 15 This is a double buffered version of the PPC bus D 0 15 lines controlled by on board logic These lines will be 5 EXPDI driven only if BTOOLCS1 or BTOOLCS2 are asserted O
63. EN ER T UA 11 Hard Reset Configuration Source Selection 1 7 12 aW DOSCHLIODR eei ax SCR RO OUR IG RERUM Ple NOR RD And ees 12 Local Bus Mode did Hears 14 10 60x Parity Support Selection 14 Clock SOUTCE Selection 2 LA coda A een 13 FCC2 Ethernet Mode Selection 15 FCC3 Ethernet Mode Selection 16 Host Controlled Operation Scheme Command Converter 17 Host Controlled Operation Scheme Parallel Port 17 Stand Alone Configuration 18 P15 COP ITAG Port Connector 18 1 RS232 Serial Port Connector 19 Flash Memory SIMM Insertion 20 WY opes ber e a _ 22 JES Therm C ODE PUT Msc MA 23 VPP Source Selection e pce xam tue ewe VOR eee 23 PCI Host Configuration Registers 34 PCI Interrupt Routing Scheme 36 Main Clock Generator Scheme 39 PCI Clock Generator Scheme
64. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc To save on board s real estate this button is not a dedicated one but is shared with the Soft Reset button and the ABORT button when both are depressed Hard Reset is generated 4 1 2 3 Internal Sources Hard Reset The 2 has internal sources which generate Hard Reset Among these sources are 1 Loss of Lock Reset When one of the PLLs Core CPM is out of lock hard reset is gen erated 2 Check Stop Reset When the core enters a Check Stop state from some reason hard reset may be generated depended on CSRE bit in the RMR 3 Bus Monitor Reset When the bus monitor is enabled and a bus cycle is not terminated hard reset is generated 4 S W Watch Dog Reset When the S W watch dog is enabled and application s w fails to perform its reset routine it will generate hard reset 5 COP JTAG Reset Internal Hard reset may be forced by driving the HRESET line via the external pin s scan chain Not useful for run time In general the PQ2 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset source has been identified A hard reset sequence is followed by a soft reset sequence 4 1 2 4 Hard Reset Configuration When Hard Reset is applied to the PQ2 externally as well as internally it samples the Hard Reset configuration word This configuration may be taken from an internal default in case RSTCON
65. Freescale Semiconductor Inc Functional Description bled in L2cache boards 2 The PQ2 supports additional wait state on SDMUX line so that row address may be allowed to propagate via the Latch Multiplexers in time for the Activate command 3 To support SDRAM PBI Page Based Interleaving the relative location of the Row Address field is shifted up the address lines depended on the number of internal banks within an SDRAM This since the Bank Select line s are inserted between the Column LSB and Row MSB address lines 4 The L2 Cache used is the MPC2605 This device can operate at maximum speed of 66MHz Therefore the USE OF L2 CACHE WILL LIMIT THE 60X BUS FREQUENCY TO 66MHZ ONLY compared to 100MHz without L2 Cache for the MPC8280 The performance of the SDRAM 15 decreased by the addition of the external multiplexers of the SDRAMs address lines 4 7 4 SDRAM Error Correction Support The PQ2FADS ZU has an optional support for Parity Error Correction for SDRAM accesses To support that option the DP 0 7 lines are connected to the SDRAM DP 0 7 lines Since the PQ2 muxes DP 0 7 signals with other signals bus switch is used to select between DP 0 7 signals and other functions PQ2 60x SDRAM DPO EXT_BR2 DP 0 7 22 DP 0 7 DP1 EXT_BG2 DP2 EXT_DBG2 DP3 EXT_BR3 ED DP4 EXT EX EOS DP6 IRQ6 EXT RQ EXT BR3 EXT DBG3 IRQ6 IRQ7 Figure 4 7
66. HardReset B 2 0 amp Slot2IntB PON DEFAULT Slot2IntB Active HardReset B 0 amp INTD amp Slot2IntBMask fb then Slot2IntB Active else 15 Active Ibeelllreeettlttttetttetteetteltereretteletrreteterettteerreteteterererereteteterererereretetetetejelek state diagram Slot2IntC state Slot2IntC Active if HardReset B 2 0 amp Slot2IntC PON DEFAULT Slot2IntC_Active HardReset B 0 amp PCI INTA B amp Slot2IntCMask fb Slot2IntC Mask fb then ISlot2IntC Active else Slot2IntC Active state Slot2IntC Active MOTOROLA PQ2FADS ZU User s Manual 149 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information if HardReset B 0 amp Slot2IntC_PON DEFAULT Slot2IntC_Active HardReset B 0 amp INTA amp Slot2IntC Mask fb then Slot2IntC Active else ISlot2IntC Active state diagram Slot2IntD state Slot2IntD Active if HardReset B 0 amp Slot21ntD PON DEFAULT Slot2IntD Active HardReset B 0 amp PCI INTB B amp Slot2IntDMask fb Slot2IntDMask fb then ISlot2IntD Active else Slot2IntD Active state Slot2IntD Active if HardReset 0 amp Slot2IntD PON DEFAULT Slot2IntD_Active HardReset B 0 amp INTB B amp Slot2IntDMask fb then Slot2IntD Active else ISlot2
67. MOTOROLA PQ2FADS ZU User s Manual 127 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information x UNI Declarations Ijoleloleleleteleteretetetetetelerererererererererererererererererereteletelerelelerelerelereleretetetetetetetetetetetetetetereteteretererererererererererek Reset Declarations HARD RESET ACTIVE 0 SOFT RESET ACTIVE 20 HARD RESET ASSERTED SyncHardReset_B fo HARD RESET ACTIVE data buffers enable BUFFER_DISABLED 1 BUFFER_ENABLED BUFFER_DISABLED BUFFER HOLD OFF HoldOffCnt fb 0 the delay is required for read as well since a fast device eg bcsr may content with the flash eeprom END OF FLASH EEPROM READ DVal_B amp ICs0 B Cs4 6 1 DS yncHardReset end of flash eeprom read cycle not during hard reset config END OF PCI INT CONT READ B amp
68. Memory Controller Initializations For 100Mhz FLASH as Boot Device Init Value Reg Device Type Bus hex Description BRO SM73228XG1JHBGO by PPC FF801801 Base at FF800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBGO by 001801 Base at FF000000 32 bit port size no parity Smart Modular Tech GPCM SM73288XG4JHBGO by FE001801 Base at FE000000 32 bit port size no parity Smart Modular Tech GPCM ORO SM73228XG1JHBGO by FF800876 8MByte block size CS early negate 11 w s Smart Modular Tech Timing relax SM73248XG2JHBGO by FF000876 16MByte block size CS early negate 11 w s Smart Modular Tech Timing relax SM73288XG4JHBGO by FE000876 32MByte block size CS early negate 11 w s Smart Modular Tech Timing relax BR1 BCSR PPC 04501801 Base at 04500000 32 bit port size no parity GPCM FFFF8010 32 KByte block size all types access 1 w s BR2 SDRAM PPC 00000041 Base at 0 64 bit port size no parity Sdram MT48LC4M32B2 by machine 1 MICRON OR2 002 0 32MByte block size 4 banks per device row starts at A7 12 row lines internal bank interleaving allowed normal AACK operation BR3 SDRAM Local D0001861 Base at D0000000 32 bit port size no parity MT48LC2M32B2 by Bus Sdram machine 2 MICRON OR3 FF803280 8MByte block size 4 banks per device row starts at A9 11 row lines internal bank in
69. POWER QUICC II family of processors Using its on board resources and a debugger a developer is able to download code run it set breakpoints display memory and registers and connect proprietary h w via the expansion connectors to be incorporated into a desired system with the POWER QUICC II processors This board could also be used as a demonstration tool 1 application s w may be programmed into its Flash memory and ran in exhibitions etc 1 Either on or off board MOTOROLA PQ2FADS ZU User s Manual 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information 1 2 Definitions Acronyms and Abbreviations PQ2FADS ZU PowerQUICC II Family ADS Board MPC8260 PowerQuicc 2 Hip3 PQ2 PowerQuicc 2 Hip4 MPC8280 PowerQuicc 2 Hip7 PQ2 PowerQUICC 2 Processors family VOYAGER MPC8260 PowerQUICC 2 PPC PowerPC Peripheral Components Interconnect USB Universal Serial Bus CPM Communication Processor Module SDRAM Synchronous Dynamic Random Access Memory VADS Voyager Application Development System Kbyte 1024 bytes LSB Least Significant Byte Isb least significant bit Mbyte 1048576 bytes DIMM Dual In line Memory Module SIMM Single In line Memory Module TBD To Be Defined UPM User Programmable Machine EVB Evaluation Board GPCM General Purpose Chip select Machine GPL General Purpose Line BCSR Board Control and Status Register FLASH Non volatile reprogrammab
70. PQ2 SDRAM PCI Add In cards address and data buffers are powered by the 3 3 bus which is produced from the ATX power supply 6 1 3 5V Stand By Rail The 5V stand by power rail comes from the ATX Power Supply Its only use is to power the logic required to support the power button in the front panel on the ATX chasis 6 1 4 VDDH Rail The PQ2 s VDDH power bus 3 3V is produced from the 5V bus using a low voltage drop linear voltage regulator made by Micrel the MIC29501 3 3BU A production option is made so that the level on this bus may be varied by means of trimming potentiometer TR2 However this will requires replacing some components This option allows the VDDH to be in the range of 3 0V 3 6V 6 1 5 VDDL Bus The PQ2 s internal logic and the PLL are powered with a lower voltage power source voltage of which may be in 3 ranges of levels 2 3V 2 7 1 7V 1 9V 1 8V 2 0V Selection between the above range levels is done via a jumper which selects between different resistor values within the VDDL s variable regulator feedback network while the fine tuning within a range is done by means of a trimming potentiometer Changing the voltage to the Core logic of the PQ2 obviously has an influence over the maximal speed of the core There is the power speed trade off i e lower operation speeds may be obtained with lower voltage supply 6 1 6 12V Rail The 12V bus from the ATX Power Supply supports the PCI slots
71. PQ2FADS ZU has the following switches and indicators 3 2 1 Power On RESET Switch SW1 The Power On RESET switch SW1 performs Power On reset to the PQ2 as if the power was applied to the ADS When the 2 is reset that way all configuration and all data residing in volatile memories are lost After PORST signal is negated the PQ2 re acquires the power on reset and hard reset configuration data from the hard reset configuration source Flash EEPROM 3 2 2 ABORT Switch 5 2 The ABORT switch is normally used to abort program execution this by issuing level 0 interrupt to the PQ2 If the ADS is in stand alone mode it is the responsibility of the user to provide means of handling the interrupt since there is no resident debugger with the PQ2FADS ZU The ABORT switch signal is debounced and may be disabled by software 3 2 3 SOFT RESET Switch SW3 The SOFT RESET switch SW3 performs Soft reset to the PQ2 internal modules maintaining PQ2 s configuration clocks amp chip selects and SDRAMs contents The switch signal is debounced and it is not possible to disable it by software 3 2 4 HARD RESET Switches SW2 amp SW3 When BOTH switches SW2 and SW3 are depressed simultaneously HARD reset is generated to the PQ2 When the PQ2 is HARD reset all its configuration is lost including data stored in the SDRAMs and the 2 has to be re initialized 1 Except for Hard Reset configuration word
72. RN58 RN59 RN61 RN62 RN64 RN65 RN69 RN95 RN97 RN98 RN99 CRA06S0803000RT DALE 44 RN31 RN33 RN34 RN35 470 065 0803 471 JRT1 DALE 45 RN36 RN37 RN38 RN39 RN93 RN94 43 CRA06S 0803430 RT DALE 46 RN76 RN78 RN79 RN80 33 CRA06S 0803330 R DALE 47 RP1 RP2 1K 3362P 1 102 BOURNS 48 83 R 1 R 38 R 48 R49 R50 R51 R59 R122 R135 R141 R 142 R143 R145 R146 R157 R158 R160 R161 R167 R169 R173 R174 R175 R177 R183 R184 R185 R191 R199 R201 R207 R208 R211 R214 R215 R217 R218 R219 R220 R221 R223 R228 R229 R230 R231 R245 R246 R247 R248 R253 R254 10K D11010KFCS ROEDER STEIN R267 R279 R293 R306 R 307 R318 R319 R328 R332 R341 R342 R 343 R 344 R 347 R 353 R356 R 368 R 379 R 383 R 384 R 389 8 390 R 396 R 406 R 407 R420 R421 R 422 R 428 R 431 R432 R433 206 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 49 8 R2 R3 R4 R5 R128 R129 75 D11075RFCS R130 R131 DRALORIK 50 4 R6 R15 R18 R19 49R9 D2549R9FCS ROEDER STEIN 51 4 R7 R13 R14 R17 78R7 D2578R7FCS D2578R7FCS 52 9 R8 R9 R10 R20 R24 R295 33R2 011 33R2FCS R303 R305 R312 ROEDER STEIN 53 2 R12 R11 158 CRCW0603 1580F
73. Setting MODCK 1 3 for PLLs Multiplication Factor SW6 6 8 10 2 3 4 Setting Hard Reset Configuration Source 7 11 2 3 5 setting Boot Source DEG Shee aS eee dk eee 12 2 3 6 Setting MODCKH 0 3 for PLLs Multiplication Factors 13 2 3 7 Setting PCI for PCI Bus 13 2 3 8 Setting PCI ARBITER for PCI Mode Enabled 13 2 3 9 Setting PCI DLL for PCI Mode Enabled 13 2 3 10 Setting Local Bus functionality SDRAM or PCI 13 60x Bus Party Support de be peek EE EO GR ER PENA E YS 14 2 3 12 Clock In Source selection 14 2 3 13 FCC2 Ethernet Port mode MII RMII 15 2 3 14 FCC3 Ethernet Port mode MII RMII 15 2 3 15 USB Sp eed sel gfti n u u ee OK we ed ew 16 23 16 USB M deselect n ote ER x ea dus 16 2 3 17 COP JTAG Connection 16 2 9 15 Power p SN he osos 16 Installation L 16 2 4 1 Host Controlled Operation 16 2 4 2 Stand Alone
74. Supply Figure 6 1 PQ2FADS ZU Power Scheme To support off board application development the power buses are connected to the expansion connectors so that external logic may be powered directly from the board The maximum current allowed to be drawn from the board on each bus also depends on the current drawn by the PCI bus The figures are shown in Table 6 1 Table 6 1 Expansion Connectors Maximum Current Consumption Power Bus Max Current VCC TBD V3 3 TBD The PCI Standard specifies that each Add In card should consume maximum 25 Watt from all power sources combined The maximum current consumption allowed per power source for a total of 25Watt according to the PCI Standard is shown in Table 6 2 Table 6 2 Maximum Power Consumption Per Add In Card Power Rail Add In Card 5V 5A Max system depended 3 3V 7 6A Max system depended 12V 500mA 12V 100mA 80 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 1 1 5V Rail Some of the PQ2FADS ZU peripherals not including the PCI Add In cards which should be 3 3V ONLY on the PCI interface but can use 5V for other components on board reside on the 5V bus Since the PQ2 15 not 5V tolerant buffering is provided between 5V peripherals and the PQ2 protecting the PQ2 from the higher voltage level 6 1 2 3 3V Rail The
75. Supply Connected to ADS s 5 VCC plane Provided as power supply for external tool B27 B28 B29 B30 B31 B32 GND Digital Ground Connected to main GND plane the ADS C2 CLK8 Buffered System Clock C3 GND Digital Ground Connected to main GND plane the ADS C4 BTOOLCS 1 Buffered Tool Chip Select 1 L This is a buffered PQ2 s CS6 line reserved for an external tool C5 BTOOLCS2 Buffered Tool Chip Select 2 L This is a buffered PQ2 s CS7 line reserved for an external tool C6 GND Digital Ground Connected to main GND plane the ADS C7 ATMEN ATM Port Enable L This line enables the ATM port UNI s output lines towards the PQ2 An external tool using the same pins as does the ATM port should consult this signal before driving the same lines Failure to do so might result in permanent damage to the PM5350 ATM UNI C8 ATMRST Port Reset L This signal resets the ATM UNI PM5350 An external tool may use this signal to its benefit C9 FETHRST Ethernet Port Reset L This signal resets LXT970 Ethernet transceiver An external tool may use this signal to its benefit C10 HRESET PQ2 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the PQ2 During that sequence asserted by the 2 for 512 system clocks Pulled Up on the ADS using a 1KQ resistor When driven by an external tool MUST be driven with an Open
76. The assignments selection is done via a dedicated jumper 7 PON DEF ATT FLASH 50 FLASH CS0 When asserted low CS0 is assigned to the FLASH SIMM and CS4 is assigned to E7PROM When negated 50 is assigned to the E PROM and CS4 is assigned to the FLASH SIMM The assignments selection is done via a dedicated jumper ATM EN ATM Port Enable When asserted low the ATM UNI chip PM5350 connected to FCC1 is enabled for transmission and reception When negated the ATM transceiver is in standby mode and its associated buffers are in tri state mode freeing all its i f signals for off board use via the expansion connectors RW ATM RST ATM Port Reset When asserted low the ATM port transceiver is in reset state This line is driven also by HRESET signal of the PQ2 RW FETHIEN1 Fast Ethernet Port 1 Initial Enable When asserted low the DM9161 s port residing on FCC2 is enabled after Power Up or after FETH RST is negated When negated high the DM9161 s MII port is isolated after Power Up or after FETH_RST is negated and all i f signals are tri stated After initial value has been set this signal has no influence over the 0 9161 isolation may be controlled 0 10 bit RW FETH1 RST Fast Ethernet port 1 Reset When active low the DM9161 is reset This line is also driven by HRESET signal of the PQ2 Since MDDIS pin of the DM9161 is driven low with this applica
77. WRITE IntMaskReg amp Slot2IntBMask DATA BIT pin Slot2IntBMask_ Active amp HardReset B 0 Slot2IntBMask_ PON DEFAULT Slot2IntBMask_Active HardReset B 0 amp Slot2IntB Mask DEFAULT Slot2IntBMask_ Active then Slot2IntBMask_Active else Slot2IntB Mask_Active MOTOROLA PQ2FADS ZU User s Manual 157 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information state diagram Slot2IntC Mask state Slot2IntC Mask Active WRITE IntMaskReg amp Slot2IntCMask DATA BIT pin Slot2IntC Mask Active amp HardReset B lt lt 0 Slot2IntCMask_PON DEFAULT Slot2lntC Mask Active HardReset B 0 amp Slot2IntC Mask PON DEFAULT Slot2IntCMask_Active then Slot2IntC Mask Active else Slot2IntC Mask Active state Slot2IntC Mask Active WRITE IntMaskReg amp Slot2IntCMask DATA BIT pin Slot2IntCMask Active B lt lt 0 Slot2IntCMask PON DEFAULT Slot2IntCMask_Active 3 HardReset B 2 0 amp Slot2IntCMask PON DEFAULT Slot2IntC Mask Active then Slot2IntC Mask Active else Slot2IntC Mask Active TOKIO KAKA IKARIA KAA KAKA IIA AIR RAR state diagram Slot2IntDMask state Slot2IntDMask Active WRITE IntMaskReg amp Slot2IntDMask DATA BIT pin Slot2IntDMask Active amp Hard
78. addresses 0 0 0x8 0x10 amp 0x18 b With L2 Cache c Programmed in BCSR Local Bus pins function is Local Bus d Programmed in FLASH Local Bus pins function is PCI Table 5 4 2 Power On Reset Configuration EEPROM Init Address Value hex Description hex 0 04 145 Internal arbitration Internal memory controller Core enabled Single PQ2 60X Bus mode 8 Bit Boot size Exceptions vectored to OXFFFxxxxx Internal space 64 bit slave for external master 8 B2 L2cache signals configured as BADDRx lines DP 1 7 configured as L2 cache and IRQ 6 7 Initial internal space 0 0 000000 74 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 4 2 Power On Reset Configuration EEPROM Init Address Value hex Description hex 10 36 Boot memory space OxFE000000 OxFFFFFFFF ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB No masking on bus request lines Local bus pins function as PCI PCI is boot master AP 1 3 configured as BNKSEL 0 2 APE configured as IRQ7 and CS11 as CS11 18 45 CS10 configured as BCTL1 a Programmed into the E PROM in addresses 0x0 0x8 0x10 amp 0x18 b With L2 Cache Table 5 5 SIU REGISTERS PROGRAMMING Init Register Value hex Description RMR 0001 Check Stop Reset enabled
79. also be reset by either asserting RST bit in BCSRI see Table 4 10 or by asserting 717 the RESET bit in the Master Reset and Identify Load Meters register via the UNI microprocessor interface The UNI transmit and receive clocks are fed with 19 44 MHz 20 ppm clock generator 5 V powered while the receive and transmit fifos clocks of the UTOPIA interface are provided by the PQ2 The 2 can provide the same clock for both UTOPIA transmit and receive or separate 54 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description clocks for each hard configured The ATM SAR is connected to the physical medium by an optical interface Use is done with HP s HFBR 5805 optical interface which operates at 1300 nm with upto 2 Km transmission range The ATM PHY is connected to IRQ7 and generates an interrupt when an appropriate event occurs NOTE When the 60x Data Parity option is on IRQ7 pin switches functionality to parity and the interrupt output is routed to IRQ3 It is the responsibilty of the user to set the appropriate functionality of the IRQ3 pin SIUMCR register NOTE When 16 bit UTOPIA bus is used the extra pins are in conflict with other functions In that case the16 bit UTOPIA bus will disable the USB RS232 port 2 and the Fast Ethernet MDC functions NOTE When Multi PHY UTOPIA bus is used the extra pins a
80. and Boot Code in EEPROM BOOT IN EEPROM bcsrConfEn 1 amp boot device B 1 HRESET Conf Word in BCSR and Boot Code in EEPROM HARD RESET ASSERTION HardReset 0 amp SyncHardReset B fb 0 amp DSyncHardReset B fb 1 CSO ASSERTED 50 B 0 CS4 ASSERTED 54 0 FIRST CFG BYTE READ 50 ASSERTED amp IDSyncHardReset B fb amp ConfAdd MOTOROLA PQ2FADS ZU User s Manual 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HRESET IN BCSR B SCND BYTE READ 50 ASSERTED amp IDSyncHardReset amp ConfAdd HRESET IN BCSR THIRD BYTE READ 50 ASSERTED amp IDSyncHardReset amp ConfAdd HRESET IN BCSR FORTH BYTE READ 50 ASSERTED amp IDSyncHardReset amp ConfAdd HRESET IN BCSR AIR ARIA KARA KAKA IIA AAI IKK Equations state diagrams 5 TORII ACOA ARIA RAIA KARA SHHHHHHE ii EE H Hi T f d HHH EH f f Sg d HF HHH f d HHH HH HHHH HHH TH HHH
81. and may be used for any available function of the PB27 90 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description C6 FETHCRS PB26 T S Fast Ethernet Carrier Sense H When this signal is asserted High while the Ethernet port is enabled and the LXT970 is in half duplex mode it indicates that either the transmit or receive media are non idle When the LXT970 is in either full duplex or repeater operation it indicates that the receive medium is non idle When the Ethernet port is disabled this line may be used for any available function of PB26 C7 FETHTXD3 PB25 T S Fast Ethernet Transmit Data 3 0 This is the MII transmit data bus The drives these lines according to rising edge FETHTXCK C8 FETHTXD2 PB24 When the ethernet port is disabled these lines may be used for any C9 FETHTXDI 23 available respective function C10 22 21 T S Fast Ethernet Receive Data 3 0 This is the receive data bus The LXT970 drives these lines according to rising edge of FETHRXCK C12 FETHRXDI PB20 When the ethernet port is disabled these lines are tristated and may be C13 F
82. be documented separately per each tool These signals are available at the System expansion connector PON DEF ATT TOOLREV 0 3 TOOL Revision 0 3 This field may contain the revision code of an external tool connected to the PQ2 The various combinations of this field will be described per each tool users manual These signals are available at the System expansion connector The revision option for the external tools are shown in Table 4 17 12 15 EXTTOLI 0 3 External Tools Identification These lines which are available at the CPM expansion connectors are intended to serve as tools identifier On board S W may check these lines to detect The presence of various tools h w expansions at the CPM expansion connectors For the external tools codes and their associated combinations see Table 4 14 16 17 SWOPT 0 1 2 Software Option 0 1 This field shows the state of a dedicated dip switches providing an option to manually change a program flow 18 19 L2CSIZE 0 1 L2 Cache Size 0 1 This filed encodes the size of the L2 Cache present on the PQ2FADS ZU For the encoding of the various cache sizes see Table 4 18 20 21 BVERN 0 1 Board Version Number 0 1 This field represents the version code hard assigned to the PQ2FADS ZU See Table 4 15 for version encoding 11 22 23 BREVN 0 1 Board Revision Number 0 1 This field represents the revision code hard as
83. bus 1 the Flash SIMM EPROM ATM UNI MPP interface PCI Interrupt Controller and BCSR are buffered while the SDRAM and the cache are not buffered from the 60X bus Latches are provided over address and strobe when necessary lines while transceivers are provided for data Use is done with 74ALVT buffers by Philips which are 3 3V operated and 5V tolerant and provide bus hold to reduce pull up pull down resistors count as required by the PQ2 This type of buffers reduces noise on board due to reduced transitions amplitude To further reduce noise and reflections serial damping resistors are placed over SDRAM address and all PQ2 strobe lines The data transceivers are open only if there is an access to a valid buffered board address or during Hard Reset configuration That way data conflicts are avoided in case an unbuffered memory read or off board memory is read provided that it is not mapped to an address valid on board It is the users responsibility to avoid such errors On the Local bus Bus Muxing devices are used to direct the local bus signal to either PCI slots or SDRAM according to the local bus functionality and therfore no use of buffers is done The PCI bus is not buffered at all because the PCI Standard is very strict and defines exactly the electrical characteristics of the bus which is buffer free 4 6 Chip Select Generator The memory controller of the PQ2 15 used as a chip select generator to acc
84. bus or USB port are enabled either one will conflict with the MDC and MDIO signals Therfore the MDC and MDIO functionality will switch to PC3 and PC2 respectively 4 13 3 RS232 Ports To assist user s applications and to provide convenient communication channels with both a terminal and a host computer two identical RS232 ports are provided on the PQ2FADS ZU connected to SCC1 and SCC2 ports of the PQ2 Use is done with MAX3241 transceiver which generates RS232 levels internally using a single 3 3V supply and has a standby mode When the 5232 RS232EN2 bits in are asserted low the corresponding transceiver is enabled When negated the corresponding transceiver is in standby mode within which the receiver outputs are tri stated enabling the use of the corresponding ports pins off board via the expansion connectors Nine pins female D Type stacked connector is used configured to be directly via a flat cable connected to a standard IBM PC like RS232 connector DCD ses 9 GND 5 Figure 4 13 RS232 Serial Ports Connector 4 13 3 1 RS 232 Ports Signal Description In the list below the directions I O and I O are relative to the POZ2FADS ZU board i e means input to the PQ2FADS ZU CD O Data Carrier Detect This line is always asserted by the PQ2FADS ZU TX Transmit Data e RX Receive Data 1 Not supported on
85. configuration words only the 1 st configuration word is influential 29 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc e PQ2FADS ZU without L2 Cache FLASH BCSR is the boot device CSO is assigned to the FLASH and CS4 is assigned to the E PROM PQ2FADS ZU without L2 Cache E PROM is the boot device CSO is assigned to the E PROM and CS4 is assigned to the FLASH e PQ2FADS ZU with L2 Cache FLASH is the boot device CSO is assigned to the FLASH and CS4 is assigned to the E PROM e PQ2FADS ZU with L2 Cache is the boot device 50 is assigned to the E PROM and CS4 is assigned to the FLASH Table 4 1 BCSR FLASH Hard Reset Configuration Word Data Prog Offset In Value Field Bus Value Implication Flash Hex Bits Bin Hex ERB 0 Internal Arbitration Selected 0 0C 1 8 1 0 Internal Memory Controller CSO active system boot CDIS 2 0 Core Enabled EBM 3 071 0 Single PQ2 Mode for boards without L2Cache 1 60X Bus Mode for boards with L2Cache BPS 4 5 11 32 Bit Boot Port Size CIP 6 0 Sets Core Initial Prefix MSR IP 1 so that system exception table is placed at address OxFFF00100 regardless of FLASH memory size ISPS 7 64 bit internal space for external master accesses In fact don t care on this board since externa
86. control status register In this file Prototype the following changes were made 12 03 02 Added support for in Hard Reset Config Word determined by external signal nPCI Mode oeoteteteteeteeteettetttetettttetetereeretereettettertertetetttttteretetetetetettetttteteteteteeter In this file Prototype the following changes were made 11 01 02 x Added support for USB Second Fast Ethernet PARITY option on 60x MUX control EKEK EEK In this file P rototype the following changes were made 07 15 02 MOTOROLA PQ2FADS ZU User s Manual 103 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Added support for a second Fast Ethernet PHY Removed support for fast down load through TAG
87. controlled 3 Dual RS232 ports residing on 5 amp SMC2 4 USB port 1 1 USB standard compliant with speed control 12 or 1 5 Mbps and mode control Host or slave 4 13 1 ATM Port To support the PQ2s ATM controller a 155 52Mbps User Network Interface UNI is provided on board connected to FCC1 of the PQ2 via UTOPIA I F Use is done with PM5384 S UNI 155 ULTRA by PMC SIERA Although these transceivers are capable of supporting 51 84Mbps rate support is given to 155 52Mbps only The PHY supports UTOPIA level 2 which means support for 8 or 16 bit UTOPIA bus in single or multi PHY mode The control over the mode of UTOPIA bus connection is done through BCSR3 The control over the transceiver is done using the microprocessor interface of the transceiver controlled by the PQ2 memory controllers GPCM Since the UNI is 5V powered and the 2 is 3 3V powered 5V intolerant the UNI is buffered LCX buffers from the PQ2 on both the receive part of UTOPIA interface and the microprocessor control ports The ATM transceiver may be enabled disabled at any time by writing 70 1 respectively to the ATMEN bit in BCSRx When ATMEN is negated 717 the microprocessor control port is also detached from the PQ2 and its associated FCC may be used off board via the expansion connectors The ATM transceiver reset input is driven by HRESET signal of the PQ2 so that the UNI is reset whenever hard reset sequence occurs The UNI may
88. controller board obtained from a third party developer Figure 2 15 shows the pin configuration of the connector TDO GND TDI QREQ TCK TMS SRESET e GND HRESET N C Im e 16 CKSTP OUT Figure 2 15 P15 COP JTAG Port Connector 2 4 4 Terminal to PQ2FADS ZU RS 232 Connection A serial RS232 terminal or any other RS232 equipment may be connected to the RS 232 connectors and The RS 232 connectors are 9 pin female D type connectors arranged in a stacked configuration connected to SCC2 of the PQ2 is the lower P1A connected to SCC1 of the PQ2 is the upper in the stack 18 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation The connectors are arranged in a manner that allows for 1 1 connection with the serial port of an IBM AT or compatibles i e via a flat cable The pinout which is identical for both and is shown in Figure 2 16 CD 1 RX Pas 1 8 CTS DIRNS 9 N C GND 5 Figure 2 16 P1A P1B RS232 Serial Port Connector 2 4 5 10 100 Base T Ethernet Ports Connection The 10 100 Base T port connectors P3 and P4 are an 8 pin 90 receptacle RJ45 connector The connection between the 10 100 Base T ports to the network is done by a standard cable having two RJ45 8 jacks on its ends The pinout of P3 and P4 is
89. data it holds is incorrect As a back up it holds the default Hard Reset configuration word and the default PCI configuration The Hard Reset configuration word stored in the E PROM differs from the one stored in the FLASH in the BPS field which is the Boot Port Size the E7PROM is 8 bits while the FLASH is 32 bits It uses a single chip select CSO or CS4 which depends on the chip select used by the Flash The selection of the chip select is done by a dip switch The E PROM connection scheme is shown in Figure 4 11 The device used is ATMEL AT28HC64B a 5V Byte alterable E PROM 150ns access time with byte wide JEDEC pinout Although the device is placed in a socket it can be programmed on board In order to program the device on board it has to be unlocked it can be locked to prevent unauthorized alterations of its contents The lock can be done by hardware or software The hardware lock is done by write inhibit the PQ2 does not assert WE during write cycles set in the BRx register The software lock is achieved by writing a unique sequence to the device To 1 It is required to do so anyway since L2Cache must operate within a full 64 bit data bus environment 50 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description unlock a different unique sequence has to be written E PROM Socket DATA 0 7 ADDRESS
90. multiples of its port size in bytes X depth E g BCSRO appear at memory locations 4700000 4700020 4700040 while BCSR1 appears at 4700004 4700024 4700044 and so on b The internal space of the ATM UNI control port is 256 bytes however the minimal block size tha may be controlled by the GPCM is 32 KBytes Initially at hOF000000 hOFOOFFFF set by hard reset configuration Refer to the PQ2 User s Manual for complete description of the internal memory map An 8 Kbyte device is used 16 Kbyte 32 Kbyte devices can also be used so it appears repeatedly in 8Kbyte multiples starting from C2000000 f Set by hard reset configuration Table 5 2 PQ2FADS ZU Memory E PROM as Boot Device Address Range 00000000 OOFFFFFF 01000000 O3FFFFFF Memory Type SDRAM DIMM 32 MByte Device Name 64 MByte Port Size 64 Memory Size 64 MByte 04000000 044FFFFF Empty Space 5 MByte MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 71 Freescale Semiconductor Inc Memory Map and Initialization Table 5 2 PQ2FADS ZU Memory Map E PROM as Boot Device Address Memor Port Device Name HOY Range Type Size Size 04500000 BCSR 0 7 8 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 0450
91. pins function as PCI bus APPC 22 23 MODCK1 AP 1 TC 0 functions as BKSELO MODCK2 AP 2 TC 1 functions as BKSEL1 MODCK3 AP 8 TC 2 functions as BKSEL2 IRQ7 APE functions as IRQ7 CS11 AP 0 functions as CS11 36 CS10PC 24 25 01 CS10 BCTL1 DBG_DIS functions as BCTL1 ALD_EN 26 PCI Auto Load Enable When high Bridge Configuration is done automatically from the FLASH E PROM is configuration source PPC core should be disabled right after the Hard Configuration Word When low the PPC Core should configure the PCI Bridge Reserved 27 Reserved MODCK HI 28 31 0101 Determines the Core s frequency out of power up reset Actually not relevant when the PCI is active since the PCI MODCK 0 3 take presidency 45 a For L2 Cache Boards b Applies only ONCE after power up reset MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 33 Freescale Semiconductor Inc The PCI configuration registers which are set at Hard Reset sequence are shown in Figure 4 1 0 Reserved Address Offset Hex Device ID 0x18C0 Vendor ID 0x1057 00 PCI Status PCI Command 04 BIST Control Header Type Latency Timer Cache Line Size PIMMR Base Address Register Figure 4 1 Host Configuration Registers 4 1 3 Soft Reset Soft Reset may be generated on the board fro
92. signal is asserted Low while the ATM port is enabled and ATMRFCLK goes high on octet of data is available at the PM5350 s ATMRXD 7 0 lines When negated while ATMRFCLK goes high data on ATMRXD 7 0 is invalid however driven When the ATM port is disabled this line may be used for any available function for PA28 B5 ATMRSOC PA27 T S ATM Receive Start Of Cell H When this signal is asserted High while the ATM port is enabled it indicates that the 1 st octet of data for the received cell is available at the PM5350 s ATMRXD 7 0 lines This line is updated over the rising edge of ATMRFCLK When the ATM port is disabled this line is tristated and may be used for any available function for PA27 B6 ATMRCA PA26 T S ATM Receive Cell Available H When this signal is asserted High while the ATM port is enabled and ATMRFCLK goes high it indicates that the PM5350 s receive FIFO is either full or that there are 4 empty bytes left in it PM5350 internal programming dependent When the ATM port is disabled this line is tristated and may be used for any available function of PA26 B7 ATMTXDO 25 T S ATM Transmit Data 7 0 When the ATM port is enabled this bus carries the ATM cell octets written to the PM5350 s transmit FIFO This 8 ATMTXDI PA24 bus is considered valid only when is asserted and are sampled on the rising edge of ATMTFCLK B ATMTXD2 PA2 I When
93. which is acquired only once after PON Reset MOTOROLA PQ2FADS ZU User s Manual 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions 3 2 5 SW5 Reset Configuration Switch SW5 is 4 switch Dip Switch For its function see Section 2 3 5 3 2 6 SW4 Software Options Switch SW4 is a 4 switch Dip Switch This switch is connected over SWOPT 0 2 lines which are available at BCSR2 S W options may be manually selected according to SW4 state SW4 is factory set to all ON See Figure 3 1 SWOPTO Pulled to 1 SWOPTO Driven to 70 SWOPT1 Pulled to 1 SWOPT1 Driven to 0 SWOPT 2 Pulled to 1 SWOPT2 Driven to 0 RESERVED SWI Figure 3 1 SW4 Description 3 2 7 P24 VDDL Voltage Level Range Selection P24 selects between 4 different voltage level ranges available for VDDL For further information over its function see Section 2 3 1 3 2 8 P13 IDDL Measurement JP13 resides in IDDL s main current flow To measure IDDL JP13 should be removed using a solder tool and a current meter should be connected instead with wires as short and thick as possible Warning The job of removing JP13 and soldering the cur rent meter connections instead is very delicate and should be done by a skilled technician If this process is done by unskilled hands or re peated more than 3 times permanent damage may occur to the PQ2FADS ZU
94. without L2Cache 47 60X Bus Mode for boards with L2Cache BPS 4 5 01 8 Bit Boot Port Size CIP 6 0 Sets Core Initial Prefix MSR IP 1 so that system exception table is placed at address OxFFF00100 regardless of FLASH memory size ISPS 7 64 bit internal space for external master accesses In fact don t care on this board since external master is not supported 32 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 2 2 Hard Reset Configuration Word Field L2CPC Data Bus Bits 8 9 Prog Value Bin Implication CI BADDR 29 IRG2 selected BADDR 29 WT BADDR 30 IRQ3 selected as BADDR 30 L2_HIT IRQ4 selected as unassigned CPU_BG BADDR 31 IRQ5 as BADDR 31 DPPC 10 11 Data Parity Pin configuration as DPO as EXT_BR2 DP1 as EXT_BG2 DP2 as EXT_DBG2 DP3 as EXT_BR3 DP4 as EXT_BG3 5 as EXT_DBG3 DP6 as IRQ6 DP7 as IRQ7 Reserved 12 Reserved ISB 13 15 010 IMMR initial value 0 0 000000 i e the internal space resides initially at this address Offset In Flash Hex 8 Value Hex B2 BMS 16 Boot memory at 0xFE000000 BBD 17 ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB MMR 18 19 Mask Masters Requests Boot Master is PCI LBPC 20 21 01 Local Bus
95. 0 10 Base T Ethernet Connector 85 7 3 Connector 2 tosi tele ew ER WE Eek E CE 85 7 4 P4 CPM Expansion Connector 87 7 5 9 Connectors 94 MOTOROLA PQ2FADS ZU User Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables 7 6 P27 ATX Power Supply Connector 96 7 7 PLS Lattice ISP Connector ne ees Ge ee OL ese ess ue 97 7 8 P17 System Expansion 98 7 9 USB Connector sooi seene EIE HEP 103 PQ2FADS ZU User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures 1 1 241 2 2 2 9 2 4 2 6 2 7 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 3 1 3 2 3 3 4 1 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 6 1 74 List of Figures PQ2FADS ZU Block Diagram 6 PQ2FADS ZU Top Side Part Location Diagram 8 VDL Raunge SelecHon P22 52 de oe hee us 9 Trimmer RP2 esi aute NI ects 10 ucc ue EPIS vr
96. 020 01 L D A SAMTEC 28 2 P 7 P 25 23762 23762 ERNI 29 3 8 9 10 145154 4 30 11 11 12 13 14 16 17 MICTOR38 2 767004 2 AMP 18 23 28 29 30 31 1 P15 LPH 16SA SG KCC 32 4 19 20 22 26 CON10AP TSM 10501 S DV AP SAMTEC 33 1 P21 SMB Straight 825 50 0 1 111 SUHNER 34 1 P24 CON6AP HEADER 3x2 SMT SAMTEC 35 1 P27 ATX_Power Connect 39 29 9202 MOLEX or 36 1 P31 DNR 25PCB SG DNR 25PCB SG KCC_Keltron 37 2 Q2 Q1 MMDF2P02HD MMDF2P02HD ON SEMI CONDUCTOR MOTOROLA PQ2FADS ZU User s Manual 205 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 38 04 0 3 MMDF4N01HD MMDF4N01HD ON SEMI CONDUCTOR 39 29 RN1 RN2 RN3 RN4 RN25 RN26 RN27 RN43 RN44 RN45 RN46 RN47 RN48 RN49 RN50 RN51 RN52 RN56 RN57 RN60 RN66 RN67 RN70 RN71 RN74 RN81 RN91 RN92 RN105 22 CRA3A4E 220 T AVX 40 35 RN5 RN15 RN16 RN17 RN18 RN20 RN21 RN23 RN24 RN28 RN29 RN30 RN32 RN40 RN41 RN42 RN53 RN54 RN75 RN82 RN83 RN84 RN85 RN86 RN87 RN88 RN89 RN90 RN96 RN100 RN101 RN102 RN103 RN104 RN106 10K RS8A1002 ROHM 41 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 10 CRA06S 0803100 R DALE 42 RN14 RN63 RN68 RN72 RN73 RN77 33 AVX 43 14 RN19 RN22 RN55
97. 08027 DACH I z Ll 91 5 5 H Y Y 4027 Li 74027 T 19027 sony 5 x ONT PaTquesse 30u uq uo spuedep p9TH a ou 2 Spaeoq eu 3T 5 602 lt jo x Iquesse jou 4seg 243 91H ur pe Tquesse ue ax EIVISI ZLVISL LIVISL 20 5 OVISI ZA3H1001 LASHIOOL OASHIOOL KZ s 5 99 zeny 0H AS rH 20 Ur DIS KX SOITON 104 lt 501 AU OL joL svoasu xnwas OL oo Bu 9868 3L 29 66 EAA mad lt 5
98. 12 C13 C14 C15 16 17 19 20 21 22 24 31 32 33 36 37 38 40 43 44 45 46 47 48 49 50 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 79 80 81 83 85 86 87 88 89 90 91 92 93 94 95 96 101 102 103 104 105 107 108 109 110 111 112 113 114 115 116 117 118 119 120 128 129 130 131 132 133 134 135 136 137 142 145 146 148 149 150 151 152 153 156 C157 C158 C159 C160 C161 C167 C168 C169 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C 184 C185 C186 C187 C188 C189 C190 C191 C194 C195 C 196 C197 C198 C199 C200 C201 C202 C203 C204 C205 C 206 C207 C208 C209 C210 C211 212 213 218 219 220 221 222 227 228 229 230 231 232 233 234 235 236 237 238 239 C240 C241 C242 C246 C251 C252 C253 C254 C255 C256 C257 C258 C259 C260 C261 C262 C263 C268 C269 C270 C271 C272 C273 C274 C275 100nF 0603Y C104KAT2A AVX MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 203 Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials C276 C277 C280 C281 C283 C288 C292 C294 C295 C296
99. 16 bus clock cycles and then re checks the state of the HRESET line HRESET is an open drain signal and must be driven with an open drain gate by which ever external source is driving it Otherwise contention will occur over that line which might cause permanent damage to either board logic and or to the 2 itself 4 1 2 1 COP TAG Port Hard Reset To provide convenient hard reset capability for a COP JTAG controller HRESET line appears at the COP JTAG port connector The COP JTAG controller may directly generate hard reset by asserting low this line 4 1 2 2 Manual Hard Reset To allow run time Hard reset when the COP controller is disconnected from the PQ2FADS ZU and to support resident debuggers manual Hard is facilitated Depressing both Soft Reset SW3 and ABORT SW2 buttons asserts the HRESET pin of the PQ2 generating a HARD RESET sequence Since the HRESET line may be driven internally by the PQ2 it must be driven to the PQ2 with an open drain gate If off board connected to the PQ2FADS ZU is to drive HRESET line then it should do so with an open drain gate this to avoid contention over this line When Hard Reset is generated the PQ2 is reset in a destructive manner i e the hard reset configuration is re sampled all registers except for the PLL s are reset including memory controller registers reset of which results in a loss of dynamic memory contents 28 PQ2FADS ZU User s Manual MOTOROLA
100. 17 31 BCSR E POE OE CSO EM WE p CS CS 0 64 T ICE Figure 4 11 E7PROM Connection scheme Additional address lines are connected to the socket according to the JEDEC format as an option to use E7PROM up to 32 KByte To allow proper operation with the L2 Cache the PQ2 needs to be set to 60X bus mode in which the address bus for the 2 is latched 4 11 PCI Bus The PQ2 has a PCI module which enables it to act as an Host Master or a Target On this board the PQ2 serves only as a PCI host a bridge between the PCI Bus and the PowerPC core The PQ2 PCI Bridge is designed to connect the PowerPC processor and memory system to the PCI system bus to which I O components are connected The PCI Bridge enables the PQ2 to gluelessly bridge PCI masters and agents to a PowerPC system host It uses a 32 bit multiplexed address data bus that can run from 25MHz up to 66MHz The interface provides address and data parity with error checking and reporting It also provides three physical address spaces 32 bit address memory 32 bit address I O and the PCI configuration space The PQ 2 also includes an on chip Arbiter which enables arbitration of up to three PCI masters Only three PCI slots are supported on the PQ2FADS ZU because of the Arbiter capacity Each slot can host either a PCI master or PCI target The PQ2 as a Bridge can support more PCI devices but that will require
101. 2 Cache is not present on the board the PQ2 is configured in Single PQ2 Mode Le assuming only one PQ2 on the 60x bus with no support for external master access This allows for internal address multiplexing to occur which makes the external address multiplexers redundant and therefore not assembled This improves SDRAM performance 4 4 2 60X Bus Mode When L2 Cache is installed the PQ2FADS ZU the PQ2 may no longer operate in single PQ2 mode since the address must be seen as is by the cache That requires the use of the external address multiplexers for the SDRAM In this mode SDRAM performance is decreased due to added wait state caused by the delay associated with the external multiplexers on the 1 st access in a NOTE In this mode only devices which are 60x com patible or devices which have 64 bit data bus and are buffered from the 60x bus can operate on the 60x bus This due to the 60x bus address tenure feature This means that when the L2 40 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Cache is used the Flash EEPROM BCSR and PCI Interrupt Controller are not accesible For further details consult the PQ2 User Manual 45 Buffering In order to achieve best performance it is necessary to reduce the capacitive load over the 60X bus as much as possible Therefore the slower devices on the
102. 2CACHE INHIBITED state 2 INHIBITED if WRITE BCSR 06 L2CACHE INH DATA BIT pin L2CACHE INHIBITED 6 RESET L2CACHE INH PON DEFAULT L2CACHE_INHIBITED PON RESET amp L2CACHE INH PON DEFAULT L2CACHE_INHIBITED then L2CACHE INHIBITED else IL2CACHE INHIBITED state diagram L2Flush B state L2CACHE FLUSHED if WRITE BCSR 06 MOTOROLA PQ2FADS ZU User s Manual 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information L2CACHE_FLUSH_DATA BIT pin IL2CACHE FLUSHED 6 RESET L2CACHE FLUSH PON DEFAULT L2CACHE_FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT L2CACHE _FLUSHED then IL2CACHE FLUSHED else L2CACHE FLUSHED state 2 FLUSHED WRITE BCSR 06 2 FLUSH DATA BIT pin L2CACHE FLUSHED amp RESET L2CACHE FLUSH PON DEFAULT L2CACHE_FLUSHED PON RESET amp L2CACHE FLUSH PON DEFAULT L2CACHE_FLUSHED then L2CACHE FLUSHED else IL2CACHE FLUSHED TRIO AKAROA RIA RAR AKA KAKA II AKA AIR IAA state diagram L2Lock B state L2CACHE LOCKED WRITE BCSR 06 2 LOCK DATA BIT pin 2 LOCKED 6 RESET L2CAC
103. 5 and BCSR7 Board Control Status Register 3 amp 5 5 5 to BCSR7 are additional control status registers which may be accessed as a word at offset 0x14 to 0x1C from BCSR base address These registers not implemented They may be read or written but with no valid data nor any effect on the board The description of BCSR3 and 1 Provided that BCSR is not disabled MOTOROLA PQ2FADS ZU User s Manual 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 5 5 is shown in Table 4 22 Table 4 22 BCSR5 to BCSR7 Description BIT MNEMONIC Function DER ATT 0 31 Reserved Un Implemented 4 15 COP TAG Port The COP Control Observation Port is part of the PQ2 s JTAG machine implemented as a set of additional instructions and logic within the JTAG permissions This port may be connected to a dedicated debug station for extensive system debug There are several third party debug solutions on the market These debug stations may be connected to the host computer via either Ethernet Parallel Port RS232 or any other media The debug station connection scheme is shown in Figure 4 14 Host Ethernet Media Adaptor RS232 USB 16 Wire Media Media To COP lt lat Cable Figure 4 14 Debug Station Connection Schemes To support debug station connection to the COP JT
104. 60X Main SDRAM Machine 1 CS3 SDRAM Local Bus SDRAM Machine 2 CS4 E2PROM Flash SIMM 60X Buffered GPCM CS5 ATM UNI Microprocessor 60X Main GPCM CS6 Communication Tool M P 60X Buffered GPCM UPMx Interface CS1 CS7 Communication Tool 60X Buffered GPCM UPMx Interface CS2 CS8 PCI Interrupt Controller 60X Buffered GPCM CS 9 11 Unused user available a Selection is done by a dip switch 4 7 Synchronous Dram 60X Bus To enhance performance especially in higher operation frequencies 32MBytes of SDRAM are provided on board The SDRAM is unbuffered from the PQ2 60X bus Use is done with two 32 2 by Micron or compatibles which each is X 32bit X 4banks The SDRAM s timing is controlled by SDRAM Machine 1 associated with 60X bus via its assigned Chip Select lines See Table 4 5 The SDRAM Machine supports PBI Page Bank Interleave which increases the SDRAM throughput The SDRAM connection scheme when no 5 When an unbuffered CS region is being accessed buffers do not open anyway 1 During read cycles 42 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Functional Description L2 cache is used is shown in Figure 4 5 2 2S2 650 SDRAS RAS SDCAS CAS SDWE WE BANKSEL 1 2 BA 1 0 A11 DA1 5 2 A10 A19 A9 A 20 28 SDDOM 07
105. 60x SDRAM Data Parity Support NOTE When using the Data Parity option IRQ6 and IRQ7 pins change functionality to Data Parity pins Therfore the two interrupt lines are switched to IRQ2 and IRQ3 so the user should be aware and switch to work with the relevant IRQs To be able to work with IRQ2 and this function must be enabled in SIUMCR register MOTOROLA PQ2FADS ZU User s Manual 45 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 8 Synchronous Dram Local Bus To enhance performance especially in higher operation frequencies 8MBytes of SDRAM are provided on board The SDRAM is unbuffered from the PQ2 local bus Use is done with one MTLC2M32B2 by Micron or compatibles which each is 512K X 32bit X 4banks The SDRAM s timing is controlled by SDRAM Machine 2 associated with local bus via its assigned Chip Select lines See Table 4 5 The SDRAM Machine supports PBI Page Bank Interleave which increases the SDRAM throughput The SDRAM connection scheme is shown in Figure 4 8 LSDRAS RAS LSDCAS CAS LSDWE WE LA 17 18 ERG LSDA10 LA20 21 29 A10 AQ LSDDOM 0 3 b 42 0 53 8 0 DQMB 0 3 DQ 0 63 CKE SYSCLK gt CLK MT48LC2M32B2 6 Figure 4 8 Local Bus SDRAM Connection Scheme 4 8 1 Local Bus SDRAM Programming After power up the SDRAM needs to be initialized by means of programming to est
106. 7FE3 04500004 BCSRI 4 Byte 04507FE7 04500008 BCSR2 4 Byte 04507FEB 0450000C BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001 BCSR7 4 Byte 04507FFF 04508000 Empty Space 1 MByte 045FFFFF 04600000 UNI Proc PMC5384 I F 8 32 KByte 04607FFF Control 04608000 Empty Space 1 MByte 046FFFFF 047000002 Internal 32 128 KByte 0471FFFF 04720000 Empty Space 64 KByte 0472FFFF 04730000 Interrupt 32 32 KByte 04737FFF Controller 04738000 Empty Space 800 KByte 047FFFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte O4FFFFFF 05000000 Empty Space Tool Board is located at 60000000 and 70000000 2 GByte 7FFFFFFF 80000000 PCI Memory PCI Agents GPL WIndows 32 1 Gbyte BFFFFFFF 72 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 2 PQ2FADS ZU Memory E PROM as Boot Device Address Memory Port Memory Device Name Size Size 0000000 Empty Space 32 MByte C1FFFFFF C2000000 Flash SIMM 32M SIMM 32 32 MByte C2FFFFFF SM73288 C3000000 16M SIMM C37FFFFF SM73248 C3800000 8M SIMM C3FFFFFF SM73228 C4000000 Empty Space 200
107. A IIR AIR RAK Slot0IntAMask_ DATA 00 5 DATA D1 Slot0IntC DATA D2 Slot0IntDMask_DATA_BIT 03 SlotiInthMask_ DATA 04 SlotlIntBMask DATA 05 SlotlIntC 06 126 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotlIntDMask DATA D7 Slot2IntAMask DATA 08 Slot2IntBMask DATA 09 Slot2IntCMask DATA 010 Slot2IntDMask DATA 011 Ijoleleleleleteletetetetetetetelerererererererererererererererereretetelerelerelelerelerelereleretetetetetetetetetetetetetetereterererererererererererererek Flash Declarations FLASH_ENABLE_ACTIVE 0 the presence detect encoding for the below is fictional needs to be updated with real data 29020 F_PD 8 1X 2 MByte bank SM73228XU1 PD 2 1X 8 MByte bank SM73248XU2 F_PD 1 2X 8 MByte banks SM73288XU4 0 4X 8 MByte banks FLASH BANK1 29020 SM73228XU1 SM73248XU2 amp 8 SM73288XU4 6 A7 amp A8 FLASH SM73248XU2 amp A8 SM73288XU4 amp 7 amp A8 FLASH 7 amp 8 6 SM73288XU4 FLASH_BANK4 7 amp A8 amp SM73288XU4
108. A29 READ BCSR 4 IBrdContRegCs B W amp 27 amp A28 amp 1429 x BCSR 0 definitions L2CACHE_INHIBITED 0 L2CACHE FLUSHED 0 L2CACHE LOCKED 0 L2CACHE CLEARED 0 SIGNAL LAMP ON 0 MOTOROLA PQ2FADS ZU User s Manual 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information TERIOR EEE ERA RK Power On Defaults Assignments 9 OIRO IIIA KICK L2CACHE INH PON DEFAULT L2CACHE INHIBITED L2CACHE FLUSH PON DEFAULT L2CACHE FLUSHED L2CACHE LOCK PON DEFAULT L2CACHE LOCKED L2CACHE CLEAR PON DEFAULT 12 CLEARED SIGNAL LAMPO PON DEFAULT 51 LAMP SIGNAL LAMP1 PON DEFAULT z SIGNAL LAMP Ijolelolelelelereteletereteretererererererererererererererererererelerelerelerelelelek Data Bits Assignments AOI
109. ABLE then IRS232 1 ENABLE else RS232 1 ENABLE state 5232 1 ENABLE WRITE BCSR 16 5 232 1 ENABLE DATA BIT pin 5232 1 ENABLE amp RESET 5232 1 ENABLE PON DEFAULT 5 232 1 ENABLE RESET amp 5232 1 ENABLE PON DEFAULT 25232 1 then 5232 1 ENABLE else IRS232 1 ENABLE MOTOROLA PQ2FADS ZU User s Manual 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Ijolololeleletereteretetetetetelelererererererererererererererererereteletelerelelerelerelereleretetetetetetetetetetetetereteretererererererererererererere state diagram 5 232 2 B state 5232 2 ENABLE if VGR_WRITE_BCSR_1 amp 5 232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp RESET RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE PON RESET amp RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE then IRS232 2 ENABLE else RS232 2 ENABLE state 5232 2 ENABLE WRITE BCSR 1 amp Atm16 amp AtmMultiPHY B amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp RESET RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE PON RESET amp 5232 2 ENABLE PON DEFAULT RS232 2 ENABLE then RS232 2 ENABLE else IRS232 2 ENABLE
110. ADS ZU User s Manual 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description these options are additional clock configuration bits PCI MODCKH 0 3 the most significant bits of the MODCK field which determine additional options for the clock generator Although these bits are sampled whenever the hard reset sequence is entered they are influential only once after power on reset If a hard reset sequence is entered later MODCKH 0 3 although sampled are don t care The PCI signal which is sampled concurrently with the 0 3 pins determines the PCI bus clock frequency see Section 2 3 7 When set high it divides the PCI bus frequency by two When reset low the PCI bus frequency is as determined by the MODCK 1 3 and PCI MODCKH 0 3 signals 4 1 2 Hard Reset Hard Reset may be generated on the ADS by the following sources 1 COP JTAG Port 2 Manual Hard reset 3 PQ2 s internal sources Hard Reset when generated causes the PQ2 to reset all its internal hardware except for PLL logic re acquires the Hard reset configuration from its current source and jumps to the Reset vector in the exception table Since hard reset resets also the refresh logic for dynamic RAMs their content is lost as well HRESET when asserted is extended internally by the PQ2 for additional 512 bus clock cycles at the end of which the PQ2 waits for
111. AES 4 13 2 100 10 Base T 2 41 DM9161 Control puhu 413 3 RS232 POFIS 2 59S Zo xn pee ee I 4 13 3 1 RS 232 Ports Signal Description tt ants shad tates CN EA 4 13 5 PG Parallel Port aa eke 4 14 Board Control amp Status Register 4 14 1 BCSRO Board Control Status Register O 4 14 2 BCSRI Board Control Status Register 4 14 3 BCSR2 Board Control Status Register 2 4 14 4 BCSR3 Board Control Status Register3 4 14 5 BCSR4 Board Control Status Register 4 4 14 6 BCSR5 and BCSR7 Board Control Status Register 3 amp 5 415 COP JPAG Poit tae wie ioe Section 5 Memory Map and Initialization 5 1 Memory Mapin y epp ui ayasa v RUD ROCA E ts 5 2 2 Register Programming 3 21 System a 5 2 2 Memory Controller Registers Programming Section 6 Physical Properties 6 1 POVE Spp 653 eis adi a irs etta Clg SV yasa Set uq ALL os sue hae p Edo 6 1 3 5V Stand B
112. AG port a 16 pin generic header connector is provided on PQ2FADS ZU carrying the COP JTAG signals as well as additional signals aiding in system debug The pinout of this connector which is a general Motorola recommendation for including a COP JTAG port in a design is shown in Figure 4 15 and detailed 1 Not provided with the PQ2FADS ZU 66 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description in Table 4 23 TDO TDI QREQ TCK TMS SRESET HRESET CKSTP_OUT Figure 4 15 COP JTAG Port Connector Table 4 23 COP JTAG Port Signals Description Pin No Signal Name Attribute Description 1 TDO Transmit Data This the JTAG s serial data output driven by Falling edge of TCK 2 N C Not Connected 3 TDI Transmit Data In This is the JTAG serial data input sampled by the PQ2 on the rising edge of TCK This line is pulled up internally by the PQ2 4 TRST Test port Reset 1 When this signal is active Low it resets the JTAG logic This line is pull down on the PQ2FADS ZU with a 1 resistor to provide constant reset of the JTAG logic 5 QREQ Quiescent Request L When asserted low this line indicates that the PQ2 desires to enter low power mode This signal may be required by a debug station 6 V3 3 3 3V power supply bus 7 TCK Test por
113. ASH amp DSyncHardReset_B fb CS4 ASSERTED amp FLASH amp HRESET BOOT IN EEPROM EEPROM IFlashCs4 B 50 ASSERTED amp FLASH amp HRESET BOOT IN FLASH CSO ASSERTED amp FLASH BANK4 amp BOOT IN FLASH amp DSyncHardReset CS4 ASSERTED amp FLASH amp HRESET BOOT IN EEPROM EEPROM EEpromCs B oe H IEEpromCs 50 ASSERTED amp HRESET BOOT IN EEPROM 50 ASSERTED amp BOOT EEPROM amp DSyncHardReset CS4 ASSERTED amp HRESET BOOT IN FLASH BOOT IN FLASH UNI Chip Select Ibeepetlllreetetttttetttetteettteterertetelereerertetelererererererererererererererererereretetetetererereretetetetejele equations AtmUniCsOut B oe H IAtmUniCsOut B AtmUniCsIn B MOTOROLA PQ2FADS ZU User s Manual 165 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information x Power On Reset equations S PORIn B clk SYSCLK S PORIn B ar 0 S PORIn B ap 0 S PORIn B PORIn
114. BMask state SlotlIntBMask Active if VGR WRITE IntMaskReg amp SlotlIntBMask DATA BIT pin SlotlIntBMask Active amp HardReset B 2 0 SlotllntBMask PON DEFAULT SlotlIntBMask Active 3 HardReset B 0 amp SlotlIntBMask PON DEFAULT SlotlIntBMask Active then ISlotlIntBMask Active else SlotlIntBMask Active state 5 Active if VGR WRITE IntMaskReg amp 154 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotlIntBMask DATA BIT pin SlotilntBMask_ Active amp HardReset B 0 SlotilntBMask_ PON DEFAULT SlotllntBMask_Active HardReset B 0 amp SlotlIntB Mask PON DEFAULT SlotlIntBMask Active then SlotlIntBMask Active else ISlotlIntBMask Active state diagram SlotlIntC Mask state SlotlIntC Mask Active WRITE IntMaskReg amp SlotlIntCMask DATA BIT pin SlotlIntC Mask Active amp HardReset B 0 SlotllIntCMask PON DEFAULT SlotlIntCMask Active HardReset B 0 amp SlotlIntC Mask PON DEFAULT 15 Active then SlotlIntC Mask Active else SlotlIntC Mask Active state SlotlIntC Mask Active if VGR WRITE IntMaskReg amp Slotl
115. C2605 will stop 1 RW entering new data into the cache while yet maintaining existing data and responding to cacheable cycles This signal has no function in a PQ2FADS ZU that does not have an L2 Cache installed 5 L2C CLEAR L2 Cache Clear When this bit is active Low for min 8 bus clock cycles 1 RW the L2 cache invalidates all its entries without flushing the same process as with HRESET asserted However it still monitors the bus so it can immediately respond when this process ends This signal is connected to the L2 TAG CLR of the MPC2605 but has no function when a cache is not installed on the PQ2FADS ZU 6 31 Reserved Un implemented 0 R 4 14 2 BCSR1 Board Control Status Register 1 The is a control register on the PQ2FADS ZU It is accessed at offset 4 from BCSR base address It may be read or written at any time BCSR1 gets its defaults upon Power On reset The 1 Provided that BCSR 15 not disabled 2 Provided that BCSR is not disabled MOTOROLA PQ2FADS ZU User s Manual 59 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc fields are described in Table 4 10 Table 4 10 BCSR1 Description BIT MNEMONIC Conf_Word Function Config_Source When asserted low Hard Reset Configuration Word is sourced from the BCSR When negated Hard Reset Configuration Word is sourced from the FLASH EEPROM
116. DALE 54 25 R16 R21 R26 R27 R67 R68 22R1 D1122R1FCS R69 R70 R202 R203 R209 R210 R270 R274 R282 R292 R297 R 308 R 309 R 310 R 311 R329 R 330 R 333 R 334 ROEDER STEIN 55 53 R22 R23 R25 R28 R 29 R 30 4K7 D1104K7FCS R35 R36 R37 R41 R 42 R 43 R45 R46 R47 R85 R95 R100 R162 R163 R170 R179 R180 R194 R195 R205 R216 R224 R225 R226 R227 R233 R234 R235 R236 R237 R251 R252 R255 R256 R263 R264 R 265 R266 R275 R276 R277 R287 R300 R301 R320 R324 R331 ROEDER STEIN 56 52 R31 R33 R 39 R 40 R 44 91 1 D11001KFCS R94 R96 R97 R116 R117 R119 R120 R121 R148 R204 DRALORIK R212 R213 R239 R240 R259 R260 R261 R268 R269 R271 R272 R273 R285 R286 R 288 R289 R 337 R 338 R348 R 352 R 354 R358 R 369 R 378 R 386 R387 R391 R 392 R 394 R 395 R397 R405 R 416 R 419 R 429 R430 57 1 R32 2K2 D2502K2FCS ROEDER STEIN 58 2 R178 R34 510 CRCW0603 5100F DALE 59 28 R52 R53 R54 R55 R56 R57 330 R58 R62 R64 R 89 2 90 7 92 R93 R 102 R 103 R 106 R 108 R372 R 373 R 375 R 377 R 400 R401 R402 R 409 R 423 R 424 R427 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 207 Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 60 27 R60 R79 R110 R111
117. DMask Active 6 HardReset B 2 0 Slot lntbMask PON DEFAULT Slot0IntDMask_Active 3 HardReset B 0 amp Slot0IntDMask_ PON DEFAULT SlotOIntDMask Active then Slot lntDMask Active else Slot0IntDMask_Active state diagram SlotlIntAMask state SlotlIntAMask Active WRITE IntMaskReg amp MOTOROLA PQ2FADS ZU User s Manual 153 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SlotlIntAMask DATA BIT pin SlotllInthMask_ Active amp HardReset B 0 SlotlIntAMask_ PON DEFAULT SlotllntAMask_Active HardReset B 0 amp 5 DEFAULT SlotlIntAMask Active then ISlotlIntAMask Active else SlotlIntAMask Active State SlotllnthMask_Active if VGR WRITE IntMaskReg amp SlotlIntAMask DATA BIT pin SlotilntAMask_ Active amp HardReset B 0 SlotilntAMask_ PON DEFAULT SlotlIntAMask Active HardReset B 0 amp 5 PON DEFAULT SlotllntAMask_ Active then SlotlIntAMask Active else ISlotlIntAMask Active state diagram SlotlInt
118. ETHRXD2 PB19 used for any available respective parenthesized function 14 FETHRXD3 18 15 PB17 T S PQ2 s Port B 17 4 Parallel I O lines May be used to any of their available functions C16 PB16 C17 15 C18 PB14 C19 PB13 C20 PB12 C21 22 PB10 C23 9 C24 PB8 C25 PB7 C26 PB6 C27 PBS C28 PB4 C29 ATMRCLK T S ATM Receive Clock A divide by 8 of the ATM line clock recovered by the ATM receive logic Provided to assist Circuit Emulation Tool Enabled only when pin A29 of this connector is either not connected or driven low Otherwise Tri stated MOTOROLA PQ2FADS ZU User s Manual 91 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description C30 GND Digital Ground Connected to main GND plane the ADS C31 C32 D1 PC31 T S PQ2 s Port 31 22 Parallel I O lines May be used to any of their available functions D2 PC30 D3 PC29 D4 PC28 05 27 D6 PC26 D7 PC25 D8 PC24 D9 PC23 D10 PC22 D11 ATMTFCLK PC21 T O T S ATM Transmit FIFO Clock Upon the rising edge of this clock driven by the PQ2 while the ATM port is enabled the cell octets are written to the PM5350 s transmit FIFO This clock samples ATMTXD 7 0 ATMT
119. E_IntMaskReg amp Slot lntCMask DATA BIT pin Slot0IntC Mask Active amp HardReset 0 Slot lntCMask PON DEFAULT Slot0IntC Mask Active HardReset B 0 amp Slot0IntC Mask DEFAULT Slot0IntCMask_ Active then Slot0IntC Mask Active else Slot0IntC Mask Active state Slot0IntC Mask Active if VGR WRITE IntMaskReg amp Sloto lntCMask DATA BIT pin SlotO lntCMask Active HardReset B lt lt 0 Slot0IntCMask PON DEFAULT Slot0IntCMask_Active 152 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information HardReset B 0 amp Slot0IntCMask_ PON DEFAULT Slot0IntC Mask Active then Slot0IntC Mask Active else Slot0IntC Mask Active state diagram Slot0IntDMask state Slot lntDMask Active if VGR WRITE IntMaskReg amp Sloto lntDMask DATA BIT pin SlotOIntDMask Active amp HardReset 0 Slot lntDMask PON DEFAULT Slot0IntDMask_Active 3 HardReset B 0 amp Slot olntbDMask PON DEFAULT z SlotOlntDMask Active then Slot0IntD Mask_Active else Slot0IntDMask_Active state Slot0IntDMask_Active if VGR_WRITE_IntMaskReg amp Sloto lntDMask DATA BIT pin SlotO lnt
120. F is negated during HRESET asserted or taken from the Flash l E PROM BCSR MS 8 bits of the data bus in case RSTCONF signal is asserted along with HRESET The default configuration word can be taken from the E PROM BCSR in case the Flash has been tampered with The selection between the BCSR FLASH and the E PROM as the source of the default configuration word is determined by a dedicated dip switch see Section 2 3 5 and a jumper see Section 2 3 4 During hard reset sequence the configuration master reads the Flash or E7PROM or BCSR memory at addresses 0 8 0x18 0x20 a byte each time to assemble the 32 bit configuration word A total of 64 bytes of data 1s read from D 0 7 to acquire 8 full configuration words for system that may have upto 8 PQ2 chips The configuration word for a single PQ 2 is stored in the Flash memory SIMM in the E PROM or as default in the BCSR while the other seven words are not initialized as there are no additional PQ2 on the PQ2FADS ZU The default configuration word is shown in Table 4 1 for the FLASH and in Table 4 2 for the 2 PCI module configuration is 256 Bytes long and should start at address Ox 100 There are four possible configuration words In general from any device residing on CSO 2 In general The PQ2 for which RSTCONF is asserted along with PORST asserted or in particular the PQ residing on PQ2FADS ZU 3 Although the 2 as configuration master reads 8
121. FADS ZU User Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables List of Tables 1 1 PQ2FADS ZU specifications 122i b ke aei prx 5660 ERU pa at 3 2 1 CS Encoding uuu la ac px ca et eae 11 4 1 BCSR FLASH Hard Reset Configuration Word 30 4 2 E2PROM Hard Reset Configuration Word 22 4 3 PCI Interrupt Register Description 37 4 4 PCI Interrupt Mask Register Description 38 4 5 PQ2FADS ZU Chip Select Assignments 42 4 6 100 MHz SDRAM Mode Register Programming 44 4 7 100 MHz SDRAM Mode Register Programming 47 4 8 L2 Cache CFG 0 2 Settings au testo 33 4 9 BCSRO Description EG e Gorka p byes GE Ae RAI bebe 59 4 10 BESRI DeserIipti6n Sack buda tes 60 4 11 BCSR2 Description TEE AQ TIR 61 4 12 FLASH Presence Detect 7 5 Encoding 62 4 13 FLASH Presence Detect 4 1 Encoding 62 4 14 EXTOOLI U3 JASSIBDIDODE 5222 56 Rony ee 62 4 15 PQ Board Version Encoding 4 3 sepone FEN 63 4 16 PQ2 Board R
122. GO 16 MByte 2 banks of 4 X 2M X 8 by Smart Modular 0010 Technology SM73228XG1JHBGO 8 MByte 1 bank of 4 X 2M X 8 by Smart Modular 0011 1111 Not Supported Table 4 14 EXTOOLI 0 3 Assignment EXTTOOLI 0 3 External Tool 0 T ECOM PQ2 Communication tool 1 Reserved 2 T1 Circuit Emulation Tool 3 E Reserved F Tool Non Existent 62 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Functional Description Table 4 15 PQ2 Board Version Encoding Version Number 0 1 Hex 0 PQ2 Board Version PQ2 Voyager ADS 1 Reserved 2 PQ2 Add In Card 3 Motherboard Table 4 16 PQ2 Board Revision Encoding Revision Number 0 1 Hex 0 PQ2 Board Revision ENG Engineering 1 PILOT 2 A 3 Reserved Table 4 17 External Tool Revision Encoding TOOLREV 0 3 hex External Tool Revision 0 ENGINEERING 1 PILOT 2 A 3 F Reserved Table 4 18 L2 Cache Size Encoding L2CSIZE 0 1 L2 Cache Size 00 Reserved 01 512 KBytes 10 Reserved 12 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 63 Functional Description Freescale Semiconductor Inc 4 14 4 BCSR3 Board Contr
123. HE LOCK PON DEFAULT L2CACHE_LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT L2CACHE_LOCKED then IL2CACHE LOCKED else L2CACHE LOCKED state L2CACHE LOCKED WRITE BCSR 06 2 LOCK DATA BIT pin L2CACHE LOCKED 6 RESET L2CACHE LOCK PON DEFAULT 2 LOCKED PON RESET amp L2CACHE LOCK PON DEFAULT L2CACHE_LOCKED then 132 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information L2CACHE_LOCKED else IL2CACHE_LOCKED state diagram L2Clear state L2CACHE CLEARED WRITE BCSR 0 amp 2 CLEAR DATA BIT pin 2 CLEARED amp RESET L2CACHE CLEAR PON DEFAULT L2CACHE_CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT L2CACHE_CLEARED then IL2CACHE CLEARED else L2CACHE CLEARED state 2 CLEARED WRITE BCSR 06 2 CLEAR DATA BIT pin L2CACHE CLEARED amp RESET L2CACHE CLEAR PON DEFAULT IL2CACHE CLEARED PON RESET amp L2CACHE CLEAR PON DEFAULT L2CACHE_CLEARED then L2CACHE CLEARED else IL2CACHE CLEARED Ibpelllreetettlttttttttttettetererttelterreteteereteteteterrertetete
124. IMMR 04700000 Internal space 0x047000000 SYPCR FFFFFFC3 Software watchdog timer count FFFF Bus monitor timing FF PPC Bus monitor Enabled Local Bus monitor Enabled S W watch dog disabled S W watch dog if enabled causes reset S W watch dog if enabled prescaled BCR 100C0000 Single PQ2 60X Bus mode 1 wait states on address tenure L2Cache 884440009 L2Cache assumed 1 clock hit delay when L2cache available 1 level Pipeline depth Extended transfer mode enabled for PCC Extended transfer mode disabled for Local Buses Odd parity for PPC amp Local Buses External Master delay enabled Internal space responds as 64 bit slave for external master not relevant for this application a With L2 Cache 5 2 2 Memory Controller Registers Programming The memory controller on the PQ2FADS ZU is initialized to 100MHz operation i e registers programming is based on 100MHz timing calculation it will also work for slower bus speeds but the timing will have to be optimized There are two possible initializations for the memory controller e Flash SIMM is assigned to CSO and is assigned to CS4 Flash SIMM is assigned to CS4 and E PROM is assigned to CSO PQ2FADS ZU User s Manual 75 For More Information On This Product Go to www freescale com MOTOROLA Memory and Initialization Freescale Semiconductor Inc Both options are shown in Table 5 6 and Table 5 7 Table 5 6
125. IRQ3 It is the responsibilty of the user to set the appropriate functionality of the IRQ3 pin SIUMCR register 4 13 2 1 DM9161 Control The DM9161 is controlled via the MII management port which is a 2 wire interface a clock 1 Using resistors 2 Also known as MII MDIO port MOTOROLA PQ2FADS ZU User s Manual 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description MDC and a bidirectional data line MDIO This is in fact a bus 1 up to 32 devices may reside over it while the protocol defines a 5 bit slave address field which is compared against the slave address set to each device by hardware during device reset according to the levels on some pins On the board the slave address is hard set to b00000 for FCC2 and b00011 for FCC3 The PQ 2 interfaces this port using two pins PC9 for and 10 for MDC There is no special support within the PQ2 for the MDIO port and the protocol is implemented in S W The MDIO port may interrupt a host in 2 ways a driving low the MDIO line during IDLE time or b using a dedicated interrupt line MDINT This line is connected to the PQ2 s DP7 CSE1 IRQ7 line appearing also at the CPM expansion connectors Since IRQ7 may also be driven by any tool connected to the expansion connectors it should be driven with an Open Drain buffer IRQ7 is pulled up on the board NOTE If ATM 16 bit UTOPIA
126. IntCMask DATA BIT pin SlotllntCMask Active HardReset lt lt 0 SlotlIntCMask_ PON DEFAULT SlotlIntCMask Active HardReset B 0 amp SlotllIntCMask PON DEFAULT SlotlIntC Mask Active then SlotlintC Mask Active else 15 Mask Active state diagram SlotlIntDMask MOTOROLA PQ2FADS ZU User s Manual 155 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information state SlotlIntDMask Active WRITE IntMaskReg amp SlotlIntDMask DATA BIT pin SlotlIntDMask Active amp HardReset 0 SlotlIntDMask PON DEFAULT SlotlIntDMask Active HardReset B 0 amp SlotlIntDMask_ DEFAULT SlotlIntDMask_ Active then SlotlIntDMask_Active else SlotlIntDMask Active state SlotlIntDMask Active if VGR WRITE IntMaskReg amp SlotlIntDMask DATA BIT pin SlotlIntDMask Active HardReset B 0 SlotllntbMask PON DEFAULT SlotllntDMask Active HardReset B 0 amp SlotllIntDbMask PON DEFAULT SlotlIntDMask Active then SlotlIntDMask Active else ISlotlIntDMask Active
127. IntD Active RACIAL PCI Interrupt Mask Register AIR Ijolelolelelelereteretetetetetererererererererererererererererererereteretelerelelerelerelereleretetetetetetetetetetetetereteteterererererererererererererek equations IntMaskReg clk SYSCLK 150 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IntMaskReg ar 0 IntMaskReg ap 20 state diagram Slot0IntAMask state Slot lntAMask Active WRITE IntMaskReg amp 5 DATA BIT pin Slot0InthMask_ Active amp HardReset B lt lt 0 Slot0IntAMask_PON DEFAULT Slot0IntAMask_Active 3 HardReset B 0 amp Slot0IntAMask PON DEFAULT SlotOlntAMask Active then Slot0IntAMask_Active else Slot0IntAMask_ Active state Slot0IntAMask_Active if VGR WRITE IntMaskReg amp Slot lntAMask DATA BIT pin Slot0IntAMask_ Active amp
128. LED WRITE BCSR 36 FETH2 ENABLE DATA BIT pin FETH2 ENABLED amp RESET FETH2 ENABLE PON DEFAULT FETH2_ ENABLED PON RESET amp FETH2 ENABLE PON DEFAULT 2 ENABLED then FETH2 ENABLED else 140 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 2 ENABLED Ijoleloleleletereteretetetetetelelererererererererererererererereretetelerelerelelerelerelerelejetetetetetetetetetetetetetetereterererererererererererererek state diagram FEthRst2 B state FETH2 RESET ACTIVE WRITE BCSR 3 amp FETH2 RESET DATA BIT pin FETH2 RESET ACTIVE 6 RESET FETH2 RESET PON DEFAULT 2 RESET ACTIVE PON RESET amp FETH2 RESET PON DEFAULT 2 RESET then IFETH2 RESET ACTIVE else FETH2 RESET ACTIVE state FETH2 RESET ACTIVE WRITE BCSR 36 FETH2 RESET DATA BIT pin FETH2 RESET ACTIVE amp RESET FETH2 RESET PON DEFAULT FETH2 RESET PON RESET amp FETH2 RESET PON DEFAULT FETH2 RESET ACTIVE then FETH2 RESET ACTIVE else IFETH2 RESET ACTIVE AKA AKA AIR state diagram Atm16 B state ATM16 ENABLED WRITE BCSR 36 ATM16 ENABLE DATA BIT pin ATM16 ENABLED am
129. LT USB SPEED then IUSB SPEED HIGH else USB SPEED HIGH state USB SPEED HIGH WRITE BCSR 36 USB SPEED DATA BIT pin USB SPEED HIGH 6 RESET USB SPEED PON DEFAULT USB SPEED HIGH PON RESET amp USB SPEED PON DEFAULT USB SPEED then USB SPEED HIGH else IUSB SPEED HIGH TORK ARIA ARAKI ARAKI KAA AIR AHA AR RIK state diagram US BVccO state USB VCCO ON WRITE BCSR 36 MOTOROLA PQ2FADS ZU User s Manual 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information USB VCCO DATA BIT pin USB VCCO_ON amp RESET USB VCCO PON DEFAULT 058 ON PON RESET amp USB VCCO PON DEFAULT USB VCCO ON then IUSB VCCO ON else USB VCCO state USB VCCO ON WRITE BCSR 36 USB VCCO DATA 05 VCCO ON amp RESET USB VCCO PON DEFAULT USB VCCO PON RESET amp USB VCCO PON DEFAULT USB VCCO then USB VCCO ON else IUSB VCCO TERIOR KAKA RACIAL KAKA IAA AIR State_diagram FEthEn2_B state FETH2 ENABLED WRITE BCSR 36 FETH2 ENABLE DATA BIT pin FETH2 ENABLED amp RESET FETH2 ENABLE PON DEFAULT 2 ENABLED PON RESET amp FETH2 ENABLE PON DEFAULT FETH2 ENABLED then IFETH2 ENABLED else FETH2 ENABLED state FETH2 ENAB
130. MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information PQ2FADS ZU User s Manual 185 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information 186 EL BELZI D a mm Tin By T simia EE HESS ERE A ams AIT 14 BELT PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information PU DIPPET uu sa p a uil L mccum Erroi iij m L mm HH BBS H ral an E P PQ2FADS ZU User s Manual 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Freescale Semiconductor Inc 188 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information
131. Mode selection The USB port supports two modes Host and Slave The selection is software controlled in the BCSR At power up the default selection is Host 2 3 17 COP TAG Connection There are two options to connect to the COP port of the PQ2 COP JTAG connector or a Parallel port of a PC The COP JTAG connector requires a command converter while the second option connects directly to the parallel port of a PC and eliminates the need for one The selection is done automaticaly if a cable is connected to the parallel port in a PC then this connection has the priority over the COP JTAG connector 2 3 18 Power On Off Switch The Power On or Off is done by switching SW7 2 4 Installation Instructions When the PQ2FADS ZU has been configured as desired by the user it can be installed according to the required working environment as follows Host Controlled Operation Stand Alone 2 4 1 Host Controlled Operation In this configuration the PQ2FADS ZU is controlled by a host computer via the COP port which is a subset of the JTAG port This configuration allows for extensive debugging using on host 16 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation debugger There are two options to connect to the COP port 1 The host is connected to the board by a COP controller command converter provided by a th
132. Not Connected 8 INTD Not Connected 5V 9 PRSNT1 Connected to GND Reserved Not Connected 10 Reserved Not Connected 3 3V I O 11 PRSNT2 Connected to GND Reserved Not Connected 12 CONNECTOR 3 3 volt key CONNECTOR 3 3 volt key KEY KEY 13 CONNECTOR 3 3 volt key CONNECTOR 3 3 volt key KEY KEY 14 Reserved Not Connected 3 3Vaux Not Connected 15 Ground RST 16 CLK 3 3 I O 17 Ground GNT 18 REQ Ground 19 3 3V PME Not Connected 20 AD 31 AD 30 21 AD 29 3 3 94 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Support Information Table 7 5 P7 P9 Connectors Side Comments Side A Comments 22 Ground AD 28 23 AD 27 AD 26 24 AD 25 Ground 25 3 3V AD 24 26 3 IDSEL 27 AD 23 3 3 28 Ground AD 22 29 AD 21 AD 20 30 AD 19 Ground 31 3 3V AD 18 32 AD 17 AD 16 33 C BE 2 3 3V 34 Ground FRAME 35 IRDY Ground 36 3 3V TRDY 37 DEVSEL Ground 38 Ground STOP 39 LOCK Not Connected 3 3V 40 PERR SDONE Not Connected 41 3 3V SBO Not Connected 42 SERR Ground 43 3 3V PAR 44 C BE 1 AD 15 45 AD 14 3 3 46 Ground AD 13 47 AD 12 AD 11 48 AD 10 Ground 49 M66EN Coupled to GND AD 09 using 0 01uF capacitor 50 Ground Ground 51 Ground Ground MOTOR
133. O D SoftReset B PIN 17istype Actual soft reset output O D 30 connected to N C of Abort 108 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 29 connected of Abort P B NMIEn NODE _istype enables T S NMI pin B PIN 20istype Actual NMI pin O O D Data Buffers Enables and Reset configuration support EKEK EEKE _ 102 Transfer Error Acknowledge DataBufEn B PIN 85istype com invert data buffer enable ToolCs1 B PIN 27 comm toolcs line 1 ToolCs2 B 21 comm tool cs line 2 ToolDataBufEn B PIN 9listype com invert tool data buffer enable x Hard Reset Configuration Logic boot device B PIN 118 selects EEPROM FLASH B as boot device bcsrConfEn PIN 93 selects Hard Reset Configuration Source as BCSR or EEPROM FLASH Auxiliary Pins
134. OLA PQ2FADS ZU User s Manual 95 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 5 P7 P8 P9 PCI Connectors Side Comments Side A Comments 52 AD 08 0 53 AD 07 3 3V 54 3 3V AD 06 55 AD 05 AD 04 56 AD 03 Ground 57 Ground AD 02 58 AD 01 AD 00 59 3 3V I O 3 3V I O 60 64 Not Connected REQ64 Not Connected 61 5V 5V 62 5V 5V 7 1 7 P27 ATX Power Supply Connector This is a standard ATX Form Factor Power Connector as described in Table 7 6 Table 7 6 P27 ATX Power Supply Connector Pin Signal Pin Signal 1 3 3VDC 11 3 3VDC Sense 2 3 3VDC 12 12VDC 3 Groung 13 Groung 4 5VDC 14 Power_On 5 Groung 15 Groung 6 5VDC 16 Groung 7 Groung 17 Groung 8 Power_OK 18 5VDC 9 5VStand_By 19 5VDC 10 12VDC 20 5VDC 7 1 8 19 20 Mach Lattice ISP Connector This is a 10 pin generic 0 100 pitch header connector providing In System Programming ISP 96 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information capability for Latice made programmable logic on board The pinout of P15 is shown in Table 7 7 Table 7 7 P15 Lattice ISP Connector Pin No Signal Nam
135. P3 and P4 100 10 Base T Ethernet port Connector P3 or P4 is a RJ 45 Type Connector for Twisted Pair Ethernet as described in Table 7 2 Table 7 2 P3 P4 100 10 Base T Ethernet Connector Pin No Signal Name Description 1 TPTX Twisted Pair Transmit Data positive output from the PQ2FADS ZU 2 TPTX Twisted Pair Transmit Data negative output from the PQ2FADS ZU 3 TPRX Twisted Pair Receive Data positive input to the PQ2FADS ZU 4 N C Not connected Bob Smith terminated on the PQ2FADS ZU 5 6 TPRX Twisted Pair Receive Data negative input to the PQ2FADS ZU 7 Not connected Bob Smith terminated on PQ2FADS ZU 8 7 1 3 P15 J TAG Connector P15 is a Motorola standard COP JTAG connector for the 60X processors family It is a 16 pin protected header connector as described in Table 7 3 Table 7 3 P15 COP JTAG Connector Pin No Signal Name Attribute Description TDO Transmit Data Output This the PQ2 s JTAG serial data output driven by Falling edge of TCK GND Digital GND Main GND plane TDI I Transmit Data In This is the JTAG serial data input of the ADS sampled on the rising edge of TCK TRST I Test port Reset L When this signal is active Low it resets the JTAG logic of the PQ2 This line is pull down on the ADS with a 1KQ resistor to provide constant reset of the JTAG logic MOTOROLA PQ2FADS ZU User s Manual 85 For M
136. R112 0 D11000RFCS ROEDER R113 R115 R118 R192 R238 STEIN R257 R258 R290 R294 R299 R304 R313 R321 R322 R323 R 339 R370 R371 R 380 R 382 388 R 393 61 28 R61 R63 R65 R66 R 86 R 87 220 R88 R101 R104 R105 R107 R 109 R 359 R 360 R 361 R 362 363 R 364 R 365 R 374 R 376 R398 R399 R408 R410 R411 R425 R426 62 19 R71 R72 R73 R75 R 76 77 4382 D1143R2FCS ROEDER R78 R80 R81 R82 R 83 R 84 STEIN R232 R242 R262 R278 R280 R281 R413 63 2 R114 R74 08005 WSL2512 0 0050hm DALE 1 64 1 R98 110 CR3211 J T AVX 65 21 R99 R 123 R 124 R 125 R 127 330 D25330RJ CS ROEDER R 132 R 140 R 147 R 155 R 156 STEIN 164 R 168 R 171 176 R 181 R 189 R 196 R 197 R 200 R 206 R415 66 2 R126 R136 1K D25001KFCS DRALORIK 67 10 R133 R159 R165 R166 R172 150 D25150RFCS ROEDER R186 R187 R412 R417 R418 STEIN 68 12 R134 R139 R190 R198 R 335 1K5 D2501K5FCS ROEDER 336 R 340 R 345 R 346 R 351 STEIN R366 R 367 69 2 R 138 R 137 24R3 D2524R3FCS ROEDER STEIN 70 1 R144 330 D25 330RJ CS ROEDER STEIN 71 1 R149 220 D25220RJ CS DRALORIK 72 4 R150 R151 R284 R357 51R1 D1151R1FCS ROEDER STEIN 73 3 R152 R153 R154 150 025 1508 CS ROEDER STEIN 74 2 R182 R188 6K8 1 025 06K8FCS ROEDER STEIN 75 2 R193 R222 2R7 D2502R7FCS ROEDER STEIN 208 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc S
137. RAR IORI RAK L2CACHE INH DATA D2 L2CACHE FLUSH DATA D3 L2CACHE LOCK DATA D4 L2CACHE CLEAR DATA BIT D5 SIGNAL LAMPO DATA D6 SIGNAL LAMP1 DATA D7 x BCSR 1 definitions EKEK EEK BCSR BOOT 0 bcsrConfEn 0 Hard Reset Conf Word from BCSR MEMORY BOOT 1 bcsrConfEn 1 Hard Reset Conf from EEPROM FLASH FLASH BOOT 0 boot device 0 EEPROM BOOT 1 boot device B 1 ATM_ENABLED 0 ATM_RESET ACTIVE 0 120 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information FETH1 ENABLED 0 FETH1 RESET ACTIVE 0 RS232 1 ENABLE 0 RS232 2 ENABLE 0 Power On Defaults Assignments 9 TERCERA IIR AIR RIK ATM ENABLE PON DEFAULT ENABLED RESET PON DEFAULT RESET ACTIVE FETH1 ENABLE PON DEFAULT FETH1 ENABLED
138. ROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information A8 PIN 68 for flash support A27 PIN 15 A28 PIN 12 A29 PIN 11 00 PIN 75istype 01 PIN 22istype D2 132istype D3 77istype 04 PIN 16 05 142istype 06 60istype 07 PIN 87istype D8 PIN 66istype D9 PIN 72istype com D10 PIN 70istype D11 PIN 39istype Board Control Pins Read Write SEE EEE ARR AAAI AAAI L2Inh_B PIN 130istype reg buffer flash enable L2Flush B PIN 42istype reg buffer 60x bus sdram enable L2Lock B PIN 112istype reg buffer bursting sram enable L2Clear B PIN 128istype reg buffer local bus sdram enable SignaLampO B PIN 44istype reg buffer status lamp 0 for misc s w visual SignaLampl B PIN 38istype reg buffer status lamp 1 for misc s w visual AtmEn B PIN 134istype reg buffer uni enable AtmDis B PIN 114istype atm uni disable MOTOROLA PQ2FADS ZU User s Manual 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Info
139. Register Ijoleleleleleteleteretetetetetelererererererererererererererererereteteletelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek Slot0IntANODE istype reg invert Slot0IntB NODE istype reg invert Slot0IntCNODE istype reg invert Slot0IntDNODE istype reg invert SlotlInNtANODE istype reg invert SlotlIntBNODE istype reg invert SlotlIntCNODE istype reg invert SlotlInNtDNODE istype reg invert Slot2IntANODE istype reg invert Slot2IntB NODE istype reg invert Slot2IntCNODE istype reg invert Slot2IntDNODE istype reg invert TICKERS EEE EEE EAA AICCCR PCI Interrupt Mask Register Slot0IntAMaskNODE istype reg buffer PCI Slot 0 Interrupt A Mask Slot0IntB MaskNODE istype reg buffer PCI Slot 0 Interrupt Mask Support Information PCI Slot Interrupt A PCI Slot 0 Interrupt B PCI Slot 0 Interrupt C PCI Slot 0 Interrupt D PCI Slot 1 Interrupt A PCI Slot 1 Interrupt B PCI Slot 1 Interrupt C PCI Slot 1 Interrupt D PCI Slot2 Interrupt A PCI Slot2 Interrupt B PCI Slot 2 Interrupt C PCI Slot 2 Interrupt D MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 111 Freescale Semiconductor Inc Supp
140. Reset B 0 5 PON DEFAULT Slot2lntDMask Active HardReset B 0 amp Slo2IntDMask PON DEFAULT Slot2IntDMask_Active then ISlot2IntDMask Active 158 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information else Slot2IntDMask_Active State Slot2IntDMask_Active if VGR_WRITE_IntMaskReg amp Slot2IntDMask DATA BIT pin Slot2lIntDMask Active HardReset B 0 Slot2IntDMask PON DEFAULT Slot2IntDMask_Active HardReset 0 amp Slot2IntDMask PON DEFAULT Slot2IntDMask_ Active then Slot2IntDMask Active else ISlot2IntDMask Active AKA AKA AR IIA AIA ARAKI TRIO KAKA RAR ARIA RAIA KARA II AAAI ARR IK IK External Read Registers Chip S elects equations Bcsr2Cs B oe H Bcsr4Cs B oe H IBcsr2Cs B VGR_READ BCSR 2 IBcsrdCs B VGR READ BCSR 4
141. S ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description address It may be read or written at any time BCSRO gets its defaults upon Power On reset fields are described in Table 4 9 Table 4 9 BCSRO Description BIT MNEMONIC Function E ATT 0 PBI Page Base Interleaving In 60X mode i e with L2 Cache this bit should 0 R W reflect system programmer responsibility the state of bit in PSDMR In Single PQ2 Mode i e without L2 Cache this bit has no effect 1 Reserved 5 0 R W 2 L2C_INH L2 Cache Inhibit When this bit is active low the L2 cache is inhibited 0 RW and unable to respond to cacheable cycles However bus activity is still monitored by the cache so that it may respond immediately after this signal is negated This signal is connected to the MPC2605 s L2 UPDATE INH This signal has no function in a PQ2FADS ZU that does not have an L2 Cache installed 3 L2C FLUSH L2 Cache Flush When this bit is active low for min 8 bus cycles the 1 RW MPC2605 initiates a process within which valid lines are marked invalid while dirty lines are written back to memory and marked invalid This signal is connected to the L2 FLUSH signal of the MPC2605 This signal has no function in a PQ2FADS ZU that does not have an L2 Cache installed 4 L2C LOCK L2 Cache Lock When this bit is active low the MP
142. U User s Manual 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information IFEthRstOut2 B FEthRst2_B fo HardReset_B a a a Hard reset configuration equations RstConf_B oe H RstConf B L Ijoleloleleleleretetetetetetetelererererererererererererererererererereletelerelelerelerelerelereteteteteteteteteteteteteteteteterererererererererererererek NMI generation equations NMIEn NMI_B 0 0 D RstDebl com amp AbrDebl com only abort button depressed local data buffers enable equations SyncHardReset_B clk SYSCLK SyncHardReset_B ar
143. U using a 1KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure in doing so might result in permanent damage to the 2 or to board logic 14 N C Not Connected 15 XBR3 Normally configured as XBR3 which has function with this CKSTOP_OUT connector May be configured as CKSTOP_OUT Check Stop Out L When asserted Low indicates that the PQ2 core has entered a Check Stop state 16 GND Digital GND Main GND plane 68 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization 5 Memory Map and Initialization 5 1 Memory Map All accesses to PO2FADS ZU s memory slaves are controlled by the PQ2 s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks for existence size delay and type of the FLASH memory SIMM mounted on board and decides on the assignments of 50 and 54 2 and FLASH and programs the memory controller accordingly The SDRAM E PROM and the FLASH memory respond to all types of memory access i e problem supervisory program data and DMA This memory map is a recommended memory map and since it is a soft map devices address may be moved about the map to the convenience of any user There are a
144. User s Manual PQ2FADS ZU UM Revision 0 0 April 8 2003 PQ2FADS ZU User s Manual Freescale Semiconductor Inc MOTOROLA intelligence everywhere 9 digital dna PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Motorola Inc 2003 Freescale Semiconductor Inc Important Notice to Users While every effort has been made to ensure the accuracy of all information in this document Motorola assumes no liability to any party for any loss or damage caused by errors or omissions or by statements of any kind in this document its updates supplements or special editions whether such errors are omissions or statements resulting from negligence accident or any other cause Motorola further assumes no liability arising out of the application or use of any information product or system described herein nor any liability for incidental or consequential damages arising from the use of this document Motorola disclaims all warranties regarding the information contained herein whether expressed implied or statutory including implied warranties of merchantability or fitness for a particular purpose Motorola makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights nor do the descriptions contained herein imply the granting or license to make use or sell equipment constr
145. XPTY ATMTXEN and ATMTSOC When the ATM port is disabled this line may be used for any available function of PC21 D12 PC20 T S PQ2 s Parallel I O Port C 20 Parallel I O line May be used for any of its available functions D13 FETHRXCK PC19 T S Fast Ethernet Receive Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is extracted from the received data and driven to the PQ2 to qualify incoming receive data When the Ethernet port is disabled this line is tristated and may be used for any available function of PC19 014 FETHTXCK PC18 T S Fast Ethernet Transmit Clock When the Ethernet port is enabled this clock 25 MHz for 100 Mbps 2 5 MHz for 10 Mbps is normally extracted from the received data and driven to the PQ2 to qualify out coming transmit data In Slave mode not used with this application this clock should be input to the LXT970 When the Ethernet port is disabled this line is tristated and may be used for any available function of PC18 015 17 T S PQ2 s Port 17 15 Parallel I O lines May be used to any of their available functions D16 PC16 D17 PC15 92 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 4 P4 CPM Expansion Connector Pin No Signal Nam
146. ablish its mode of operation The SDRAM is programmed according to the following procedure 1 Issue Precharge All command 2 Issue 8 CBR refresh commands 3 Issue MODE SET command An SDRAM is programmed by issuing a Mode Register Set command During that command data is passed to the Mode Register through the SDRAMs address lines This command is fully supported by the SDARM machine of the PQ2 Before that can take place the SDRAM machine of the 2 has to be initialized 46 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Functional Description Mode Register programming values are shown in Table 4 6 Table 4 7 100 MHz SDRAM Mode Register Programming SDRAM DRAMM Address 5 ode Value Meaning Reg Field Line A11 MSB Reserved 0 10 Reserved 0 9 0 1 O Burst Read amp Burst Write Copy Back data cache 1 Burst Read amp Single Write Write Through Data cache A8 Reserved 0 A7 Reserved 0 4 CAS Latency 011 Data Valid 3 Clocks cycles after CAS Asserted A3 Burst Type 0 Sequential Burst A2 A0 Burst Length 011 8 Burst Length a Actually SDRAMs 0 is connected to PQ2s LA29 and so on 4 8 2 SDRAM Refresh The SDRAM is refreshed using its auto refresh mode I e using SDRAM machine one s periodic timer
147. an auto refresh command is issued to the SDRAM every 8 2 psec so that all 2096 SDRAM rows are refreshed within specified 17 msec while leaving an interval of 47 msec of refresh redundancy within that window as a safety measure to cover for possible delays in bus availability for the refresh controller 4 8 3 Local Bus SDRAM Functionality The local bus can function in two mode 1 Local Bus SDRAM 2 PCI Both options are implemented on board and the selection is done with the pin jumper JP9 Bus Muxing devices are used to direct the local bus signals to the PCI or to the SDRAM 4 8 4 Local SDRAM Error Correction Support The PQ2FADS ZU has an optional support for Parity Error Correction for Local Bus SDRAM accesses To support that option the LCL_DP 0 3 lines are connected to a Local Bus SDRAM device which functions as ECC memory Since the PQ2 muxes LCL_DP 0 3 signals with other PCI signals bus mux is used to select between LCL_DP 0 3 signals and PCI function MOTOROLA PQ2FADS ZU User s Manual 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description PQ2 Local SDRAM LCL_DP 0 3 LCL_DP 0 3 LCL DPO PCI C BEO DP1 PCI C BE1 E NS LCL DP2 PCI C BE2 PCI Bus DP3 PCI 0 3 0 3 Figure 4 9 Local Bus SDRAM Data P
148. and the VPP 12V option from programming the FLASH 6 1 7 12V Rail The 12V bus from the ATX Power Supply supports the PCI slots MOTOROLA PQ2FADS ZU User s Manual 81 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 2 Connectors The PQ2FADS ZU has connectors attached to serve the following functions ATX Power Supply 100 10 Base T Ethernet ports ATM 155Mbps port RS232 port 1 RS232 port 2 CPM Expansion JTAG Logic Analyzer Connectors SN SO Programmable logic In System Programming ISP PCI Connectors System Expansion USB Connector 13 Parallel Port Connector 6 2 1 ATX Power Connector The ATX power connector is a 20 lead standard ATX power connector The female part is soldered to the PCB while the plug is connected to the power supply That way fast connection disconnection of power is facilitated 6 2 2 Fast Ethernet Port Connectors The Ethernet connector on the PQ2FADS ZU is a Twisted Pair 100 10 Base T connector Use is done with 90 RJ45 8 connector 6 2 3 ATM 155 Port Connection The ATM 155 I F to the media is optical rather than electrical Use is done with HP s HFBR 5805 optical I F which is placed on the edge of the board for convenient connection 6 2 4 RS232 PortS Connector The RS232 port connector is a stacked 9 pin 90 female D Type connector which sav
149. arity Support 49 Flash Memory SIMM The PQ2FADS ZU is provided with 8Mbyte of 95 nsec flash memory SIMM the 5 73228 by Smart Modular Technology which is composed of four LH28F016SCT L95 chips by Sharp arranged as 2M X 32 in a single bank Support is given also to 16MBytes and 32 MBytes simms The Flash SIMM resides an 80 pin SIMM socket is buffered from the 60X bus to reduce capacitive load over it To minimize use of PQ2s chip select lines only one chip select line CSO or CS4 if the E PROM is using CSO is used to select the Flash as a whole while distributing chip select lines among the module s internal banks is done by on board programmable logic according to the Presence Detect lines of the Flash SIMM inserted to the PO2FADS ZU The access time of the Flash memory provided with the PQ2FADS ZU is 95 nsec however devices with different delay are supported as well By reading the delay section of the Flash SIMM Presence Detect lines see Table 4 12 the debugger can establish via register ORO in case CS0 is used or if CS4 is used the correct number of wait states needed to access the Flash SIMM considering 100MHz system clock frequency The control over the Flash is done with the GPCM and a dedicated CSO or CS4 region which controls the whole bank During hard reset initialization the debugger or any application S W for that matter reads the Flash Presence Detect lines via BCSR and deter
150. as 12V programmable modules The selection between VPP s voltage levels is done via a dedicated jumper To avoid inadvertent programming or erasure of the Flash it is recommended to leave the jumper open so that no VPP is applied to the Flash SIMM 4 9 2 Flash and L2Cache If the L2 cache is installed the PQ2 needs to be programmed to 60x bus mode This requires the latches for the buffered address bus to the Flash As well as all other slow static devices to be MOTOROLA PQ2FADS ZU User s Manual 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description enabled The 3 lowest order address lines for the Flash are provided by the BADDR 27 29 lines of the PQ2 However BADRR29 function of the PQ2 is multiplexed with CI Cache Inhibit function over the same pin Therefore prior to enabling the L2Cache any code residing in the Flash should be moved into the PowerPC bus SDRAM prior to changing BADDR29 function to CI via SIUMCR 4 10 E2PROM Memory The PQ2FADS ZU is provided with 8 KBytes of E PROM memory in a PLCC package The E PROM resides on a socket in case it is desired to replace or re program a different configuration for the board The is used only for the purpose of supplying the Reset Configuration Word during power on reset and for storing the PCI configuration data It is used as a back up for the Flash memory in case the Flash is not installed or the
151. avoid reflection these lines are sertes terminated with 43 resistors A2 EXPA17 A3 EXPA18 A4 EXPA19 A5 EXPA20 A6 EXPA21 7 22 8 23 9 24 10 25 EXPA26 12 27 13 28 14 29 15 16 17 EXP12V These can be connected to positive 12V source from the PCI edge connector thru J3 This line is fused by 0 5A ressetable poly switch 19 N C Not Connected A20 EXP3 3V O 3 3V Power Out These lines are connected to the main 3 3V plane of the PQ2PCIAI ADS this to provide 3 3V power where necessary for 21 external tool connected A22 A23 A24 A25 N C Not Connected 98 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description A26 EXPVCC 5V Supply Connected to ADS s 5V VCC plane Provided as power supply for external tool A27 A28 A29 A30 A31 A32 Bl GND Digital Ground Connected to main GND plane the ADS B2 B3 B4 TSTATO I Tool Status 07 7 These lines may be driven b
152. ble T interrupt is masked 12 31 Reserved Un implemented R W 38 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 3 Clock Generator There are two main clock circuits on board 1 PQ2 System Clock 2 PCI Clock 4 3 1 PQ2 Clock The 2 requires a single clock source as the main clock source All PQ2 60x bus timings referenced to the main clock input CLKINI The main clock input is in 1 1 ratio to the bus clock with internal skew elimination PLL Use is done with 66MHz for Hip3 and Hip4 devices 3 3V clock oscilator 100MHz for Hip7 device which is connected to a low inter skew buffer U39 to split the load between all various clock consumers on both boards Special care is taken to isolate and terminate the clock route between the on board PLL and the 2 this to provide a clean clock input for proper operation The main clock scheme is shown in Figure 4 3 2 CLOCK GEN 0 60x SDRAM 66 MHZ gt ae BCSR Buffers gt __ L2CACHE I EXPANSION LB SDRAM Figure 4 3 Main Clock Generator Scheme 4 3 2 Clock The PCI bus clock is derived internally from the main clock input CLKINI The generated PCI clock is output from a PCI dedicated PLL named
153. ble 1 low power mode option for all communication transceivers BCSR controlled enabling use of communication ports off board via the expansion connectors Dedicated PQ2 communication ports expansion connectors for convenient tools connection carrying also necessary bus signals for transceivers M P I F connection Use is done with 2 X 128 pin DIN 41612 receptacle connectors External Tools identification amp status read capability via BCSR Separate Power On Reset Push Button Soft Hard Reset Push Button and ABORT Push Button ATX Power Supply 1 Hard reset is applied by depressing BOTH Soft Reset amp ABORT buttons PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information Multi Range PQ2 internal logic operation voltage selectable by jumper between three ranges 1 3V to 1 7V for MPC8280 Hip7 1 7V to 1 9V for PQ2 Hip4 or 2 3V to 2 7V for MPC8260 Hip3 Software Option Switch provides 8 S W options via BCSR MOTOROLA PQ2FADS ZU User s Manual 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc IPCI Slot 33 66Mhz 3 3V IPCI Slot 33 66Mhz 3 3V IPCI Slot 33 66Mhz 3 3V 3 3V SDRAM 8 MBytes 32 Bit BUS SWITCH PCI Bus JTAG PQ2 CLKINI Main Clock Logic Ana
154. c to support direct connection to standard Parallel Port EPP SPP modes in Desk Top PC for debug purposes using CodeWarrior tools Power On Reset Option via JTAG Selectable Local bus function Local Bus SDRAM connection or PCI bus in host mode 8MByte Synchronous Dram soldered on board residing on local bus with optional parity support controlled by SDRAM machine 2 Programmable Power On Reset and Hard Reset Configuration via E PROM or via Flash memory for the PQ2 core PCI Local Bus is PCI Standard 2 2 compliant 3 PCI slots are available to host up to 3 masters targets cards 3 3V only arbitration is supported by the on chip Arbiter PCI bus supports 25 66 MHz 3 3V devices determined by the user Simple generic Interrupt Controller to handle the PCI interrupts 4 in each PCI slot Module Enable Indications for all on board modules High density MICTOR Logic Analyzer connectors carrying all 60x local bus and CPM signals for fast logic analyzer connection 155 Mbps ATM UNI on with Optical I F connected to the PQ2 via UTOPIA Level 2 I F supporting 8 16 bit in single multi PHY using the PMC SIERA 5384 Two 100 10 Base T Ports on FCC2 and FCC3 with T P I F controlled using Davicom DM9161 USB Port USB 1 1 Standard Compliant using Philips PDIUSBP11 USB transceiver USB Port is with shutdown option and speed selectable BCSR controlled Dual RS232 port residing on SCC amp SCC2 Module disa
155. ct Go to www freescale com 1i MOTOROLA Freescale Semiconductor Inc Support Information 1444444 t peg i E F fj 2 I i b E 1 F a fu ais a 4 11 t T E r bill rr r Emi fees P i i 4444 Bs 3 r ie E Bh L E 1 154 1212131351 az dedimus F 1 bil 277 tin kih LI Eh bak i 1 83 LLLI 1 L mime niim Gees T i F MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 177 Freescale Semiconductor Inc Support Information 178 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information 7148 TIRE didi esi deti enin MEA y ka LT D i J xx ux m mi MER ie 0g m nan 0000 007 JI E i Ill n III lis HHBH
156. ctually two memory maps which depend on the device assigned to CSO regardless of the Hard Reset Configuration Word source The memory address for the device assigned to CSO is always the same as determined in the Hard Reset configuration word Since the FLASH and E PROM require different memory spaces different memory maps are devised for each case For details see Table 5 1 and Table 5 2 Table 5 1 PQ2FADS ZU Memory Map FLASH or BCSR as Boot Device Address Memory Port Memory Device Name Range Type Size Size 00000000 60x SDRAM 32MByte 64MByte 64 MByte 01FFFFFF 01000000 O3FFFFFF 04000000 Empty Space Optional 4MByte local bus SDRAM for legacy 5 MByte 044FFFFF support MOTOROLA PQ2FADS ZU User s Manual 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 1 PQ2FADS ZU Memory Map FLASH or BCSR as Boot Device Address Memor Port Memor y Device Name ney Range Type Size Size 04500000 BCSR 0 7 8 32 32 KByte 04507FFF 04500000 BCSRO 4 Byte 04507FE3 04500004 BCSRI 4 Byte 04507FE7 04500008 BCSR2 4 Byte 04507FEB 0450000C BCSR3 4 Byte 04507FEF 04500010 BCSR4 4 Byte 04507FF3 04500014 BCSR5 4 Byte 04507FF7 04500018 BCSR6 4 Byte 04507FFB 0450001 BCSR7 4 Byt
157. described in Table 7 2 P3 P4 100 10 Base T Ethernet Connector on page 85 2 4 6 Memory Installation The PQ2FADS ZU is supplied with one type of memory module Hash Memory SIMM 2 4 6 1 Flash Memory SIMM Installation To install a memory SIMM it should be taken out of its package put diagonally in its socket 054 and then raised to a vertical position until the metal lock clips are locked See Figure 2 17 1 IBM AT is a trademark of International Business Machines Inc MOTOROLA PQ2FADS ZU User s Manual 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation CAUTION The memory SIMMs have alignment nibble near their 1 pin It is important to align the memory correctly before it is twisted otherwise damage might be inflicted to both the memory SIMM and its socket 2 Flash SM Metal Lock Clip SIMM Socket Figure 2 17 Flash Memory SIMM Insertion 20 PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Operating Instructions 3 Operating Instructions 3 1 Introduction This chapter provides necessary information to use the PQ2FADS ZU in host controlled and stand alone configurations This includes controls and indicators memory map details and software initialization of the board 3 2 Controls and Indicators The
158. e 04507FFF 04508000 Empty Space 1 MByte 045FFFFF 04600000 UNI Proc PMC5384 I F 8 32 KByte 04607FFF Control 04608000 Empty Space 1 MByte 046FFFFF 047000002 Internal 32 128 KByte 0471FFFF MAP 04720000 Empty Space 64 KByte 0472FFFF 04730000 PCI Interrupt 32 32 KByte 04737FFF Controller 04738000 Empty Space 800 KByte 047FFFFF 04800000 PCI Memory Agents PIMMR via PCI Direct 8 MByte O4FFFFFF 05000000 Empty Space Tool Board is located at 60000000 and 70000000 2 GByte 7FFFFFFF 80000000 PCI Memory PCI Agents GPL WIndows 32 1 Gbyte BFFFFFFF 70 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 1 PQ2FADS ZU Memory Map FLASH or BCSR as Boot Device Address Memory Port Memory Device Name 5 Range Type Size Size C0000000 Empty Space 32 MByte C1FFFFFF 2000000 ATMEL AT28HC64B 8 32 KByte C2007FFF C2008000 Empty Space 200 CFFFFFFF MByte 0000000 Local Bus 8MByte 32 8 MByte DO7FFFFF SDRAM D0800000 Empty Space 1 GByte FDFFFFFF 000000 Flash SIMM 32M SIMM 32 32 MByte FEFFFFFF SM73288 FF000000 16M SIMM FF7FFFFF SM73248 FF800000 8M SIMM FFFFFFFF SM73228 a The device appears repeatedly in
159. e Attribute Description 1 ISPTCK I ISP Test port Clock This clock shifts in out data to from the programmable logic JTAG chain 2 N C Not Connected 3 ISPTMS I ISP Test Mode Select This signal qualified with ISPTCK changes the state of the prog logic JTAG machine 4 GND Digital GND Main GND plane 3 ISPTDI I ISP Transmit Data In This is the prog logic s JTAG serial data input sampled on the rising edge of TCK 6 5V power supply bus 7 ISPTDO ISP Transmit Data Output This the prog logic s JTAG serial data output driven by Falling edge of TCK 8 GND Digital GND Main GND plane 9 N C Not Connected 10 N C Not Connected 7 1 9 P27 System Expansion Connector P27 is a 128 pin 90 DIN 41612 connector which provides a minimal system I F required to interface various types of communication transceivers This connector contains 16 bit lower PPC bus address lines 16 bit higher PPC bus Data lines plus useful GPCM and UPM control lines The pinout of P17 is shown in Table 7 8 MOTOROLA PQ2FADS ZU User s Manual 97 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description Al 16 O Expansion Address 16 31 This is a Latched Buffered version of the PQ2 s PPC Address lines 16 31 provided for external tool connection To
160. e Attribute Description D18 RS_CD1 PC14 T S RS232 Port 1 Carrier Detect L Connected via RS232 transceiver to RS232 1 input allowing detection of a connected terminal to this port This line is simply a PI O input line to the PQ2 When RS232 Port 1 is disabled this line is tristated and may be used for any available function of PC14 D19 PC13 T O T S PQ2 s Port 13 Parallel I O line May be used to any of its available functions D20 RS CD245 12 T S 5232 Port 2 Carrier Detect L Connected RS232 transceiver to RS232 DTR2 input allowing detection of a connected terminal to this port This line is simply a PI O input line to the PQ2 When RS232 Port 2 is disabled this line is tristated and may be used for any available function of PC12 D21 T O T S PQ2 s Port C 11 Parallel I O line May be used to any of its available functions D22 FETHMDC PC10 T S Fast Ethernet Port Management Data Clock This slow clock S W generated qualifies the management data I O to read write the LXT970 s internal registers When the Ethernet port is disabled this line may be used for any available function of PC10 D23 FETHMDIO PC9 T S Fast Ethernet Port Management Data I O This signal serves as bidirectional serial data line qualified by FETHMDC to allow read write the LXT970 s internal registers When the Ethernet port is disabled this line may be used for any available
161. e LXT970 responds by sending invalid code symbols on the line When the Ethernet port is disabled this line may be used for any available function of PB31 C2 FETHRXDV PB30 T S Fast Ethernet Receive Data Valid H When this signal is asserted High while the Fast Ethernet port is enabled and FETHRXCK goes high it indicates that data is valid on the MII Receive Data lines FETHRXD 3 0 When the Fast Ethernet port is disabled this line is tristated and may be used for any available function go PB30 C3 FETHTXEN PB29 T S Fast Ethernet Transmit Enable H The PQ2 will assert High this line to indicate data valid on the FETHTXD 3 0 lines When the Fast Ethernet port is disabled this line may be used for any available function of PB29 C4 FETHRXER PB28 T S Fast Ethernet Receive Error When this signal is asserted High by the LXT970 while the Ethernet port is enabled and FETHRXCK goes high it indicates that the port is receiving invalid data symbols from the network When the Ethernet port is disabled this line is tristated and may be used for any available function of PB28 C5 FETHCOL PB27 T S Fast Ethernet Port Collision Detected H When this signal is asserted High by the LXT970 while the ethernet port is enabled it indicates a Collision state over the line When the LXT970 is in Full Duplex mode this line is inactive When the Ethernet port is disabled this line is tristated
162. e is connected to the transmit parity of the PM5350 ATM UNI When this port is disabled this signal may be used for any available function of PD16 A17 I2CSDA PD15 T S This signal is connected to the serial data line This line may be used off board as an data line for external device A18 I2CSCL PD14 T S This signal is connected to the serial clock line This line may be used off board as clock line for external device MOTOROLA PQ2FADS ZU User s Manual 87 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 4 P4 CPM Expansion Connector Pin No Signal Name Attribute Description 19 PD13 T S PQ2 s PD 13 4 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions A20 PD12 A21 PD11 A22 PD10 A23 PD9 A24 PD8 A25 PD7 26 PD6 A27 PDS A28 PD4 A29 ATMRCLKDIS I ATM Receive Clock Out Disable When active H the ATMRCLK output on pin C29 of this connector is Tri stated When either not connected or driven low ATMRCLK on pin C29 is enabled This provides compatibility with ENG revision communication tools A30 EXPVCC 5V Supply Connected to ADS s 5V VCC plane Provided as power supply for external tool A31 A32 Bl ATMTXEN PA31 T S
163. ed this signal is tristated and may be used to any available alternate function for PD31 A2 RS TXDI PD30 I O T S When RS232 port 1 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to any available alternate function for PD30 A3 PD29 5 PQ2 s Port D 29 line Parallel I O or CPM dedicated line May be used for any of it s available functions A4 RS_RXD2 PD28 T S When RS232 port 2 is enabled this signal is the receive data line for that port When this port is disabled this signal is tristated and may be used to any available alternate function for PD28 5 RS_TXD2 PD27 T O T S When RS232 port 2 is enabled this signal is the transmit data line for that port When this port is disabled this signal may be used to any available alternate function for PD27 A6 PD26 T S PQ2 s PD 26 18 Port D lines Parallel I O or CPM dedicated lines May be used for any of their available functions A7 PD25 A8 PD24 A9 PD23 A10 PD22 All PD21 12 PD20 13 PD19 Al4 PD18 15 PD17 5 ATM Receive Parity Line When the ATM port is enabled this line is connected to the receive parity of the PM5350 ATM UNI When this port is disabled this signal is tristated and may be used for any available function of PD17 16 PD16 T S Transmit Parity Line When the ATM port is enabled this lin
164. eleleteretetetetetetetelerererererererererererererererererererelerelerelelerelerelereleretetetetetetetetetetetetetetetetetererererererererererererek Power Buffer NODE istype reg buffer Ijoelolelelelereteretetetetetelelererererererererererererererereretereletelerelelerelerelerelereteteteteteteteteteteteteteteretetererererererererererererek Creating internal clock generator NODE istype com keep inv2 NODE istype com keep inv3 NODE istype com keep inv4 NODE istype com keep inv5 NODE istype com keep counter0 counterl counter2 counter3 counter4 counter5 counter6 MOTOROLA PQ2FADS ZU User s Manual 169 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information counter7 countera0 counteral countera2 countera3 countera4 countera5 countera6 7 counterbO counterb1 counterb2 counterb3 counterb4 counterb5 counterb6 counterb7 NODE istype reg buffer EKEK EKK j HHH x HHH H H HHH TH HHEH T To TEE H f
165. es on board space made of two connectors for two ports 6 2 5 CPM Expansion Connector The CPM expansion connectors carries all CPM pins i e Port A to Port D signals Use done with DIN 41612 128 pin PCB connector residing the board allowing convenient vertical connection to off board tools Power supply pins are also provided through this connector 6 2 6 COP TAG Port Connector The debug port connector is a Motorola standard COP JTAG connector for the 60X processors N 82 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties family It is a generic 16 pin 2 X 8 Male SMD 90 protected header connector 6 2 7 Logic Analyzer Connectors To support fast connection to HPs 16500 Logic Analyzers series for debugging purposes a set of dedicated connectors is provided Use is done with 38 pin SMT high density matched impedance MICTOR connectors made by AMP These connectors carry the unbuffered 60X signals and should be placed as near to the PQ2 as possible to provide short PCB routes yielding better reflections and crosstalk immunity They do not carry the PCI bus signals due to the restrictions enforced by the PCI Standard There are also connectors for the CPM signals 6 2 8 Mach s In System Programming ISP Connector This is a 10 pin generic 0 100 pitch header connector providing In System Programm
166. escale Semiconductor Inc Support Information else when VGR_READ_IntMaskReg then DataP CI IntMaskR eg fb Reset Logic equations Reset oe ResetEn Reset 0 open drain RstDebl Rstl amp RstDebl com amp Rst0 Reset push button debouncer AbrDeb1 1 amp AbrDebl com amp 0 Abort push button debouncer HardResetEn RstDebl com amp 1 both buttons are depressed SoftResetEn RstDebl com amp l AbrDeb1 com only reset button depressed TransRst oe 7 transceivers reset always enabled IAtmRstOut B AtmRst HardReset IFEthRstOutl1 B FEthRstl_B fo HardReset MOTOROLA PQ2FADS Z
167. ess on board and off board memories saving boards area reducing cost power consumption and increasing flexibility To enhance off board application development memory modules including the BCSRx may be disabled via BCSR in favor of an external memory connected via the expansion connectors That way a CS line may be used off board via the expansion connectors while its associated local memory is disabled When a CS region assigned to a buffered memory is disabled via BCSR the local data 1 Required for Flash E PROM Interrupt Controller and BCSR 2 An address which is covered in a Chip Select region that controls a buffered device 3 allow a configuration word stored in the Flash E7PROM memory to become active 4 After the BCSR is removed from the local memory map there is no way to access it but to re apply power to the PQ2FADS ZU MOTOROLA PQ2FADS ZU User s Manual 41 For More Information On This Product Go to www freescale com Functional Description Freescale Semiconductor Inc transceivers are disabled during access to that region avoiding possible contention over data lines The 2 chip select assignments to the various memories registers on the PQ2FADS ZU shown in Table 4 5 Table 4 5 PQ2FADS ZU Chip Select Assignments Select Assignment Bus Machine CSO Flash SIMM E PROM 60X Buffered GPCM 81 BCSR 60X Buffered GPCM CS2 SDRAM
168. evision Encoding 63 4 17 External Tool Revision Encoding 63 4 18 L3 Cache Size Bucodilg se ases 63 4 19 gt Description uuu tee see x exe ha Gees eS 64 4 21 PCI Board Present Signal Definitions 65 4 20 BCSR4 Description 2254 65 4 22 BCSR5 Description u Seve VERRE OR MESE ER 66 4 23 COP JTAG Port Signals 67 5 1 PQ2FADS ZU Memory FLASH BCSR as Boot Device 69 5 2 PQ2FADS ZU Memory E2PROM as Boot Device 71 5 3 BCSR FLASH Power On Reset Configuration 74 5 4 E2PROM Power On Reset Configuration 74 5 5 SIU REGISTERS PROGRAMMING 75 5 6 Memory Controller Initializations For 100Mhz FLASH as Boot Device 76 5 7 Memory Controller Initializations For 100Mhz 2 as Boot Device 77 5 8 Memory Controller Initializations For 100 827 78 6 1 Expansion Connectors Maximum Current Consumption 80 6 2 Maximum Power Consumption Per Add In Card 80 7 1 RIS 06 ed tbe Dec ole ete Pe An ep ra Ae 84 7 2 P3 P4 10
169. extra slots that can host PCI targets only Therefore to avoid dedicated slots for PCI targets only three slots are implemented 1 As well as all other slow static devices MOTOROLA PQ2FADS ZU User s Manual 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description The PCI Bridge is implemented on the PQ2 Local Bus Due to PCI Standard restrictions no other application can reside on the local bus The PCI bus can operate at frequencies of 25MHz up to 66MHz 3 3V only The 3 3V restriction is due to the PQ2 which is not 5V compliant The PCI bus layout is shown in Figure 4 12 Special care was taken when the layout of the PQ2FADS ZU was done so that the PCI standard recommendations are followed strictly Main Clock 66MHz JTAG PCI Clock 2 x PQ2 JS 8 Distribution Ly CLKIN1 CLKIN2 4 PCI Clock 2 2 PCI Clock e e amp DLLOUT PCI Bus 5 PCI arbiter lt lt a ae 00000004 lt lt lt Interrupt Controller Figure 4 12 Bus Scheme The clock source for PQ2 is Main Clock 66MHz or 1OOMHz clock oscillator The PCI Clock is derived internally from the Main Clock and output at DLLOUT That clock is then distributed to each PCI device
170. face The selection is done by setting JP2 When a jumper is placed between positions 1 2 of JP2 the MII interface is enabled When a jumper is placed between positions 2 3 of JP2 the RMII interface is enabled See Figure 2 10 JP2 JP2 1 2 3 1 2 3 Mode RMII Mode Factory Setup Figure 2 10 FCC2 Ethernet Mode Selection NOTE For the mode change to take place the setting of JP2 should be done while the board is powered off 2 3 14 FCC3 Ethernet Port mode MII RMII The Ethernet PHY on FCC3 is set by default to 100Base Tx Full Duplex and can be configured to operate in MII or RMII interface The selection is done by setting JP3 When a jumper is placed between positions 1 2 of JP3 the MII interface is enabled When a jumper is placed between positions 2 3 of the interface is enabled See Figure 2 11 MOTOROLA PQ2FADS ZU User s Manual 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation JP3 JP3 1 2 3 1 2 3 MII Mode RMII Mode Factory Setup Figure 2 11 FCC3 Ethernet Mode Selection NOTE For the mode change to take place the setting of should be done while the board is powered off 2 3 15 USB Speed selection The USB port supports two speeds 12Mbits s and 1 5Mbits s The selection is software controlled in the BCSR At power up the default selection is 12Mbits s 2 3 16 USB
171. function of PC9 D24 PC8 T O T S PQ2 s Port C 8 0 Parallel I O lines May be used to any of their available functions D25 PC7 D26 PC6 D27 PCS D28 PC4 D29 PC3 D30 PC2 D31 D32 PCO The functions in parenthesis are PQ2 s parallel I Os Normally connected to ATMTFCLK on the ADS MS bit For that matter both 100 Base T and 10 Base T 7 1 5 P11 P12 P13 P14 P16 P17 P18 P23 P28 P29 P30 Logic Analyzer MICTOR Connectors These are 38 pin SMT high density matched impedance connector made by AMP They contain MOTOROLA PQ2FADS ZU User s Manual 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information the PQ2 60X bus 60X system and memory controller signals unbuffered The pinout of these connectors is shown in the schematics For signal description of these connectors see the PQ2 User s Manual 7 1 6 P10 P8 P9 PCI Connectors These 2 X 62 3 3V keyed 32 bit PCI connectors The pinout of each connector is available in Table 7 5 For signal descriptions for these connectors see the PCI v2 2 Standard Table 7 5 P7 P8 P9 PCI Connectors Side Comments Side A Comments 1 12V Not Connected TRST 2 TCK 12V 3 Ground TMS 4 TDO TDI 5 5V 5V 6 5V INTA 7 INTB Not Connected INTC
172. hronous DRAM On Local Bus 8 MBytes 32 bit wide with optional parity Operating temperature 0 C 70 C room temperature Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Length 12 305 mm Width 9 229 mm Thickness 0 063 1 6 mm 1 5 PQ2FADS ZU Features Supports MPC8260 Hip3 PQ2 Hip4 MPC8280 Hip7 processors 64 bit PowerQUICC II Communication Processor running up to 100 external bus frequency e 32 MByte Synchronous Dram soldered on board residing on 60X bus PBI mode with optional parity support controlled by SDRAM machine 1 Optional address Latch Multiplexer is available if L2 cache module is assembled MOTOROLA PQ2FADS ZU User s Manual 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information Optional 1 2 MByte L2 Cache on board using 2 MPC2605 Look Aside cache modules 8 MByte 80 pin Flash SIMM buffered from 60X bus Support for upto 32 MByte controlled by GPCM 5V 12V Programmable with Automatic Flash SIMM identification via BCSR Support for both On and OFF SIMM Flash reset 5V 12V VPP in circuit programming voltage for Flash SIMM jumper selectable 8 KBytes E PROM buffered from the 60x bus controlled by the GPCM Board Control amp Status Register BCSR Controlling Boards Operation On board COP JTAG connector On board logi
173. ia dip switch SW5 1 PQ2 s MODCKH 0 3 via SW6 1 4 PQ2 s PCI MODCK via SW6 5 PQ2 s PCI ARBITER via SW5 2 PQ2 s PCI DLL via SW5 3 Local Bus functionality SDRAM PCI via jumper JP9 PQ2 s 60x Bus parity support On Off via jumper JP10 Clock In source External or On Board clock oscillator JP11 FCC2 and FCC3 MII RMII modes via jumpers JP2 and JP3 respectively USB speed 12Mbits s or 1 5Mbits s and mode Host or Slave software controlled in BCSR PQ2 s COP JTAG connection COP JTAG connector P15 or direct connection to PC parallel port P31 selected automatically by connecting parallel cable Power Supply On Off Switch via SW7 i Das n oo EH 0 CHA pr HB CH O C 1112 Figure 2 1 PQ2FADS ZU Side Part Location Diagram 2 3 1 Setting VDDL Level Range P24 To support all revisions of the PQ2 provisions are taken to provide necessary voltage levels on PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation VDDL to match the process by which the PQ2 is manufactured Via P24 four voltage level ranges are provided P24 setting options are shown in Figure 2 2 1 When jumper is placed between positions 1
174. ident debugger if any is made available to the board This interrupt is enabled by setting the MSR EE bit To support external off board generation of an NMI the IRQO line is driven by an open drain gate This allows for an external h w to also drive this line If an external h w indeed does so it is compulsory that IRQO is driven by an open drain or open collector gate 4 2 2 ATM UNI Interrupt To support ATM UNI User Network I F event report by means of interrupt the interrupt output of the UNI INTB is connected to IRQ7 line of the PQ2 This IRQ7 input is shared with the Fast Ethernet PHY Interrupt Since INTB of the UNI is an open drain output it is possible to connect additional on and off board interrupt requesters on the same IRQ7 provided that they drive IRQ7 with open drain gate as well When an interrupt request appears in IRQ7 it is necessary to MOTOROLA PQ2FADS ZU User s Manual 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description check the source of the interrupt whether it s the ATM UNI or the Fast Ethernet PHY 4 2 3 Fast Ethernet PHY Interrupt To support the two fast Ethernet Transceivers event reports by means of interrupt the interrupt outputs of the DM9161 are connected to IRQ7 line of the PQ2 This IRQ7 input is shared with the ATM UNI Interrupt 4 2 4 Interrupt Each PCI slot can generate up to four
175. in the PQ2 is enabled When set high the PCI Arbiter is disabled an external arbiter can be used When switch SWS 2 is at the OFF position its corresponding PCI ARBITER line is pulled high 1 disabled while when at the ON position pulled down 0 enabled see Figure 2 6 2 3 9 Setting PCI DLL for PCI Mode Enabled The settings of this line determines the operation of the DLL for PCI Mode enabled When PCI Mode is enabled the DLL must be enabled When PCI DLL is set low the DLL is disabled When set high the DLL is enabled When switch SW5 3 is at the OFF position its corresponding PCI DLL line is pulled high 1 enabled while when at the ON position pulled down 0 disabled see Figure 2 6 2 3 10 Setting Local Bus functionality SDRAM or PCI There are two modes to set the Local bus Local Bus SDRAM or PCI The mode is determined by setting JP9 When a jumper is placed between positions 1 2 JP9 the PCI mode is enabled When a jumper is placed between positions 2 3 of 9 the PCI mode is disabled and the Local bus is connected to SDRAM see Figure 2 7 MOTOROLA PQ2FADS ZU User s Manual 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation JP9 JP9 1 2 3 1 2 3 PCI Enabled Local Bus SDRAM Enabled Factory Setup Figure 2 7 JP9 Local Bus Mode 2 3 11 60x Bus Parity Suppor
176. ing capability for Vantis made programmable logic on board 6 2 9 PCI Connectors A set of three standard PCI 3 3V keyed 124 pin 32 bit connectors is provided for connecting up to three PCI Add In cards 6 2 10 System Expansion Connector The System Expansion Connector is 128 pin DIN 41612 connector which provides a minimal system F required to interface to other tool boards which may use the CPM Expansion Connector This connector contains 16 bit lower PPC bus address lines 16 bit higher PPC bus Data lines plus useful GPCM and UPM control lines 6 2 11 USB Connector The USB connector is standard type A type A USB connector 6 2 12 Parallel Port Connector The parallel connector is a standard 25 pin D Type male connector 6 3 PCB Layout The PQ2FADS ZU layout was done in a manner suitable for high frequency operation and it follows closely the PCI Standard layout recommendations Following is a list of measures which are taken to meet this design goal Traces are as short as possible Clock signals and sensitive strobe signals are shielded and routed as a chain Multilayer PCB with ground and supply layers PCI signals lengths and impedance according to PCI Standard Rev 2 2 MOTOROLA PQ2FADS ZU User s Manual 83 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc 7 Support Information In this chapter all information needed fo
177. interrupts to a total of twelve 3 slot x 4 interupts each Each PCI expansion board can generate an interrupt at any given time Since there is only one interrupt input available the 2 an Interrupt Controller is used The Interrupt Controller receives all the possible interrupts from the PCI slots and generate one interrupt IRQ6 to the 2 A simple generic Interrupt Controller is implemented using CPLD device The Interrupt Controller is implemented as an Interrupt Register and an Interrupt Mask Register The Interrupt Controller has its own dedicated chip select line CS8 A simple priority scheme is devised to prioritize the interrupts from different slots The PCI IRQ routing are according to Figure 4 2 2 ADDRESS CONTROL PCI Interrupt Controller Figure 4 2 PCI Interrupt Routing Scheme An interrupt request in any of the INTx lines will set three interrupt bits in the PCI Interrupt Register if not masked in the Interrupt Mask Register since there are three possible interrupt sources for every INTx line It is up to the user to implement a polling process to verify the real interrupt source by polling the Interrupt Pending bit in the PCI device and clear the other two The PCI Interrupt Register can be read at any time and accessed at offset 0 0 from CS8 base address The description of the PCI Interrupt Register is in Table 4 3 36 PQ2FADS ZU User s Manual MOTOROLA For More Info
178. ion the associated MODCK is pulled down 0 SW6 is shown in Figure 2 4 while the various combinations for SW6 6 8 and their associated MODCK 1 3 values are shown in Table 2 1 1 May be either boot FLASH or EEPROM or BCSR on the ADS 10 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation MODCKHO MODCKHO MODCKH2 MODCKH2 MODCKH3 MODCKH3 PCI MODCK PCI MODCK MODCKI MODCK1 MODCK2 MODCK2 MODCK3 MODCK3 SW6 Factory Set Figure 2 4 SW6 Description Table 2 1 MODCK 1 3 Encoding Lo mE 2 3 4 Setting Hard Reset Configuration Source J P7 The Boot sequence which starts when HRESET is asserted may be from two sources 1 BCSR default Hard Reset Configuration Word CSO is assumed to be assigned to the FLASH 2 Memories FLASH EEPROM user controlled Hard Reset Configuration Word MOTOROLA PQ2FADS ZU User s Manual 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation When a jumper is placed between positions 1 2 of JP7 the Hard Reset Configuration source is a memory FLASH EEPROM as configured by switch SW5 1 When a jumper is set between positions 2 3 of JP7
179. iption push button is depressed the SRESET line is asserted to the PQ2 generating a Soft Reset sequence Since the SRESET line may be driven internally by the PQ2 it must be driven by an open drain gate to avoid contention over that line If off board H W connected to the PQ2FADS ZU is to drive SRESET line then it should do so with an open drain gate this to avoid contention over this line 4 1 3 3 Internal Sources Soft Reset The only internal Soft reset source is the COP JTAG soft reset which may be generated using Public JTAG instructions to shift active value 0 to the SRESET pin the boundary scan chain This is not useful for run time 4 1 4 Bus Reset The PCI Module in the PQ2 can generate a reset signal dedicated for PCI devices which reside on the PCI bus This is a reset to the PCI bus which is initiated by the PCI bus Host the PQ2 on this board This reset can also be initiated by a Soft PCI Reset by setting a dedicated bit in a PCI control register consult the PQ2 User Manual for details 4 2 Local Interrupter There are external interrupts which are applied to the 2 via its interrupt controller 1 ABORT NMI 2 ATM UNI interrupt 3 Fast Ethernet PHY Interrupt 4 PCI interrupt 4 2 1 ABORT Interrupt The ABORT is generated by a push button When this button is depressed the IRQO input to the PQ2 is asserted The purpose of this type of interrupt is to support the use of res
180. ird party Host Computer Media I F 1 at Cable MEDILL Media2COP P15 ATX Power Supply Figure 2 12 Host Controlled Operation Scheme Command Converter 2 The host is connected to the board directly from the host s parallel port Host Computer Standard Media I F Parallel Cable ATX Power Supply P31 Figure 2 13 Host Controlled Operation Scheme Parallel Port 2 4 2 Stand Alone Operation In this mode the board is not controlled by the host via the COP port It may connect to host via one of its other ports e g RS232 port Fast Ethernet port ATM155 port etc Operating in this mode requires an application program to be programmed into the board s Flash memory MOTOROLA PQ2FADS ZU User s Manual 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation COMM ia 2 K Computer 5 SS 222 5 ZZ 7 Z 4 Zh 2 a Ethernet 27 gt K Mery 2 2 E ATM 155 optics U1 iic PIAJP B ATX Power Supply Figure 2 14 Stand Alone Configuration 2 4 3 COP Connector P15 The PQ2FADS ZU COP interface connector P15 is a 16 pin male Header connector The connection between the PQ2FADS ZU and the COP controller is by a 16 line flat cable supplied with the COP
181. ite extended hold time after read BR8 PCI Interrupt Controller PPC 04731801 Base at 04730000 32 bit port size no parity GPCM on PPC bus OR8 FFFF8010 32 KByte block size all types access 1 w s MOTOROLA PQ2FADS ZU User s Manual 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 8 Memory Controller Initializations For 100Mhz Reg Device Type Bus Description hex PSDMR MT48LC4M32B2 PPC C24B36A3 Page Based Interleaving Refresh enabled normal 32 MByte operation mode address muxing mode 2 14 16 on Single BNKSEL 8 10 8 clocks refresh recovery 3 PQ2 clocks precharge to activate delay 3 clocks activate to Bus read write delay 4 beat burst length 2 clock last data Mode out to precharge 2 clock write recovery time no extra cycle on address phase normal timing for control lines 3 clocks CAS latency LSDMR MT48LC2M32B2 Local C28737A3 Page Based Interleaving Refresh enabled normal 8 MByte Bus operation mode address muxing mode 2 16 18 on BNKSEL A9 on LSDA10 8 clocks refresh recovery 3 clocks precharge to activate delay 3 clocks activate to read write delay 8 beat burst length 2 clock last data out to precharge 2 clock write recovery time no extra cycle on address phase normal timing for control lines 3 clocks CAS latency PSRT PPC Bus Sdra
182. l master is not supported 30 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 1 BCSR FLASH Hard Reset Configuration Word Field L2CPC Data Bus Bits 8 9 Prog Value Bin Implication CI BADDR 29 IRQ2 selected BADDR 29 WT BADDR 30 IRQ3 selected as BADDR 30 L2 selected as unassigned CPU_BG BADDR 31 IRQ5 as BADDR 31 DPPC 10 11 Data Parity Pin configuration as DPO as EXT_BR2 DP1 as EXT_BG2 DP2 as EXT_DBG2 DP3 as EXT_BR3 DP4 as EXT_BG3 5 as EXT_DBG3 DP6 as IRQ6 DP7 as IRQ7 Reserved 12 Reserved ISB 13 15 010 IMMR initial value 0 0 000000 i e the internal space resides initially at this address Offset In Flash Hex 8 Value Hex B2 BMS 16 Boot memory Flash at 0000 BBD 17 ABB IRQ2 pin is ABB DBB IRQ3 pin is DBB MMR 18 19 11700 41 Mask Masters Requests Boot Master is PCI when is enabled in the FLASH 00 No masking Local Bus SDRAM mode in the BCSR LBPC 20 21 01700 41 Local Bus pins function PCI bus FLASH 00 Local Bus pins function as Local Bus BCSR APPC 22 23 MODCK1 AP 1 TC 0 functions as BKSELO MODCK2 AP 2 TC 1 functions as BKSEL1 MODCKS AP 3 TC 2 functi
183. le memory ZIF Zero Input Force BGA Ball Grid Array ADI Application Development Interface COP Common On chip Processor SAR Segmentation And Reassembly UTOPIA Universal Test amp OPerations Interface for ATM 1 3 Related Documentation MPC8260 PQ2 MPC8280 User s Manual VADS Users Manual 2605 Data Sheet PMC SIERRA 5384 Long Form Data Sheet 2 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Information DM9161 DAVICOM Data Sheet 14 Specifications The PQ2FADS ZU specifications are given in Table 1 1 Table 1 1 PQ2FADS ZU specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached 5Vdc TBD A Typ TBD A Max 3 3 TBD A TBD A Max 12Vdc TBD 12Vdc TBD Max MPC8260 running 66 MHz Bus Clock Frequency MPC8264 5 6 running up to 83 MHz Bus Clock Frequency MPC8280 5 running up to 100 MHz Bus Clock Frequency Microprocessor Addressing Total address range on PPC Bus Total address range on Local Bus 4 Giga Bytes 32 address lines 256 KBytes External 18 address lines 4 Giga Bytes Internal 32 address lines internal decoding Flash Memory SIMM PPC Bus 8 MByte 32 bits wide expandable to 32 MBytes Synchronous Dynamic RAM DIMM PPC Bus 32 MByte 64 bits wide with optional parity Sync
184. led via MDIO 0 10 bit 4 FETH2_RST Fast Ethernet port 2 Reset When active low the 9161 is reset This 1 R W line is also driven by HRESET signal of the PQ2 Since MDDIS pin of the DM9161 is driven low with this application the negation of this signal causes all the H W configuration bits to be sampled for initial values and device control is moved to the MDIO channel which is the control path of the MII port 5 ATM16 ATM 16 bit UTOPIA When asserted low the UTOPIA is set for 16 bit 1 R W When negated high the UTOPIA is set for 8 bit 6 ATM SINGLE PH ATM SINGLE PHY When asserted low the UTOPIA is set to Multi PHY 1 R W Y When negated high the UTOPIA is set for Single PHY 7 PCI MODE PCI MODE When asserted low the Local Bus function is set to PCI R When negated high the Local Bus is set for Local Bus SDRAM 8 31 Reserved un implemented a Required for voltage levels adaptation 4 14 5 BCSR4 Board Control Status Register 4 BCSRA is a status register which is accessed at offset 0x10 from the BCSR base address Its a 1 Provided that BCSR is not disabled 64 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description read only register which may be read at any time BCSR4s various fields are described in Table 4 20 Table 4 20 BCSR4 Description BIT MNEMONIC Function EE ATT 0 1 PCIO PRSNT 0 1 PCI Slot
185. lot 1 Interrupt C Masked SlotlIntDMask Active 21 PCI Slot 1 Interrupt D Masked MOTOROLA PQ2FADS ZU User s Manual 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Slot2IntAMask_Active 21 Slot 2 Interrupt A Masked Slot2IntBMask_Active 1 PCI Slot 2 Interrupt Masked Slot2IntCMask Active 21 PCI Slot 2 Interrupt C Masked Slot2IntDMask Active 21 PCI Slot 2 Interrupt D Masked Power On Defaults Assignments Slot0IntAMask_PON DEFAULT Slot0IntAMask_Active Slot lntBMask PON DEFAULT Slot0IntBMask_ Active Slot lntCMask PON DEFAULT Slot0IntCMask_ Active Slot lntDMask PON DEFAULT Slot0IntDMask_ Active SlotlintAMask_PON DEFAULT SlotlintAMask Active SlotlintBMask PON DEFAULT SlotlIntBMask_ Active SlotlintCMask PON DEFAULT SlotlIntCMask_ Active SlotlintDMask PON DEFAULT SlotlintDMask Active Slot2IntAMask PON DEFAULT Slot2IntAMask Active Slot2IntBMask PON DEFAULT Slot2IntBMask_ Active Slot2IntCMask PON DEFAULT Slot2IntCMask_ Active Slot2IntDMask PON DEFAULT Slot2IntDMask_ Active Data Bits Assignments 9 URI III
186. ltage measuring device VDDL level is factory set at the mid range for the appropriate level range but may be changed via RP2 Rotating RP2 CCW will increase VDDL voltage up to range high while rotating it CW will decrease VDDL down to range low LD26 provides visual indication for VDDL level it MOTOROLA PQ2FADS ZU User s Manual 9 For More Information This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation illuminates brighter with rise of VDDL VDDL change Vs RP2 s rotation direction is shown in Figure 2 3 RP2 HIGH LOW Figure 2 3 VDDL Trimmer RP2 WARNING While in higher ranges of VDDL and higher rang es of internal operation frequencies the PQ2 might require some sort of COOLING measures to be taken Failure in doing so might result in PERMANENT DAMAGE inflicted to the PQ2 2 3 3 Setting MODCK 1 3 for PLLs Multiplication Factor SW6 6 8 After 1K cycles the negation of the Power On Reset signal the PQ2 samples the 7 MODCK lines the lower 3 on MODCK 1 3 and the upper four MODCKH 0 3 field read from the Hard Reset Configuration Word when the PCI is disabled to establish the multiplication factors of CPM s and Core s PLLs The levels on MODCK 1 3 lines set using SW6 switches 6 8 When an individual switch is at the OFF position its associated MODCK line is pulled high 1 while when at the ON posit
187. lyzer 60X Bus CPM gt lt 3 3V lt gt 5V DATA Transceivers amp Address Latches 5 SCC2 FCC2 FCC3 FCC1 SCC4 CPM 60X Bus Data 60x Bus OPTIONAL Latch Mux 60X Bus Add 0 O Res 60X Bus buffered B 5 B 5 Status Register EN 3 3V DM9161 3 3V DM9161 3 3V gt 5384 PDIUSBP1 gt 4 Figure 1 1 PQ2FADS ZU Block Diagram PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Logic Analyzer Mictors Buffered System Bus 3 3V SDRAM 32 MBytes 64 Bit 3 3V L2 CACHE 512K 64 Bit OPTIONAL 5V FLASH SIMM 8 32MByte 32 Bit 3 3 E PROM 8KByte 8 bit m x DING gt nO gt Ee 2 g AA n 5 2 Magnetics 14 2 5 Magnetics 4 SE x Bx a lt 85 Pa 2 n 2 EE Ow MOTOROLA Freescale Semiconductor Inc Hardware Preparation and Installation 2 Hardware Preparation and Installation 2 1 Introduction This chapter provides unpacking instructions hardware preparation and installation instructions for the PQ2FADS ZU 2 2 Unpacking Instructions NOTE _ If the
188. m Supported PPC 13 Divide MPTPR output by 20 PSRT 1 Generates refresh every 8 2 usec while 15 6 required This will work also for 66MHz bus 12 4usec LSRT Local 13 Divide MPTPR output by 20 PSRT 1 Generates Bus refresh every 8 2 psec while 15 6 required This will work also for 66MHz bus 12 4usec MPTPR All SDRAMs on board 2800 Divide Bus clock by 41 MPTPR 1 decimal 78 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 Physical Properties 6 1 Power Supply The board gets the power from the ATX Power Supply it seats in an ATX Chassis All the power rails on the board are derived from the ATX Power Supply There are 4 power rails with the PQ2 VDDH VDDL Internal Logic VCCSYN CPM PLL VCCSYNI Core PLL and there are 5 power rails on the PQ2FADS ZU 1 5V rail Stand By 5V rail V3 3 3 3V rail VDDL 1 7V 2 5V rail 12V rail Ste MOTOROLA PQ2FADS ZU User s Manual 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical Properties 6 12V rail PCI Connectors PQ2FADS ZU Logic amp Peripherals 5V 12V 5 1 3 3V 5 3 3 m LLI VDDL VCCSYN VDDH Power
189. m the below sources 1 COP JTAG Port 2 Manual Soft Reset 3 Internal PQ2 source Soft Reset when generated causes the 2 to reset its internal logic while keeping its hard reset configuration and memory controller setup and then jumping to the Reset vector in the exception table Since soft reset does not reset the refresh logic for dynamic RAMs their contents is preserved SRESET when asserted is extended internally by the PQ2 for an additional 512 bus clock cycles at the end of which the PQ2 waits for 16 bus clock cycles and then re checks the state of the SRESET line SRESET is an open drain signal and must be driven with an open drain gate by every external source driving it Otherwise contention will occur over that line which might cause permanent damage to either the boards logic and or to the itself 4 1 3 1 COP TAG Port Soft Reset To provide convenient soft reset capability for a COP JTAG controller SRESET line appears at the COP JTAG port connector P3 The COP JTAG controller may directly generate Soft reset by asserting low this line 4 1 3 2 Manual Soft Reset To allow run time Soft reset when the COP controller is disconnected from PQ2FADS ZU and to support resident debuggers a Soft Reset push button is provided When the Soft Reset MOTOROLA PQ2FADS ZU User s Manual 34 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Descr
190. mines how to program registers BRO amp ORO or BR4 amp OR4 within which the size and the delay of the region are determined The Flash module may be disabled enabled at any time by writing 1 70 1 1 initialization that follow the hard reset sequence at system boot 48 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description respectively to the FlashEn bit in BCSRI The Flash connection scheme is shown in Figure 4 10 FLASH SIMM DATAO 31 ADDRESSQ29 1020 WEO WEO WEI gt gt WED WES BCSR EOE POE 51 2 CSI CSO FLASH CS1 gt 65 oe 52 54 gt C53 CS3 CS4 PP PD2 SZ 4 PD3 4 PD4 PPS PD5 06 PD6 PD7 es Figure 4 10 FLASH SIMM Connection Scheme As can be seen in Figure 4 10 the FLASH CS is distributed to four CS signals The distribution depends on the size of the FLASH module installed it is read by the BCSR using the PD 1 7 pins The Hard Reset configuration word stored in the FLASH differs from the one stored in the E PROM in the BPS field which is the Boot Port Size the 2 is 8 bits while the FLASH is 32 bits 4 9 1 Flash Programming Voltage Support is given to 5V as well
191. mp SlotlIntB PON DEFAULT SlotlIntB_Active HardReset B 0 amp PCI INTA B amp SlotlIntBMask fb SlotlIntBMask fb then ISlotlintB Active else SlotlintB Active state SlotlIntB Active if HardReset B 2 0 amp SlotlIntB PON DEFAULT 5 Active HardReset B 0 amp INTA amp SlotlIntBMask fb then SlotlintB Active else ISlotlintB Active state diagram SlotlIntC state SlotllntC Active if HardReset 2 0 amp SlotllIntC PON DEFAULT SlotlIntC Active HardReset B 0 amp PCI amp SlotlIntCMask fb SlotlIntC Mask fb then ISlotlIntC Active else SlotlintC Active state SlotlIntC Active if HardReset B 2 0 amp SlotllIntC PON DEFAULT SlotllntC Active HardReset B 0 amp INTB amp SlotlIntC Mask fb then SlotlintC Active else ISlotlintC Active MOTOROLA PQ2FADS ZU User s Manual 147 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information SRSA EEEE EEK state diagram SlotlIntD state SlotllntD Active if HardReset B 2 0 amp SlotllIntD PON DEFAULT SlotlIntD Active HardReset B 0 amp B amp Slo
192. oats Also 5V power will optionally be provided for the USB connector controlled by USB VCCO in BCSR4 When USB VCCO is driven low a 5V supply will be connected to pin 1 of the USB connectors NOTE The USB function is in conflict with ATM 16 bit UTOPIA bus and Fast Ethernet MDC functions It is up to the user to select the desired function on the shared pins 4 13 5 PC Parallel Port A new feature to this board is the direct connection to a PC parallel port for the purpose of debugger connection CodeWarrior An on board logic is used to interface to the parallel port and translate the signals to COP JTAG format The parallel port support both EPP and SPP modes of the parallel port in a PC The direct connection eliminates the need for an external command converter When connected to a PC s parallel port the parallel port connection has automatic priority over the COP JTAG connector interface 4 14 Board Control amp Status Register BCSR Most of the hardware options on the PQ2FADS ZU are controlled or monitored by the BCSR which is a 32 bit wide read write register file The BCSR is accessed via the PQ2s memory controller see Table 4 5 and in fact includes 8 registers BCSRO to BCSR7 Since the minimum block size for a CS region is 32K Bytes and only A 27 29 lines are decoded by the for MOTOROLA PQ2FADS ZU User s Manual 57 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
193. ol Status Register 3 BCSR3 is a control register which is accessed at offset 0xC from the BCSR base address Its read write register which may be read or written at any time BCSR3s various fields are described in Table 4 20 Table 4 19 BCSR3 Description BIT MNEMONIC Function FON ATT DEF 0 USB EN USB Port Enable When asserted low the USB chip connected to SCC4 1 R W is enabled for transmission and reception When negated the USB transceiver is in standby mode and its associated buffers are in tri state mode freeing all its signals for off board use via the expansion connectors 1 USB HI SPEED USB Hi Speed When asserted low the USB chip connected to SCC4 is 0 R W set for hi speed 12 Mbps transmission and reception When negated the USB transceiver is set to low speed 1 5 Mbps transmission and reception 2 USBVCCO USB Port VCC EN When asserted high 5V power is applied to the USB 0 R W Bus When negated power to the USB port is disconnected 3 FETHIEN2 Fast Ethernet Port 2 Initial Enable When asserted low the DM9161 s 1 R W port residing on FCC3 is enabled after Power Up or after FETH_RST is negated When negated high the DM9161 s port is isolated after Power Up or after FETH_RST is negated and all i f signals are tri stated After initial value has been set this signal has no influence over the DM9161 and MIl isolation may be control
194. on 74 Interconnect Signals So TEST EE IUS RF E Rd oui Spe HO 84 7 1 1 P1 RS232 ports 1 and 2 Connectors 84 7 1 2 and 100 10 Base T Ethernet port Connector 85 7 13 PI5 COP JTAG Connector 85 7 1 4 P7 CPM Expansion Connector 86 7 1 5 P12 P13 P14 P16 P17 P18 P23 P28 P29 P30 Logic Analyzer Connectors 93 7 1 6 9 Connectors 94 7 1 7 P27 ATX Power Supply Connector 96 7 1 8 19 20 Mach Lattice ISP Connector 96 7 1 9 P27 System Expansion 97 AE USB Connector rag hoe hoe ara hh owe 103 7 2 Programmable Logic 103 TIC GUSS ce eA ERE ade 103 7 2 2 U41 Power switch debounce 168 1 9 Schematics and Bill Of Materials 174 Tar sa EL 174 73 2 Materials 203 MOTOROLA PQ2FADS ZU User Manual V For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Vi PQ2
195. on On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Figure 7 1 PQ2FADS ZU Bill of Materials 107 2 U12 U13 DM9161 DM9161E DAVICOM 108 11 U14 U21 U23 U24 U 30 U33 IDT74CBTLV3257PG IDT74CBTLV3257PG U34 U40 U57 U66 U 70 109 1 U15 5 80828 S 80828ANMP EDR SEIKO T2 110 2 U59 U16 IDTQS3VH16233 PV IDTQS3VH16233 PV IDT 111 12 U18 U19 U20 U22 U 25 U29 IDTQS34XV245Q3 IDTQS34XV245Q3 IDT U61 U62 U63 U65 U 67 U68 112 1 U27 MPC8285 113 1 U28 SN74LVT8980ADWR SN74LVT8980ADWR 114 1 U31 MIC29500BT MIC29500 3 3BT MICREL 115 2 U69 U32 MT48LC2M32B2TG 6 MICRON 116 1 U35 M4A3_192 96 M4A3 192 96 6VC LATTICE 117 2 U37 U71 MPC2605 MPC2605ZP 66 MOTOROLA 118 3 U38 U43 U44 741 541 MC74LCX541DT MOTOROLA 119 1 U39 MPC9448 MPC9448FA MOTOROLA 120 1 U41 M4A5 64 32 V C48 M4A5 64 32 7V C48 VANTIS 121 1 U42 SN74ALVCH162260 SN74ALVCH162260 TI 122 3 U45 U77 U78 74LCX16244 MC74LCX16244DT MOTOROLA 123 1 U46 EPM3064ATC100 10 EPM3064ATC100 10 ALTERA 124 1 U47 74LCX 16245 MC74LCX16245DT ON SEMI CONDUCTOR 125 1 U49 74LVXZ161284MTD 74LVXZ161284MTD TI 126 1 U50 LM317D2T LM317D2T ON SEMI CONDUCTOR 127 1 U52 AT28HC64B 70J AT28HC64B 70J C ATMEL 128 1 U54 FLASH 5 80 M73228XG1J HBGO SMART MOD ULAR TECH NOLOGIES 129 1 U55 74LCX74D MC74LCX74D ON Semicon ductor
196. on the bus in a way that they are all synchronized by keeping all clock traces the same length The PCI Clock is also fed back to the PQ2 for synchronization and skew elimination purposes An interrupt from any PCI slot is handled by a simple generic Interrupt Controller Each slot can generate up to four interrupts for a total of twelve interrupts that the controller will support It will be made of two register mapped in a dedicated CS region One is an Interrupt Register see Table 4 3 and the second is Interrupt Mask Register see Table 4 4 A simple priority scheme is devised to allow the controller to support more than one interrupt concurrently 4 12 L2 CACHE Support To enhance benchmarking optional support is provided for L2 Cache Use is done with two MPC2605 devices each containing 256KBytes of look aside cache along with its control providing a total of 512KByte L2 cache 52 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description The cache is connected directly over the 60X bus and is supported gluelessly by the PQ2 The presence of the L2 Cache calls for the introduction of latch multiplexers over SDRAMs address lines because the MPC2605 snooping logic needs to monitor the address as is linear rather than multiplexed and the bus works by the 60X bus protocol allowing address pipelining These latch m
197. ons as BKSEL2 IRQ7 APE functions as IRQ7 CS11 AP 0 functions as CS11 36 02 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 31 Freescale Semiconductor Inc Functional Description Table 4 1 BCSR FLASH Hard Reset Configuration Word Data Prog Offset In Value Field Bus Value Implication Flash Hex Bits Bin Hex CS10PC 24 25 91 CS10 BCTL1 DBG_DIS functions as BCTL1 18 45 ALD_EN 26 0 PCI Auto Load Enable When high PCI Bridge Configuration is done automatically from the FLASH E PROM is configuration master PPC core should be disabled right after the Hard Configuration Word When low the PPC Core should configure the PCI Bridge Reserved 27 0 Reserved 28 31 0101 Determines the Core s frequency out of power up reset Actually not relevant when the PCI is active since the PCI MODCK 0 3 take presidency a For L2 Cache Boards b BCSR is set for no PCI configuration c Applies only ONCE after power up reset Table 4 2 E PROM Hard Reset Configuration Word Data Prog Offset In Value Field Bus Value Implication Flash Hex Bits Bin Hex ERB 0 Internal Arbitration Selected 0 04 148 1 0 Internal Memory Controller CSO active at system boot CDIS 2 0 Core Enabled EBM 3 0 1 0 Single PQ2 Mode for boards
198. ore Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 3 P15 COP JTAG Connector Pin No Signal Name QREQ Attribute Description Quiescent Request L When asserted low this line indicates that the 2 desires to enter low power mode This signal may be required by a debug station 3v3 3 3V power supply bus TCK Test port Clock This clock shifts in out data to from the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge TCK is pulled up internally by the PQ2 N C Not Connected TMS Test Mode Select This signal qualified with TCK in a same manner as TDI changes the state of the JTAG machine This line is pulled up internally by the PQ2 10 GND Digital GND Main GND plane 11 SRESET O D Soft Reset L This is the PQ2 s soft reset which is in fact a non maskable interrupt making the PPC take the reset exception from the reset vector This line may be driven by the PQ2 as well during soft reset sequence for 512 system clocks This line is pulled up on the ADS with a 1KQ resistor When driven externally it MUST be driven with an Open Drain gate Failure to do so may result in permanent damage to PQ2 and or to ADS logic 12 GND Digital GND Main GND plane 13 HRESET
199. ort Information Slot0IntCMaskNODE istype reg buffer PCI Slot 0 Interrupt Mask Slot0IntDMaskNODE istype reg buffer PCI Slot 0 Interrupt D Mask SlotlIntAMaskNODE istype reg buffer PCI Slot 1 Interrupt A Mask SlotlIntB MaskNODE istype reg buffer PCI Slot 1 Interrupt B Mask SlotlIntC MaskNODE istype reg buffer PCI Slot 1 Interrupt C Mask SlotlIntDMaskNODE istype reg buffer PCI Slot 1 Interrupt D Mask Slot2IntAM askNODE istype reg buffer PCI Slot 2 Interrupt A Mask Slot2IntB MaskNODE istype reg buffer PCI Slot 2 Interrupt Mask Slot2IntC MaskNODE istype reg buffer PCI Slot 2 Interrupt C Mask Slot2IntDMaskNODE istype reg buffer PCI Slot 2 Interrupt D Mask PCI Interrupt Request to PQ2 PCI InterruptNODE istype generated Interrupt to PQ2 Misceleneous KeepPinsConnected NODE istype com ESSE EEE CAIRO HHH HHH HR HHEH dg Ht FF d f
200. p RESET ATM16 ENABLE PON DEFAULT ATM16 ENABLED PON RESET amp ATM16 ENABLE PON DEFAULT ATM16 ENABLED then IATM16 ENABLED else ATM16 ENABLED MOTOROLA PQ2FADS ZU User s Manual 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information state ATM16 ENABLED if VGR_WRITE_BCSR_3 USBEn amp 5232 2 amp ATM16 ENABLE DATA BIT pin 16 ENABLED amp RESET ATM16 ENABLE PON DEFAULT ATM16 ENABLED PON RESET amp ATM16 ENABLE PON DEFAULT 16 ENABLED then ATM16 ENABLED else IATM16 ENABLED state diagram AtmS inglePHY state ATM SINGLE PHY ENABLED if WRITE BCSR 3 amp 5232 2 B amp SINGLE PHY ENABLE DATA BIT pin SINGLE PHY ENABLED amp IPON RESET SINGLE PHY ENABLE PON DEFAULT SINGLE PHY ENABLED PON_RESET amp SINGLE PHY ENABLE PON DEFAULT SINGLE PHY ENABLED then IATM SINGLE PHY ENABLED else ATM SINGLE PHY ENABLED state ATM SINGLE PHY ENABLED WRITE BCSR 36 SINGLE PHY ENABLE DATA BIT pin SINGLE PHY ENABLED 6 IPON RESET SINGLE PHY ENABLE PON DEFAULT IATM SINGLE PHY
201. p RESET FETH1 ENABLE PON DEFAULT FETH1_ENABLED PON RESET 6 FETH1 ENABLE PON DEFAULT then FETH1 ENABLED else ENABLED state diagram FEthRstl_B state FETH1 RESET ACTIVE if WRITE BCSR 16 FETH1 RESET DATA BIT pin FETH1 RESET ACTIVE 6 RESET FETH1 RESET PON DEFAULT FETH1 RESET ACTIVE PON RESET 6 FETH1 RESET PON DEFAULT FETH1 RESET ACTIVE 136 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information then RESET ACTIVE else FETH1 RESET ACTIVE state FETH1 RESET ACTIVE WRITE BCSR 16 FETH1 RESET DATA BIT pin FETH1 RESET ACTIVE amp RESET FETH1 RESET PON DEFAULT FETH1 RESET ACTIVE PON RESET amp FETH1 RESET PON DEFAULT FETH1 RESET ACTIVE then FETH1 RESET ACTIVE else IFETH1 RESET ACTIVE TRIO KAKA IKARIA RARER KAA IIA ARIK IK state diagram RS232En1_B state RS232_1 ENABLE WRITE BCSR 16 5 232 1 ENABLE DATA RS232_1 ENABLE amp RESET RS232 1 ENABLE PON DEFAULT 5232 1 ENABLE PON RESET amp 5232 1 ENABLE PON DEFAULT RS232_1 EN
202. r support maintenance and connectivity to the PQ2 ADS PCI is provided Interconnect signals The PQ2FADS ZU interconnects with external devices via the following set of connectors RS232 ports 1 and 2 P2 USB Connector P3 and P4 100 10 Base T Ethernet ports dp 7 8 9 P15 JTAG 7 CPM Expansion P12 P13 P14 P16 P17 P18 P23 P28 P29 P30 Logic Analyzer Connectors P10 P8 P9 PCI Slots Connectors P27 ATX Power Supply Connector P26 P20 Mach Lattice and ALTERA In System Programming ISP 10 P25 System Expansion 11 P31 Parallel Port connector 7 1 1 P1 RS232 ports 1 and 2 Connectors is a dual 9 Pin D Type connectors as described in Table 7 1 Table 7 1 P1 Connector Pin No Signal Name Description 1 CD Carrier Detect output from the PQ2FADS ZU 2 TX Transmit Data output from the PQ2FADS ZU 3 RX Receive Data input to the PQ2FADS ZU 4 DTR Data Terminal Ready input to the PQ2FADS ZU 5 GND Ground signal of the PQ2FADS ZU 6 DSR Data Set Ready output from the PQ2FADS ZU 84 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 1 P1 Connector Pin No Signal Name Description 7 N C No connect 8 CTS Clear To Send output from the PQ2FADS ZU 9 N C No connect 7 1 2
203. ral Purpose Led 2 Indicator LD18 This is a general purpose red LED which is user controlled by BCSRO 3 2 31 Ethernet Port 1 LINK Indicator LD19 The yellow Ethernet Twisted Pair Link Integrity LED indicator LINK lights to indicate good link integrity on the 10 100 Base T port LD19 is off when the link integrity fails 3 2 32 Fast Ethernet Port 2 Full Duplex Indicator LD20 When the Dm9161 on FCC3 is enabled and is in Full Duplex operation mode the red led LD20 MOTOROLA PQ2FADS ZU User s Manual 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operating Instructions lights 3 2 33 General Purpose Led 1 Indicator LD21 This is a general purpose green LED which is user controlled by BCSRO 3 2 34 Fast Ethernet Port 2 100Base Tx Indicator LD22 When the DM9161 on FCC3 is enabled and is in 100 Mbps operation mode the green led LD22 lights 3 2 35 USB Enabled Indicator LD23 The yellow USB enable LED indicates that the USB transceiver is connected to the PQ2 3 2 36 Ethernet Port 2 LINK Indicator LD24 The yellow Ethernet Twisted Pair Link Integrity LED indicator LINK lights to indicate good link integrity on the 10 100 Base T port LD24 is off when the link integrity fails 3 2 37 Ethernet Port 2 Tx Rx Indicator 1025 The green Ethernet Transmit Receive LED indicator blinks whenever the Dm9161 on FCC3 is transmitting or receiving data via the 10 100 Base T po
204. re in conflict with other functions In that case the multi PHY UTOPIA bus will disable the two RS232 port functions 4 13 2 100 10 Base T Ports Two fast Ethernet ports with 100 Base TX I F is provided on the PQ2FADS ZU These ports also support 10 Mbps ethernet 10 Base T via the same transceiver the DM9161 by Davicom DM9161 are connected to FCC2 and FCC3 of the PQ2 via or interface which is used for both devices control and data path The initial configuration of the DM9161 on the PQ2FADS ZU is set by external resistors 100 Full Duplex in mode The selection between MII RMII for FCC2 and FCC3 is done by jumpers JP2 and JP3 respectively The DM9161 must be set to or while in power down The DM9161 reset input is driven by either asserting the FETH RST bit in BCSRI see Table 4 10 or by asserting a specific bit in an internal register via MII I F To allow external use of FCC2 and FCC3 their pins appear at the CPM expansion connectors and the ethernet transceiver may be Disabled Enabled at any time via the MIIs port The DM9161 is able to interrupt the PQ2 via IRQ7 line This line is shared also with the CPM expansion connectors Therefore any tool that is connected to IRQ7 should drive these lines with an Open Drain buffer NOTE When the 60x Data Parity option is on IRQ7 pin switches functionality to parity and the interrupt output is routed to
205. rererererererereterelerelerelelerelerelerelereteteteteteteteteteteteteteteteteterererererererererererere Pins declaration System pins SYSCLK PIN 5 ChasisPowerln B PIN 15 Chassis Power Switch PowerOn B PIN 16 istype Power Supply Power On LEE 168 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information db GHHHHE HHH He f FHF T H f dog HH og og EH GHHHHHE 4 t gH f HH dg x HH HHH Hg E HHHH HHR Chassis Power Switch Buffer Ijolelol
206. rererereteteterererereretetetetelelek state diagram SignaLampO B state SIGNAL LAMP ON WRITE BCSR 06 SIGNAL LAMPO DATA BIT pin SIGNAL LAMP ON 6 RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP PON RESET amp SIGNAL LAMPO PON DEFAULT z SIGNAL LAMP then ISIGNAL LAMP ON MOTOROLA PQ2FADS ZU User s Manual 133 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information else SIGNAL LAMP ON state SIGNAL LAMP ON WRITE BCSR 06 SIGNAL LAMPO DATA BIT pin SIGNAL LAMP ON 6 RESET SIGNAL LAMPO PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL LAMPO PON DEFAULT SIGNAL LAMP then SIGNAL LAMP ON else ISIGNAL LAMP ON a a state diagram SignaLamp1_B state SIGNAL LAMP ON WRITE BCSR 06 SIGNAL LAMP1 DATA SIGNAL LAMP 6 RESET SIGNAL LAMP1 PON DEFAULT SIGNAL LAMP PON RESET amp SIGNAL LAMP1 PON DEFAULT z SIGNAL LAMP then ISIGNAL LAMP ON else SIGNAL LAMP ON state SIGNAL LAMP ON WRITE BCSR 06 SIGNAL LAMP1 DATA BIT pin SIGNAL LAMP ON 6 RESET SIGNAL LAMP1 PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL LAMP1 PON DEFAULT SIGNAL LAMP then SIGNAL LAMP ON else ISIGNAL LAMP
207. rmation PIN 28istype reg buffer UTOPIA 16 bit enable Atm8 B PIN 116istype UTOPIA 8 bit enable AtmS ingleP HY B PIN 4istype reg buffer UTOPIA Single PHY enable AtmMultiP HY B PIN 58istype com UTOPIA Multi PHY enable AtmRst B NODE 15 reg buffer atm uni reset bit AtmR stOut B PIN 76istype uni reset driven by register orby HRESET B USBEn B PIN 5istype reg buffer USB enable USBDis B PIN 86istype USB disable USBHiSpd B PIN 26 reg buffer USB Hi Speed Select USBLowSpd B PIN 133istype USB Low Speed Select USBVccO PIN 7istype reg buffer USB Line Voltage Select PIN 9Qistype reg buffer fast ethernet trans 1 enable FEthDisl PIN 23istype fast ethernet trans 1 Disable FEthEn2 B PIN 40 fast ethernet trans 2 enable FEthDis2 B PIN 79istype fast ethernet trans 2 Disable FEthRstl B NODE istype reg buffer fast ethernet trans 1 reset bit FEthRstOutl B PIN 139istype fast eth trans 1 reset driven by register or by HRESET B FEthRst2 B NODE istype reg buffer fast ethernet trans 2 reset bit FEthRstOut2 B PIN 110istype fast eth trans 2 reset driven by register or by HRESET B FEthMDSel1 PIN 10istype Eth MDC FEthMDSel2 PIN Eth MDIO MDC Mux2 RS232bEnl B PIN 32istype
208. rmation On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 3 Interrupt Register Description BIT MNEMONIC PCIO_INTA Function PCI Slot 0 INTA PCI Slot 0 Interrupt A 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled PON DEF ATT PCIO_INTB PCI Slot 0 INTB Slot 0 Interrupt 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled PCIO INTC PCI Slot 0 INTC PCI Slot 0 Interrupt C 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled PCIO INTD PCI Slot 0 INTD PCI Slot 0 Interrupt D 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled INTA PCI Slot 1 INTA PCI Slot 1 Interrupt A 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled INTB PCI Slot 1 INTB PCI Slot 1 Interrupt B 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled INTC PCI Slot 1 INTC PCI Slot 1 Interrupt C 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled INTD PCI Slot 1 INTD PCI Slot 1 Interrupt D 0 no interrupt was requested 1 an interrupt was requested and
209. rt 3 2 38 VDDL Indication LD26 The green VDDL indicator led LD26 is lit to indicate a VDDL power activity Since VDDL level may vary LD26 s illumination level also varies accordingly 3 2 39 Parallel Port connection LD27 The green Parallel Port connection LED indicates that the board is connected directly to the Pc s parallel port and the COP JTAG connector P15 is irrelevant 3 2 40 External Debugger Connection Indicator LD28 The green external debugger connection LED indicates that a command converter can be connected to the COP JTAG connector P15 26 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 4 Functional Description In this chapter the various modules combining PQ2FADS ZU are described to their design details 4 1 Reset amp Reset Configuration There are several reset sources the PQ2FADS ZU 1 Power On Reset 2 Manual Hard Reset 3 Manual Soft Reset 4 PCI bus reset 5 PQ2 Internal Sources See also the PQ2 U M 4 1 1 Power On ResetPQ2 The power on reset to the PQ2 initializes the processor state after power up A dedicated logic using Seiko S 80728AN DR T1 which is a voltage detector of 2 8V 2 4 asserts PORESET input to the PQ2 for a period of 2 5sec This time period is long enough to cover also the VDDL stabilization powered by a different voltage regulator
210. s dark it indicates that the DM9161 is in power down mode and disconnected from FCC2 enabling the use of its associated FCC2 pins off board via the expansion connectors The state of LD12 is controlled by BCSRI 3 2 25 RS232 Port 1 ON LD13 When the yellow RS232 Port 1 ON led is lit it designates that the RS232 transceiver connected to PLA upper DB9 connector is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode and its associated SCC1 pins may be used off board via the expansion connectors 3 2 26 Fast Ethernet Port 1 Full Duplex Indicator LD14 When the Dm9161 on FCC2 is enabled and is in Full Duplex operation mode the red led LD14 lights 3 2 27 RS232 Port 2 ON LD15 When the yellow RS232 Port 2 ON led is lit it designates that the RS232 transceiver connected to P1B lower DB9 connector is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode and its associated SCC2 pins may be used off board via the expansion connectors 3 2 28 Fast Ethernet Port 1 100Base Tx Indicator LD16 When the DM9161 on FCC2 is enabled and is in 100 Mbps operation mode the green led LD16 lights 3 2 29 Ethernet Port 1 Tx Rx Indicator 1017 The green Ethernet Transmit Receive LED indicator blinks whenever the Dm9161 on FCC2 is transmitting or receiving data via the 10 100 Base T port 3 2 30 Gene
211. s taken from Flash SIMM EEPROM the functionality of the MODCKH 0 3 bits in the Hard Reset Configuration Word depends on the mode of the PCI When the PCI mode in the PQ2 Hip4 and Hip7 is enabled by jumper JP9 the MODCKH 0 3 lines are taken from SW6 1 4 and the MODCKH 0 3 bits in the Hard Reset Configuration Word are ignored When the PCI mode in the is disabled Local Bus SDRAM is enabled MODCKH 0 3 are taken from the Hard Reset Configuration Word SW6 1 4 set the upper 4 bits of the MODCK field during Hard Reset Configuration acquisition When an individual switch of SW4 1 4 is at the OFF position its corresponding MODCKH line is pulled high 17 during Hard Reset while when at the ON position pulled down 0 see Figure 2 4 2 3 7 Setting PCI MODCK for PCI Bus Clock The settings of this line determines the frequency of the PCI bus when the PQ2 is in PCI mode When PCI is set low the PCI bus frequency is set by the MODCK lines When set high the PCI bus frequency is half of what is set by the MODCK lines When switch SW6 5 is at the OFF position its corresponding PCI MODCK line is pulled high 1 enabled while when at the ON position pulled down 0 disabled see Figure 2 4 2 3 8 Setting PCI ARBITER for PCI Mode Enabled The settings of this line determines the operation of the PCI Arbiter when the PQ2 is in PCI mode When PCI ARBITER is set low the PCI Arbiter
212. shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 2 3 Hardware Preparation To select the desired configuration and ensure proper operation of the PQ2FADS ZU board changes of the Dip Switch settings may be required before installation The location of the switches indicators Dip Switches and connectors is illustrated in Figure 2 1 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions PQ2 s Internal Logic Supply Level Range Via connector P24 Internal Logic Supply Level within range VDDL Via potentiometer RP2 PQ2Zs MODCK 1 3 Determining Core s and PLLs multiplication factor via dip switches SW6 6 8 PQ2 s Hard Reset Configuration word Source BCSR or Memory FLASH EEPROM via MOTOROLA PQ2FADS ZU User s Manual 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation ot jumper JP7 PQ2 s Boot code Source EEPROM FLASH v
213. signed to the PQ2FADS ZU See Table 4 16 for revisions encoding 24 SWOPT2 Software Option 2 This is the LSB of the field Shows the state of a dedicated dip switch providing an option to manually change a program flow 25 27 FLASH_PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH_PD 7 5 see Table 4 12 28 31 FLASH_PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket For the encoding of FLASH PD 4 1 see Table 4 13 a There is additional bit to this field See next on the same table MOTOROLA 1 Provided that BCSR is not disabled PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 61 Functional Description Freescale Semiconductor Inc Table 4 12 FLASH Presence Detect 7 5 Encoding Table 4 13 FLASH Presence Detect 4 1 Encoding FLASH_PD 7 5 FLASH DELAY nsec 000 Not Supported 001 150 010 100 120 011 80 90 100 70 101 111 Not Supported 0000 FLASH_PD 4 1 Technology Flash TYPE SIZE SM73288XG4JHBGO 32 MByte 4 banks of 4 X 2M X 8 by Smart Modular 0001 Technology SM73248XG2JHB
214. sserted SlotlIntB_Active 21 PCI Slot 1 Interrupt B asserted SlotlintC Active 21 PCI Slot 1 Interrupt C asserted SlotlintD Active 21 PCI Slot 1 Interrupt D asserted Slot2IntA Active 21 PCI Slot 2 Interrupt A asserted Slot2IntB Active 21 PCI Slot 2 Interrupt B asserted Slot2IntC Active 21 PCI Slot 2 Interrupt C asserted Slot2IntD Active 21 PCI Slot 2 Interrupt D asserted EEEE KKK P ower On Defaults Assignments EEEE EKEK Slot0IntA_PON_DEFAULT Slot lntB PON DEFAULT Slot lntC PON DEFAULT Slot lntD PON DEFAULT Slotlint PON DEFAULT SlotlintB PON DEFAULT SlotlintC PON DEFAULT SlotlintD PON DEFAULT Slot2lInt PON DEFAULT Slot2IntB PON DEFAULT Slot2lIntC PON DEFAULT 124 15 Active Slot0IntB_ Active Slot0IntC_Active Slot0IntD_ Active 15 Active 15 0 Active SlotlIntC_ Active SlotlIntD_ Active Slot2IntA_ Active Slot2IntB_ Active ISlot2IntC Active PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Slot2IntD_PON DEFAULT Slot2IntD Active EKE EKK Data Bits Assignments
215. t Error correction parity on the 60x bus transactions is optional by setting JP10 Since the 8 data parity pins are muxed with other functions Bus Mux is used to connect the data parity pins to the SDRAM device When a jumper is placed between positions 1 2 of JP10 the 60x parity support is disabled When a jumper is placed between positions 2 3 of JP10 the 60x parity support is enabled See Figure 2 8 JP10 JP10 1 2 3 1 2 3 60x Parity Disabled 60x Parity Enabled Factory Setup Figure 2 8 JP10 60x Parity Support Selection 2 3 12 Clock In Source selection The main clock source can be selected between an external off board source by connecting to P21 or an on board clock oscilator The selection is done by setting JP11 When a jumper is placed between positions 1 2 of JP11 the external clock source is enabled When a jumper is placed between positions 2 3 of JP11 the on board clock oscilator is enabled See Figure 2 9 14 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation and Installation 1 2 3 1 2 3 External Clock On board Clock Oscilator Factory Setup Figure 2 9 Clock Source Selection 2 3 13 FCC2 Ethernet Port mode MII RMII The Ethernet PHY on 2 is set by default to 100 Full Duplex can be configured to operate in MII or RMII inter
216. t Go to www freescale com Freescale Semiconductor Inc Support Information without warrying about contention between flash and data buffers equations HoldOffCnt clk SYSCLK HoldOffC nt ar 0 HoldOffC nt ap 0 HoldOffTc HoldOffCnt fb 3 when END OF FLASH EEPROM READ READ amp HoldOffC nt fb 0 HoldOffCnt fb 0 amp HoldOffCnt fb 4 amp DSyncHardReset B fb then HoldOffCnt HoldOffCnt fb 1 else HoldOffCnt 0 x Flash EEPROM Chip Selects EEE EERE ARR AAA AACR equations FlashCsOutoe hf IFlashCs1 B 50 ASSERTED amp FLASH BANK1 amp HRESET BOOT IN FLASH CSO ASSERTED amp FLASH amp BOOT IN FLASH amp DSyncHardReset CS4 ASSERTED amp FLASH 6 HRESET BOOT IN EEPROM IN EEPROM IFlashCs2 B 50 ASSERTED amp FLASH BANK2 amp HRESET BOOT IN FLASH 164 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information CSO ASSERTED amp FLASH BANK2 amp BOOT IN FLASH amp DS yncHardReset CS4 ASSERTED amp 2 amp HRESET BOOT IN EEPROM EEPROM IFlashCs3 B 50 ASSERTED amp FLASH amp HRESET FLASH CSO ASSERTED amp FLASH BANK3 6 BOOT IN FL
217. t Clock This clock shifts in out data to from the PQ2 JTAG port Data is driven on the falling edge of TCK and is sampled both internally and externally on it s rising edge TCK is pulled up internally by the PQ2 8 N C Not Connected 9 TMS Test Mode Select This signal qualified with TCK same manner as TDI changes the state of the JTAG machine This line is pulled up internally by the PQ2 10 N C Not Connected MOTOROLA PQ2FADS ZU User s Manual 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description Table 4 23 COP JTAG Port Signals Description Pin No Signal Name Attribute Description 11 SRESET Soft Reset 1 This is the PQ2 s soft reset which is in fact non maskable interrupt making the PowerPC take the reset exception from the reset vector This line may be driven by the PQ2 as well during soft reset sequence for 512 system clocks This line is pulled up on the PQ2FADS ZU with a 1KQ resistor When driven externally it MUST be driven with an Open Drain gate Failure in doing so might result in permanent damage to the PQ2 to board logic 12 GND Digital GND Main GND plane 13 HRESET PQ2 s Hard Reset L When asserted by an external H W generates Hard Reset sequence for the PQ2 During that sequence asserted by the MPC for 512 system clocks Pulled Up on the PQ2FADS Z
218. tC Slot2IntD IntMaskReg SlotOIntAM ask Slot0IntB Mask SlotOIntC Mask 51080110 Mask SlotlintA Mask SlotlintB Mask SlotlIntC Mask SlotlIntDMask Slot2IntAMask Slot2IntB Mask Slot2IntC Mask Slot2IntDMask ToolCs 1 51 B ToolCs2 B FlashCsOut FlashCs4 B FlashCs3 B FlashCs2 B FlashCs1 B Reset HardReset B SoftReset B ResetEn HardResetEn SoftResetEn TransRst AtmRstOut B FEthRstOutl B FEthRstOut2 B Rst Rst1 Rst0 Abr Abr1 Abr0 Debounce RstDeb1 AbrDeb1 SyncHardReset_B DSyncHardReset B RstCause PORIn_B Rst1 Rst0 Abr1 Abr0 HoldOffCnt HoldOffCnt2 HoldOffCnt1 HoldO ffC nt0 PD4 F PD2 PD1 Cs MOTOROLA PQ2FADS ZU User s Manual 117 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information 50 B Cs4 B BrdContRegCs B IntContCs B AtmUniCsIn B ToolCs1 B ToolCs2 B BufEn DataBufEn B ToolDataBufEn B ConfAdd A27 A28 ifndef L2CACHE CfgB yteO 0 0 0 0 1 1 0 0 CfgB ytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 Local Bus 1 0 CfgB yte3 0 0 0 0 ModckHO ModckH 1 ModckH2 M odckH3 ifdef L2CACHE CfgB yteO 0 0 0 1 1 1 0 0 CfgB ytel 1 0 1 1 0 0 1 0 CfgByte2 0 0 0 0 0 Local Bus 1 0 CfgB yte3 0 0 0 0 ModckHO ModckH 1 ModckH2 M odckH3
219. tMaskReg ADD 1 VGR_WRITE_IntReg IntContCs amp IDVal B amp R amp A27 6 A28 amp A29 WRITE IntMaskReg IIntContCs amp IDVal B amp R_B_W amp IA27 6 A28 amp A29 READ IntReg lIntContCs B amp IR B W amp 127 amp 1428 6 1429 READ IntMaskReg llntContCs B amp IR amp 1427 amp IA28 amp A29 EKEK EEK Interrupt Request Definitions IrqOe Slot0IntA SlotOIntB 5 Slot0IntD SlotlintA SlotlintB SlotlintC SlotliIntD Slot2IntA Slot2IntB Slot2IntC Slot2IntD PQ2FADS ZU User s Manual 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information a a PCI Interrupt Register definitions TRO KAKA IKARIA ARIA AAA KAKA IAA AIA AKI EKEK EEKE Slot0IntA_Active 1 PCI Slot 0 Interrupt A asserted Slot0IntB_Active 1 Slot 0 Interrupt B asserted Slot0IntC_Active 21 PCI Slot 0 Interrupt C asserted Slot0IntD_Active 21 PCI Slot 0 Interrupt D asserted SlotlIntA_Active 21 PCI Slot 1 Interrupt A a
220. terleaving allowed normal AACK operation BR4 2 2000801 Base at 2000000 8 bit port size write protect disabled no parity OR4 AT28HC64B 70JC by FFFF8866 32 KByte block size CS output half a clock after Atmel address all types access 6 w s Timing relax BR5 5384 ATM UNI PPC 04600801 Base at 04600000 8 bit port size no parity GPCM on PPC bus 5 FFFF8E56 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for write extended hold time after read BR8 PCI Interrupt Controller PPC 04731801 Base at 04730000 32 bit port size no parity GPCM on PPC bus OR8 FFFF8010 32 KByte block size all types access 1 w s 76 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Map and Initialization Table 5 7 Memory Controller Initializations For 100Mhz 2 as Boot Device a Init Value Reg Device Type Bus hex Description BRO E PROM PPC FFF00801 Base at FFFFEO000 8 bit port size write protect disabled no parity GPCM ORO AT28HC64B 70JC by FFFF8866 32 KByte block size CS output half a clock after Atmel address all types access 6 w s Timing relax BR1 BCSR PPC 04501801 Base at 04500000 32 bit port size no pari
221. the board 56 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description e DTR D Data Terminal Ready This signal is used by the software on the PQ2FADS ZU to detect if a terminal is connected to the board DSR Data Set Ready This line is always asserted by the PQ2FADS ZU RTS Request To Send This line is not connected in the PQ2FADS ZU e CTS Clear To Send This line is always asserted by the PQ2FADS ZU NOTE RS232 port 2 SCC2 functionality is in conflict with ATM 16 bit UTOPIA bus and Multi PHY UTOPIA bus RS232 port 1 is in conflict with Multi PHY UTOPIA bus It is up to the user to determine the desired function on the shared pins 4 13 4 USB Port The USB port resides on the PQ2FADS ZU and is driven by the USB port of the MPC8280 Hip7 only through SCC4 A dedicated USB transceiver the PDIUSBP11 by PHILIPS is provided along with a tri state buffer separating this port from the MPC8280 s USB port this to allow Port disable option and off board use of MPC8280 USB pins To correctly support the 2 speed modes of the USB detachable pull up resistors 3 3V provided over D and D lines of the USB controlled by the USB SPD bit of BCSR4 When USB SPD is in low speed level low D is pulled up while D remains floating When USB SPD bit is in high speed level D is being pulled up and D fl
222. therwise they are tristated 1 EXPD2 E10 The direction of these lines is determined by buffered BCTLO in C17 EXPD3 function of W R C18 EXPD4 C19 5 C20 EXPD6 C21 EXPD7 C22 EXPD8 C23 EXPD9 C24 EXPD10 C25 EXPD11 C26 EXPD12 C27 EXPD13 C28 EXPD14 C29 15 C30 N C Not Connected C31 C32 D1 GND Digital Ground Connected to main GND plane the ADS D2 D3 D4 Expansion Write Enable 0 1 L These are buffered GPCM Write Enable lines 0 1 They are meant to qualify writes to GPCM controlled DS 8 16 data bus width memory devices This to provide eased access to various communication transceivers EXPWEO controls EXPD 0 7 while EXPWE1 controls EXPD 8 15 These lines may also function as UPM controlled Byte Select Lines which allow control over almost any type of memory device MOTOROLA PQ2FADS ZU User s Manual 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Table 7 8 P17 System Expansion Connector Pin No D6 Signal Name Attribute Description GND Digital Ground Connected to main GND plane the ADS D7 EXPGLO Expansion General Purpose Lines 0 5 1 These are buffered D8 GPL 0 5 lines which assist UPM control over memory device if EXPGL Hf necessary These are output only signals and therefore do not support H D9 EXPGL2
223. tion the negation of this signal causes all the H W configuration bits to be sampled for initial values and device control is moved to the MDIO channel which is the control path of the MII port RW RS232EN 1 RS232 port 1 Enable When asserted low the RS232 transceiver for port 1 is enabled When negated the RS232 transceiver for port 1 is in standby mode and SCC1 pins are available for off board use via the expansion connectors RW RS232EN 2 RS232 port 2 Enable When asserted low the RS232 transceiver for port 2 is enabled When negated the RS232 transceiver for port 2 is in standby mode and SCC2 pins are available for off board use via the expansion connectors RW 8 31 Reserved Un implemented a Required for voltage levels adaptation 4 14 3 BCSR2 Board Control Status Register 2 BCSR 2 is a status register which is accessed at offset 8 from BCSR base address Its a read 60 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description only register which may be read at any time BCSR2s various fields are described in Table 4 11 Table 4 11 BCSR2 Description BIT MNEMONIC TSTAT 0 7 Function Tool Status 0 7 This field is reserved for external tool status report The exact meaning of each bit within this field is tool unique and therefore will
224. tlIntDMask fb then ISlotlIntD Active else SlotlIntD_Active state SlotlIntD Active if HardReset B 0 amp SlotlIntD PON DEFAULT SlotllntD Active HardReset B 0 amp B amp SlotlIntDMask fb then SlotlintD Active else ISlotlintD Active IRA ARAKI AKIRA AERA KAKA IAA AIR state diagram Slo2IntA state Slot2IntA Active if HardReset B 2 0 amp Slot2lInt PON DEFAULT Slot2IntA Active HardReset B 0 amp PCI B amp Slot2IntAMask fb S ot2IntAM ask fb then ISlot2IntA Active else Slot2IntA Active state Slot2IntA Active if HardReset B 2 0 amp Slot2lInt PON DEFAULT Slot2IntA Active HardReset B 0 amp B amp Slot2IntAMask fb then 148 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Support Information Slot2IntA Active else ISlot2IntA Active a state diagram Slot2IntB State Slot2IntB Active if HardReset B 2 0 amp Slot2IntB_ PON DEFAULT Slot2IntB Active HardReset B 0 amp PCI INTD B amp Slot2IntBMask fb 5 ot2IntBM ask fb then ISlot2IntB Active else Slot2IntB Active state Slot2IntB Active if
225. ty GPCM OR1 FFFF8010 32 KByte block size all types access 1 w s BR2 SDRAM PPC 00000041 Base at 0 64 bit port size no parity Sdram MT48LC4M32B2 by machine 1 MICRON OR2 002 0 32MByte block size 4 banks per device row starts at A7 12 row lines internal bank interleaving allowed normal AACK operation BR3 SDRAM Local D0001861 Base at D0000000 32 bit port size no parity MT48LC2M32B2 by Bus Sdram machine 2 MICRON OR3 FF803280 8MByte block size 4 banks per device row starts at A9 11 row lines internal bank interleaving allowed normal AACK operation BR4 SM73228XG1JHBGO by PPC C3801801 Base at C3800000 32 bit port size no parity Smart Modular Tech GPCM SM73248XG2JHBGO by C3001801 Base at C3000000 32 bit port size no parity Smart Modular Tech GPCM ASM73288XG4JHBGO C2001801 Base at C2000000 32 bit port size no parity by Smart Modular Tech GPCM OR4 SM73228XG1JHBGO by FF800876 8MByte block size CS early negate 11 w s Smart Modular Tech Timing relax SM73248XG2JHBGO by FF000876 16MByte block size CS early negate 11 w s Smart Modular Tech Timing relax SM73288XG4JHBGO by FE000876 32MByte block size CS early negate 11 w s Smart Modular Tech Timing relax BR5 5384 UNI 04600801 Base at 04600000 8 bit port size no parity on PPC bus 5 FFFF8E56 32K Byte block size delayed CS assertion early CS and WE negation for write cycle relaxed timing 7 w s for read 8 for wr
226. ucted in accordance with this description Trademarks This document includes these trademarks Motorola and the Motorola logo are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer For an electronic copy of this book visit Motorola s web site at http e www motorola com Motorola Inc 2003 All Rights Reserved PQ2FADS ZU Revision 0 0 User s Manual 2 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Table of Contents Section 1 General Information 1 1 TNtFOGUCTION oe e I tatu yayta sa Q aaa n tur e HE 1 1 2 Definitions Acronyms and Abbreviations 2 1 3 Related Documentation 2 14 Specifications RA BERE D 1 5 PO2PEADS ZU Beat res T co ed ce eade fe ee 3 Section 2 Hardware Preparation and Installation 2 1 IMtrOdUCHION 22 7 2 2 Unp cking Instruetiolls eresi senose ee Qe 7 2 3 Hardware Preparation DAUE I e ARE ARERR E ER E 7 2 3 1 Setting VDDL Level Range 24 8 2 3 2 Setting VDDL Supply Voltage Level 9 2 3 3
227. ultiplexers are soldered in place only in case a cache is installed on board Otherwise they are omitted and bypassed by 0 resistors See also Section 4 7 3 L2 Cache Support Influence On SDRAM Design 4 12 1 L2 Cache Configuration amp Control The cache is configured via 5 configuration lines CFG 0 4 for the following functions 1 Cache size is set by CFG 0 2 The various settings of these lines per each cache module are encoded in Table 4 8 Table 4 8 L2 Cache CFG 0 2 Settings CFG 0 2 256K 000 Reserved 512K 1010 1 st Module A26 0 011 2 nd Module A26 1 2 Snoop is Enabled CFG3 driven low for both modules 3 AACK assertion enabled CFG4 driven high for both modules The caches HRESET lines are connected directly to the SRESET line of the PQ2 so that whenever Soft reset is asserted to or by the PQ2 the cache is reset along with it loosing all data previously stored in it The cache has 5 control lines that control its operation and state PWRDWN constantly set to high no power down support on the PQ2FADS ZU e L2FLUSH assertion of which flushes out the cache array This signal is controlled by BCSRO 2MISS INH in fact Cache Lock When Asserted the cache does not change its contents Controlled by BCSRO e L2TAG CLR Clears all tag memory Controlled by BCSRO e 2UPDATE INH In fact cache freeze without information loss Controlled b
228. upport Information Figure 7 1 PQ2FADS ZU Bill of Materials 76 1 R241 47K D25047KFCS ROEDER STEIN 77 3 R243 R249 R250 20 D25020RFCS DRALORIK 78 1 R244 OR5 D250R50FCS ROEDER STEIN 79 2 R326 R 283 10 D25010RFCS ROEDER STEIN 80 4 R291 R296 R298 R302 300 XXX ROEDER STEIN 81 4 R314 R315 R325 R327 15 025 O15RFCS DRALORIK 82 4 R316 R317 R349 R350 0 D25000RFCS ROEDER STEIN 83 1 R355 300 0805 W 301 BOURNS 84 1 R381 5K6 D2505K6FCS ROEDER STEIN 85 1 R385 3K D25 03K S DRALORIK 86 1 R403 172 CRCW0603 1720F DALE 87 1 R404 21R5 CRCW0603 21R5F DALE 88 1 R414 243 D25243RFCS ROEDER STEIN 89 1 5 1 POWER ON_RESET KS12 R23 CQE C amp K 90 1 SW2 ABORT KS12 R21 CQE C amp K 91 1 SW3 SOFT RESET KS12 R22 CQE C amp K 92 2 SW5 SW4 SW_DIP 4 SM 90 045 GRAYHIL 93 1 SW6 SW DIP 8 SM 90HBW 08S GRAYHIL 94 1 SW7 E101MD1ABE E101MD1ABE C amp K 98 1 91 HFBR 5805 HFBR 5805 AGILENT 99 2 U26 U2 74ACT541 74ACT541DW ON SEMI CONDUCTOR 100 2 U4 U3 MAX3241E CAI MAX3241ECAI 101 1 U5 MIC5209 2 5BS 5209 2 5 5 MICREL 102 1 U6 PDIUSBP11A PDIUSBP11A PHILIPS 103 2 U7 U8 TG22 3506 TG22 3506ND HALO 104 6 U9 U17 U 36 U48 U51 U53 74LCX125 MC74LCX125DT MOTOROLA 105 1 U10 947 MPC947FA MOTOROLA 106 1 911 5384 5384 PMC SIERRA MOTOROLA PQ2FADS ZU User s Manual 209 For More Informati
229. upt is masked 1 Mask PCI Slot 0 INTB Mask PCI Slot 0 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 2 Mask PCI Slot 0 INTC Mask PCI Slot 0 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 3 MPCIO_INTD Mask PCI Slot 0 INTD Mask PCI Slot 0 Interrupt D 0 R W 0 interrupt is available 1 interrupt is masked 4 MPCI1_INTA Mask PCI Slot 1 INTA Mask PCI Slot 1 Interrupt A 0 R W 0 interrupt is available 1 interrupt is masked 5 INTB Mask PCI Slot 1 Mask PCI Slot 1 Interrupt 0 R W 0 interrupt is available 1 interrupt is masked 6 INTC Mask PCI Slot 1 INTC Mask PCI Slot 1 Interrupt C 0 R W 0 interrupt is available 1 interrupt is masked 7 INTD Mask PCI Slot 1 INTD Mask PCI Slot 1 Interrupt D 0 R W 0 interrupt is available 4 interrupt is masked 8 MPCI2_INTA Mask PCI Slot 2 INTA Mask PCI Slot 2 Interrupt A 0 R W 0 interrupt is available T interrupt is masked 9 MPCI2_INTB Mask PCI Slot 2 INTB Mask PCI Slot 2 Interrupt B 0 R W 0 interrupt is available 4 interrupt is masked 10 MPCD Mask PCI Slot 2 INTC Mask PCI Slot 2 Interrupt C 0 R W 0 interrupt is available 1 interrupt is masked 11 MPCD INTD Mask PCI Slot 2 INTD Mask PCI Slot 2 Interrupt D 0 R W 0 interrupt is availa
230. urce Selector 23 32 12 GND c aou paged EE E bh a 23 3 2 13 Power Indicator 1 24 3 2 14 12 Indicator 102 24 3 2 15 UTOPIA 16 Indicator LD3 24 3 2 16 UTOPIA Multi PHY Indicator LD4 24 3 217 SV Indicators EDS es See te WU SNB ERO YEN 24 3 218 3 3V Indicator EDO bum beer fu EEG HU A EGER ine 24 3 2 19 USB Power Indicator LD7 24 32 20 12 Indicator EDS 24 3 2 21 RUN Indicator 9 24 3 222 ATMON DDIOS T ee n kaa pes do QUA 24 3 2 23 Fast Ethernet Port 2 Enabled 1011 25 3 2 24 Fast Ethernet Port 1 Enabled 1012 25 3 225 Port LON te Lo e ecce d Ete ro EN 25 3 2 26 Fast Ethernet Port 1 Full Duplex Indicator 914 23 3 221 RS232 Port 2 ON DES Lei et er reu ME 25 3 2 28 Fast Ethernet Port 1 100Base Tx Indicator LD16 25 3 2 29 Ethernet Port 1 Indicator LDI7 25 3 2 30 General Purpose Led 2 018
231. waiting to be handled PCD INTA PCI Slot 2 INTA PCI Slot 2 Interrupt A 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled PCI2_INTB PCI Slot 2 INTB Slot 2 Interrupt 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 10 PCD INTC PCI Slot 2 INTC PCI Slot 2 Interrupt C 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 11 PCI2_INTD PCI Slot 2 INTD PCI Slot 2 Interrupt D 0 no interrupt was requested 1 an interrupt was requested and waiting to be handled 12 31 Reserved Un implemented R W Also available is an Interrupt Mask Register which provides the user with the option to mask any of the possible PCI interrupt sources It can be read or written at any time and accessed at offset 0 4 from CS8 base address The description of the PCI Interrupt Mask Register is in Table 4 4 MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 37 Functional Description Freescale Semiconductor Inc Table 4 4 PCI Interrupt Mask Register Description BIT MNEMONIC Function PON ATT DEF 0 MPCIO INTA Mask PCI Slot 0 INTA Mask PCI Slot 0 Interrupt A 0 R W 0 interrupt is available 4 interr
232. ww freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information as BE ES asma iE E alii a SEMI CIN MOTOROLA PQ2FADS ZU User s Manual For More Information On This Product Go to www freescale com 191 Freescale Semiconductor Inc Support Information Freescale Semiconductor Inc quie parri ee SC ee reba Ire 192 HH HAAN ipit nun Lg ail 3 dim Fit d HHMH m TUM manam TREE Glee inui 1 sum Su j HB bid H 4 PQ2FADS ZU User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Support Information m MEE ni eris Hills imn idem R i i RM i 0 li i D 1 000 E f 1 i yS 1 sites hanmade
233. y BCSRO All the above signals are connected directly to both cache modules 1 1 residing on the same bus as the processor 1 Only single level is allowed with the PQ2 2 For minimum 8 Bus clock cycles MOTOROLA PQ2FADS ZU User s Manual 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Functional Description 413 Communication Ports The PQ2FADS ZU has several communication ports to allow convenient evaluation of the CPM features Obviously it is not possible to provide all types of communication interfaces supported by the CPM but it is made convenient to connect any communication interface devices to the 2 via the CPM Expansion connectors residing on the edge of the board All CPM pins are visible on MICTOR connectors In order to avoid long routes and stubs bus muxing devices are used to direct the CPM signals to a communication element on board or to the expansion connector A signal that is used on board will not be visible in the expansion connector and vise versa The control is done by enabling disabling the communication elements on board The communication ports interfaces provided on the PQ2FADS ZU are listed below 1 155 Mbps ATM UNI on with Optical interface using the UTOPIA Level 2 interface support for 8 or 16 bit in multi or single PHY 2 Two 100 10 Base T Ports on FCC2 and FCC3 with T P interface MII or RMII on Hip7 devices only
234. y Rall dined pied 6 14 V DDE ieee VIE exe 6 15 VDD Bus tans eke De eb vt 6 1 6 12 i reri He we e els edad DU 6 2 e dese Ael RN 6 2 1 ATX Power Connector 6 2 2 Fast Ethernet Port Connectors IV PQ2FADS ZU User Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Table of Contents 6 2 3 ATM 155 Port Connection 82 G24 RS232 Connector usss ee els dx 82 6 25 Expansion Connector 82 6 2 6 COPJTAG Port Connector aes Ba 82 6 2 7 Logic Analyzer Connectors 83 6 2 8 Mach s In System Programming ISP Connector 83 6 2 9 PCI Con e etforsS os 83 6 2 10 System Expansion Connector 83 6 2 LL USB Connection sas cetur Sex ee ae us 83 6 2 12 Parallel Port COnmector usus IRURE ON 83 G3 elu weed E IMS Ia ERAT SU AR E 83 Section 7 Support Informati
235. y an external tool to be read via BCSR2 of the ADS These lines are pulled up on the ADS by BS TSTATI 10 KO resistors See also Table 4 11 BCSR2 Description on page 61 B6 TSTAT2 B7 TSTAT3 B8 TSTAT4 B9 TSTATS B10 TSTAT6 Bll TSTAT7 B12 1 Tool Revision 0 3 These lines should be driven by an external tool with the Tool Revision Code to be read via BCSR2 of the ADS These TOOLREV1 lines are pulled up on the ADS by 10 KQ resistors See also Table 4 11 B14 TOOLREV2 BCSR2 Description on page 61 B15 TOOLREV3 B16 EXTOLIO I External Tool Identification 0 3 These lines should be driven by an external tool with the Tool Identification Code to be read via BCSR2 of 7 EXTOLII the ADS These lines are pulled up on the ADS by 10 resistors See B18 EXTOLI2 also Table 4 11 BCSR2 Description on page 61 B19 EXTOLI3 B20 N C Not Connected B21 EXP3 3V 3 3V Power Out These lines are connected to the main 3 3V plane of the PQ2PCIAI ADS this to provide 3 3V power where necessary for B22 external tool connected B23 B24 MOTOROLA PQ2FADS ZU User s Manual 99 For More Information On This Product Go to www freescale com Support Information Freescale Semiconductor Inc Table 7 8 P17 System Expansion Connector Pin No Signal Name Attribute Description B25 N C Not Connected B26 EXPVCC 5V

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