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AN11227 - NXP Semiconductors

1. B comprrc 1 24 SNSBOOST i SNSMAINS 2 23 RCPROT fsw HBC ee SNSAUXPFC 3 22 SSHBC EN Teu HBC max SNSCURPFC 4 21 SNSFB CCO SLOWED drive GATEHS SNSOUT 5 20 RFMAX DOWN supic 6 18 CFMIN CURRENT HBC DRIVE CONTROL arp 17 a ND Vugiceuiy 209 drive GATELS penp 8 17 SNSCURHBC KHOFMIN suPREG 8 16 n c GATELS 10 15 HB n c 11 14 SUPHS SUPHV 12 13 GATEHS aa2 003401 unregulated pee cece ewe 7 it m output EM cca RET E La i P 1 9 Rees cavesorra E L i max 2 5 V VOLTAGE max 1 5 V Mo 1 second L G6 ano sara Eo SUPHS it output 1 VOLTAGE PIN RFMAX 4 maus RRR Ter Sr S MAT 1 Vo 9 PH DISCHARGE CURRENT el T SUPHS l regulated LL i EUM LEVEL pne T 7 utu SHIFTER 0142aa860 001aal037 I 4 N HB f o drive GATEHS yg i n ADAPTIVE NON OVERLAP I SLOPE HB ee DETECTION 1L 9 1 CAPACITIVE MODE REGULATION start slope slope start slope slope SUPREG 2 5V gt 0mA Or P GATELS SNSBOOST BOOST VOLTAGE 1 7 V gt 100 mA Y aia ae x ICURHBC COMPENSATION Pu PGND 014aaa865 LO lt ET I Tptsc SNSCURHBC frequency iv H 170 uA control 1v Ln ae SEE L cB RS
2. D1 BYV25X 600 Q4 D2 D6 FCPF7N60 BYV25X 600 BAS316 C24 47 pF 1 BYQ28x 200 S Rx FCPF7N60 i h 1 15kQ C4 LP 2920HA63 00 nm J 4 Q5 3 12 arn ie L5 m FCPF7N60 D Du C25 i a C39 H 47 pF 6 c32 C37 100 nF J2 T uF T uF LED and DIM a i c30 C26 22 nF 1nF f 1 R48 7 T Ed 27kQ R44 D3 T PRESTR SE Brie 1500 a BAS316 GND PFC GND HB i mains rF amp S R51a R7 c8 10 C8a 100 47 nF R30 BnF es o RIT 1ko RET I 4 7MQ i D11 R51b R14 R11 Ws ZK s0v 10 t L 22k0 12ko R32 c27 TET C6 110 2 2nF R51c 100 nF R18 10 T 1 4 7MQ c7 R10 R51d 470nF 33kQ 10 R33 D8 T Re T S8 4120T on BAS316 t 3 6 kQ COMPPFC SNSBOOST 7 om tt KF R40 T 220 pF SA SNSMAINS RCPROT R12 ul ci 3 6 kO A 26 680 nF SNSAUXPFC SSHBC EN R34 T SNSCURPFC SNSFB 0a R15 u3 T REMAX SFH615A 2 R13 C18 i 4 1 1nF R37 Z nm t 7 SNSCURHBC C29 D9 c12 390 nF BAS316 10 nF i i th lt R25 330 kQ rT c13 680 nF R38 i i Wii R24 4700 100 cat t 22nFlY IL C14 ony STAR D4 ll 4 7 uF BYG20J c33 n m Hs 4 4 St il heatsink 82 mm x 33 mm HS2_ c19 R21 c17 c16 R20 VW t ll HE heatsink 62 mm x 33 mm 330 pF 18kQ 2 2 uF 2 2 uF 75kQ GND HB R39 C34 Pre at 04 H8 05 Dio nm nm O O O O u4 nm GND_IC R41 T n m 1 GND HB R19 E a 470 Q R26 x Y 33 kQ BAS316 R35 R
3. 4 2 3 4 5 6 7 8 2 7 V DC SNSBOOST RCPROT SSHBC EN SNSFB RFMAX CFMIN SGND SNSCURHBC hold PFC operation disable protection timer disable over current sensing n c HB SUPHS GATEHS d E 0 V DC to Vboost nom pj sense voltage if ded fi needed t COMPPFC operation SNSMAINS apply non SNSAUXPFC i protection sense voltage SNSCURPFC E if needed SNSOUT SUPIC GATEPFC PGND 25V DC SUPREG external GATEES SUPIC n c supply SUPHV jc enia i i IC enable COMPPFC operation SNSMAINS apply non SNSAUXPFC protection SNSCURPFC SNSOUT SUPIC 25 V DC external SUPIC supply GATEPFC PGND SUPREG GATELS n c SUPHV ON oar WN SNSBOOST RCPROT SSHBC EN SNSFB RFMAX CFMIN SGND SNSCURHBC hold PFC operation enable protection timer enable over current n c a sensing e Vboost nom S 01aal100 AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 85 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC Fig 60 Typical signals during a separate HBC start up for an increase in Vpoost B00 19 03 11 36 15 B Numsl 20 11 96 49 ue uml 22001 odd roca 318 a ce
4. fast slope n slow slope incomplete slope 001aal033 Fig 23 Adaptive non overlap switching during normal operating conditions The non overlap time depends on the Vug slope but has an upper and lower time limit An integrated minimum non overlap time 160 ns max prevents accidental cross conduction in all conditions The maximum non overlap time is limited to the charging time of the oscillator If the Vig slope takes more time than the charging of the oscillator 25 of Vig switching period the MOSFET is forced to switch on In this case the MOSFET is not soft switching The maximum non overlap time limitation ensures that at a high fsw ugc the MOSFET on time is at least 25 96 of the Vig switching period Capacitive mode During error conditions for example output short circuit load pulse too high or special start up conditions fsw HBc can become lower than the resonance frequency The resonant tank then has a capacitive impedance In capacitive mode the Vig slope does not start after the MOSFET has switched off It is not preferred to switch on the other MOSFET The lack of soft switching increases dissipation in the MOSFETs The conducting body diode in the MOSFET at the switching moment can damage or even destroy the device quickly All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 46 of 102 NX
5. ORGAN iosa vOKDGAMm e 6X 20005 pv VA ru AA 4 A Ne AA oe A nie LU vv VBoosr 0 V Vgoosr 40 V peii Ya v F fj N men fi D fi m Veet eu pl Vielen Kal O18 12 06 51 go Nm DO0D 10 03 12 60 47 G Mme ORGANS 5 7 DOS 19 YONOGAMA 693 OMA iv HB slope is too slow for proper HAE HEHE HHEH detection gt High frequency RRR RRR RAI li running M Hh I n i VV VV VY EVV VY VOY VN v VA Ve A Vo 9 Yeh V aL VA A A I i sae he sl ies ty a eA rw Vgoosr 100V Increase output current HB slope is fast enough for proper detection E gt Low frequency running by 3 ree normal SNSFB regulation ie TT LEENI S ween ET n rt T pete e aT a ce gp pese rd 22 oo ma Pim Ate CC A n Rote li VA j f V my NI W vy WW Wy E3494 V v yov y Vy KO d Y M Wu wy M X Aw tu EE Veoosr 3 300v T m Veeosr 350V VBoosr 395 V dmm BERE MEE 001aal101 The following list provides an association between pins and the protection states for which they are being monitored SSHBC EN When the IC lowers Vssupcy eN it indicates a protection with correction to high HBC frequency RFMAX Vremax indicates the HBC oscillator frequency which can cause a high frequency protection CFMIN A partially slow oscillator signal cannot observe proper detection of HB slope or a possible Capacitive m
6. E VSNSFB situation A Vhys Vburst Vburst normal operation stop burst stop burst normal operation VHB VSNSFB situation B Vhys Vburst Vburst 001aal048 Fig 38 Principle of burst mode operation with Vsuseg and comparator levels 9 1 SNSOUT controlled burst mode The HBC and the PFC of the SSL4120 can be operated in burst mode In burst mode the converters operate for a limited time followed by a period of non operation Burst mode operation increases the efficiency during low load conditions and can be used for current controlled outputs A simple external circuit that uses the information from the feedback loop can detect the low load condition The detection circuit pulls down Vsnsout to pause the operation of the SSL4120 for a burst off time All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 62 of 102 NXP Semiconductors AN1 1 227 9 2 SSL4120 resonant power supply control IC with PFC Vsnsout has two levels for burst mode operation burst off level for HBC 1 1 V Under this level only the HBC pauses its operation Both high side and low side power switches are off and the PFC continues operation Above this level the HBC resumes operation and it does not execute a soft start sequence burst off level for PFC 0 4 V Under this level the PFC also pauses its operation
7. 0 2 eee eee 72 OverTemperature Protection IC OTP 72 Latched protection 72 Resetting a latched protection shutdown state 73 SNSOUT protection 73 OverVoltage Protection HBC output OVP 74 OVP using the Typc auxiliary winding 74 Principle of operation llus 74 Connecting external measurement circuits 74 UnderVoltage Protection HBC output UVP 74 UVP using the Tygc auxiliary winding 74 Principle of operation 00 74 Severe voltage drop 0 0000 75 Connecting external measurement circuits 75 HBC output OVP and UVP combinations 75 Circuit configurations 75 HBC output OVP enabled and UVP disabled 75 HBC output UVP enabled and OVP disabled 76 Both HBC output OVP and UVP disabled 77 Protection timer 0 5 78 Block diagram of the RCPROT function 78 RCPROT working as protection timer 78 RCPROT working as a restart timer 79 Dimensioning the timer function 80 Miscellaneous advice and tips 81 continued gt gt NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 101 of 102 NXP Semiconductors AN11227 11 11 11 11 11 11 11 11 11 11 2 1 11 2 2 11 2 2 1 11 2 2 2 11 2 3 12 12 1 12 2 he ek moli a mA annnR why on 12 3 13 14 14 1 14 2 14 3 15
8. 4 7 MQ 1 Rcomp COMPPFC 1 T RsNsBoosT Ccomp2 I Ccomp1 ji Arne 60 KQ aaa 005142 1 Rgoost is the total of both resistors Fig 21 SNSMAINS and COMPFC circuitry with THD improvement The total parasitic capacitance on the PFC MOSFET drain consists of e MOSFET output capacitance Coss Discrete dV dt limiting capacitance Total inter winding capacitance of the PFC transformer primary winding All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 42 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC To prevent the mains current dropping to zero the PFC gate drive signal on time is increased near to Vmains zero crossings As a result the peak current increases near to V mains zero crossings and the PFC inductor energy increases The on time is increased by reducing VCOMPPFC The modulation signal is tapped from the mains voltage via resistor Rtyp and injected into Ccomp1 Via capacitor Crap Find the best Rtyp and Cryp value using experimentation However the total value of R3 and Rrup must be equal to the value for R3 as calculated in Section 7 6 In the example from Section 7 6 R3 is calculated 560 KQ with Ryup 0 During the tuning of the THD and mains harmonics ensure that the sum of R3 and Rryp is 560 KQ A good starting value for Ctyp is
9. 60 uA is able to charge the soft start capacitor Cssprc to 0 5 V A minimum soft start resistor of 12 kO is required to guarantee enabling of the PFC Cssprc provides the soft start and soft stop timing in combination with its parallel resistor HssPrc Input for indirectly sensing the output voltage of the resonant converter It is normally connected to an Typc auxiliary winding and is also an input for HBC or PFC HBC burst mode This pin has four functions related to internal comparators e OVP Vsnsout gt 3 5 V latched UVP Vsnsout lt 2 3 V protection timer e Hold HBC Vsusour lt 1 0 V stop switching HBC burst mode e Hold HBC and PFC Vsnsourt lt 0 4 V stop switching HBC and PFC burst mode The pin also contains an internal current source of 100 uA Initially the current source generates up to 1 5 V across an external impedance gt 20 kQ to avoid unintended burst mode operation All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 8 of 102 NXP Semiconductors AN1 1 227 Table 2 SSL4120 resonant power supply control IC with PFC Pinning overview continued Pin 6 7 9 10 11 12 13 14 15 16 Name SUPIC GATEPFC PGND SUPREG GATELS n c SUPHV GATEHS SUPHS HB n C Functional description IC voltage supply input and output of the internal HV start up sou
10. NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC Fig 65 Example of a 250 W application with standby supply part 1 of 3 2 005 92 Fig 66 Example of a 250 W application with standby supply part 2 of 3 lslllilsesuun 93 Fig 67 Example of a 250 W application with standby supply part 3 of 3 2 000005 94 Fig 68 Example of a SSL4120 90 W LED driver with 1 5A CC output 95 continued gt gt AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 99 of 102 NXP Semiconductors AN11227 16 Contents SSL4120 resonant power supply control IC with PFC 5 2 1 1 5 2 1 2 5 2 2 5 2 3 5 3 1 5 3 2 5 3 3 5 3 3 1 5 3 3 2 5 3 3 3 5 4 5 4 1 5 4 2 5 5 1 5 5 2 AN11227 Introduction Scope and setup iisiesls esses Related documents 55 SSL4120 highlights and features Resonant conversion Power factor correction conversion SSL4120 resonant power supply control IC With PFC aa eee ens FeatUles cepe epe aed i General features 0000 eae Power factor controller features Resonant half bridge controller features Protection features 2 0 0055 Protection features 200 0005 Typical applications Pin overview with functional description
11. e R1 R222MQ e R3 560 KQ e R42 47 KQ Ran rH EUH AD 3 yo 2MORORIO UID asi Where e CX 220 nF AN11227 All information provided in this document is subject to legal disclaimers O NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 41 of 102 NXP Semiconductors AN1 1 227 7 6 3 7 7 AN11227 SSL4120 resonant power supply control IC with PFC The time constant equals tgch Rach x CX 2465 kO x 220 nF 542 ms SNSMAINS open pin detection The SNSMAINS pin which senses Vmains has an integrated protection circuit to detect an open pin When the pin is not connected a 33 nA internal current source either pulls the pin down under the stop level of 0 9 V or keeps it under the start level of 1 15 V When the SNSMAINS pin is shorted to ground the results are similar PFC on time modulation to reach low THD When Vmains is near 0 V the energy in the PFC inductor is low because the peak current follows the mains voltage E inductor Zr 23 Before the PFC stage can transfer energy to the bus capacitor the parasitic capacitances on the drain of the PFC MOSFET must be first charged from almost 0 V to the boost voltage of 400 V to 450 V ley 24 capacitor 2 R1 es TPFC mains cx1 1 71 e rect S gt Vboost R2 RTHD T I R3 SNSMAINS 2 scrub Jr 4 7 Mo R4 T C4
12. 27 November 2012 31 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 6 6 Mutual disturbance of PFC and HBC The charge and discharge currents for the MOSFET gate of the PFC and HBC are independently driven in time Due to these current peaks being high they can give disturbance on control and sense signals As both the PFC and HBC controllers are integrated in the SSL4120 The large GATEPFC and GATELS driver currents can also give mutual interference to the controller operation Design the gate circuits and PCB layout see Section 11 1 to prevent the interference The construction shown in Figure 12 and Figure 13 helps keep the fast and high switch off current local for a high power MOSFET AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 32 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 7 PFC functions 7 1 AN11227 The PFC operates in Quasi Resonant QR or Discontinuous Conduction Mode DCM with valley detection to reduce the switch on losses The maximum switching frequency of the PFC is limited to 380 kHz which reduces switching losses by valley skipping This reduction is mainly near the zero crossings of the mains voltage and effective at low mains input voltage and medium low output load condition The 380 kH
13. 329 pF CFMIN 3x 2x 57 kHz x 2 456000 di RFMAX maximum frequency setting T serias 47x TRFMAX max i Iosc min V naxi soft start RFMAX TREMAX max R RFMAX R a V max soft start REMAX _ 2 5 V RFMAX I z I RFMAX max RFMAX max Analog to the situation with losc min f 2 oscnas 7 FR MAX max loscinin sw soft start HBC gy CcrMIN X AV sc CFMIN 4 x Conn X 2 I 8 x CcrMIN sw so t start HBC Losc min RFMAX max 7 47 I 8 Cermin Sow sopt starnnpc 190 pA RFMAX max 47 R 25V_ _ 11 75 REMAX PULL 02 4 a A ee a E TREMAX max 8x CcrMIN i sw soft start HBC 150 pA Example Requirement fgw soft start HBC 180 kHz and Ccrmin 330 pF 8x330 pF x 180 kHz 150 nA _ 475 PLE A 69 15 pA TRFMAX max 4 7 2 5 V RnryAx 7 59 15 ud uA 36 kQ 30 31 32 33 34 35 36 37 38 39 Remark The average multiplication factor is 4 7 There is a small deviation in value depending on other parameters and presetting conditions Practical verification of the result is advised RFMAX and High Frequency Protection HFP Normally the converter does not operate continuously at the preset maximum frequency This maximum frequency is only used for a short time during soft start or temporary fault overload conditions When the operating frequency remains at or close to maximum frequency for a longer period a fault condition is assumed and a
14. All rights reserved Application note Rev 1 27 November 2012 65 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC 001aal053 Vmains 230 V AC Vmains 100 V AC 0 5 Po W Fig 43 Remaining 90 W converter losses in burst mode Varain PFC 100 V div Vo 100 mV div x Vip 100 Vidiv 001aal054 Fig 44 Simultaneous HBC and PFC burst mode operation including output voltage ripple 9 5 Choice of Vpurst and Vhys levels Set the power levels for bursting using an external comparator for dimensioning the burst mode Figure 39 shows a typical comparator circuit with hysteresis The basic choice for the voltage level at which the comparator must be active Vpurst can be made experimentally The input voltage of the resonant converter Vpoos see Figure 46 influences the relationship between Vo and Vswsrg All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 66 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 001aal041 6 0 VSNSFB e V 2 5 8 3 Se Z 5 4 5 2 5 0 0 50 100 150 200 250 Po W 1
15. The maximum peak current lp PFC max for a PFC operating in critical conduction mode can be calculated with the following equation 2x 2 T Potnameplate i z 2 x 42 x Pisas B 7 5 p PFC max 7 V V mains min mains min Example Efficiency n 0 9 Po nameplate 250 W Vimains min 90V lo PFC max 8 73 A All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 33 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC s lp PFC max 10 9 60 A 7 2 PFC regulation 7 2 1 Sensing Vboost PFC stage EET boost 4 7 MQ il RBoosT 4 7 MQ RSNSBOOST 60 KQ 001aal026 Fig 15 PFC output regulation example SNSBOOST Vboost iS set with a resistor divider between boost and the SNSBOOST pin When in regulation Veuspoosr is kept at 2 5 V The resistor divider can have a total value up to 10 MO to limit power loss RsNusBoosr can be calculated using the following equation R _ Rboost V eg SNSBOOST 6 SNSBOOST y Zy boost reg SNSBOOST Example Rooost 4 7 MQ 4 7 MO 9 4 MQ Vpoost 394 V M hi R N boost reg SNSBOOST x 60 kQ 7 boost reg SNSBOOST 394 2 Use a capacitor on SNSBOOST to prevent wrong measurements due to MOSFET switching noise mains surge events or ESD events Also for
16. supply Remark If during debugging or starting a protection has been activated switching the SUPIC supply off and on to reset a latched protection state can be required AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 84 of 102 NXP Semiconductors AN11227 SSL4120 resonant power supply control IC with PFC 4 2 3 4 5 6 T 8 o 27 V DC SNSBOOST RCPROT SSHBC EN SNSFB RFMAX CFMIN SGND SNSCURHBC hold PFC operation disable protection timer disable over current sensing n c HB SUPHS GATEHS ON Oak WD SNSBOOST RCPROT SSHBC EN SNSFB RFMAX CFMIN SGND SNSCURHBC hold PFC operation disable protection timer enable over current sensing Vboost nom expe edes 1 i 1 1 IC enable COMPPFC j operation i SNSMAINS vapply none SNSAUXPFC Protection sense voltage SNSCURPFC E if needed SNSOUT SUPIC GATEPFC PGND 25V DC SUPREG external GATEES SUPIC n c supply SUPHV a 1 1 IC enable COMPPFC i operation SNSMAINS apply non SNSAUXPFC protection sense voltage SNSCURPFC E if needed SNSOUT SUPIC GATEPFC PGND 25V DC SUPREG external GATELS SUPIC n c supply SUPHV Fig 59 HBC only start up and debugging step by step 1 I i 1 IC enable 1 i 1
17. 44 Inductive mode normal operation 44 Capacitive mode 0005 46 Capacitive Mode Regulation CMR 47 HBC oscillator 0 0 00 e eee eee 49 Presets iso ene hace SU EpL RE 49 Operational control 0 49 CFMIN and RFMAX slsssssessse 50 CFMIN minimum frequency setting 50 RFMAX maximum frequency setting 51 RFMAX and High Frequency Protection HFP 51 HBC feedback SNSFB 5 52 HBC Open Loop Protection OLP 53 SSHBC EN soft start and enable 54 Switching on and off using an external pull down function 4 54 Switching on and off using SSHBC EN 55 Hold and continue 55 Soft start HBC 0 00000 eee 55 Soft start voltage levels 56 SSHBC EN charge and discharge 56 SNSFB SSHBC EN and soft start reset operating frequency control 57 Soft start reset 0 0 2 2 00 000 cece eee 58 HBC overcurrent protection and regulation 59 HBC overcurrent regulation 59 Star p iiio sl sese A 60 HBC overcurrent protection 60 SNSCURHBC and Vpoos compensation 60 Current measurement circuits 61 SNSCURHBC layout lusus 61 Burst mode operation 62 SNSOUT controlled burst mode 62 All information provided in this document is subject to legal disclaimers
18. 7 n zZ A SLST R p ol o3g uteipA rs A i E I A i t Ss 1 j aaa 004784 SSL4120 basic application diagram Fig 1 AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 12 of 102 NXP Semiconductors AN11227 SSL4120 resonant power supply control IC with PFC rect I mains reset 1x 7 PFC i SNSAUXPFC VALLEY 43 na DETECTION valley PFC SUPREG pH T T GATEPFC m 014aaa864 PGND mals open pin 5 6 V I 1204A detection 40 pA T 9 P Q 120 pA 4 47 pA 5j AT s8vN 05V FILTER SNSCURPFC 40 uA D T undervoltage clamp RSNSCURPFC yt HK COMPPFC 1500 A aaa D4 A FO VALLEY SWITCHING pon 339 HA B D GATEPFC 25V oft SpA OTA Veoost 1 is d T PFC boost OVP Varain PFC BoostOv level 2 63 V d Vreat N HBC start HBC stop boost UVP VSNSAUXPFC M 9 demag SNSAUXPFC Vgoosr Vreo N reec demag trigger Demagnetization magnetized valley PFC 04V PFC boost SCP top fo
19. HB detection not working properly at low voltage and the internal slope detection HB not detecting a fast slope In this situation a quick check of the PFC operation can be done by lowering the external supply voltage of 2 7 V on SNSMAINS and SNSBOOST to a value under 2 5 V This function allows the gate drive pulses on GATEPFC to be seen Varying the voltage changes the on time After this check revert the voltage to 2 7 V to continue the HBC only start up see Section 11 2 2 1 2 Increasing the value of Vboost at a certain Vpoost the HB detection works correctly and fsw HBC to drive maximum power is minimal If the HB slope remains slow the output current is probably low Increasing the output current probably results in proper HB switching 3 When Vboost reaches a level closer to the nominal working voltage the depending on the output load correct output voltage is reached Then regulation starts working This results in increasing fsw Hgc with increasing Vboost until the nominal working voltage of Vboost IS Set 4 When the basic operation of the HBC with SNSFB regulation is working well protection features are added one by one Proper operation or a need for change can be evaluated 5 When a self supplying application is used the external supply voltage can be removed when the system works well at Vboost nom The system can now start with the internal high voltage start up supply and an auxiliary winding can take over the SUPIC
20. SSL4120 resonant power supply control IC with PFC 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 8 1 9 8 2 9 9 9 9 1 9 9 2 9 9 3 9 9 4 9 10 9 11 9 12 10 10 1 10 2 10 2 1 10 2 2 10 2 2 1 10 3 10 3 1 10 3 1 1 10 3 1 2 10 3 1 3 10 3 2 10 3 2 1 10 3 2 2 10 3 2 3 10 3 2 4 10 3 3 10 3 3 1 10 3 3 2 10 3 3 3 10 3 3 4 10 4 10 4 1 10 4 2 10 4 3 10 4 4 11 External comparator for burst mode implementation llle 63 Advantages of burst mode for HBC 64 Advantages of burst mode for HBC and PFC simultaneously 2 20 0 eee 65 Choice of Vpurst and Viys levels 66 Output power operating frequency characteristics 2000 0005 67 Reduced Vsypus during burst 68 Audible noise 2 0 22000 eee 68 Measurements in the resonant transformer construction 0 0000 eee aee 68 Burst power dependent noise level 69 PFC converter and resonant converter simultaneous bursting 69 PFC output voltage variations 70 PFC burst duration 70 Switching between burst and normal operation x edes ee eee i eo 70 Audible noise during mode transition 70 Design guidelines for burst mode operation 71 Enable disable burst mode 71 Unused burst mode 4 71 Protective functions 00 eee eens 72 Protection overvieW 00 72 IC protection
21. The IC is then restarted and Cncpnor is further discharged Ichfast RCPROT 2 2 MA is only activated in the case of short circuit protection of the SNSBOOST All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 79 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 10 4 4 Dimensioning the timer function AN11227 The required restart time trestart determines the time constant tRcprot made by the values of Rrcprot and Cncpnor f RCPROT ES DUE restart ae 0 48 XT con 40 1n LIERCPROT In 2 V RCPROT With this time constant and the required protection time tprotection the value of RRcPnoT and Crcprot can be calculated as follows R V RCPROT _ 4 41 RCPROT P m serene FS protection protection f t Leh slow RCPROT X l e REIROS 100 pAx 1 e RaeROT _ RCPROT 42 CRCPROT R RCPROT Example trestart 500 ms tprotection 30 ms e trcprot 240 ms HncPRor 341 kQ Cncpenor 705 nF All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 80 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 11 Miscellaneous advice and tips 11 1 PCB layout 11 1 1 General setup The SSL
22. contains an Open Loop Protection OLP This protection monitors Vsusrepg When it exceeds 7 7 V the protection timer is started In normal operating conditions the OPTO coupler current is between 0 66 mA and 2 2 mA which pulls down Vswsrg Due to a fault in the feedback loop the current can become less than 260 uA which leads to OLP All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 53 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 8 6 SSHBC EN soft start and enable The SSHBC EN pin provides the following three functions t enables the PFC VSSHBC EN gt 1 2 V PFC and HBC VssHBC EN 222 V t performs an HBC frequency sweep during soft start from 3 2 V to 8 V t provides HBC frequency control during protection Seven internal current sources operate the frequency control depending on the required action e Soft start OverCurrent Protection high low charge 160 pA 40 uA high low discharge 160 uA 40 uA e Capacitive mode regulation high low discharge 1800 uA 440 uA General bias discharge b mA ic e 8 e FREQUENCY CONTROL V e 3 2V COMP 22V enable HBC COMP hav enable PFC 120 pA 40 pA SSHBC EN 22 Oe il ipe uA 440gA 1120pA 40upA 5 yA K CSSHBC EN O disable I jd i
23. control IC with PFC 2 4 Features 2 4 1 General features Integrated power factor controller and resonant controller Universal mains supply operation High level of integration resulting in a low external component count and a cost effective design Enable input Also allows enabling of PFC only On chip high voltage start up source Standalone operation or IC supply from external DC supply 2 4 2 Power factor controller features Boundary mode operation with on time control for highest efficiency Valley zero voltage switching for minimum switching losses Frequency limitation to reduce switching losses Accurate boost voltage regulation Burst mode switching with soft start and soft stop 2 4 3 Resonant half bridge controller features Integrated high voltage level shifter Adjustable minimum and maximum frequency Maximum 500 kHz half bridge switching frequency Adaptive non overlap timing Burst mode switching 2 4 4 Protection features Safe restart mode for system fault conditions General latched protection input for output overvoltage protection or external temperature protection Protection timer for time out and restart OverTemperature Protection OTP Soft start and soft restart for both converters Undervoltage protection for mains brownout boost IC supply and output voltage Overcurrent regulation and protection for both converters Accurate overvoltage protection for boost voltage Capacitive mode protection for res
24. e G 001aal024 Fig 12 GATELS and GATEHS drivers Both HBC drivers have a strong current source capability and an extra strong current sink capability In HBC operation fast switch on of the external MOSFET is not critical as the HB node swings automatically to the correct state after switch off zero voltage switching Fast switch off however is important to limit switching losses and prevent delay especially at high frequency Supply voltage and power consumption See Section 5 5 3 and Section 5 5 5 for a description of the supply voltages and power consumption by the MOSFET drivers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 29 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 6 4 General subjects on MOSFET drivers 6 4 1 Switch on The time to switch on depends on The supply voltage for the internal driver The characteristic of the internal driver The gate capacitance to be charged The gate threshold voltage for the MOSFET to switch on The external circuit to the gate 6 4 2 Switch off The time to switch off depends on The characteristic of the internal driver The gate capacitance to be discharged The voltage on the gate just before discharge The gate threshold voltage for the MOSFET to switch off The e
25. gradually increasing Vmaing to start PFC operation Vmains nom iS applied to check PFC functionality While doing this remove any external voltage source on SNSMAINS and SNSBOOST If a problem is expected that Vo is too high Rsnspoost can be temporarily increased in value This leads to a lower output voltage regulation setting Supply a DC voltage to the mains input instead of the usual AC voltage to be able to observe proper PFC operation more easily with an oscilloscope This results in more stable signals with a fixed fsw prc for evaluation HBC and PFC operation When both converters work properly independently they can be checked working simultaneously Remove the additions used for start up and debugging Remark A normal ripple voltage on Vboost results in frequency variations in the HBC for compensation At high output power the voltage ripple on Vboost is larger All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 88 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 12 Application examples and topologies 12 1 Examples of IC evaluation and test setup Examples of a test evaluation setup are provided in Figure 63 and Figure 64 This setup can be used to e Check if an IC is still functional not defect e Evaluate specific IC functions or pin properties
26. high CMR low CMR high low ties soft start soft start 001aal042 Fig 32 SSHBC EN overview of sources clamps and levels 8 6 1 Switching on and off using an external pull down function The SSHBC EN can be used to switch on and off the converters using an external pull down function This function is often driven using a microcontroller from the secondary side of an optocoupler The main power supply PFC and HBC can be switched off for Standby mode and switched on for normal operation A separate standby supply must supply the microcontroller functions during Standby mode It is also possible to switch keep off the HBC and have the PFC operational AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 54 of 102 NXP Semiconductors AN1 1 227 8 6 1 1 8 6 1 2 AN11227 8 6 2 SSL4120 resonant power supply control IC with PFC The SSL4120 also offers the possibility to switch on off using the SNSOUT function This function is intended for burst mode operation where the duration of the on states and off states are short Switching on and off using SSHBC EN When a voltage is present at pin SUPHV or pin SUPIC a current from the SSHBC EN pin charges Cssunoyew If the pin is not pulled down this current increases Vssupcyen to 8 4 V Since Vssypcyen is above the level to enable the operatio
27. internal HB OCP level is set at 1 V for VsnscurHec This level is higher than the HB OCR level of 0 5 V When the HB OCP level is reached fsw HBc immediately jumps to fmax sott star HBc USing a soft start reset procedure The frequency jump is followed by a normal sweep down The selected fmax soft start HBC Value must limit the output power under these conditions The operation during HB OCP can be observed on Vssypcyen as a new soft start Depending on the load overload or fault condition during this new soft start OCR or OCP can be reactivated SNSCURHBC and Vb 0st compensation The primary current also called resonant current is sensed via pin SNSCURHBC It senses the momentary voltage across an external current sense resistor Rcunupgc The use of the momentary current signal allows a fast OCP and simplifies the stability of the OCR The OCR and OCP comparators compare Vsnscurusc to the maximum positive and negative values The primary current is higher for the same output power when Vboost is low A boost compensation function is included to reduce the dependency of the protected output current level for Vpoost The boost compensation sources and sinks a current from the SNSCURHBC pin This current creates a voltage across the series resistor RsnscurRHBc A typical value for Rsnscurusc is 1 KQ All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Re
28. is used for accurate high speed protection functions and control The PFC and resonant controller combination in one IC makes the SSL4120 suitable for lighting LED drivers high power and slim converter applications This application note describes the SSL4120 functions used in the typical applications NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC Table 1 Revision history Rev Date Description v 1 20121127 first release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 2 of 102 NXP Semiconductors AN1 1 22 1 Introduction SSL4120 resonant power supply control IC with PFC 1 1 Scope and setup This application note discusses the SSL4120 functions for applications in general Because the SSL4120 provides extensive functionality many subjects are discussed Each section or paragraph in this application note can be read as a standalone explanation with few cross references to other parts of the application note or the data sheet This leads to some repetition between the application note and the SSL4120 data sheet In most cases typical values are given to enhance the readability Section 1
29. lower frequency range the current in the converter reacts strongly to frequency variations Burst mode The soft start capacitor Cssupgc Ew is not charged or discharged during the non operation time in burst mode operation Vssypc en does not change during this time SNSFB SSHBC EN and soft start reset operating frequency control The SNSFB and SSHBC EN pins can simultaneously control fsygc SSHBC EN is dominant to provide protection and soft start capability Additionally there is an internal soft start reset mechanism that overrules both SNSFB and SSHBC EN control inputs and immediately sets the HBC frequency to fmax soft start HBC All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 57 of 102 NXP Semiconductors AN1 1 227 8 6 2 4 AN11227 SSL4120 resonant power supply control IC with PFC Soft start reset Some protections require a fast correction of the HBC operating frequency to a higher value but they do not require switching stops OCP is an example see Table 4 When OCP is active the oscillator control input is disconnected Cssugc ew fsw HBc S immediately set to maximum In most cases changing to fmax soft starty HBC restores safe switching operation When Vssupc eN drops under 3 2 V the control input of the oscillator reconnects to Cssugc eN and normal soft start sweep follows Figure 35 shows
30. operates at a voltage above 25 V Initially the charging current is low 1 1 mA When Vsupic exceeds the short circuit protection level of 0 65 V the generated current increases to 5 1 mA When Vgypic reaches 22 V a start operation is initiated and the source is switched off During start operation an auxiliary supply takes over the supply of SUPIC If the takeover is not successful the SUPHV source is reactivated and a restart is made Vsupic under 15 V Gate driver output for high side MOSFET of HBC High side driver supply connected to an external bootstrap capacitor between HB and SUPHS The supply is obtained using an external diode between SUPREG and SUPHS Reference for the high side driver GATEHS Pin HB is an input for the internal half bridge slope detection circuit for adaptive non overlap regulation and Capacitive mode protection It is externally connected to a half bridge node between the MOSFETSs of HBC Not connected high voltage spacer 17 18 AN11227 SNSCURHBC SGND Sense input for the momentary current of the HBC If the voltage level representing the primary current is too high internal comparators increase regulation to a fgwiHBc frequency VsnscuRHBc 0 5 V or protect VsnscurHBc 1 V by switching immediately to sw soft start HBC The additional current from SNSCURHBC can compensate protection level variations due to Vboost Variations This current leads to a voltage offset across the ex
31. seriously endanger the feasibility of the SNSOUT sensing function The coupling of the auxiliary winding with the primary winding must be as small as possible to avoid a primary voltage component on the auxiliary voltage Place the auxiliary winding on the secondary winding windings and as physically remote as possible from the primary winding The differences in results are shown in Figure 7 using comparison of secondary side position Ou 16 1 Vaux THBG impfoved T p 001aal020 Fig 7 Position the Tugc auxiliary winding for good output coupling 5 3 4 Difference between HB output UVP on SNSOUT and HBC OCP OCR on SNSCURHBC In a system that uses output voltage sensing with the SNSOUT function there can be an overlap in functionality in an output overpower or output short circuit situation In such a situation often both the SNSOUT HBC output UVP and the HBC OCP OCR on SNSCURHBO activate the protection timer There are basic differences between both functions SNSOUT monitors indirectly the HBC output voltage or another external protection circuit such as NTC temperature measurement HBC OCP OCR monitors the power in the HBC by sensing the primary current in detail SNSOUT is a more general usable protection input while SNSCURHBC is designed for HBC operation In addition SNSOUT also offers three other functions HBC output OVP latched hold HBC for burst mode AN11227 All i
32. sheet UM10575 demo board user manual All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 3 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 2 SSL4120 highlights and features AN11227 2 1 2 2 Resonant conversion Today s market demands high quality reliable small lightweight and efficient power supplies In principle the higher the operating frequency the smaller and lighter the transformers filter inductors and capacitors can be On the other hand the core switching and winding losses of the transformer increase at higher frequencies and become dominant This effect reduces the efficiency at a high frequency which limits the minimum size of the transformer The corner frequency of the output filter usually determines the bandwidth of the control loop A well chosen corner frequency allows high operating frequencies to achieve a fast dynamic response Pulse Width Modulated PWM power converters such as flyback up and down converters are widely used in low and medium power applications A disadvantage of these converters is that the PWM rectangular voltage and current waveforms cause turn on and turn off losses that limit the operating frequency The rectangular waveforms also generate broadband electromagnetic energy that can produce ElectroMagnetic Interferen
33. susBoosr lt 0 4 V e Regulation of PFC output voltage VregisusBoosr 2 5 V PFC soft OVP cycle by cycle VovP SNSBOOST gt 2 63 V Start function HBC enable Vstart SNSBOOST 2 3V e Brownout function HBC disable Vuvp snsgoosn 1 6 V AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 11 of 102 NXP Semiconductors AN11227 SSL4120 resonant power supply control IC with PFC 4 Application diagram and block diagrams disable RRFMAX CCFMIN CSSHBC EN z Ww o a L N 7 RRCPROT CRCPROT A CTHD mains Ao I 5 o o OPAS Ap Aana R E 1 ge WWIII zu goo go fg Lj M eo eet See mele CEN 1 ral a I n a a Tg z HH o9 S e II ia T S il Hp Lf 14 8 o 2 z 2 E o a I 5 2 o a 2 2 Z D a 2A D a uw amp Qo g o QA 2 8 IH Jo HJTIOHLINOO YOLOVA YAMOd a 5 Q 2 a E 2 T gt O x K u T O 2 gt 2 ain lt 2 o o 5 o oO o 7 216 6 Hi ji d Qa 5 ol o T g D
34. the PFC output voltage and Rsnsgoost controls it The internal error amplifier with a reference voltage of 2 5 V senses Vswspoosr The amplifier converts the input error voltage with a transconductance gm 80 uA V to its output This output is available at COMPPFC for adding an external loop compensation network The current from the error amplifier results in a loop voltage Vcompprc VcowPProc in combination with Vsnsmains determines the PFC switching on time A compensation network typically comprising one resistor and two capacitors at pin COMPPFC is used to stabilize the PFC control loop I RBOOST 4 7 MQ RBOOST 4 7 MQ RSNSBOOST 60 KQ aaa 004791 Fig 16 Basic PFC voltage control loop with PFCCOMP and on time modulation The transfer function has a pole at 0 Hz a zero by Regmp Ccomp2 and a pole again by Ccomp Ccomp2 Set the zero frequency to 10 Hz while the next pole frequency is at 40 Hz The zero point and pole frequencies of the compensation network can be calculated as follows 1 ia oe e 8 i 2n x Rcomp i C compa f C compl b camps 9 P 2n x Rcomp Ccomp1 5 E compl The choice also concerns a trade off between power factor and transient behavior A lower regulation bandwidth leads to a better power factor but the transient behavior becomes poorer A higher regulation bandwidth leads to a better transient response but a poor
35. this reason place the measurement resistor and the filtering capacitor close to the IC in the PCB layout 7 2 2 SNSBOOST open and short circuit pin detection The PFC does not start switching until VeNsgoosr is above 0 4 V This feature serves as short circuit protection for Vpoost and SNSBOOST pin itself 1 The SSL4120 PFC operates in Quasi Resonant QR mode with valley detection providing good efficiency Valley detection needs additional ringing time within every switching cycle This time for ringing adds short periods of no power transfer to the output capacitor The system must compensate the no power transfer with a higher peak current A rule of thumb is that the peak current in QR mode is a maximum of 10 higher than the calculated peak current in critical conduction mode AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 34 of 102 NXP Semiconductors AN1 1 227 AN11227 7 2 3 SSL4120 resonant power supply control IC with PFC An internal current source draws a small amount of current from SNSBOOST The circuit prevents switching when the pin is left open as Vsnspoost remains lower than 0 4 V This combination also creates an Open Loop Protection PFC boost OLP when for example a resistor in the boost divider network is disconnected PFCCOMP in the PFC voltage control loop The SNSBOOST pin senses
36. uA fixed current on the CFMIN pin Varmax and the connected resistor value controls the variable part of Ccryin charging discharging current VarMax can vary between 0 V minimum frequency and 2 5 V maximum frequency SNSFB and the SSHBC EN function drive Varmax HBC switching frequency The protection timer is started when the voltage level is above 1 88 V An error is assumed when the HBC is operating at high frequency for a longer time Sense input for HBC output regulation feedback by voltage Sinking a current from SNSFB creates the feedback regulation voltage on the SNSFB pin Vsnsep is produced when this current is passed through a 1 5 KQ internal resistor which is internally connected to 8 4 V The regulation voltage range is from 4 1 V to 6 4 V The SNSFB pin controls the maximum and minimum frequencies The SNSFB range is limited to 65 of the maximum frequency preset using Rremax The provision of open loop detection activates the protection timer when Vsnsrp exceeds 7 7 V All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 10 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC Table 2 Pinning overview continued Pin Name 22 SSHBC EN 23 RCPROT 24 SNSBOOST Functional description Combined soft start protection frequency control of HBC and IC enable input P
37. 001aal057 Fig 48 Example of longer burst time for PFC using ramp on SNSOUT Switching between burst and normal operation Interaction between the PFC and resonant converters in burst mode can lead to a situation where the system alternates between burst and normal mode for certain output power conditions Audible noise during mode transition As a result of the previously mentioned interactions a stable situation can occur during the following operating modes alternating in time Resonant burst with short burst time without PFC burst time too short to start Resonant burst with long burst time and PFC burst Normal operation for resonant and PFC bursts All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 70 of 102 NXP Semiconductors AN1 1 227 AN11227 9 10 9 11 9 12 SSL4120 resonant power supply control IC with PFC Transitions between modes and variations within a certain mode have a corresponding effect on audible noise Design guidelines for burst mode operation Design for a stable PFC nominal output voltage Vpoost during burst mode Best efficiency is achieved when the number of cycles for each burst is as small as possible only a few cycles Best efficiency is achieved by resistively tuning the comparator circuit to preset the Vpurst and Vhys System and component toleranc
38. 1 nF and Rtyp equal to R3 Crup sets the amount of modulation Adjusting Rtyp and R3 makes it possible to change slightly the modulation phase and the energy for each harmonic can be levelled to meet the Class C mains harmonics requirements All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 43 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 8 HBC functions 8 1 8 2 8 3 8 3 1 AN11227 Boost UVP The IC begins HBC operation when Vpgost is higher than approximately 90 Of Vpoostinom to ensure proper working of the HBC VaNusBoosr is sensed continuously When Vsnsgoost drops under 1 6 V switching of the HBC is stopped when the low side MOSFET is on The HBC re starts when Vsnspoost exceeds the start level of 2 3 V HBC switch control The internal control for the MOSFET drivers determines when the MOSFETSs are switched on and off It uses the input from several functions 1 An internal divider is used to provide the alternating switching of high side and low side MOSFET for every oscillator cycle 2 The adaptive non overlap see Section 8 3 sensing on HB determines the switch on moment 3 The oscillator see Section 8 4 determines the switch off moment 4 Several protection and enable functions determine when the resonant converter is switching HB
39. 12 96 of 102 NXP Semiconductors AN11227 14 Legal information SSL4120 resonant power supply control IC with PFC 14 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 14 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages tha
40. 13 a C314 l C315 il C316 l C317 D351 GATEHS SUPHV i a302 pi 1mF T 1 mF T 1 mF 1mF T 1 mF D312 SUPHS 12N50C3 SUPREG Stren ne 1N4148 1N4007 E HB GATELS R352 R352 aL C302 D304 pannil 220 pF BS n c SUPREG is STAT nass SBL2060CT SUPREG dO KG R30 SNSCURHBC PGND C308 C300 SNSCURHBC R Teon T a7 ue L E E 2x0 c309 L esas SGND GATEPFC T Sane SORE CFMIN SUPIC SNSCURHB T L302 R310 mE 1 uH R303 RFMAX SNSOUT 470 T27nF Sh DVRA Em SUPIC I L T 1 ZR SNSFB SNSCURPFC Ri E 48CTQ060 I cais 1 coa En SSHBC EN SNSAUXPFC _L ca06 Hii C304 cao 150 BAS316 i l TOET OET d de T ur RCPROT SNSMAINS L R365 D366 D306 i 1 t Pl SNSBOOST COMPPFC L C321 R366 270kO L C365 BAS316 48CTQ060 10 nF 39 kQ I5 nF R302 1 C322 can SUPREG 150kQ T 2 pF 4 7 nF Hee paw T R360 k Da Q307 T 1 A C362 R367 R364 BCSIA0 R361 C361 T 3 3nF 2 2kO n c Rais i 68 ka T 10 nF 77 L et i mm ala 470 Q SUPREG one R317 L C324 R312 R314 100 Q T n c 36 KQ 10 KQ p 3 C323 R323 R369 47 ne 2 7 kO ITKO H E L 1C303 2 2nF TL431 s R313 1kQ I 001aal107 1 Remove to enable burst mode operation Fig 66 Example of a 250 W application with standby supply part 2 of 3 SJ0jonpuoolul8S dXN 94d YUM 9 J043u09 Ajddns samod 1ueuosai Qz LESS LoclLLNV ajou uonesddy ZLOZ JequieAON Z2 L 9H sieuirejosip Jeba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y ZOL 40 t6 LZZLLNY
41. 16 PGB layout rmx nne onie aai 81 General setup 0 0 isses 81 Groundihg iius bake nex x RR 81 Current loops llle eese 81 Grounding layout example 82 Miscellaneous 200020000 82 Connecting SNSCURHBC pin 17 82 CFMIN pin 19 and RFMAX pin 20 82 SNSBOOST pin 00000 eee 83 Starting debugging partial circuits 83 HBC only 0 0 e eee eee ee 84 PEGonly Re ERRARE 87 Operational check without mains voltage 87 Operational check with mains voltage 88 HBC and PFC operation 88 Application examples and topologies 89 Examples of IC evaluation and test setup 89 Example of a 250 W application with standby SUDply 5d aieo Leo cti T ies 92 Example of a SSL4120 90 W LED driver with 1 5 A CC output 0 95 Abbreviations ner 96 Legal information Leee 97 Definitions 0 000002 2c eee 97 Disclaimers 0 0200 cece eee eee 97 Trademarks 00 002 000 e eee eee 97 Figures 2 0 cee ee 98 Contenis o crci cesse ho re 100 SSL4120 resonant power supply control IC with PFC Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 All rights reserved For more information please visit http Awww nxp com For sales office addresses plea
42. 4 PFCCOMP in the PFC voltage control loop 35 Mains compensation in the PFC voltage control loop EEEE ET ee 36 PFC demagnetization and valley sensing 36 PFC auxiliary sensing circuit 37 PFC frequency limit 00 38 continued gt gt NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 100 of 102 NXP Semiconductors AN11227 7 4 7 4 1 7 4 1 1 7 4 1 2 7 4 2 7 5 7 6 7 6 1 7 6 2 7 6 3 7 7 8 1 8 2 8 3 8 3 1 8 3 2 8 3 3 8 4 8 4 1 8 4 2 8 4 3 8 4 3 1 8 4 3 2 8 4 4 8 5 8 5 1 8 6 8 6 1 8 6 1 1 8 6 1 2 8 6 2 8 6 2 1 8 6 2 2 8 6 2 3 8 6 2 4 8 7 8 7 1 8 7 1 1 8 7 2 8 7 3 8 7 4 8 7 5 9 9 1 AN11227 PFC OverCurrent Regulation and Protection PFC OCR OCP 2 2 0005 38 PFC soft start and soft stop 38 Soft Starts eccere etae er Pees E VR ETE 39 SOfl SIODs s ces etam en ey e edat 39 SNSCURPFC open and short protection 39 PFC boost OverVoltage Protection OVP 39 PFC mains UnderVoltage Protection brownout protection 40 Undervoltage or brownout protection level 40 Discharging the mains input capacitor 41 SNSMAINS open pin detection PFC on time modulation to reach low THD 42 HBC functions 0 0 cece eee eee 44 Boost UVP Jalas eaa b PER Rex gin 44 HBC switch control 2 0055 44 HBC adaptive non overlap
43. 4120 contains two largely independent converter controllers in one package General advice is to separate the PFC and HBC circuits physically on the PCB to avoid mutual interference 11 1 2 Grounding Connect SGND and PGND directly under the IC on the ground plane if possible to avoid false signal detection by driver current disturbance see Figure 58 A star grounding construction provides the lowest risk of mutual converter disturbance or signal detection disturbance In this system the central star point can be chosen at the boost capacitor ground Avoid large currents on grounding tracks that are meant for signal measurement Also connect the heatsinks to the PGND to lower the HF emission 11 1 3 Current loops 001aal065 Fig 56 Gounding structure and current loops GATEPFC and GATELS AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 81 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 11 1 4 Grounding layout example 11 1 5 11 1 5 1 11 1 5 2 AN11227 001aal066 Fig 57 Grounding layout example with star point at the boost capacitor Miscellaneous Connecting SNSCURHBC pin 17 Place a series resistor Rgsnscurusc in the SNSCURHBC connection as close as possible to pin 17 The resi
44. 58 U2B 2 2kQ 82kQ LM393DG D13 BAS316 K 1 D5 C21 T 18 V 680 nF R57 C28 C22 3 3 kQ 40 nF 2 2 nF aaa 004768 Fig 68 Example of a SSL4120 90 W LED driver with 1 5 A CC output paniasad suu Iv ZLOZ A 8 dXN GO ZOL JO S6 SIOJONPUODIWIS dXN indino 99 Y GL YM 19ALUp AIT M 06 0ZLPTSS Jo ejduex3 EZL 94d U 9 J043u09 Ajddns samod 1ueuosai Qz LESS LoclLLNV NXP Semiconductors AN11227 13 Abbreviations SSL4120 resonant power supply control IC with PFC AN11227 Table 5 Abbreviations Acronym Description ADT Adaptive Dead Time BCD Bipolar CMOS DMOS CMR Common Mode Rejection EMC ElectroMagnetic Compatibility EMI ElectroMagnetic Interference or Immunity HB Half Bridge HBC Half Bridge Converter or Controller HFP High Frequency Protection HV High Voltage IC Integrated Circuit LCD Liquid Crystal Display LLC Resonant tank or Converter Lm Lr Cr in series OCP OverCurrent Protection OCR OverCurrent Regulation OLP Open Loop Protection OPTO Optocoupler OTP OverTemperature Protection OVP OverVoltage Protection PCB Printed Circuit Board PFC Power Factor Converter Controller Correction PWM Pulse Width Modulation SCP Short Circuit Protection SOI Silicon On Insulator UVP UnderVoltage Protection All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 20
45. AN11227 SSL4120 resonant power supply control IC with PFC Rev 1 27 November 2012 Application note Document information Info Content Keywords SSL4120 converter LED driver lighting resonant converter PFC burst mode Abstract The SSL4120 integrates a controller for Power Factor Correction PFC and a controller for a half bridge resonant converter HBC It provides the drive function for the discrete MOSFET for the up converter and for the two discrete power MOSFETs in a resonant half bridge configuration The resonant controller part is a high voltage controller for a zero voltage switching LLC resonant converter The resonant controller includes a high voltage level shift circuit and several protection features such as overcurrent protection open loop protection capacitive mode protection and a general purpose latched protection input In addition to the resonant controller the SSL4120 also contains a Power Factor Correction PFC controller The efficient PFC operation is achieved using quasi resonant operation at high power levels and quasi resonant operation with valley skipping at lower power levels Overcurrent protection overvoltage protection and demagnetization sensing ensures safe operation in all conditions The proprietary high voltage BCD Powerlogic process makes direct start up possible from the rectified universal mains voltage in an efficient way A second low voltage Silicon On Insulator SOI IC
46. All rights reserved Application note Rev 1 27 November 2012 27 of 102 NXP Semiconductors AN1 1 227 AN11227 5 6 2 5 6 3 SSL4120 resonant power supply control IC with PFC Example Isupic burst off 4 mA e AVsupic burst Vaux THBO bust 19 V 19V 15V 2 4V Atpurst off 25 ms Ab aeta 25 ms AV supic burst Csupic supic burst off X Value of CsuPREG CsupnEc must not be larger than Csypic to support charging of Csuprec during an HV source start This prevents a severe voltage drop on SUPIC due to the charge of Csuprec If SUPIC is supplied by an external standby source this method is not important SUPREG is the supply for the current of the gate drivers Keeping current peaks local is achieved using an SMD ceramic capacitor supported by an electrolytic capacitor This combination is necessary to provide sufficient capacitance to prevent a voltage drop during high current loads CsupReg must be much larger than the total MOSFETs capacitance that is driven to prevent significant voltage drop The MOSFET capacitance includes the SUPHS parallel load and capacitor bootstrap construction When considering the internal voltage regulator Csupngc must be gt 1 uF Often a much larger value is used for the reasons mentioned previously Value of Csupus Csupus must be much larger than the gate capacitance to support charging the gate of the high side MOSFET This size is to prevent a signi
47. All rights reserved Application note Rev 1 27 November 2012 63 of 102 NXP Semiconductors AN1 1 227 AN11227 9 3 SSL4120 resonant power supply control IC with PFC The comparator input monitors the regulation voltage Vsnsrp to a preset burst voltage value by R1 and R2 Vburst When the HBC power output power is low Vsynsrg decreases and when it reaches Vp rg the switching stops by pulling down Vsnsout to ground When the switching stops no energy is converted and Vo drops Vsnsrp then increases again When Vsywsrg reaches Vpurst Vnys Rnys Sets the voltage hysteresis switching resumes When the power delivered during a burst is larger than needed for the output VsnsFB quickly decreases stopping the switching at Vpurst The time needed for Vawsrg to reach Vburst is dependent on Vo and its load When Po increases to high levels normal operation is resumed because Vsnsrp can no longer reach Vburst Advantages of burst mode for HBC The main reasons for applying burst mode in a resonant converter are to reduce the current output current of a current controlled output improve the efficiency at low output power by reducing the power losses The graphs in Figure 40 and Figure 41 show the improvement principle in an example of a 250 W resonant converter including non bursting PFC 001aal050 100 n 80 with burst mode l 60 40 with burst mode N 20 normal m
48. Application diagram and block diagrams Supply functions Basic supply system overview SSL4120 supplies 0 00 Supply monitoring and protection Low voltage IC supply SUPIC pin SUPIC start up 2 0 0 eee eee eee VoupHv 225 Vi eee eee SUPHV not connected used SUPIC stop UVP and SCP SUPIC current consumption SUPIC using the Typc auxiliary winding SUPPI Yaara iier x exe hinges dare Rn RR cece Start up by Vsupeuv Block diagram for SUPIC start up Auxiliary winding on the HBC transformer SUPIC and SNSOUT using Typc auxiliary WNA s ep carnal RR xREEEG Der eX REPRE Auxiliary supply voltage variations by output current Voltage variations by auxiliary winding position primary side component Difference between HB output UVP on SNSOUT and HBC OCP OCR on SNSCURHBC 0 00000 e eee SUPIC supply by external voltage Star UD 26 4 Sree sace E eran d oie aes ek RS Stop SUPREG Block diagram of SUPREG regulator SUPREG during start up All information provided in this document is subject to legal disclaimers 5 5 3 5 5 4 5 5 4 1 5 5 4 2 5 5 4 3 5 5 5 5 5 5 1 5 5 5 2 5 5 6 5 5 6 1 5 5 6 2 5 6 5 6 1 5 6 1 1 5 6 1 2 5 6 1 3 5 6 1 4 5 6 2 5 6 3 6 7 2 3 7 3 7 3 1 7 3 2 Supply voltage for the output drivers SUPREG 23 Supply voltage for the output drivers SUPHS 24 Initial charging of CsupHs 20 24 Cur
49. C adaptive non overlap Inductive mode normal operation The high efficiency of a resonant converter is the result of Zero Voltage Switching ZVS of the power MOSFETs also called soft switching A small non overlap time also called dead time is required between the on time of the high side MOSFET and low side MOSFET to allow soft switching During this non overlap time the primary resonant current charge or discharges the capacitance of the half bridge between ground and Vboost After the charge or discharge the body diode of the MOSFET starts conducting and because the MOSFET drain voltage is zero there are no switching losses This mode of operation is called Inductive mode because the switching frequency is above the resonance frequency and the resonant tank has an inductive impedance All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 44 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC GATEHS l l GATELS Vboost VHB 0 ITHBC VCFMIN ia e aga T ci t 001aal032 Fig 22 Inductive mode HBC switching The time required for the transition of Vg depends on the amplitude of the resonant current at the moment of switching There is a complex relationship between the amplitude fsw HBc Vboost and Vo Ideally the IC switches o
50. C capacitive mode regulation HBC increase frequency Section 8 3 2 HBC HBC ANO HBC adaptive non overlap HBC prevent hazardous switching Section 8 3 1 AN11227 10 2 10 2 1 10 2 2 IC protection OverTemperature Protection IC OTP The SSL4120 contains an accurate internal overtemperature protection When the junction temperature exceeds the overtemperature level of 140 C the IC enters the Thermal hold state The Thermal hold state is left when the temperature has dropped by 10 C The circuit resumes operation with a complete restart including a soft start of PFC and HBC Latched protection Only an overvoltage detection on SNSOUT leads to a latched shutdown protection state Vsnsout must exceed 3 5 V to enter a latched shutdown state All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 72 of 102 NXP Semiconductors AN1 1 227 10 2 2 1 SSL4120 resonant power supply control IC with PFC Resetting a latched protection shutdown state When a latched protection shutdown state has occurred it is reset by one of the following actions Vsupic drops under 7 V and Vsupuy is lower than 7 V Vsnsmains drops under 0 8 V and then rises above 0 85 V Vssuec en is pulled down under 1 2 V Ven prc ssHBC EN In most cases a reset using Vsnsmains S activated before a reset by SUPIC SUPHV This enables a rest
51. E SENSING 15 V gt BOOST OVER VOLTAGE SENSING BOOST UNDER VOLTAGE SENSING BOOST SHORT SENSING SGND SUPREG 4 7 KQ operation Aq Ly BS170 gt H mI 43V SOFTSTART RESET SSHBC EN 220 nF 10V Example of a basic IC evaluation and test set up with a high bus voltage SENSING 0 5 V OVER CURRENT REGULATION SENSING BOOST COMPENSATION 17 SNSCU RHBC 2kQ SENSING OUTPUT 1 V OVER CURRENT PROTECTION SENSING OUTPUT 2 3 V UNDER VOLTAGE 3 5 V OVER VOLTAGE 2 on i L optional mor SENSING SENSING 82 kQ 5 SNSOUT restart 10 nF 27 ko 11 V operating 0 V for gt 150 ms restart 8 2kQ 21 SNSFB 10 nF FREQUENCY 001aal105 94d YUM 9 jo3uoo Ajddns 1 mod jueuosai Qz LESS LoclLLNV SIOJONPUODIWIS dXN 91ou uoneoiddy ZLOZ JequioAON ZZ AY sjeuirejosip Jeba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y ZOL 40 Z6 LZZLLNY paniasa Syu Iv ZLOZ N8 dXN C103 mil 0 22 pF C111 Mtl 0 22 uF Hd D101 1N5408 R101 BD101 L104 L103 D102 2 MQ 220 pH 200 uH BYV29X 600 I 724 gt V
52. Except for the SUPHV circuit all internal circuits are either directly or indirectly supplied from this pin 5 2 1 SUPIC start up Connect SUPIC to an external buffer capacitor This buffer capacitor can be charged in several ways Internal high voltage HV start up source e Auxiliary supply for example from a winding on Tugc External DC supply for example from a standby supply The IC starts operating when Vsupic and Vsupreg reach the start level The start level value of Vsupic depends on the condition of the SUPHV pin 5 2 1 1 Vsuppv 225 V Vsupnv 25 V is typically in a standalone application where the HV start up source initially charges SUPIC The Vsupic start level is 22 V The large difference between the start and stop levels 15 V allows sufficient discharge time for capacitor Csypic to take over the IC supply by the Typc auxiliary supply 5 2 1 2 SUPHV not connected used SUPHV not connected or used is the case when the SSL4120 is supplied from an external DC supply The Vsupic start level is now 17 V During start up and operation the IC is continuously supplied by the external DC supply Do not connect the SUPHV pin in this kind of application 5 2 2 SUPIC stop UVP and SCP The IC stops operating when Vsupic drops under 15 V which is the UnderVoltage Protection UVP of SUPIC While in the process of stopping the HBC continues until the low side MOSFET is active before stopping the PFC and HBC operation
53. FC or PFC HBC Externally connected to a soft start capacitor and an enable pull down function This pin has three functions Enable PFC Vssupc en gt 1 V and PFC HBC Vgsuecyen gt 2 V HBC frequency sweep during soft start from 3 2 V to 8 V HBC frequency control during protection between 8 V to 3 2 V Seven internal current sources operate the frequency control depending on which one of the following actions is required e Soft start and HB OVP high low charge 160 uA 40 uA high low discharge 160 uA 40 nA e CMR high low discharge 1800 uA 440 pA e General bias discharge 5 uA Timer presetting for time out and restart The values of an externally connected resistor RncPnor and capacitor Cacport determine the timing A 100 pA charge current activates the timer during certain protection events OCR using the SNSCURHBC pin HFP using the RFMAX pin OLP using the SNSFB pin UVP using the SNSOUT pin When the level of 4 V is reached the protection is activated Racpnor discharges Cncpnor and at a level of 0 5 V a restart is made If an SCP SNSBOOST occurs Cncpnor is quickly charged by 2 2 mA After it reaches the 4 V level Cacpnor is discharged after which a new start is initiated Sense input for boost voltage regulation output voltage of the PFC stage It is externally connected to a resistive divided boost voltage Vboost This pin has four functions e SNSBOOST pin short circuit protection VscP
54. Fig 47 Transformer construction Burst power dependent noise level The amount of audible noise is related to the amount of energy in each burst At low output power the magnetization current of the resonant converter determines the amount of energy The amount of transferred energy is low Use burst mode only at low power a few watts output power to avoid problems with audible noise When the transition level between Normal mode and burst mode is chosen at a higher output power the level of audible noise is larger Overshoot on feedback voltage When the output load is increased the system reverts to normal operation The transition from burst mode to Normal mode is based on the feedback voltage In certain burst conditions the feedback voltage can overshoot This feature keeps the system in burst mode at higher output power levels than intended As the power level in this situation is larger the amount of noise is also larger PFC converter and resonant converter simultaneous bursting When in the burst mode PFC operation stops while the resonant converter is not Switching In most cases this saves extra energy consumption by reduced switching losses from the PFC converter The total system PFC and resonant behavior in burst mode can differ from the situation when only the resonant converter would operate in burst mode Although this results in good performance there are a number of interactions All information provide
55. Introduction Section 2 SSL4120 highlights and features Section 3 Pin overview with functional description An overview of the SSL4120 pins with a summary of the functionality Section 4 Application diagram and block diagrams Section 5 Supply functions Section 6 7 8 9 and 10 describe the main functions of the SSL4120 providing an in depth explanation of the issues relating to the subject The functions are written from an application point of view Section 6 MOSFET drivers GATEPFC GATELS and GATEHS Section 7 PFC functions Section 8 HBC functions Section 9 Burst mode operation Section 10 Protective functions An overview of the protection functions of the SSL4120 with an extended explanation and related issues on the subject These functions are described and seen from an applications point of view Section 11 Miscellaneous advice and tips A collection of subjects related to PCB design and debugging are discussed including proposals for the way of working Section 12 Application examples and topologies This section contains examples of applications circuit diagrams and possible topologies Remark All values provided throughout this document are typical values unless otherwise stated 1 2 Related documents Additional information and tools can be found in other SSL4120 documents such as AN11227 SSL4120 data
56. NSCURHBC VrogiSNsBOOST ni E 4 Lh T SNSCURHBC 1kW RCURHBC protection 05V 4 AN timer 08 ds C 73mA standby Csupic ay n supply 84V TE external protection timer 84V xr open loop level 7 7 V 001aal044 SNSFB aal 15k0 B ji em i OCPHBC CO 100 na j HFPHBC OLP SNSFB ES UVP SNSOUT 15V restart SCP SNSBOOST L i latched 35V RESTART 22mA 100yA protecion Sutput QVE z PROTECTION TIMER CONTROL f P SNSOUT shut down 1 z protection output UVP Uu 235V DTA 40v timer sd IT 11V ESSE hold HBC n tA osv I 001aal063 dl RRCPROT L CRCPROT hold PFC 04V 340 kQ T 640 nF aaa 004790 Fig 3 SSL4120 block diagram part 2 AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 14 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 5 Supply functions 5 1 Basic supply system overview CMS S boost mains e lI i o I l SUPHV 12 SUPHS GATEPFC GATEHS I K C zr CSUPHS HB THBC SUPREG e external start when gt SUPHV present 22V COMP GATELS COMP enable IsuPHV m 40 7 V SUPIC SCP 0 65 V COMP COMP i 10 3 V start when stop SUPHV not present 17v SUPIC Vaux THBC Iq COMP S COMP output 3 SUPIC UVP 15V OVP latched lt ES d shut
57. P Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC GATEHS E 0 E GATELS Sd C 0 Vboost Vug no slope wrong polarity ITHBC 0 delayed oscillator VCFMIN memo eee LL sues 8 ee 0 eA delayed switch on during capacitive mode 001aal034 t Fig 24 Capacitive mode HBC switching The adaptive non overlap system of the SSL4120 always waits until the slope at the half bridge node starts It guarantees safe best switching of the MOSFETs in all circumstances In Capacitive mode it can take half the resonance period before the resonant current changes back to the correct polarity and starts charging the half bridge node The oscillator remains in its slow charging current mode until the half bridge slope starts to allow this relatively long waiting time see also Section 8 4 2 and Figure 28 The MOSFET is forced to switch on when the half bridge slope does not start at all and the slowed down oscillator reaches the high level The Capacitive Mode Regulation CMR function increases fsw ugc to bring the converter from Capacitive mode to Inductive mode operation again 8 3 3 Capacitive Mode Regulation CMR The adaptive non overlap function prevents the harmful switching in Capacitive mode However an extra action is executed which results in the CMR to end the Capacitive mode operation and return to Inductive mode operation Capaci
58. P function of SNSOUT Remark The diode is blocking for higher voltage values on SNSOUT so that the OVP is still enabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 75 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC COMP HBC output OVP 3 5V latched shutdown 5 SNSOUT Ji COMP T Vaux THBC HBC output UVP protection timer 2 35V COMP SUPREG 10 9 V Y hold HBC lt E bius 1N4148 COMP hold PFC lt F 0 4 V 3 3 kQ 001aal059 Fig 50 Example of disabling HBC output UVP function of SNSOUT 10 3 3 3 HBC output UVP enabled and OVP disabled AN11227 In some applications disabling OVP can be required Disabling OVP is realized by adding a circuit that prevents Vsnsout from exceeding 3 5 V As a practical example Vsnsout can be prevented from exceeding the preset voltage by externally adding a low impedance resistive divider with a fixed voltage The resistive divider is connected to SNSOUT using a diode This simple circuit is not accurate but it does provide the basic capability to disable the OVP function of SNSOUT Remark The diode is blocking for lower values of Vsnsout so that the UVP is still enabled Another possibility is to add a Zener diode function on SNSOUT to li
59. PFC 10 4 Protection timer The SSL4120 has a programmable timer that is used for the timing of several forms of protection The timer is used in two ways As a protection timer As a restart timer The values for both types of timer can be independently preset by an external resistor and capacitor connected to RCPROT 10 4 1 Block diagram of the RCPROT function al Pha RRCPROT I 001aal062 Fig 53 Block diagram of the RCPROT function 10 4 2 RCPROT working as protection timer short long repetitive error error error error no error Ich slow RCPROT IRCPROT 0 Vu RCPROT VRCPROT 0 protection trigger L 1L 1L t 001aal063 Fig 54 RCPROT protection timer operation AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 78 of 102 NXP Semiconductors AN1 1 227 10 4 3 AN11227 SSL4120 resonant power supply control IC with PFC Figure 54 shows the operation of the protection timer When an error condition occurs a fixed current of 100 uA flows from the RCPROT pin and charges the Cncpnor The voltage rises inverse exponentially due to Racprot The protection time is passed when the upper switching level of 4 V has been reached The appropriate protective action is then executed the cur
60. Vboost 310V DC 2 Vboost 350 V DC 3 Vooost 390 V DC Fig 45 Vsnsrp to Po characteristic examples Aspects that influence the voltage levels Vburst and Vhys of burst mode e HBC input voltage Vpoost e Vsnsep regulation levels in combination with the preset frequency range determined using Rremax and Ccemin Dynamic behavior of the regulation during burst mode and during normal operation large load variations 9 6 Output power operating frequency characteristics Figure 46 show that it is critical to make a design choice for a certain Vsnsep to start bursting This kind of characteristic has a risk that because of the spread that the system can remain in burst mode or never enter it at all The dimensioning of the LLC can be made more suitable for burst mode The standard approach is to design the system in such a way that it cannot regulate to no load even at the highest fgwHBc During the lowest loads the fsw HBc required for regulation must become infinite A voltage level for Vburst Can then easily be chosen to ensure that burst mode is activated at the lowest load and that the remaining load conditions operate in normal mode Burst mode now enables the system to operate at no load AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 67 of 102 NXP Semiconductors AN1 1 227 SSL4120
61. Vsupic has a low level detection at 0 65 V to detect a short circuit to ground This level also controls the current source from the SUPHV pin AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 16 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC 5 2 3 SUPIC current consumption The SUPIC current consumption depends on the state of the SSL4120 e Disabled IC state When the IC is disabled via the SSHBC EN pin the current consumption is low at 250 uA e SUPIC charge SUPREG charge thermal hold restart and shutdown state Only a small part of the IC is active during the charging of SUPIC and SUPREG before start up a restart sequence or shutdown after activation of protection The PFC and HBC are disabled The current consumption from SUPIC in these states is low at 400 pA Boost charge state PFC is switching and HBC is still off The high voltage start up source current is large enough to supply SUPIC The current consumption is therefore under the maximum current 5 1 mA that SUPHV can deliver Operating supply state Both the PFC and HBC are switching The current consumption is larger The MOSFET drivers are dominant in the current consumption see Section 5 5 5 especially during HBC soft start when the switching frequency is high and during no
62. ain valley detection even at low ringing amplitudes Set Vsnsauxprc as high as possible while taking into account its absolute maximum rating of 25 V The number of turns of the auxiliary winding on the PFC coil can be calculated using the following equation 25V V CSNSAUXPPCUMG y N ppe Ap X322 133 turns N aux PFCymax Vi prC max 11 Where VsNsAUXPFC max IS the absolute maximum voltage rating All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 37 of 102 NXP Semiconductors AN1 1 227 AN11227 7 3 2 7 4 7 4 1 SSL4120 resonant power supply control IC with PFC VL PF max is the maximum voltage across the PFC primary winding Nprc is the number of turns on the PFC coil for this example a value of 52 is used The Vboost level at PFC boost OVP determines the maximum voltage across the PFC primary winding and can be calculated using the following equation V VL PFC max Ee Vboost att vx 394 V 415 V 12 V eg SNSBOOST 2 5 V In this example a design value of 394 V is used for nominal Vpoost When a PFC coil with a higher number of auxiliary turns is used a resistor voltage divider can be placed between the auxiliary winding and SNSAUXPFC The total resistive value of the divider must be less than 10 kQ to prevent delay of the valley detection in combination with parasitic capaci
63. amples are provided in Section 12 Value of Csupic General Use two types of capacitors on SUPIC An SMD ceramic type with a smaller value located close to the IC and an electrolytic type with the major part of the capacitance Start up A larger capacitor is needed when the HV source initially provides the supply before it is taken over by the auxiliary winding The capacitor value must be large enough to handle the start up before the Tugc auxiliary winding supply takes over the supply of SUPIC Example Isupic start up 10 mA AVsupic start up 22 V 15 V 27 V e AlyauxHBC 15v 70 ms A vaux HBC gt 15 V 70 ms 10 mA x y 100 uF 3 Csupic gt supic start up Ay SUPIC start up Normal operation The main purpose of the capacitors on SUPIC for normal operation is to keep the current load variations for example gate drive currents local Burst mode operation When burst mode operation is applied the supply construction often uses an Typc auxiliary winding and start up from an HV source While in burst mode there is a long period during which the Type auxiliary winding is not able to charge Csypic because the HBC is not switching time between two bursts Therefore the capacitor value of Csypic must be large enough to keep the voltage above 15 V This voltage prevents activating the SUPIC undervoltage stop level All information provided in this document is subject to legal disclaimers NXP B V 2012
64. art before Vboost is discharged fast shutdown reset When resetting by interrupting the mains input some time is still required to lower Vsnsmalins Under 0 8 V The time depends on the component values used on the SNSMAINS circuit and the value Vmaing An additional aspect is a possible leakage of the bridge rectifiers that allows the charging of SNSMAINS by the rectified mains voltage capacitor reverse current through the diodes At moderate rectifier temperature the charging of SNSMAINS can be neglected but at high temperature it is a significant parameter A reset possibility by external control for example a microcontroller is available using the SSHBC EN function 10 3 SNSOUT protection AN11227 COMP t 1 5 V ia Vaux THBC I K HBC output OVP 3 5V latched shutdown 5 SNSOUT COMP T 1 HBC output UVP protection timer 2 35V SUPREG COMP m Y hold HBC 14V COMP id hold PFC 04V ele 001aal058 Fig 49 SNSOUT protection All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 73 of 102 NXP Semiconductors AN1 1 227 10 3 1 10 3 1 1 10 3 1 2 10 3 1 3 10 3 2 10 3 2 1 10 3 2 2 AN11227 SSL4120 resonant power supply control IC with PFC OverVoltage Protection HBC output OVP The SSL4120 has an OVP intended for monitoring t
65. ases Vsnsgoost to the PFC boost OVP protection level The voltage value at which PFC boost OVP becomes active can be calculated with the following equation V Vovecboost rn oe y X394 Ve 415 V 15 V eg SNSBOOST 2 5 V In the example a design value of 394 V is used for nominal Vboost PFC mains UnderVoltage Protection brownout protection Vsnsmains s sensed continuously to prevent the PFC operating at very Vmains input voltages When Vsnsmains drops under 0 89 V the switching of the PFC is stopped This mains undervoltage protection is sometimes referred to brownout protection Vsnsmains must be an average DC value that represents the Vmains The system works best with a time constant of approximately 150 ms for pin SNSMAINS When Vsnsmains drops it is internally clamped to 1 05 V which is 0 1 V under the start level of 1 15 V This level allows a fast restart when Vmains returns after a mains dropout The PFC re starts when Vsnsmains exceeds the start level of 1 15 V In the following calculations the Rtyp value is assumed to be zero to simplify the equations o R1 mains Cx JE Qe feet Hae P gt boost p RTHD I L I M I L R3 l I aaa 004792 Fig 20 SNSMAINS circuitry Undervoltage or brownout protection level The AC input voltage is measured using R1 and R2 Each resistor alternately senses half the sine cycle both resistors have the
66. ax soft start RFMAX 2 5 V fmin HBC 0 VSSHBC EN 0 3 2 V Vimax soft start RFMAX 8 4 V Volamp SSHBC EN 3 V Vpu en SSHBC 8 V Vimin HBC SSHBC EN 0 66 mA IsNsrB lt 2 2 mA regulating IsnsFB lt 0 66 mA not yet regulating 001aal043 Fig 33 fsw upc related to SSHBC EN voltage At start up Vssugc ew is low which corresponds to the fmax soft startyHBC During the soft start procedure the external capacitor Cssypc is charged Vssupc Ew rises and the fsw HBC decreases The contribution of the soft start function ends when Vssugc eN is above 8 V Vssuecven is clamped at 8 4 V and remains at that level during normal operation When Vssugpcyew iS reduced during protection or regulation the voltage is clamped at 3 0 V The clamping provides a quick response so that the fgwHBc can be reduced again Under 3 2 V the discharge current is reduced to 5 uA SSHBC EN charge and discharge Initially at start up the soft start external capacitor Cssupc ew is only charged to obtain a decreasing frequency sweep from fimax soft start HBC Besides the soft start function SSHBC EN is also used for regulation purposes such as OCR Therefore the voltage on Cssypcyen can vary by charging and discharging it by internal current sources For example in case OCR a continuous alternation between charging and discharging CssuBo EN Capacitor occurs Vssupgc eN can be regulated in this way overruling the si
67. bus R102 C112 C114 AA R103 Ic101 R119 Tero 2M0 1 pF 1 w s kO Ud 220 UF I Hn SNSAUXPFC SUPHV T zii 3 6 kO R116 R111 560 kQ 100 Q101 SNSMAINS G TEPFC pies R104 I c12 Q201 R110 Ri 47kQ T 1uF i PBSS5350T a ko ie R115 R107 R113 PGND 4 SNSCURPFC 220 12 kQ 4 7MQ i C107 R105 mh R106 47 nF 010 010 1k 1W 1W R108 33kQ COMPPFC SNSBOOST 1 24 z 4 I C106 L C105 L c109 R114 Hig nF m F 10 nF 58 2 kQ zi 001aal106 Fig 65 Example of a 250 W application with standby supply part 1 of 3 Ajddns qpueis yum uoneorjdde M osz e jo ajdwexy Zz 94d YUM 9 J043u09 Ajddns 1eMod 1ueuosai Qz LESS Loc LLNV SIOJONPUODIWIS dXN Lec INV 91ou uoneoiddy ZLOZ JequieAON Z2 L 9H sieuirejosip Jeba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y peaiesei suu Iv ZLOZ A 8 dXN GO ZOL JO 6 Td a301 Vous Pl 12N50C3T 1N4148 R355 R356 L C301 T F1 220 pF LP3925 100 510 Lp 660 uH R357 L301 100 ka Ls 110 uH a uH I T 34 4 4 2 2 4 D303 H BIA aaa 1 24V 8A 1C101 SBL2060CT iB C3
68. c and the protection timer is started e Half Bridge OverCurrent Protection HB OCP steps to fmax soft start HBC A Vboost Compensation function is included to reduce the variation in the preset protection level of the resonant current VSNSBOOST BOOST COMPENSATION CONTROL i boost Ibst SNSCURHBC EX l x HBC operating f COMP EF HB OCP z 1V COMP 7 HB OCP Ex1 1V RSNSCURHBC 17 SNSCURHBC I COMP 1kQ RCURHBC HB OCR 05V COMP I HB OCR pe lbstc SNSCURHBC 170 uA 0 uA VSNSBOOST 18V 25V 2 68V 001aal046 Fig 36 SNSCURHBC functions 8 7 1 HBC overcurrent regulation The lowest comparator levels of 0 5 V at the SNSCURHBC pin belong to the OverCurrent Regulation OCR level There is a comparator for both the positive and negative polarity If either level is exceeded discharging the soft start capacitor slowly increases the frequency Every time the OCR level is exceeded this state is latched until the next stroke and the soft start discharge current is enabled When both the positive and All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 59 of 102 NXP Semiconductors AN1 1 227 8 7 1 1 AN11227 8 7 2 8 7 3 SSL4120 resonant power supply control IC with PFC negative OCR levels are exceeded the soft start discharge current flows continuous
69. ce EMI A resonant DC to DC converter produces sinusoidal waveforms and reduces the switching losses which provide the possibility of operation at higher frequencies Recent environmental considerations have resulted in a need for high efficiency performance at low loads Burst mode operation of the resonant converter can provide the improved efficiency when the converter is required to remain active The burst mode operation can also provide a higher range of a current controlled output Why resonant conversion high power high efficiency EMI friendly compact Power factor correction conversion Most switch mode power supplies result in a non linear impedance load characteristic to the mains input Current taken from the mains supply occurs only at the highest voltage peaks and is stored in a large capacitor The energy is taken from this capacitor storage in accordance with the switch mode power supply operation characteristics Government regulations dictate special requirements for the load characteristics of certain applications Two main requirements can be distinguished Mains harmonics requirements EN61000 3 2 Class C Power factor real power apparent power All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 4 of 102 NXP Semiconductors AN1 1 227 AN11227 2 3 SSL4120 resonant power sup
70. d in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 69 of 102 NXP Semiconductors AN1 1 227 9 9 1 9 9 2 9 9 3 9 9 4 AN11227 SSL4120 resonant power supply control IC with PFC PFC output voltage variations When bursting the PFC converter the resonant control system determines the timing This feature results in a situation where the PFC cannot maintain a constant Vboost The burst operation limits the time during which the PFC can convert power This time can be too short The result is either a lower or a varying Vboost This voltage also has consequences for the resonant converter as its input voltage is not the same The working conditions change towards a new balance The resonant converter must be able to remain operational during these conditions It is important to check that the resonant controller has not been stopped because Vsnssoost is too low Triggering the boost UVP level on SNSBOOST causes an unacceptable voltage decrease in the output of the resonant converter PFC burst duration Normally a square Vsnsourt pulse leads to equal operation time for PFC and HBC see Figure 44 If a longer PFC operating time is needed for correct balance it can be achieved by adding a capacitor on SNSOUT to create a ramp signal The PFC starts at a voltage of 0 4 V allowing a longer PFC operating time S00us div
71. disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 90 of 102 91ou uoneoiddy ZLOZ JequioAON ZZ AY sieuirejosip eba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul Iv ZOL JO 16 LZZLLNY pamasa suu Ily ZLOZ A 8 dXN O low voltage supply 33 V 1N4148 1N4148 33 kQ 2N7000 Fig 64 1N4148 1ko Dh high voltage supply 400 V 100 nF 68kQ am T jra 100 kQ LL 10nF 100 uF WL 100 nF L1pF 1N4937 100 LL 1 F soov 40V Fov Fazv X soov 01w o 18kQ 100 nF Hm jio n kK SNSBOOST SUPHV SUPIC SUPREG H Hn 82kQ High side driver 14 SUPHS 6NK60 1nF SNSMAINS 2 SERIES po 1 Q 600 V 1 i L STABILIZER AND 13 GATEHS inae 18kQ S210 nF SUPREG SENSING E 15kQ z cans reset ces sje we ws COMPENSATION Low side driver SENSINGAND CLAMP SUPPLY SWITCH SUPREG an p 10nF CONTROL CONTROL m 100pF T 600 V INNER 10 GATELS 600 V 15kQ 10 150 OFF TIME EIMET ADAPTIVE 8 PGND error FREQUENCY LIMIT NONDVERIAD CENTRAL amplifier a T GROUND GND 2v SENSING Lip eeMPPEOIT 2217 V gt sueic START A AND CAPACITIVE SUPPLY PART UNDER VOLTAGE MODE PFC driver SUPREG PFC PART 680 pF 15KQ SNSCURPFC 4 h k 47 nF i 7 SOFT STARTA lax 120 kO RESTART AND C ROPROT 23 PROTECTION H 22pF TIMER OVER TEMPERATUR
72. down 3 SNSOUT L COMP COMP HBC output Ic reset lt TN UVP 2 35 V protection timer Fig 4 Basic overview internal IC supplies 5 1 1 SSL4120 supplies The main supply for the SSL4120 is SUPIC SUPHV can be used to charge SUPIC for starting the supply During operation a supply voltage is applied to SUPIC and the SUPHV source is switched off The SUPHV source is only switched on again at a new start up The internal regulator SUPREG generates a fixed voltage of 10 9 V to supply the internal MOSFET drivers GATEPFC GATELS and GATEHS A bootstrap function with an external diode is used to make supply SUPHS This is used to supply GATEHS SUPIC and SUPREG also supply other internal SSL4120 circuits AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 15 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 5 1 2 Supply monitoring and protection The supply voltages are internally monitored to determine when to initiate certain actions such as starting stopping or protection In several applications Vsypic can also be used to monitor the HBC output voltage by protection input SNSOUT The applications include for example using an auxiliary winding construction Tugc as shown in Figure 4 5 2 Low voltage IC supply SUPIC pin SUPIC is the main IC supply
73. drop across the bootstrap diode is directly related to the amount of current that is required to charge Csypys The resulting Vsypus also has a relationship to the time available for charging A large voltage drop occurs when an external MOSFET with a large gate capacitance is switched at high frequency high current and a short time During burst mode operation a low voltage on SUPHS can occur In burst mode there are long periods when switching does not occur Therefore Csypus is not charged The circuit supplied by SUPHS slowly discharges Csupus during this time When a new burst starts Vsupus is lower than during normal operation During the first switching cycles Csupus is recharged to its normal level During burst mode at low output power the switching frequency is normally rather high which limits a fast recovery of Vsupus Although in most applications the voltage drop is limited it is an important issue for evaluation It can influence the selection of the best diode type for the bootstrap function and the value of Csupus SUPREG power consumed by the MOSFET drivers During operation the drivers GATEPFC GATELS and GATEHS charging the gate capacitances of the external MOSFETs are a major part of the power consumption from SUPREG The amount of energy required in time is linear to the switching frequency Often for the MOSFETS used the total charge is specified for certain conditions With this specification an estimation can b
74. e made for the amount of current needed from SUPREG All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 25 of 102 NXP Semiconductors AN1 1 227 5 5 5 1 5 5 5 2 5 5 6 5 5 6 1 5 5 6 2 AN11227 SSL4120 resonant power supply control IC with PFC GATELS and GATEHS driving a total of two MOSFETs Alsupic ugC 2X Q sate HBC XJsw HBC 1 Example Qgate HBC 40 nC fsw HBC 100 kHz Alsupjc 2x40 nC x 100 kHz 8 mA Remark The calculated value is higher than the practical value in general because the switching operation deviates from the MOSFET specification for Qoare GATEPFC Al supiC PFC m Q Lare PFC XJsw PFC 2 Example Qgate PFc 40 nC sw PFC 100 kHz Alsupic prc 40 nC x 100 kHz 4 mA SUPREG supply voltage for other circuits The regulated voltage of SUPREG can also be used as a regulated supply for an external circuit The load of the external circuits affects the start up time and the total load IC and external circuit of SUPREG during operation Current available for supplying an external circuit from SUPREG The total current available from SUPREG is a minimum of 40 mA Determine how much current the IC requires and the amount of current required by the external circuit ISUPREG external 40 MA IsupREGiIc With respect to the IC by far the greatest am
75. er circuit parts The following provides a step by step sequence for debugging HBC only with protection disabled HBC only with protection disabled and variable DC input voltage HBC only with protection enabled PFC only 5 PFC HBC complete application WON The best approach is to check the HBC converter first and then the PFC converter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 83 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 11 2 1 HBC only Figure 59 shows a suggestion for the setup temporary additions to the existing application to force operation and the sequence for disabling enabling the different functions A moderate current load can be applied to the converters output to ascertain the correct functioning Remark A latching overvoltage detection on SNSOUT gt 3 5 V can still prevent operation VcrMiN VaArELS VGaTEHs and Vppg can be monitored to assess continuously the functioning of the converter controller When the PFC function is disabled Vboost is often applied by using a DC or AC voltage to the mains input connections Check the regulation by increasing Vpoost for the following situations in the sequence given 1 Initially at Vboost O V fsw upc is low with a short on time and a long off time This is due to the
76. er power factor All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 35 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC 7 2 4 Mains compensation in the PFC voltage control loop The mathematical equation for the transfer function of a power factor corrector contains the square of V mains y 10 mains K V mains In a typical application this results in a low bandwidth for low Vmains While at high V mains the MHR requirements can be hard to meet The SSL4120 contains a correction circuit to compensate for the Vmains influence SNSMAINS measures the average Vmaing which is used for internal compensation Figure 17 shows the relationship between Vsnsmains Vcomppec and the on time With this compensation it is possible to keep the regulation loop bandwidth constant over the complete Vmaing range This feature yields a fast transient response on load steps while still complying with Class C MHR requirements ton max at low mains VsNsMANNS 0 9 V ton PFC VSNSMAINS 3 3 V ton max at high mains 0 Vton COMPPFC max Vton COMPPFC zero VPFCCOMP 001aal028 Fig 17 Relationship between on time Vsnsmains and Vcompprc 7 3 PFC demagnetization and valley sensing When the MOSFET drain voltage is at its minimum valley switch
77. ernal power source that provides the input voltage for the internal voltage regulator that provides SUPREG At start up Vsupic must reach a specific voltage level before SUPREG is activated e Using the internal HV supply SUPREG is activated when Vsupic 22 V Using an external low voltage supply SUPREG is activated when Vsypic 17 V Supply voltage for the output drivers SUPREG The SSL4120 has a powerful output stage for GATEPFC and GATELS to drive large MOSFETs These internal drivers are supplied by SUPREG that provides a fixed voltage SUPREG EXTERNAL GATE CIRCUIT Ces T Ves 001aal023 Fig 10 Simplified model of MOSFET drive It can be seen from Figure 10 that current is drawn from SUPREG when the external MOSFET is switched on by charging the gate to a high voltage All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 23 of 102 NXP Semiconductors AN1 1 227 5 5 4 5 5 4 1 5 5 4 2 AN11227 SSL4120 resonant power supply control IC with PFC The shape of the current from SUPREG at switch on is related to e The supply voltage for the internal driver 10 9 V e The characteristic of the internal driver The gate capacitance Ces to be charged e The gate threshold voltage for the MOSFET to switch on The external circuit to the gate Re
78. es play a significant role in variations of performance in production The HBC regulation feedback loop can be optimized for Normal mode Any additional filtering can be done in the comparator circuit However use it moderately so control of the situation can be maintained during the burst mode operation Enable disable burst mode In microcontroller operated applications such as DALI controlled systems a clear separation is made between normal operation and standby operation An enable disable function can be added to avoid the resonant converter entering burst mode when short periods of low load occur during normal operation An extra enable disable switch function in the comparator circuit implements the enable disable function Unused burst mode When the burst mode is not required not applying a circuit to switch SNSOUT leaves the burst mode function inactive This can be done by removing D1 and or Q1 from Figure 39 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 71 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 10 Protective functions Most protection functions are discussed in the chapters of the systems of which they are a part Table 4 contains an overview of links to the corresponding places in this document In the following paragraphs the remaining more indepe
79. etermines the maximum frequency when Vrrmax 2 5 V The maximum frequency of the oscillator is independent of the settings on CFMIN and RFMAX and is limited internally to a minimum of 500 kHz Figure 27 shows the relationship between Vrrmax and fsw HBc for three different values of Ccrmin and Rremax flimit HB C few soft startHBC B high high B low low sw HBC C low too low fsw soft start HBC A fmin HBC A B and C fmin HBC A VRFMAX 0 VHFP RFMAX 001aal037 Fig 27 Frequency relationships Operational control During operation the state of the half bridge node HB controls the oscillator is An internal slope detection circuit monitors Vg The charge current of the oscillator is initially set to a low value of 30 uA After the start of the half bridge slope has been detected the charge current is increased to the normal value corresponding to the operating frequency Feedback via the SNSFB pin controls the working frequency Normally the half bridge slope starts directly after the switch off of the MOSFET the time with the low oscillator current 30 uA being negligible All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 49 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC The similarity between GATELS and GATEHS when switching is that the
80. ficant voltage drop on SUPHS by the gate charge When burst mode is applied Csupus is discharged by 37 uA during the time between two bursts All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 28 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 6 MOSFET drivers GATEPFC GATELS and GATEHS AN11227 6 1 6 2 6 3 The SSL4120 provides three outputs for driving external high voltage power MOSFETs e GATEPFC for driving the PFC MOSFET e GATELS for driving the low side of the HBC MOSFET e GATEHS for driving the low side of the HBC MOSFET GATEPFC The SSL4120 has a strong output stage for PFC to drive a high voltage power MOSFET It is supplied by the fixed voltage from Vsypreg 10 9 V GATELS and GATEHS Both drivers have identical driving capabilities for the gate of an external high voltage power MOSFET The low side driver is referenced to pin PGND and is supplied from SUPREG The high side driver is floating referenced to HB the connection to the midpoint of the external half bridge The high side driver is supplied using Csypus that is supplied from an external bootstrap function via SUPREG The bootstrap diode charges Csupus when the low side MOSFET is on boost 14 B GATEHS 15 9 gt GATELS IC i SUPHS CSUPHS T HB SUPREG
81. fsw HBC fmin HBC and the 0 66 mA ensures sufficient bias current for correct operation of the optocoupler fmax soft start HBC S reached at 2 2 mA The frequency range during regulation fmax tb HBc is approximately 60 of the preset range fmax sott start HBC fmin HBC The remaining upper part of the frequency range fsw HBc gt fmax foyHBC is only used during soft start or protection using the SSHBC EN pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 52 of 102 NXP Semiconductors AN11227 8 5 1 AN11227 SSL4120 resonant power supply control IC with PFC VSNSFB VRFMAX Vimin SNSFB 6 4 V VssHBC EN 8 V Vtmax SNSFB 4 1 V Velamp SNSFB 3 2 V 0 0 0 ISNSFB 260 pA 0 66 mA 2 2 mA 8mA loLP SNSFB tmin SNSFB lfmax SNSFB Iclamp SNSFB Fig 30 SNSFB V I characteristics 2 5 V Vtmax soft startRFMAX 1 5 V 0 6 X Vtmax soft start RFMAX Vtmax fb RFMAX 001aal040 001aal041 1 2 6 0 VSNSFB V 5 8 3 54 52 5 0 0 50 100 150 200 Po W 1 Vooost 310V DC 2 Vooost 350 V DC 3 Vooost 390 V DC Fig 31 Examples of Vsusrg to Po characteristics 250 HBC Open Loop Protection OLP The resonant controller of the SSL4120
82. gnal on the feedback input SNSFB The charge and discharge current can have a high value 160 uA or a low value 40 uA The SSL4120 two speed soft start sweep allows a combination of a resonant converter short start up time and stable regulation loops such as OCR All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 56 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC In some cases there can be a situation where OCR is activated during the soft start sequence This results in a feedback controlled or corrected soft start The fast charge discharge speed is used for the upper frequency range where VssHBc EN lt 5 6 V In the upper frequency range the current and power in the converter do not react strongly to frequency variations VSNSCURHBC 160 uA 0 uA 4 ISSHBC EN 49 UA 160 uA 8v 56V VSSHBC EN l 3 2 V i Fig 34 OverCurrent Regulation HBC output OCR during start up Fast soft start sweep charge and discharge Slow soft start sweep charge and discharge 001aal044 8 6 2 3 AN11227 The slow charge and discharge speed is used for the lower frequency range where Vssugpoy EN IS above 5 6 V In the
83. he HBC Vo HBC output OVP is one of the functions that is combined on the SNSOUT pin OVP using the Tyugc auxiliary winding When dealing with a mains insulated converter Vo can be measured via the Tugc auxiliary winding A special transformer construction is required to measure accurately the secondary voltage on the primary circuit side It is important that this winding has a good coupling with the secondary windings and a minimum coupling with the primary winding In this way a good representation of the output voltage situation is obtained see Section 5 3 3 1 and Figure 6 Triple insulated wire can be used to meet the mains insulation requirements Principle of operation The voltage is sensed at the SNSOUT pin via an external rectifier and resistive divider Overvoltage is detected when Vsnsout exceeds 3 5 V After detecting HBC output OVP the SSL4120 enters the latched protection shutdown state Connecting external measurement circuits When latched protection is needed for other detection circuits it can be added to SNSOUT with a series diode UnderVoltage Protection HBC output UVP The SSL4120 has an undervoltage protection intended for monitoring the HBC output voltage HBC output UVP is one of the functions that is combined on the SNSOUT pin UVP using the Typc auxiliary winding When dealing with a mains insulated converter Vo can be measured via the auxiliary winding of Tugc A special transformer construction
84. icient to charge Csupus completely Start HBC operation is when VsNusBoosr reaches 2 3 V which is approximately 90 96 of nominal Vboost Current load on SUPHS The current taken from SUPHS consists of two parts Internal MOSFET driver GATEHS e Internal circuit to control GATEHS 37 pA quiescent current Figure 11 shows that the current taken by the GATEHS driver occurs at switch on The shape of the current from SUPHS at switch on is related to The value of the supply voltage for the internal driver The characteristic of the internal driver The gate capacitance to be charged The gate threshold voltage for the MOSFET to switch on The external circuit to the gate VsupHs Can vary All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 24 of 102 NXP Semiconductors AN1 1 227 5 5 4 3 5 5 5 AN11227 SSL4120 resonant power supply control IC with PFC boost 14 gt GATEHS 15 SUPHS CSUPHS T D GATELS IC 001aal024 Fig 11 Typical application of SUPHS Lower voltage on SUPHS During normal operation each time the Half Bridge HB node is switched to ground level the bootstrap function charges Caupus Vsupus is normally lower than Vsyprec or other bootstrap supply input because of the voltage drop across the bootstrap diode The voltage
85. ing the PFC MOSFET is switched on for the next stroke This valley switching reduces switching losses and EMI see Figure 18 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 36 of 102 NXP Semiconductors AN11227 AN11227 7 3 1 SSL4120 resonant power supply control IC with PFC on 4 GATEPFC off Vboost Vrect Vdrain PFC 0 Vrect N VSNSAUXPFC 0 Vdemag SNSAUXPEC 7 Vboost Vrect N IrRPFC 0 demag trigger TPFC Valley PFC 7 top for detection 001aal029 Fig 18 PFC demagnetization and valley sensing SNSAUXPFC detects the valleys An auxiliary winding on the PFC coil provides a measurement signal on SNSAUXPFC It gives a reduced and inverted copy of the MOSFET drain voltage When a valley of the Varain PFC top at VsNSAUXPEC is detected the MOSFET is switched on If no top valley at the drain is detected on Vsnsauxprc Within 4 us after demagnetization is detected the MOSFET is forced to switch on PFC auxiliary sensing circuit Add a 5 kO series resistor to SNSAUXPFC to protect the internal circuit of the IC against excessive voltage for example during lightning surges In the PCB layout place this resistor close to the IC to prevent disturbances causing incorrect switching It is important to maint
86. is required to measure accurately the secondary voltage on the primary circuit side It is important that this winding has a good coupling with the secondary windings and a minimum coupling with the primary winding to obtain a good representation of the output voltage situation see Section 5 3 3 1 and Figure 6 Triple insulated wire can be used to meet the mains insulation requirements Principle of operation The voltage is sensed at the SNSOUT pin via an external rectifier and resistive divider Undervoltage is detected when Vsnsout drops under 2 35 V When detecting HBC output UVP the SSL4120 starts the protection timer by charging it with 100 pA When the undervoltage condition remains until the timer reaches the protection level the controller stops and then the restart timer restarts it At start up Vsnsout normally starts at a level lower than 2 35 V The timer setting must allow sufficient time for start up to charge Vsnsout to a value above 2 35 V preventing undesired protection during start up All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 74 of 102 NXP Semiconductors AN1 1 227 10 3 2 3 10 3 2 4 10 3 3 10 3 3 1 10 3 3 2 AN11227 SSL4120 resonant power supply control IC with PFC In applications where the SSL4120 is supplied from an auxiliary winding to SUPIC Vsupic monitoring ca
87. istics 53 SSHBC EN overview of sources clamps and levels iube ER oe ea eat rre 54 fsw HBc related to SSHBC EN voltage 56 OverCurrent Regulation HBC output OCR during start up 0 20 eee eee eee 57 Soft start reset and two speed soft start 58 SNSCURHBC functions 59 SNSCURHBC half bridge current measurement All information provided in this document is subject to legal disclaimers Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Fig 44 Fig 45 Fig 46 Fig 47 Fig 48 Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Fig 54 Fig 55 Fig 56 Fig 57 Fig 58 Fig 59 Fig 60 Fig 61 Fig 62 Fig 63 Fig 64 configurations 2000e0 eee 61 Principle of burst mode operation with Vsnsrp and comparator levels 2 62 Principle of burst mode operation with SNSFB and comparator levelS 63 Improved efficiency by HBC burst mode in a 250 W converter 000200 eee eee 64 Reduced losses by HBC burst mode in a 250 W converter a na anuau nananana 65 Increased efficiency at low output power in burst HBC and PFC 90 W converter 65 Remaining 90 W converter losses in burst mode 66 Simultaneous HBC and PFC burst mode operation including output voltage ripple 66 Vesusrea to Po characteristic examples 67 Normal mode output power characteristics Adapted for easy implementation of bur
88. ly The operating frequency is slowly increased until the resonant current value just reaches the preset value The behavior during OCR can be observed on VssupcyeN as a resultant regulation voltage When an OCR situation is present for a long time a serious fault condition is assumed During OCR the protection timer is activated The charging of the protection timer is active approximately a half period cycle after the 0 5 V level is exceeded If the detection levels are continuously exceeded the timer is charged continuously However if the detection levels are only exceeded occasionally the timer is charged as required Refer to Section 10 3 3 4 for details on charging and discharging of the protection timer The restart state is activated when Vncpnor reaches the protection level of 4 V Start up The overcurrent regulation is effective for limiting the output current during start up A smaller soft start capacitor can be chosen which allows faster start up The small soft start capacitor can result in an excessive output current but the OCR function can slow down the frequency sweep to keep the output current within the limits HBC overcurrent protection In most cases the HB OCR is able to keep the current under the set maximum values However HB OCR cannot be fast enough to limit the current for certain error conditions Half Bridge OverCurrent Protection HB OCP is implemented to protect against those error conditions The
89. mark The switching moments of GATEPFC and GATELS are independent in time The charging of SUPHS for GATEHS is synchronized in time with GATELS but has a different shape because of the bootstrap function Supply voltage for the output drivers SUPHS The high side driver is supplied by an external bootstrap buffer capacitor The bootstrap capacitor is connected between the high side reference pin HB and the high side driver supply input pin SUPHS While Vip is low an external diode from SUPREG charges this capacitor Selecting a suitable external diode minimizes the voltage drop between SUPREG and SUPHS This selection is especially important when using a MOSFET which needs a large amount of gate charge and or when switching at high frequencies Instead of using SUPREG as the power source for charging Csypys another supply Source can be used In such a construction it is important to check for correct start stop sequences and to prevent the voltage exceeding the maximum value of Vyp 14 V Remark The current taken from SUPREG to charge Vsupus differs for each cycle in time and shape from the current taken by the GATEPFC and GATELS drivers Initial charging of Csupus At start up the bootstrap function charges Csypys when GATELS is set HIGH to switch on the low side MOSFET While Csypys is being charged GATELS is switched on for charging and the PFC operation is started The time between start charging and start HBC operation is normally suff
90. mer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 14 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 97 of 102 NXP Semiconductors AN11227 15 Figures SSL4120 resonant power supply control IC with PFC Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 AN11227 SSL4120 basic application diagram 12 SSL4120 block diagram part 1 13 SSL4120 block diagram part 2 14 Basic overview internal IC supplies 15 Block diagram SUPIC and SUPREG start up with SUPHV and Tyugc auxiliary winding supply 18 Tupc auxiliary winding on primary side left and secondary side righ
91. mer noise rattle at start up or during burst mode operation The soft start slowly increases the primary peak current at the start of operation The soft stop function slowly decreases the transformer peak current before operation is stopped All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 38 of 102 NXP Semiconductors AN1 1 227 7 4 1 1 7 4 1 2 AN11227 7 4 2 7 5 SSL4120 resonant power supply control IC with PFC AZ ne 4 SNSCURPFC RSSPFC Il RCURPFC CssPFC L 001aal030 Fig 19 PFC soft start and soft stop set up Rssprec and a Cssprc between SNSCURPFC and Rcurprc set both functions Soft start Before start of operation an internal current source of 60 uA charges the capacitor to Vsnscurprc 60 uA x Rssprc When Vsnscurprc exceeds the internal start voltage of 0 5 V the operation is started Select Rssprc 12 KO to ensure that the start voltage level is reached At start up the current source is stopped and Vsnscurprc drops as Rssprc discharges Cssprc During this discharge each cycle s peak current increases until Cssprc is discharged completely and the normal peak current regulation level PFC OCR OCP is reached Rcurprc sets the PFC OCR OCP level The soft start period is calculated using Equation 14 Tsoft star PFC Rs
92. mit the voltage on this pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 76 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC Vaux THBC COMP HBC output OVP latched shutdown 5 SNSOUT COMP T Tr HBC output UVP protection timer 2 35 V COMP SUPREG 10 9 V Y hold HBC 14V 8 2kO COMP 1N4148 hold BEG 04V A 27k0 x 001aal060 Fig 51 Example of disabling the SSL4120 OVP function of SNSOUT 10 3 3 4 Both HBC output OVP and UVP disabled When OVP or UVP functionality is not required a fixed voltage between 2 35 V and 3 5 V can be applied to SNSOUT This fixed voltage is obtained from a resistive divider that is referenced to VsupnEc VsuPREG 10 9 V COMP Y HBC output OVP 3 5V 91 kO latched shutdown 5 SNSOUT COMP T T HBC output UVP 33kQ protection timer 2 35 V COMP hold HBC 11V COMP hold PFC 0 4 V 001aal061 Fig 52 Example of disabling both HBC output UVP and OVP functions of SNSOUT AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 77 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with
93. n also activate a protection when an error condition causes Vo to drop see Section 5 2 2 Severe voltage drop When Vawsour drops to a low voltage the hold HBC and hold PFC functions on this input pin stop the HBC and PFC Connecting external measurement circuits When restart protection is needed for other detection circuits it can be added on SNSOUT with a series diode HBC output OVP and UVP combinations Circuit configurations The following list contains examples of configurations for which certain functionality on the SNSOUT pin is disabled OVP enabled and UVP disabled see Section 10 3 3 2 UVP enabled and OVP disabled see Section 5 3 3 3 Both OVP and UVP disabled see Section 10 3 3 4 Remark In the examples given burst mode operation can still be implemented independent of the UVP and or OVP functionality HBC output OVP enabled and UVP disabled In some applications preventing the activation of UVP on SNSOUT by disabling UVP can be required for example LED drivers with current controlled output Disabling UVP can be realized by adding a circuit that prevents Vsnsout from dropping under 2 35 V As a practical example Vsnsout can be prevented from dropping under a preset voltage by adding an external low impedance resistive divider with a fixed voltage The resistive divider is connected to SNSOUT using a diode This simple circuit is not accurate but it does provide the basic capability to disable the UV
94. n of PFC 1 2 V and PFC HBC 2 2 V the IC is enabled The IC can be disabled by pulling down Vssypc en under 1 2 V The PFC controller stops switching immediately but the HBC continues until the low side stroke is active The pull down current must be larger than lou ssugc eN 42 HA PFC only active Only the HBC is disabled when VSSHBC EN is pulled under the Ven IC SSHBC EN 2 2V while keeping it above Ven prc ssHBC EN 1 2 V The low side power switch of the HBC is on when the HBC is disabled via the SSHBC EN pin HBC only active The SSL4120 is not designed to provide this operating mode but it can be realized by forcing a Vsnssoost higher than 2 63 V but under 5 V In this way the PFC output overvoltage protection is activated and PFC operation stopped The HBC operates because VsusBoosr exceeds its start level of 2 3 V boost UVP This operating mode is not likely to be required in an application but it is useful for starting up and debugging purposes during analyses or evaluation Hold and continue The SNSOUT function can be used to start and stop the PFC and HBC This method is intended for burst mode operation to switch off the converters for only a short time It is possible to operate only the HBC in burst mode or both HBC and PFC simultaneously The possibilities are similar to SSHBC EN with the main difference being that HBC continues without soft start see Section 9 1 Soft start HBC SSHBC EN provides the soft s
95. n the MOSFET when the transition of Vig has reached its end value It must not wait longer especially at high output load to prevent a swing back of Vps The adaptive non overlap function of the SSL4120 provides an automatic measurement and control function that decides when to switch on As it uses actual measurement input the control adapts for operation changes in time Because of this adaptive non overlap function it is not necessary to preset a fixed non overlap time which is always a compromise between different operating conditions The adaptive non overlap function senses the slope at Vug after one MOSFET has been switched off Normally the slope Vip starts directly Once the transition of the HB node is complete the slope ends The adaptive non overlap function detects the slope end and the other MOSFET is switched on As a result the non overlap time is automatically adjusted to the best value which provides the lowest switching loss Even if the Vig transition cannot be fully completed AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 45 of 102 NXP Semiconductors AN1 1 227 AN11227 8 3 2 SSL4120 resonant power supply control IC with PFC carens j ji lt gt lt ao a a cates if is Vboost 4 VHB
96. ndent protection functions are discussed 10 1 Protection overview Table 4 Overview of protection functions with links Part Symbol Protection Action Link IC SUPIC UVP SUPIC undervoltage protection SUPIC IC disable Section 5 2 2 IC SUPREG UVP SUPREG undervoltage protection IC disable Section 5 5 IC UVP supplies undervoltage protection supplies IC disable and reset IC SUPIC SCP SUPIC short circuit protection low HV start up current Section 5 2 2 IC HBC output OVP HBC overvoltage protection output IC shutdown Section 10 3 1 IC HBC output UVP HBC output undervoltage protection IC restart after protection time Section 10 3 2 IC IC OTP IC overtemperature protection IC disable Section 10 2 1 PFC PFC OCR PFC overcurrent regulation PFC switch off cycle by cycle Section 7 4 PFC mains UVP mains undervoltage protection PFC hold switching Section 7 6 1 PFC PFC boost OVP PFC boost overvoltage protection PFC hold switching Section 7 5 PFC PFC boost SCP PFC boost short circuit protection IC restart Section 7 2 2 HBC HBC boost UVP HBC boost undervoltage protection HBC disable Section 8 1 HBC HBC OLP HBC open loop protection IC restart after protection time Section 8 5 1 HBC HBC HFP HBC high frequency protection IC restart after protection time Section 8 4 4 HBC HBC OCR HBC overcurrent regulation HBC frequency increase Section 8 7 1 IC restart after protection time HBC HBC OCP HBC overcurrent protection HBC step to maximum frequency Section 8 7 2 HBC HBC CMR HB
97. nformation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 20 of 102 NXP Semiconductors AN1 1 227 AN11227 5 4 5 4 1 5 4 2 5 5 SSL4120 resonant power supply control IC with PFC hold HBC PFC for burst mode SUPIC supply by external voltage Start up When the SSL4120 is supplied by an external DC supply the SUPHV pin can remain unconnected The Vsupic start level is now 17 V When Vsupic exceeds 17 V the internal regulator is activated and charges SUPREG At Vsuprec 10 7 V GATELS is switched on for the bootstrap function to charge SUPHS And at the same time the PFC operation is internally enabled When all enable conditions are met the SSL4120 starts the PFC function When Vboost reaches approximately 90 96 VausBoosr 2 2 3 V of its nominal value the HBC starts Stop Operation of the SSL4120 can be stopped by switching off the external source for SUPIC When Vsupic drops under 15 V operation is stopped When shut down because of a triggered protection the state is reset by internal logic when Vsupic drops under 7 V SUPREG SUPIC has a wide voltage range for easy application SUPIC cannot be directly used to supply the internal MOSFET drivers because of this feature as the allowed gate voltage of many external MOSFETs would be exceeded The SSL4120 contains an integrated series stabilizer to avoid
98. ns enable level Vetart SNSMAINS 1 15 V e Vmains Stop level brownout Vstop sNSMAINS 0 9 V Vmains compensation for the PFC control loop gain bandwidth e Fast latch reset Vist snsmains 0 75 V The mains enable and mains stop level enable and disable the PFC Enabling and disabling of the resonant controller is based on Vsusaoosr Vsnsmains must be an averaged DC value representing Vmains Do not use the pin for sensing the Vmains phase Open pin detection is implemented as an internal current source 33 nA Sense input from an auxiliary winding of the PFC coil for demagnetization timing and valley detection to control the PFC switching It is 100 mV level with a time out of 50 us Connect the Tpcr auxiliary winding using an impedance to the pin to prevent damage of the input for example from lightning surges Recommended is a 5 1 kQ series resistor Open pin detection is implemented as an internal current source 33 nA Current sense input for PFC This input is used to limit the maximum peak current in the PFC core The PFCSENSE is a cycle by cycle protection The PFC MOSFET is switched off when Vsnscurpec reaches 0 5 V The internal logic controls a 60 uA internal current source connected to the pin This current source is used to implement a soft start and soft stop function for the PFC to prevent audible noise in burst mode The pin is also used to enable the PFC The PFC only starts when the internal current source
99. o prevent voltage overshoot and control the output power capability disable 1 SNSBOOST protection SNSMAINS 2 RCPROT timer itd as SNSAUXPFC SSHBC EN protection enable PFC and SNSCURPFC a zn 4 disable HBC start if neede 5 1 5 v DO 6 7 25 V DC ji DC Optional remove oe gt lt boost connection SUPE to high side MOSFET supply RUM I 001aal102 Fig 61 Start up debugging for PFC only Operational check without mains voltage Without mains input voltage by lowering the external Vsnsmains and VsnsgoosrT to under 2 5 V drive pulses can be observed on GATEPFC Lower voltages lead to a longer on time Under 0 89 V pulses stop because of SNSMAINS UVP and restarts when the level increases above 1 15 V All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 87 of 102 NXP Semiconductors AN11227 11 2 2 2 11 2 3 AN11227 SSL4120 resonant power supply control IC with PFC vOtORAMA 91758 5 ZOOS Zemon D V DOs cOsAmvowOu 10149 y lowering the external voltage on VsnspoostT and VSNSMAINS VGATEPFC VGATEPFC VGATEPFC n A n a 7 y p pm Bige OU t smt i 001aal103 Fig 62 Typical GATEPFC signals without mains voltage Operational check with mains voltage There is no simple step by step method of
100. ode 0 10 20 30 40 50 Po W Fig 40 Improved efficiency by HBC burst mode in a 250 W converter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 64 of 102 NXP Semiconductors AN1 1 22 AN11227 SSL4120 resonant power supply control IC with PFC 001aal051 with burst m normal mode with burst mode Po W Fig 41 Reduced losses by HBC burst mode in a 250 W converter 9 4 Advantages of burst mode for HBC and PFC simultaneously The SSL4120 provides a burst mode system that simultaneously switches the HBC and PFC In this way during the burst period the power is transferred directly from the input to the output The HBC determines the repetition time of the burst and the PFC follows During the burst period the PFC operates in normal regulation PFC bursting obtains extra reduction in power consumption Figure 42 to Figure 44 show examples of the results 100 001aal052 n 90 80 70 60 50 0 20 40 60 80 100 Po W Fig 42 Increased efficiency at low output power in burst HBC and PFC 90 W converter All information provided in this document is subject to legal disclaimers NXP B V 2012
101. ode detection PGND and SGND If the IC detects HB operation while there is zero input voltage it indicates that the connection between these pins at the IC is not present Gate currents lead to false HB slope detection SNSCURHBC Any disturbances on this pin voltage spikes can lead to an increase of fswiHBc while the measurement voltage signal is clean All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 86 of 102 NXP Semiconductors AN1 1 227 11 2 2 11 2 2 1 AN11227 SSL4120 resonant power supply control IC with PFC e SNSOUT Vsnsout must be between 2 35 V and 3 5 V for normal operation A voltage can be forced on pin SNSOUT to avoid protection But it is often related by a resistive divider to the SUPIC and is correct when SUPIC is supplied externally e RCPROT Several protection functions charges the timer capacitor Crcprot PFC only Keeping Vssupc eN under or forcing it to drop under 2 2 V can disable the HBC function A voltage higher than 1 2 V can enable the PFC function Applying an additional voltage from an external supply of approximately 1 5 V on SSHBC EN enables PFC only operation The set up is similar to the HBC only operation setup but for extra safety the Vpoost connection to the HBC high side switch can be disconnected In addition a small load can be connected on Vboost t
102. onant converter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 6 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 2 5 Protection features The SSL4120 provides several protection functions that combine detection with a response to solve the problem Regulating the frequency because of overpower or bad half bridge switching can solve the problem or keep the IC operating safely until it is stopped and restarted timer function 2 6 Typical applications Lighting LED drivers High power converters Slim converters AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 7 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 3 Pin overview with functional description Table 2 Pinning overview Pin Name 1 COMPPFC 2 SNSMAINS 3 SNSAUXPFC 4 SNSCURPFC 5 SNSOUT AN11227 Functional description Frequency compensation for the PFC control loop Externally connected filter with typical values 150 nF 33 KQ 470 nF and connected to Vmains using a capacitor to modulate the PFC on time Sense input for V mains Externally connected to resistive divided V mains This pin has four functions Vmai
103. open loop protection capacitive mode protection and a general purpose latched protection input In addition to the resonant controller the SSL4120 also contains a Power Factor Correction PFC controller Especially developed for Lighting applications that require low harmonic distortion of the mains current Efficient PFC operation is provided using functions such as e quasi resonant operation at high power levels e quasi resonant operation with valley skipping at lower power levels In addition the IC includes overcurrent protection overvoltage protection and demagnetization sensing ensures safe operation in all conditions The proprietary high voltage BCD Powerlogic process makes direct start up possible from the rectified universal mains voltage in an efficient way A second internal low voltage SOI die is used for accurate high speed protection functions and control The SSL4120 controlled PFC and resonant converter topology is flexible and enables a broad range of applications for wide input AC mains voltages 85 V to 305 V The combination of PFC and resonant controller in one IC makes the SSL4120 suitable for compact power supplies with a high level of integration and functionality All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 5 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply
104. oscillator signal determines the switch off moment The Vig sensing circuit determines the switch on moment As Vup sensing determines when to switch on the time between switching one MOSFET off and the other one on is adaptive Adaptive non overlap time or adaptive dead time has no influence on the oscillator signal The oscillator frequency control comprises time determination between the gate switch off moments including a small period in which the oscillator current is only 30 uA GATEHS l l GATELS Vboost VHB ITHBC 0 VCFMIN fee ee ee 30 uA period 001aal038 Fig 28 Timing overview of the oscillator and HBC drive 8 4 3 CFMIN and RFMAX 8 4 3 1 AN11227 This section explains the method of calculating the values for the Cermin and RgEMAx CFMIN minimum frequency setting Tost 2 X fsw HBC 25 lose 26 Ich tach A 26 AV 4 sc CFMIN V CFMIN T Vi CFMIN 3V IV 2V 27 T sels 150 uA 28 I _ min E 150 uA Ccrmin B 29 2x2 X fsw HBC min x AVosce cCFmMIN 8 X fsw HBC min All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 50 of 102 NXP Semiconductors AN11227 8 4 3 2 AN11227 8 4 4 SSL4120 resonant power supply control IC with PFC Example Requirement fsw HBC min 57 kHz 150 uA 0 00015 C RU ERN
105. ount of current from SUPREG is consumed by the MOSFET drivers GATELS GATEHS and GATEPFC Other circuit parts in the IC consume a maximum of 3 mA IsuPREG IC IsuPREG drivers IsUPREG external ISUPREG IC SUPREG drivers 4 MA max ISUPREG drivers iS estimated using the method provided in Section 5 5 5 An estimation by measurement While supplying the circuit from an external power supply the SUPIC current used can be assumed as a first approximation of how much SUPREG current the IC circuits draw An estimation can be made of the power available for external circuits using this value Remark The highest power consumption value is reached when the MOSFET drivers are switching at the highest frequency All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 26 of 102 NXP Semiconductors AN1 1 227 5 6 5 6 1 5 6 1 1 5 6 1 2 5 6 1 3 5 6 1 4 AN11227 SSL4120 resonant power supply control IC with PFC Example ISUPIC IC max measured 18 MA ISUPREG IC IsuPIC IC max measurea 18 MA IsuPREG extema 40 MA IsupREa c 40 mA 18 MA 22 mA Remark Vsuprec must remain above the undervoltage protection level of 10 3 V to maintain full functionality During start up high external current loads can lead to problems Value of the capacitors on SUPIC SUPREG and SUPHS Some practical ex
106. peaiesei suu Ily ZLOZ A 8 dXN O C208 1 5 nF R208 1000 L201 VBUS I D201 R201 C201 2 7 MQ I 2 2nF a SUPIC A R118 ne D202 R203 e 470 I bs VCC I uF P D204 48CTQO60 ea d Lon Paen I 470 uF T 470 uF T 470 uF I ZD201 30 V R215 VCC 1 5 kQ I C215 R237 220 R216 12kQ ik pF n c C213 R213 oko 47 nF 5 1 kQ l IC202 Il i SFH615 m R206 C206 C401 II 2 2nF IC203 22 nF TL341 5 1 KQ nF Fig 67 Example of a 250 W application with standby supply part 3 of 3 R218 10 kQ R219 10 kQ 5V Y R320 910 1 STBY 1C304 SFH610 001aal108 94d U 9 J043u09 Ajddns samod 1ueuosai Qz LESS ZoclLLNV SJOJONPUOSIWIIS dXN LZZLLNY 91ou uonesiddy ZLOZ 1 qQW AON ZZ AY SJOLUIE OSIP Jeba 0 joefqns s jueuunoop S14 ui PEPIAOI uoneuuojul y
107. ply control IC with PFC The requirements work towards a more resistive characteristic of the mains load and a low total harmonic distortion THD for lighting devices Measures are required regarding the input circuit of the power supply to fulfill these requirements Passive often a series coil or active often a boost converter circuits can be used to modify the mains load characteristics An additional market requirement for the added mains input circuit is that it works with a good efficiency and have a low cost Using a boost converter to meet these requirements provides the benefit of a fixed DC input voltage when combined with a resonant converter The fixed input voltage makes design of the resonant converter easier especially for wide mains input voltage range applications In addition the fixed input voltage makes it possible to obtain a higher efficiency SSL4120 resonant power supply control IC with PFC The SSL4120 integrates two controllers one for Power Factor Correction PFC and one for a half bridge resonant converter HBC It provides the drive function for the discrete MOSFET for the up converter and for the two discrete power MOSFETs in a resonant half bridge configuration The resonant controller part is a high voltage controller for a zero voltage switching LLC resonant converter The resonant controller includes a high voltage level shift circuit and several protection features such as overcurrent protection
108. protection activated All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 51 of 102 NXP Semiconductors AN1 1 227 8 5 AN11227 SSL4120 resonant power supply control IC with PFC The HFP senses Vprrmax This voltage indicates the actual operating frequency When the frequency is higher than approximately 75 of the frequency range Vrrmax 1 83 V the protection timer is started Remark During normal regulation the maximum frequency leads to only 60 of the present range and Vnreyax is 1 5 V maximum HBC feedback SNSFB A typical power supply application contains mains insulation in the HBC On the secondary mains insulated side the Vo is compared to a reference and amplified The SSL4120 is normally placed on the primary side The output of the error amplifier is transferred to the primary side via an OPTO coupler The output of the OPTO coupler on the primary side can be connected directly to SNSFB THBC 8 4V 3 2V CONTROL m 15 kO 001aal039 Fig 29 Typical basic SNSFB application The SNSFB pin supplies the OPTO coupler from an internal voltage source of 8 4 V via an internal series resistor of 1 5 kO This internal series resistance allows spike filtering by an external capacitor at the pin if needed The feedback input has a threshold current of 0 66 mA At this level
109. r detection SNSBOOST 9 8 MQ 001aal029 SPIKE FILTER x I 1 58V 1nF 62kQ PFC 45 nA SUPPLY onov SUPIC SCP Vstart SUPHV 25V SUPHV 25V 17V 22V IT UVP SUPIC 15V HV START UP SOURCE CONTROL ch off SUPHV 0 mA lch red sUPHV 1 1 mA Ich nom SUPHV 5 1 mA 10 9V 5 5 mA 4 reduced current enable supply 4 Oto gt 2V FREQUENCY CONTROL HBC K SSHBC EN tc m disable isi SUPREG SUPREG start startlevel 10 7 V SUPREG UVP CSUPREG stoplevel 10 3 V n t 001aal064 aaa 004789 Fig 2 SSL4120 block diagram part 1 AN11227 All information provided in this document is subject to legal disclaimers Rev 1 27 November 2012 NXP B V 2012 All rights reserved 13 of 102 Application note NXP Semiconductors AN11227 SSL4120 resonant power supply control IC with PFC
110. rce All internal circuits are directly or indirectly via SUPREG supplied from this pin except for the high voltage circuit The buffer capacitor on SUPIC can be charged in several ways Internal High Voltage HV start up source e Tuc auxiliary winding supply or capacitive supply from switching half bridge node e External DC supply for example a standby supply The IC enables operation when Vgypic reaches the 22 V for HV start or 17 V for external supply start level It stops operation under 15 V and a shutdown reset is activated at 7 V Gate driver output for PFC MOSFET Power ground Reference ground for HBC low side and PFC driver Output of the internal regulator 10 9 V Internal IC functions such as the MOSFET drivers use this supply It can also be used to supply an external circuit SUPREG can provide a minimum of 40 mA SUPREG becomes operational after Vsupic has reached its start level The IC starts full operation when Vsupreg has reached 10 7 V SUPREG UVP If Vsuprec drops under 10 3 V after start the IC stops operating and the current from SUPIC is limited to 5 4 mA to allow recovery Gate driver output for low side MOSFET of HBC Not connected high voltage spacer High voltage supply input for internal HV start up source In a standalone power supply application this pin is connected to the boost voltage Vpoost SUPIC and SUPREG are charged with a constant current by the internal start up source SUPHV
111. rent load on SUPHS 24 Lower voltage on SUPHS 25 SUPREG power consumed by the MOSFET drlVerS nior Rp EP e exce rey wi 25 GATELS and GATEHS driving a total of two MOSFETs 0 000 e cece ees 26 GATEPFG sretala riiai tree EU eats 26 SUPREG supply voltage for other circuits 26 Current available for supplying an external circuit from SUPREG 26 An estimation by measurement 26 Value of the capacitors on SUPIC SUPREG and SUPHS 0000s eee eens 27 Value of Csupic cre eee eee ee ee 27 General Jis rede Pose S eee weeds 27 StartUp ie cices Re eee aes 27 Normal operation 2 27 Burst mode operation 27 Value of CsupReG eee eee eee eee 28 Value of CsupHs Corer Ce eee ee ee re ee ee 28 MOSFET drivers GATEPFC GATELS and GATES ses rok ehm ath mnn in mans 29 GATEPFG 2 pg seo eee Y Rer iS 29 GATELS and GATEHS 4 29 Supply voltage and power consumption 29 General subjects on MOSFET drivers 30 Swilch ON ese nk pad bo ee ode S 30 Switch off nanana aaan 000 cee eee 30 Specifications 2 0000 eee 31 Mutual disturbance of PFC and HBC 32 PFC functions Lulsueesee 33 PFC output power and voltage control 33 PFC regulation 000000 34 Sensing Vooost eseri sedes wrier te eee 34 SNSBOOST open and short circuit pin detection 00 ute Eaa E a 3
112. rent source is stopped and Rpcpnor discharges Cpcpnor If error condition ends before 4 V has been reached the current source is stopped the pin discharges through Rgcpnor No further actions are taken If the error condition is permanent the system fluctuates between stop and restart The following events activate the protection timer OCR using the SNSCURHBC pin HFP using the RFMAX pin OLP using the SNSFB pin UVP using the SNSOUT pin The activation of protection and restart can be forced by increasing Vacprot above 4 V but not higher than 12 V using an external circuit RCPROT working as a restart timer During certain error conditions it can be required to disable the IC temporarily This feature is especially useful when an error can overheat components A temporary disable allows power supply components to cool down after which the IC must automatically restart The restart timer determines the time to restart long error error no error 4V VRCPROT 0 V V 5 0 restart trigger 4 C t 001 aal064 Fig 55 RCPROT operating as a restart timer Normally Cacprot is discharged to 0 V but when a restart is requested a 2 2 mA current quickly charges Cpcpnor until it reaches the 4 V upper switching level After this the RCPROT pin current becomes zero and Rpcpnor discharges Cncpnor The restart time is triggered when the 0 5 V lower switching level has been reached
113. resent during low loads and is the dominant energy during burst mode Switching the converter sequences on and off continuously at a certain speed and duration can lead to audible noise The main mechanism for producing noise is the interruption of magnetization current sequences leading to a mechanical force This interruption is especially the case on the core of the resonant transformer which starts acting as a loudspeaker When burst mode is applied during higher output power conditions the converted energy also contributes and leads to an increased risk of audible noise Measurements in the resonant transformer construction It is necessary to adapt the mechanical transformer construction to prevent problems with audible noise under specific conditions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 68 of 102 NXP Semiconductors AN1 1 22 AN11227 9 8 2 9 9 SSL4120 resonant power supply control IC with PFC One measure is to adhere the core parts to each other using a material with damping vibration absorbing properties A combination can be made with the air gap construction Other vibration damping measures can also help when audible noise is a critical issue for a product 001aal056 1 Left hand transformer with glue to reduce audible noise 2 Right hand transformer has standard construction
114. resonant power supply control IC with PFC 001aal055 001aal097 6 2 200 VSNSFB fsw HBC V kHz 5 6 160 Vburst 25V 4 8 120 4 0 80 20 40 60 80 100 0 20 40 60 80 100 Po W Po W Vsnsrp as a function of Po fsw HBC as a function of Po Fig 46 Normal mode output power characteristics Adapted for easy implementation of burst mode comparator level detection AN11227 9 7 9 8 9 8 1 Reduced Vsypus during burst During the idle time Csupus is not charged During normal operation each time the half bridge node HB is switched to ground level the bootstrap function of the external diode between SUPHS and SUPREG charges Csupus In burst mode there are periods of non switching and therefore no charging of Csupus During this time the circuit supplied using SUPHS slowly discharges Csypus When a new burst starts Vsupus is lower than in normal operation During the first switching cycles Csypus is recharged to its normal level It is important that during these first recharge cycles Vsuprec does not drop under the protection level of 10 3 V Audible noise As the burst mode is normally used when the output power is low the converted energy does not contribute much to generate audible noise The magnetization current however is still p
115. responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN11227 All information provided in this document is subject to legal disclaimers design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation p
116. rmal operation Initially the stored energy in the SUPIC capacitor delivers the SUPIC current After a short time the supply source on SUPIC takes over 5 3 SUPIC using the Tygc auxiliary winding supply 5 3 1 Start up by Vsupuv In a standalone power supply application the IC can be started using a high voltage source rectified mains voltage when the SUPHV high voltage input is connected to Vpoost PFC output voltage The internal HV start up source which delivers a constant current from SUPHV to SUPIC charges the SUPIC and SUPREG SUPHV is operational at a voltage 25 V When Vsupic is under the short circuit protection level 0 65 V the current from SUPHV is low 1 1 mA This feature limits the dissipation in the HV start up source when SUPIC is shorted to ground During normal conditions Vsupic quickly exceeds the protection level and the HV start up source switches to normal current 5 1 mA The HV start up source switches off when Vsupic has reached the start level 22 V The current consumption from SUPHV is low 7 uA when switched off When Vsupic has reached the start level 22 V SUPREG is charged When VsupnEc reaches the level of 10 7 V it enables operation of HBC and PFC The Typc auxiliary winding supply must take over the supply of SUPIC before it discharges to the SUPIC undervoltage stop level 15 V All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights re
117. roducts This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by custo
118. ruction Triple insulated wire is needed when the Typc auxiliary winding is placed on the transformer construction secondary area AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 18 of 102 NXP Semiconductors AN1 1 227 5 3 3 1 5 3 3 2 AN11227 SSL4120 resonant power supply control IC with PFC 001aal019 Fig 6 Tygc auxiliary winding on primary side left and secondary side right SUPIC and SNSOUT using Tygc auxiliary winding The SNSOUT input provides a combination of four functions e HBC output OVP Vausour gt 3 5 V latched e HBC output UOP Vsnsout lt 2 35 V protection timer e Hold HBC Vsnsout lt 1 1 V stop switching HBC burst mode e Hold HBC and PFC Vsnsout lt 0 4 V stop switching HBC and PFC for burst mode Remark A more detailed explanation of the SNSOUT functions can be found in Section 10 3 1 and Section 10 3 2 Often a circuit is used which combines SUPIC and output voltage monitoring using SNSOUT with one Typc auxiliary winding But an independent construction for SUPIC and SNSOUT is also possible This construction can be used in a situation where SUPIC is supplied by a separate standby supply and the T gc auxiliary winding is used only for output voltage sensing It is also possible not to use SNSOUT for output sensing but as a general purpose protection inp
119. s at SUPREG in combination with an external DC supply for SUPIC the dissipation reduces in the series stabilizer In principle SUPREG can only source current The drivers of GATELS and GATEPFC are supplied using Vsuprec and draw current from it during operation depending on the operating condition Some change in value can be expected due to current load and temperature 10 925 001aal002 41 00 001aal021 VsuUPREG VSUPREG V V 10 95 10 915 10 90 10 905 pie 10 85 10 895 Vsupic 20 V 10 80 10 885 10 75 0 20 40 60 50 0 50 100 150 ISUPREG load mA Temperature C Fig 8 Typical Vsuprec characteristics for load and temperature AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 22 of 102 NXP Semiconductors AN1 1 227 5 5 1 5 5 2 5 5 3 AN11227 SSL4120 resonant power supply control IC with PFC Block diagram of SUPREG regulator SUPHV current SUPIC Vaux THBC source 11V i reduced current SupReg SUPREG SUPREG start CSUPREG gt 10 7 V T SUPREG UVP lt 10 3 V 001aal022 Eos V Fig 9 Block diagram of internal SUPREG regulator SUPREG during start up SUPREG is supplied by SUPIC SUPIC is the unregulated ext
120. same value A typical resistor value of 2 MQ can be applied for R1and R2 to keep the bleeder loss low The average voltage sensed is calculated as follows All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 40 of 102 NXP Semiconductors AN1 1 227 7 6 2 SSL4120 resonant power supply control IC with PFC 242 V mains avg Um i V nains RMS 16 The SNSMAINS brownout protection RMS voltage level is calculated with Equation 17 _ RI x R2 17 RI R2 T R R3 Vbo mains 2 25 X Vuvp SNSMAINS X 1 18 Example Required Vbo mains 66 V AC with Vuvp SNsMAINs 0 89 V R1 R2 2 MQ gt Ry 1 MQ V 2 x x 0 89 um 1 19 f x x U x bo mains 2 2 R4 66 1 9771 x DOLES RS 1 20 R3 560 KQ R4 47 KQ The time constant for a recommended time constant of 150 ms with C4 3300 nF SNSMAINS R4 x C4 47 kQ x 3300 nF 155 ms Discharging the mains input capacitor There is often an application requirement to discharge the X capacitors in the EMC input filter within a certain time The replacement values of R1 R2 R3 and R4 determine the resistance required for discharging the X capacitors in the input filter The replacement value can be calculated with Equation 21 R2 x R3 R4 R R 21 dch R2 R3 R4 Example Required tach lt 600 ms with
121. se send an email to salesaddresses nxp com Date of release 27 November 2012 Document identifier AN11227
122. seby capacitive mode protection regulation mode protection regulation notice voltage drop on VssuBC EN 001aal036 Oscilloscope traces contain normal time base top and zoomed view bottom Fig 26 Typical protection and regulation behavior in capacitive mode during bad start up AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 48 of 102 NXP Semiconductors AN1 1 227 AN11227 8 4 8 4 1 8 4 2 SSL4120 resonant power supply control IC with PFC HBC oscillator The slope controlled oscillator determines fgwHBc The oscillator generates a triangular voltage waveform at the external Cermin on the pin Presets Two external components determine the frequency range CcrMIN Sets the minimum frequency in combination with an internally trimmed current source e Rremax Sets the frequency range and in combination with Cermin the maximum frequency The oscillator frequency depends on the charge and discharge current of Cermin The charge and discharge current consists of a fixed part which determines fmin HBc In addition a variable part which depends on the Rearmax value and Varmax Vremax is 0 V when the oscillator frequency is minimum e Vremax is 2 5 V when the oscillator frequency is maximum e The value of Rarmax determines the relationship between Varmax and the frequency It also d
123. served Application note Rev 1 27 November 2012 17 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 5 3 2 Block diagram for SUPIC start up 5 5 mA O reduced is current Jg 0 65 V SUPIC SCP HV START UP SOURCE CONTROL Ich off SUPHV 0 MA enable SUPREG Ich red SUPHV 1 1 mA Ich nom SUPHV 5 1 mA SUPREG SUPHV present SUPREG start CSUPREG 10 7 V Vstart SUPHC gt 25 V 22 V Vstart SUPHC lt 25 v 22V c L P SUPREG UVP Vstart SUPHC lt 15 V f 13v mus Fig 5 Block diagram SUPIC and SUPREG start up with SUPHV and Tygc auxiliary winding supply 5 3 3 Auxiliary winding on the HBC transformer A Tupc auxiliary winding can be used to obtain a supply voltage for SUPIC during operation As SUPIC has a wide operational voltage range 15 V to 38 V itis not a critical parameter for constant voltage outputs But Vsupic must be low for low power consumption The Tugc auxiliary winding supply must be an accurate representation of Vo to use the auxiliary winding voltage for the IC supply and HBC output voltage measurement using SNSOUT Physically place the Tupc auxiliary winding on the secondary output side to ensure a good coupling When mains insulation is included in Typc it can affect the auxiliary winding const
124. specified to show the capability of the internal driver The simplified model in Figure 14 demonstrates that the charge and discharge current values are dependent on the conditions of the supply and gate voltages The value of the source current is highest when the supply voltage is highest and the gate voltage 0 V The value of the sink current is highest when the gate voltage is highest Table 3 PFC and HBC driver specifications Symbol PFC driver pin GATEPFC Isource GATEPFC Isink GATEPFC Isource GATEHS Isource GATELS Isink G ATEHS Isink GATELS Parameter Conditions Min Typ Max Unit source current on pin GATEPFC VoaTeprc 2 V 0 5 A sink current on pin GATEPFC VaaTeprc 2 V 0 7 A VaarEPrG 10 V 1 2 A HBC high side and low side driver pins GATEHS and GATELS source current on pin GATEHS Veateus Vop 4 V 310 mA source current on pin GATELS VaarELS VPaNp 4 V 310 mA sink current on pin GATEHS VoaTeHs Vug 2 V 560 mA VoaTeHs Vupg 11 V 1 9 A sink current on pin GATELS VaarELS VPaNp 2 V 560 mA VaareLs Veanp 11 V I 1 9 s A AN11227 The supply voltage from SUPREG to GATEPFC and GATELS is constant at 10 9 V The supply voltage for GATEHS is lower and depends on the operating conditions see Section 5 5 4 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1
125. sprc Cssprc 14 Soft stop Soft stop is achieved by switching on the internal current source of 60 uA again The current charges Cssprc and the increasing capacitor voltage decreases the peak current When Vsnscurprc reaches 0 5 V the operation is stopped VaNscunpro is only measured during the off time of the PFC power switch to prevent measurement disturbances during soft stop SNSCURPFC open and short protection When the SNSCURPFC pin is open SNSCURPFC is charged to 0 5 V by the internal current source of 60 LA for soft start The PFC does not start switching because of OCP When the SNSCURPFC pin is short circuit to ground the PFC cannot start operation as the start level of 0 5 V has not been reached PFC boost OverVoltage Protection OVP An overvoltage protection circuit is built in to prevent boost overvoltage during load steps and mains transients When Vsuspoosr exceeds 2 63 V the switching of the power factor All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 39 of 102 NXP Semiconductors AN1 1 227 AN11227 7 6 7 6 1 SSL4120 resonant power supply control IC with PFC correction circuit is stopped The PFC resumes switching when Vsnssoost drops under 2 63 V When the resistor between pin SNSBOOST and ground is open OVP also triggers In this situation the internal current source of 45 nA incre
126. st mode comparator level detection 68 Transformer construction 69 Example of longer burst time for PFC using ramp on SNSOUT 2 2 2 00000 e eee 70 SNSOUT protection 005 73 Example of disabling HBC output UVP function of SNSOUT 0 00002 76 Example of disabling the SSL4120 OVP function OP SNSOUT rier ta oia ne ke eee eee 77 Example of disabling both HBC output UVP and OVP functions of SNSOUT 77 Block diagram of the RCPROT function 78 RCPROT protection timer operation 78 RCPROT operating as a restart timer 79 Gounding structure and current loops GATEPFC and GATELS 205 81 Grounding layout example with star point at the boost capacitor 2 200 0005 82 PCB layout of the SGND PGND CFMIN RFMAX and SNSCURHBC pins 83 HBC only start up and debugging step by step 85 Typical signals during a separate HBC start up for an increase in Vpoost 86 Start up debugging for PFC only 87 Typical GATEPFC signals without mains Voltage eom Ped wns ae eee beet 88 Example of a basic test setup on a single low voltage supply 24 V 0 00002 cee eee 90 Example of a basic IC evaluation and test set up with a high bus voltage 91 continued gt gt NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 98 of 102
127. stor is important for avoiding disturbance pick up Also avoid capacitive coupling between the connection to pin 17 and the HB track to pin 15 that contains high dV dt signals CFMIN pin 19 and RFMAX pin 20 Connect the oscillator capacitor on Ccryin from pin 19 to SGND pin 18 with short tracks to prevent pickup of disturbances by an external field Although less critical a similar construction can be used for RnEMAx All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 82 of 102 NXP Semiconductors AN1 1 221 SSL4120 resonant power supply control IC with PFC SNSFB 21 SUPHS 14 GATEHS 13 SSHBC EN 22 SNSBOOST 24 2 SNSMAINS 3 SNSAUXPFC 1 GOMPPFC 10 GATELS aaa 005151 Fig 58 PCB layout of the SGND PGND CFMIN RFMAX and SNSCURHBC pins 11 1 5 3 SNSBOOST pin AN11227 Connect the resistor and capacitor on SNSBOOST pin to the SGND pin with short tracks to prevent pickup of disturbances by an external field Starting debugging partial circuits When starting a newly built application for the first time or when an error is observed during operation it is possible to activate circuit parts step by step This function enables errors to be located more easily and an evaluation can be performed under conditions that restrict the influences from oth
128. t 04 19 Position the Tugc auxiliary winding for good output coupling 2 200 eae 20 Typical Vsupreg characteristics for load and temperature ee cce ne 22 Block diagram of internal SUPREG regulator 23 Simplified model of MOSFET drive 23 Typical application of SUPHS 25 GATELS and GATEHS drivers 29 Gate circuits examples lusus 30 Simplified model of a MOSFET drive 31 PFC output regulation example SNSBOOST 34 Basic PFC voltage control loop with PFCCOMP and on time modulation 35 Relationship between on time Vsnsmains and VcomPPFC UT 36 PFC demagnetization and valley sensing 37 PFC soft start and soft stop set up 39 SNSMAINS circuitry llle 40 SNSMAINS and COMPFC circuitry with THD improvement sseseeeee ene 42 Inductive mode HBC switching 45 Adaptive non overlap switching during normal operating conditions 46 Capacitive mode HBC switching 47 Capacitive Inductive HBC operating frequencies 48 Typical protection and regulation behavior in capacitive mode during bad start up 48 Frequency relationships 49 Timing overview of the oscillator and HBC drive 50 Typical basic SNSFB application 52 SNSFB V I characteristics 53 Examples of Vsnsrp to Po character
129. t customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are
130. tances PFC frequency limit fsw PFC is limited to 380 kHz to minimize the switching losses If the frequency for quasi resonant operation is above the 380 kHz limit the system switches over to Discontinuous conduction mode The PFC MOSFET is only switched on at a minimum voltage across the switch valley switching One or more valleys are skipped when necessary to keep fsw pec under 380 kHz valley skipping The maximum off time is limited to 50 us after the last PFC gate signal to ensure proper control of the PFC MOSFET under all circumstances PFC OverCurrent Regulation and Protection PFC OCR OCP The maximum peak current which switched using the external MOSFET is limited cycle by cycle by sensing the voltage across a measurement resistor Rcuynpec The SNSCURPFC pin measures the voltage which is limited to 0 5 V At this voltage level the MOSFET is switched off Take a small voltage margin into account to avoid false triggering of the PFC OCR RcunPrc can be calculated with Equation 13 Vocn PFO T V i 0 52 V 0 1 V R margin 48 Q 13 ia TL PFC max 8 73 A Vsnscurpec senses an initial voltage peak at the moment the PFC MOSFET switches on because its parasitic capacitances are discharged SNSCURPFC has a leading edge blanking of 310 ns to mask this event so it does not react to this initial peak PFC soft start and soft stop The PFC has a soft start function and a soft stop function to prevent transfor
131. tart function for the resonant converter The relationship between fsw Hgc and output current power is not constant It is highly dependent on the Vo and Vboost voltage and the relationship can be complex The SSL4120 has a soft start function to ensure that the resonant converter starts or restarts with safe HBC currents The soft start function forces a start at high HBC frequency so that currents are acceptable in all conditions The soft start slowly decreases fgw HBc until the output voltage regulation has taken over the frequency control The limitation of the output current during start up also limits the output voltage rise and prevents an overshoot During soft start in parallel to the soft start frequency sweep the SNSCURHBC function monitors the primary current and can activate regulation OCR in a temporary overpower situation All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 55 of 102 NXP Semiconductors AN1 1 227 AN11227 8 6 2 1 8 6 2 2 SSL4120 resonant power supply control IC with PFC The soft start uses Vssupc en as an input Cesupc ew sets the timing duration of the soft start event As VssupoyeEN IS also used as enable input the soft start functionality is above the enable related voltage levels see Figure 33 Soft start voltage levels VRFMAX fsw HBC flimit HBC Vtm
132. ternal series resistor Rsuscunugo The current measurement resistor Rcyrusc and the series resistance Rsuscunuagc 1 KO typ provides the total series resistance Signal ground reference for IC All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 9 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC Table 2 Pinning overview continued Pin Name 19 CFMIN 20 RFMAX 21 SNSFB AN11227 Functional description HBC oscillator pin The value of the external capacitor determines the minimum switching frequency of the HBC In combination with Rermax it sets the operating frequency range A triangular voltage waveform is generated Ccrmin VicrMin 1 V and Vu creMiN 3 V to facilitate switching timing A fixed minimum charge discharging current of 150 uA determines the minimum frequency During special conditions the charge discharging current is reduced to 30 uA to slow down the charging temporarily An internal function limits the operating frequency to 670 kHz HBC oscillator frequency pin The value of the resistor Rremax connected between this pin and ground determines the frequency range Both the minimum and maximum frequencies of the HBC are preset Ccrmin sets the minimum frequency The absolute maximum frequency is internally limited to 670 kHz In addition to the 150
133. the soft start reset and the two speed frequency downward sweep Protection om l off 8v 5 6 V VSSHBC EN 3 2V 0 fmax HBC fsw HBC NER S cC OMEN fmin HBC 7 0 t m regulation gt a max fast slow sweep cals regulation forced sweep 001 aal045 Fig 35 Soft start reset and two speed soft start The soft start reset is also used to ensure a safe start up at maximum frequency fsoft start HBc When the HBC is enabled using SSHBC EN or after a restart The soft start reset is not used when the operation has been stopped for burst mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 58 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC 8 7 HBC overcurrent protection and regulation Measurement of the primary resonant current indicates the level of output power that the converter generates During a fault or output overload condition this current often increases considerable By monitoring this current and then taking appropriate action the converter can remain operational during a temporary fault or overload condition The resonant controller of the SSL4120 has two functions when in an overcurrent condition Half Bridge OverCurrent Regulation HB OCR slowly increases fsw Hg
134. this issue and to create a few other benefits The series stabilizer generates an accurate regulated voltage on CsupREG This stabilized Vsuprec is used for Supply of internal PFC driver Supply of internal low side HBC driver Supply of internal high side driver via external components Reference voltage for optional external circuits The series stabilizer for SUPREG is enabled after SUPIC has been charged In this way optional external circuitry at SUPREG does not consume from the start up current during the charging of SUPIC Caupic acts as a buffer at charge of SUPREG and start up of the IC VsupreG must reach Vetart SuPREG before the IC starts operating to ensure that the external MOSFETs receive sufficient gate drive if Vsypic is also above its start level All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 21 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC The SUPREG has an UnderVoltage Protection When Vsuprec drops under the 10 3 V two actions take place The IC stops operating to prevent unreliable switching due to too low gate driver voltage The PFC controller stops switching immediately but the HBC continues until the low side stroke is active The maximum current from the internal SUPREG series stabilizer is reduced to 5 4 mA If an overload occur
135. tion provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 61 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC 9 Burst mode operation AN11227 In dimmable LED driver applications with current controlled output the burst mode operation can be used to reach low output currents Burst mode can also be used to improve efficiency at low output loads By temporarily interrupting the switching losses during idle time are minimized Because the average power needed at the output is low it is easy for the converter to deliver it during a short conversion time a burst The burst mode operation of the SSL4120 is based on interrupting the switching while maintaining regulation With an external comparator the regulation Vsnsrg can be monitored to determine when to stop and start switching Stopping and starting again can be controlled via the SNSOUT pin When starting again after interruption no soft start is applied as the system is still in regulation close to the regular working point The regulation loop of the system normally by the output voltage or current determines the timing of burst switching on and off In this way a small ripple on the output voltage current is deliberately created during burst mode Po N A normal operation hold burst hold burst normal operation VHB
136. tive mode is detected when the Vip slope does not start shortly 690 ns after the MOSFET is switched off At detection of capacitive mode fsw HBc is increased quickly Discharging Cssugc ew With a high current 1800 A from the moment tno slope 690 ns has passed before the half bridge slope starts to increase fgwHBc The resulting fsw HBC increase regulates the HBC back to the border between Capacitive mode and Inductive mode AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 47 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC resistive i aVo a capactive 7 inductive Vboost Qmax Mmax Vboost min Mnom Vboost nom load independent point 4 series resonance Mmin Vboost max Qnom Amin fO fl fr fmax fsw HBC 001aal035 Fig 25 Capacitive Inductive HBC operating frequencies The typical slowing of the oscillator in combination with the discharging of Cssypc en can identify a CMR in the SSL4120 H OH 19 1 z l 5 00 Uto VSNSCURHBC me i 2 00 Ualio UC 1 20MHz CHS 10 1 0 500 Uvdiv DC 1 28MHz CHA 10 1 0 100kVsdiv lt Full SONS T HAN WIN W A A i Wi ill 1j MT MW Edge f Single 9 90 U Typical behavior at capacitive Frequency increa
137. using a soft stop The HBC is already paused Above this level the PFC resumes operation with a soft start Keep the PFC always active for better THD and Power Factor for dimmable lighting applications Diode D1 in Figure 39 ensures that the PFC is not using burst mode A 100 pA current from the SNSOUT pin keeps the voltage at a 1 5 V internal clamp voltage which is above both burst mode levels This function avoids burst mode activation when the output voltage is not yet present The impedance between the SNSOUT pin and ground must therefore be larger than 20 kO External comparator for burst mode implementation A comparator circuit between SNSFB and SNSOUT can do the implementation of the burst mode Vaux THBC COMP HBC output OVP 3 5V latched shutdown Li 5 SNSOUT COMP 1 t1 HBC output UVP protection timer 2 35 V i SUPREG I i COMP l l Y D1 l i hold HBC 14V BURST TT n i l Q1 I MODE l COME FUNCTION burst l I hold PFC lt m L Rhys M i l i hys H I i al l m m m m m e m e e e e e e e e QD oue o o e o o e o e m a l Ol 7 3 MA IC 8v 32V 3 1 5 kQ CONTROL J aaa 004793 Fig 39 Principle of burst mode operation with SNSFB and comparator levels AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012
138. ut See Section 10 3 3 for more information In a combined SUPIC and SNSOUT function using one Typc auxiliary winding some issues must be addressed to get a good output voltage representation for SNSOUT measurement The advantage of a good coupling representation of the Tugc auxiliary winding with the output windings is also that a stable auxiliary voltage is obtained for SUPIC A low SUPIC voltage value can be designed more easily for lowest power consumption Auxiliary supply voltage variations by output current At high peak current loads the voltage drop across the series components of the HBC output stage resistance and diodes is compensated using regulation The compensation results in a larger voltage on the windings at higher output currents because of the higher currents which cause an increased voltage drop across the series components The Typo auxiliary winding supply shows that this variation is caused due to the HBC output All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 19 of 102 NXP Semiconductors AN1 1 2217 SSL4120 resonant power supply control IC with PFC 5 3 3 3 Voltage variations by auxiliary winding position primary side component Due to a less optimal position of the auxiliary winding Vsnsout and or SUPIC can contain a certain amount of undesired primary voltage component This component can
139. v 1 27 November 2012 60 of 102 NXP Semiconductors AN1 1 227 AN11227 SSL4120 resonant power supply control IC with PFC The amplitude of the current is linearly dependent on Vpoost At Vboost nom the current is zero and the voltage across is also present on the SNSCURHBC pin At the Vboost start level Vsnspoost 1 8 V and the current is maximum 170 pA The direction of the current sink or source depends on the active gate signal The voltage across RsnscurHBc reduces the amplitude of Vsnscurnsc resulting in a higher effective current protection level The value of Rsnscurnusc sets the amount of compensation 8 7 4 Current measurement circuits Vboost Vboost ee E jy C 1inF denon 47 SNSCURHBC i 47 SNSCURHBC RSNSCURHBC RSNSCURHBC lres 1kQ0 1kO Ore RCURHBC 0 02 Ires RCURHBC 001aal047 Fig 37 SNSCURHBC half bridge current measurement configurations 8 7 5 SNSCURHBC layout As SNSCURHBC must be able to cycle by cycle sense the measurement signal at higher frequencies it is easily influenced by disturbances Place Rsnscurusc close to the IC to reduce the length of the PCB track that can pick up interfering signals This placement prevents interference on this input As the impedance of Rcyrusc is normally low the PCB track between RsnscurHsc and Rcurusc is not critical regarding disturbance All informa
140. with limited interference from the total system AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 89 of 102 NXP Semiconductors AN11227 SSL4120 resonant power supply control IC with PFC external supply 0a SUPIC lt external supply ce ae 2kO0 T 4 7 kQ n SUPIC J 200 Q i ON OFF 22 KQ 47 KQ regulates to 2 5 V I SOME SNSBOOST 27k0 47nF SUPIC 470 nF 33kQ 150 nF Y L L 22 KQ L I SNSMAINS RCPROT SUPIC 3 M 2 7 KQ 1 pF 330 kQ 2000 m I W 500 pr P SNSAUXPFC SSHBC EN Bd 47 nF all off BS170 2200 uH de L SNSCURPFC SNSFB 1kQ 56nF t5kQ 4 m zn SNSOUT RFMAX 24k0 Fa 47nF 24KO iso n SUPIC c SUPIC CFMIN 4 7 pF 560 pF GATEPFC SGND 560 pF PGND SNSCURHBC 1kQ SUPREG nic 470 nF GATELS HB I 330 nF SUPIC n c suPus PYV27400 M T 100 pF SUPHV GATEHS 100 pH 04N60C3 1uF 470pF 40 04N60C3 001aal104 Fig 63 Example of a basic test setup on a single low voltage supply 24 V All information provided in this document is subject to legal
141. xternal circuit to the gate Because the timing for switching off the MOSFET is more critical than switching it on the internal driver can sink more current than it can source At higher frequencies and or short on time timing becomes more critical for correct switching Sometimes a compromise is made between fast switching and EMI effects A gate circuit between the driver output and the gate can be used to optimize the switching behavior GATEPFC GATEPFC t GATEPFC i GATEPFC C b d Lm Fig 13 Gate circuits examples 001aal025 Switching on and off the MOSFETS using the drivers can be modeled by alternating charge and discharge of a gate source MOSFET capacitance through a resistor Rpson of the internal gate driver AN11227 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 27 November 2012 30 of 102 NXP Semiconductors AN1 1 227 SSL4120 resonant power supply control IC with PFC SUPREG EXTERNAL GATE CIRCUIT Ces T Ves 001aal023 Fig 14 Simplified model of a MOSFET drive 6 5 Specifications The main function of the internal gate drivers is to source current and sink current to switch on and off the external MOSFET switch The amount of current that can be sunk and sourced is
142. z limit is high enough to reach low harmonic distortion of the mains input current as required by lighting devices The PFC is designed as a boost converter with a fixed output voltage An advantage of a fixed boost is that the HBC can be designed to a high input voltage which makes the HBC design easier Another advantage of the fixed boost is the possibility to use a smaller boost capacitor Cboost Value or to have a significant longer hold up time In the SSL4120 system the PFC is always active The PFC is switched on first when the mains voltage is present The HBC is switched on after the Cpoost is charged to approximately 90 96 of its normal value The system can be operated in burst mode for improved efficiency at low output loads During this mode the HBC determines the on off sequences and the PFC can be made to burst simultaneously for even better efficiency results PFC output power and voltage control The PFC of the SSL4120 is ton controlled and therefore it is not necessary to measure the mains phase angle The on time is kept constant for the mains voltage and load condition during the half sine wave to ensure a good Power Factor PF and Mains Harmonics Reduction MHR Using a constant ton the switching current to the PFC output is proportional to the sine waveform input voltage An essential PFC coil design parameter is the highest peak current This current occurs at the lowest input voltage and maximum output power

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