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SmartModule SM520PC

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1. A41 DRAM 3o 64Bit CASO DQMO 32Bit B41 CORE 50 Speaker A42 DRAM 30 CAS1 842 ISA 5i n c A43 DRAM 3o CAS2 DQM0 B43 ISA 50 A44 DRAM 3o CAS3 DQM1 B44 ISA 50 MEMR A45 DRAM 30 CAS4 DQM2 B45 ISA 50 SMEMR A46 DRAM 30 CAS5 DQM3 B46 ISA 50 MEMW 47 DRAM 30 CAS6 DQM2 B47 ISA 50 SMEMW A48 DRAM 30 CAS7 DQM3 B48 IDE CH2 5 i o n c A49 DRAM 3i o MD0 B49 IDE CH2 5 i o n c A50 DRAM 3 i o MD1 850 IDE CH2 5 i o n c A51 DRAM 3 i o MD2 851 IDE CH2 5 i o n c 52 DRAM 3 i o MD3 B52 IDE CH2 5 i o n c A53 DRAM 3 i o MD4 B53 IDE CH2 5 i o n c A54 DRAM 3 i o MD5 B54 IDE CH2 5 i o n c A55 DRAM 3 855 IDE CH2 5 i o n c 56 DRAM 3i o MD7 B56 IDE CH2 5 i o n c 57 POWER GROUND B57 IDE CH2 5 i o n c A58 DRAM 3 MD8 B58 IDE CH2 5 i o n c A59 DRAM 3 i o MD9 B59 IDE CH2 5 i o n c A60 DRAM 3 i o MD10 60 IDE CH2 5 i o n c A61 DRAM 3 i o MD11 B61 IDE CH2 5 i o n c A62 DRAM 3 i o MD12 B62 IDE CH2 5 i o n c A63 DRAM 3 i o MD13 B63 IDE CH2 5 i o n c A64 DRAM 3 i o MD14 B64 IDE CH2 50 n c 5 DRAM 3i o MD15 B65 IDE CH2 50 n c A66 POWER GROUND B66 IDE CH2 50 n c A67 DRAM 3 MD16 B67 IDE CH2 50 n c A68
2. 5 1 1 How to use this 5 1 2 TirademiarkS u u u uu C LLLI 5 1 3 A B a 5 1 4 Who should use this produtt si siusiniriniznznziiniizzjeniainzzznzzezzaniknanzzzzzonniiti nipkkriazzzeni tikieazzziztatii 5 1 5 Recycling Information s sisien g kati d Erin ea ei ratiti 5 1 6 SMART Support Request Form SMART SRF nanna 6 1 7 smart Designin Center smart nn 7 1 8 Limited Warranty m 8 1 9 Sample Design u u uuu nnns 8 OVERVIEW s iu uu e Sa A 9 2 1 iaa 9 2 2 Unique Features iii iii nir nr i ar 9 2 3 SM520PC block diagram U U I 10 2 4 SPecifiCatIONS iii e 11 2 5 Ordering Codes LULU a a 13 2 6 BIOS u Eh 14 2 7 This product is YEAR 2000 CAPABLE 14 2 8 Related Application Notes U u U U U UU U 14 2 9 SM520PC Incompatibilities to a standard 15 2 10 The smartModule520PC thermoanalysis eene nnns 17 PC FUNCTIONAL DESCRIPTION secta 18 3 1 Interrupt Controllers 18 3 2 PCI Devices and Definitions
3. 18 3 3 Timers and GOupterS usu 19 3 3 1 Programmable Tino cm 19 3 3 2 Battery backed clock 20 3 3 3 Watehdod Em 20 3 4 zo 21 3 4 1 M 21 3 4 2 EEPROM Memory for Setup sse nemen enemies 21 3 4 3 BIOS CMOS 22 3 5 CMOS p b a 23 3 6 EEPROM saved CMOS Setup U U u uu ener 29 3 7 Download the VGA BIOS and the CORE BIOS U U u u 30 3 8 ccoo cocaina ci ve essen we 31 3 8 1 System Memory Map I L nennen n rana 31 3 8 2 32 3 9 BIOS Data Area 4444 4 47 3 10 VGA LED 54 3 10 1 VGA LCD Controller 69000 54 3 10 2 VGA LCD BIOS for 69000 54 3 10 3 Display Modes 55 3 10 4 VGA LCD BIOS 56 3 10 5 Memory 69000 CRT TFT 57 3 10 6 Memory 69000 Color STN DD 58 3 10 7 Memory 69000 Mono STN DD 59 3 11 The Special Function Interface SFI 1 U 60 3 1
4. index A18 KBD 5 Keyboard data B18 FLOPPY 50 drive select 1 19 KBD 5o Kevboard clock 19 FLOPPY 5i disk change A20 MOUSE 50 MOUSE clock B20 FLOPPY 50 motor on 1 A21 MOUSE 5 i o MOUSE data B21 FLOPPY 50 direction A22 POWER Ground B22 FLOPPY 50 step impulse A23 IDE CH1 5 i o IDE HD 0 B23 FLOPPY 50 write data A24 IDE CH1 5 i o IDE HD 1 B24 FLOPPY 50 write gate A25 IDE CH1 5 i o IDE HD2 B25 FLOPPY track zero A26 IDE CH1 5 i o IDE HD 3 B26 FLOPPY 5i write protected A27 IDE CH1 5 i o IDE HD 4 B27 FLOPPY read data A28 IDE CH1 5 i o IDE HD 5 B28 FLOPPY 50 head select A29 IDE CH1 5 i o IDE HD 6 B29 FLOPPY 50 drive select 0 A30 IDE CH1 5 i o IDE HD 7 B30 FLOPPY 50 motor on 0 A231 IDE CH1 5 i o IDE HD 8 B31 APM n c A32 IDE CH1 5 i o IDE HD 9 B32 IDE CH1 50 IDE RESET A33 IDE CH1 5 i o IDE HD 10 B33 APM 5i n c A34 IDE CH1 5 i o IDE HD 11 B34 USB 5 USB P0 A35 IDE CH1 5 i o IDE HD 12 B35 USB 5 ilo USB P0 A36 IDE CH1 5 i o IDE HD 13 B36 IDE CH1 50 A0 A37 IDE CH1 5 i o IDE HD 14 B37 IDE CH1 50 A1 A38 IDE CH1 5 i o IDE HD 15 B38 IDE CH1 50 A2 A39 IDE CH1 50 IDE primary cs0 B39 IDE CH1 50 IORDY A40 IDE CH1 50 IDE primary cs1 B40 LCD 50 LCD D32 Remarks 5o 5V output 5 ilo 5V input output 30 3V output 3 i o 3V input output active low signal o c open collector output NC n
5. 8259A compatible interrupt controller within the TX chipset provides seven prioritized interrupt levels Of these several are normally associated with the board s onboard device interfaces and controllers and sev eral are available on the AT expansion bus Interrupt Sources 1 onboardused clock tick function from timerO IROG Floppy 1 Jjes IRO7 LPTiparalelpriner Jjes jFreefouser IRQ13 coprocessor 1 1 Jjes may depends on the LAN configuration 3 2 PCI Devices and Definitions The following definitions for the peripherals corresponds with the BIOS Device IDSEL PIRQ REQ GNT Comment SLOT 1 AD20 A B C D 0 0 SLOT 2 AD21 B C D A 1 1 SLOT 3 AD22 C D A B 2 2 SLOT 4 AD23 D A B C 3 3 VGA Controller AD20 Option LAN Controller AD29 IRQ A 0 0 USB 82C861 AD26 IRQ C 2 2 18 DIGITAL LOGIC AG SM520PC Manual V1 1 3 3 Timers and Counters 3 3 1 Programmable Timers An 8253 compatible timer counter device is also included in the board s ASIC device This device 15 utilized in precisely the same manner as in a standard AT implementation Each channel of the 8253 is driven by a 1 190 MHz clock derived from a 14 318 MHz oscillator which can be internally divided in order to provide a variety of frequencies Timer 2 can als
6. U U u rn 79 6 6 Thermal Specifications 80 DESIGNIN BLOCK SCHEMATICS 81 7 1 Chipsset ELAN520 from 44 4 4 100111 82 7 1 1 Architecture OVerview cccccccccccccnononononononononnnononononnnnnnnnnnnnnnnnnnnnnnnnnnononononononnnnnnnnnnnnnnnns 82 7 1 2 DRAM uu u DUM d reci 83 7 1 3 PCI Interface nn a Pa a us 83 7 1 4 POVES SIONA E e 5 5 e i Dee PRESE d PARERE 84 7 1 5 Design Consideratioris ee i a a ORI RH REOR ERR ARR 84 7 1 6 PCI Signal Descripitons is 85 7 2 Powermanagenmient ie 87 7 3 GClOCKS A ev davies Hed 87 7 4 STAG SONAS rei e At A Sa aaa Asa exes 87 7 5 PCI B s Signals LUISA iere eren ie ente eei nenne 88 7 6 ISA EIO Signals A A IRL ua 89 7 7 USB Interface om A LII Mie 90 7 8 IDE Interface LEE Ae ee ee ea a hi hel 90 7 9 BIOS to Flash Memory Interface 91 BEANS 20 S BIOS i anaE 91 SAMPLES SCHEMATICS SMXXPC DK 91 INDEX rx cect che A 96 DIGITAL LOGIC AG SM520PC Manual V1 1 1 PREFACE This manual is for integrators and programmers of systems based on the smartModule 520PC system on chip family It contains information on hard
7. O 38 DIGITAL LOGIC AG SM520PC Manual V1 1 Ad Read Write Description dress Status 00D2h Write request register for DMA channels 4 7 Write single mask register bit channels 4 7 bits 7 3 0 bit 2 Reserved 0 Clear mask bit bits 1 0 Channel select 00 Channel 4 01 Channel 5 10 Channel 6 11 Channel 7 Mode register for DMA channels 4 7 bits 7 6 00 11 Clear byte pointer Demand mode 01 Single mode 10 Block mode 11 Cascade mode 0 Address increment select 1 Address decrement select 0 Disable auto initialization 1 Enable auto initialization Operation type 00 Verify operation 01 Write to memory 10 Read from memory 11 Reserved Channel select 00 Channel 4 01 Channel 5 10 Channel 6 Channel 7 flip flop for DMA channels 4 7 1 Setmaskbit R Read Temoran Regier or OMA chama OOF2h R W OOFFh Math coprocessor SCSI Controller if installed I O addresses 0170h 0177h are reserved for use with a secondary hard drive See addresses 01F0h 01F7h for bit definitions 0170h 0172h 39 Continued DIGITAL LOGIC AG SM520PC Manual V1 1 dress Status mm sensro oraaa w wiegesonsestenrgserhrtasaneo Continued Error register for hard drive 0 Diagnostic mode bits 7 3 Reserved bits 2 0 Errors 0001 No errors 0010 Controller error 0011 Sector buffer error 0100 ECC device error
8. 832 532 Ta A SO OA apaq A 1 800 600 16 60 40 000 938 42 0 59 1300 1000 800 600 16 72 50 000 938 42 0 59 300 1300 1000 800 600 16 75 149500 938 42 0 59 300 1300 1000 800 600 16 85 56250 938 42 0 59 300 1300 1000 p r edes 800 600 24 60 40 000 1406 42 0 59 300 1769 1469 800 600 24 72 50 000 1406 42 0 59 300 1769 1469 800 600 24 75 49 500 1406 42 0 59 300 1769 1469 800 600 24 85 56250 1406 42 0 59 300 1769 1469 AI cxx ecouter means not possible resolution with the 4Mb Video RAM 59 SM520PC Manual V1 1 DIGITAL LOGIC AG 3 11 The Special Function Interface SFI All functions are performed by starting the SW interrupt 15h with the following arguments THIS FUNCTION IST NOT IMPLEMENTED IN THE ACTUAL BIOS REVISION 3 11 1 INT 15h SFR Functions Function Number Description Input Values Output Values Function Number Description EEPROM Input Values Output Values Function Number Description Input Values Output Values 60 WRITE TO EEPROM Writes the Data byte into the addressed User Memorv Cell from the serial The old value is automatically deleted EOh Function Request AL Databyte to store BX Address in the EEPROM 0 1024 Possible
9. ending scan line Position of cursor for each video page Current cursor po sition is stored two bytes per page First byte specifies the column the second byte specifies the row 60h Current Video Display Page 63h 64h 3B4h 3D4h 6845 compatible port address for current mode Monochrome Color Timer count for 24 hour rollover flag Reset flag 1243h 72h 73h 76h 77h Work area for hard disk Continued Soft reset Memory test is bypassed Status of last hard disk operation No error Invalid function requested Address mark not located Write protect error Sector not found Reset failed DMA overrun error Data boundary error Bad sector flag selected Bad track detected Invalid number of sectors on format Control data address mark detected DMA arbitration level out of range ECC or CRC error Data error corrected by ECC Controller failure Seek operation failure Timeout Drive not ready Undefined error occurred Write fault on selected drive Status error or error register 0 Sense operation failed Number of hard drives 50 DIGITAL LOGIC AG BIOS Data Area Definitions continued 8Ah Reserved 8Bh Diskette drive data transfer rate information bits 7 5 Data rate on last operation 00 500 KBS 01 300 KBS 10 250 KBS Last drive step rate selected Data transfer rate at start of operation 00 500 KBS 01 300 KBS 10 250 KBS Reserved Copy of
10. Diskette hardware interrupt occurred bits 6 4 Not used bits 3 2 Reserved bit 1 0 Recalibrate drive B bit 0 0 Recalibrate drive A Continued 48 DIGITAL LOGIC AG SM520PC Manual V1 1 BIOS Data Area Definitions continued Diskette Drive Motor Status Drive Motor Status bit 7 Current operation 0 Write or Format 1 Read or Verify bit 6 Reserved bits 5 4 Drive Select 00 Drive A 01 Drive B bits 3 2 Reserved 0 Disable 1 Enabled bit 1 Drive B Motor Status 0 Off 1 On bit 1 Drive A Motor Status 0 Off 1 On Diskette Drive Motor Timeout Disk drive motor is powered off when the value via the INT 08h timer interrupt reaches 0 03h 04h 06h opened 08h 09h 0Ch 10h Write protect error Sector not found Diskette change line active door DMA overrun error Data boundary error Unknown media type ECC or CRC error 20h Controller failure 40h Seek operation failure 80h Timeout fo e say Continued H HI uo Diskette Drive Status bit 7 Drive Ready 0 Ready 1 Not ready bit 6 Seek Error 0 No error 1 Error occurred bit 5 Controller operation 0 Working 1 Failed bits 4 0 Error Codes 00h No error 01h Invalid function requested 02h Address mark not located 49 DIGITAL LOGIC AG SM520PC Manual V1 1 BIOS Data Area Definitions continued 50h 5Fh 60h 61h Start and end lines for 6845 compatible cursor type starting scan line 61h
11. Without electronic know how we expect you to have questions This manual assumes that you have a general knowledge of PC electronics Because of the complexity and the variability of PC technology we can t give any warranty that the prod uct will work in any particular situation or combination attention to the electrostatic discharges Use a CMOS protected workplace Power supply OFF when you are working on the board or connecting any cables or devices This is a high technology product You need know how in electronics and PC technology to install the system 1 5 Recycling Information Hardware Print epoxy with glass fiber wires are of tin plated copper Components ceramics and alloys of gold silver check your local electronic recycling DIGITAL LOGIC AG SM520PC Manual V1 1 1 6 SMART Support Request Form SMART SRF 1 Send this SRF with your problem description to DIGITAL LOGIC AG smartModule DesignIn Center Nordstr 11 F CH 4542 Luterbach SWITZERLAND Fax 41 32 681 58 01 E Mail support digitallogic com Internet www digitallogic com Support request form fill in and send via fax to DIGITAL LOGIC AG support center SRF No S118 Date Customer company Customer Name Customer Tel No Customer E Mail Customers Customers Country Address SMART type SM520PC processing date Request tvpe Support Report Operating Svstem Designin Aid
12. serial port 1 bits 7 5 Reserved bit 4 1 Loopback mode for diagnostic testing of serial port bit 3 1 User defined output 2 bit 2 1 User defined output 1 bit 1 Force Request To Send active bit 0 Force Data Terminal Ready active Continued 45 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status ___ 03FEh Modem status register serial port 1 bit 7 i bit 6 i i bit 5 bit 4 bit 3 i bit 2 ili i bit 1 bit 0 Delta Clear To Send Reserved 03FDh Line status register serial port 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 Data ready Transmitting shift and holding registers empty Transmitter shift register empty Break interrupt Framing error Overrun error Data Carrier Detect Ring Indicator Data Set Ready Clear To Send Delta Data Carrier Trailing Edge Ring Indicator Delta Data Set Ready 03FFh Scratch register serial port 1 used for diagnostics 0A79h w PnP Data write register only for PnP devices 46 DIGITAL LOGIC AG SM520PC Manual V1 1 3 9 BIOS Data Area Definitions The BIOS Data Area is an area within system RAM that contains information about the system environment System environment information includes definitions associated with hard disks diskette drives keyboard video as well as other BIOS functions This area is created when the system is first powered on It occu pies a 256 byte area from 0400h 04FFh The followin
13. to go on even if there is no keyboard or display adapter With the Embedded Support Kit users can almost work with such machines like they are used to on a standard PC The BIOS contains support for both serial and parallel transmission 3 13 1 The Remote Server REMHOST EXE The utility REMHOST is started on the host computer It listens on the serial or parallel port for incoming tar get requests executes the commands and sends the output values back The user can decide on the host machine in a configuration file which devices the target system should redi rect By default the target assumes to redirect video and keyboard services The following options are available in the configuration file REMHOST INI PORT 1 COM LPT port number LPT use parallel port for transmission comment this for serial port FLOPPY enable host floppy FLOPPY ROMDISK IMG use a floppy disk image WRPROT simulate write protection for remote drives NOKEYB II disable host keyboard NOVIDEO disable host video DUALVIDEO use target display and remote video simultaneously Within the configuration file you can add comments with Instead of using a real floppy drive you can also generate image files of floppy disks Access to these image files are much faster than to real floppy disks Additionally the image files can be write protected So you can build up virtual floppy drives to initially set up the target s file system
14. to start test tools during production Floppy disk images can be produced with the utility FDIMAGE Type FDIMAGE H to get a list of available options Rem not supported needs a customized BIOS 62 DIGITAL LOGIC AG SM520PC Manual V1 1 When video redirection is enabled option NOVIDEO not active the BIOS will skip the initialization of both ISA and PCI VGA cards The BIOS thereby comes up much quicker Using the keyword DUALVIDEO will enable possible VGA cards as well and display video output on both the real video card and on the remote machine This allows hardware engineers to debug vga controller problems The BIOS will not warn for missing keyboards as soon as remote keyboard is enabled You can leave REMHOST by pressing the left SHIFT and STRG keys simultaneously 3 13 2 Remote enabler To enable the remote function one has to make a hardware switch as follows 4 DTR and pin 9 RI have to be bridged on the target PC Leave pin 9 unconnected open from the host PC 3 13 3 Cable Definition The wiring of the serial null modem cable is as follows PC1 Host PC2 Target Signal Name Pin Number Pin Number Signal Name DCD 1 7 8 RTS CTS RxD 2 3 TxD TxD 3 2 RxD DTR 4 Sa 6 DSR GND 5 5 GND DSR 6 4 DTR RTS CTS 7 8 1 DCD 63 DIGITAL LOGIC AG SM520PC Manual V1 1 3 14 Watchdog Control RESWDOG EXE In this sample the PC will reboot af
15. 3i REQ0 B69 PCI 3o GNT0 70 3i REQ1 B70 PCI 3o GNT1 A71 PCI 3i REQ2 B71 PCI 3o GNT2 A72 PCI 3i REQ3 B72 PCI 3o GNT3 A73 RES 30 ACLED from LAN B73 POWER 5V A74 PCI 3 FRAME B74 PCI 3 i o IRDY A75 PCI 3 i o TRDY B75 PCI 3 i o STOP A76 PCI 3 DEVSEL B76 PCI 3 i o PAR 3 SERR B77 PCI 3 i o LOCK A78 RES 30 LILED from LAN B78 PCI 3o PCI RESET A79 Core 3i Resetinput POWERgood B79 ISA 5i n c A80 Res n c B80 ISA 50 DACK7 All PCI signals are left open if the SmartModule does not support the PCI bus Remarks 50 5V output 30 3V output active low signal 5 i o 3 i o 5V input output 3V input output o c open collector output RES pin function depending of the CPU reserved NC not connected 76 DIGITAL LOGIC AG SM520PC Manual V1 1 SM520PC Connector J2 Pin 81 120 81 LCD 50 LCD 024 B81 USB 5 i o USB P1 82 LCD 50 LCD 025 882 USB 5 i o USB P1 A83 LCD 50 LCD 026 883 USB 5 i o n c 84 LCD 50 LCD 027 884 USB 5 i o n c A85 LCD 50 LCD 028 885 ISA 50 LA22 A86 LCD 50 LCD 029 B86 ISA 50 LA23 A87 LCD 50 LCD 030 B87 PCI 5i o PERR 88 LCD 50 LCD 031 B88 RES 30 n c A89 ELAN ROMRD B89 122 3 i o SMB DAT A90 ELAN ROMWR B90 120 3o SMB CLK A91 POWER 3 3V B91 POWER 3
16. 42 o 300 604 304 THE A EOS asa E quat Y 640 480 16 60 25475 600 42 o 0 300 904 604 640 480 16 72 31500 600 42 o 0 300 904 604 640 480 16 75 31500 600 42 o 300 904 604 640 480 16 85 136000 600 42 o 300 904 604 pear E Jue O 640 480 24 60 25 175 900 42 o 0 300 1204 904 640 480 24 72 31500 900 42 0 0 300 1204 904 640 480 24 75 31500 900 42 o 0 300 1204 904 640 480 24 85 36 000 900 42 o 300 1204 904 EME eee 800 600 8 60 40000 469 42 o 0 300 773 473 800 600 8 72 50000 469 42 o o 300 773 473 800 600 8 75 49500 469 42 o o 300 773 473 800 600 8 85 56250 469 42 o 300 773 473 Iz 800 600 16 60 40 000 938 42 o 300 1242 942 800 600 16 72 50 000 938 42 o 0 300 1242 942 800 600 16 75 49 500 938 42 o 0 300 1242 942 800 600 16 85 56250 938 42 o 300 1242 942 1 800 600 24 60 40 000 1406 42 o 0 300 1710 1410 800 600 24 72 50 000 1406 42 o 0 300 1710 1
17. Asynchronously resets the TAP controller in the processor VCCT V_Core GTL Termination Voltage Used by the POWERON pin on the ITP debug port to determine when target system is on POWERON pin is pulled up using 1 resistor to VTT 87 DIGITAL LOGIC AG SM520PC Manual V1 1 7 5 PCI Bus Signals e All unused general purpose inputs GPIs should be pulled to a valid logic level with 10 KO resistor When pulled high they should be pulled to V 3S expect the GPls that are in the Vcc SUS well PCI Bus Signal Resistor Values onboard smartModule Name Termination Resistor Pull up pull down Resistor Unused GPIs None 10 K to a valid level IDSEL signals 100 None PIRQ A D None 10 K Pull up to V_3S SDONE None 10 K Pull up to V_3S SBO None 10 K Pull up to V_3S FRAME None 10 K Pull up to V_3S TRDY None 10 K Pull up to V_3S STOP None 10 K Pull up to V_3S IRDY None 10 K Pull up to V_3S DEVSEL None 10 K Pull up to V_3S PLOCK None 10 K Pull up to V_3S PERR None 10 K Pull up to V_3S SERR None 10 K Pull up to V_3S REQ64 None 10 K Pull up to V_3S ACK64 None 10 K Pull up to V_3S PCIREQ D A None 10 K Pull up to V 3S REQJ A C None 10 K Pull up to V_3S 88 DIGITAL LOGIC AG SM520PC Manual V1 1 7 6 ISA EIO Signals ISA EIO Signal Resistors Values Name Termination R
18. B44 D34 E R4 B45 D35 E R5 A106 VS IFLM FRAM 5 FLM VSYN VSYN VSYN YD VS E B106 HS LP LOAD CP1 CL1 HSYN HSYN HSYN LP LP HS B105 SHFCLK CP2 CL2 CK CK CK XCKL XCK SH CIK B119 M DF M ENAB ENAB 5 M PANEL Generic LM64P80 LCM 5491 LQ9D011 1010031 LQ10DX0 LM64C03 LM64CO SHARP SANYO SHARP 1 1 1 8 SHARP SHARP SHARP Sharp 78 DIGITAL LOGIC AG SM520PC Manual V1 1 6 4 CRT Monitor Signaldefinition Pin Name Function A101 green analog output green A102 blue analog output blue A103 red analog output red B101 gnd analog ground B102 vsynch vertical synchron signal to the CRT B103 hsynch horizontal synchron singla to the CRT 6 5 Connector Specifications The DIGITAL LOGIC AG smartModule 520PC module connectors are surface mount 0 635mm pitch 240pin connectors Parameter Condition Specification Material Contact Beryllium Copper Housing Thermoplast Molded Electrical Current 0 5 Amp Voltage 100 VAC Termination Resistance 20mOhms Insulation Resistance 500MOhm Mechanical Mating Cycles 50 Connector Mating Force 1N per contact Connector Unmating Force 0 4N per contact Pitch 0 635mm Number of pins 240 The manufacturer of the connector is Source on SM520PC module Part Name Part Number On customers board to hold a SM520PC 5 MOLEX 240pin 534
19. Controller 0 Disabled 1 Enabled bit 4 Internal IDE Controller 0 Disabled 1 Enabled bit 3 Hard Drive 0 Custom Flag 0 Disable 1 Enabled bit 2 Hard Drive 0 IDE Flag 0 Disable 1 Enabled bit 1 Hard Drive 1 custom Flag 0 Disable 1 Enabled bit 0 Hard Drive 1 IDE Flag 0 Disable 1 Enabled Continued 26 DIGITAL LOGIC AG CMOS Map Continued EMS Memory Size Low Bvte 1Eh EMS Memorv Size High Bvte 1Fh 24h Custom Drive Table 0 These 6 bytes 48 bits contain the following data Cylinders Landing Zone 10 bits Write Precomp 10 bits Heads Sectors Track 8 bits Byte 0 bits 7 0 Lower 8 Bits of Cylinders Byte 1 bits 7 2 Lower 6 Bits of Landing Zone bits 1 0 Upper 2 Bits of Cylinders Byte 2 bits 7 4 Lower 4 Bits of Write Precompensation bits 3 0 Upper 4 Bits of Landing Zone Byte 3 bits 7 6 Reserved bits 5 0 Upper 6 Bits of Write Precompensation Byte 4 23h bits 7 0 Number of Heads Byte 5 24h bits 7 0 Sectors Per Track 25h 2Ah Custom Drive Table 1 These 6 bytes 48 bits contain the following data Cylinders Landing Zone 10 bits Write Precomp 10 bits Heads Sectors Track 8 bits Byte 0 bits 7 0 Lower 8 Bits of Cylinders Byte 1 bits 7 2 Lower 6 Bits of Landing Zone bits 1 0 Upper 2 Bits of Cylinders Byte 2 bits 7 4 Lower 4 Bits of Write Precompensation bits 3 0 Upper 4 Bits of Landing Zone Continued 27 SM520PC Manual V1 1 DIGITA
20. Mounting holes hard drive 2 51nch 1DE primary 2 5Inch mart IDE bus primary and secondary IDE bus termination and separation for MSM DK 94 i TAT DIGITAL LOGIC AG 10 INDEX Battery 19 battery current 19 BIOS CMOS 21 BIOS ROM 20 BUS 12 CMOS 21 CMOS Setup 29 Coprocessor 11 CRT Displays 56 DesignIn 66 Dog 12 Download the VGA BIOS 30 EEPROM Memory for Setup 20 EMI EMC 13 Floppy disk 11 Harddisk list 28 Harddisk List 21 map 33 IDE interface 11 interfaces 12 interrupt 15h 61 Interrupt Controllers 17 86 IrDA 75 SM520PC Manual V1 1 2 Q N LCD Controller LED criterions QN tA tA Mechanical Dimensions 66 69 70 memory address MAP 32 PCI Devices Power Supply RN Real time clock 19 Remote function 63 ROM BIOS 20 RTC Address MAP 19 SFI 61 Signaldefinition 78 smart480 bus 71 SODIMM 80 Special Function Interface 61 Specifications 11 VGA 55 VGA BIOS 31 Watchdog 19 WatchDOG 63
21. OS Version BIOS Adaption BIOS Version vo Manual Correction others Problem description Solution Answer will be filled in by DIGITAL LOGIC AG SMART Designin center Support date Support statistics Support sign Comment Support cost yes no Offered costs CHF USD DEM for serving design support Designin No Effective time costs DIGITAL LOGIC AG SM520PC Manual V1 1 1 7 smart Designin Center smart DIC DIGITAL LOGIC AG offers a Designin support from a specialized engineering group in the SMART Designin Center SMART DIC To initialize a Designin Support please fill in the SMART SRF form The Designin Support can be offered in each phase of a Designin procedure Oniv the ordered support value will be charged The charge fees are as follow Design Phase Support tvpe Fee Charged Evaluation 01 Consultation CHF 200 per hour 02 Training CHF 200 per hour 03 Design of the customers specification CHF 150 hour Schematics 10 Consultation CHF 200 per hour 11 Design of the schematics CHF 150 per hour 12 Review Inspection of customers schematics CHF 300 per sheet 13 Development of circuits schematics CHF 200 per hour Layout 20 Consultation CHF 200 hour 21 Design of the layout CHF 150 per hour 22 Review Inspec
22. SI 1234h User Password otherwise EEP is write protected DLAG Password for access to the DLAG Memory Cells None all registers are preserved READ FROM EEPROM E1h Reads the Data byte from the addressed User Memory Cell of the serial AH E1h Function Request BX Address in the EEPROM 0 1024 Possible SI 1234h User Password DLAG Password for access to the DLAG Memory Cells AL read databyte WRITE SERIALNUMBER E2h Writes the Serialnumber from the serial EEPROM into the addressed DLAG Memory Cell The old value is automatically deleted AH E2h Function Request DX CX BX Serialnumber Binary not Ascii SI Password None all registers are preserved DIGITAL LOGIC AG SM520PC Manual V1 1 Eunction READ SERIALNUMBER Number E3h Description Reads the serialnumber from the board into the serial EEPROM Input Values E3h Function Request Output Values DX CX BX rialnumber Binary not Ascii Function WRITE PRODUCTION DATE amp RESET DLAG COUNTERS Number E4h Description Writes the production date into the addressed DLAG Memory Cell from the serial EEPROM The old value is automatically deleted Ifthe Password is also in DX the counters will be resettet 0 Input Values AH E4h Function Request Year 1997 gt BH 19 BL 97 Month 1 12 Day of Month 1 31 Password Password if counters should be resetted otherwise no password Output Values None all registers are preserved
23. not used 3 3V OK LAN Speed LED not used 5 1 2 Power control LEDs on the SM520PC On the topside of the smartModule 586PC are 2 LED s located 1 The GREEN POWER LED Indicates that the 3 3V core supply for the CPU is OK This LED must light as soon as the external 5V power supply is available 2 The GREEN RESET RUN LED OFF The module is in the RESET state that means no operation The WatchDOG or the power supervisor or an active external reset signal holds the modul in the RESET state ON The module is running normally After power up this LED must light ON after 1 2sec AFTER A SUCCESSFUL BOOT SEQUENCE TWO GREEN LED S ARE ON 66 DIGITAL LOGIC AG SM520PC Manual V1 1 6 DESIGNIN WITH THE smartModule 6 1 Mechanical Dimensions SM520PC 67 DIGITAL LOGIC AG SM520PC Manual V1 1 6 11 Mechanical PCB Pad Dimensions on the 68 DIGITAL LOGIC AG SM520PC Manual V1 1 6 1 2 PCB to SM520PC height 69 DIGITAL LOGIC AG 6 1 3 Mechanical Dimensions of the PCB plug Must be mounted onto the customers electronicboard carrierboard Standard height Expanded height 5 0mm do not place components below the smartModule SM520PC Manual V1 1 7 0 place max 2 0mm components below the smartModule
24. placed as close as possible to the chipset e When the distance between the Southbridge and connector is greater than 4 the terminating resistors should be placed within 1 of the Southbridge e When using the ISA reset signal RSTDRV from the Southbridge it should be routed through a Schmitt trigger for RESET signals e Ground pins 19 2 22 24 26 30 40 of both ATA connectors e Pins 20 and 34 of both ATA connectors should be left unconnected e According to ATA 4 specification 10 KO pull down resistor is required on DD7 to allow a host to rec ognize the absence of a device at power up e Both IDE devices should connect to IRQ14 e CSEL connected 28 together between the two ATA connectors and be pulled down with a 470 resistor to meet PC97 requirement e DIAG pin 34 connected together between the two ATA connectors 90 DIGITAL LOGIC AG IDE Interface Signal Resistor Values SM520PC Manual V1 1 Name Termination Resistor Q Pull up pull down Resistor PDDREQ 33 82 for Ultra DMA 5 6 K pull down PIORDY 82 Ultra DMA only 1 K Pull up CSEL Pin 28 None 470 pull down All signals to the IDE 33 None connector DD7 33 10 K pull down 7 9 BIOS to Flash Memory Interface e 2 Mbits of flash is usually all that is required to support the ELAN520 in all configurations These are the recommendations for an Intel 28F200BV flash part 8 ELAN520 s B
25. register channel 2 0043h Programmable Interrupt Timer mode port control word register for counters 0 and 2 bits 7 0 Counter select 00 Counter 0 select 01 Counter 1 select 10 Counter 2 select its 5 00 Counter latch command 01 R W counter bits 0 7 only 10 R W counter bits 8 15 only 11 R W counter bits 0 7 first then bits 8 15 its 3 Select mode 000 Mode 0 001 Mode 1 programmable one shot x10 Mode 2 rate generator x11 Mode 3 square wave generator 100 Mode 4 software triggered strobe 101 Mode 5 hardware triggered strobe i Binary counter is 16 bits Binary counter decimal BCD counter 0048h Rw Programmable interrupt timer 0060h R Keyboard controller data port or keyboard input buffer 0060h Keyboard or keyboard controller data output buffer Continued 36 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status C 0064h Keyboard controller read status bit 7 No parity error Parity error on keyboard transmission bit 6 No timeout Received timeout bit 5 No timeout Keyboard transmission timeout bit 4 Keyboard inhibited Keyboard not inhibited bit 3 Data Command bit 2 ystem flag status bit 1 Input buffer empty Input buffer full bit 0 Output buffer empty Output buffer full 0064h w Keyboard controller input buffer 0070h CMOS RAM index register port and NMI mask bit 7 1 NMI disabled bits 6 0 0 CMOS RAM index 0071h CMOS RAM data register port 0080h
26. signals carefully if he likes to upgrade lateron with another module with a higher performance The following performance will be available 700Mhz smP3PC 700 400MHz smP3PC 400 266Mhz smGXPC X smP5PC 133Mhz sm520 PC sm520 PCX 66Mhz sm486PCX CPU 486SX 586DX Pentium Pentium lll CPU 486SX ELAN400 520PC Pentium Pentium Ill CPU Clock 33 99Mhz 133Mhz 166 266Mhz 400 700Mhz Power consumption 3 4 Watts 3 5 Watts 5 7 Watts 7 9 Watts Standard functions DRAM Expansion 32Bit 32Bit 64Bit 64Bit Keyboard amp Mouse yes yes yes yes COM1 yes yes yes yes COM2 yes yes yes yes Floppydisk yes yes yes yes LPT1 yes yes yes yes Prim DIE yes yes yes yes Sec DIE no yes yes yes ISA Bus yes yes yes yes CRT VGA Signals yes yes yes yes LCD 24Bit yes yes yes yes Unique functions PCCard yes no no no LAN yes no no no PCl Bus no ves ves ves Kevmatrix ves no no no 1 4VGA LCD ves no no no 36Bit LCD Extension no ves ves ves USB Interface no no ves ves COM3 ves no no no ZV Port no no no no 16 DIGITAL LOGIC AG SM520PC Manual V1 1 2 10 The smartModule520PC thermoanalvsis DIGITAL LOGIC provides a set of thermal images made after 120min operating in a typical applications SM520PC Version 1 1 run MSDOS EDIT Time gt 120 min DIGITAL LOGIC AG SM520PC Manual V1 1 3 PC FUNCTIONAL DESCRIPTION 3 1 Interrupt Controllers
27. 0 4656 4356 means not possible resolution with 4Mb Video 58 DIGITAL LOGIC AG SM520PC Manual V1 1 3 10 7 Memory 69000 Mono STN DD Panels Hor Vert Refr DCLK FB M Video Total Resol Resol jbpp Hz Mhz kByte kByte kByte kByte Input with w o kBvte Video Video 8 60 25175 300 42 0 38 300 642 342 640 480 8 72 31500 300 42 0 38 300 642 342 640 480 8 75 31500 300 42 0 38 300 642 342 640 480 8 85 36000 300 42 0 38 300 642 342 iii 640 4801 16 60 281751 600 42 0 38 300 942 642 640 480 16 72 31500 600 42 0 38 300 942 642 640 480 16 75 31500 600 42 0 38 300 942 642 640 480 16 85 36 000 600 42 0 38 300 942 642 Pe L 640 480 24 60 25475 900 42 0 38 300 1242 942 640 480 24 72 31500 900 42 0 38 300 1242 942 640 480 24 75 31500 900 42 0 38 300 1242 942 640 480 24 85 36 000 900 42 o 38 300 1242 942 800 600 8 60 40000 469 42 0 59 300 832 532 800 600 8 72 50000 469 42 0 59 300 832 532 800 600 8 75 49 500 469 42 0 59 300 832 532 800 600 8 85 156250 469 42 0 59 300
28. 0 300 42 120 0 300 724 424 640 480 8 75 31500 300 42 120 0 300 724 424 640 480 8 85 36000 300 42 120 0 300 724 424 EIA A sau Ee ras 640 480 16 60 25 175 600 42 120 300 1024 724 640 480 16 72 31 500 600 42 120 300 1024 724 640 480 16 75 31 500 600 42 120 300 1024 724 640 480 16 85 36 000 600 42 120 0 300 1024 724 pear A ee eres See 640 480 24 60 25 175 900 42 120 0 300 1324 1024 640 480 24 72 31500 900 42 120 0 300 1324 1024 640 480 24 75 131500 900 42 120 0 300 1324 1024 640 480 24 85 136 000 900 42 120 0 300 1324 1024 800 600 8 02000 469 42 188 0 300 960 800 600 8 72 50000 469 42 188 0 300 960 800 600 8 75 149500 469 42 188 0 300 960 800 600 8 85 56250 469 42 188 300 960 or 800 600 16 60 40 000 938 42 188 0 300 1429 1129 800 600 16 72 50 000 938 42 188 0 300 1429 1129 800 600 16 75 149500 938 42 188 0 300 1429 1129 800 600 16 85 56250 938 42 188 0 300 1429 1129 800 600 24 60 40 000 1406
29. 0000 Not installed 0001 Drive A 360 K 0010 Drive A 1 2 MB 0011 Drive A 720 K 0100 Drive A 1 44 MB 0101 Drive A 2 88 MB Diskette Drive B 0000 Not installed 0001 Drive B 360 K 0010 Drive B 1 2 MB 0011 Drive B 720 K 0100 Drive B 1 44 MB 0101 Drive B 2 88 MB Fixed Hard Drives bits 7 4 Hard Drive 0 AT Type 0000 Not installed 0001 1110 Types 1 14 1111 Extended drive types 16 44 See location 19h bits 3 0 Hard Drive 1 AT Type 0000 Not installed 0001 1110 Types 1 14 1111 Extended drive types 16 44 See location 2Ah See the Fixed Drive Type Parameters Table in Chapter 2 for infor mation on drive types 16 44 Continued 25 DIGITAL LOGIC AG SM520PC Manual V1 1 CMOS Map Continued la Em bits 7 6 Number of Diskette Drives 00 One diskette drive 01 Two diskette drives 10 11 Reserved Primary Display Type 00 Adapter with option ROM 01 CGA in 40 column mode 10 CGA in 80 column mode 11 Monochrome Reserved Math Coprocessor Presence 0 Not installed 1 Installed Bootable Diskette Drive Not installed Installed 19h Extended Drive Type Hard Drive 0 See the Fixed Drive Type Parameters Table in Chapter 2 for infor mation on drive types 16 44 Extended Drive Type Hard Drive 1 See the Fixed Drive Type Parameters Table in Chapter 2 for infor mation on drive types 16 44 Custom and Fixed Hard Drive Flags bits 7 6 Reserved bit 5 Internal Floppy
30. 0101 Control processor error Operation mode bit 7 Block 0 Bad block 1 Block not bad Error 0 No error 1 Uncorrectable ECC error Reserved ID 0 ID located 1 ID not located Reserved Command 0 Completed 1 Not completed Track 000 Not found Not found 1 DRAM 0 1 Found 3022 86 0 40 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status 01F6h R W Drive Head register for hard drive 0 bit 7 bit 6 bit 5 bit 4 Drive select 0 First hard drive 1 Second hard drive Head select bits 01F7h Status register for hard drive 0 bit 7 1 Controller is executing a command bit 6 1 Drive is ready bit 5 1 Write fault bit 4 1 operation complete bit 3 1 Sector buffer requires servicing bit 2 1 Disk data read completed successfully bit 1 Index is 1 at each disk revolution bit 0 zi Previous command ended with error 01F7h Command register for hard drive 0 0200h R W Game controller ports 020Fh 0201h data game port 0220 R W Soundport AD1816 reserved 022Fh I O addresses 0278h 027Ah are reserved for use with parallel port 2 See the bit defi nitions for addresses 0378h 037Ah 0278h R W Data port for parallel port 2 0279h R Status port for parallel port 2 0279h PnP Address register only for PnP devices 027Ah 02B0h R W Digital I O for Latch WDOG Control 02BFh I O addresses 02E8h O2EFh are reserved for use with seria
31. 0PC design has the knowledge of designing ISA based PC architec ture DIGITAL LOGIC AG SM520PC Manual V1 1 2 OVERVIEW 2 1 Features The smartModule 520PC is a miniaturized PC system on chip unit incorporating the major elements of a PC AT compatible computer It includes standard PC AT compatible elements such as Powerfull X86 with 133MHz clock BIOS ROM SODIMM socket for 16 128MB Timers DMA Real time clock 2k EEPROM LPT1 1 COM2 Speaker interface AT keyboard interface PS 2 mouse interface Floppydisk interface ATA IDE harddisk interface channels VGA LCD video controller Embedded smartBUS480 3 3V power supply switched mode 2 2 Unique Features EEPROM for setup and configuration UL approved parts 2xUSB Option LAN 100 10Base T as an assemblyoption PCX DIGITAL LOGIC AG SM520PC Manual V1 1 2 3 SM520PC block diagram Chip CPU x86 BRAN E SO DIMM 16 128MB BUS ELAN520 Northbridge PCI BUS ELAN520 LCD VGA VRAM Southbridge Controller 2 MB Speaker 69000 LIRAT LCD CRT Watchdog EEPROM ISA BUS BIOS SMSC Super I O 256kByte MAX2II MAX2II IrDA FD LPT1 COM1 COM2 KB Mouse 10 DIGITAL LOGIC AG SM520PC Manual V1 1 2 4 Specifications CPU CPU ELAN520 133MHz from AMD Mode Real Protected Compatibilitv 8086 80386 1 Level Cache 16 amp 16kByte write back Word Size 32 Bits Physical Addr
32. 1 1 INT 15h SFIS FUnCIORS l uu u u uu SE 60 3 12 Remote function COCO NO N 62 3 13 Remote Features ones lt lt Rana CERE 62 3 13 1 The Remote Server REMHOST EXE nanna 62 3 13 27 Remote enabler rrr eere ke ea keta 63 3 13 3 Cable Definition oia asi gece acta ree EUR 63 3 14 Watchdog Control LLUUU ie kt 64 DIGITAL LOGIC AG SM520PC Manual V1 1 4 5 8 9 10 DESCRIPTION OF THE JUMPERS 65 LED CRITERIONS li ien 66 5 1 2 Power control LEDs on the SM520PC u 66 DESIGNIN WITH THE SMARTMODUIE 67 6 1 Mechanical Dimensions SM520PC sr 67 6 1 1 Mechanical Pad Dimensions on the 68 6 1 2 PCB to SM520PC height iier ertet we cede ine cuts 69 6 1 3 Mechanical Dimensions of the PCB plug a 70 6 1 4 Mechanical Dimensions of the SM520PC receptacle 71 6 2 SM520PC uses signals on the smart480 bus eene 72 6 3 LCD Interface Signaldefinition ss UU U U uuu uu nnns 78 6 4 CRT Monitor Signaldefinition U UU u u uu u 79 6 5 Connector Specifications
33. 11Bh 011Ch 011Fh 0120h 0122h 0123h 0125h 0126h 0128h 0129h 012Bh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0200h 03FFh 0200h 027Fh 0400h 07FFh CMOS Setup valid 01 valid Keymatrix Setup valid 01 valid Flag for DLAG Message FF no message Copy of CMOS Setup data reserved for AUX CMOS Setup Serial Number Production date year day month 1 Service date year day month 2 Service date year day month 3 Service date year day month Booterrors Autoincremented if any booterror occurs Setup Entries Autoincremented on every Setup entry Low Battery Autoincremented everytime the battery is low EEPROM gt CMOS Startup Autoincremented on every poweron start Number of 512k SRAM Number of 512k Flash BIOS Version V1 4 gt 0132h 4 0133h 1 BOARD Version V1 5 gt 0124h 5 0125h 1 BOARD TYPE M PC 104 E Euro W ZMSWS S Slot C Custom CPU TYPE 01h ELAN300 310 O2h ELAN400 03h 486SLC 04h 486DX 05 5 Keymatrix Setup data Keymatrix Table Free for Customer s use 21 DIGITAL LOGIC AG SM520PC Manual V1 1 3 4 3 BIOS CMOS Setup If wrong setups are memorized in the CMOS RAM the default values will be loaded after resetting the RTC CMOS RAM with the CMOS RESET jumper If the battery is down it is always possible to start the sys tem with the default values from the BIOS WARNING On the next setup pages switch with TAB the values for special
34. 12 B87 DRAM 3 i o MD53 A88 POWER Ground B88 DRAM 3i o MD54 A89 DRAM 3 i o MD24 B89 DRAM 3 i o MD55 A90 DRAM 3 i o MD25 B90 POWER GROUND A91 DRAM 3 i o MD26 B91 DRAM i o MD56 A92 DRAM 3 i o MD27 892 DRAM 3i o MD57 A93 DRAM 3 i o MD28 B93 DRAM 3i o MD58 A94 DRAM 3 MD29 894 DRAM 3 i o MD59 A95 DRAM 3 i o MD30 895 DRAM 3i o MD60 A96 DRAM 3 i o MD31 B96 DRAM 3 i o MD61 A97 POWER GROUND B97 DRAM 3i o MD62 A98 DRAM 3 i o MD32 898 DRAM 3i o MD63 A99 DRAM 3i o MD33 B99 POWER GROUND A100 DRAM 3 i o MD34 B100 IDE CH2 5 n c A101 DRAM 3 i o MD35 B101 IDE CH2 5 i o n c A102 DRAM 3 i o MD36 B102 IDE CH2 5 i o IRQ A103 DRAM 3 i o MD37 B103 IDE CH2 5 i o n c 104 DRAM 3 i o MD38 B104 IDE CH2 5 i o A0 A105 DRAM 3 i o MD39 B105 IDE CH2 5 i o A1 A106 POWER GROUND B106 IDE CH2 5 i o A2 107 DRAM 3 i o MD40 B107 DRAM 3o BA0 A108 DRAM 3 i o MD41 B108 Core 5 if WD strobe A109 DRAM 3 i o MD42 B109 Core 5 i WD enable 110 DRAM 3 i o MD43 B110 DRAM 3o BA1 A111 DRAM 3 i o MD44 B111 XBUS 30 XDO 112 DRAM 3i o MD45 8112 XBUS 30 XD1 113 DRAM 3i o MD46 B113 XBUS 30 XD2 A114 DRAM 3i o MD47 B114 XBUS 3o XD3 115 DRAM 3o RAS0 B115 XBUS 30 XD4 116 DRAM RAS 1 B116 XBUS 30 XD5 A117 DRAM 30 RAS2 8117 XBUS 3o XD6 A118 DRAM 3o RAS3 B118 XBUS 30 XD7 119 DR
35. 2 50 coe TF m PCB LAYOUT GOMPON 53475 2409 Dimension mm inches Circuits A Overall Length B 151 to Last C D 240 83 07 3 270 75 565 2 970 79 17 3 110 78 07 3 070 DLAG partnumber 439004 70 DIGITAL LOGIC AG SM520PC Manual V1 1 6 14 Mechanical Dimensions of the SM520PC receptacle Mounted on the smartModule 586PC as a reference only 6 40 252 PCB LAYOUT COMPONENT SIDE 52760 2409 Dimension mm inches Circuits A B C D 240 84 07 3 309 75 565 2 970 80 47 3 168 78 87 3 105 DLAG part number 439003 71 DIGITAL LOGIC AG SM520PC Manual V1 1 6 2 SM520PC uses signals on the smart480 bus SM520PC Connector J1 Pin 1 40 A1 POWER VCC 5V B1 ISA 5i n c A2 ISA 50 RESDRV B2 ISA 51 IRQ5 A3 ISA 5i SBHE B3 ISA 5i IRQ3 A4 ISA 5i MEMCS16 B4 ISA 5i IRQ4 A5 ISA 5i IOCS16 B5 ISA 5i IRQ5 A6 ISA 50 IOW B6 ISA 5i n c A7 ISA 50 IOR B7 ISA 5i IRQ7 A8 ISA 50 SYSCLK B8 ISA 5i IRQ10 A9 ISA 50 TC B9 ISA 5i IRQ11 A10 ISA 50 ALE B10 ISA 51 IRQ12 A11 ISA 5 i o SD7 B11
36. 20PC Manual V1 1 2 6 BIOS History Version Date Status Modifications 1 26 2003 Serieproduction Inside BIOS 2 7 This product is YEAR 2000 CAPABLE This DIGITAL LOGIC product is YEAR 2000 CAPABLE This means that upon installation it accurately stores displays processes provides and or receives date data from into and between 1999 and 2000 and the 20 and 21 centuries including leap year calculations provided that all other technology used in combi nation with said product properly exchanges date data with it DIGITAL LOGIC makes no representation about individual components within the product should be used independently from the product as a whole You should understand that DIGITAL LOGIC s statement that an DIGITAL LOGIC product is YEAR 2000 CAPABLE means only that DIGITAL LOGIC has verified that the product as a whole meets this definition when tested as a stand alone product in a test lab but does not mean that DIGITAL LOGIC has verified that the product is YEAR 2000 CAPABLE as used in your particular situation or configuration DIGITAL LOGIC makes no representation about individual components including software within the product should they be used independently from the product as a whole DIGITAL LOGIC customers use DIGITAL LOGIC products in countless different configurations and in con junction with many other components any systems and DIGITAL LOGIC has
37. 3V A92 LAN Option LAN TX B92 ISA 5i n c A93 LAN Option LAN TX B93 ISA 5i IOCHCK A94 LAN Option LAN RX B94 ICT 3i TCK A95 LAN Option LAN RX B95 ICT 3i TDI A96 3i n c B96 ICT 3i TDO A97 CORE VCC SUSPEND 5V B97 ICT 3i TMS A98 APM 3 i o LAN SUSA B98 APM 3o VESA DDA A99 APM 3 i o LAN SUSB B99 APM 3o VESA DDC 100 3 i o GPIO2 B100 APM 3i GPIO7 A101 VGA o analoq qreen B101 VGA analoq qround 102 VGA analog blue B102 VGA Vsvnch A103 VGA o analoq red B103 VGA o Hsvnch A104 LCD 50 LCD 8104 LCD 50 LCD 105 GROUND B105 LCD 50 LCD SHCLK A106 LCD 50 LCD FLM VS B106 LCD 50 LCD LP HS A107 LCD 50 LCD 012 8107 LCD 50 LCD D0 A108 LCD 50 LCD 013 8108 LCD 50 LCD D1 109 LCD 50 LCD 014 8109 LCD 50 LCD 02 110 LCD 50 LCD 015 B110 LCD 50 LCD D3 A111 LCD 50 LCD D16 B111 LCD 50 LCD D4 A112 LCD 50 LCD D17 B112 LCD 50 LCD D5 A113 LCD 50 LCD D18 B113 LCD 50 LCD D6 A114 LCD 50 LCD D19 B114 LCD 50 LCD D7 A115 LCD 50 LCD D20 B115 LCD 50 LCD D8 A116 LCD 50 LCD D21 B116 LCD 50 LCD D9 A117 LCD 50 LCD D22 B117 LCD 50 LCD D10 A118 LCD 50 LCD D23 B118 LCD 50 LCD D11 A119 LCD 50 LCD ENABKL B119 LCD 50 LCD M A120 POWER LCD VCC OUT 3V B120 POWER CPU CORE Vcc2 Remarks 5o 5V output 5 ilo 5V input output 30 3V output 3 i o 3V input output active low signal open collector output NC not connected RES pin function depending of the CPU reserved 77 DIGITA
38. 410 800 600 24 75 49 500 1406 42 o 0 300 1710 1410 800 600 24 85 56250 1406 42 o o 300 1710 1410 awisa IA a 1024 768 16 60 65 000 1536 42 o 1840 1540 1024 768 16 70 175 000 1536 42 0 300 1840 1540 1024 768 16 75 78 750 1536 42 0 1540 IEEE NEN 1024 768 24 60 65 000 2304 2608 2308 0 0 2308 0 2308 0 0 0 0 1024 94 500 2304 2608 2308 _ j j j 0 oO E Ed 0 0 NN EN E 1280 1024 16 60 108 0 2560 42 0 300 2864 2564 0 0 0 0 0 2564 2564 2564 Exi 4144 3844 4144 3844 1280 1024 157 5 2560 p iI 1280 1024 24 60 1080 3840 42 0 1280 1024 24 72 1280 3840 42 0 1280 1024 24 75 1350 3840 42 0 0 300 4144 3844 1280 1024 24 85 1575 3840 42 0 0 300 4144 3844 means not possible resolution with the 4Mb Video RAM 57 DIGITAL LOGIC AG SM520PC Manual V1 1 3 10 6 Memory 69000 Color STN DD Panels Hor Vert JRefr DCLK jCursor FB M Video Total Resol Resol jbpp Hz Mhz kByte kByte kByte Input with w o kByte Video Video 8 60 25475 300 42 120 0 300 724 424 640 480 8 72 3150
39. 42 188 0 1898 1598 800 600 24 72 50 000 1406 42 188 0 300 1898 1598 800 600 24 75 49 500 1406 42 188 0 300 1898 1598 800 600 24 85 56250 1406 42 188 0 300 1898 1598 1024 768 16 60 165 000 1536 42 307 0 300 2147 1847 1024 768 16 70 175 000 1536 42 307 0 300 2147 1847 1024 768 16 75 78 750 1536 42 307 0 300 2147 1847 1024 768 16 85 94 500 1536 42 307 0 300 2147 1847 PERE i 1024 768 24 60 65 000 2304 42 307 0 300 2915 2615 1024 768 24 72 75 000 2304 42 307 0 300 2915 2615 1024 768 24 75 78 750 2304 42 307 0 300 2915 2615 1024 768 24 85 94 500 2304 42 307 300 2915 2615 AA II i MEA 1280 1024 16 60 1080 2560 42 512 0 3376 3676 1280 1024 16 70 1280 2560 42 512 0 3376 3676 1280 1024 16 75 135 0 2560 42 512 0 3376 3676 1280 1024 16 85 1575 2560 42 512 0 300 3376 3676 TTIR 1280 1024 24 60 1080 3840 42 512 0 300 4656 4356 1280 1024 24 72 1280 3840 42 512 0 300 4656 4356 1280 1024 24 75 1350 3840 42 512 0 300 4656 4356 1280 1024 24 85 157 5 3840 42 512 0 30
40. 75 2409 Alternatives h 6mm PCB PCB 53467 2409 7 h 7mm PCB PCB 53481 2409 SM520PC connector h 5mm MOLEX 240pin Mating connector 52760 2409 Only as reference 79 DIGITAL LOGIC AG SM520PC Manual V1 1 6 6 Thermal Specifications Each product will undergo a Burnin Test of 10 cycles of 30 min between the operating temperatures of 25 C to 70 C or higher if extended ranges are required The critical point is to meet the max Tcase temperature of the CPU This temperature is specified by 110 C for the SQFP case The tables show the allowable ambient tempera ture at various airflows and with different heatsink configurations CPU 586 case 90 C Power consumption 4W CPU frequencv Air temperature case T case T case no Airflow Airflow Airflow 0 m sec 3 m sec 6 m sec 133MHz 70 These values have to be definitely defined when having series status 80 DIGITAL LOGIC AG SM520PC Manual V1 1 7 DESIGNIN BLOCK SCHEMATICS ATTENTION Very important information for smartModule integrators 1 2 3 4 minimum schematics to operate with the smartModule 586PC is described further on Place on the 5Volt line 10x 100nF capacitors nearest possible at the powerpins Place on the 5Volt line 4 x 100uF 16V and 2 x tantal capacitors Use a separate ground and 5Volt plane in the OEM P
41. AM MWEA B119 ISA 3o BIOSCS A120 DRAM 3o MWEB B120 POWER VCC 5 Volt Remarks 5o 5V output 5 5V input output 3o 3V output 3 i o 3V input output active low signal open collector output NC not connected RES pin function depending of the CPU reserved The memorybus may only used if no onboard DRAM module ist used Ask for application schematics 74 DIGITAL LOGIC AG SM520PC Manual V1 1 SM520PC Connector J2 Pin 1 40 A1 50 strobe B1 COM1 50 1 2 PRINTER 50 auto B2 COM1 5i DSR1 PRINTER 50 error B3 COM1 5i RXD1 A4 PRINTER 5o init B4 COM1 50 RTS1 5 PRINTER 50 slctin B5 COM1 50 TXD1 6 PRINTER 5 i o PRINTER data 0 B6 COM1 5i CTS1 PRINTER 5 i o PRINTER data 1 B7 COM1 50 DTR1 A8 PRINTER 5 i o PRINTER data 2 B8 COM1 5i 9 PRINTER 5 i o PRINTER data 3 B9 COM2 5o DCD2 A10 PRINTER 5 i o PRINTER data 4 B10 COM2 5i DSR2 A11 PRINTER 5 i o PRINTER data 5 B11 COM2 5i RXD2 A12 PRINTER 5 i o PRINTER data 6 B12 COM2 50 RTS2 A13 PRINTER 5 i o PRINTER data 7 B13 COM2 50 TXD2 A14 PRINTER 5i acknowledqe B14 COM2 5i CTS2 A15 PRINTER 5i busy B15 COM2 50 DTR2 A16 PRINTER 5i paper end B16 COM2 RI2 17 51 B17
42. BIGITAL L eGIC smart embedded computers TECHNICAL USER S MANUAL FOR SmartModule SM520PC Nordstrasse 11 F CH 4542 Luterbach Tel 41 0 32 681 58 00 Fax 41 0 32 681 58 01 support digitallogic com Homepage http www digitallogic com DIGITAL LOGIC AG SM520PC Manual V1 1 COPYRIGHT 1999 2003 BY DIGITAL LOGIC AG No part of this document may be reproduced transmitted transcribed stored in a retrieval system in any form or by any means electronic mechanical optical manual or otherwise without the prior written permis sion of DIGITAL LOGIC AG The software described herein together with this document are furnished under a license agreement and may be used or copied only in accordance with the terms of that agreement ATTENTION All information in this manual and the product are subject to change without prior notice REVISION HISTORY Prod Serialnumber Product BIOS Doc Date Vis Modification m To sss Version Remarks News Attention 02 2003 KUF 05 2003 Version Preliminary i26 V 105208DAR l PRODUCT REGISTRATION Please register your product under http www digitallogic com gt SUPPORT After registration you will receive driver amp software updates errata information customer information and news from DIGITAL LOGIC AG products automatically DIGITAL LOGIC AG SM520PC Manual V1 1 Table of Contents 1 3 Ld eo
43. CB If 3 3V DRAM extension are used integrate a 3 3V powerplane to supply the DRAMs and other 3 3V parts The 3 3V supply may be loaded with max 300mA Place also on the 3 3V plane 5 to 10 x 100nF and 2 x 100pF capacitors nearest possible to the supply pins of each components Place the DRAMs directly under the smartModule To meet all EMI EMC parameters place on every peripheral line go to external cables ferrite and a 47pF capacitor to ground All generic pullup resistor should be 10k typ All generic buffers are recommended to be 74HCT245 244 or 74ABT245 244 type If using SODIMM s please refer to our overview list which is also on our CD Cleaning the contacts on the SODIMM and the socket with e g pure alcohol is highly recommended to may eliminate memory er rors For any questions we are providing a Designin support Please fill out the form in chapter 1 6 to initialize a Designln support 81 DIGITAL LOGIC AG SM520PC Manual V1 1 7 1 The Chipsset 520 from 7 1 1 Architecture overview This chapter is intended to provide vou with all the informations vou mav need if vou want to extend the basic SM520 design like using more DRAM or connecting a varietv of peripherals using the interfaces provided bv the smart module itself The interfaces to SM520PC X can be further divided like this Power supply DRAM bus connected to North Bridge of ELAN520 ISA Bus can be designed as PC 104 stan
44. DRAM 3 i o MD17 B68 DRAM 50 SD CLK2 A69 DRAM 3 MD18 B69 DRAM 50 SD A70 DRAM 3 MD19 B70 DRAM 50 SD CKE1 AT1 DRAM 3 MD20 B71 DRAM 50 5 A72 DRAM 3 MD21 B72 DRAM 50 5 A73 DRAM 3i o MD22 B73 DRAM 50 S RASA A74 DRAM 3 i o MD23 B74 DRAM 50 S CASB A75 DRAM 30 875 DRAM 50 n c 76 DRAM 30 MA1 B76 DRAM 50 n c A77 DRAM 3o MA2 B77 DRAM 50 n c 78 DRAM 30 MA3 B78 DRAM 50 5 DCLK0 A79 DRAM 3o MA4 B79 DRAM 50 S DCLK1 A80 DRAM 3o 5 880 CORE 30 24MHz Output Remarks 5V output 5 ilo 5V input output 30 3V output 3 i o 3V input output active low signal o c open collector output NC not connected RES pin function depending of the CPU reserved The memorybus may only used if no onboard DRAM module ist used Ask for application schematics 73 DIGITAL LOGIC AG SM520PC Manual V1 1 SM520PC Connector J1 Pin 81 120 Pin Group 5 5 Pin Group Vot 5 5 A81 DRAM 30 MA 6 B81 POWER Ground A82 DRAM 30 MA 7 882 DRAM 3 i o MD48 A83 DRAM 30 8 B83 DRAM 3 i o MD49 A84 DRAM 3o MA 9 884 DRAM 3 i o MD50 A85 DRAM 3o MA 10 B85 DRAM 3i o MD51 A86 DRAM 3o MA 11 B86 DRAM 3 i o MD52 A87 DRAM 3o MA
45. Eunction READ PRODUCTION DATE Number E5h Description Reads the production date from the board in the serial EEPROM Input Values AH E5h Function Request Output Values BX Year 1997 gt BH 19 BL 97 CH Month 1 12 CL Day of Month 1 31 61 DIGITAL LOGIC AG SM520PC Manual V1 1 3 12 Remote function Remote works only with the COM 1 port on the SM520PC BIOS default settings are normally as follows Internal ELAN COM1 Internal ELAN B NONE SUPER I O NONE SUPER I O D COM 2 3 13 Remote Features FS FORTH SYSTEME has added its remote package Embedded Support Kit to the AMD ElanSC520 BIOS The Embedded Support Kit allows you to control your target machine from a host computer using ei ther a serial or parallel null modem cable This is accomplished by transferring all INT10h video and INT16h keyboard requests to the host machine executing the command there and finally returning the results back to the target system The target system seems to behave just like it would use its own VGA card and keyboard but in fact it uses the resources of the host computer Additionally the target can access the floppy drive and the harddisk of your host PC These features are of great value when you bring up your own board for the first time In embedded systems typical PC components are often left away to save costs A standard BIOS typically would stop and warn the user that devices are missing The BIOS has been modified
46. IOS More details are available in the separate BIOS manual on our CD and homepage 9 SAMPLES ScHEMATICS SMxxPC DK On the following pages one will see the schematic for the SM520PC development kit 91 DIGITAL LOGIC AG SM520PC Manual V1 1 i pl fem ee Foo i Fen e Foo 4 elles 25352505522 LAN and IDE LEDs PREH 000020201202220202 y SESUSEREPSEPUESS iiti Free selection for PCI LAN Slot PC 1044 settings PC 104 PCI Slot ST OT n ti 221 Ethernet controller Smartmodule PCI configuration for LAN and extension slot I i tii i jii 5 rH 53 a gi 8 92 DIGITAL LOGIC AG SM520PC Manual V1 1 POWER button E e i i x E I i i EEG i t i i A nil Pg d 2 1 Battery Utility JTAG and RES connectors MSM_DK USB Con HHHP Serial ports DUAL USB port VGA Video input DIGITAL LOGIC AG SM520PC Manual V1 1 connector connector nien SDRAM extension on DK IDE secondary 2 5Inch MSM DK P5 P3 IDE only for Smart IDE primary 2 5Inch IDE primary 3 5Inch PS 3 5Inch rima SM58 torti Floppv connector E 8 5 5 z 5 8 5 a IDE primary 3 5Inch Smart
47. ISA 5i IRQ14 A12 ISA 5 i o SD6 B12 ISA 5i IRQ15 A13 ISA 5 i o 505 813 51 COREBIOS Enable 14 ISA 5 i o SD4 B14 CORE 5i VGABIOS ENABLE 15 ISA 5 i o SD3 B15 ISA 50 LA21 A16 ISA 5 i o SD2 B16 ISA 50 LA20 A17 ISA 5 i o SD1 B17 ISA 50 LA19 18 ISA 5 i o SD0 B18 ISA 50 LA18 A19 ISA 50 IOCHRDY B19 ISA 50 LA17 20 ISA 50 B20 ISA 5 i o SD8 21 ISA 50 SA19 B21 ISA 5i o SD9 22 ISA 50 SA18 B22 ISA 5 i o SD10 A23 ISA 50 SA17 B23 ISA 5 i o SD11 A24 ISA 50 SA16 B24 ISA 5 i o SD12 A25 ISA 50 SA15 B25 ISA 5 i o SD13 A26 ISA 50 SA14 B26 ISA 5 i o SD14 A27 ISA 50 SA13 B27 ISA 5 i o SD15 A28 ISA 50 SA12 B28 ISA 5i DRQ 0 A29 ISA 50 SA11 B29 ISA 5i DRQ 1 A30 ISA 50 SA10 B30 ISA 5i DRQ 2 A31 ISA 50 SA9 B31 ISA 5i DRQ 3 A32 ISA 50 SA8 B32 ISA 5i n c A33 ISA 50 SA7 B33 ISA 5i n c A34 ISA 50 SAG B34 ISA 50 OSC 14 31 2 A35 ISA 50 5 5 835 ISA 50 DMAO A36 ISA 50 SA4 B36 ISA 50 DMA1 A37 ISA 50 SA3 B37 ISA 50 DMA2 A38 ISA 50 SA2 B38 ISA 50 DMA3 A39 ISA 50 SA B39 ISA 50 DMA5 A40 ISA 50 SAO B40 ISA 50 DMA6 These signals LA17 LA19 correspond with the SA17 SA19 Remarks 5o 5V output 30 3V output active low signal 5 5V input output 3 i o 3V input output o c open collector output RES pin function depending of the CPU reserved NC not connected 72 DIGITAL LOGIC AG SM520PC Manual V1 1 SM520PC Connector J1 Pin 41 80
48. L LOGIC AG SM520PC Manual V1 1 6 3 LCD Interface Signaldefinition Pin LCD Mono Mono Mono TFT TFT HR STN STN TFT 480BUS Line SS 8Bit DD 8Bit DD 16Bit 9 12 16Bit 18 24Bit 18 24Bit DD 8Bit DD 36Bit 16Bit B107 DO UD3 UD7 BO BO B00 R1 0 B108 D1 UD2 UD6 B1 B1 B01 G1 UGO 1 B109 D2 001 005 B2 B2 B02 B1 UBO 2 B110 D3 UDO UD4 B3 B3 B03 R2 UR1 O B3 B111 D4 LD3 UD3 B4 B4 B10 G2 LRO 4 B112 D5 LD2 UD2 GO B5 B11 B2 LGO 5 B113 D6 LD1 UD1 G1 B6 B12 R3 LB0 E B0 B114 D7 z LDO UDO G2 B7 B13 G3 LR1 E B1 B115 D8 PO LD7 G3 G0 G00 B3 UG1 E B2 B116 D9 P1 E LD6 G4 G1 G01 R4 UB1 E B3 B117 D10 P2 z LD5 G5 G2 G02 G4 UR2 4 B118 D11 P3 LD4 RO G3 G03 B4 UG2 E B5 A107 D12 P4 LD3 R1 G4 G10 R5 LG1 O G0 A108 D13 P5 LD2 R2 G5 G11 G5 LB1 O G1 A109 D14 P6 LD1 R3 G6 G12 B5 82 O G2 110 015 7 5 LDO R4 G7 G13 R6 LG2 O G3 A111 D16 5 RO R00 O G4 A112 D17 i E R1 R01 O G5 A113 D18 z a R2 R02 E G0 A114 D19 z R3 R03 B E G1 A115 D20 I R4 R10 I E G2 A116 D21 z z E R5 R11 3 E G3 117 022 R6 R12 E E G4 A118 D23 I R7 R13 a E G5 A81 D24 O RO A82 D25 O R1 A83 D26 O R2 A84 D27 O R3 A85 D28 O R4 A86 D29 O R5 A87 D30 E RO A88 D31 E R1 B40 D32 E R2 B43 D33 E R3
49. L LOGIC AG SM520PC Manual V1 1 CMOS Map Continued MTENNI 3 bits 7 6 Reserved bits 5 0 Upper 6 Bits of Write Precompensation Bvte 4 bits 7 0 Number of Heads Bvte 5 bits 7 0 Sectors Per Track Boot Password bit 7 Enable Disable Password 0 Disable Password 1 Enable Password bits 6 0 Calculated Password SCU Password bit 7 Enable Disable Password 0 Disable Password 1 Enable Password bits 6 0 Calculated Password Base Memory Installed bit 7 Flag for Memory Size 0 640KB 1 512KB bits 6 0 Reserved Minor CPU Revision Differentiates CPUs within a CPU type i e 486SX vs 486 DX vs 486 DX 2 This is crucial for correctly determining CPU input clock frequency During a power on reset Reg DL holds minor CPU revision Major CPU Revision Differentiates between different CPUs i e 386 486 Pentium This is crucial for correctly determining CPU input clock fre quency During a power on reset Reg DH holds major CPU revision Hotkey Usage bits 7 6 Reserved bit 5 Semaphore for Completed POST bit 4 Semaphore for 0 Volt POST not currently used bit 3 Semaphore for already in SCU menu bit 2 Semaphore for already in PM menu bit 1 Semaphore for SCU menu call pending bit 0 Semaphore for PM menu call pending Definitions for these locations vary depending on the chipset 28 DIGITAL LOGIC AG SM520PC Manual V1 1 3 6 EEPROM saved CMOS Setup The EEPROM has different func
50. Temporary storage for additional page register ll ia checkpoints Continued 37 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status 00A1h are reserved for the slave programmable interrupt controller The bit definitions are identical to those of addresses 0020h 0021h except where indicated 00AO0h Programmable interrupt controller 2 00A1h R W Programmable interrupt controller 2 mask bit 7 0 Reserved bit 6 0 Enable hard disk interrupt bit 5 0 Enable coprocessor execution interrupt bit 4 0 Enable mouse interrupt bits 3 2 0 Reserved bit 1 0 Enable redirect cascade bit 0 0 Enable real time clock interrupt 00DOh Status register for DMA channels 4 7 bit 7 1 Channel 7 request bit 6 1 Channel 6 request bit 5 1 Channel 5 request bit 4 1 Channel 4 request bit 3 1 Terminal count on channel 7 bit 2 1 Terminal count on channel 6 bit 1 1 Terminal count on channel 5 bit 0 1 Terminal count on channel 4 00D0h register for channels 4 7 bit 7 DACK sense active low DACK sense active high bit 6 DREQ sense active low DREQ sense active high bit 5 Late write selection Extended write selection bit 4 Fixed Priority Rotating Priority bit 3 Normal Timing Rotating Timing bit 2 Enable controller 1 Disable controller bit 1 0 Disable memory to memory transfer 1 Enable memory to memory transfer bit 0 Reserved Continued O O O O
51. _3S DEVSEL None 10 K pull up to V_3S IRDY None 10 K pull up to V_3S TRDY None 10 K pull up to V_3S STOP None 10 K pull up to V_3S REQ 4 0 None 10 K pull up to V_3S if unused GNT 4 0 None 10 K pull up to V 3S if used PHOLD None 10 K pull up to V_3S PHLDA None 10 K pull up to V_3S PAR None None SERR None 10 K pull up to V_3S CLKRUN None 8 2 10 K pull up to V_3S PCIRST 33 see Bus Signals None PLOCK None 10 K pull up to V_3S 84 DIGITAL LOGIC AG 7 1 6 PCI Signal Descripitons SM520PC Manual V1 1 Name Type Voltage Description AD 31 0 1 0 V_3 Address Data The standard PCI address and data lines The address PCI is driven with FRAME assertion and data is driven or received in following clocks 3 0 7 1 0 V_3 Command Byte Enable The command is driven with asser PCI tion and bvte enables corresponding to supplied or requested data are driven on the following clocks FRAME 1 0 V_3 Frame Asseriton indicates the address phase of a PCI transfer Nega PCI tion indicates that one more data transfers are desired by the cycle initiator DEVSEL 1 0 V_3 Device Select This signal is driven by the 443TX Host Bridge when a PCI PCI initiator is attempting to access DRAM DEVSEL is asserted at medium decode time IRDY 1 0 V3 Initiator Ready Asserted when the initiator is ready for data transfer PCI TRDY 1 0 V_3 Target Ready Asserted when th
52. al time video acceleration This additional bandwidth also allows more flexibility in the other graphics functions intensely used in Graphics User Interface GUIs such as Microsoft Win dows Versatile Panel Support The 69000 support a wide varety of monochrome and color Single Panel Single Drive SS and Dual Panel Dual Drive DD standard and high resolution passive STN and active matrix TFT MIM LCD and EL pan els With HiQColor technology up to 256 gray scales are supported on passive STN LCDs Up to 16 7M different colors can be displayed on passive STN LCDs and up to 16 7M colors on 24bit active matrix LCDs The 69000 offers a varety of programmable features to optimize display quality Vertical centering and streching are provided for handling modes with less than 480 lines on 480 line panels Horizontal and vertical streching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800x600 1024x768 and 1280x1024 panels Low Power Consumption The 69000 uses a variety of advanced power management features to reduce power consumption of the display sub system and to extend battery life optimized for 3 3V operation the 69000 internal logic bus and panel interfaces operate at 3 3V but can tolerate 5V operation Software Compatibility Flexibility The 69000 is fully compatible with the VGA standard at both the register and BIOS levels DIGITAL LOGIC supply a full
53. byte along with the high byte 03F9h store the data transmission rate divisor bits 7 0 Data bits 0 7 when the Divisor Latch Access Bit DLAB is 1 Baud rate divisor high byte This byte along with the low byte 03F8h store the data transmission rate divisor bits 7 0 Bits 8 15 when DLAB 1 Interrupt enable register bits 7 4 Reserved bit 3 Modem status interrupt enable bit 2 Receiver line status interrupt enable bit 1 Transmitter holding register empty inter rupt enable bit 0 Received data available interrupt enable when DLAB 0 Interrupt identification register serial port 1 bits 7 3 Reserved bits 2 1 Identify interrupt with highest priority 00 Modem status interrupt 4th priority 01 Transmitter holding register empty 3rd priority 10 Received data available 2nd priority 11 Receiver line status interrupt 1st priority bit 0 0 Interrupt pending register contents can be used as a pointer to interrupt ser vice routine 1 No interrupt pending Line control register serial port 1 bit 7 Divisor Latch Access DLAB 0 Access receiver buffer transmitter hold ing register and interrupt enable register 1 Access divisor latch 1 Set break enable Forces serial output spacing state and remains Stick parity Even parity select Parity enable Number of stop bits Word length 00 5 bit word length 01 6 bit word length 10 7 bit word length 11 8 bit word length Modem control register
54. dard connection PCI Bus 2 1 compliant 33MHz and internal PCI masters like USB and IDE Devices connected to Super lO integrated in SM520PCX like Keyboard Mouse Serial and parallel port Infrared devices Floppy Disk General Purposes The following figure show the available interfaces to the SM520PC X PCI Interface IDE IDE 2x PCI Interface Controller Bridge USB USB Controller Interface Internal X Bus ISA Bus Keyboarc amp Legacy PIC Key amp Mouse amp PIT Controller Interface Interface Floppy GPIO Power Man amp Floppy Disk Disk Interface GPIO Controller Interface Parallel IEEE 1294 2 Bus 2 Interface Controller Controller Interface Acoass Bus Serial amp Two 16550 Real time IR UARTS amp IR Clock Interface ISA Interface The ELAN520 is a complete pc in a chip solution as you can be seen in chapter xxx That means that only standard elements required to reach functionality are power supply and interface connectors to SM480Bus In the following chapters the basic connectors and power supply you need are described further on 82 DIGITAL LOGIC AG SM520PC Manual V1 1 In case additional feature for the SM520PCX carrier board should be needed like additional DRAM devices on ISA or PCI bus the following chapters provide basic schematics like the one to be found on Digital Logic product using SM520PCX as a core unit 7 1 2 DRAMI Interface Th
55. e DRAM interface is a 32 bit data path that supports Synchronous DRAM SDRAM memory The DRAM controller inside the Chipset is capable of generating 3 1 1 1 for posted writes for any type of DRAM that is used While read performance is 6 1 1 1 for SDRAM 7 1 3 PCI Interface The PCI interface is 2 1 compliant and supports up to four PCI bus masters in addition to the Southbridge bus master requests 83 DIGITAL LOGIC AG SM520PC Manual V1 1 7 1 4 PCI Bus Signals The smartModule supports 3 3 and 5V PCI An 8 2 10 KO pull up to V 3S should be placed on the CLKRUN signal 7 1 5 Design Considerations The smartModule supports up to four PCI masters with its REQ 3 0 GNT 3 0 pairs The PCI bus supports up to 10 PCI loads PCI components soldered on the motherboard add one load each and each PCI con nector adds approximately 2 loads A design with four PCI slots and no motherboard devices uses all avail able PCI loads When all four REQ 3 0 Z GNT 3 0 pairs are used simulation is required to ensure that the PCI Bus Specification Rev 2 1 timings are met lt is recommended per PCI specification that the design have series resistors 1000 on each of the PCI connector IDSEL lines PCI Bus Signals Resistor Values Name Termination Resistor Pull up Pull down Resistor Q ex ternal used AD 31 0 None None C BE 3 0 None None FRAME None 10 K pull up to V
56. e target is ready for a data transfer PCI Stop 1 0 V_3 Stop Asserted by the target to request the master to stop the current PCI transaction 85 DIGITAL LOGIC AG SM520PC Manual V1 1 PCI Signal Descriptions continued Name Type Voltage Description PLOCK V_3 Lock Indicates an exclusive bus operation and may require multiple PCI transactions to complete When LOCK is asserted non exclusive transactions may proceed The 443TX supports lock for CPU initiated cycles only PCI initiated locked cycles are not supported REQI4 0 V3 PCI Hold PCI master requests for PCI PCI GNT 4 0 V3 PCI Grant Permission is given to the master to use PCI PCI PHOLD V_3 PCI Hold This signal comes from the expansion bridge it is the bridge PCI request for PCI The 443TX Host Bridge will drain the DRAM write buff ers drain the processor to PCI posting buffers and acquire the host bus before granting the request via PHLDA This ensures that GAT timing is met for ISA masters The PHOLD protocol has been modified to include support for passive release PHLDA V_3 PCI Hold Acknowledge This signal is driven by the 443TX Host Bridge PCI to grant PCI to the expansion bridge The PHLDA protocol has been modified to include support for passive release PAR V3 Parity A single parity bit is provided over AD 31 0 and C BE 3 0 PCI SERR 1 0 V_3 System Error The 443TX asserts this signal to ind
57. esistor Pull up pull down Resistor Q SAD15 0 None 10 K Pull up to V_3S MEMR None 1 K Pull up to V_3S MEMW None 1 K Pull up to V_3S IOR None 1 K Pull up to V_3S IOW None 1 K Pull up to V_3S IOCS16 None 1 K Pull up to V_3S IOCHRDY None 1 K Pull up to V_3S MEMCS16 None 1 K Pull up to V_3S REFRESH None 1 K Pull up to V_3S ZEROWS None 1 K Pull up to V_3S IRQx None 10 K Pull up to V_3S see above DRQx None 4 7 K Pull down SIRQ None 10 K Pull up to V_3S IOCHK None 4 7 K Pull up if using ISA bus 89 DIGITAL LOGIC AG SM520PC Manual V1 1 7 7 USB Interface 7 8 IDE Interface e 5 6 pull down resistors on PDDREQ and SDDREQ e 1 KQ pull up resistors on PIORDY and SIORDY e 470 KO pull down resistors on pin 28 of the IDE connector CSEL Support Cable Select CSEL is a 97 requirement The state of the cable select pin determines the master slave configuration of the hard drive at the end of the cable e The primary IDE connector uses IRQ14 and the secondary IDE connector uses IRQ15 e The ATA 4 specification requires 33 series terminating resistors on P SDIOR P SDIOW P SDCS 1 3 P SDA 2 0 P SDDACK and P SDD 15 0 These series termination resistors should be placed as close as possible to the PIIX4E e For Ultra DMA enabled systems the ATA 4 specification also requires 82 series termination resistors on P SDDREQ INTRQx and P SIORDY These series terminating resistors should be
58. essing 32 lines Virtual Addressing 128 Mbvtes Clock Rates 133 MHz selectable Math Coprocessor Available on the CPU Power Management available Defined bv the BIOS 8237A comp 2 channels 8 Bits 8259 comp 8 2 levels PC compatible 8254 comp 3 programmable counter timers DRAM SODIMM32Bit 144pin holder 16 128Mbyte 32Bit BUS external expandable up to 256Mbyte Controller 69000 PCI BUS CRT 2Mbyte LCD up to 1024 x 768 x 256 colors Panel TFT 24Bit STN EL Plasma Mass Storage FD Floppy disk interface for max 2 floppy HD IDE interface AT Type for max 2 harddisks Flashdisk Optional 2Mbyte with FFS onmodule expandable up to 8MByte DIGITAL LOGIC AG SM520PC Manual V1 1 Standard AT Interfaces Serial Device Name COM1 yes 4 3F8 COM2 es IRQ3 2F8 Baudrates 50 115 KBaud programmable Parallel LPT1 printer interface Modes SPP output EPP bidir Keyboard AT or PS 2 keyboard Mouse PS 2 Speaker 0 1 W output drive RTC Integrated into the with CMOS RAM 256byte Backup current 5 at 3V Battery Not assembled Watchdog LTC1232 with power fail detection strobe time max 1 sec ISA 996 standard bus Clock 8 MHz PC 104plus IEEE 996 standard bus buffered Clock 8 MHz defined by the Southbrisge USB 2 Channels DRAM SDRAM 32Bit Power Supply Working 5 Volts 596 3 3V onboard switch mode regulator Power Rise Time gt 100us 0V 4 75V Physical C
59. g table lists the contents of the BIOS data area loca tions in offset order starting from segment address 40 00h 1oh 11h Equipment list bits 15 14 Number of parallel printer adapters 00 Not installed 01 One 10 Two 11 Three bits 13 12 Reserved bits 11 9 Number of serial adapters 00 Not installed 001 One 010 Two 011 Three 100 Four Reserved Number of diskette drives 00 One drive 01 Two drives Initial video mode 00 EGA or PGA 01 40 x 25 color 10 80 x 25 color 11 80 x 25 monochrome Reserved 1 Pointing device present 1 Math coprocessor present 1 Diskette drive present Reserved for port testing by manufacturer bits 7 1 Reserved bit 0 0 Non test mode 1 Test mode 12h Memory size in kilobytes low byte Memory size in kilobytes high byte Continued 47 DIGITAL LOGIC AG SM520PC Manual V1 1 BIOS Data Area Definitions continued Keyboard Shift Qualifier States bit 7 Insert mode bit 6 CAPS lock bit 5 Numlock bit 4 Scroll Lock bit 3 Either Alt key bit 2 Either control key bit 1 Left Shift key bit 0 Right shift key 0 not set 1 set Keyboard Toggle Key States bit 7 1 Insert held down bit 6 1 CAPS lock held down bit 5 1 Num Lock held down bit 4 1 Scroll Lock held down bit 3 1 Control Num Lock held down bit 2 1 Sys Re held down bit 1 1 Left Alt held down bit 0 1 Left Control held down Diskette Drive Recalibration Flag bit 7 1
60. haracteristics Dimensions Length 85 mm 0 1mm Depth 66 mm 0 1mm Height 16 mm 4 0 2mm with 5mm bus connectors Weight 90 gr 9 ounces PCB Thickness 1 6 mm 0 0625 inches nominal PCB Layer Multilayer Operating Environment Relative Humidity 5 9096 non condensing Vibration 5 to 2000 Hz Shock 10G Temperature Operating Standard version 133MHz 25 C to 0 C Extended version 40 C to 85 C T B D Storage 55 C to 85 C 12 DIGITAL LOGIC AG EMI EMC IEC1131 2 refer MIL 461 462 ESD Electro Static Discharge REF Radiated Electromagnetic Field EFT Electric Fast Transient Burst SIR Surge Immunity Requirements High frequency radiation SM520PC Manual V1 1 IEC 801 2 EN55101 2 VDE 0843 0847 Part 2 metallic protection needed separate Ground Layer included 15 kV single peak IEC 801 3 VDE 0843 Part 3 IEC770 6 2 9 not tested IEC 801 4 EN50082 1 VDE 0843 Part 4 250V 4kV 50 ohms Ts 5ns Grade 2 Supply 500 I O 5Khz IEC 801 5 IEEE587 VDE 0843 Part 5 Supply 2 kV 6 pulse minute 500 V 2 pulse minute FD CRT none 55022 Any information is subject to change without notice 2 5 Ordering Codes SM520PC SM520PCX SM520PCN SMxxPC DK 32 smartModule520PC 133MHz Video OMByte smartModule520PC 133MHz Video LAN OMbvte smartModule520PC 133MHz no Video no LAN OMByte smartModulexxPC Development Kit with 32Mbvte DRAM 13 DIGITAL LOGIC AG SM5
61. hard status register Copy of hard drive error register 8Ch 8Dh 8Eh Hard drive interrupt flag 8Fh Diskette controller information bit 7 Reserved bit 6 1 Drive confirmed for drive B bit 5 1 Drive B is multi rate bit 4 1 Drive B supports line change bit 3 Reserved bit 2 1 Drive determined for drive A bit 1 1 Drive B is multi rate bit 0 1 Drive B supports line change 90h 91h Media type for drives bits 7 6 Data transfer rate 00 500 KBS 01 300 KBS 10 250 KBS 1 Double stepping required when 360K diskette inserted into 1 2MB drive 1 Known media is in drive Reserved Definitions upon return to user applications 000 Testing 360K in 360K drive 001 Testing 360K in 1 2 MB drive 010 Testing 1 2 MB in 1 2 MB drive 011 Confirmed 360K in 360K drive 100 Confirmed 360K in 1 2 MB 101 Confirmed 1 2 MB in 1 2 MB drive 111 720K in 720K drive or 1 44 MB in 1 44 M drive Uquid H H H H I Continued 51 SM520PC Manual V1 1 DIGITAL LOGIC AG SM520PC Manual V1 1 BIOS Data Area Definitions continued 92h 93h Scratch area for diskette media Low byte for drive A high byte for drive B 94h 95h Current track number for both drives Low byte for drive A high byte for drive B 96h Keyboard Status bit 7 1 Read ID bit 6 1 Last code was first ID bit 5 1 Force to Num Lock after read ID bit 4 1 Enhanced keyboard installed bit 3 1 Right ALT key active bit 2 1 Right Co
62. icate an error condi PCI tion Please refer to the Intel 430TX AGPset datasheet Order Number 290633 001 for further information CLKRUN 10D V3 Clock Run An open drain output and also an input The 443TX Host PCI Bridge requests the central resource PIIXAE to start or maintain the PCI clock by asserting CLKRUN The 443TX Host Bridge tri states CLKRUN upon deassertion of Reset since CLK is running upon deas sertion of Reset PCI V3 Reset When asserted this signal asynchronously resets the 443TX CMOS Host Bridge The PCI signals also tri state compliant with PCI Rev 2 1 specifications 86 DIGITAL LOGIC AG SM520PC Manual V1 1 7 2 Powermanagement The ELAN520 has no implemented Powermanagement system 7 3 Clocks Series matching resistors are required Resistor Value 10 ohms Placement As near as possible to the driver pin less than 1 7 4 ITP JTAG Signals Name Type Voltage Description TDO O V_CPUPU JTAG Test Data Out Serial output port TAP instructions and data are shifted out of the processor from this port TDI V_CPUPU Test Data In Serial input port TAP instructions and data are shifted into the processor from this port TMS V_CPUPU JTAG Test Mode Select Controls the TAP controller change se quence TCLK V CPUPU JTAG Test Clock Testability clock for clocking the JTAG bound arv scan sequence TRST V CPUPU JTAG Test Reset
63. inued 32 DIGITAL LOGIC AG SM520PC Manual V1 1 Ad Read Write Description dress Status DMA channel 0 3 command register ES bit 7 Oo bit 6 I bit 5 bit 4 bit 3 Queis epe isis bit 2 bit 1 I 20zZ20 bit 0 iming DACK sense active high low low high REQ sense active high low low high rite selection Late write selection Extended write selection riority Fixed Rotating Normal Rotating ontroller enable disable Enable Disable emory to memory enable disable Disable Enable Reserved 0009h w DMA write request register DMA channel 0 3 mask register bits 7 3 Reserved bit 2 0 1 Clear bit Set bit bits 1 0 Channel Select 00 01 10 11 Channel 0 Channel 1 Channel 2 Channel 3 DMA channel 0 3 mode register bits 7 6 00 01 10 11 Demand mode Single mode Block mode Cascade mode 0 Address increment select 1 Address decrement select 0 Disable auto initialization 1 Enable auto initialization Operation type 00 01 10 11 Verify operation Write to memory Read from memory Reserved Channel select 00 01 10 11 Channel 0 Channel 1 Channel 2 Channel 3 Continued 33 DIGITAL LOGIC AG SM520PC Manual V1 1 dress Status register Continued Programmable Interrupt Controller Initialization Command Word 1 ICW1 provided b
64. it 4 1 bits 7 5 000 Used only in 8080 or 8085 mode bit 4 1 ICW1 is used bit 3 0 Edge triggered mode 1 Level triggered mode 0 Successive interrupt vectors separated by 8 bytes 1 Successive interrupt vectors separated by 4 bytes 0 Cascade mode 1 Single mode 0 ICW4 not needed 1 ICW4 needed Used for ICW2 ICW3 or ICW4 in sequential order af terlCW1 is written to port 0020h ICW2 bits 7 3 Address A0 A3 of base vector address for interrupt controller bits 2 0 Reserved should be 000 ICW3 for slave controller 00A1h bits 7 3 Reserved should be 0000 bits 2 0 1 Slave ID ICW4 bits 7 5 bit 4 bit 2 bit 1 bit 0 Reserved should be 000 0 No special fully nested mode 1 Special fully nested mode Mode 00 01 bits 3 2 Non buffered mode Non buffered mode 10 Buffered mode slave 11 Buffered mode master 0 Normal EOI 1 Auto EOI 0 8085 mode 1 8080 8088 mode 34 DIGITAL LOGIC AG SM520PC Manual V1 1 Ad Read Write Description dress Status O Continued PIC master interrupt mask register OCW1 bit 7 Enable parallel printer interrupt bit 6 Enable diskette interrupt bit 5 Enable hard disk interrupt bit 4 Enable serial port 1 interrupt bit 3 Enable serial port 2 interrupt bit 2 Enable video interrupt bit 1 Enable kybd pointing device RTC inter rupt bit 0 Enable interrupt timer PIC OWC2 if bits 4 3 0 bit 7 Reserved bi
65. l port 4 See the bit defini tions for I O addresses 03F8h 03FFh Continued 41 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status I O addresses 02F8h 02FFh are reserved for use with serial port 2 See the bit defini tions for I O addresses 03F8h O3FFh C CA 7177 7777 Baud rate divisor low byte when DLAB 1 Baud rate divisor high byte when DLAB 1 U matur O T umama jew s ere n 0300h R W LAN controller if installed 031Fh I O addresses 0372h 0377h are reserved for use with a secondary diskette controller See the bit definitions for O3F2h 03F7h Digital output register for secondary diskette drive control Select register for secondary diskette data transfer rate Data port for parallel port 1 Status port for parallel port 1 bit 7 0 Busy bit 6 0 Acknowledge bit 5 1 Out of paper bit 4 1 Printer is selected bit 3 0 Error bit 2 0 IRQ has occurred bit 1 0 Reserved Continued 42 DIGITAL LOGIC AG SM520PC Manual V1 1 Ad Read Write Description dress Status 037Ah R W Control port for parallel port 1 bits 7 5 Reserved bit 4 Enable IRQ bit 3 Select printer bit 2 Initialize printer bit1 Automatic line feed bit 0 Strobe O3BOh Various video registers 03B8h I O addresses 03BCh 03BEh are reserved for use with parallel port 3 See the bit defi
66. nitions for addresses 0378h 037Ah O3BCh Data port parallel port 3 03BDh Status port parallel port 3 Control port parallel port 3 R W Video subsvstem EGA VGA 03C2h R W Various CGA and CRTC registers 03D9h 03E0h PCCARD Address select 03E1h PCCARD Data transfer with 365SL controller I O addresses 03E8h 03EFh are reserved for use with serial port 3 See the bit defini tions for addresses 03F8h L e sam arp ei pot Baud rate divisor low byte when DLAB 1 Baud rate divisor high byte when DLAB 1 mm e Cr AAN D S Fees TT 03F2h W Digital output register for primary diskette drive controller bits 7 6 0 Reserved bit 5 1 Enable drive 1 motor bit 4 1 Enable drive 0 motor bit 3 Enable diskette DMA bit 2 Reset controller bit 1 Reserved bit 0 Select drive 0 Select drive 1 Continued 43 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status Status register for primary diskette drive controller d 3 bit 7 1 bit 6 0 1 bit 5 1 bit 4 1 bits 3 2 R bit 1 1 bit 0 1 Data register is ready Transfer from system to controller Transfer from controller to system Non DMA mode Diskette drive controller is busy eserved Drive 1 is busy Drive 0 is busy 03F5h Rw Data register for primary diskette drive controller Control port for primary diskette drive controller bits 7 4 Reser
67. no way to test whether all those configurations and systems will properly handle the transition to the year 2000 DIGITAL LOGIC en courages its customers and others to test whether their own computer systems and products will properly handle the transition to the year 2000 The only proper method of accessing the date in systems is indirectly from the Real Time Clock via the BIOS The BIOS in DIGITAL LOGIC computerboards contains a century checking and maintenance feature the checks the laest two significant digits of the year stored in the RTC during each BIOS request INT 1A to read the date and if less than 80 i e 1980 15 the first year supported by the PC updates the century byte to 20 This feature enables operating systems and applications using BIOS date time services to reliably manipulate the year as a four digit value 2 8 Related Application Notes Description Application Notes re availble at http www digitallogic com gt support or any Application CD from DIGITAL LOGIC 14 DIGITAL LOGIC AG SM520PC Manual V1 1 2 9 SM520PC Incompatibilities to a standard PC A T only 4 DMA channels DMA 0 3 no BUS master signal only 11 IRQ lines available DIGITAL LOGIC AG SM520PC Manual V1 1 The smart480 bus the future upgrade path DIGITAL LOGIC produces different smartmodules using the smart480 bus Since each module has some unique features the integrator must use this
68. nochrom single drive SS and dual drive DD STN 4 TFT panels e Advanced Power Management features minimize power usage in Normal operation Standby Sleep modes Panel Off Power Saving Mode e VESA Standards supported e Fully Compatible with VGA e Driver Support for Windows 3 1 Windows 95 98 Windows NT3 1 NT4 0 3 10 2 VGA LCD BIOS for 69000 VGA BIOS The 65555 and 69000 VGA BIOS hereafter referred to as 69000 BIOS is an enhanced high performance BIOS that is used with the 69000 VGA Flat Panel CRT Controller to provide an integrated Flat panel VGA solution The BIOS is optimized for 69000 VGA Flat Panel CRT Controller and provides Full compatibility with the IBM VGA BIOS Support for monochrome LCD 640x480 800x600 1024x768 and 1280x1024 TFT or STN displays Optional support for other displays Supports VESA BIOS Extensions including VBE 2 0 VBE DDC 1 0 and VBE PM 1 0 Supports either VESA local bus or PCI bus Extended BIOS functions which offer easy access to 69000 control ler features and capabilities Support for simultaneous display 44K BIOS supports 8 panels 48K BIOS supports 16 panels 54 DIGITAL LOGIC AG SM520PC Manual V1 1 High Performance Integrated Memory The integrated SDRAM memory can support up to 83MHz operation thus increasing the available memory bandwidth for the graphics subsystem The result is support for additional high color high resolution graph ics modes combined with re
69. ntrol key active bit 1 1 Last code was 1 Last code was 97h Keyboard Status i 1 Keyboard error i 1 Updating LEDs i 1 Resend code received i 1 Acknowledge received i Reserved i 1 Caps lock LED state i 1 Num lock LED state i 1 Scroll lock LED state A0h Wait active flag bit 7 1 Time has elapsed bits 6 1 Reserved bit 0 1 INT 15h AH 86h occurred 52 DIGITAL LOGIC AG SM520PC Manual V1 1 3 9 1 1 Compatibility Service Table In order to ensure compatibility with industry standard memory locations for interrupt service routines and miscellaneous tabular data the BIOS maintains tables and jump vectors FF859h Entry point for INT 15h System Services 53 DIGITAL LOGIC AG SM520PC Manual V1 1 3 10 VGA LCD 3 10 1 VGA LCD Controller 69000 69000 High Performance Flat Panel CRT HiQVideo Accelerator with Integrated Memory e Highly integrated Flat Panel and CRT GUI Accelerator amp Multimedia Engine Palette DAC Clock Synthe sizer and integrated frame buffer e Integrated High performance SDRAM memory 2MB integrated memory 83 MHz SDRAM operation HiQColor Technology implemented with TMED Temporal Modulated Energy Distribution e Hardware Windows Acceleration e Integrated composite NTSC PAL Support e Hardware Multimedia Support High Performance Flat Panel Display resolution and color depth at 3 3V 36 bit direct interface to color and mo
70. o be used as a general purpose timer if the speaker function is not required Timer Assignment Timer Function 07 5 clock tick 18 2 Hz DRAM refresh request timing 15 us Speaker tone generation time base 19 DIGITAL LOGIC AG SM520PC Manual V1 1 3 3 2 Battery backed clock RTC An AT compatible date time clock is located within the chipset The device also contains a CMOS static RAM compatible with that in standard ATs System configuration data is normally stored in the clock chip s CMOS RAM in a manner consistent with the convention used in other AT compatible computers Connect an external Lithium battery of 3V to the RTC pin The battery backed clock can be set by using the DIGITAL LOGIC AG SETUP at boot time Addresses 70h Index register 71h Data transfer register RTC Address MAP 00 Real clock 10 BIOS setup Standard 40 7F Extended BIOS With an external Lithium 3V battery the board is able to work over 10 years without replacing The chip set consumes the following currents Typical battery current at 25 C lt 5 3 3 3 Watchdog The watchdog function is an implemented function of the ELAN520 and must be set triggered by the application Activate the Wachtdog in the bios setup The watchdog is hardware triggered and will be activated also in case of a hanging system The watchdog is programmable between 0 5ms and 32sec The RESWDOG CCP is a programming
71. oot Is the empty diskspace where the down exe is located larger than 64kB for safe storage Is the floppydisk not write protected Start the downloading tool with CORE BIOS FLASH520 xxxx yyy VGA BIOS FLASH520 V xxxx yyy The tool and the correspond bios are located on the product CD 30 DIGITAL LOGIC AG SM520PC Manual V1 1 3 8 Memory 3 8 1 System Memory Map The PENTIUM CPU used as central processing unit on the MICROSPACE has a memory address space which is defined by 32 address bits Therefore it can address 1 GByte of memory The memory address MAP is as follows CPU Pentium _______ 5 ____ JFunction Comments 0CC000 0CFFFFh 16 KBytes BIOS extensions selected by the hardware 0D0000 0D4000h 16 KBytes free for user 0D4000 0D8000h 16 KBytes free for user 0D8000 0DFFFFh 32 KBytes free for user 31 DIGITAL LOGIC AG SM520PC Manual V1 1 3 8 2 System I O map The following table shows the detailed listing of the I O port assignments used in the MICROSPACE board dress Status 0006h DMA channel 3 address byte 0 low then byte 1 0007h DMA channel 3 word count byte 0 low then byte 1 0008h DMA channel 0 3 status register bit 7 1 Channel 3 request bit 6 1 Channel 2 request bit 5 1 Channel 1 request bit 4 1 Channel 0 request bit 3 1 Terminal count on channel 3 bit 2 1 Terminal count on channel 2 bit 1 1 Terminal count on channel 1 bit 0 1 Terminal count on channel 0 Cont
72. ose steps 4 Restart the system and check the VGA BIOS header message The LCD name must be visible for only a short time The VGABIOS message appears as first info page on the screen 5 Stop the system connect the LCD to the system and restart again Ifon the LCD no image appears as soon as the monitor begins to show the first text stop the system immediately otherways the LCD will get damaged 7 Check the LCD connection again FOR A NEW LCD TYPE NOT AVAILABLE NOW If the LCD BIOS for your LCD is not available DIGITAL LOGIC will adapt the LCD and provide you with one working cable To initialise this we need the following points from you 1 An order to adapt the LCD for the costs ask your sales contact 2 Send the LCD panel a datasheet a connector to the LCD and the inverter for the backligth ATTENTION DIGITAL LOGIC AG is never responsible for a damaged LCD display Even when there are mistakes in the BIOS or in any documentation for the LCD 56 DIGITAL LOGIC AG SM520PC Manual V1 1 3 10 5 Memory 69000 CRT TFT Panels Hor Vert Refr DCLK jCursor FB M Video Total Resol Resol bpp Hz Mhz kByte kByte kByte Input with w o kByte Video Video oO 640 480 8 60 25775 300 42 640 480 8 72 31500 300 42 o 0 300 604 304 640 480 8 75 31500 300 42 0 0 300 604 304 640 480 8 85 36000 300
73. ot connected RES pin function depending of the CPU reserved 75 DIGITAL LOGIC AG SM520PC Connector J2 Pin 41 80 SM520PC Manual V1 1 A41 PRINTER 50 PDACKZ B41 IrDA 5o IrDA TX Fast A42 50 PREQ B42 IrDA IrDA RX Fast A43 IDE CH1 5i IRQ B43 LCD 50 LCD D33 44 IDE CH1 50 IOR B44 LCD 50 LCD 034 45 IDE CH1 50 IOW B45 LCD 50 LCD D35 A46 POWER VCC 5V 46 POWER 31 Battery 3 0V for RTC A47 PCI 3 i o AD0 B47 PCI 3 ilo AD16 A48 PCI 3 i o AD1 848 3 i o AD17 A49 PCI 3 i o AD2 B49 PCI 3 i o AD18 A50 PCI 3 i o AD3 B50 PCI 3 i o AD19 A51 PCI 3 i o AD4 B51 PCI 3 i o AD 20 IDSELO A52 PCI 3 AD5 B52 PCI 3 i o AD 21 IDSEL1 A53 PCI 3 i o AD6 B53 PCI 3 i o AD 22 IDSEL2 A54 PCI 3 i o AD7 B54 PCI 3 ilo AD 23 IDSEL3 55 PCI 3 i o AD8 B55 PCI 3 i o AD24 A56 PCI 3 i o AD9 B56 PCI 3 i o AD25 A57 PCI 3 i o AD10 B57 PCI 31 0 AD26 A58 PCI 3 AD11 B58 PCI 3 AD27 A59 PCI 3 i o AD12 B59 PCI 3i o AD28 A60 PCI 3 i o AD13 B60 PCI 3 i o AD29 A61 PCI 3 i o AD14 B61 PCI 31 0 AD30 A62 PCI 3 i o AD15 B62 PCI 3 i o AD31 A63 PCI 30 B63 PCI 31 PIRQA A64 PCI 3o C BE1 B64 PCI 3i PIRQB A65 PCI 30 C BE2 B65 PCI 3i PIRQC A66 PCI 3o C BE3 B66 PCI 3i PIRQD A67 POWER VCC 5V 67 POWER VCC 5V 68 PCI CLK1 B68 PCI 3o PCI CLK2 A69 PCI
74. parameters are modifiable Normally the parameters are set correctly by DIGITAL LOGIC AG Be very careful in modifying any parameter since the system could crash Some parameters are dependent on the CPU type The cache parameter is always available for example So if you select too few wait states the system will not start until you reset the CMOS RAM using the RAM Reset jumper but the default values are reloaded If you are not familiar with these parameters do not change anything 22 DIGITAL LOGIC AG SM520PC Manual V1 1 3 5 CMOS RAM Map Systems based on the industry standard specification include a battery backed Real Time Clock chip This clock contains at least 64 bytes of non volatile RAM The system BIOS uses this area to store information including system configuration and initialization parameters system diagnostics and the time and date This information remains intact even when the system is powered down The BIOS supports 128 bytes of CMOS RAM This information is accessible through I O ports 70h and 71h CMOS RAM can be divided into several segments Locations 00h OFh contain real time clock and status information Locations 10h 2Fh contain system configuration data Locations 30h 3Fh contain System BIOS specific configuration data as well as chipset specific in formation Locations 40h 7Fh contain chipset specific information as well as power management configuration parameters The following
75. sample of how to do implement it into the customer s application Any comments explanations are integrated inside the file See also chapter 3 12 20 DIGITAL LOGIC AG SM520PC Manual V1 1 3 4 BIOS 3 4 1 ROM BIOS An EPROM with 8 Bit wide data access normally contains the board s AT compatible ROM BIOS The BIOS takes a 29C020 EPROM or equivalent device The board s wait state control logic automatically inserts four memory wait states in all CPU accesses to this socket The ROM BIOS occupies the memory area from C0000H through FFFFFh however the board s ASIC logic reserves the entire area from C0000h through FFFFFh for onboard devices so that this area is already usable for ROM DOS and BIOS expansion mod ules Consult the appropriate address map for the MICROSPACE SM520PC ROM BIOS 3 4 1 1 Standard BIOS ROM DEVICE 29C020 PLCC32 MAP E0000 FFFFFh C0000 CBFFFh CC000 CFFFFh Core BIOS 256kB onboard soldered VGA BIOS from Chips amp Technology 32kB or 44kB reserved 3 4 2 Memory for Setup The EEPROM is used for setup and configuration data stored as an alternative to the CMOS RTC Option ally setup driver may update the CMOS if the battery is running down and the checksum error would appear and stop the system The capacity of the EEPROM is 2 kByte Organisation of the 2048Byte EEPROMs Address MAP 0010h 007Fh 0080h 00FFh 0100h 010Fh 0110h 0113h 0114h 0117h 0118h 0
76. table provides a summary of how these areas may be further divided Beginning Ending Checksum Description 23 DIGITAL LOGIC AG Time of day seconds specified in BCD Alarm seconds specified in BCD Time of Day minutes specified in BCD Alarm minutes specified in BCD rines speses Status Register A Bit7 Update in progress Bits 6 4 Time based frequency divider Bits 3 0 Rate selection bits that define the periodic in terrupt rate and output frequency 0Bh Status Register B Bit7 Run Halt 0 Run 1 Halt Bit 6 Periodic Timer 0 Disable 1 Enable Bit5 Alarm Interrupt 0 Disable 1 Enable Bit4 Update Ended Interrupt 0 Disable 1 Enable Bit3 Square Wave Interrupt 0 Disable 1 Enable Bit 2 Calendar Format BCD Binary Bit 1 Time Format 12 Hour 24 Hour Bit 0 Daylight Savings Time 0 Disable 1 Enable n Status Register C Bit 7 Bit 6 Interrupt Flag Periodic Interrupt Flag Bit 5 Alarm Interrupt Flag Bit 4 Update Interrupt Flag Bits 3 0 Reserved Status Register D Bit 7 Real Time Clock 0 Lost Power 1 Power Continued 24 SM520PC Manual V1 1 DIGITAL LOGIC AG SM520PC Manual V1 1 CMOS Map Continued CMOS Location for Bad CMOS and Checksum Flags bit 7 Flag for CMOS Lost Power 0 Power OK 1 Lost Power bit 6 Flag for CMOS checksum bad 0 Checksum is valid 1 Checksum is bad Diskette Drives bits 7 4 Diskette Drive A
77. ter 4 sec when pushing the ESC kev The tool and the sourcecode example are located on our product CD Sourcecode example of the reswdog exe include lt stdio h gt include lt conio h gt include lt dos h gt void main unsigned char kk unsigned int tt 0x10 timeout 4 Sec TIMEOUT values tt 0 invalid value tt 0x01 0 5 uSec tt 0x02 0 5 mSec tt 0x04 1 0 Sec tt 0x08 2 0 Sec tt 0x10 4 0 Sec tt 0x20 8 0 Sec tt 0x40 16 0 Sec tt 0x80 32 0 Sec pointer to address of WATCHDOG Timer Control unsigned int far unsigned int far MK_FP 0xE000 0xFCBO E000 FCBO printf Press ESC to quit n sequence enable WATCHDOG and assign the timeout tt ff 0x3333 ff OxCCCC ff OxC000 tt body user code while 1 if kbhit if getch 0x1B return return to OS In this sample JIPC will reboot after 4 Sec printf 02X r kk nothing just to do something sequence for cleaning WATCHDOG counter IIthe timing interval between such sequences must be less than watchdog timeout for this sample lt 4 Sec ff OxAAAA ff 0x5555 A 64 DIGITAL LOGIC AG SM520PC Manual V1 1 4 DESCRIPTION OF THE JUMPERS none 65 DIGITAL LOGIC AG SM520PC Manual V1 1 5 LED CRITERIONS LED Color Function Red LANACTIVE RUN OK LAN LINKLED
78. tion of customers layout CHF 300 per sheet 23 Development of circuits layout CHF 200 per hour BIOS 30 Consultation CHF 200 per hour 31 Modification Test of the BIOS sourcecode CHF 1500 per day 32 Review Inspection of customers software CHF 300 per hour 33 Development of software CHF 200 per hour Prototype 40 Consultation CHF 200 per hour 41 Test of customers system CHF 1200 per day 42 Review Inspection of customers system CHF 300 per hour 43 Development of test entvironment CHF 200 per hour All costs are payable in advance DIGITAL LOGIC AG SM520PC Manual V1 1 1 8 Limited Warranty DIGITAL LOGIC AG warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from DIGITAL LOGIC AG Switzerland This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period DIGITAL LOGIC AG will repair or replace at its discretion any defec tive product or part at no additional charge provided that the product is returned shipping prepaid to DIGITAL LOGIC AG All replaced parts and products become property of DIGITAL LOGIC AG Before returning any product for repair customers are required to contact the company This limited warranty does not extend to any product which has been damaged as a result of accident mis
79. tions as listed below e Backup of the CMOS Setup values e Storing system informations like version production date customisation of the board CPU type e Storing user application values The EEPROM will be updated automatically after exiting the BIOS setup menu The system will operate also without any CMOS battery While booting up the CMOS is automatically updated with the EEPROM values If the system hangs or a problem appears the following steps must be performed 1 Reset the CMOS Setup use the jumper to reset or disconnect the battery for at least 10 minutes 2 Press Esc until the system starts up 3 Enter the BIOS Setup a load DEFAULT values b enter the settings for the environment c exit the setup 4 Restart the system e The user may access the EEPROM through the INT15 special functions Refer to the chapter SFI func tions 3 11 1 e The system information are read only information To read use the SFI functions 29 DIGITAL LOGIC AG SM520PC Manual V1 1 3 7 Download the VGA BIOS and the CORE BIOS Before downloading a BIOS please check as follows Select the SHADOW option in the BIOS for a BIOS and VGA if this option is available Disable the EMM386 or other memory managers in the CONFIG SYS of your bootdisk Make sure that the FLASH520 EXE programm and the BIOS to download are on the same path and directory Boot the DOS without config sys amp autoexec bat gt press F5 while starting DOS b
80. ts 6 5 000 Rotate in automatic EOI mode clear 001 Nonspecific EOI 010 operation 011 Specific EOI 100 Rotate in automatic EOI mode set 101 Rotate on nonspecific command 110 Set priority command 111 Rotate on specific EOI command Reserved should be 00 Interrupt request to which the command applies PIC interrupt request and in service registers programmed by OCW3 Interrupt request register bits 7 0 0 No active request for the corresponding interrupt line 1 Active request for the corresponding interrupt line Interrupt in service register bits 7 0 0 Corresponding interrupt line not cur rently being serviced 1 Corresponding interrupt line is currently being serviced OCWS3 if bit 4 0 bit 3 1 bit 7 Reserved should 0 bits 6 5 00 No operation 01 No operation 10 Reset special mask 11 Set special mask bit 4 Reserved should be 0 bit Reserved should be 1 bit 2 0 No poll command 1 Poll command bits 1 0 00 No operation 01 Operation 10 Read interrupt request register on next read at port 0020 h 11 Read interrupt in service register on next read at port 35 DIGITAL LOGIC AG SM520PC Manual V1 1 O Ad Read Write Description dress Status 0022h Chipsset Register Address 0023h Chipsset Register Data 0040h R W Programmable Interrupt Time read write counter 0 key board controller channel O 0041h Programmer Interrupt Timer channel 1 0042h R W Programmable Interrupt Timer miscellaneous
81. use abuse such as use of incorrect input voltages wrong cabling wrong polarity improper or insufficient ventilation failure to follow the operating instructions that are provided by DIGITAL LOGIC AG or other con tingencies beyond the control of DIGITAL LOGIC AG wrong connection wrong information or as a result of service or modification by anyone other than DIGITAL LOGIC AG Neither if the user has not enough knowledge of these technologies or has not consulted the product manual or the technical support of DIGITAL LOGIC AG and therefore the product has been damaged Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranty of merchantability and fitness for a particular purpose and DIGITAL LOGIC AG ex pressly disclaims all warranties not stated herein Under no circumstances will DIGITAL LOGIC AG be liable to the purchaser or any user for any damage including any incidental or consequential damage expenses lost profits lost savings or other damages arising out of the use or inability to use the product 1 9 Sample Design Schematics DIGITAL LOGIC AG offers all schematics as a design guide only DIGITAL LOGIC AG assumes no respon sibility for final system design is also assumed that the designer has the reference manual of the ELAN520 AMD chip the programmers reference from the ELAN520 chip DIGITAL LOGIC AG assumes that the designer of a smartModule 52
82. ved l I I O addresses 03F8h 03FFh are reserved for use with serial port 1 The bit definitions for these addresses also apply to serial ports 2 3 and 4 iu bit 3 0 1 bit 2 0 1 bit 1 0 1 R bit 0 Reduce write current Head select enable Disable diskette drive reset Enable diskette drive reset Disable diskette drive initialization Enable diskette drive initialization eserved Digital input register for primary diskette drive controller bit 7 1 bit 6 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit O Diskette drive line change Write gate Head select 3 reduced write current Head select 2 Head select 1 Head select 0 Drive 1 select Drive 0 select Select register for primary diskette data transfer rate bits 7 2 Reserved bits 1 0 00 01 10 11 500 Kbs mode 300 Kbs mode 250 Kbs mode Reserved Transmitter holding register for serial port 1 Contains the character to be sent Bit 0 the least significant bit is the first bit sent bits 7 0 Data bits 0 7 when the Divisor Latch Access Bit DLAB is 0 Receive buffer register for serial port 1 Contains the character to be received Bit 0 the least significant bit is the first bit received bits 7 0 Data bits 0 7 when the Divisor Latch Access Bit DLAB is 0 Continued 44 DIGITAL LOGIC AG 1 0 Ad Read Write SM520PC Manual V1 1 dress 03F8h Status R W Baud rate divisor low byte This
83. ware requirements interconnections and details of how to pro gram the system The specifications given in this manual were correct at the time of printing advances mean that some may have changed in the meantime 1 1 How to use this manual This manual is written for the original equipment manufacturer OEM who plans to build computer systems based on the system on chip units It provides instructions for designing installing and configuring the unit and describes the system and setup requirements 1 2 Trademarks Chips amp Technologies SuperState R MICROSPACE MicroModule DIGITAL LOGIC AG DOS Vx y Windows Microsoft Inc PC AT PC XT IBM NetWare Novell Corporation Ethernet Xerox Corporation DR DOS PALMDOS Digital Research Inc Novell Inc ROM DOS Datalight Inc 1 3 Disclaimer DIGITAL LOGIC AG makes no representations or warranties with respect to the contents of this manual and specifically disclaims any implied warranty of merchantability or fitness for any particular purpose DIGITAL LOGIC AG shall under no circumstances be liable for incidental or consequential damages or related ex penses resulting from the use of this product even if it has been notified of the possibility of such damage DIGITAL LOGIC AG reserves the right to revise this publication from time to time without obligation to notify any person of such revisions 1 4 Who should use this product Electronic engineers with know how in PC technology
84. y VGA compatible BIOS end user utilities and drivers for common application programs Acceleration for All Panels and All Mode The 69000 graphics engine is designed to support high performance graphics and video acceleration for all supported display resolutions display types and color modes There is no compromise in performance op erating in 8 16 or 24 bpp color modes allowing true acceleration while displaying up to 16 7M colors 3 10 3 Display Modes Supported The 69000 supports the modes which appear in the table below Resolution Color bpp Refresh Rates Hz 640x480 8 60 75 85 640x480 16 60 75 85 640x480 24 60 75 85 800x600 8 60 75 85 800x600 16 60 75 85 800x600 24 60 75 85 1024x768 8 60 75 85 1024x768 16 60 75 85 1280x1024 8 60 55 DIGITAL LOGIC AG SM520PC Manual V1 1 3 10 4 VGA LCD BIOS Support Each LCD display needs a specific adapted VGA BIOS This product is equipped with the CRT standard VGABIOS To connect a LCD display to this product you need to perform the following 1 Check the FP_LIST PDF if the LCD BIOS is available Get the latest VGA BIOS at our webpage http www digitallogic com IF THE LCD BIOS IS AVAILABLE 2 Inthe FLATPANEL SUPPORT documentation the connection between the LCD and this product will be described 3 DOWNLOAD the corresponding LCD BIOS with the utility DOWN_000 EXE Go the the section 3 7 in this manual and follow th

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