PCI2510 User`s Manual
Contents
1. GATE OUT GEO Y 0 Ole lee eee cet M Ju funy EN 1 0 FF FE CW z 10 LSB z3 OUT D g 0 0 o a FF i ni81 l2 2 2 92 2 00 CWz10 LSB 3 LSB 2 WR CLK GATE OuT 0 0 0 FF ninini N bee Figure 6 1 Mode 0 BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 17 PCI2510 Data Acquisition V6 108 NOTE The following conventions apply to all mode timing diagrams 1 Counters are programmed for binary not BCD counting and for reading writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 HEX is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to read writer LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values MODE 1 Hardware retriggerable one shot OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results2. Hysteresis 500mV Power Interface 4 65 5 25 VDC 1A General DIO TTL compatible 4 channel digital inputs 4channel digital outputs Interrupt Source DIO 7 and Timer 2 Pattern match and Change detection DI FIFO overflow and DO FIFO underflow DI STP and DO STP Power Consumption Typical Termination resistor ON 5 V 1 07A termination resistor OFF S5V I1 1A Maximum Termination resistor ON 5V 1 32A termination resistor OFF 5V 1 36A gt Operating Temperature 0 C 50 C BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 3 VV VV WV Y Y PCI2510 Data Acquisition V6 108 gt Storage Temperature 20 C 70 C gt Relative Humidity 5 95 Transfer Characteristics gt Data Transfer Mode Bus Mastering DMA Data Transfer Bus Width 8 16 32 bits programmable gt Max Transfer Rate DI 40MB sec 32 bit 10MHz 120MB sec 32 bit 40MHz external trigger when data length is less than FIFO size DO 40MB sec 32 bit 10MHz gt Operation Mode Handshaking Handshaking Mode gt Direction I O gt Samples No Finite transfer Continuous I O gt Asynchronous 8255 Emulation gt Synchronous burst Handshaking gt Clock source for Burst Handshaking Internal 20MHz 15MHz 10MHz internal clock External CLKIN Normal Mode gt Input Data Acquisition at a predetermined rate by internal external clock gt Output output waveform at a predetermined rate by internal external clock gt C
3. Chapter 4 Connection Ways for Each Signal 4 1 High speed Digital Input Output Connection The input output signal of the PA The input output signal of the PB Digital Port 4 2 General Digital Input Connection DIO switch signal DI t ae we ap 7 switch device DGND 11 PCI2510 Data Acquisition V6 108 4 3 General Digital Output Connection switch device DOO switch signal DO 1 4 DO2 DO3 T n a oe switch device DGND Ec 4 4 Clock Input and Trigger Signal Connection jis CLKOUT pae y CLKIN DGND S 4 5 Counter Timer Signal Connection C ter Ti tput si OUT Counter Timer outpu signal la CLK External clock input signal la GAT EGate control input signal D DGND Gy 12 PCI2510 Data Acquisition V6 108 Chapter 5 Transfer Mode PCI2510 provides two types of transmit modes for sample input data from external device to the PCI2510 or output data from PCI2510 to external device B Normal Mode B Handshaking Mode 5 1 Normal Mode 5 1 1 High speed Digital Input In Normal mode of PCI2510 you can start to transmit the data from external device to the PCI2510 by start signal or stop it by stop signal You can generate start or stop signal by software command external trigger via DI STR DI STP and pattern DI When PCI2510
4. DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND N IN IN N O j jb JW je e e e le e O le IN Tw A Tn TDW JIN jo pO r2 Ju A u aAa YN lo IV CLKOUT CLKIN DO STP DO STR DI STP DI STR DO ACK DO REQ DI ACK DI REQ V6 108 PCI2510 Data Acquisition V6 108 Pin definition PAO PA7 PBO PB7 Digital inputs outputs of the PB port PCO PC7 Digital inputs outputs of the PC port PDO PD7 Digital inputs outputs of the PD port DIO D13 4 channels general digital input DO0 DO3 4 channels general digital output DI REQ Digital input channel request signal DI ACK Digital input channel response signal DI STR The trigger start signal of the digital input channels DI STP The trigger stop signal of the digital input channels DO REQ Digital output channel request signal DO ACK Digital output channel response signal DO STR The trigger start signal of the output input channels DO STP The trigger stop signal of the output input channels CLKIN External clock input CLKOUT Internal clock output DGND GND 3 2 The Definition of Counter Timer Connector P1 10 pin definition CLKO l 2 GATEO CLKI 3 4 GATEI CLK2 5 6 GATE2 OUTO 7 8 OUTI DGND 9 10 OUT2 CLKO CLK2 Clock plus input pin GATEO GATE2 Gate control input pin OUTO OUT2 Counter Timer output pin DGND Digital ground PCI2510 Data Acquisition V6 108
5. are shown as active high 2 There are two types of DO clock source listed below Internal 20MHz 15MHz 1OMHz internal clock External CLKIN 5 2 Handshaking Mode There are two different transmit modes for handshaking B Burst B 8255 Emulation 5 2 1 Burst High Speed Digital Input For the Burst High Speed Digital Input if the external device would like to transmit the data to PCI2510 it will enable the DI REQ signal to PCI2510 If PCI2510 is ready to get the data it will also enable the DI ACK signal to external device and then the data will be transmitting from external device to the PCI2510 Clock Source EXT CLKIN DI REUQ fa DI ACK E apanan SS XE NOTE 1 In this instance DI REQ and DI_ACK signal are shown as active high 14 PCI2510 Data Acquisition V6 108 2 There are two types of DI clock source listed below Internal 20MHz 15MHz 10MHz internal clock External CLKIN 5 2 2 Burst High Speed Digital Output For the Burst High Speed Digital Output if the PCI2510 would like to transmit the data to the external device it will enable the DO REQ signal to external device If the external device is ready to get the data it will also enable the DO ACK signal to PCI2510 and then the data will be transmitting from PC12510 to the external device Clock Source EXT CLKOUT DO REQ DO ACK y y Data count CIA EA 255 LEX XS AX HX v NOTE 1 In this instance DO_REQ and DO ACK si
6. gets the start signal it will start to receive data from external device at next clock Point A When PCI2510 gets the stop signal it will stop to receive the data at next clock Point B A B Clock i i SOUrCe i i i start Signal Softw mmand Trigger m sew en DESTE Pate D Data i 1 count NOTE 1 In this instance start stop signal are shown as active high 2 Note that you can t generate start and stop signal by pattern DI at the same time 3 There are two types of DI clock source listed below Internal 20MHz 15MHz 10MHz internal clock External CLKIN 5 1 2 High speed Digital Output In Normal mode of PCI2510 you can start to transmit the data from PCI2510 to the external device by start signal or stop it by stop signal You can generate start or stop signal by software command external trigger via DO_STR DO_STP When PCI2510 gets the start signal it will start to send data to external device at next clock Point A When PCI2510 gets the stop signal from external device it will stop to send the data at next clock Point B BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 13 PCI2510 Data Acquisition V6 108 A B Clock j Source Softwafe command Trigger Start Signal signal ffom DO STR f i l Software command Trigger Stop Signal signal tem DO STP Data count L de DED i i 1 In this instance start stop signal
7. in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in duration The one shout is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected unless the counter is retriggered In that case the Counter 1s loaded with the new count and the one shot pulse continues until the new count expires PCI2510 Data Acquisition V6 108 CWsil LSB i ojojojojfFF ojo ni n n n il2ltlsleelils CWz12 LSBz3 OUT CW 12 LSBz2 LSE m 4 CLK PPL LL GATE or J l njn 1n 1n ul oly folerltela ls Figure6 2 Mode 1 MODE 2 Rate Generator This Mode functions like a divide by N counter It is typically used to generate a Real Time Clock interrupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for on CLK pulse OUT then goes high again the Counter reloads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediate
8. IU bir DIRETTA JW TIT cn ed B a art pe gm il 4 f t a pa m o dha oo ed L E Mm min ia i E pE WW mmni g ELHA TITTTLETTTE 4 jiii ki F F Li F LI E amp L d PECTED pp IHE Hu Km eae Li THREE 4 L IN B IN EXE NE ME ie iierrerr amp k Sirs M 3 n L m pa LI i LI DUM R mL me ki PRPRTHP ERTL eT CXYXEXARREERA Mi he E LELE P NES a Trin h Wide T a Mm 8 Mm B SS 8 i E NNEANN HA eee ase T f Pee ier te e p E 4 SRIF PCI2510 vex APRI MI T ji ma M M BM M I M M M M o el edd e h pee Aita LEAI Xifi Diii ADRE ETIN tiai KANT f m La A BER a 3 ix I WP pl A uw X D oe LEE al E a Li oM EDHE E wm 2 3 Interface Description Please refer to the first section of the main component layout diagram to understand the general function of the following main components 2 3 1 Signal Connector CNI digital input and output connector P1 Timer input and output port 2 3 2 Physical ID of DIP Switch SWI Set physical ID number When the PC is installed more than one PCI2510 you can use the DIP switch to set a physical ID number for each board which makes it very convenient for users to distinguish and visit each board in the progress of the hardware configuration and software programming The following four place numbers are expressed by the binary system When DIP switch p
9. PCI2510 User s Manual a Beijing ART Technology Development Co Ltd PCI2510 Data Acquisition V6 108 Contents 87 2 ajetias crs sersa ssa E nneaba sh uta nosea wuss d d TA l 2 CNPT L VEIT OW 3 Chapter 2 Components Layout Diagram and a Brief Description sssssssesnnnnnznnenznnnnnzznnnnnnzzznnzzzzzzntenenznzzzzznnannzzznnnzzana 6 PAR MI Block D a a a 6 2 2 The Main Component Layout Diagram sisar nirna rE n A EE EAN E R AN EA tees PUE RES EA N AN raa 7 2 3 loer aCe DOSer pr OBL a a a IO cU cR IN LRM Ue IDE UL CiseC S Ee DoEeE 7 2 90l al DIIS 7 PAS SPAN Pi sie il ID Oi DD D RN RD 7 inni d Tu EB IT ONS a sec sais d tika 9 3 l The Demmitionor DIDO Comme tor ni B B A a 9 3 2 The Donnntomor Counter Timer Connect iii ea 10 Chapter 4 Connection Ways for Bach Stgh l sasccxssadoestavaiesgscesaiiensessdiedacsesdvaiavaisetiasaasesistedisdaanaiiuaianctisdacssadsaleseiieissxausesdeneisess 1 4 1 High speed Digital Input Output Connection ccc ccccecccsseeeseeseseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 11 4 2 General Digital Input Connection iiis oer rtr ere ter he eH ER ERES EE a A A E N PAN RENNA E Ra NENTS 11 43 General Digital Uo OM Me OU OI sissekanne T u 12 4 4 Clock Input and Trigger Signal Commection ccscsesceseeseseees
10. T is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses One CLK pulse after the count expires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts CW 16 LSA s 4 GATE o f LV Jy Vl T L j n Jaber eee Ii Jua w ISlit iSlaluielalzsls 2 CW 16 LSBa5 wH DW 16 LSB 4 ee OUT 0 o eo oj o oj oj oljo o IN nininiitlslalalslsl l3 Figure 6 4 Mode 3 Note A GATE transition should not occur one clock prior to terminal count MODE 4 Software triggered strobe OUT will be initially high When the initial count expires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 21 PCI2510 Data Acquisition V6 108 After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low unti
11. atible Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt PCI2510 Data Acquisition Board gt ART Disk a user s manual pdf b drive c catalog gt Warranty Card FEATURES Specifications Features gt High speed Channel 32 TTL compatible gt Port port PA port PB port PC port PD 8 bit port gt Input and Output Port Settings 32DI PA PD default 32DO PA PD 16DI PA PB amp 16DO PC PD 8DI PA amp 8DO PC programmable gt On board FIFO DI 16KB DO 16KB gt Terminator on board Schottky diode termination gt Messaging the message can be generated when 1 specified number of bytes has been transferred 2 when a specified input pattern is matched 3 when a measurement operation completes gt Input Level High level 22V Low level lt 0 8V gt Input Load terminator resistor is 110Q the terminator voltage is 2 9V low level 0 5V 22 4mA high level 2 7V 1mA max terminator OFF TTL compatible low level 0 5V 20mA high level 2 7V 1mA max Output Level High level P2 7V Low level lt 0 5V Driving Capacity low level 0 5V max 48mA sink high level 2 4V min 15mA Source
12. esseseeseseesersessesceececssersescesececsceserseseesecersnssersrnss 12 2 5 Counter Timer Signal Connector ia ai ia sario E ERE ERRUHE pede SPARE ERE DRE RUE RE SERRE ERR DRE I ENE A SERE DRE RUE EE SEES PERERA EPA SR ERE eo aa 12 Chaple r o Dy 13 SANOT M OE E EE E Pr E E E PP eee 13 a JA Me ls 0 B Bero 1D ERN nT ni DEE A E 13 S Metis 69 0 peepee epee nr OE 13 S EM Hands hak mo Mode a ne ne ne ne eo ee eo ee en ee ee ee ee eee 14 25 2 4 Bor iee pcd Dioral IND eee E 14 5 2 2 Burst High Speed Digital OUEID L EE 15 5 2 3 8255 Emulation High Speed Digital Input eee 15 5 2 4 8255 Emulation High Speed Digital Output enhn anas 16 Chapter o Methods of Using LIUnet COUNIOE uen aene ieni enkante o i e 16 SN Vy foiiis n 16 Chapter 7 Notes and Warranty POLICY E TENS 24 al IO O A 24 qu WV AMA eA PO y g e DUM EIN E ci US 24 Products Rapid Installation and Self check eee tete erbe toe T A ee 25 Rapid MS Pa ACM 525 3252252 52929 229 59 02 22 2 0 9 2 0 0 0 2 2 2 2 2 0 2 9 e pde ieEr ee 25 SEIT 0 25 Deleo Wrono last illa ot steer EN eins iesu cues ny eins tenu EE E a c oe a cones edd 25 PCI2510 Data Acquisition V6 108 Chapter I Overview The PCI2510 is a 32 ch Digital I O card for PCI bus Its digital I O channels are TTL comp
13. gnal are shown as active high 2 There are two types of DO clock source listed below Internal 20MHz 15MHz 1OMHz internal clock External CLKIN 5 2 3 8255 Emulation High Speed Digital Input For the 8255 Emulation High Speed Digital Input if the external device would like to transmit the data to PCI2510 it will send a DI REQ signal to PCI2510 If PCI2510 is ready to get the data it will also response a DI ACK signal to external device and then one unit of data will be transmitting from external device to the PCI2510 DI_REQ DI ACK Data count N 1 CR BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 15 PCI2510 Data Acquisition V6 108 The DI REQ and DI_ACK signal are shown as active low ONLY in handshaking mode of 8255 Emulation 5 2 4 8255 Emulation High Speed Digital Output For the 8255 Emulation Ultra Speed Digital Output the PCI2510 would like to transmit the data to the external device it will send a DO REQ signal to external device If the external device is ready to get the data it will also response a DO ACK signal to PCI2510 and then one unit of data will be transmitting from PCI2510 to the external device DO REQ DO ACK Data count NOTE The DO REQ and DO ACK signal are shown as active low ONLY in handshaking mode of 8255 Emulation Chapter 6 Methods of Using Timer Counter 6 1 The Working Mode MODE 0 Interrupt on terminal count Mode 0 1s typically used for event c
14. l N 1 CLK pulses after the initial count is written If a new count is written during counting if will be loaded on the next CLK pulse and counting will continue from the new count If a two byte count is written the following happens 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobe low N 1 CLK pulses after the new count of N is written CW 18 LSB 3 0 0 o FF FF FF a 1 0 FF FE FD CW 18 LSB 3 CW 18 LSB 3 LSB 2 GATE OUT F 1 Figure 6 5 Mode 4 MODE 5 Hardware triggered strobe OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has expired OUT will go low for one CLK pulse and then go high again BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 22 PCI2510 Data Acquisition V6 108 After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 pulse after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count i
15. lock Source for DI Internal 20MHz 15MHz 1OMHz internal clock External CLKIN gt Clock Source for DO Internal 20MHz 15MHz 10MHz internal clock External CLKIN gt Start Mode Software command Trigger signal occurred from DI STR or DO STR Pattern DI gt Stop Mode Software command Trigger signal occurred from DI STP or DO STR Pattern DI Finite transfers Change Detection gt DI Only monitor the selected input channel and capture data whenever there is a transition on one of the channels and then issue a IRQ gt Clock Source for DI Internal 20M Hz 15MHz 1OMHz internal clock External CLKIN Start Mode Software command Trigger signal occurred from DI STR Pattern DI Stop Mode Software command Trigger signal occurred from DI STP Pattern DI Finite transfers Trigger Function DI Trigger Signal DI STR DI STP DO Trigger Signal DO STR DO STP Low level 0 8 V max High level 2 0 V min Trigger Type rising or falling edge or digital pattern for DI only Pulse Width for Edge Triggers 10 ns min VV ON No ON ON V Pattern Trigger Detection Capabilities Detect pattern match on user selected data lines BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 4 PCI2510 Data Acquisition V6 108 Trigger gt Trigger Channel 3 Timer 0 to 2 Resolution 16 bit gt Trigger Time Base 10MHz gt Timer 2 interrupt source General DIO Channel NO 4 channel digital i
16. ly A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is written This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is received after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 19 PCI2510 Data Acquisition V6 108 and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode2 a COUNT of 1 I illegal CW z14 L5B 3 GATE OUT slaliislalsis wwf n ININIM M 5 ada a 2 ada CWelf LSB 3 e JLILD U U U U U U U U GATE a INN oo a Ihle m w glelelsleltlal CW 14 LSB s 4 LSB 95 l GATE Pele dm te 1 81219 1 0518 Figure 6 3 Mode 2 Note A GATE transition should not occur one clock prior to terminal count MODE 3 Square wave mode Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the initial c
17. nload an RMA application form from our company website Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installa
18. nputs 4channel digital outputs Electrical Standard TTL compatible gt DE high level 2V min low level 0 8V max gt DO high level 2 4V min low level 0 5V max Other Features gt On board Clock Oscillator SOMHz gt Board Dimension 161mm L 101mm W PCI2510 Data Acquisition V6 108 Chapter 2 Components Layout Diagram and a Brief Description 2 1 Block Diagram SCSI II 100pin Connector Active ME sia 3 REG REG K Terminator D16 D23 U 16K FIFO Pon L T s pS Active p REG REG Terminator 1 D24 D31 ME a 16K FIFO pd es Ke p D8 amp D15 Active gt REG REG K Terminator D0 D7 16K FIFO pw PCI CS PLX ji BUS PCI9054 K REG REG gt D16 D23 Active j REG REG Terminator D8 D15 16K FIFO K gia D24 D31 Address Bus Control Control Bus gt Timing Interrupt Logic Data Bus gt PCI2510 Data Acquisition V6 108 2 2 The Main Component Layout Diagram E amp zi d Tilia E ra iiiiiiiiiha pF I ads X il Lom mi i LE MM LI E adaggajau BEPENATU III ace eRe KIEN eehepanhad l i To p J TINI qis ti 5 Hi um i M MEEEEM I hhbkbbb amp as amp o ri G TLIETT L
19. oints to ON that means 1 and when it points to the other side that means 0 As they are shown in the following diagrams place ID3 is the high bit IDO is the low bit and the black part in the diagram represents the location of the switch Test software of the company often use the logic ID management BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 7 PCI2510 Data Acquisition V6 108 equipments and at this moment the physical ID DIP switch is invalid If you want to use more than one kind of the equipments in one and the same system at the same time please use the physical ID as much as possible ID3 ID2 IDI IDO ON DES l 2 3 4 The above chart shows 1111 so it means that the physical ID is 15 ID3 ID2 IDI IDO ON _ NN BID l 2 3 4 The above chart shows 0111 so it means that the physical ID is 7 ON ID3 ID2 IDI IDO ON l 2 3 4 The above chart shows 0101 so it means that the physical ID is 5 OFF 0 IM oo OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 E OFF 0 ON D ON D 9 oN A ON D ON D oN ON ON D PCI2510 Data Acquisition Chapter 3 Signal Connectors 3 1 The Definition of DI DO Connector CNI 100 pin definition DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
20. ount has expired OUT goes low for mainder of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is received after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new counter will be loaded at the end of the current half cycle BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 20 PCI2510 Data Acquisition V6 108 Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter 1s reloaded with the initial count The above process is repeated indefinitely Odd counts OU
21. ounting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 16 PCI2510 Data Acquisition V6 108 GATE I enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will continue from the new count If a two byte count is written the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the counting sequence to be synchronized by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulse later no CLK pulse is needed to load the Counter as this has already been done CW 10 LSA 4 ml
22. s written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CW 1A LSB 3 CLR GATE CWs1 LSB 3 fll CLK GATE OUT a iin minim CWa1A LSB 3 LSBz5 CLE GATE OUT ius uw u s o o o FF FF o 9 i 13 2 0 rFl rEI 5 l a Figure 6 6 Mode 5 PCI2510 Data Acquisition V6 108 Chapter 7 Notes and Warranty Policy 7 1 Notes In our products packing user can find a user manual a PCI2510 module and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using PCI2510 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of PCI2510 module 7 2 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form
23. tion When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 25
24. which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation gt gt gt Damage caused by unsuitable storage environments i e high temperatures high humidity or volatile chemicals gt Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 24 PCI2510 Data Acquisition V6 108 5 To ensure the speed and quality of product repair please dow
Download Pdf Manuals
Related Search