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Correction for Incorrect Description Notice RL78/G14 Descriptions in

1. x 100 96 Cox Rox In 1 2 Vb 1 Number of transferred bits Transfer rate This value is the theoretical value of the relative difference between the transmission and reception sides Note 7 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the TxDq by using port input mode register PIMg and port output mode register g POMg For and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 34 NC SAS 40 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 UART mode connection diagram during communication at different potential TxDq RL78 microcontroller User s device RxDq UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remark 1 Rb Q Communication line
2. reception os 9 TOOLRxD TOOLTxD mode Lg 9 TOOLO tsu tSUINIT d 1 The low level is input to the pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end tsu How long from when the TOOLO pin is placed at the low level until a pin reset ends tHD How long to keep the TOOLO pin at the low level from when the external and internal resets end excluding the processing time of the firmware to control the flash memory 24 N SAS 58
3. reception os 9 TOOLRxD TOOLTxD mode Lg 9 TOOLO tsu tSUINIT d 1 The low level is input to the pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end tsu How long from when the TOOLO pin is placed at the low level until a pin reset ends tHD How long to keep the TOOLO pin at the low level from when the external and internal resets end excluding the processing time of the firmware to control the flash memory 24 N SAS 68 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 This chapter describes the electrical specifications for the products Industrial applications TA 40 to 105 Caution 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used an
4. Mirror Data flash memory Data flash memory F1000H Reserved CORE Reserved F0800H FO7FFH Special function register 2nd SFR Special function register 2nd SFR 2 Kbyte 2 Kbytes Reserved Reserved yyyyyH XXXXXxH XXXXXH Code flash memory Code flash memory Note 00000H 00000H c 2013 Renesas Electronics Corporation All rights reserved Page 48 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E Note Code flash memory and RAM address of each product are as follows Date October 23 2013 Note Code flash memory area RAM area and the detected lowest address of each product are as follows Products Code flash memory 00000H to xxxxxH RAM zzzzzH to FFEFFH Detected lowest address for read instruction fetch execution yyyyyH R5F104xA x A to C E to G 16384 x 8 bit 00000 to O3FFFH 2560 x 8 bit FF500H to FFEFFH 10000H R5F104xC Ato C E to J L 32768 x 8 bit 00000H to 07FFFH 4096 x 8 bit FEFOOH to FFEFFH 10000H R5F104xD x 2 A to C E to G J L 49152 x 8 bit 00000H to OBFFFH 5632 x 8 bit FE900H to FFEFFH 10000H R5F104xE Ato C Eto G J L 65536 x 8 bit 00000H to OFFFFH 5632 x 8 bit FE900H to FFEFFH 10000H R5F104xF x 2 A to C E to G J L M P 98304 x 8 bit 00000H to 17
5. Vpp Note 3 Overall error Note 1 10 bit resolution 3 6 V lt VoD lt 5 5 V Target pin ANI2 to ANI14 Conversion time 2 7 V lt Voo lt 5 5 V 2 4 V lt Voo lt 5 5 V 10 bit resolution 3 6 V lt Voo lt 5 5 V Target pin Internal reference voltage and temperature sensor output voltage HS high speed main mode 2 7 V lt Voo lt 5 5 V 2 4 V lt Voo lt 5 5 V 10 bit resolution 2 4 V lt ANREFP lt 5 5 V AVREFP Vpp Note 3 Zero scale error Notes 1 2 10 bit resolution 2 4 V lt lt 5 5 V AVREFP Vpp Note 3 Full scale error Notes 1 2 10 bit resolution 2 4 V lt lt 5 5 V Vpp 3 Integral linearity error Note 1 10 bit resolution 2 4 V lt ANREFP lt 5 5 V Vpp Note 3 Differential linearity error Note 1 Analog input voltage ANI2 to ANI 14 AVREFP Internal reference voltage output Veer Note 4 2 4 V lt lt 5 5 V HS high speed main mode Temperature sensor output voltage V1MPs25 Note 4 2 4 V lt Voo lt 5 5 V HS high speed main mode Note 1 Excludes quantization error 1 2 LSB Note 2 This value is indicated as a ratio FSR to the full scale value Note 3 When AVREFP lt VDD the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVREFP VDD Zero scale error Full scale error Add 0 05
6. Note 1 Transfer rate in the SNOOZE mode is 4800 bps only However the SNOOZE mode cannot be used when FRQSELA 1 Note 2 The following conditions are required for low voltage interface when EVppo lt VDD 2 4 V lt EVppo lt 2 7 V 1 3 Mbps Note 3 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 32 MHz 2 7 V lt lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User s device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remark 1 q UART number q 0 to 3 g PIM and POM number g 0 1 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 2tENESAS 26 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 2 During communication at same potential CSI mode master mode SCKp internal clock output 40 to 105 C 2 4 V lt EVppo 1
7. EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Parameter Supply current Note 1 1002 2 HALT mode HS high speed main mode Note 7 Conditions fuoco 64 MHz 32 MHz Note 4 Voo 5 0 V Voo 3 0 V fuoco 32 MHz 32 MHz Note 4 Voo 5 0 V Voo 3 0 V fHoco 48 MHz 24 MHz Note 4 Voo 5 0 V Voo 3 0 V fHoco 24 MHz 24 MHz Note 4 Voo 5 0 V Voo 3 0 V fHoco 16 MHz 16 MHz Note 4 Voo 5 0 V Voo 3 0 V 2 2 HS high speed main mode Note 7 fmx 20 MHz Note 3 Vo 5 0 V Square wave input Resonator connection fmx 20 MHz Note 3 Voo 3 0 V Square wave input Resonator connection fmx 10 MHz Note 3 Voo 5 0 V Square wave input Resonator connection fmx 10 MHz Note 3 Voo 3 0 V Square wave input Resonator connection Subsystem clock operation 32 768 kHz Note 5 Ta 40 C Square wave input Resonator connection fsuB 32 768 kHz Note 5 25 Square wave input Resonator connection fsuB 32 768 kHz Note 5 50 Square wave input Resonator connection 32 768 kHz Note 5 70 Square wave input Resonator connection fsuB 32 768 kHz Note 5 85 Square wave input Resonator connection fsuB 32 7
8. Using the SNOOZE mode function in the software trigger mode or hardware trigger no wait mode is prohibited Using the SNOOZE mode function in the sequential conversion mode is prohibited When using the SNOOZE mode function specify a hardware trigger interval of at least shift time to SNOOZE mode Geom A D power supply stabilization wait time A D conversion time 2 fci clocks Even when using SNOOZE mode make sure to set the AWC bit to 0 in normal operation mode and change it to 1 just before transiting to STOP mode Also make sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode If the AWC bit is left set to 1 A D conversion will not start normally in spite of the subsequent SNOOZE or normal operation mode Note Refer to 23 2 3 SNOOZE mode c 2013 Renesas Electronics Corporation All rights reserved Page 22 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Explanations of SNOOZE mode related to the A D converter added page 658 Incorrect 1 If an interrupt is generated after A D conversion ends Omitted e While in the select mode After A D conversion ends and the A D conversion end interrupt request signal INTAD is generated the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal operation mode To stop the high speed on chip oscillator clock supplied while in the SNOOZE mode clear b
9. 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt EVbppo lt 4 0 V and 2 3 V Vb lt 2 7 V 1 Maximum transfer rate bps x Ro x In 1 Z0 x3 Vb 1 Transfer rate x 2 Baud rate error theoretical value x 100 96 x Ro x 1 9 Vb 1 Number of transferred bits Transfer rate This value is the theoretical value of the relative difference between the transmission and reception sides Note 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer Note 5 Use it with gt Vb ztENESAS 39 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 6 The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 1 8 V lt EVppo lt 3 3 V and 1 6 V Vb x 2 0 V Maximum transfer rate bps x Ro x In 1 x3 Vb 1 Transfer rate x 2 Baud rate error theoretical value
10. A D converter operating current lapc Notes 1 6 When conversion at maximum speed Normal mode AVrerP Voo 5 0 V Low voltage mode AVrerP Voo 3 0 V A D converter reference voltage current 1 Note 1 Temperature sensor operating current 1 Note 1 D A converter operating current IpAc Notes 1 11 13 Per D A converter channel Comparator operating current Icmp Notes 1 12 13 Voo 5 0 V Regulator output voltage 7 2 1 V Window mode Comparator high speed mode Comparator low speed mode Voo 5 0 V Regulator output voltage 1 8 V Window mode Comparator high speed mode Comparator low speed mode LVD operating current ILvp Notes 1 7 Self programming operating current IrFsp Notes 1 9 BGO operating current Isco Notes 1 8 SNOOZE operating current IsNoz Note 1 ADC operation The mode is performed Note 10 The A D conversion operations are performed Low voltage mode AVrerP Voo 3 0 V CSI UART operation DTC operation Note 1 Current flowing to VDD Note 2 When high speed on chip oscillator and high speed system clock are stopped Note 3 Current flowing only to the real time clock RTC excluding the operating current of the low speed on chip oscillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of eit
11. Operation stops D reset processing time Voltage stabilization wait time POR processing time 1 1 64 ms 3 10 ms Internal reset signal up E Le Note 4 Before the MCU starts normal operation it requires the voltage stabilization wait time POR processing time after the voltage reaches VPOR 1 51 V TYP and also requires the following LVD reset processing time after the voltage reaches the LVD detection level VLvpH LVD reset processing time 0 ms TYP to 0 0701 ms max When supply voltage falls and returns after only an internal reset occurs by the voltage detector LVD it requires the following processing time after the voltage reaches the LVD detection level VLvpH LVD reset processing time 0 0511 ms TYP to 0 0701 ms max RENESAS TECHNICAL UPDATE TN RL A004C E Date October 23 2013 38 27 3 6 Invalid memory access detection function page 1105 Incorrect Correct Figure 27 10 Invalid memory access detection function Possibility access Fetching Figure 27 10 Invalid memory access detection function instructions Write execute Accessibility Instruction fetch Write execution Special function register SFR 256 byte Special function register SFR 256 bytes General purpose register 32 byte General purpose register 32 bytes RAMNote RAMNete 2222z2H Mirror
12. lt 4 0 V 2 3 V lt Vbo x2 7 V tkcv2 2 36 24V lt lt 3 3 V 1 6 V lt Vbo lt 2 0 V 2 2 100 Slp setup time 4 0 V lt lt 5 5 V 2 7 V lt Vb lt 4 0 V 1 40 to SCKp1 Note 2 27 V lt lt 4 0 V 2 3 V lt Vb lt 2 7 V 1 40 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 20V 1 60 SIp hold time 1 62 from SCKp1 Note 3 Delay time from SCKpl 4 0 V lt EVbppo 5 5 V 2 7 V lt Vb 4 0 V 2 240 to SOp output Note 4 Cb 30 pF Rb 1 4 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V 2 428 Cb 30 pF Rb 2 7 2 4 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V 2 1146 Cb 30 pF Rv 5 5 Notes Cautions and Remarks are listed on the next page 24 N SAS 42 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 1 Transfer rate in the SNOOZE mode MAX 1 Mbps Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp outpu
13. Remark 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM number g 0 1 3 to 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 27 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 3 During communication at same potential CSI mode slave mode SCKp external clock input TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso 1 0 V 1 2 Parameter Conditions HS high speed main mode MIN MAX SCKp cycle time Note 5 tkcv2 4 0 V lt EVppo 5 5 V 20 MHz lt fuck 16 ns fuck 20 MHz 12 fuck ns 2 7 V lt 5 5 V 16 MHz lt fuck 16 fuck ns fuck 16 MHz 12 fuck ns 2 4 V lt EVpp0 lt 5 5 V 12 and 1000 ns SCKp high low level width tKH2 t amp L2 4 0 V lt lt 5 5 V tkcv2 2 14 ns 2 7 V lt EVppo lt 5 5 V tkcv2 2 16 ns 2 4 V lt EVpp0 lt 5 5 V tkcv2 2 36 ns setup time to SCKp1 Note 1 tsik2 2 7 V lt lt 5 5 V 1 40 ns 2 4 V lt EVbppo lt 5 5 V 1 60 ns Slp hold time from SCKp1 Note 2 tksi2 1 62 ns Delay time from SCKp to SOp output Note 3 tkso2 C 30
14. 1 6 V lt EVpDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter Data setup time reception tsu DAT Conditions 2 7 V EVppo 5 5 V Cb 50 pF Rb 2 7 kQ HS high speed main mode LS low speed main mode LV low voltage main mode MIN 1 85 Note 2 MAX MIN 1 145 Note 2 MAX MIN 1 145 Note 2 MAX 2 2 1 8 V EVppo lt 5 5 V Cb 100 pF Rb 3 KQ 1 145 Note 2 1 145 Note 2 1 145 Note 2 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1 230 Note 2 1 230 Note 2 1 230 Note 2 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 1 290 Note 2 1 290 Note 2 1 fuck 290 Note 2 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 1 290 Note 2 1 290 Note 2 Data hold time transmission Note 1 Note 2 Caution tHD DAT 2 7 V EVppo 5 5 V Cb 50 pF Rb 2 7 kQ 1 8 V EVppo lt 5 5 V Cb 100 pF Rb 3 KQ 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ The value must also be equal to or less than 4 Set the fuck value to keep the hold time of SCLr L and SCLr Select the no
15. 10 000 Note 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite Note 2 When using flash memory programmer and Renesas Electronics self programming library Note 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 35 9 Dedicated Flash Memory Programmer Communication UART 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVss1 0 V 24 N SAS 57 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 10 Timing for Switching Flash Memory Programming Modes 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions How long from when an external reset ends until the tsuiNir POR and LVD reset must initial communication settings are specified before the external reset ends How long from when the pin is placed at the tsu POR and LVD reset must end low level until an external reset ends before the external reset ends How long the TOOLO pin must be kept at the low POR and LVD reset must end level after an external reset ends before the external reset ends excluding the processing time of the firmware to control the flash memory V 3 RESET
16. 2 While in the software tri r mode or hardware trigger wait mode the ADCS bit can be used as a status fl for the conversion operation status However while in the hardware trigger no wait mode this bit cannot be used as a status flag 3 While in the software trigger mode or hardware trigger no wait mode the operation of the A D voltage comparator is controlled by the ADCS and ADCE bits and it takes 1 us from the start of operation for the operation to stabilize Therefore when the ADCS bit is set to 1 after 1 us or more has elapsed from the time ADCE bit is set to 1 the conversion result at that time has priority over the first conversion result Otherwise ignore data of the first conversion Correct 2 A D converter mode register ADMO Omitted Notes 1 For details of the FR2 to FRO LV1 LVO bits and A D conversion see Table 14 3 A D Conversion Time Selection Deleted 2 In software trigger mode or hardware trigger no wait mode the operation of the A D voltage comparator is controlled by bits ADCS and ADCE and it takes 1 us from the start of operation for the operation to stabilize Therefore when the ADCS bit is set to 1 after 1 us or more has elapsed from the time ADCE bit is set to 1 the conversion result at that time has priority over the first conversion result Otherwise ignore data of the first conversion Cautions 1 Change bits ADMD FR2 to FRO LV1 and LVO while conversion is stopped ADCS 0 ADCE 0
17. When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected ztENESAS 23 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 AC Timing Test Points ViH VOH ViH VOH Test points ViL VoL Lm ES ViL VoL External System Clock Timing 1 fEx 1 fExs EXCLK EXCLKS TI TO Timing TIOO to T110 to TI13 1 fro gt TOOO0 to TO10 to TO13 TRJIOO TRJOO TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 TRDIOCO TRDIOC1 TRDIODO TRDIOD1 TRGIOA TRGIOB 2tENESAS 24 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 tTJIH TRJIO tTDIH TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 TRDIOCO TRDIOC1 TRDIODO TRDIOD1 trpsiL INTPO I trciL tTGIH TRGIOA TRGIOB 2tENESAS 25 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Interrupt Request Input Timing tINTL INTPO to INTP11 Key Interrupt Input Timing to KR7 RESET Input Timing tRSL 34 NC SAS 26 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 5 Peripheral Functions Characteristics AC Timing Test Points ViH VOH ViH VOH Test points ViL VoL M x ViL VoL 34 5 1 Serial array unit 1 During communication at same potential
18. 12 fuck 8 MHz lt lt 20 MHz 10 fuck 4 MHz lt fuck lt 8 MHz 8 fuck 16 fuck fuck x 4 MHz G fuck 10 fuck 10 fuck 2 7 V EVppo lt 4 0 V 24 MHz lt fuck 20 230505270 50 MHz fuck 24 MHz 16 fuck 16 MHz lt fuck lt 20 MHz 14 fuck 8 MHz lt fuck lt 16 MHz 12 fuck 4 MHz lt fuck lt 8 MHz 8 fuck 16 fuck fuck x 4 MHz G fuck 10 fuck 10 fuck 1 8 V lt EVppo lt 3 3 V 24 MHz lt fuck 48 MCK 1 6 lt lt 2 0 2 20 MHz lt fuck lt 24 MHz 36 fi MCK 16 MHz lt fuck lt 20 MHz 32 8 MHz lt fuck lt 16 MHz 26 4 MHz lt fuck lt 8 MHz 16 f MCK 16 fuck fuck x 4 MHz 10 10 fuck 10 fuck SCKp high low level width 4 0 V lt EVpp0 lt 5 5 V 2 7 V lt Vo lt 4 0 V tkcy2 2 12 tkcy2 2 50 tkcy2 2 50 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V tkcy2 2 18 tkcy2 2 50 tkcy2 2 50 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 tkcv2 2 50 tkcy2 2 50 tkcy2 2 50 Slp setup time to SCKp1 Note 3 4 0 V lt EVpp0 lt 5 5 V 2 7 V lt Vo lt 4 0 V 1 20 1 fuck 30 1 fuck 30 2 7 V lt lt 4 0 V 2 3 V lt Vb lt 2 7 V 1 fuck 20 1 fuck 30 1 fuck 30 1 8 V lt
19. Figure 25 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 2 2 2 When LVD is in interrupt amp reset mode option byte 000C1H 010C1H LVIMDS1 LVIMDSO 1 0 Supply voltage __ Operating voltage range lower limit 1 Veonz 1 51 V TYP Veo 1 50 V TYP 1 Wait for oscillation 1 Wait for oscillation accuracy stabilization 1 accuracy stabilization 2 High speed on chip oscillator clock Starting oscillation is tarling oscillation is E f specified by software 5 High speed i specified by software system clock fux when X1 oscillation i is selected 1 s Reset i Normal operation high speed on chip oscillation CPU Operation oscillator clock 2 Ds stop stops 1 Reset processing time 5 DX Normal operation high speed on chip Note2 oscillator clock Operation stops Reset processing tim POR processing time POR processing time Internal reset signal INTLVI Not 5 Reset processing time 387 to 720 us Page 46 of 50 RENESAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 2 LVD is interrupt amp reset mode option byte 000C1H 010C1H LVIMDS1
20. 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVREFM ANI1 ADREFM 1 target ANIO ANI2 to ANI14 ANI16 to ANI20 TA 40 to 105 2 4 V lt VpD lt 5 5 V 1 6 V lt EVDD1 lt VDD Vss EVsso EVss1 0 V Reference voltage Note 3 Reference voltage AVREFM 0 V Note 4 HS high speed main mode Resolution Parameter Conditions Conversion time 8 bit resolution 24VxVppx5 5V 39 Zero scale error Notes 1 2 8 bit resolution 2 4V lt Vpp lt 5 5V 0 60 Integral linearity error Note 1 8 bit resolution 2 4 V lt Vpop lt 5 5 V 2 0 Differential linearity error Note 1 8 bit resolution 2 4 V lt VDD lt 5 5 V 1 0 Analog input voltage VBGR Note 3 Note 1 Note 2 Note 3 Note 4 Excludes quantization error 1 2 LSB This value is indicated as a ratio FSR to the full scale value Refer to 35 6 2 Temperature sensor characteristics internal reference voltage characteristic When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVREFM Integral linearity error Add x0 5 LSB to the MAX value when reference voltage AVREFM Differential linearity error Add x0 2 LSB to the MAX value when reference voltage AVREFM 34 NC SAS 52 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATION
21. 4 0 V x EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 4 0 V lt EVpp0 lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 KQ 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 C 100 pF 5 5 KQ The value must also be equal to or less than 4 Use it with gt Vb Set the fuck value to keep the hold time of SCLr L and SCLr H Select the TTL input buffer and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the N ch open drain output VoD tolerance When 30 to 52 products EVpp tolerance When 64 to 100 products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For ViH and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 24 N SAS 53 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Simplified 12 mode connection diagram during communication at different potential Vb Vb Rb Rb SDAr RL78 microcontroller User s device SCLr Simplified I2C mode serial transfer timing
22. 4 MHz fiH 4 MHz Note 3 Normal operation Voo 3 0 V Voo 2 0 V HS high speed main mode Note 5 fmx 20 MHz Note 2 Voo 5 0 V Normal operation Square wave input Resonator connection fmx 20 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection fmx 10 MHz Note 2 5 0 V Normal operation Square wave input Resonator connection fmx 10 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection LS low speed main mode Note 5 fmx 8 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection fmx 8 MHz Note 2 2 0 V Normal operation Square wave input Resonator connection Subsystem clock operation Notes and Remarks are listed on the next page fsuB 32 768 kHz Note 4 40 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 25 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 50 operation Square wave input Resonator connection 32 768 kHz Note 4 70 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 85 Normal operation Square wave input Resonator con
23. 80 pin LQFP 14 x 14 80 100 LQFP 14 x 20 100 pin products these specifications show target values which may change after device evaluation Correct 34 3 2 On chip oscillator characteristics Ta 40 to 85 C 1 6 V x EVpDpo 1 lt lt 5 5 V Vss EVsso EVss1 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency High speed on chip oscillator 20 to 85 C 1 8 V lt Voo lt 5 5 V clock frequency accuracy 2 46VzVoo 18 V 40 to 20 C 1 8 V lt Voo lt 5 5 V 1 6 V lt Voo lt 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected with bits 0 to 4 of the option byte 000 2 010 2 and bits 0 to 2 in the HOCODIV register 2 This table only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time c 2013 Renesas Electronics Corporation All rights reserved Page 4 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 2 Incorrect descriptions of connection of unused pins of P60 to P63 in Table 2 3 in the Pin functions chapter revised page 83 Incorrect Table 2 3 Connection of Unused Pins 100 pin products 2 3 Pin Name Circuit Type Recommended Connection of Unused Pins P60 SCLAO Input Ind
24. HS high speed main mode Note 5 Conditions fuoco 64 MHz 32 MHz Note 3 Basic operation Vop 5 0 V Voo 3 0 V fuoco 32 MHz 32 MHz Note 3 Basic operation Vop 5 0 V Voo 3 0 1 2 HS high speed main mode Note 5 fuoco 64 MHz 32 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 32 MHz 32 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 48 MHz 24 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 24 MHz 24 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fHoco 16 MHz 16 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V HS high speed main mode Note 5 fmx 20 MHz Note 2 Voo 5 0 V Normal operation Square wave input Resonator connection fmx 20 MHz Note 2 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz Note 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 10 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection Subsystem clock operation Notes and Remarks are listed on the next page fsuB 32 768 kHz Note 4 Ta 40 C Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 Ta 25 C
25. Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into and EVppo including the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Vpp lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz Regarding the
26. Note 9 Current flowing during self programming Note 10 For shift time to the SNOOZE mode see 23 3 3 SNOOZE mode Note 11 Current flowing only to the D A converter The supply current of the RL78 microcontrollers is the sum of or Ipp2 and IpAc when the D A converter operates in an operation mode or the HALT mode Note 12 Current flowing only to the comparator circuit The supply current of the RL78 microcontrollers is the sum of 002 or 1203 and when the comparator circuit is in operation Note 13 comparator and D A converter are provided in products with 96 KB or more code flash memory Remark 1 fiL Low speed on chip oscillator clock frequency Remark 2 fsuB Subsystem clock frequency XT1 clock oscillation frequency Remark 3 CPU peripheral hardware clock frequency Remark 4 Temperature condition of the value is TA 25 34 NC SAS 19 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 4 Characteristics TA 40 to 85 1 6 V lt EVDD0 lt VDD lt 5 5 V Vss EVsso 551 0 V 1 2 Conditions Instruction cycle Main system HS high speed main 2 7 V lt lt 5 5 V 0 03125 minimum instruction clock mode 24V lt 27 V 0 0625 execution time operation LS low speed main 1 8V lt lt 5 5 V 0 125 mode LV low voltage main 1 6 V x lt 5 5 V 0 25
27. Timer RG input high level tTGIH TRGIOA TRGIOB 2 5 fCLK width low level width tTGIL TOOO to TOO3 fro HS high speed main mode 4 0 V lt EVppo lt 5 5 V TO10 to TO13 2 7 V lt EVbbo lt 4 0 V TRJIOO TRJOO 2 4 V x lt 2 7 V TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 TRDIOCO TRDIOC1 TRDIODO TRDIOD1 TRGIOA TRGIOB output frequency PCLBUZO PCLBUZ1 output HS high speed main mode 4 0 V lt EVppo lt 5 5 V frequency 2 7 V lt EVbbo lt 4 0 V 24V EVppo lt 2 7 V Interrupt input high level INTPO 2 4 V lt lt 5 5 width low level width INTP1 to INTP11 2 4 V lt EVppo lt 5 5 V Key interrupt input low level KRO to KR7 2 4 V lt lt 5 5 V width RESET low level width 34 NC SAS 21 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Minimum Instruction Execution Time during Main System Clock Operation Tcv vs HS high speed main mode When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Cycle time Tcv us Supply voltage Vpp V 34 NC SAS 22 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 AC Timing Test Points ViH VOH ViH VOH Test points ViL VoL Lm ES Vi
28. 0 n Channel number n 0 9 PIM and POM number g 3 5 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 7 00 Remark 4 This value is valid only when CSIOO s peripheral redirect function is not used 24 N SAS 43 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 40 to 85 1 8 V lt EVpDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 1 3 Parameter Conditions HS high speed LS low speed main LV low voltage main mode mode main mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcy1 gt 4 fcLk 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo x27 V Cb 30 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note Cb 30 pF Rb 5 5 SCKp high level 4 0 V lt EVppo lt 5 5 V tkcy1 2 75 tkcv1 2 75 tkcv1 2 75 width 2 7 V lt Vb lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V tkcv4 2 170 tkcy1 2 170 tkcy1 2 170 2 3 lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V tkcy1 2 458 tkcv1 2 458 tkcv1 2 458 1 6 V lt Vb lt 2
29. 10 11 20 21 30 31 g PIM number g 0 1 3 to 5 14 h POM number h 0 1 3 to 5 7 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 24 N SAS 32 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode TA 40 to 105 2 4 V lt EVppo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 1 2 Parameter Conditions HS high speed main mode Transfer rate reception 4 0 V lt EVppo lt 5 5 V 12 Note 1 Note 1 Note 2 Note 3 Caution Remark 1 Remark 2 Remark 3 Remark 4 MIN MAX 2 7 V lt Vb lt 4 0 Theoretical value of the maximum transfer rate 2 6 fuck Note 3 V lt EVppo 4 0 V 12 Note 1 V lt VWb lt 2 7V Theoretical value of the maximum transfer rate 2 6 fuck Note 3 V lt EVppo lt 3 3 V 12 Notes 1 2 V lt Vb lt 2 0 V Theoretical value of the maximum transfer rate 2 6 Note 3 Transfer rate in the SNOOZE mode is 4800 bps only However the SNOOZE mode cannot be used when FRQSELA 1 The following conditions are required for low voltage interface when lt VDD 2 4 V l
30. 20 MHz Note 3 Voo 5 0 V Square wave input Resonator connection fmx 20 MHz Note 3 3 0 V Square wave input Resonator connection fmx 10 MHz Note 3 Voo 5 0 V Square wave input Resonator connection fmx 10 MHz Note 3 Voo 3 0 V Square wave input Resonator connection Subsystem clock operation fsuB 32 768 kHz Note 5 TA 40 Square wave input Resonator connection fsuB 32 768 kHz Note 5 25 Square wave input Resonator connection 32 768 kHz Note 5 50 Square wave input Resonator connection 32 768 kHz Note 5 70 Square wave input Resonator connection 32 768 kHz Note 5 85 Square wave input Resonator connection 32 768 kHz Note 5 105 Square wave input Resonator connection STOP mode Note 8 40 25 50 70 85 105 Notes and Remarks are listed on the next page 24 N SAS 12 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into and i
31. 47 4 0 V lt EVDDo lt 5 5 V P102 P120 P130 P140 to P145 5 7 lt EVppo 40 V When duty lt 7096 Note 3 24VxEVppo 2 7 V Total of P05 P06 P10 to P17 4 0VxEVppox5 5V P30 P31 P50 to P57 27 V EVDDo c 40 V P64 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 When duty lt 70 Note 3 Total of all pins 24VxEVppox 5 5 V When duty lt 70 Note 3 24VxEVppo 2 7 V Per pin for P20 to P27 2 4 V lt VoD lt 5 5 V P150 to P156 Total of all pins 24V lt lt 5 5 When duty x 70 Note 3 Value of current at which the device operation is guaranteed even if the current flows from the EVpp1 VoD pins to an output pin However do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to Total output current of pins IOH x 0 7 n x 0 01 Example Where n 80 and loH 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin POO P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P
32. Industrial applications TA 40 to 85 Caution 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used Caution 2 With products not provided with an EVppo EVpp1 EVsso or EVss1 pin replace EVppo and EVpp1 with VDD or replace EVsso and EVssi with Vss Caution 3 The pins mounted depend on the product Refer to 2 1 Port Functions to 2 2 1 With functions for each product 34 NC SAS 1 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 4 Absolute Maximum Ratings Absolute Maximum Ratings 1 2 Parameter Symbols Conditions Ratings Supply voltage VDD 0 5 to 6 5 EVppo EVpp1 EVpbo EVDD1 0 5 to 6 5 EVsso EVss1 EVsso EVss1 0 5 to 0 3 REGC pin input voltage ViREGC REGC 0 3 to 2 8 and 0 3 to 0 3 Note 1 Input voltage Vn to P06 P10 to P17 P30 P31 0 3 to EVppo 0 3 P40 to P47 P50 to P57 P64 to P67 and 0 3 to 0 3 Note 2 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 P60 to P63 N ch open drain 0 3 to 6 5 P20 to P
33. LVD Detection Voltage of Reset Mode and Interrupt Mode 40 to 105 VPDR lt lt 5 5 V Vss 0 V Parameter Conditions lt Detection voltage Supply voltage level Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Power supply fall time Minimum pulse width Detection delay time 34 NC SAS 55 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 2 LVD Detection Voltage of Interrupt amp Reset Mode 40 to 105 C VPDR lt lt 5 5 V Vss 0 V Parameter Interrupt and reset mode VLVDDO VPOC2 VPOC1 VPOCO 0 1 Conditions 1 falling reset voltage VLVDD1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage VLVDD2 LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage VLVDD3 LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage 35 6 7 Power s
34. Normal mode AVrerP Voo 5 0 V Low voltage mode AVrerP Voo 3 0 V A D converter reference voltage current 1 Note 1 Temperature sensor operating current 1 Note 1 D A converter operating current IpAc Notes 1 11 13 Per D A converter channel Comparator operating current Icmp Notes 1 12 13 Voo 5 0 V Regulator output voltage 7 2 1 V Window mode Comparator high speed mode Comparator low speed mode Voo 5 0 V Regulator output voltage 1 8 V Window mode Comparator high speed mode Comparator low speed mode LVD operating current ILvp Notes 1 7 Self programming operating current IrFsp Notes 1 9 BGO operating current Isco Notes 1 8 SNOOZE operating current IsNoz Note 1 ADC operation The mode is performed Note 10 The A D conversion operations are performed Low voltage mode AVrerP Voo 3 0 V CSI UART operation DTC operation Note 1 Current flowing to VDD Note 2 When high speed on chip oscillator and high speed system clock are stopped Note 3 Current flowing only to the real time clock RTC excluding the operating current of the low speed on chip oscillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either 1 1 002 and IRTC when the real time clock operates in operation mode or HALT mo
35. UART mode 40 to 85 1 6 V lt EVDDo EVDD1 lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main LS low speed main LV low voltage main Mode Mode Mode MIN MAX MIN MAX MIN MAX Transfer rate 24VxEVppox5 5V 6 Note 2 fuck 6 fuck 6 Note 1 Theoretical value of the 5 3 1 3 0 6 maximum transfer rate fuck Note 3 1 8 V lt lt 5 5 V 6 Note 2 fuck 6 fuck 6 Theoretical value of the 5 3 1 3 0 6 maximum transfer rate Note 3 1 7 V lt lt 5 5 V 6 Note 2 6 Note 2 fuck 6 Theoretical value of the 5 3 1 3 0 6 maximum transfer rate fuck fcLk Note 3 1 6 V lt EVDD0 lt 5 5 V Note 2 6 Theoretical value of the 1 3 0 6 maximum transfer rate fuck fcLk Note 3 Note 1 Transfer rate in the SNOOZE mode is 4800 bps only However the SNOOZE mode cannot be used when FRQSELA 1 Note 2 The following conditions are required for low voltage interface when EVppo lt VDD 2 4 V lt EVppo lt 2 7 V 2 6 Mbps 1 8 V x EVpDo lt 2 4 V 1 3 Mbps 1 6 V x EVpDo lt 1 8 V MAX 0 6 Mbps Note 3 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 32 MHz 2 7 V lt lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V LS low speed main mode 8 MHz 1 8 V lt
36. Vss EVsso 551 0 V 1 2 Parameter Transfer rate Note 1 Note 2 Note 3 Note 4 Caution Remark 1 Remark 2 Remark 3 Remark 4 Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX reception 4 0 V lt EVppo lt 5 5 V 6 Note 1 6 Note 1 6 1 2 7 lt lt 40 Theoretical value of the 5 3 1 3 0 6 maximum transfer rate Note 4 7 V lt EVppo lt 4 0 V 6 Note 1 6 Note 1 fuck 6 Note 1 3V lt VWb lt 2 7V Theoretical value of the 5 3 1 3 0 6 maximum transfer rate Note 4 8 V EVppo lt 3 3 V fuck 6 6 6 6 lt lt 20 Notes 1 2 3 Notes 1 2 Notes 1 2 Theoretical value of the 5 3 1 3 0 6 maximum transfer rate fuck fcLk Note 4 Transfer rate in the SNOOZE mode is 4800 bps only However the SNOOZE mode cannot be used when FRQSELA 1 Use it with 2 Vb The following conditions are required for low voltage interface when lt VDD 2 4 V lt lt 2 7 V MAX 2 6 Mbps 1 8 V x EVpDo lt 2 4 V MAX 1 3 Mbps The maximum operating frequencies of the CPU peripheral hardware clock are HS high speed main mode 32 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V LS low speed main mode 8 MHz 1 8 V lt Vo
37. document for English R01UH0186EJ0100 1 Specifications of the on chip oscillator characteristics in the Page 1179 Page 4 Electrical specifications chapter 2 Incorrect descriptions of connection of unused pins of P60 to P63 in Paae 83 Page 5 Table 2 3 in the Pin functions chapter 9 9 Explanations of the timer RG interrupt Page 5e 13 14 Cautions of the high speed on chip oscillator frequency select register HOCODIV 284 Page Page NN Pages 1048 to 1050 2 NS of reset processing time standby mode 1052 to 1055 1060 Page 18 1061 1072 1073 Cautions of A D converter mode register 0 ADMO Page 613 Page 19 Incorrect descriptions of caution on A D conversion time selection Pages 616 to 623 Page 20 42 Explanations when using SNOOZE mode in the A D converter Pages 625 626 and Pages 21 to 23 chapter 658 Explanations when using temperature sensor and internal reference 13 voltage 1 45 V of the A D test function in the Safety functions Pages 655 662 Pages 24 25 chapter Items of flash memory programming characteristics Page 1231 Page 30 3 1 3 Internal data memory space Page 105 Page 31 17 7 3 SNOOZE mode function Page 847 Pages 32 33 23 2 2 STOP mode Pages 1050 1052 Page 34 23 2 3 SNOOZE mode Page 1055 Page 34 27 3 6 Invalid memory access detection function Page 1105 Page 34 Figure 29 3 Format of Option Byte 000C2H 010C2H Page 1121 Page 35 34 4 1 Pin characteristics Page 1181
38. is 1 write 0 to bits IMFB and IFMA at the same time c 2013 Renesas Electronics Corporation All rights reserved Page 8 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 4 Explanations of the timer RD interrupt added Explanations of the timer RD interrupt added page 518 Incorrect Since the interrupt source timer RD interrupt is generated by a combination of multiple interrupt request sources for timer RD the following differences from other maskable interrupts apply Omitted e While multiple bits in the TRDIERI register are set to 1 if the first request source is met and the TRDIFi bit is set to 1 and then the next request source is met the TRDIFi bit is cleared to 0 when the interrupt is acknowledged However if the previously met request source is cleared the TRDIFi bit is set to 1 by the next generated request source Correct Since the interrupt source timer RD interrupt is generated by a combination of multiple interrupt request sources for timer RD the following differences from other maskable interrupts excluding the timer RG interrupt apply Omitted e While multiple bits in the TRDIERI register are set to 1 if the first request source is met and the TRDIFi bit is set to 1 and then the next request source is met the TRDIFi bit is cleared to 0 when the interrupt is acknowledged However if the previously met request source is cleared the TRDIFi bit is set to 1 by the ne
39. lt 5 5 V 400 Note 1 kHz 2 7 V lt Vo lt 4 0 V Cb 50 pF Rb 2 7 2 7 V lt EVppo lt 4 0 V 400 Note 1 kHz 2 3 V lt lt 2 7 V Cb 50 pF Rb 2 7 KQ 4 0 V lt EVppo lt 5 5 V 100 Note 1 kHz 2 7 V lt Vo lt 4 0 V 100 pF Rb 2 8 2 7 V lt EVppo lt 4 0 V 100 Note 1 kHz 2 3 V lt Vb x 2 7 V Cb 100 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 100 Note 1 kHz 1 6 V lt Vo lt 2 0 V Cb 100 pF Rb 5 5 Hold time when SCLr L tLow 4 0 V lt lt 5 5 V 1200 ns 2 7 V lt Vo lt 4 0 V Cb 50 pF Rb 2 7 kO 2 7 V lt EVppo lt 4 0 V 1200 ns 2 3 V lt Vo lt 2 7 V Cb 50 pF Rb 2 7 4 0 V lt lt 5 5 V 4600 ns 2 7 V lt Vb lt 4 0 V Cb 100 pF Rb 2 8 2 7 V EVppo lt 4 0 V 4600 ns 2 3 V lt Vo lt 2 7 V Cb 100 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 4650 ns 1 6 V lt Vo 2 0 V Cb 100 pF Rb 5 5 KQ Hold time when SCLr tHiGH 4 0 V lt EVppo lt 5 5 V 620 ns 2 7V lt Vo lt 4 0 V Cb 50 pF Rb 2 7 KQ 2 7 V EVppo lt 4 0 V 500 ns 2 3 V lt Vo lt 2 7 V Cb 50 pF Rb 2 7 kO 4 0 V lt EVDppo lt 5 5 V 2700 ns 2 7 V lt Vo lt 4 0 V Cb 100 pF Rb 2 8 2 7 V EVppo lt 4 0 V 2400 ns 2 3 V lt lt 2 7 V Cb 100 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1830 ns 1 6 V lt Vo lt 2 0
40. 0 7 VDD P60 to P63 0 7 EVDDO 6 0 P121 to P124 P137 EXCLK EXCLKS RESET 0 8 VDD VDD Input voltage low Caution to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Normal input buffer 0 0 2 P01 P04 P10 P14 to P17 P30 P31 P43 P44 P50 TTL input buffer 4 0 V lt EVpp0 lt 5 5 V P53 to P55 P80 P81 P142 P143 TTL input buffer 3 3 V lt lt 4 0 V 0 5 TTL input buffer 2 4 V lt lt 3 3 V 0 32 P20 to P27 P150 to P156 0 3 VDD P60 to P63 0 3 P121 to P124 P137 EXCLK EXCLKS RESET P74 P80 to P82 and P142 to P144 is even in the N ch open drain mode Remark 24 N SAS 0 2 VDD Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins The maximum value of of pins P00 P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P71 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 TA 40 to 105 2 4 V lt EVppo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 4 5 Conditions Output voltage high to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P
41. 0 V fuoco 16 MHz fiH 16 MHz Note 3 Normal operation 5 0 V Voo 3 0 V LS low speed mode Note 5 fuoco 8 MHz 8 MHz Note 3 Normal operation Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 5 fHoco 4 MHz fiH 4 MHz Note 3 Normal operation Voo 3 0 V Voo 2 0 V HS high speed main mode Note 5 fmx 20 MHz Note 2 5 0 V Normal operation Square wave input Resonator connection fmx 20 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz Note 2 Voo 5 0 V Normal operation Square wave input Resonator connection fmx 10 MHz Note 2 Voo 3 0 V operation Square wave input Resonator connection LS low speed main mode Note 5 fux 8 MHz Note 2 Voo 3 0 V Normal operation Square wave input Resonator connection fmx 8 MHz Note 2 Voo 2 0 V Normal operation Square wave input Resonator connection Subsystem clock operation Notes and Remarks are listed on the next page fsuB 32 768 kHz Note 4 40 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 25 operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 TA 50 Normal operation S
42. 0 V Note Cb 30 pF Rb 5 5 SCKp low level 4 0 V lt EVppo lt 5 5 V tkcv1 2 12 tkcy1 2 50 1 2 50 width 2 7 V Vb 4 0 V Cb 30 pF Rb 1 4 2 7 V EVppo 4 0 V tkcv1 2 18 tkcy1 2 50 1 2 50 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V tkcv4 2 50 1 2 50 Kcv1 2 50 1 6 V lt Vb lt 2 0 V Note Cb 30 pF Rb 5 5 Note Use it with EVDDo gt Vb Caution Select the TTL input buffer for the pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register PIMg and port output mode register g POMg For and see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page 24 N SAS 44 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 40 to 85 1 8 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter 81 setup time to SCKp1 Note 1 Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 30 pF Rb 1 4 HS high speed main mode LS low speed main mode LV low vol
43. 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite Note 2 When using flash memory programmer and Renesas Electronics self programming library Note 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 34 9 Dedicated Flash Memory Programmer Communication UART 40 to 85 1 8 V lt 1 lt lt 5 5 V Vss EVsso 1 0 V 24 N SAS 67 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 10 Timing for Switching Flash Memory Programming Modes 40 to 85 1 8 V lt 1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions How long from when an external reset ends until the tsuivir POR and LVD reset must initial communication settings are specified before the external reset ends How long from when the pin is placed at the tsu POR and LVD reset must end low level until an external reset ends before the external reset ends How long the TOOLO pin must be kept at the low POR and LVD reset must end level after an external reset ends before the external reset ends excluding the processing time of the firmware to control the flash memory V 3 RESET
44. 1182 Page 36 34 4 2 Supply current characteristics Pages 1186 to 1195 Page 36 34 5 AC characteristics Pages 1196 to 1197 Page 36 34 6 1 Serial array unit Pages 1198 to 1221 Page 36 34 6 2 Serial interface Page 1222 Page 36 34 7 1 A D converter characteristics Pages 1223 to 1226 Page 36 34 7 2 Temperature Sensor Internal Reference Voltage Page 1227 Page 36 Characteristics 34 7 5 POR circuit characteristics Page 1128 Page 36 Supply Voltage Rise Time None Page 37 34 9 s Memory STOP Mode Low Supply Voltage Data Retention Page 1231 Page 37 aracteristics Chapter 30 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 None Page 37 Pages 1049 1052 to 1055 1060 1061 Pages 38 to 47 1072 1073 27 3 6 Invalid memory access detection function Page 1105 Pages 48 49 Cautions of flash memory programming by self programming Page 1142 Page 50 Incorrect descriptions of reset processing time standby mode release time Incorrect Bold with underline Correct Gray hatched c 2013 Renesas Electronics Corporation All rights reserved Page 2 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Revision History RL78 G14 Incorrect description notice issued document history Document Number TN RL AO004A E TN RL A004B E TN RL A004C E Issue Date Dec 6 2012 July 4 2013 Oct c 2013 Renesas Electronics Corporation All ri
45. 2 Do not set the ADCS bit to 1 and the ADCE bit to 0 at the same time 3 Do not change bits ADCS and ADCE from 0 to 1 at the same time using an 8 bit manipulation instruction Make sure to set these bits in the order shown in 14 7 A D Converter Setup Flowchart c 2013 Renesas Electronics Corporation All rights reserved Page 19 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 11 Incorrect descriptions of caution on A D conversion time selection revised pages 616 to 623 Incorrect Table 14 3 A D Conversion Time Selection Omitted Cautions _1 When rewriting the FR2 to FRO LV1 and LVO bits to other than the same data sto D conversion once ADCS z 0 beforehand Correct Table 14 3 A D Conversion Time Selection Omitted Cautions 1 Rewrite bits FR2 to FRO LV1 and LVO to other than the same data while conversion is stopped ADCS 0 ADCE 0 2013 Renesas Electronics Corporation All rights reserved Page 20 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 12 Explanations when using SNOOZE mode in the A D converter chapter added Explanations of A D converter mode register 2 ADM2 added pages 625 626 Incorrect 4 A D converter mode register 2 ADM2 Omitted ADREFP1 ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Voo Supplied from P20 AVnerP ANIO Supplied from the internal reference volt
46. 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Absolute Maximum Ratings 2 2 Parameter Symbols Conditions Ratings Output current high Per pin to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Total of all POO to P04 P40 to P47 P102 P120 P130 pins P140 to P145 170 mA poe P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Output current low Per pin to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Total of all POO to P04 P40 to P47 P102 P120 P130 pins P140 to P145 170 pos poe P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Operating ambient In normal operation mode 40 to 105 Note temperature In flash memory programming mode Storage temperature 65 to 150 Note Total operating time in 85 to 105 C 10 000 hours Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is
47. 5 5 V 1 7 V lt lt 5 5 V 1 6 V lt EVpp0 lt 5 5 V Hold time when 2 7 V lt lt 5 5 V SCLAO L 1 8 V lt lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVpp0 lt 5 5 V Hold time when 2 7 V EVppo lt 5 5 V SCLAO H 1 8V EVppox5 5V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt EVpp0 lt 5 5 V Notes Cautions and Remarks are listed on the next page 34 NC SAS 55 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 1 12C standard mode 40 to 85 C 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX Data setup time reception tsu DAT 2 7 V lt lt 5 5 V 250 250 250 ns 1 8 V lt lt 5 5 V 250 250 250 ns 1 7 V lt EVbppo lt 5 5 V 250 250 250 ns 1 6 V lt EVbppo lt 5 5 V 250 250 ns Data hold time transmission tHo DaT 2 7 V lt lt 5 5 V 0 3 45 0 3 45 0 3 45 us note 1 8 V lt EVbppo lt 5 5 V 0 3 45 0 3 45 0 345 us 1 7 V lt EVbppo lt 5 5 V 0 3 45 0 3 45 0 3 45 us 1 6 V lt lt 5 5 V 0 3 45 0 3 45 us Setup time of stop condition tsu sro 2 7 V
48. 5 V 4600 Cb 100 pF Rb kQ Data setup time reception tsu DAT 2 7 V EVppo lt 5 5 V 1 220 Note 2 Cb 50 pF Rb 2 7 2 4V EVopo lt 5 5 V 1 580 Note 2 Cb 100 pF Rb KQ Data hold time transmission tHD DAT 2 7 V EVppo lt 5 5 V Cb 50 pF Rb 2 7 2 4 V EVppo lt 5 5 V Cb 100 pF Rb 3 KQ Note 1 The value must also be equal to or less than 4 Note 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the normal input buffer and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page 2tENESAS 31 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 C Simplified 12C mode connection diagram during communication at same potential VDD Rb SDAr SDA RL78 microcontroller User s device SCLr Simplified I2C mode serial transfer timing during communication at same potential 1 fscL tLow tHIGH SCLr SDAr tHD DAT 50 DAT Remark 1 Rb Q Communication line SDAr pull up resistance Ce F Communication line SDAr SCLr load capacitance Remark 2 r IIC number 00 01
49. ADREFPO Selection of the side reference voltage source of the A D converter Supplied from Voo Supplied from P20 AVnerP ANIO Supplied from the internal reference voltage 1 45 V ios 1 Setting prohibited When ADREFP1 or ADREFPO bit is rewritten this must be configured in accordance with the following procedures 1 Set ADCE 0 2 Change the values of ADREFP1 and ADREFPO 3 Stabilization wait time A 4 Set ADCE 1 5 Stabilization wait time B When ADREFP1 and ADREFPO are set to 1 and 0 respectively the setting is changed to A 5 us B 1 us When ADREFP1 and ADREFPO are set to 0 and 0 respectively or set to 0 and 1 respectively A needs no wait and B 1 ys After 5 stabilization time start the A D conversion When ADREFP1 and ADREFPO are set to 1 and 0 respectively A D conversion cannot be performed on the temperature sensor output and internal reference voltage output Make sure to perform A D conversion while ADISS 0 Specification of the SNOOZE mode Do not use the SNOOZE mode function Use the SNOOZE mode function When there is a hardware trigger signal in the STOP mode the STOP mode is exited and A D conversion is performed without operating the CPU the SNOOZE mode The SNOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware clock fcx If any other clock is selected specifying this mode is prohibited
50. CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 TA 40 to 85 C 1 6 V lt EVpDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 4 5 Conditions to P06 P10 to P17 P30 4 0 V x EVpDo lt 5 5 V P31 P40 to P47 P50 to P57 10 0 mA Output voltage high P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 4 0 V EVI loH1 3 0 000 lt 5 5 V mA 1 8 V lt EVI loH1 1 5 lt 5 5 V mA 1 6V lt EV DDO lt 1 8 V loH1 1 0 mA P20 to P27 P150 to P156 1 6 V lt lt 5 5 V loH2 100 uA Output voltage low to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 4 0 V EVppo lt 5 5 V loL1 20 0 mA 4 0 V EVDDO0 lt 5 5 V loL1 8 5 mA 2 7 V EVDDO lt 5 5 V loL1 3 0 mA 2 7 V EVDDO lt 5 5 V loL1 1 5 mA 1 8 V lt EVDDO0 lt 5 5 V loL1 0 6 mA 1 6 V lt EVppo lt 5 5 V loL1 0 3 mA P20 to P27 P150 to P156 1 6 V lt VDD lt 5 5 V 1012 400 P60 to P63 4 0 V EVI loL3 15 0 lt 5 5 V mA 4 0 lt EV lt 5 5 V loL3 5 0 mA 2 7 lt lt 5 5 V loL3 3 0 mA 1 8V lt EV lt 5 5 V loL3 2 0 mA 1 6V lt
51. ELECTRICAL SPECIFICATIONS TA 40 to 105 Conditions to PO6 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Vi EVpbo P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 EXCLK XT1 XT2 EXCLKS In input port or external clock input In resonator connection Input leakage current low to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Vi EVsso P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 EXCLK XT1 XT2 EXCLKS In input port or external clock input In resonator connection On chip pull up resistance Remark to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Vi EVsso 2tENESAS In input port Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 30 to 64 pin products TA 40 to 105 2 4 V lt lt VDD lt 5 5 V Vss EVsso 0 V Parameter Supply current Note 1 Operating mode
52. EVpp1 VoD pins to A current higher than the absolute maximum rating must not flow into one pin Note 4 Caution 100 mA for industrial applications R5F 104xxDxx do not output high level in N ch open drain mode Remark POO P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P71 P74 P80 to P82 and P142 to P144 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2tENESAS RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 TA 40 to 85 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 5 Output current low Note 1 Per pin for to P06 Note 1 Note 2 Note 3 Remark Conditions P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Per pin for P60 to P63 Total of POO to P04 P40 to P47 4 0 V lt EVDD0 lt 5 5 V P102 P120 P130 P140 to P145 27 lt lt 40 When duty lt 70 Note 3 1 8 V x EVpp0 lt 2 7 V 1 6 V x EVppo lt 1 8 V Total of P05 P06 P10 to P17 4 0 V lt lt 5 5 V P30 P31 P50 to P57 2 7 V lt EVppo lt 4 0 V P60 to P67 P70 to P77 1 8 V x EVpbo lt 2 7 V P80 to P87 P100 P101 P110 P111 P146 P147 1 6 V x EVDD0 lt 1 8 V When duty 70 Note 3
53. FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVREFP VDD Note 4 Refer to 35 6 2 Temperature sensor characteristics internal reference voltage characteristic 2tENESAS 49 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 2 When reference voltage AVREFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFM ANI1 ADREFM 1 target pin ANI16 to ANI20 TA 40 to 105 C 2 4 V lt EVppo EVDD1 lt VDD lt 5 5 V 2 4 V lt AVREFP lt VDD lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVREFP Reference voltage AVREFM 0 V Parameter Conditions Resolution Overall error Note 1 10 bit resolution 2 4 V lt lt 5 5 V lt Vpp Notes 3 4 Conversion time 10 bit resolution 3 6 V lt VoD lt 5 5 V Target ANI pin ANI16 to ANI20 27V lt 55 2 4 V lt Voo lt 5 5 V Zero scale error Notes 1 2 10 bit resolution 2 4 V lt lt 5 5 V EVppo x AVrerp Vpp Notes 3 4 Full scale error Notes 1 2 10 bit resolution 2 4 V lt 5 5 V lt Notes 3 4 Integral linearity error Note 1 10 bit resolution 2 4 V x lt 5 5 V EVppo x AVrerp Vpp Notes 3 4 Differential linearity error Note 1 10 bit resolution 2 4 V x AVREFP lt 5 5 V EV
54. High electric potential Comparator high speed mode window mode 0 76 reference voltage Low electric potential Comparator high speed mode window mode 0 24 reference voltage Operation stabilization wait time Internal reference voltage 2 4 V lt VoD lt 5 5 V HS high speed main mode Note Note Not usable in sub clock operation or STOP mode 35 6 5 POR circuit characteristics 40 to 105 Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Note 1 Minimum pulse width Note 2 Note 1 However when the operating voltage falls while the LVD is off enter STOP mode or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 35 4 AC Characteristics Note 2 Minimum time required for a POR reset when exceeds below VPpR This is also the minimum time required for POR reset from when Vpp exceeds below 0 7 V to when Vpp exceeds VPoR while STOP mode is entered or the system clock is stopped through setting bit O HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC TPw Supply voltage VDD VPOR 1 VPDR 0 7 V 9 24 N SAS 54 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 6 6 LVD circuit characteristics 1
55. Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 50 C Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 Ta 70 C Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 Ta 85 C Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 Ta 105 C Normal operation Square wave input Resonator connection 2tENESAS 10 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 1 Note 2 Note 3 Note 4 Note 5 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into and including the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowi
56. POR has the following functions The reset signal is released when the supply voltage Vpp exceeds 1 51 V 0 03 V However use either the voltage detection function or the external reset pin to retain the reset status until the Voo reaches the operation voltage range shown in 34 4 AC Characteristics Compares supply voltage and detection voltage Vepr 1 50 V 0 03 V generates internal reset signal when Vpp lt However when the operation voltage drops switch the MCU to STOP mode or use either the voltage detection function or the external reset to enter the reset status before the falls below the operation voltage range shown in 34 4 AC Characteristics 25 3 Operation of Power on reset Circuit The timing of generation of the internal reset signal by the power on reset circuit and voltage detector is shown below c 2013 Renesas Electronics Corporation All rights reserved Page 27 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 16 Explanations of the A D test function in the Safety functions chapter added section 27 3 8 Explanation of Figure 27 15 A D test register ADTES added page 1109 Incorrect 1 A D test register ADTES Figure 27 15 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target This i loa i ificati i ADS AVREFM 1 1 AVREFP
57. Page 32 of 50 132 NE SAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 Correct SNOOZE mode makes UART operate reception by RxDq pin input detection while the STOP mode Normally UART stops communication in the STOP mode But using the SNOOZE mode makes reception UART operate unless the CPU operation by detecting RxDq pin input Only following channels can be set to the SNOOZE mode e 30 to 64 pin products UARTO 80 to 100 pin products UARTO and UART2 When using UARTq in SNOOZE mode execute the following settings before entering STOP mede Refer to Flowcharts of SNOOZE mode operation in Figure 17 118 and Figure 17 120 In SNOOZE mode UART reception baud rate must be set differently from normal operation Refer to Table 17 3 to set registers SPSm and SDRmn 15 9 Set bits and SSECmn to enable or disable the error interrupt INTSREO when a communication error occurs Set the SWCm bit in the serial standby control register m SSCm to 1 just before entering STOP mode After initialization set the SSm1 bit to 1 in the serial channel start register m SSm When the MCU detects the RxDq pin edge input input the start bit after entering STOP mode the UART reception is started Cautions 1 The SNOOZE mode can only be specified when the high speed on chip oscillator clock is selected for Note that SNOOZE mode cannot be used when the high speed on chip oscillat
58. RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 25 Figure 29 3 Format of Option Byte 000C2H 010C2H page 1121 Old New Figure 29 3 Format of Option Byte 000C2H 010C2H Figure 29 3 Format of Option Byte 000C2H 010C2H Address 000C2H 010C2H Address 000C2H 010C2H 4 3 2 1 0 7 6 5 4 3 2 1 0 CMODE1 csMoDEO 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSELO CMODE1 C5MODEO 1 0 FRQSEL3 FROSEL2 FRQSEL1 FRQSELO Setting of flash operation mode Setting of flash operation mode CMODE1 CMODEO Operating Frequency Operating Voltage CMODE1 CMODEO Operating Frequency Operating Voltage Range Range Range Range poo foo LV low voltage main mode 1 to 4 MHz 1 6 to 5 5 V LV low voltage main mode 1 to 4 MHz 1 6 to 5 5 V 1 0o LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V o 1 LS low speed main mode 1 to 8 MHz 1 8 to 5 5 V dms 1to 16 MHz 2 4 to 5 5 V 1 to 16 MHz 2 4 to 5 5 V speed main mode i i high sp in 11032 MHz 271055V 1 1 HS high speed main mode TIS EO ME 271055V Other than above Setting prohibited Other than above Setting prohibited Frequency of the highspeed Frequency of the high speed FRQSEL4 FROSEL3 FRQSEL2 FRQSEL1 FRQSELO on chip oscillator FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSELO on chip oscillator fuoco 1 1 64 MHz 3 S esee ge L3 T833
59. Release by Reset 2 2 3 When subsystem clock is used as CPU clock Omitted Reset processing time when HALT mode or STOP mode is released Reset pro ing time 387 to 720 us When LVD is used 155 to 407 us When LVD off 2013 Renesas Electronics Corporation All rights reserved Page 38 of 50 132 NE SAS Date October 2013 Correct Figure 23 4 HALT Mode Release by Reset 1 2 Omitted 2 When high speed on chip oscillator clock is used as CPU clock Omitted Refer to Chapter 24 RESET FUNCTION for the reset processing time For details about the reset processing time for power on reset POR circuit and voltage detector LVD refer to Chapter 25 POWER ON RESET CIRCUIT Figure 23 4 HALT Mode Release by Reset 2 2 3 When subsystem clock is used as CPU clock Omitted Refer to Chapter 24 RESET FUNCTION for the reset processing time For details about the reset processing time for power on reset POR circuit and voltage detector LVD refer to Chapter 25 POWER ON RESET CIRCUIT RENESAS TECHNICAL UPDATE TN RL A004C E Incorrect descriptions of reset processing time revised pages 1052 to 1054 Incorrect 2 STOP mode release The STOP mode can be released by the following two sources a Release by unmasked interrupt request When an unmasked interrupt request is generated the STOP mode is released After the oscillation stabilization time has elapsed if interrupt acknowledgement is enabled vectore
60. TRGIF bit is set to 1 by the next generated request source When status flags of interrupt sources applicable status flags of timer are set to 0 and their interrupts are disabled in the timer RG interrupt enable register TRGIER use either one of the following methods a to c a Set OOH all interrupts disabled to the TRGIER register and write 0 to applicable status flags Go on to the next page Page 13 of 50 RENESAS c 2013 Renesas Electronics Corporation All rights reserved RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 b When there are bits set to 1 interrupt enabled in timer RG interrupt enable register TRGIER and status flags of interrupt sources related to their bits are 0 write 0 to applicable status flags Example To clear the TRGIMFB bit to O when bits TRGIMIEA and TRGOVIE are set to 1 interrupt enabled and the TRGIMIEB bit is set to O interrupt disabled Timer RG Interrupt Enable Register TRGIER Interrupt enabled TRGIER TRGOVIE fJ TRGUDIE TRGIMIEB TRGIMIEA 1 0 0 1 Interrupt disabled Timer RG Status Register TRGSR TRGDIRF TRGOVF TRGUDF f TRGIMFB f TRGIMFA 0 0 1 1 0 As status flags TRGOVF TRGIMFA corresponding to the bit which is set to 1 interrupt enabled are 0 write 0 to the TRGIMFB bit c When there are bits set to 1 interrupt enabled in the timer RG interrupt enable register TRGIER and status f
61. TxDq pull up resistance Communication line TxDq load capacitance Vb V Communication line voltage Remark 2 q UART number q 0 to 3 g PIM and POM number g 0 1 5 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 Remark 4 UART2 cannot communicate at different potential when bit 1 PIORO1 of peripheral I O redirection register 0 PIORO is 1 24 N SAS 41 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO only 40 to 85 C 2 7 V lt EVpDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V 1 2 HS high speed LS low speed main main mode mode MIN MAX MIN MAX MIN MAX Parameter Conditions LV low voltage main mode SCKp cycle time tkcy1 gt 2 fcLk 4 0 V EVppo lt 5 5 V 27V lt Vb lt 4 0 V Cb 20 pF Re 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 20 pF Rb 2 7 KQ SCKp high level width 4 0 V EVppo lt 5 5 V 27V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ tkcv1 2 50 tkcy1 2 50 tkcv1 2 50 2 7 V EVoppo lt 4 0 V 2 3 V lt Vb x27 V Co 20 pF Rb 2 7 KQ tkcy1 2 120
62. V Cb 100 pF Rb 5 5 KQ 34 NE SAS 45 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 8 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 2 Parameter Conditions HS high speed main mode MIN MAX Data setup time reception tSU DAT 4 0 V lt EVppo lt 5 5 V 1 fuck 340 Note 2 2 7 V lt Vb lt 4 0 V Cb 50 pF Rb 2 7 KQ 2 7 V lt EVppo lt 4 0 V 1 fMck 340 Note 2 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 1 fuck 760 Note 2 2 7 V lt Vo lt 4 0 V Cb 100 pF Rb 2 8 2 7 V lt EVppo lt 4 0 V 1 760 Note 2 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 570 Note 2 1 6 V lt Vb lt 2 0 V Cb 100 pF Rb 5 5 KQ Data hold time transmission tHD DAT 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 50 pF Rb 2 7 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 100 pF Rb 2 8 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 100 pF Rb 5 5 Note 1 The
63. be used Remark When using the X1 oscillator and XT1 oscillator refer to 5 4 System Clock Oscillator 34 2 2 On chip oscillator characteristics 40 to 85 1 6 V lt lt 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency Notes 1 2 High speed on chip oscillator clock frequency 20 to 85 1 8 V lt lt 5 5 1 6 V lt VDD lt 1 8 V 40 to 20 1 8 V lt Voo lt 5 5 V 1 6 V lt Voo lt 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Note 1 High speed on chip oscillator frequency is selected with bits 0 to 4 of the option byte 000C2H and bits 0 to 2 of the HOCODIV register Note 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time 24 N SAS 4 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 3 DC Characteristics 34 3 1 Pin characteristics TA 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V Output current high Note 1 Note 1 an output pin Note 2 Note 3 Conditions Per pin for to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 1 6 V x
64. bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 2 mn 00 01 02 10 12 13 34 N SAS 47 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 5 2 Serial interface TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main mode Standard mode Fast mode MAX SCLAO clock frequency Fast mode gt 3 5 MHz Standard mode gt 1 MHz Setup time of restart condition tsU STA Hold time Note 1 tHD STA Hold time when SCLAO L Hold time when SCLAO tHIGH Data setup time reception tsu DAT Data hold time transmission Note 2 HD DAT Setup time of stop condition tsu sro Bus free time tBUF Note 1 The first clock pulse is generated after this period when the start restart condition is detected Note 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIORO2 in the peripheral I O redirection register 0 PIORO is 1 At this time the pin characteristics 1 loL1 VoH1 VoL1 must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of R
65. bits set to 1 interrupt enabled in timer RG interrupt enable register TRGIER and status flags of interrupt sources related to their bits are 1 write O to these status flags and applicable status flags at the same time Example To clear the TRGIMFB bit to 0 when the TRGIMIEA bit is set to 1 interrupt enabled and the TRGIMIEB bit is set to O interrupt disabled Timer RG Interrupt Enable Register TRGIER TRGIER TRGOVIE TRGUDIE 9 TRGIMIEB TRGIMIEA 0 0 0 1 Interrupt disabled Timer RG Status Register TRGSR TRGDIRF TRGIMFB 0 1 1 As the status flag TRGIMFA corresponding to the bit which is set to 1 interrupt enabled is 1 write O to bits TRGIMFB and TRGIFMA at the same time c 2013 Renesas Electronics Corporation All rights reserved Page 12 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E 6 Explanations of the timer RG interrupt added Explanations of the timer RG interrupt added Page 562 Incorrect Not applicable new Correct 9 4 Timer RG Interrupt Timer RG generates the timer RG interrupt request from four sources Table 9 16 lists the Registers Associated with Timer RG Interrupt and Figure 9 31 shows the Timer RG Interrupt Block Diagram Table 9 16 Registers Associated with Timer RG Interrupt Date October Timer RG Status Register Timer RG Interrupt Enable Register Interrupt Request Flag Register Interr
66. during communication at different potential 1 fscL tLow tHIGH SCLr SDAr tHD DAT tSU DAT Remark 1 Rb Q Communication line SDAr SCLr pull up resistance Communication line SDAr SCLr load capacitance Vb V Communication line voltage Remark 2 number 00 01 10 11 20 30 31 g PIM POM number g 0 1 3 to 5 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 2 mn 00 01 02 10 12 13 34 N SAS 54 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 5 2 Serial interface IICA 1 12C standard mode TA 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V 1 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MAX SCLAO clock Standard mode 2 7 V lt lt 5 5 V frequency gt 1 MHz 1 8 V lt lt 5 5 V 1 7 V lt lt 5 5 V 1 6VxEVppox 5 5 V Setup time of tsu sta 2 7 V lt lt 5 5 V restart condition 1 8V EVppox5 5V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt EVpp0 lt 5 5 V Hold time Note 1 tHp sta 2 7 V lt EVopo lt 5 5 V 1 8 V lt lt
67. fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 Remark 4 UART2 cannot communicate at different potential when bit 1 PIORO1 of peripheral I O redirection register 0 PIORO is 1 24 N SAS 36 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 40 to 105 2 4 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 1 3 Parameter Conditions HS high speed main mode MIN MAX SCKp cycle time tkcy1 gt 4 fcLk 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb 4 0 V Cb 30 pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo x 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V Cb 30 pF Rb 5 5 SCKp high level width 4 0 V lt EVppo lt 5 5 V tkcy1 2 150 2 7 V lt Vb lt 4 0 V Cb 30 pF Rb 1 4 2 7 V EVppo lt 4 0 V tkcy1 2 340 2 3 V lt Vo lt 2 7 V Cb 30 pF Rb 2 7 2 4 V EVppo lt 3 3 V tkcv1 2 916 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 SCKp low level width 4 0 V lt lt 5 5 V tkcv1 2 24 2 7 V Vb lt 4 0 V Cb 30 pF Rb 1 4 2 7 V EVppo 4
68. lt lt 5 5 V Vss EVsso EVss1 0 V Parameter SCKp cycle time Conditions tkcy1 gt 4 fcLK 2 7 V Evopo 5 5 V HS high speed main mode MIN MAX 250 2 4 V lt lt 5 5 V 500 SCKp high low level width tKL1 4 0 V EVppo lt 5 5 V tkcv1 2 24 2 7 V EVppo lt 5 5 V tkcv1 2 36 2 4 V lt EVpp0 lt 5 5 V tkcy1 2 76 setup time to SCKp1 Note 1 4 0 V EVppo lt 5 5 V 66 2 7 V EVppo lt 5 5 V 66 2 4 V lt lt 5 5 V 51 hold time from SCKp1 Note 2 Delay time from SCKp to SOp output Note 3 C 30 pF Note 4 Note 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg
69. lt lt 5 5 V 2 0 85 to 105 1 0 20 to 85 1 5 40 to 20 Serial array unit UART CSI fcLk 2 16 Mbps supported fcLk 4 Simplified 12 communication UART CSI fcLk 4 Simplified 12C communication IICA Standard mode Fast mode Fast mode plus Standard mode Fast mode Voltage detector Remark Rising 1 67 V to 4 06 V 14 stages Falling 1 63 V to 3 98 V 14 stages Rising 2 61 V to 4 06 V 8 stages Falling 2 55 V to 3 98 V 8 stages The electrical characteristics of the products Industrial applications TA 40 to 105 are different from those of the products A Consumer applications and D Industrial applications For details refer to 35 1 to 35 10 24 N SAS RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 1 Absolute Maximum Ratings Absolute Maximum Ratings 1 2 Parameter Symbols Conditions Ratings Supply voltage VDD 0 5 to 6 5 EVppo EVpp1 EVpbo EVDD1 0 5 to 6 5 EVsso EVss1 EVsso EVss1 0 5 to 0 3 REGC pin input voltage ViREGC REGC 0 3 to 2 8 and 0 3 to 0 3 Note 1 Input voltage Vn to P06 P10 to P17 P30 P31 0 3 to EVppo 0 3 P40 to P47 P50 to P57 P64 to P67 and 0 3 to 0 3 Note 2 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 P60 to P63 N ch open drain 0 3 to 6 5 P20 to P27 P1
70. lt 5 5 V 1 0 frequency 24V lt VDD lt 2 7 V 1 0 fEXS 32 0 0625 External system clock tEXH 2 7 V lt VDD lt 5 5 V 24 high level width tEXL 24 lt 0 lt 2 7 30 low level width tEXHS tEXLS TIOO to TIO3 10 tTIH triL 1 fuck 10 TI13 input high level Note width low level width Timer RJ input cycle 2 7 V lt EVppo lt 5 5 V 100 2 4 V lt lt 2 7 V 300 Timer RJ input high tTJIH 2 7 V lt lt 5 5 V 40 13 7 level width low level trJiL 24V lt EVppo lt 2 7 V width Note The following conditions are required for low voltage interface when lt VDD 2 4 V lt EVppo lt 2 7 V MIN 125 ns Remark Timer array unit operation clock frequency Operation clock to be set by the CKSmn bit of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 3 24 N SAS 20 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V 2 2 Conditions Timer RD input high level tTDIH TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 width low level width tTDIL TRDIOCO TRDIOC1 TRDIODO TRDIOD1 Timer RD forced cutoff signal trbsiL P130 INTPO 2MHz lt lt 32 MHz 1 input low level width lt 2 MHz 1 fcLK 1
71. lt 5 5 V 44 110 110 2 4 V lt EVppo 5 5 V 75 110 110 1 8 V EVppo 5 5 V 110 110 110 1 7 V lt EVpp0 5 5 V 220 1 6 V EVppo 5 5 V 220 Slp hold time 1 7 V lt EVppo lt 5 5 V 19 from SCKp1 Note 2 1 6 V EVppo lt 5 5 V 19 Delay time from 1 7 V lt EVbpo lt 5 5 V SCKp to SOp output 30 pF Note 4 Note 3 1 6 V lt EVppo lt 5 5 V C 30 pF Note 4 Note 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remark 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM number g 0 1 3 to 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be
72. lt EVppo lt 5 5 V 4 0 4 0 4 0 us 1 8 V lt lt 5 5 V 4 0 4 0 4 0 us 1 7 V lt EVppo lt 5 5 V 4 0 4 0 4 0 us 1 6 V lt lt 5 5 V 4 0 4 0 us Bus free time tBUF 2 7 V EVppo lt 5 5 V 4 7 4 7 4 7 us 1 8 V lt EVpp0 lt 5 5 V 4 7 4 7 4 7 us 1 7 V lt lt 5 5 V 4 7 4 7 4 7 us 1 6 V lt lt 5 5 V 4 7 4 7 us Note 1 The first clock pulse is generated after this period when the start restart condition is detected Note 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIORO2 in the peripheral I O redirection register 0 PIORO is 1 At this time the pin characteristics loL1 VoL1 must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 24 N SAS 56 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 12C fast mode TA 40 to 85 1 6 V lt EVppo EVDD1 lt lt 5 5 V Vss EVsso 551 0 V Parameter Conditions HS high speed LS low speed LV low voltage main mode main mode main mode MAX MAX i MAX SCLAO clock frequency Fast mode 2 7 V lt
73. ms max When LVD is off The second and subsequent reset processing time after POR is released 0 531 ms TYP 0 675 ms max When LVD is used 0 259 ms TYP 0 362 ms max When LVD is off After power is supplied a voltage stabilization wait time of about 0 99 ms TYP and up to 2 30 ms MAX is required before reset processing starts after the external reset is released 3 The state of P40 is as follows High impedance during the external reset period or reset period by the POR High level during other types of reset or after receiving a reset signal connected to the on chip pull up resistor Reset by POR and LVD circuit supply voltage detection is automatically released when Voo 2 2 Vivo after the reset After reset processing execution of the program with the high speed on chip oscillator clock as the operating clock starts For details see Chapter 25 POWER ON RESET CIRCUIT or Chapter 26 VOLTALGE DETECTOR RENESAS TECHNICAL UPDATE TN RL A004C E Incorrect descriptions of reset processing time revised pages 1072 1073 Incorrect Supply voltage Operating voltage range lower limit 1 51 VPDR 1 50 V TYP ov RESET pin High speed on chip oscillator clock Figure 25 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 2 1H VP 10 us or more Wait for osci
74. on chip oscillator clock g Starting X1 oscillation is specified by software High speed system clock when X1 oscillation is selected Reset processing Normal operation high speed on chip oscillator clock M Watchdog timer overfiow 10 0511 ms Execution of illegal instruction 10 0701 ms MAX Detection of RAM parity error Detection of illegal memory access Internal reset signal Reset penod oscillation stop CPU status Normal operation Port pin except P130 Port pin P130 RENESAS TECHNICAL UPDATE TN RL A004C E Figure 24 4 Timing of Reset in STOP mode by RESET Input Wait for oscillation STOP instruction execution accuracy stabilization a High speed on chip oscillator clock Starting X1 oscillation is specified by software High speed system clock when X1 oscillation is selected Reset Stop status ra Normal operation Normal ration T CPU status Toscillation stop Dp high speed on chip oscillator clock RESET Reset processing 387 to 674 yis When LVD is used 155 to 360 ps When LVD off nternal reset signa except P130 Port pin P130 Nef Note When P130 is set to high level output before reset is effected the output signal of P130 can be dummy output as a reset signal to an external device because P130 outputs a low level when reset is effected To release a reset signal t
75. on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2tENESAS 3 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 2 Oscillator Characteristics 35 2 4 X1 XT1 characteristics 40 to 105 2 4 V lt Voo lt 5 5 V Vss 0 V X1 clock oscillation frequency fx Note Ceramic resonator 2 7 V lt lt 5 5 crystal resonator 2 4 V lt VDD lt 2 7 V XT1 clock oscillation frequency fxr Note Crystal resonator Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 osc
76. pF Note 4 2 7 V lt EVppo lt 5 5 V 2 fuck 66 ns 2 4 V lt EVpp0 lt 5 5 V 2 fuck 113 ns Note 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and 1 The Slp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 C is the load capacitance of the SOp output lines Note 5 The maximum transfer rate when using the SNOOZE mode is 1 Mbps Caution Select the normal input buffer for the pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg Remark 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM number g 0 1 3 to 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 28 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 3 During communication at same potential CSI mode slave
77. set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 30 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 4 During communication at same potential CSI mode slave mode SCKp external clock input 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 1 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX SCKp cycle 2 4 0 V lt EVppo lt 5 5 V 20 MHz lt fuck 8 fuck ns ime N time Nes fuck lt 20 MHz G fuck G fuck 6 fmcK ns 2 7 V lt EVppo lt 5 5 V 16 MHz lt fuck 8 fuck ns fuck lt 16 MHz G fuck G fuck 6 fuck ns 2 4 V lt lt 5 5 V G fuck G fuck 6 fuck ns and 500 and 500 and 500 1 8V lt EVpp0 lt 5 5 V G fuck G fuck G fuck ns and 750 and 750 and 750 1 7 V lt EVpp0 lt 5 5 V G fuck G fuck 6 fuck ns and 1500 and 1500 and 1500 1 6 V EVppo 5 5 V 6 fuck 6 ns and 1500 and 1500 SCKp high tkH2 4 0 V lt EVbbo lt 5 5 V tkcy2 2 7 tkcy2 2 7 tkcv2 2 7 ns 2 7 V lt lt 5 5 V 2 2 8 tkcy2 2 8 tkcv2 2 8 ns 1 8 V lt lt 5 5 V tkcv2 2 18 tkcv2 2 18 tkcv2 2 18 ns 1 7 V lt lt 5 5 V tkcy2 2
78. these status flags and applicable status flags at the same time Example To clear the IMFB bit to 0 when the IMIEA is set to 1 interrupt enabled and the IMIEB is set to 0 Timer RD Interrupt Enable Register i TRDIERI Interrupt disabled Timer RD Status Register i TRDSRi TRDSRi we As the status flag IMFA corresponding to the bit which is set to 1 interrupt disabled interrupt enabled is 1 write O to bits IMFB and IMFA at the same time c 2013 Renesas Electronics Corporation All rights reserved Page 10 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 5 Explanations of the timer RG status register added Explanations of the timer RG status register added page 534 Incorrect Note 1 Correct Note 1 When the counter value of timer RG changes from FFFFH to 0000H the TRGOVF bit is set to 1 Omitted The writing results are as follows If the read value is 1 writing 0 to the bit sets it to 0 e f the read value is 0 the bit remains unchanged even if 0 is written to it Even if the bit is changed from 0 to 1 After reading and then 0 is written to it it remains 1 e Writing 1 has no effect When the counter value of timer RG changes from FFFFH to 0000H the TRGOVF bit is set to 1 Omitted The writing results are as follows e Writing 1 has no effect e f the read value is 0 the bit remains unchange
79. timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 34 NC SAS 17 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 3 Peripheral Functions Common to all products TA 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Low speed on chip oscillator operating current Iri Note 1 Conditions RTC operating current Notes 1 2 3 12 bit interval timer operating current Notes 1 2 4 Watchdog timer operating current Iwpr Notes 1 2 5 fil 15 kHz A D converter operating current lapc Notes 1 6 When conversion at maximum speed
80. to FFEDFH R5F104xE x A to C E to G J L FE900H to FEDO9H R5F104xJ x F J L M P F9FOOH to FA309H 3 The RAM area in the products listed below cannot be used when using the self programming function or rewriting the data flash because they are used by libraries R5F104xD x Ato C E to G J L FE900H to FEDO9H R5F104xE x A to C E to G J L FE900H to FEDO9H R5F104xJ x A to C E to J L FA300H to R5F104xJ x F J L M P F9F00H to FA309H 3 The internal RAM area in the following products cannot be used as stack memory when using the on chip debugging trace function 4 The internal RAM area in the following products cannot be used as stack memory when using the on chip debugging trace function R5F104xJ x A to C E to G J L FA300H to FA6FFH c 2013 Renesas Electronics Corporation All rights reserved Page 31 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E 21 17 7 3 SNOOZE mode function page 847 Incorrect e 30to 64 pin products UARTO only e 80 to 100 pin products UARTO and UART2 When using the SNOOZE mode function set the SWCm bit of serial standby control register m SSCm to 1 just before switching to the STOP mode Cautions 1 The SNOOZE mode can only be specified when the high speed on chip oscillator clock is selected for 2 The maximum transfer rate when using UARTq in the SN 9600 bps target ZE mode is
81. transfer rate Expression for calculating the transfer rate when 2 7 V lt lt 4 0 V and 2 3 V lt Vb lt 2 7 V 1 Maximum transfer rate bps Cb x Rb x In 1 20 Vb 1 Transfer rate x 2 Baud rate error theoretical value x 100 96 1 Transfer rate x Ro x In 1 22 Vb x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides Note 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 34 N SAS 34 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 5 The smaller maximum transfer rate derived by using 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 4 V lt EVppo lt 3 3 V and 1 6 V Vb x 2 0 V Maximum transfer rate bpp x Ro x In 1 x3 Vb 1 Transfer rate x 2 Baud rate error theoretical value x 100 96 Vb 1 x Number of transferred bits Transfer rate Thi
82. used as CPU clock Omitted Omitted 2 When high speed on chip oscillator clock is used as CPU clock 2 When high speed on chip oscillator clock is used as CPU clock Omitted Omitted mE Note Refer to Chapter 24 RESET FUNCTION for the reset processing time For details Reset processing time when HALT mode or STOP mode is released about the reset processing time for power on reset POR circuit and voltage detector 155 to 407 us When LVD off LVD refer to Chapter 25 POWER ON RESET CIRCUIT c 2013 Renesas Electronics Corporation All rights reserved Page 41 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E Explanations of SNOOZE mode shift time added page 1055 Incorrect 23 2 3 SNOOZE mode 1 SNOOZE mode setting and operating statuses Omitted The operating statuses in the SNOOZE mode are shown below c 2013 Renesas Electronics Corporation All rights reserved Page 42 of 50 Date October 2013 Correct 23 2 3 SNOOZE mode 1 SNOOZE mode setting and operating statuses Omitted In SNOOZE mode transition wait status to be only following time When FRQSEL4 0 18 us to 65 us When FRQSEL4 1 18 us to 135 us Remark Transition time from STOP mode to SNOOZE mode varies depending on the temperature conditions and the STOP mode period Transition time from SNOOZE mode to normal operation When vectored interrupt servicing is carried out HS High speed
83. value must also be equal to or less than 4 Note 2 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 30 52 products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the N ch open drain output Von tolerance When 30 to 52 products EVpp tolerance When 64 to 100 products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For ViH and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 24 N SAS 46 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Simplified I2C mode connection diagram during communication at different potential Vb Vb Rb Rb SDAr RL78 microcontroller User s device SCLr Simplified I2C mode serial transfer timing during communication at different potential 1 fscL tLow tHIGH SCLr SDAr tHD DAT tSU DAT Remark 1 Rb Q Communication line SDAr SCLr pull up resistance Communication line SDAr SCLr load capacitance Vb V Communication line voltage Remark 2 number 00 01 10 11 20 30 31 g PIM POM number g 0 1 3 to 5 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn
84. vol tage main mode MIN MAX 1000 Note 1 MIN MAX 400 Note 1 MIN MAX 400 Note 1 1 8 V lt 5 5 V Cb 100 pF Rb 3 KQ 400 Note 1 400 Note 1 400 Note 1 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 300 Note 1 300 Note 1 300 Note 1 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 250 Note 1 250 Note 1 250 Note 1 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 250 Note 1 250 Note 1 Hold time when SCLr L 2 7 V EVppo lt 5 5 V Cb 50 pF Rb 2 7 kO 1 8 V lt 5 5 V Cb 100 pF Rb 3 KQ 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ Hold time when SCLr H 2 7 V EVppo lt 5 5 V Cb 50 pF Rb 2 7 kO 1 8 V EVppo lt 5 5 V Cb 100 pF Rb 3 KQ 1 8 V lt EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ 1 6 V EVppo lt 1 8 V Cb 100 pF Rb 5 KQ Notes and Caution are listed on the next page and Remarks are listed on the page after the next page 24 N SAS 35 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 5 During communication at same potential simplified 12C mode 40 to 85
85. 0 V tkcv1 2 36 2 3 V lt Vo lt 2 7 V Cb 30 pF Rb 2 7 2 4 V EVppo lt 3 3 V tkcy1 2 100 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register PIMg and port output mode register POMg For and see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page 24 N SAS 37 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output TA 40 to 105 2 4 V lt EVDDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 3 Parameter Conditions HS high speed main mode MIN MAX Slp setup time to SCKp1 Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVDpo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 Slp hold time from SCKp1 Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVDpo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 p
86. 0 bit resolution 3 6 V lt Voo lt 5 5 V Target pin internal reference voltage and temperature sensor output voltage HS high speed main mode 2 4 lt 00 lt 5 5V 2 7 V lt Voo lt 5 5 V Zero scale error Notes 1 2 10 bit resolution 1 8 V lt Voo lt 5 5V 1 6 V lt lt 5 5 V Note 3 Full scale error Notes 1 2 10 bit resolution 1 8 V lt Voo lt 5 5V 1 6 V lt lt 5 5 V Note 3 Integral linearity error Note 1 10 bit resolution 1 8 V lt lt 5 5 V 1 6 V lt lt 5 5 V Note 3 Differential linearity error 10 bit resolution 1 8 V lt lt 5 5 V Note 1 1 6 V lt lt 5 5 V Note 3 Analog input voltage ANIO to ANI14 ANI16 to ANI20 Internal reference voltage Note 4 2 4 V lt Voo lt 5 5 V HS high speed main mode Temperature sensor output voltage V1MPs25 Note 4 2 4 V lt Voo lt 5 5 V HS high speed main mode Note 1 Excludes quantization error 1 2 LSB Note 2 This value is indicated as a ratio 96 FSR to the full scale value Note 3 When the conversion time is set to 57 us min and 95 us max Note 4 Refer to 34 6 2 Temperature sensor characteristics internal reference voltage characteristic 24 N SAS 61 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 4 When reference voltage Internal reference voltage
87. 0 to P102 P110 P111 P120 P140 to P147 Vi EVsso 2tENESAS In input port Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 30 to 64 pin products TA 40 to 85 1 6 V lt EVDDO lt VDD lt 5 5 V Vss EVsso 0 V Parameter Supply current Note 1 Operating mode HS high speed main mode Note 5 Conditions fuoco 64 MHz 32 MHz Note 3 Basic operation Vop 5 0 V Voo 3 0 V fuoco 32 MHz 32 MHz Note 3 Basic operation Vop 5 0 V Voo 3 0 HS high speed main mode Note 5 fuoco 64 MHz 32 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 32 MHz 32 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 48 MHz 24 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 24 MHz 24 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V fuoco 16 MHz 16 MHz Note 3 Normal operation Vop 5 0 V Voo 3 0 V LS low speed main mode Note 5 fuoco 8 MHz 8 MHz Note 3 Normal operation Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 5 fHoco
88. 09 85 Resonator connection 1 74 8 28 Ipp3 STOP mode Ta 40 0 19 0 57 oto Ta 25 0 25 0 57 50 0 33 2 26 70 0 52 3 99 85 1 46 8 00 Notes and Remarks are listed on the next page 24 N SAS 16 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to VDD EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter D A converter comparator LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing int
89. 1 2 120 tkcy1 2 120 SCKp low level width 4 0 V EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ tkcy1 2 7 tkcy1 2 50 1 2 50 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 27 V Co 20 pF Rb 2 7 KQ tkcv1 2 10 tkcy1 2 50 tkcv1 2 50 81 setup time to SCKpt Note 1 4 0 V EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 2 7 V lt lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 20 pF Rb 2 7 KQ 51 hold time from SCKp1 Note 1 4 0 V EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V lt lt 4 0 V 2 3 V lt Vb lt 2 7 V Co 20 pF Rb 2 7 KQ Delay time from SCKp to SOp output Note 1 Notes Caution and Remarks are listed on the next page 4 0 V EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Co 20 pF Rb 2 7 KQ 24 N SAS 42 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO only TA 40 to 85 2 7 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter 81 setup time to SCKp4 Note 2 Conditions 4 0 V EVpp
90. 1 45 V gt 1 control IVREFO IVCMPO gt other than CoEPOL 1 Digital filter 00B Q match ELC event COWDE 3 times 0 Both edge fork 32 2118 detection fcLk 8 10B O 018 Sampling clock C1FCK1 2013 Renesas Electronics Corporation All rights reserved Page 15 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Correct Figure 16 1 Comparator Block Diagram COFCK1 COFCKO Comparator 0 Sampling clock CLK 32 Doe COFCK1 COFCKO 3 times other than 00B Both edge detection ET COMPO One edge ELC event IVCMPO Q9 detection d COVRF 0 COWDE Q IVREFO INTCMPO 9 4 comparator detection 0 interrupt 1 control Lp Oveouro COMP1 IVCMP1 o Comparator 1 ELC event IVREF1 OQ INTCMP1 comparator detection 1 interrupt Internal reference voltage 1 45 V SPDMD Note When setting either the COWDE bit or C1WDE bit or both bits to 1 this switch is turned ON and the division resistor to generate the comparison voltage becomes enabled Remarks 0 1 CnMON CnVRF CnWDE CnENB Bits in the COMPMDR register CnFCK1 CnFCKO CnEDG CnEPO Bits in the COMPFIR register SPDMD CnOE CnlE Bits in the COMPOCR regist
91. 140 to P147 4 0 V lt EVppo lt 5 5 V loH1 3 0 mA 0 0 7 2 7 V lt EVppo lt 5 5 V loH1 2 0 mA 0 0 6 2 4 V lt EVDDO lt 5 5 V loH1 1 5 mA 0 0 5 P20 to P27 P150 to P156 2 4 V lt VoD lt 5 5 V loH2 100 uA 0 5 Output voltage low Caution to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 4 0 V lt EVppo lt 5 5 V loL1 8 5 mA 2 7 V EVppo lt 5 5 V loL1 3 0 mA 2 7 V EVDDO lt 5 5 V loL1 1 5 mA 2 4 V EVDDO lt 5 5 V loL1 0 6 mA P20 to P27 P150 to P156 2 4 V lt VoD lt 5 5 V 1012 400 P60 to P63 output high level in N ch open drain mode Remark 4 0 V lt EVppo lt 5 5 V loL3 15 0 mA 4 0 V lt EVppo lt 5 5 V loL3 5 0 mA 2 7 V EVDDO lt 5 5 V loL3 3 0 mA 2 4 V lt 5 5 V loL3 2 0 mA 24 N SAS POO P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P71 P74 P80 to P82 P142 to P144 do not Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RL78 G14 TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Input leakage current high CHAPTER 35
92. 21 to P124 P137 0 3 to 0 3 Note 2 P150 to P156 EXCLK EXCLKS RESET Output voltage to P06 P10 to P17 P30 P31 0 3 to EVppo 0 3 P40 to P47 P50 to P57 P60 to P67 and 0 3 to Vpp 0 3 Note 2 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 P20 to P27 P150 to P156 0 3 to 0 3 Note 2 Analog input voltage ANI16 to ANI20 0 3 to EVppo 0 3 and 0 3 to AVREF 0 3 Notes 2 3 ANIO to ANI14 0 3 to 0 3 and 0 3 to AVREF 0 3 Notes 2 3 Note 1 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it Note 2 Must be 6 5 V or lower Note 3 Do not exceed 0 3 V in case of A D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins Remark 2 AVREF side reference voltage of the A D converter Remark 3 Vss Reference voltage 24 N SAS 2 RL78 G14 CHAPTER
93. 27 P121 to P124 P137 0 3 to 0 3 Note 2 P150 to P156 EXCLK EXCLKS RESET Output voltage to P06 P10 to P17 P30 P31 0 3 to EVppo 0 3 P40 to P47 P50 to P57 P60 to P67 and 0 3 to Vpp 0 3 Note 2 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 P20 to P27 P150 to P156 0 3 to 0 3 Note 2 Analog input voltage ANI16 to ANI20 0 3 to EVppo 0 3 and 0 3 to AVREF 0 3 Notes 2 3 ANIO to ANI14 0 3 to 0 3 and 0 3 to AVREF 0 3 Notes 2 3 Note 1 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it Note 2 Must be 6 5 V or lower Note 3 Do not exceed 0 3 V in case of A D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins Remark 2 AVREF side reference voltage of the A D converter Remark 3 Vss Reference voltage 24 N SAS 2 RL78 G14 C
94. 3 re Note Set the same value as 000C2H to 010C2H when the boot swap operation is used a METTE because 000C2H is replaced by 010C2H Other than above Note Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H Caution Be sure to set bit 5 to 1 and bit 4 to 0 c 2013 Renesas Electronics Corporation All rights reserved Page 35 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E 26 34 4 1 Pin characteristics Incorrect Fixed typo in Note 3 in pages 1181 and 1182 ages 1181 1182 27 34 4 2 Supply current characteristics pages 1186 to 1195 Incorrect Fixed typo in Notes and typical values of IDD2 and IDD3 in pages 1186 to 1195 28 34 5 AC Characteristics Old Specifications of the external system clock frequency and external system clock input high level width low level width in page 1196 to 1197 extended ages 1196 1197 29 34 6 1 Serial array unit Incorrect Fixed typo in 34 6 1 Serial array unit in pages 1198 to 1221 ages 1198 to 1221 30 34 6 2 Serial Interface page 1222 Incorrect Fixed typo in 34 6 2 Serial interface page 1222 31 34 7 1 A D converter characteristics pages 1223 to 1226 Old Specifications of 34 7 1 A D converter characteristics in pages 1223 to 1226 extended 32 34 7 2 Temperature Sensor Internal Reference Voltage Characteristics page 1227
95. 5 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 40 to 85 1 8 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter Slp setup time to SCKp Note 1 Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 30 pF Rb 1 4 HS high speed main mode LS low speed main mode LV low voltage main mode MIN MAX MIN MAX MIN MAX 3 3 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 C 30 pF Rb 5 5 SIp hold time from SCKp Note 1 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 Cb 30 pF Rb 5 5 Delay time from SCKp1 to SOp output Note 1 Note 1 Note 2 Caution 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 30 pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 C 30 pF Rb 5 5 When DAPmn 0 and CKPmn 1 o
96. 6 MHz 1 0 0 9 feu 105 2 27 1 53 9 12 MHz 1 0 9 7 1 60 2 19 8 MHz 1 0 099 fees 105 2 27 1 53 6 MHz 1 0 099 79 1 60 2 19 05 4 MHz 1 0 99 1 3 MHz 1 0 09 fata 79 1 60 2 19 2 MHz 1 0 099 KIZ 105 2 27 1 54 1 MHz 1 0 1025 105 2 27 1 57 When the high speed on chip oscillator clock accuracy is at 1 5 or 2 0 the acceptable range is limited as follows 1 5 Subtract 0 5 from the maximum acceptable value of fin 1 0 and add 0 5 to the minimum acceptable value of fiu 1 0 fiu 2 0 Subtract 1 0 from the maximum acceptable value of fin 1 0 and add 1 0 to the minimum acceptable value of fiu 1 0 Remarks Maximum and minimum acceptable values in the above table are the baud rate acceptable values in UART reception Make sure to set the baud rate for transmission within this range c 2013 Renesas Electronics Corporation All rights reserved Page 33 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 22 23 2 2 STOP Mode page 1050 1052 Refer to No 37 pages 38 to 40 in this document 23 23 2 3 SNOOZE Mode page 1055 Refer to No 37 page 42 in this document 24 27 3 6 Invalid memory access detection function page 1105 Refer to No 38 page 48 in this document c 2013 Renesas Electronics Corporation All rights reserved Page 34 of 50 132 NE SAS
97. 66 tkcy2 2 66 tkcy2 2 66 ns 1 6V lt EVpp0 lt 5 5 V tkcy2 2 66 tkcv2 2 66 ns Slp setup time tsik2 2 7 V lt lt 5 5 V 1 20 1 30 1 30 ns CM 1 8 V lt 5 5 V 1 30 1 30 1 30 ns 1 7 V lt 5 5 V 1 40 1 40 1 40 ns 1 6 V lt lt 5 5 V 1 40 1 40 5 Slp hold time tksi2 1 8 V lt EVpp0 5 5 V 1 fuck 31 1 31 1 31 ns fi SCK al en 1 7 V lt 5 5 V 1 250 1 250 1 250 ns 1 6 V lt 5 5 V 1 250 1 250 ns Delay time tkso2 C 30 pF Note 4 2 7 V lt EVpp0 5 5 V 2 fuick 2 fuck 2 ns from SCKp to 44 110 110 em 2 4 V lt EVpp0 5 5 V 2 2 2 ns 75 110 110 1 8 V lt 5 5 V 2 2 2 ns 100 110 110 1 7 V lt EVpp0 5 5 V 2 2 2 ns 220 220 220 1 6 V lt EVppo lt 5 5 V 2 2 ns 220 220 Note 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0
98. 68 kHz Note 5 TA 105 Square wave input Resonator connection STOP mode Note 8 40 C 25 50 70 85 105 Notes and Remarks are listed on the next page 24 N SAS 16 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into EVppo and EVDp1 including the input leakage current flowing when the level of the input pin is fixed to VDD EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter D A converter comparator LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog
99. 7 lt EVppo lt 4 0 V lt lt 2 7 Theoretical value of the 1 2 Note 4 1 2 Note 4 1 2 Note 4 maximum transfer rate Cb 50 pF Rb 2 7 Vb 2 3 V 8 V EVppo lt 3 3 V Notes 5 6 Notes 5 6 Notes 5 6 6V lt Vb lt 2 0 Theoretical value of the 0 43 Note 7 0 43 Note 7 0 43 Note 7 maximum transfer rate Cb 50 pF Rb 5 5 Vb 1 6 Note 1 The smaller maximum transfer rate derived by using fMck 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt EVppo lt 5 5 V and 2 7 V Vb lt 4 0 V 1 Maximum transfer rate bps Cb x Rb x In 1 m Vb HR Transfer rate x 2 Vb Baud rate error theoretical value x 100 96 1 Number of transferred bits Transfer rate This value is the theoretical value of the relative difference between the transmission and reception sides Note 2 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer Note 3 The smaller maximum transfer rate derived by using
100. 71 P74 P80 to P82 and P142 to P144 do not output high level in N ch open drain mode Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2tENESAS 5 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V 2 5 Conditions Output current low Note 1 Per pin for to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Per pin for P60 to P63 Total of POO to P04 P40 to PA7 4 0V EVppox 5 5 V P102 P120 P130 P140 to P145 57 lt lt 4 0 V When duty lt 70 Note 3 2 4 V x lt 2 7 V Total of P05 P06 P10 to P17 4 0VxEVppox5 5V P30 P31 P50 to P57 27 V EVDDo 4 0 V P60 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 When duty 70 Note 3 2 4 V lt lt 2 7 V Total of all pins When duty lt 70 Note 3 Per pin for P20 to P27 P150 to P156 Total of all pins 24V Vpp 55 V When duty lt 70 Note 3 Note 1 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVsso EVss1 and Vss pins Note 2 However do not exceed the total current valu
101. 8 V EVppo lt 5 5 V 200 200 1 7 V lt lt 5 5 V 400 400 1 6 V lt EVppo lt 5 5 V 400 400 DAPmn 1 2 7 V lt EVppo lt 5 5 V 120 120 1 120 1 8 V EVppo lt 5 5 V fuck 200 200 1 200 1 7 V lt 5 5 V 400 400 1 400 1 6 V lt EVpp0 lt 5 5 V 1 400 1 fuck 400 SSIOO hold time 2 7 V lt EVppo lt 5 5 V 120 120 1 120 1 8 V lt EVppo 5 5 V fuck 200 200 1 200 1 7 V lt EVpp0 5 5 V fuck 400 400 1 400 1 6 V lt EVbpo lt 5 5 V 1 400 1 fuck 400 DAPmn 1 2 7 V lt EVppo lt 5 5 V 120 120 1 8 V lt EVppo lt 5 5 V 200 1 7 V lt lt 5 5 V 400 1 6 V lt lt 5 5 V 400 Caution Select the normal input buffer for the pin and SCKp and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg Remark p CSI number 00 m Unit number m 0 n Channel number n 0 g PIM number g 3 5 CSI mode connection diagram during communication at same potential SCKp SCK RL78 microcontroller 51 SO Users device SOp SI CSI mode connection diagram during communication at same potential Sla
102. ADREFP1 1 ADREFPO 0 reference voltage AVREFM ANI1 ADREFM 1 target pin ANIO ANI2 to ANI14 ANI16 to ANI20 TA 40 to 85 2 4 V lt VpD lt 5 5 V 1 6 V lt EVpp EVDD1 lt VDD Vss EVsso EVssi 0 V Reference voltage VBGR Note 3 Reference voltage AVREFM 0 V Note 4 HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution 24VxVppx5 5V 39 Zero scale error Notes 1 2 8 bit resolution 2 4V lt Vpp lt 5 5V 0 60 Integral linearity error Note 1 8 bit resolution 2 4 V lt Vpop lt 5 5 V 2 0 Differential linearity error Note 1 8 bit resolution 2 4 V lt VDD lt 5 5 V 1 0 Analog input voltage VBGR Note 3 Note 1 Excludes quantization error 1 2 LSB Note 2 This value is indicated as a ratio FSR to the full scale value Note 3 Refer to 34 6 2 Temperature sensor characteristics internal reference voltage characteristic Note 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVREFM Integral linearity error Add x0 5 LSB to the MAX value when reference voltage AVREFM Differential linearity error Add x0 2 LSB to the MAX value when reference voltage AVREFM 34 NC SAS 62 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 6 2 Temperature sensor characteristics inter
103. APTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKcv1 SCKp tsiK1 tksi1 51 Input data SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKcv1 SCKp SOp Output data Remark 1 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 24 N SAS 48 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input TA 40 to 85 1 8 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V HS high speed main mode MIN Parameter SCKp cycle time Note 1 Conditions 4 0 V lt EVppo lt 5 5 V 24 MHz lt fuck LS low speed main mode LV low voltage main mode 14 fuck MAX MAX MAX 20 MHz lt fuck lt 24 MHz
104. At this time make sure to clear bit 2 AWC 0 SNOOZE mode release in A D converter mode register 2 ADM2 to 0 If the AWC bit is left set to 1 A D conversion will not start normally in subsequent SNOOZE or normal operation mode c 2013 Renesas Electronics Corporation All rights reserved Page 23 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 13 Explanations when using temperature sensor and internal reference voltage 1 45 V of the AID test function in the Safety functions chapter added Explanation of 14 7 4 Setup when using temperature sensor added page 655 Incorrect 14 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 14 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register there is a possibility of no interrupt signal being generated In this case the results are not stored in the ADCR ADCRH registers Correct 14 7 4 Setup when using temperature sensor example for software trigger mode and one shot conversion mode Figure 14 35 Setup When Using Temperature Sensor Omitted Note Depending on the settings of the ADRCK bit and ADUL ADLL register interrupt signals may not be generated this case the results are not stored in ADCR and ADCRH registers Caution This setting can be selected only in HS high speed main mode c 2013 Renesas Ele
105. CAL UPDATE TN RL A004C E c 2013 Renesas Electronics Corporation All rights reserved Page 47 of 50 RENESAS Date October 2013 3 When LVD is in reset mode option byte 000C 1H LVIMDS1 LVIMDSO 1 1 Supply voltage Operating voltage range lower limit V VPOR 1 51 V TYP Veor 1 50 V TYP ov Wait for oscillation Wait for oscillation T Note 3 i Wait for oscillation accuracy stabilization r accuracy stabilization 1 accuracy stabilization High speed on chip oscillator clock fiH t i Starting oscillation is Starting oscillatjon is Tow Starting oscillation js Specified by software by software UNDE specified by software High speed system H f WE clock n when X1 oscillation Normal operation Reset period Normal operation Reset period H is selected i i high speed on chip 818001 high speed on chip oscilation stops Note 2 910 5 Normal operation high speed on chip oscillator clock Note 2 TN Note 4 Ha at i FN Note 4 V 1 LVD reset processing time id Ox LVD reset processing time 1 i ix Voltage stabilization wait time POR processing time LV 1 64 ms TYP 3 10 ms max oscillator clock 2 od EENEN Note 2 CPU Operation stops oscillator clock
106. D lt 5 5 V LV low voltage main mode 4 MHz 1 6 V lt Vpb lt 5 5 V Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the TxDq by using port input mode register g PIMg and port output mode register g POMg For and see the DC characteristics with TTL input buffer selected Vb V Communication line voltage UART number q 0 to 3 g PIM and POM number g 0 1 5 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 UART2 cannot communicate at different potential when bit 1 PIORO1 of peripheral I O redirection register 0 PIORO is 1 24 N SAS 38 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode TA 40 to 85 1 6 V x EVDD1 x VDD lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX Transfer transmission 4 0 V lt EVppo lt 5 5 V rate 27V lt Vb lt 4 0 V Theoretical value of the 2 8 Note 2 2 8 Note 2 2 8 Note 2 maximum transfer rate 50 pF Rb 1 4 Vb 2
107. DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and SCKp pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance when 64 to 100 products mode for the SOp pin by using port input mode register PIMg and port output mode register POMg For Vin and ViL see the DC characteristics with TTL input buffer selected CSI mode connection diagram during communication at different potential Slave Vb SCKp RL78 microcontroller Slp SO Users device SOp SI Remark 1 Rb Q Communication line SOp pull up resistance Ce F Communication line SOp load capacitance Vb V Communication line voltage Remark 2 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 Remark 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential Also communication at different potential cannot be performed during clock synchronous serial communication with the slave select function 24 N SAS 50 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 CSI mode se
108. DLE 10 bit resolution 1 8 V lt lt 5 5 V 1 5 LSB Von 3 1 6 V lt lt 5 5 V Note 4 20 LSB Analog input voltage Van ANI2 to ANI14 0 AVREFP V Internal reference voltage Note 5 V 2 4 V lt lt 5 5 V HS high speed main mode Temperature sensor output voltage V1MPs25 Note 5 V 2 4 V lt lt 5 5 V HS high speed main mode Note 1 Excludes quantization error 1 2 LSB Note 2 This value is indicated as a ratio FSR to the full scale value Note 3 When AVREFP lt VDD the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVREFP VDD Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVREFP VDD Note 4 Values when the conversion time is set to 57 us min and 95 us max Note 5 Refer to 34 6 2 Temperature sensor characteristics internal reference voltage characteristic 24 N SAS 59 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 When reference voltage AVREFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFM ANH ADREFM 1 target pin ANI16 to ANI20 40 to 85 1 6 V lt EVpDo EVDD1 lt VDD lt 5 5 V 1 6 V lt AVREFP lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVREFP Refere
109. Date Oct 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document Category No TN RL A004C E Rev 3 00 Correction for Incorrect Description Notice RL78 G14 Information Title Descriptions in the User s Manual Hardware Rev 1 00 Technical Notification Changed Category Lot No Applicable RL78 G14 Group Reference Product R5F104xxx RL78 G14 User s Manual Hardware D t Rev 1 00 All lots ocumen RO1UHO186EJO100 Dec 2011 This document describes misstatements found in the RL78 User s Manual Hardware Rev 1 00 RO1UH0186EJ0100 Corrections Applicable Item Applicable Page Incorrect descriptions of reset processing time standby mode Pages 1049 1052 to p p 9 y 1055 1060 1061 Incorrect descriptions revised release time 1072 1073 27 3 6 Invalid memory access detection function Page 1105 Incorrect descriptions revised Cautions of flash memory programming by self programming Page 1142 Incorrect descriptions revised Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 50 zENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Corrections in the User s Manual Hardware Corrections and Applicable Items Pages in this No
110. E2 LV low voltage main mode 1to 4 MHz 1 6 to 5 5 V LS low speed main mode 1to 8 MHz 1 8 to 5 5 V 1 to 16 MHz 2 4t0 5 5 V S high speed main mode 1 to 32 MHz 2 7 to 5 5 V 2 Set the HOCODIV register while the high speed on chip oscillator clock fiu is selected as the CPU peripheral hardware clock 3 After the frequency has been changed using the HOCODIV register and the following transition time has been elapsed the frequency is switched The device operates at the frequency for the duration of 3 clocks before the frequency has been changed The CPU peripheral hardware clock waits for maximum 3 clocks at the frequency after the frequency has been changed c 2013 Renesas Electronics Corporation All rights reserved Page 17 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 9 Incorrect descriptions of reset processing time standby mode release time revised Incorrect descriptions of HALT mode release time revised page 1048 Incorrect Figure 23 3 HALT Mode Release by Interrupt Request Generation Interrupt HALT request instruction Standby release signal i Status of CPU Operating mede HALT mode 1 Wait Noe di Operating mode Oscillation High speed system clock High speed on chip oscillator clock or subsystem clock Note Wait time for HALT mode release e When vectored interrupt servicing is not carried ou Main system c
111. EV lt 5 5 V 1013 1 0 mA Caution P00 P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P71 P74 P80 to P82 P142 to P144 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 24 N SAS 8 RL78 G14 TA 40 to 85 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Input leakage current high CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Conditions to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Vi P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 EXCLK XT1 XT2 EXCLKS In input port or external clock input In resonator connection Input leakage current low to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Vi EVsso P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 EXCLK XT1 XT2 EXCLKS In input port or external clock input In resonator connection On chip pull up resistance Remark to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P10
112. EVbppo lt 5 5 V gt 3 5 MHz 1 8 V lt EVppo lt 5 5 V Setup time of restart tsu sta 2 7 V lt lt 5 5 V condition 1 8 V lt lt 5 5 V Hold time Note 1 tHD sTA 2 7 V lt lt 5 5 V 1 8 V lt lt 5 5 V Hold time when SCLAO L 2 7 V lt EVppo lt 5 5 V 1 8 V lt lt 5 5 V Hold time when SCLAO 2 7 V EVppo lt 5 5 V 1 8 V lt lt 5 5 V Data setup time reception 2 7 lt lt 5 5 V 1 8 V lt EVpp0 lt 5 5 V Data hold time transmission tHD 2 7 V lt 0 lt 5 5 V Note 2 1 8 V lt EVpp0 lt 5 5 V Setup time of stop condition tsu sto 2 7 V lt lt 5 5 V 1 8 V lt lt 5 5 V Bus free time 2 7 V lt EVppo lt 5 5 V 1 8 V lt lt 5 5 V Note 1 The first clock pulse is generated after this period when the start restart condition is detected Note 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIORO2 in the peripheral I O redirection register 0 PIORO is 1 At this time the pin characteristics loH1 loL1 VoL1 must satisfy the values in the redirect destination Rem
113. EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 1 fuck 30 1 fuck 30 1 fuck 30 Slp hold time from SCKpT Note 4 1 fuck 31 1 fuck 31 1 fuck 31 Delay time from to SOp output Note 5 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 30 pF Rb 1 4 2 120 2 573 2 573 2 7 V lt lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 2 214 2 573 2 573 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 Cb 30 pF Rv 5 5 Notes Cautions and Remarks are listed on the next page 2 573 2 573 2 573 49 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 1 Transfer rate in the SNOOZE mode MAX 1 Mbps Note 2 Use it with gt Vb Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or
114. F Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V x Vb lt 2 0 V Cb 30 pF Rb 5 5 Delay time from SCKp to SOp output Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 Note When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register PIMg and port output mode register POMg For and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page 24 N SAS 38 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output TA 40 to 105 2 4 V lt EVDDo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 3 3 Parameter Conditions HS high speed main mode MIN MAX Slp setup time to SCKp Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVDpo lt 4 0 V 2 3 V lt Vb lt 2 7
115. FFFH 12288 x 8 bit FCFOOH to FFEFFH 20000H R5F104xG x A toC E to G J L M P 131072 x 8 bit 00000H to 1FFFFH 16384 x 8 bit FBFOOH to FFEFFH 20000H c 2013 Renesas Electronics Corporation All rights reserved Page 49 of 50 132 NE SAS R5F104xH E to G J L M P 196608 x 8 bit 00000H to 2FFFFH 20480 x 8 bit FAFOOH to FFEFFH 30000H R5F104xJ x F G J L M P 262144 x 8 bit 00000H to 3FFFFH 24576 x 8 bit 9 to FFEFFH 40000H RENESAS TECHNICAL UPDATE TN RL A004C E 39 Cautions of flash memory programming by self programming added page 1142 Incorrect 30 7 Flash Memory Programming by Self Programming Omitted Caution 1 The self programming function cannot be used when the CPU operates with the subsystem clock Caution 2 To prohibit an interrupt during self programming in the same way as in the normal operation mode execute the self programming library in the state where the IE flag is cleared 0 by the DI instruction To enable an interrupt clear 0 the interrupt mask flag to accept in the state where the IE flag is set 1 by the El instruction and then execute the self programming library Caution 3 When enabling RAM parity error resets RPERDIS 0 be sure to initialize the RAM area to use 10 bytes before overwriting c 2013 Renesas Electronics Corporation All rights reserv
116. HAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Absolute Maximum Ratings 2 2 Parameter Symbols Conditions Ratings Output current high Per pin to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Total of all POO to P04 P40 to P47 P102 P120 P130 pins P140 to P145 170 POs POG P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Output current low Per pin to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Total of all POO to P04 P40 to P47 P102 P120 P130 pins P140 to P145 170 pos poe P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P100 P101 P110 P411 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Operating ambient In normal operation mode 40 to 85 temperature In flash memory programming mode Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore
117. IFICATIONS TA 40 to 105 CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKCY2 tKL2 tKH2 SCKp tsik2 gil tksi2 Slp Input data SOp Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKcv2 a tKH2 res tKL2 SCKp tsik2 RN tKsi2 Sip Input data tKso2 SOp Output data Remark 1 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential Also communication at different potential cannot be performed during clock synchronous serial communication with the slave select function 24 N SAS 44 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 7 40 to 105 8 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode TA 40 to 105 2 4 V lt EVppo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 1 2 Parameter Conditions HS high speed main mode MIN MAX SCLr clock frequency fscL 4 0 V lt EVppo
118. Incorrect Fixed typo in 34 7 2 Temperature Sensor Internal Reference Voltage Characteristics in page 1227 33 34 7 5 POR circuit characteristics Incorrect Fixed typo in 34 7 5 POR circuit characteristics in page 1228 age 1228 Page 36 of 50 132 NE SAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 Correct Refer to pages 5 and 6 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Correct Refer to pages 10 to 16 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C New Refer to page 20 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Correct Refer to pages 27 to 54 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C Correct Refer to pages 55 to 58 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 New Refer to pages 59 to 62 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Correct Refer to page 63 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Correct Refer to page 64 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 RENESAS TECHNICAL UPDATE TN RL A004C E Date Octobe
119. L SPECIFICATIONS 40 to 105 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKCY1 2 tKL1 2 tKH1 2 SCKp tSIK1 2 tksi1 2 51 Input data lt tKSO1 2 SOp Output data tssik tkssi SSI00 100 only CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKCY1 2 SCKp 51 SOp tkssi 55100 5100 only 5 is Remark 1 p CSI number p 00 01 10 11 20 21 30 31 Remark 2 m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 30 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 4 During communication at same potential simplified 12C mode 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V Parameter Conditions HS high speed main mode MIN MAX SCLr clock frequency 2 7 V EVppo lt 5 5 V 400 Note 1 Cb 50 pF Rb 2 7 kQ 2 4 V EVppo lt 5 5 V 100 Note 1 Cb 100 pF Rb KQ Hold time when SCLr L 2 7 V EVppo lt 5 5 V 1200 Cb 50 pF Rb 2 7 kQ 2 4V lt EVppo lt 5 5 V 4600 Cb 100 pF Rb 3 kQ Hold time when SCLr 2 7 V EVppo lt 5 5 V 1200 Cb 50 pF Rb 2 7 kQ 2 4 V lt EVopo lt 5
120. L VoL External System Clock Timing 1 fEx 1 fExs EXCLK EXCLKS TI TO Timing TIOO to T110 to TI13 1 fro gt TOOO0 to TO10 to TO13 TRJIOO TRJOO TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 TRDIOCO TRDIOC1 TRDIODO TRDIOD1 TRGIOA TRGIOB 2tENESAS 23 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 tTJIH TRJIO tTDIH TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 TRDIOCO TRDIOC1 TRDIODO TRDIOD1 trpsiL INTPO I trciL tTGIH TRGIOA TRGIOB 2tENESAS 24 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Interrupt Request Input Timing tINTL INTPO to INTP11 Key Interrupt Input Timing to KR7 RESET Input Timing tRSL 34 NC SAS 25 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 5 Peripheral Functions Characteristics AC Timing Test Points ViH VoH C Test points ViH VoH ViL VoL ViL VoL 35 5 1 Serial array unit 1 During communication at same potential UART mode 40 to 105 C 2 4 V lt EVppo EVpp1 lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions HS high speed main Mode MIN MAX Transfer rate Note 1 2 4 V lt lt 5 5 V 12 Note 2 Theoretical value of the maximum transfer rate 2 6 Note 3
121. LVIMDSO 1 0 Supply voltage Prob i Operating voltage range lower limit Von 1 51 V Veon 1 50 V ____ 1 Wait for oscillation ae accuracy stabilization Wait for oscillation Nea accuracy stabilization i High speed on chip oscillator clock fiH Starting oscillation ie T Starting oscillation is specified by software specified by software f High speed system when 1 oscillation Reet pore d Normal operation ees high speed on chip _ oscillator clock Note 2 is selected Normal operation high speed on chip oscillator clock Note 2 Operation sions LVD reset processing time Noe CPU Operation stops NE LVD reset processing lime Note 5 Voltage stabilization wait time POR processing time 1 64 ms TYP 3 10 ms max 0 Voltage stabilization wait time POR processing time 1 64 ms 3 10 ms max Internal reset signal INTLVI Omitted Note 5 Before the MCU starts normal operation it requires the voltage stabilization wait time POR processing time after the voltage reaches VPOR 1 51 V TYP and also requires the following LVD reset processing time after the voltage reaches the LVD detection level VLvpH LVD reset processing time 0 ms TYP to 0 0701 ms max Go on to the next page RENESAS TECHNI
122. Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 C is the load capacitance of the SOp output lines Note 5 The maximum transfer rate when using the SNOOZE mode is 1 Mbps Caution Select the normal input buffer for the pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg ztENESAS 31 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Remark 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM number g 0 1 3 to 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 34 NC SAS 32 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 4 During communication at same potential CSI mode slave mode SCKp external clock input TA 40 to 85 1 6 V x EVDD1 x VDD lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX 55100 setup time DAPmn 0 2 7 V lt EVppo lt 5 5 V 120 120 1
123. Other than the above Setting prohibited Correct 1 A D test register ADTES Figure 27 15 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES1 ADTESO A D conversion target 0 0 ANIxx This is specified using the analog input channel specification register ADS 1 0 AVREFM 1 1 AVREFP Other than the above Setting prohibited Note The temperature sensor output and internal reference voltage output 1 45 V can be selected only in HS high speed main mode c 2013 Renesas Electronics Corporation All rights reserved Page 28 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 17 Explanations of the data flash in the Flash memory chapter added page 1133 Incorrect An overview of the data flash memory is provided below e The data flash memory can be written to by using the flash memory programmer or an external device e Programming is performed in 8 bit units e Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading reading four clock cycles Omitted e Manipulating the DFLCTL register is not possible while rewriting the data flash memory e When data flash is accessed the CPU waits for three clock cycles Correct An overview of the data flash memory is provided below For details about how to rewrite the data flash memory refer to RL78 Family Flash Data Library User s Manual The
124. P VDD Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when VDD Note 4 When lt lt VoD the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVREFP VDD Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVREFP VDD Note 5 When the conversion time is set to 57 us min and 95 us max 24 N SAS 60 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 3 When reference voltage ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to 20 internal reference voltage and temperature sensor output voltage 40 to 85 C 1 6 V lt EVDD1 lt lt 5 5 V Vss EVsso EVss1 0 V Reference voltage VDD Reference voltage Vss Parameter Conditions Resolution Overall error Note 1 10 bit resolution 1 8 V lt lt 5 5 V 1 6 V lt lt 5 5 V Note 3 Conversion time 10 bit resolution 3 6 V lt lt 5 5 V Target pin ANIO to ANI14 ANI16 to ANI20 2 7 V lt Voo lt 5 5 V 1 8 V lt Voo lt 5 5 1 6 V lt Voo lt 5 5 1
125. P147 Normal input buffer 0 8 EVDDo 3 5 P01 P04 P10 P14 to P17 P30 P31 P43 P44 P50 TTL input buffer 4 0 V lt EVpp0 lt 5 5 V P53 to P55 P80 P81 P142 P143 TTL input buffer 3 3 V lt lt 4 0 V 2 0 TTL input buffer 1 6 V x EVppo lt 3 3 V 1 5 P20 to P27 P150 to P156 0 7 VDD P60 to P63 0 7 0 6 0 P121 to P124 P137 EXCLK EXCLKS RESET 0 8 VDD VDD Input voltage low Caution to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Normal input buffer 0 0 2 P04 P10 P14 to P17 P30 P31 P43 P44 P50 TTL input buffer 4 0 V lt EVpp0 lt 5 5 V P53 to P55 P80 P81 P142 P143 TTL input buffer 3 3 V lt lt 4 0 V 0 5 TTL input buffer 1 6 V x EVppo lt 3 3 V 0 32 P20 to P27 P150 to P156 0 3 VDD P60 to P63 0 3 P121 to P124 P137 EXCLK EXCLKS RESET P74 P80 to P82 and P142 to P144 is even in the N ch open drain mode Remark 24 N SAS 0 2 VDD Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins The maximum value of of pins P00 P02 to P04 P10 P11 P13 to P15 P17 P30 P43 to P45 P50 to P55 P71 RL78 G14
126. Ri and status flags of interrupt sources related to their bits are 0 write O to applicable status flags Example To clear the IMFB bit to 0 when bits IMIEA and OVIE are set to 1 interrupt enabled and the IMIEB bit is set to O interrupt disabled Timer RD Interrupt Enable Register i TRDIERI Interrupt enabled OVIE IMIED IMIEB f IMIEA Interrupt disabled Timer RD Status Register TRDSRi Bit to be cleared to 0 UDF OVF IMFD IMFB IMFA As status flags OVF IMFA corresponding to the bit which is set to 1 interrupt enabled are 0 write 0 to the IMFB bit Go on to the next page c 2013 Renesas Electronics Corporation All rights reserved Page 7 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 c When there are bits set to 1 interrupt enabled in timer RD interrupt enable register i TRDIERi and status flags of interrupt sources related to their bits are 1 write O to these status flags and applicable status flags at the same time Example To clear the IMFB bit to O when the IMIEA bit is set to 1 interrupt enabled and the IMIEB bit is set to 0 interrupt disabled Timer RD Interrupt Enable Register i TRDIERI Interrupt disabled Timer RD Status Register i TRDSRi TRDSRi we As the status flag IMFA corresponding to the bit which is set to 1 interrupt enabled
127. S 40 to 105 35 6 2 Temperature sensor characteristics internal reference voltage characteristic 40 to 105 2 4 V lt lt 5 5 V Vss EVsso EVss1 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage VTMPs25 Setting ADS register 80H TA 25 Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient Fvtmps Temperature sensor that depends on the temperature Operation stabilization wait time tAMP 35 6 3 D A converter characteristics TA 40 to 105 C 2 4 V lt EVsso EVss1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Resolution Overall error Rload 4 24V lt Vpp lt 5 5V Rload 8 MQ 24 lt lt 5 5 Settling time Cload 20 pF 2 7 V lt lt 5 5 2 4 V lt VoD lt 2 7 V 53 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 6 4 Comparator TA 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Input voltage range EVppo 1 4 EVppo 0 3 Output delay Voo 3 0 V Comparator high speed mode 1 2 Input slew rate gt 50 mV us standard mode Comparator high speed mode 2 0 window mode Comparator low speed mode 3 0 5 0 standard mode
128. SI21 cannot communicate at different potential Use other CSI for communication at different potential 24 N SAS 41 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 7 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main mode MIN MAX SCKp cycle time Note 1 4 0 V x EVppo lt 5 5 V 24 MHz lt fuck 28 2 7 V lt Vb lt 4 0 V 20 MHz lt fuck lt 24 MHz 24 fMck 8 MHz lt lt 20 MHz 20 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 2 7 V lt EVppo lt 4 0 V 24 MHz lt fuck 40 fuck 2 3V lt Vb lt 2 7V 20 MHz lt fuck lt 24 MHz 32 16 MHz lt fuck lt 20 MHz 28 8 MHz lt lt 16 MHz 24 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 2 4 V lt EVppo lt 3 3 V 24 MHz lt fuck 96 fuck 1 6 lt lt 2 0 20 MHz lt fuck lt 24 MHz 72 16 MHz lt fuck lt 20 MHz 64 fMck 8 MHz lt fuck lt 16 MHz 52 4 MHz lt fuck lt 8 MHz 32 fuck lt 4 MHz 20 fMck SCKp high low level 2 tkL2 4 0 V lt lt 5 5 V 2 7 V lt Vb lt 4 0 V 2 2 24 width 2 7 V lt
129. Total of all pins When duty lt 70 Note 3 Per pin for P20 to P27 P150 to P156 Total of all pins 1 6 lt lt 55V When duty lt 70 Note 3 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVsso EVss1 and Vss pins However do not exceed the total current value Specification under conditions where the duty factor lt 7096 The output current value that has changed to the duty factor gt 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to Total output current of pins loL x 0 7 n x 0 01 Example Where n 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 24 N SAS 6 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 TA 40 to 85 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Input voltage high Conditions to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to
130. V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 Slp hold time from SCKp Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V EVDpo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V x Vb lt 2 0 V Cb 30 pF Rb 5 5 Delay time from SCKpt to SOp output Note 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Rb 1 4 KQ 2 7 V lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 Note When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register PIMg and port output mode register POMg For and see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 24 N SAS 39 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 CSI mode connection diagram during communication at different potential Master Vb Vb SCKp RL78 microcontroller Slp SO Users device SOp SI Remar
131. Voo lt 5 5 V LV low voltage main mode 4 MHz 1 6 V lt Vpb lt 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg 24 N SAS 27 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User s device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remark 1 q UART number q 0 to 3 g PIM and POM number g 0 1 5 14 Remark 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 34 NC SAS 28 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 During communication at same potential CSI mode master mode SCKp internal clock output corresponding CSIOO only 40 to 85 2 7 V lt 1 lt VoD lt 5 5 V Vss EVsso 51 0 V Parameter Conditions HS high speed LS low speed LV low voltage main mode main mode main mode MIN MAX MIN MAX MIN MAX SCKp cycle time 1 gt 2 fctk 4 0 V lt EVbpo l
132. age 1 45 V 1 Setting prohibited When ADREFP1 or ADREFPO bit is rewritten this must be configured in accordance with the following procedures 1 Set ADCE 0 2 Change the values of ADREFP1 and ADREFPO 3 Stabilization wait time A 4 Set ADCE 1 5 Stabilization wait time B he setting i anged to Us 0 and 1 Aneeds no wait and B 1 us When ADREFP1 and ADREFPO are set to 1 and 0 respectively A D conversion cannot be performed on the temperature sensor output Be sure to perform A D conversion while ADISS 0 Specification of the SNOOZE mode Do not use the SNOOZE mode function Use the SNOOZE mode function When there is a hardware trigger signal in the STOP mode the STOP mode is exited and A D conversion is performed without operating the CPU the SNOOZE mode e The SNOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware clock fcx If any other clock is selected specifying this mode is prohibited e Using the SNOOZE mode function in the software trigger mode or hardware trigger no wait mode is prohibited e Using the SNOOZE mode function in the sequential conversion mode is prohibited Nhe c 2013 Renesas Electronics Corporation All rights reserved Page 21 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Correct 4 A D converter mode register 2 ADM2 Omitted ADREFP1
133. ark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode Cb 320 pF Rb 1 1 KQ 24 N SAS 57 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 3 12C fast mode plus TA 40 to 85 1 6 V lt EVppo EVDD1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions HS high speed LS low speed LV low voltage main mode main mode main mode MIN MAX SCLAO clock frequency fscL Fast mode plus 2 7 V lt EVbpo lt 5 5 V gt 10 MHz Setup time of restart 50 STA 2 7 V lt EVppo lt 5 5 V condition Hold time Note 1 tHD STA 2 7 V lt EVppo lt 5 5 V Hold time when SCLAO L 2 7 V lt lt 5 5 V Hold time when SCLAO tHiGH 2 7 V lt EVppo lt 5 5 V Data setup time reception tsu paT 2 7V lt lt 5 5 V Data hold time transmission tup par 2 7 V lt EVop0 lt 5 5 V Note 2 Setup time of stop condition 0 2 7 V lt EVbppo lt 5 5 V Bus free time tBUF 2 7 V lt EVppo lt 5 5 V Note 1 The first clock pulse is generated after this period when the start restart condition is detected Note 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing C
134. aution The values in the above table are applied even when bit 2 PIORO2 in the peripheral I O redirection register 0 PIORO is 1 At this time the pin characteristics loL1 1 VoL1 must satisfy the values in the redirect destination Note 3 The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode plus Cb 120 pF Rb 1 1 kO IICA serial transfer timing tLow SCLAn tHD DAT tHD STA SDAAn Stop Stop condition condition condition condition Remark 0 1 58 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 6 Analog Characteristics 34 6 1 A D converter characteristics Classification of A D converter characteristics nes Reference Voltage ANIO to ANI14 Reference voltage AVREFP Reference voltage AVREFM Refer to 34 6 1 1 ANI16 to ANI20 Refer to 34 6 1 2 Internal reference voltage Refer to 34 6 1 1 Reference voltage VoD Reference voltage Vss Refer to 34 6 1 3 Reference voltage VBGR Reference voltage AVREFM Refer to 34 6 1 4 Temperature sensor output voltage 1 When reference voltage AVREFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFM ANI1 ADREFM 1 target pin ANI2 to ANI14 internal reference voltag
135. b communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 Fast mode Cb 320 pF Rb 1 1 KQ IICA serial transfer timing tLow SCLAn tHD DAT tHD STA SDAAn pasi Stop Start Restart Stop condition condition condition condition Remark n 0 1 24 N SAS 48 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 6 Analog Characteristics 35 6 1 A D converter characteristics Classification of A D converter characteristics nes Reference Voltage ANIO to ANI14 Reference voltage AVREFP Reference voltage AVREFM Refer to 35 6 1 1 Reference voltage VoD Reference voltage Vss Refer to 35 6 1 3 Reference voltage VBcR Reference voltage AVREFM Refer to 35 6 1 4 ANI16 to ANI20 Refer to 35 6 1 2 Internal reference voltage Temperature sensor output voltage Refer to 35 6 1 1 1 When reference voltage AVREFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFM ANI1 ADREFM 1 target pin ANI2 to ANI14 internal reference voltage and temperature sensor output voltage TA 40 to 105 C 2 4 V lt AVREFP lt VDD lt 5 5 V Vss 0 V Reference voltage AVREFP Reference voltage AVREFM 0 V Parameter Conditions Resolution 10 bit resolution 2 4 V lt lt 5 5 V
136. ctronics Corporation All rights reserved Page 24 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Explanation of 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins in 14 10 Cautions for A D Converter added page 662 Incorrect 14 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANIO to ANI14 and ANI16 to ANI26 pins input voltage If a voltage of Voo and AVrerp or higher and Vss and AVrerm or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal reference voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Correct 14 10 Cautions for A D Converter 2 Input range of ANIO to ANI14 and ANI16 to ANI26 pins Observe the rated range of ANIO to ANI14 and ANI16 to ANI26 pins input voltage voltage of and AVrerp or higher and Vss and AVnerw or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addi
137. d interrupt servicing is carried out If interrupt acknowledgement is disabled the next address instruction is executed Figure 23 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock Omitted Note Wait time for STOP mode relea High lock X1 illation 3 cloc Page 39 of 50 132 NE SAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 Correct 2 STOP mode release The STOP mode can be released by the following two sources a Release by unmasked interrupt request When an unmasked interrupt request is generated the STOP mode is released After the oscillation stabilization time has elapsed if interrupt acknowledgement is enabled vectored interrupt servicing is carried out If interrupt acknowledgement is disabled the next address instruction is executed Figure 23 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock Omitted Note 1 For details of the standby release signal see Figure 21 1 Basic Configuration of Interrupt Function Note 2 STOP mode release time Supply of the clock is stopped When FRQSEL4 0 18 us to whichever is longer 65 us or the oscillation stabilization time set by OSTS When FRQSELA 1 18 ys to whichever is longer 135 ps or the oscillation stabilization time set by OSTS Wait Whe
138. d even if 0 is written to it Even if the bit is changed from 0 to 1 If the read value is 1 writing to the bit sets it to 0 When status flags of interrupt sources applicable status flags of the timer RG are set to 0 and their interrupts are disabled in the timer RG interrupt enable register TRGIER use either one of the following methods a to c Set 00H all interrupts disabled to timer interrupt enable register TRGIER and write 0 to applicable status flags Go on to the next page c 2013 Renesas Electronics Corporation All rights reserved Page 11 of 50 RENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 b When there are bits set to 1 interrupt enabled in timer RG interrupt enable register TRGIER and status flags of interrupt sources related to their bits are 0 write O to applicable status flags Example To clear the TRGIMFB bit to 0 when bits TRGIMIEA and TRGOVIE are set to 1 interrupt enabled and the TRGIMIEB bit is set to 0 interrupt disabled Timer RG Interrupt Enable Register TRGIER Interrupt enabled TRGIER TRGOVIE fJ TRGUDIE TRGIMIEB TRGIMIEA 1 0 0 1 Interrupt disabled Timer RG Status Register TRGSR TRGDIRF TRGOVF TRGUDF f TRGIMFB f TRGIMFA 0 0 1 1 0 As status flags TRGOVF TRGIMFA corresponding to the bit which is set to 1 interrupt enabled write O to the TRGIMFB bit c When there are
139. d product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used Caution 2 With products not provided with an EVpp1 EVsso or EVss1 pin replace EVppo and 1 with VDD or replace EVsso and EVssi with Vss Caution 3 The pins mounted depend on the product Refer to 2 1 Port Functions to 2 2 1 With functions for each product There are following differences between the products Industrial applications TA 40 to 105 and the products A Consumer applications and D Industrial applications Parameter A Consumer applications D Industrial applications G Industrial applications Operating ambient temperature TA 40 to 85 40 to 105 Operating mode Operating voltage range HS high speed main mode 2 7 V lt 5 5 V1 MHz to 32 MHz 2 4 V lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt VDD lt 5 5 Vg 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt VDD lt 5 5 Vg 1 MHz to 4 MHz HS high speed main mode only 2 7 V lt Vpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz High speed on chip oscillator clock accuracy 1 8 V lt Voo lt 5 5 V 1 0 TA 20 to 85 1 5 40 to 20 C 1 6 V lt Voo lt 1 8 V 5 0 TA 20 to 85 5 5 40 to 20 C 2 4 V
140. data flash memory can be written to by using the flash memory programmer or an external device Flash memory is programmed in 8 bit units Blocks can be deleted in 1 KB units Only byte read is allowed as CPU instructions 1 clock cycle wait 3 clock cycles Omitted Manipulating the DFLCTL register is prohibited while rewriting the data flash memory Transition to HALT STOP state is prohibited while rewriting the data flash memory 18 Cautions of flash memory programming by self programming added page 1142 Refer to No 39 page 50 in this document c 2013 Renesas Electronics Corporation All rights reserved Page 29 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 19 Items of flash memory programming characteristics added page 1231 Incorrect 34 10 Flash memory programming characteristics Ta 740 to 85 C 1 8 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVss 0 V Parameter Conditions CPU peripheral hardware clock 1 8 V lt VDD lt 5 5 V frequency Number of code flash rewrites 1 erase 1 write Retained for 20 years after the erase is Self serial regarded as 1 programming Number of data flash rewrites rewrite Retained for 1 years 1 000 000 The retaining years Self serial programming Retained for 5 years 100 000 Self serial programming are until next rewrite Note after the rewrite Note Note When using
141. de When the low speed on chip oscillator is selected IFiL should be added 1002 subsystem clock operation includes the operational current of the real time clock Note 4 Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip oscillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either 1001 002 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscillator is selected IFIL should be added 24 N SAS 18 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 5 Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or 003 and when the watchdog timer is in operation Note 6 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lapc when the A D converter operates in an operation mode or the HALT mode Note 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of 1002 or 003 and ILvb when the LVD circuit is in operation Note 8 Current flowing during programming of the data flash Note 9 Current flowing during self programming Note 10 For shift time to the SNOOZE m
142. e Note 3 Specification under conditions where the duty factor lt 7096 The output current value that has changed to the duty factor gt 7096 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to Total output current of pins loL x 0 7 n x 0 01 Example Where n 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 24 N SAS 6 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V Input voltage high Conditions to P06 P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P140 to P147 Normal input buffer 0 8 EVDDo 3 5 P01 P04 P10 P14 to P17 P30 P31 P43 P44 P50 TTL input buffer 4 0 V lt EVpp0 lt 5 5 V P53 to P55 P80 P81 P142 P143 TTL input buffer 3 3 V lt lt 4 0 V 2 0 TTL input buffer 2 4 V lt lt 3 3 V 1 5 P20 to P27 P150 to P156
143. e and temperature sensor output voltage TA 40 to 85 C 1 6 V lt AVREFP lt VDD lt 5 5 V Vss 0 V Reference voltage AVREFP Reference voltage AVREFM 0 V Parameter Conditions Resolution RES 8 10 bit Overall error Note 1 10 bit resolution 1 8 V lt AVrerp lt 5 5 V 1 2 3 5 LSB AVRErP Von Note 3 1 6 V lt AVREFP lt 5 5 V Note 4 12 70 LSB Conversion time 10 bit resolution 3 6 V lt Voo lt 5 5 V 2 125 39 us Target pin ANI2 to ANI14 2 7 lt lt 5 5 V 3 1875 39 us 1 8 V lt lt 5 5V 17 39 us 1 6 V lt lt 5 5 V 57 95 us 10 bit resolution 3 6 V lt Voo lt 5 5 V 2 375 39 us Target pin Internal reference voltage 5 7 y lt Vpp 5 5 V 3 5625 39 us and temperature sensor output voltage HS high speed main mode 2 4 V lt lt 5 5V 17 39 us Zero scale error Notes 1 2 Ezs 10 bit resolution 1 8 V lt lt 5 5 V 0 25 FSR Vop Note 3 1 6 V lt lt 5 5 V Note 4 0 50 FSR Full scale error Notes 1 2 5 10 bit resolution 1 8 V lt lt 5 5 V 0 25 FSR Von Note 3 1 6 V lt lt 5 5 V Note 4 0 50 FSR Integral linearity error Note 1 ILE 10 bit resolution 1 8 V lt lt 5 5 V i25 LSB AVREFP Note 3 1 6 V lt AVREFP lt 5 5 V Note 4 50 LSB Differential linearity error Note 1
144. e 4 3 0 V 0 50 2 00 fuoco 16 MHz Voo 5 0 V 0 44 1 49 16 MHz Note 4 Voo 3 0 V 044 149 LS low speed main 8 MHz Voo 3 0 V 290 800 8 MHz Note 4 Voo 2 0 V 290 800 LV low voltage fHoco 4 MHz Voo 3 0 V 440 755 mode Note 7 4 MHz Note 4 Voo 2 0 V 440 755 HS high speed main fmx 20 MHz Note 3 Square wave input 0 31 1 63 mA mode 50V Resonator connection 0 50 1 85 fmx 20 MHz Note 3 Square wave input 0 31 1 63 30V Resonator connection 0 50 1 85 fmx 10 MHz Note 3 Square wave input 0 21 0 89 50V Resonator connection 0 30 0 97 fmx 10 MHz Note 3 Square wave input 0 21 0 89 30V Resonator connection 0 30 0 97 LS low speed main fmx 8 MHz Note 3 Square wave input 110 580 mode Note 7 Voo 30V Resonator connection 160 630 fmx 8 MHz Note 3 Square wave input 110 580 Voo 20V Resonator connection 160 630 Subsystem clock 32 768 kHz Note5 Square wave input 0 28 0 66 operation 40 Resonator connection 0 47 0 85 fsuB 32 768 kHz Note 5 Square wave input 0 34 0 66 25 Resonator connection 0 53 0 85 fsuB 32 768 kHz Note 5 Square wave input 0 37 2 35 50 Resonator connection 0 56 2 54 32 768 kHz Note 5 Square wave input 0 61 4 08 70 Resonator connection 0 80 4 27 32 768 kHz Note 5 Square wave input 1 55 8
145. e wave input Resonator connection fmx 10 MHz Note 2 5 0 operation Square wave input Resonator connection fux 10 MHz Note 2 Voo 3 0 V operation Square wave input Resonator connection Subsystem clock operation Notes and Remarks are listed on the next page fsuB 32 768 kHz Note 4 40 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 25 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 50 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 70 Normal operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 85 operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 105 operation Square wave input Resonator connection 24 N SAS 14 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Note 1 Note 2 Note 3 Note 4 Note 5 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into EVppo and EVpp1 including the input leakage current flowing when the level of the input pin is fixed to VDD EVppo and EVpp1 or Vss EVsso a
146. ed Page 50 of 50 RENESAS Date Correct 30 7 Flash October 23 2013 Memory Programming by Self Programming Omitted Caution 1 The self programming function cannot be used when the CPU operates with the subsystem clock Caution 2 Caution 3 Caution 4 To prohibit an interrupt during self programming in the same way as in normal operation mode execute the self programming library in the state where the IE flag is cleared 0 by the DI instruction To enable an interrupt clear 0 the interrupt mask flag to accept in the state where the IE flag is set 1 by the El instruction and then execute the self programming library When enabling RAM parity error resets RPERDIS 0 make sure to initialize the RAM area to use 10 bytes before overwriting The high speed on chip oscillator needs to keep oscillating during self programming When the high speed on chip oscillator is stopped oscillate the high speed on chip oscillator clock HIOSTOP 0 and execute the flash self programming library after 30 us elapsed when the FRQSEL4 in the user option byte 000C2H is 0 otherwise execute the flash self programming library after 80 us elapsed RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 This chapter describes the electrical specifications for the products A Consumer applications TA 40 to 85 and
147. ependently connect to EVopo or EVsso EVss1 P61 SDAAO via a resistor P62 SCLA1 Output Leave open P63 SDAA1 P64 TI10 TO10 P65 TI11 TO11 P66 TI12 TO12 P67 TI13 TO13 Omitted Correct Table 2 3 Connection of Unused Pins 100 pin products 2 3 Pin Name Circuit Type Recommended Connection of Unused Pins P60 SCLAO Input Connect these pins independently to EVopo EVpp or P61 SDAAO EVsso EVss via a resistor Output Set 0 to the port output latch when using these pins left open Set 1 to the port output latch when connecting these pins independently to EVpp1 or EVsso EVss1 via a resistor P62 SCLA1 P63 SDAA1 P64 T110 TO10 Input Connect these pins independently to EVbp or P65 TI11 TO11 EVsso EVss via a resistor P66 TI12 TO12 Output Leave open P67 T113 TO13 Omitted c 2013 Renesas Electronics Corporation All rights reserved Page 5 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 3 Explanations of the timer RD status register added Explanations of the timer RD status register added pages 470 472 Incorrect Notes 1 The value after reset is undefined when FRQSEL4 1 in the user option byte 000C2H 010C2H and TRDOEN 0 in the PER1 register If it is necessary to read the initial value set fcuk to and TRDOEN 1 before reading Omitted 4 The
148. er c 2013 Renesas Electronics Corporation All rights reserved Page 16 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 8 Cautions of the high speed on chip oscillator frequency select register HOCODIV revised page 284 Incorrect 8 High speed on chip oscillator frequency select register HOCODIV Omitted Caution 1 Set the HOCODIV register within the operable voltage range both before and after changing the frequency Caution 2 Use the device within the voltage of the flash operation mode set by the option byte 000C2H 010C2H even after the frequency has been changed by using the HOCODIV register Option Byte Flash Operation Mode Operating Frequency Operating Voltage 000C2H 010C2H Value Range Range CMODE1 CMODE2 LV low voltage main mode 1to 4 MHz 1 6 to 5 5 V LS low speed main mode 1to 8 MHz 1 8 to 5 5 V 1 to 16 MHz 2 4 t0 5 5 V S high speed main mode 1 to 32 MHz 2 7 to 5 5 V i i m clock device op at the old Correct 8 High speed on chip oscillator frequency select register HOCODIV Omitted Caution 1 When changing the frequency of the high speed on chip oscillator by the HOCODIV register make sure the previously set frequency and newly set frequency fall within the operating frequency range for the flash operation mode set by the option byte 000C2H Option Byte Flash Operation Mode Operating Frequency Operating Voltage 000C2H Value Range Range CMODE1 CMOD
149. er rate 2 6 Note 2 Cb 50 pF Rb 1 4 Vb 2 7V V lt EVppo lt 4 0 V V lt Vb lt 2 7 V Theoretical value of the maximum transfer rate 1 2 Note 4 Cb 50 pF Rb 2 7 Vb 2 3 V V lt EVppo lt 3 3 V V lt Vb lt 2 0 V Theoretical value of the maximum transfer rate 0 43 Note 6 50 pF Rb 5 5 Vb 1 6 V Note 1 The smaller maximum transfer rate derived by using fmcK 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt EVppo lt 5 5 V and 2 7 V Vb lt 4 0 V 1 Maximum transfer rate bps Cb x Rb x In 1 22 x3 Vb 1 Transfer rate x 2 Baud rate error theoretical value x 100 96 1 Transfer rate x Rb x In 1 2229 Vb x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides Note 2 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer Note 3 The smaller maximum transfer rate derived by using 12 or the following expression is the valid maximum
150. flash memory programmer and Renesas Electronics self programming library Correct Ta 740 to 85 C 1 8 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVss 0 V Parameter Conditions CPU peripheral hardware clock frequency 1 8 V lt VoD lt 5 5 V Number of code Retaining years 20 years Ta 85 C flash rewrites etes 1 23 Retaining year 1 year Ta 25 C 1 000 000 Number of data flash rewrites Notes 123 Retaining years 5 years Ta 85 C 100 000 Retaining years 20 years Ta 85 C 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 This characteristics is shown as the flash memory characteristics and based on Renesas Electronics reliability test c 2013 Renesas Electronics Corporation All rights reserved Page 30 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 20 3 1 3 Internal Data Memory Space page 105 Incorrect Correct Cautions 2 While self programming is being executed or rewriting the data flash do not allocate the RAM address which is used in stack data buffer the branch of vectored interrupt servicing or the transfer destination or source by DTC in the R5F104xD x A to C E to J L FE900H to FED09H address between FFE20H
151. ghts reserved Description First edition issued Incorrect descriptions of No 1 to No 19 revised Rev 2 00 issued Revisions of No 20 to No 36 incorrect descriptions added Rev 3 00 issued Incorrect descriptions of No 37 to No 39 revised This notification Page 3 of 50 RENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Specifications of the on chip oscillator characteristics in the Electrical specifications chapter fixed page 1179 Incorrect 34 3 2 On chip oscillator characteristics Ta 40 to 85 C 1 6 V lt EVDD1 lt lt 5 5 V Vss EVsso EVss1 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency High speed on chip oscillator 20 to 85 1 8 V lt Voo lt 5 5 V clock frequency accuracy 1 lt lt 18 40 to 20 C 1 8 V lt Voo lt 5 5 V 1 6 V lt Voo lt 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected with bits 0 to 4 of the option byte 000 2 010 2 and bits 0 to 2 of the HOCODIV register 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time When SSOP 30 WQEN 32 40 48 FLGA 36 LQFP 7 x 7 48 pin LQFP 10 x 10 52 pin LQFP 12 x 12 64
152. her 1 1 002 and IRTC when the real time clock operates in operation mode or HALT mode When the low speed on chip oscillator is selected IFiL should be added 1002 subsystem clock operation includes the operational current of the real time clock Note 4 Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip oscillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either 1001 002 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscillator is selected IFIL should be added 24 N SAS 18 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 5 Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of Ipp1 1002 or 003 and when the watchdog timer is in operation Note 6 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lapc when the A D converter operates in an operation mode or the HALT mode Note 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of IDD1 1002 or 003 and ILvb when the LVD circuit is in operation Note 8 Current flowing during programming of the data flash
153. illator and XT1 oscillator refer to 5 4 System Clock Oscillator 35 2 2 On chip oscillator characteristics 40 to 105 2 4 V lt lt 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency Notes 1 2 High speed on chip oscillator clock frequency 20 to 85 2 4 V lt VDD lt 5 5 V 40 to 20 2 4 V lt lt 5 5 85 to 105 2 4 V lt lt 55V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Note 1 High speed on chip oscillator frequency is selected with bits 0 to 4 of the option byte 000C2H and bits 0 to 2 of the HOCODIV register Note 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time 24 N SAS 4 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 35 3 DC Characteristics 35 3 1 Pin characteristics TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V 1 5 Output current high Note 1 Per pin for to P06 2 4 V lt lt 5 5 V Note 1 Note 2 Note 3 Caution Remark Conditions P10 to P17 P30 P31 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 to P102 P110 P111 P120 P130 P140 to P147 Total of POO to P04 P40 to
154. it 2 AWC of A D converter mode register 2 ADM2 to 0 Doing this sets the clock request signal an internal ignal to the low level and stops the supply of the high speed on chip oscillator clock e While in the scan mode If even one A D conversion end interrupt request signal INTAD is generated durin D conversion of the four hannels the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal operation mode To stop the high speed on chi cillator clock supplied while in the NOOZE mode clear bit 2 AWC of A D converter mode register 2 ADM2 to 0 Doing this sets the clock request signal an internal signal to the low level and stops the supply of the high speed on chip oscillator clock Correct 1 If an interrupt is generated after A D conversion ends Omitted e In select mode When A D conversion ends and an A D conversion end interrupt request signal INTAD is generated the A D converter returns to normal operation mode from SNOOZE mode At this time make sure to clear bit 2 AWC 0 SNOOZE mode release in A D converter mode register 2 ADM2 to 0 If the AWC bit is left set to 1 A D conversion will not start normally in subsequent SNOOZE or normal operation mode e In scan mode If even one A D conversion end interrupt request signal INTAD is generated during A D conversion of four channels the A D converter transits from SNOOZE mode to normal operation mode
155. k 5 Rb Q Communication line SCKp SOp pull up resistance Communication line SCKp SOp load capacitance Vb V Communication line voltage Remark 6 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 7 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 Remark 8 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 34 NC SAS 40 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKcv1 SCKp tsiK1 tksi1 51 Input data SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKcv1 SCKp SOp Output data Remark 1 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 2 CSIO1 of 48 52 64 pin products and CSI11 and C
156. lags of interrupt sources related to their bits are 1 write O to these status flags and applicable status flags at the same time Example To clear the TRGIMFB bit to O when the TRGIMIEA bit is set to 1 interrupt enabled and the TRGIMIEB bit is set to 0 interrupt disabled Timer RG Interrupt Enable Register TRGIER TRGIER TRGOVIE TRGUDIE 9 TRGIMIEB TRGIMIEA 0 0 0 1 Interrupt disabled Timer RG Status Register TRGSR TRGDIRF TRGIMFB 0 1 1 As the status flag TRGIMFA corresponding to the bit which is set to 1 interrupt enabled is 1 write 0 to bits TRGIMFB and TRGIFMA at the same time c 2013 Renesas Electronics Corporation All rights reserved Page 14 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 7 Descriptions in the comparator block diagram improved Descriptions in the comparator block diagram improved page 675 Incorrect Figure 16 1 Comparator Block Diagram po iiic C1FCK1 C1FCKO 01 o 8 1085 clock 11 32 o Both edge C1EDG detection C1WDE Digital filter EE match C1EPOL 0 3 times C1FCKO One edge lt 7 other thaln detection 0 l l 1 1 ELC event 1 IVCMP1 1 IVREF1 Internal reference voltage
157. llation Secun stabilization 0 Us or more 1Wait for oscillation stabilization 9 2 High speed system clock fmx when X1 oscillation is selected Internal reset signal Operation Starting oscillation is __ specified by softwara 7w 1 Reset processing 4 if Normal operation high speed on chip oscillator clock 3 Starting oscillation 5 _ an NN Stop 1 ispeciied by software N Normal operation high speed on chip Reset processing oscillation Operation stops CPU stops Internal reset signal Notes 4 Reset processing time 155 to 407 us c 2013 Renesas Electronics Corporation All rights reserved oscillator clock 3 1 Page 45 of 50 RENESAS Date October Correct Supply voltage Operating voltage range lower limit Noe 1 Veon 1 51 V Veor 1 50 V ov 4 RESET pin High speed on chip 2013 Figure 25 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 2 1 When using an external reset by the RESET pin Wait for oscillation accuracy stabilization Note 2 Wait for oscillation t accuracy stabilization inn Note 2 oscillator clock when X1 oscillation is selected Starting oscillation i
158. lock to 9 clock ubsystem clock RTCLPC 0 3 to 4 clock u em clock RTCLPC 1 4 to 5 clock Correct Figure 23 3 HALT Mode Release by Interrupt Request Generation Interrupt HALT request n X Standby release signal 1 Status of CPU Operating mede HALT mode L Wait Note 2 L Operating mode Oscillation High speed system clock High speed on chip oscillator clock or subsystem clock Notes 1 For details of the standby release signal see Figure 21 1 2 Wait time for HALT mode release e When vectored interrupt servicing is carried out Main system clock 15 to 16 clocks Subsystem clock RTCLPC 0 10 to 11 clocks Subsystem clock RTCLPC 1 11 to 12 clocks When vectored interrupt servicing is not carried out Main system clock 9 to 10 clocks Subsystem clock RTCLPC 0 4 to 5 clocks Subsystem clock RTCLPC 1 5 to 6 clocks For details about incorrect descriptions in pages 1049 1050 1052 to 1055 1060 1061 1072 and 1073 refer to No 37 pages 38 to 47 in this document c 2013 Renesas Electronics Corporation All rights reserved Page 18 of 50 RENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 10 Cautions of A D converter mode register 0 ADMO added page 613 Incorrect 2 A D converter mode register 0 ADMO Omitted Notes 1 For details of the FR2 to FRO LV1 LVO bits and A D conversion see Table 14 3 A D Conversion Time Selection
159. lt 5 5 V Total of to P04 P40 to P47 P102 P120 P130 P140 to P145 When duty lt 70 Note 3 4 0V lt lt 5 5 V 2 7 V lt EVppo lt 4 0 V 1 8 V lt lt 2 7 V 1 6 V lt lt 1 8 V Total of P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P100 P101 P110 P111 P146 P147 When duty lt 70 Note 3 4 0V lt EVpp0 lt 5 5V 2 7 V x EVppo lt 4 0 V 1 8 V lt lt 2 7 V 1 6 V x EVppo lt 1 8 V Total of all pins When duty lt 70 Note 3 1 6 V x lt 5 5 V Per pin for P20 to P27 P150 to P156 1 6V lt Vpp lt 5 5V Total of all pins When duty lt 70 Note 3 However do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Total output current of pins x 0 7 n x 0 01 lt Example gt However the current that is allowed to flow into one pin does not vary depending on the duty factor Where n 80 and loH 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA 1 6 V lt VoD lt 5 5 V Value of current at which the device operation is guaranteed even if the current flows from the
160. main mode 4 99 us to 9 44 us 7 clocks LS Low speed main mode 1 10 us to 5 08 us 7 clocks LV Low voltage main mode 16 58 us to 25 40 us 7 clocks When vectored interrupt servicing is not carried out HS High speed main mode 4 99 us to 9 44 us 1 clock LS Low speed main mode 1 10 to 5 08 us 1 clock LV Low voltage main mode 16 58 us to 25 40 us 1 clock The operating statuses in the SNOOZE mode are shown next RENESAS TECHNICAL UPDATE TN RL A004C E Incorrect descriptions of reset processing time revised pages 1060 1061 Incorrect Figure 24 2 Timing of Reset by RESET Input Wait for oscillation stabilization High speed on chip oscillator clock Starting X1 oscillation is specified by software High speed system clock when X1 oscillation is selected i Reset period i Normal operation d Normal operation CPU status high speed on chip oscillator clock RESET M Reset processing 387 to 674 us When LVD is used 155 to 360 us When LVD off Internal reset signal Port pin except P130 Port pin P130 Figure 24 3 Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overfiow Wait for oscillation accuracy stabilization High speed on chip oscillator clock High speed system clock l when X1 oscillation is selected CPU status Starting X1 oscillation rs specified by softwa
161. main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Vpp lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Vpp lt 5 5 V 1 MHz to 4 MHz fx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation temperature condition of the value is 25 34 NC SAS 15 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 85 C 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions 2 2 Supply 1002 HALT mode high speed main fHoco 64 MHz Voo 5 0 V 0 88 3 32 mA current Note 1 Note 2 mode Note 7 fiu 2 32 MHz Note 4 Vop 3 0V 0 88 3 32 fuoco 32 MHz Voo 5 0 V 0 62 2 63 32 MHz Note 4 Voo 3 0 V 0 62 263 fuoco 48 MHz Voo 5 0 0 68 2 57 24 MHz Note 4 3 0 V 0 68 2 57 fuoco 24 MHz Voo 5 0 V 0 50 2 00 24 MHz Not
162. mode Subsystem clock fsuB operation 1 8 V lt VoD lt 5 5 V 28 5 In the self HS high speed main 2 7 V lt lt 5 5 V 0 03125 programming mode 2 4 V lt VDD lt 2 7 V 0 0625 mode LS low speed main 1 8 V lt lt 5 5 V 0 125 mode LV low voltage main 1 8 V lt lt 5 5 V 0 25 mode External system clock 2 7 V lt VDD lt 5 5 V 1 0 frequency 2 4 V lt lt 2 7 V 1 0 1 8 V lt VDD lt 2 4 V 1 0 1 6 V lt Vpp lt 1 8 V 1 0 32 External system clock 2 7 V lt VDD lt 5 5 V 24 input high level width 24 lt lt 27 30 low level width 1 8 V lt VDD 24 V 60 1 6 V lt Voo lt 1 8 V 120 tEXHS tEXLS 13 7 TIOO to TIO3 TI10 to triH 1 fuck 10 TI13 input high level Note width low level width Timer RJ input cycle 2 7 V lt EVppo lt 5 5 V 100 1 8 V lt lt 2 7 V 300 1 6 V lt lt 1 8 V 500 Timer RJ input high 2 7 V lt lt 5 5 V 40 level width low level 1 8 V lt EVppo lt 2 7 V width 1 6 V lt EVppo lt 1 8 V Note The following conditions are required for low voltage interface when lt VDD 1 8 V x lt 2 7 V MIN 125 ns 1 6 V x EVppo lt 1 8 V MIN 250 ns Remark Timer array unit operation clock frequency Operation clock to be set by the CKSmn bit of
163. mode SCKp external clock input 40 to 105 2 4 V x EVppo EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 2 Parameter Conditions HS high speed main mode 85100 setup time DAPmn 0 2 7 V lt EVppo lt 5 5 V 240 MIN MAX 2 4 V EVppo 5 5 V 400 DAPmn 1 2 7 V lt 5 5 V 1 240 2 4 V lt EVpp0 lt 55V 1 400 100 hold time 2 7 V EVppo 5 5 V 1 240 Caution Remark 2 4 V lt lt 5 5 V 1 400 DAPmn 1 2 7 V lt EVppo lt 5 5 V 240 2 4 V EVppo lt 5 5 V 400 Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg p CSI number p 00 m Unit number m 0 n Channel number n 0 PIM number g 3 5 CSI mode connection diagram during communication at same potential SCKp SCK RL78 microcontroller 51 SO Users device SOp SI CSI mode connection diagram during communication at same potential Slave Transmission of slave select input function CSIOO SCKOO 5100 RL78 microcontroller User s device 000 100 Remark 1 p CSI number 00 01 10 11 20 21 30 31 Remark 2 m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 29 RL78 G14 CHAPTER 35 ELECTRICA
164. mx 20 MHz Note 3 Square wave input 0 28 1 55 mA mode Note 7 5 0 V Resonator connection 0 49 1 74 fux 20 MHz Note 3 Square wave input 0 28 1 55 30V Resonator connection 0 49 1 74 fux 10 MHz Note 3 Square wave input 0 19 0 86 5 0 V Resonator connection 0 30 0 93 fmx 10 MHz Note 3 Square wave input 0 19 0 86 30V Resonator connection 0 30 0 93 LS low speed main fux 8 MHz Note 3 Square wave input 95 550 mode Note 7 Voo 3 0 V Resonator connection 145 590 fmx 8 MHz Note 3 Square wave input 95 550 Voo 2 0 V Resonator connection 145 590 Subsystem clock 32 768 kHz Note 5 Square wave input 0 25 0 57 uA operation 40 Resonator connection 0 44 0 76 32 768 kHz Note 5 Square wave input 0 30 0 57 25 Resonator connection 0 49 0 76 32 768 kHz Note 5 Square wave input 0 36 1 17 50 Resonator connection 0 59 1 36 32 768 kHz Note 5 Square wave input 0 49 1 97 70 Resonator connection 0 72 2 16 32 768 kHz Note 5 Square wave input 0 97 3 37 85 Resonator connection 1 16 3 56 Ipp3 STOP mode 40 0 18 0 51 uA Noise Noes 25 C 0 24 0 51 50 0 29 1 10 70 0 41 1 90 85 0 90 3 30 Notes and Remarks are listed on the next page 24 N SAS 12 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85
165. n operation in the SNOOZE mode finishes be sure to set the STm1 bit to 1 and clear the SEm1 bit to stop the operation Correct Omitted Caution Before transiting to SNOOZE mode and after the receive operation is completed in SNOOZE mode set the STm1 bit to 1 clear the SEm1 bit to 0 and stop the operation And after the receive operation is completed also clear the SWCm bit to 0 SNOOZE mode release c 2013 Renesas Electronics Corporation All rights reserved Page 26 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 15 Explanations of the power on reset circuit added pages 1070 1071 Incorrect 25 1 Functions of Power on reset Circuit The power on reset circuit POR has the following functions Generates internal reset signal at power on The reset signal is released when the ly volta Vpop exceeds 1 51 V 0 03 V Vpp lt VPpR Omitted 25 3 Operation of Power on reset Circuit An internal reset signal is nerated on wer application When the ly voltage Voo exceeds the detection voltage VPon the reset tus is released ly voltage Vno and detection voltage Vepr compared When lt the internal reset signal is generated The timing of generation of the internal reset signal by the power on reset circuit and voltage detector is shown below Correct 25 1 Functions of Power on reset Circuit The power on reset circuit
166. n vectored interrupt servicing is carried out 10 to 11 clocks When vectored interrupt servicing is not carried out 4 to 5 clocks Caution To reduce the oscillation stabilization time after release from the STOP mode while CPU operates based on the high speed system clock X1 oscillation switch the clock to the high speed on chip oscillator clock temporarily before executing the STOP instruction Remark 1 The clock supply stop time varies depending on the temperature conditions and STOP mode period Remark 2 The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged RENESAS TECHNICAL UPDATE TN RL A004C E Figure 23 5 STOP Mode Release by Interrupt Request Generation 2 2 2 When high speed system clock external clock input is used as CPU clock Omitted 3 When high speed on chip oscillator clock is used as CPU clock Omitted c 2013 Renesas Electronics Corporation All rights reserved Page 40 of 50 RENESAS Date October 2013 Figure 23 5 STOP Mode Release by Interrupt Request Generation 2 2 2 When high speed system clock external clock input is used as CPU clock Omitted Note 1 For details of the standby release signal see Figure 21 1 Basic Configuration of Interrupt Function Note 2 STOP mode release time Supply of the clock is stopped When FRQSELA 0 18 to 65 us When FRQSEL4 1 18 ys to 135 us Wait When vectored i
167. nal reference voltage characteristic TA 40 to 85 2 4 V lt lt 5 5 V Vss EVsso EVss1 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage VTMPs25 Setting ADS register 80H TA 25 C Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient Fvtmps Temperature sensor that depends on the temperature Operation stabilization wait time tAMP 34 6 3 D A converter characteristics 40 to 85 1 6 V lt EVsso 551 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Resolution Overall error Rload 4 1 8 V lt 00 lt 5 5 V Rload 8 1 8 lt lt 5 5 Settling time Cload 20 pF 2 7 V lt lt 5 5 1 6 V lt VoD lt 2 7 V 63 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 6 4 Comparator TA 40 to 85 1 6 V lt EVpp1 lt Vpp lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Input voltage range EVppo 1 4 EVppo 0 3 Output delay Voo 3 0 V Comparator high speed mode 1 2 Input slew rate gt 50 mV us standard mode Comparator high speed mode 2 0 window mode Comparator low speed mode 3 0 5 0 standard mode High electric potential Comparator high speed mode window mode 0 76 refe
168. nce voltage AVREFM 0 V Parameter Conditions Resolution Overall error Note 1 10 bit resolution 1 8 V lt AVREFP lt 5 5 V EVppo lt Notes 3 4 1 6 V lt lt 5 5 V Note 5 Conversion time 10 bit resolution 3 6 V lt Voo lt 5 5 V 39 Target ANI ANI16 to ANI20 27V lt lt 5 5 39 1 8 lt lt 5 5 39 1 6 V lt lt 5 5 V 95 Zero scale error Notes 1 2 10 bit resolution 1 8 V lt lt 5 5 V 0 35 lt AVRerP Vo 934 lt AVReFP lt 5 5 V Note 5 0 60 Full scale error Notes 1 2 10 bit resolution 1 8 V x lt 5 5 V 0 35 Notes 3 4 Agen T NOD Or 1 6 V lt lt 5 5 V Note 5 0 60 Integral linearity error Note 1 10 bit resolution 1 8 V lt lt 5 5 V 3 5 Notes 3 4 AV REER VDD TaS 1 6 V lt lt 5 5 V Note 5 6 0 Differential linearity error Note 1 10 bit resolution 1 8 V lt lt 5 5 V 2 0 Notes 3 4 AV REER Mop des 1 6 V lt lt 5 5 V Note 5 25 Analog input voltage ANI16 to ANI20 AVREFP and Note 1 Excludes quantization error 1 2 LSB Note 2 This value is indicated as a ratio FSR to the full scale value Note 3 When lt AVREFP lt VDD the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVREF
169. ncluding the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequenc
170. ncy fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation temperature condition of the value is TA 25 34 NC SAS 11 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 1 Flash ROM 16 to 64 KB of 30 to 64 pin products TA 40 to 85 1 6 V lt EVDDo0 lt VDD lt 5 5 V Vss EVsso 0 V 2 2 Parameter Conditions Supply current 1552 HALT mode high speed main fuoco 64 MHz Voo 5 0 V 0 80 3 09 mA Note 1 Note 2 mode Note 7 iH 32 MHz Note 4 Voo 30V 0 80 3 09 fuoco 32 MHz Voo 5 0 0 54 2 40 32 MHz Note 4 Voo 3 0 V 0 54 240 48 MHz Voo 5 0 V 0 62 2 40 24 MHz Note 4 Voo 3 0 V 0 62 2 40 Hoco 24 MHz Voo 5 0 0 44 1 83 24 MHz Note 4 3 0 V 0 44 1 83 Hoco 16 MHz Voo 5 0 V 0 40 1 38 16 MHz Note 4 3 0 V 040 1 38 LS low speed main 8 MHz Voo 3 0 V 260 710 uA mode Note 7 iH 8 MHz Note 4 Voo 2 0 V 260 710 LV low voltage main fHoco 4 MHz Voo 3 0 V 420 700 uA mode Note 7 iH 4 MHz Note 4 Voo 2 0 V 420 700 HS high speed main f
171. nd EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter D A converter comparator LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When 1 1 Ultra low power consumption oscillation However not including the current flowing into the 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz fx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation temperature condition of the value is 25 34 NC SAS 15 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS 40 to 105 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 105 2 4 V lt
172. nection 24 N SAS 10 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 1 Note 2 Note 3 Note 4 Note 5 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into and EVppo including the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Vpp lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz fx High speed system clock frequency X1 clock oscillation frequency or external main system clock freque
173. nel number n 0 9 PIM and POM numbers g 1 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 24 N SAS 29 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 3 During communication at same potential CSI mode master mode SCKp internal clock output 40 to 85 1 6 V lt EVppo 1 lt VoD lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions HS high speed LS low speed main LV low voltage main mode mode main mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcy1 gt 4 fcik 2 7 V lt Evppo lt 5 5 V 500 1000 2 4 V lt EVopo lt 5 5 V 500 1000 1 8 V lt EVppo 5 5 V 500 1000 1 7 V EVopo 5 5 V 1000 1000 1 6 V EVppo lt 5 5 V 1000 1000 SCKp high low level 4 0 V EVppo 5 5 V tkcv1 2 12 tkcy1 2 50 1 2 50 width 2 7 V EVppo 5 5 V tkcv1 2 18 tkcy1 2 50 tkcv1 2 50 2 4 V EVppo 5 5 V tkcv1 2 38 tkcy1 2 50 tkcy1 2 50 1 8 V EVppo 5 5 V tkcv1 2 50 tkcy1 2 50 1 2 50 1 7 V EVppo 5 5 V tkcy1 2 100 tkcy1 2 100 tkcy1 2 100 1 6 V lt EVppo 5 5 V tkcy1 2 100 tkcv1 2 100 Slp setup time 4 0 V lt 5 5 V 44 110 110 to SCKp1 Note 1 2 7 V EVppo
174. ng into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V x Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fuoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation temperature condition of the value is TA 25 34 NC SAS 11 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS 40 to 105 1 Flash ROM 16 to 64 KB of 30 to 64 pin products TA 40 to 105 2 4 V lt EVDDO0 lt VDD lt 5 5 V Vss EVsso 0 V Parameter Supply current Note 1 1002 Note 2 HALT mode HS high speed main mode Note 7 Conditions fuoco 64 MHz iH 32 MHz Note 4 Voo 5 0 V Voo 3 0 V fHoco 32 MHz 32 MHz Note 4 Voo 5 0 V Voo 3 0 V 48 MHz fiH 24 MHz Note 4 Voo 5 0 V Voo 3 0 V Hoco 24 MHz fiH 24 MHz Note 4 Voo 5 0 V Voo 3 0 V 16 MHz 16 MHz Note 4 Voo 5 0 V Voo 3 0 V 2 2 HS high speed main mode Note 7 MX
175. ns VPoc2 VPoc1 VPoco 0 0 0 falling reset voltage lt VLVDA1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage VLVDA2 LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage Vpoc1 VPoco 0 0 1 falling reset voltage LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage VPoc1 VPoco 0 1 0 falling reset voltage LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage VPoct VPoco 0 1 1 falling reset voltage LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage 34 6 7 Power supply voltage rising slope characteristics 40 to 85 Vss 0 V lt lt lt lt lt lt S
176. nterrupt servicing is carried out 7 clocks When vectored interrupt servicing is not carried out 1 clock 3 When high speed on chip oscillator clock is used as CPU clock Omitted Note 1 For details of the standby release signal see Figure 21 1 Basic Configuration of Interrupt Function Note 2 STOP mode release time Supply of the clock is stopped When FRQSEL4 0 18 us to 65 us When FRQSEL4 1 18 us to 135 us Wait When vectored interrupt servicing is carried out 7 clocks When vectored interrupt servicing is not carried out 1 clock Remark 1 The clock supply stop time varies depending on the temperature conditions and STOP mode period Remark 2 The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged RENESAS TECHNICAL UPDATE TN RL A004C E Date October b Release by reset signal generation b Release by reset signal generation When the reset signal is generated STOP mode is released and then as in the case with a When the reset signal is generated STOP mode is released and then as in the case with a normal reset operation the program is executed after branching to the reset vector address normal reset operation the program is executed after branching to the reset vector address Figure 23 6 STOP Mode Release by Reset Figure 23 6 STOP Mode Release by Reset 1 When high speed system clock is used as CPU clock 1 When high speed system clock is
177. o lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ HS high speed main mode LS low speed main mode LV low voltage main mode MIN MAX MIN MAX MIN MAX 2 2 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 20 pF Rb 2 7 KQ SIp hold time from Note 2 4 0 V EVppo lt 5 5 V 27V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 kO 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V 20 pF Rb 2 7 Delay time from SCKpt to SOp output Note 2 Note 1 Note 2 Caution 4 0 V EVppo lt 5 5 V 27V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 kO 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 20 pF Rb 2 7 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For ViH and ViL see the DC characteristics with TTL input buffer selected Remark 1 Rb Q Communication line SCKp SOp pull up resistance Communication line SCKp SOp load capacitance Vb V Communication line voltage Remark 2 p CSI number p 00 m Unit number m
178. o an external device set P130 to high level output by software Remark For the reset timing of the power on reset circuit and voltage detector see Chapter 25 POWER ON RESET CIRCUIT and Chapter 26 VOLTAGE DETECTOR Page 44 of 50 7tENESAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 Figure 24 4 Timing of Reset in STOP mode by RESET Input Wait for oscillation accuracy stabilization i m STOP instruction execution High speed on chip oscillator clock High speed system clock when X1 oscillation is selected CPU status Normal operation 28 7 Starting X1 oscillation is specified by software 7 Reset Stop status H Normal operation oscillation stop ME high speed on chip oscillator clock RESET Reset processing 0 0511 ms TYP ME 0 0701 ms MAX Internal reset signal Port pin except P130 Port pin P130 Notes 1 When P130 is set to high level output before reset is effected the output signal of P130 can be dummy output as a reset signal to an external device because P130 outputs a low level when reset is effected To release a reset signal to an external device set P130 to high level output by software 2 Reset processing time when an external reset is released The first reset processing time after POR is released 0 672 ms TYP 0 832 ms max When LVD is used 0 399 ms TYP 0 519
179. o the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Vbpp lt 5 5 V 1 MHz to 32 MHz 2 4 V lt VDD lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Vpp lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 34 NC SAS 17 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 3 Peripheral Functions Common to all products TA 40 to 85 1 6 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVss1 0 V Parameter Low speed on chip oscillator operating current Iri Note 1 Conditions RTC operating current Notes 1 2 3 12 bit interval timer operating current Notes 1 2 4 Watchdog timer operating current Iwpr Notes 1 2 5 fil 15 kHz
180. ode see 23 3 3 SNOOZE mode Note 11 Current flowing only to the D A converter The supply current of the RL78 microcontrollers is the sum of or Ipp2 and IpAc when the D A converter operates in an operation mode or the HALT mode Note 12 Current flowing only to the comparator circuit The supply current of the RL78 microcontrollers is the sum of 002 or 1203 and when the comparator circuit is in operation Note 13 comparator and D A converter are provided in products with 96 KB or more code flash memory Remark 1 fiL Low speed on chip oscillator clock frequency Remark 2 fsuB Subsystem clock frequency XT1 clock oscillation frequency Remark 3 CPU peripheral hardware clock frequency Remark 4 Temperature condition of the value is TA 25 34 NC SAS 19 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS 40 to 105 35 4 Characteristics TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V 1 2 Conditions Instruction cycle Main system HS high speed main 2 7 V lt lt 5 5 V 0 03125 minimum instruction clock fuAiN mode 24V lt 27V execution time operation 0 0625 Subsystem clock fsuB operation 24V Vppx x5 5V 28 5 In the self HS high speed main 2 7 V lt lt 5 5 V 0 03125 programming mode 24V lt Vpp lt 2 7V mode External system clock 2 7 V lt VDD
181. or clock fiu is specified either as 64 or 48 MHz 2 The transfer rate in SNOOZE mode is 4800 bps only 3 When the SWCm bit is 1 UARTq can be used only when the reception is started in STOP mode If UARTq is used with other SNOOZE function or interrupts concurrently and the reception is started in state other than STOP mode as described below the UARTq cannot receive data correctly and may cause framing error or parity error When the UARTq reception is started from the moment the SWCm bit is set to 1 before the MCU enters STOP mode When the UARTq reception is started in SNOOZE mode When the UARTq reception is started from the moment the MCU exits STOP mode and enters normal mode using interrupts before the SWCm bit is set to 0 RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 4 When the SSECm bit is 1 if a parity error framing error or overrun error occurs flags PEFmn FEFmn or OVFmn is not set nor an error interrupt INTSREq is generated To set the SSECm bit to 1 clear flags PEFmn FEFmn and OVFmn before setting the SWCO bit to 1 and read bits 7 to 0 RxDq in the SDRm1 register Table 17 3 UART Reception Baud Rate Setting in SNOOZE Mode High speed on chip UART reception baud rate in SNOOZE mode oscillator Baud rate 4800 bps Operating clock SDRmn Maximum Minimum fuck 15 9 acceptable value acceptable value 32 MHz 1 0 0 9 liu 105 2 2796 1 53 24 MHz 1 0 099 ficu 79 1 6096 2 18 1
182. ppo x AVrerp Vpp Notes 3 4 2 0 Analog input voltage ANI16 to ANI20 Note 1 Excludes quantization error 1 2 LSB AVREFP and Note 2 This value is indicated as a ratio FSR to the full scale value Note 3 When 0 lt AVREFP lt VDD the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVREFP VDD Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVREFP VDD Note 4 When lt lt VDD the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVREFP VDD Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVREFP VDD Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVREFP VDD 2tENESAS 50 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 3 When reference voltage ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to 20 internal reference voltage and temperature sensor output voltage TA 40 to 105 C 2 4 V lt EVppo EVDD1 lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage VDD Reference voltage Vss Parameter Resolution Conditions Overall error No
183. quare wave input Resonator connection fsuB 32 768 kHz Note 4 70 operation Square wave input Resonator connection fsuB 32 768 kHz Note 4 85 operation Square wave input Resonator connection 24 N SAS 14 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Note 1 Note 2 Note 3 Note 4 Note 5 Remark 1 Remark 2 Remark 3 Remark 4 Remark 5 Total current flowing into EVppo and EVDp1 including the input leakage current flowing when the level of the input pin is fixed to VDD EVppo and EVpp1 or Vss EVsso and EVss1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter D A converter comparator LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When 1 1 Ultra low power consumption oscillation However not including the current flowing into the 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed
184. quency 4 0 V lt EVppo lt 5 5 V 1000 Note 1 300 Note 1 300 Note 1 2 7 V lt Vb 4 0 V Cb 50 pF Rb 2 7 2 7 V EVppo 4 0 V 1000 Note 1 300 Note 1 300 Note 1 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 kQ 4 0 V lt EVppo lt 5 5 V 400 Note 1 300 Note 1 300 Note 1 2 7 V lt Vb lt 4 0 V Cb 100 pF Rb 2 8 kQ 2 7 V EVppo 4 0 V 400 Note 1 300 Note 1 300 Note 1 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 KQ sat 300 Note 1 300 Note 1 300 Note 1 1 6 V lt Vb lt 2 0 V Note 2 C 100 pF 5 5 Hold time when SCLr L 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V 100 pF Rb 2 8 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cp 100 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V x Vb lt 2 0 V Note 2 C 100 pF Rb 5 5 Hold time when SCLr 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 50 pF Rb 2 7 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V
185. r 2013 34 Supply Voltage Rise Time Old New Specifications in Supply Voltage Rise Time in page 1231 added Refer to page 66 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C 35 34 9 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics page 1231 New Old Refer to page 67 in Technical Update Exhibit Chapter 34 ELECTRICAL SPECIFICATIONS Specifications in Data Memory STOP Mode Low Supply Voltage Data Retention A D TA 40 to 85 C Characteristics in page 1231 extended 36 Chapter 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 Old New Specifications in Chapter 35 ELECTRICAL SPECIFICATIONS 40 to 105 C fixed Refer to pages 1 to 58 in Technical Update Exhibit Chapter 35 ELECTRICAL SPECIFICATIONS 40 to 105 c 2013 Renesas Electronics Corporation All rights reserved Page 37 of 50 132 NE SAS RENESAS TECHNICAL UPDATE TN RL A004C E 37 Incorrect descriptions of reset processing time standby mode release time revised Incorrect descriptions of reset processing time revised page 1049 Incorrect Figure 23 4 HALT Mode Release by Reset 1 2 Omitted 2 When high speed on chip oscillator clock is used as CPU clock Omitted Reset processing time when HALT mode or STOP mode is released Reset pro ing time 387 to 720 us When LVD is used 155 to 407 When LVD of Figure 23 4 HALT Mode
186. r DAPmn 1 and CKPmn 0 Use it with EVDDo gt Vb Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For ViH and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 24 N SAS 46 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Remark 1 Remark 2 Remark 3 Remark 4 CSI mode connection diagram during communication at different potential Master Vb Vb SCKp RL78 microcontroller Slp SO Users device SOp SI Rb Q Communication line SCKp SOp pull up resistance Communication line SCKp SOp load capacitance Vb V Communication line voltage p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 5101 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential 34 NC SAS 47 RL78 G14 CH
187. re Reset period oscillation stop Normal operation a Normal operation H high speed on chip oscillator clock Execution of Illegal Instruction Reset processing 41 to 69 Watchdog timer overflow Port pin except P130 Port pin P130 Page 43 of 50 RENESAS c 2013 Renesas Electronics Corporation All rights reserved Date October 2013 Correct Figure 24 2 Timing of Resetby RESET Input Wait for oscillation accuracy stabilization High speed on chip oscillator clock J Starting X1 oscillation is specified by software High speed system clock when X1 oscillation is selected Normal operation high speed on chip oscillator clock Reset period CPU status Normal operation RESET pin Reset processing time when an extemal reset is released Internal reset signal Port pin except P130 Port pin m ECC KE P130 met Release from the reset state is automatic in case of a reset due to a watchdog time overflow execution of an illegal instruction detection of a RAM parity error or detection of illegal memory access After reset processing program execution starts with the high speed on chip oscillator clock as the operating clock Figure 24 3 Timing of Reset Due to Watchdog Timer Overflow Execution of Illegal Instruction Detection of RAM Parity Error or Detection of Illegal Memory Access Wait for oscillation accuracy stabilization PEN High speed
188. rence voltage Low electric potential Comparator high speed mode window mode 0 24 reference voltage Operation stabilization wait time Internal reference voltage 2 4 V lt VoD lt 5 5 V HS high speed main mode Note Note Not usable in LS low speed main mode LV low voltage main mode sub clock operation or STOP mode 34 6 5 POR circuit characteristics TA 40 to 85 Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Note 1 Minimum pulse width Note 2 Note 1 However when the operating voltage falls while the LVD is off enter STOP mode or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 34 4 AC Characteristics Note 2 Minimum time required for a POR reset when exceeds below VPpR This is also the minimum time required for POR reset from when Vpp exceeds below 0 7 V to when Vpp exceeds VPoR while STOP mode is entered or the system clock is stopped through setting bit O HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC TPw Supply voltage VDD VPOR 1 VPDR 0 7 V 9 24 N SAS 64 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 6 6 LVD circuit characteristics 1 LVD Detection Voltage of Re
189. rial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKCY2 tKL2 tKH2 SCKp tsik2 gil tksi2 Slp Input data SOp Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKcv2 a tKH2 res tKL2 SCKp tsik2 RN tKsi2 Sip Input data tKso2 SOp Output data Remark 1 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 0 1 3 to 5 14 Remark 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential Also communication at different potential cannot be performed during clock synchronous serial communication with the slave select function 24 N SAS 51 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 10 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode TA 40 to 85 1 8 V lt EVDD1 lt lt 5 5 V Vss EVsso EVss1 0 V 1 2 Parameter Conditions HS high speed main LS low speed main LV low voltage main mode mode mode MIN MAX MIN MAX MIN MAX SCLr clock fre
190. rmal input buffer and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page 2tENESAS 36 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Simplified 12C mode connection diagram during communication at same potential VDD Rb SDAr SDA RL78 microcontroller User s device SCLr Simplified I2C mode serial transfer timing during communication at same potential 1 fscL tLow tHIGH SCLr SDAr tHD DAT 50 DAT Remark 1 Rb Q Communication line SDAr pull up resistance Ce F Communication line SDAr SCLr load capacitance Remark 2 r IIC number 00 01 10 11 20 21 30 31 g PIM number g 0 1 3 to 5 14 h POM number h 0 1 3 to 5 7 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 24 N SAS 37 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode TA 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V
191. s specified by software High speed system NE H clock fmx EE li Normal operation high speed on chip oscillator clock Note 3 Starting oscillation is specifi ied by software Normal operation i high speed on chip oscillator clock Note Reset period oscillation stops 4 Operation stops CPU Operation stops Internal reset signal K Note 4 Reset processing time when an external reset is released N Voltage stabilization wait time 0 99 ms TYP 2 30 ms max i processing time when an external reset is released Voltage stabilization wait time 0 99 ms TYP 2 30 ms max E Note 4 Before the MCU starts normal operation it waits until the voltage becomes stable voltage stabilization wait time after the voltage reaches VPOR 1 51 V TYP and also requires the following reset processing time when an external reset is released after the RESET signal is set to 1 high level Reset processing time when an external reset is released 0 672 ms TYP 0 832 ms max When LVD is used 0 399 ms TYP 0 519 ms max When LVD is off Note 5 The second and subsequent reset processing time after POR is released 0 531 ms TYP 0 675 ms max When LVD is used 0 259 ms TYP 0 362 ms max When LVD is off Go on to the next page 4 RENESAS TECHNICAL UPDATE TN RL A004C E
192. s value is the theoretical value of the relative difference between the transmission and reception sides Note 6 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the TxDq by using port input mode register PIMg and port output mode register g POMg For and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the next page 34 NC SAS 35 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 UART mode connection diagram during communication at different potential TxDq RL78 microcontroller User s device RxDq UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remark 1 Rb Q Communication line TxDq pull up resistance Communication line TxDq load capacitance Vb V Communication line voltage Remark 2 q UART number q 0 to 3 g PIM and POM number g 0 1 5 14 Remark 3
193. set Mode and Interrupt Mode TA 40 to 85 C VPDR lt lt 5 5 V Vss 0 V Parameter Conditions lt Detection Supply voltage level Vivbo Power supply rise time voltage Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time VLVD10 Power supply rise time Power supply fall time VLVD11 Power supply rise time Power supply fall time VLVD12 Power supply rise time Power supply fall time VLVD13 Power supply rise time lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Power supply fall time Minimum pulse width Detection delay time 24 N SAS 65 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 LVD Detection Voltage of Interrupt amp Reset Mode TA 40 to 85 VPDR lt lt 5 5 V Vss 0 V Parameter Interrupt and reset mode VLVDAO Conditio
194. t 5 5 V 1 6 V lt EVDD0 lt 1 8 V Interrupt input high level INTPO 1 6V lt Vpp lt 5 5V width low level width INTP1 to INTP11 1 6 V lt 5 5 V Key interrupt input low level KRO to KR7 1 8 V lt EVppo 5 5 V width 1 6 V EVppo 1 8 V RESET low level width 24 N SAS 21 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Minimum Instruction Execution Time during Main System Clock Operation Tcv vs HS high speed main mode When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Cycle time Tcv us Supply voltage Vpp V 34 NC SAS 22 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 Cycle time Tcv us Cycle time Tcv us Tcv vs VoD LS low speed main mode Supply voltage Vpop V Tcv vs Vpb LV low voltage main mode 10 0 25 0 1 0 01 0 10 i20 30 40 50 60 1 61 8 5 5 Supply voltage Vpp V When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected
195. t 5 5 V 62 5 250 500 2 7 V lt EVbppo lt 5 5 V 83 3 250 500 SCKp high low level 4 0 V lt lt 5 5 V tkcv1 2 7 tkcy1 2 50 tkcy1 2 50 width 2 7 V lt EVbppo lt 5 5 V tkcy1 2 10 tkcv1 2 50 tkcv1 2 50 81 setup time to SCKp1 4 0 V lt lt 5 5 V 23 110 110 Ned 2 7 V lt lt 5 5 V 33 110 410 SIp hold time from 2 7 V lt EVopo lt 5 5 V 10 10 10 SCKp1 Note 2 Delay time from SCKp to C 20 pF Note 4 SOp output Note 3 Note 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Note 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remark 1 This value is valid only when CSIOO s peripheral redirect function is not used Remark 2 p CSI number p 00 m Unit number m 0 n Chan
196. t EVppo lt 2 7 V MAX 1 3 Mbps The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 32 MHz 2 7 V lt lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the TxDq by using port input mode register PIMg and port output mode register POMg For and ViL see the DC characteristics with TTL input buffer selected Vb V Communication line voltage UART number 4 0 to 3 9 PIM and POM number 0 1 5 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 UART2 cannot communicate at different potential when bit 1 PIORO1 of peripheral I O redirection register 0 PIORO is 1 24 N SAS 33 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 2 Parameter Conditions HS high speed main mode MIN MAX Transfer rate transmission 4 0 V lt EVppo lt 5 5 V 2 7 lt lt 4 0 Theoretical value of the maximum transf
197. t becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and SCKp pin and the N ch open drain output tolerance When 30 to 52 pin products EVpp tolerance when 64 to 100 products mode for the SOp pin by using port input mode register PIMg and port output mode register POMg For Vin and ViL see the DC characteristics with TTL input buffer selected CSI mode connection diagram during communication at different potential Slave Vb SCKp RL78 microcontroller Slp SO Users device SOp SI Remark 1 Rb Q Communication line SOp pull up resistance Ce F Communication line SOp load capacitance Vb V Communication line voltage Remark 2 p CSI number p 00 01 10 20 30 31 m Unit number m 0 1 n Channel number n 0 to 3 9 PIM and POM number g 7 0 1 3 to 5 14 Remark 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 Remark 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential Also communication at different potential cannot be performed during clock synchronous serial communication with the slave select function 24 N SAS 43 RL78 G14 CHAPTER 35 ELECTRICAL SPEC
198. tage main mode MIN MAX MIN MAX MIN MAX 2 3 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 C 30 pF Rb 5 5 SIp hold time from SCKp1 Note 1 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 Cb 30 pF Rb 5 5 Delay time from SCKp to SOp output Note 1 Note 1 Note 2 Caution 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vb lt 4 0 V 30 pF 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 1 8 V lt lt 3 3 V 1 6 V lt lt 2 0 V Note 2 C 30 pF Rb 5 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 Use it with EVDDo gt Vb Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 30 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For ViH and ViL see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page 24 N SAS 4
199. te 1 10 bit resolution 2 4 V lt Voo lt 5 5 V Conversion time 10 bit resolution Target pin ANIO to ANI14 ANI16 to ANI20 3 6 V lt Voo lt 5 5 V 2 7 V lt Voo lt 5 5 V 2 4 V lt Voo lt 5 5 V 10 bit resolution Target pin internal reference voltage and temperature sensor output voltage HS high speed main mode 3 6 V lt Voo lt 5 5 V 2 7 V lt Voo lt 5 5 V 2 4 V lt Voo lt 5 5 V Zero scale error Notes 1 2 10 bit resolution 2 4 V lt lt 5 5 V Full scale error Notes 1 2 10 bit resolution 2 4 V lt Voo lt 5 5 V Integral linearity error Note 1 10 bit resolution 2 4 V lt Voo lt 5 5 V Differential linearity error Note 1 10 bit resolution 2 4 V lt Voo lt 5 5 V Analog input voltage Note 1 Note 2 Note 3 ANIO to ANI14 VDD ANI16 to ANI20 Internal reference voltage 2 4 V lt lt 5 5 V HS high speed main mode Note 3 Temperature sensor output voltage 2 4 V lt Voo lt 5 5 V HS high speed main mode Excludes quantization error 1 2 LSB This value is indicated as a ratio FSR to the full scale value Refer to 35 6 2 Temperature sensor characteristics internal reference voltage characteristic VrMPs25 Note 3 24 N SAS 51 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS 40 to 105
200. the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2tENESAS 3 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 2 Oscillator Characteristics 34 2 1 X1 XT1 characteristics 40 to 85 1 6 V lt Voo lt 5 5 V Vss 0 V Resonator Resonator Conditions X1 clock oscillation frequency fx Note Ceramic resonator 2 7 V lt VoD lt 5 5 crystal resonator 2 4 V lt VDD lt 2 7 V 1 8 V lt VoD lt 2 4 V 1 6 V lt Vpp lt 1 8 V XT1 clock oscillation frequency Note Crystal resonator Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to
201. timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 3 24 N SAS 20 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 TA 40 to 85 C 1 6 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V 2 2 Conditions Timer RD input high level tTDIH TRDIOAO TRDIOA1 TRDIOBO TRDIOB1 width low level width tTDIL TRDIOCO TRDIOC1 TRDIODO TRDIOD1 Timer RD forced cutoff signal trbsiL P130 INTPO 2MHz lt lt 32 MHz 1 input low level width lt 2 MHz 1 fcLK 1 Timer RG input high level TRGIOA TRGIOB 2 5 fCLK width low level width TOOO to TOO3 HS high speed main mode 4 0 V lt EVppo lt 5 5 V TO10 to T013 2 7 V lt lt 4 0 V TRJIOO TRJOO TRDIOAO TRDIOAM TRDIOBO TRDIOB1 1 6 V x EVopo 1 8 V TRDIOCO TRDIOC1 LS low speed main mode 1 8 V lt EVppo 5 5 V TRDIODO TRDIOD1 1 6 V lt EVppo lt 1 8 V TRGIOA TRGIOB output frequency PCLBUZO PCLBUZ1 output HS high speed main mode 4 0 V x EVppo lt 5 5 V frequency 2 7 V lt EVbpo lt 4 0 V 1 8 V lt EVbpo 2 7 V LV low voltage mode 1 6 V lt 0 lt 5 5 V N 1 8 V lt lt 2 7 V 1 6 V lt lt 1 8 V LS low speed main mode 1 8 V lt EVDD0 lt 5 5 V 1 6 V lt EVDD0 lt 1 8 V LV low voltage main mode 1 8 V lt EVppo l
202. tion the converted values of other channels may also be affected When internal reference voltage 1 45 V is selected reference voltage source for the side of the A D converter do not input internal reference voltage or higher voltage to a pin selected by the ADS register However it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage Caution The internal reference voltage 1 45 V can be selected only in HS high speed main mode c 2013 Renesas Electronics Corporation All rights reserved Page 25 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 14 Cautions when using SNOOZE mode in the serial array unit added Explanations of SNOOZE mode related to CSI added pages 786 788 Incorrect Omitted Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes be sure to set the STm0 bit to 1 and clear the SEm0 bit to stop the operation Correct Omitted Caution Before transiting to SNOOZE mode and after the receive operation is completed in SNOOZE mode set the STm0 bit to 1 clear the SEm0 bit to 0 and stop the operation And after the receive operation is completed also clear the SWCm bit to 0 SNOOZE mode release Explanations of SNOOZE mode related to the UART added pages 847 848 850 Incorrect Omitted Caution Before switching to the SNOOZE mode or after receptio
203. upply voltage rising slope characteristics TA 40 to 105 Vss 0 V Ponerse nso e Caution sure to keep the internal reset state by the LVD circuit or an external reset until reaches the operating voltage range shown in 35 4 AC Characteristics NESAS 56 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS 40 to 105 35 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics TA 40 to 105 Vss 0V Parameter Symbol Conditions Unt M retention suppl pply VDDDR 1 44 Note voltage Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected STOP mode a Operation mode Data retention mode VDD STOP instruction execution Standby release signal interrupt request 35 8 Flash Memory Programming Characteristics Ta 40 to 105 2 4 V lt VoD lt 5 5 V Vss 0 V Parameter Conditions System clock frequency 2 4 V lt VoD lt 5 5 V Number of code flash rewrites Retained for 20 years 85 Notes 1 2 3 Number of data flash rewrites Retained for 1 year 25 1 000 000 Notes 23 Retained for 5 years TA 85 100 000 Retained for 20 years 85
204. upt Mask Flag Register Priority Specification Flag Register Timer RG TRGSR TRGIER TRGIF IF2H TRGMK MK2H TRGPRO PRO2H TRGPR1 PR12H Figure 9 31 Timer RG Interrupt Block Diagram IMFA bit Timer RG interrupt IMIEA bit request IMFB bit IMIEB bit UDF bit UDIE bit OVF bit OVIE bit IMFA IMFB UDF OVF Bits in the TRGSR register IMIEA IMIEB UDIE OVIE Bits in the TRGIER register Since the interrupt source timer RG interrupt is generated by a combination of multiple interrupt request sources for timer RG the following differences from other maskable interrupts excluding the timer RD interrupt apply e When a bit in the TRGSR register is 1 and the corresponding bit in the TRGIER register is 1 interrupt enabled the TRGIF bit in the IF2H register is set to 1 interrupt requested f multiple bits in the TRGIER register are set to 1 use the TRGSR register to determine the source of the interrupt request e Since the bits in the TRGSR register are not automatically set to 0 even if the interrupt is acknowledged set the corresponding bit to 0 in the interrupt routine e While multiple bits in the TRGIER register are set to 1 if the first request source is met and the TRGIF bit is set to 1 and then the next request source is met the TRGIF bit is cleared to 0 when the interrupt is acknowledged However if the previously met request source is cleared the
205. value for current to operate the subsystem clock in STOP mode refer to that in HALT mode fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency fHoco High speed on chip oscillator clock frequency 64 MHz max fiH High speed on chip oscillator clock frequency 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 34 NC SAS 13 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V Parameter Operating mode HS high speed main mode Note 5 Conditions fuoco 64 MHz 32 MHz Note 3 Basic operation Voo 5 0 V 3 0 V fuoco 32 MHz 32 MHz Note 3 Basic operation Voo 5 0 V 3 0 V HS high speed main mode Note 5 fuoco 64 MHz 32 MHz Note 3 Normal operation 5 0 V 3 0 V fuoco 32 MHz 32 MHz Note 3 Normal operation 5 0 V Voo 3 0 V fuoco 48 MHz 24 MHz Note 3 Normal operation Voo 5 0 V Voo 3 0 V fuoco 24 MHz fiH 24 MHz Note 3 Normal operation Voo 5 0 V Voo 3
206. ve Transmission of slave select input function CSIOO SCKOO 5100 RL78 microcontroller User s device 000 100 Remark 1 p CSI number 00 01 10 11 20 21 30 31 Remark 2 m Unit number n Channel number mn 00 to 03 10 to 13 234 N SAS 33 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKCY1 2 tKL1 2 tKH1 2 SCKp tSIK1 2 tksi1 2 51 Input data lt tKSO1 2 SOp Output data tssik tkssi SSI00 100 only CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tKCY1 2 SCKp 51 SOp tkssi 55100 5100 only 5 is Remark 1 p CSI number p 00 01 10 11 20 21 30 31 Remark 2 m Unit number n Channel number mn 00 to 03 10 to 13 24 N SAS 34 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 5 During communication at same potential simplified 12C mode 40 to 85 1 6 V lt EVDD0 EVDD1 lt VDD lt 5 5 V Vss EVsso 551 0 V Parameter SCLr clock frequency Conditions 2 7 V EVppo lt 5 5 V Cb 50 pF Rb 2 7 kO HS high speed main mode LS low speed main mode LV low
207. writing results are as follows If the read value is 1 writing 0 to the bit sets it to 0 e f the read value is 0 the bit remains unchanged even if 0 is written to it Even if the bit is changed from 0 to 1 after reading and then 0 is written to it it remains 1 e Writing 1 has no effect c 2013 Renesas Electronics Corporation All rights reserved Page 6 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 Correct Notes 1 The value after reset is undefined when FRQSELA 1 in the user option byte 000C2H 010C2H and TRDOEN 0 in the PER1 register If it is necessary to read the initial value set fcuk to and TRDOEN 1 before reading Omitted 4 The writing results are as follows e Writing 1 has no effect e f the read value is 0 the bit remains unchanged even if 0 is written to it Even if the bit is changed from 0 to 1 after reading and then 0 is written to it it remains 1 e If the read value is 1 writing O to the bit sets it to 0 When status flags of interrupt sources applicable status flags of timer RD are set to 0 and their interrupts are disabled in timer RD interrupt enable register i TRDIERI use either one of the following methods a to c a Set OOH all interrupts disabled to timer RD interrupt enable register i TRDIERI and write 0 to applicable status flags When there are bits set to 1 interrupt enabled in timer RD interrupt enable register TRDIE
208. x lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until reaches the operating voltage range shown in 34 4 AC Characteristics 24 N SAS 66 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 34 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics 40 to 85 Vss OV Parameter Symbol Unt retention suppl pply VDDDR 1 46 Note voltage Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected STOP mode a Operation mode Data retention mode VDD STOP instruction execution Standby release signal interrupt request 34 8 Flash Memory Programming Characteristics Ta 40 to 85 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions System clock frequency 1 8 V lt VoD lt 5 5 V Number of code flash rewrites Retained for 20 years 85 Notes 1 2 3 Number of data flash rewrites Retained for 1 year 25 1 000 000 Notes 23 Retained for 5 years TA 85 100 000 Retained for 20 years 85 10 000 Note 1 1 erase
209. x Vb lt 2 0 V Note 2 C 100 pF 5 5 24 N SAS 52 RL78 G14 CHAPTER 34 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 10 Communication at different potential 1 8 V 2 5 V 3 V simplified I2C mode TA 40 to 85 1 8 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVss1 0 V Parameter Data setup time reception tsu DAT Conditions 4 0 V x EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 50 pF Rb 2 7 HS high speed mode LS low speed main mode LV low voltage main mode MIN 1 135 Note 3 MAX MIN 1 190 Note 3 MAX MIN 190 Note 3 MAX 2 2 2 7 V EVDppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 50 pF Rb 2 7 fuck 135 Note 3 1 190 Note 3 fMck 190 Note 3 4 0 V x EVppo lt 5 5 V 2 7 V lt Vb x 4 0 V Cb 100 pF Rb 2 8 KQ fuck 190 Note 3 1 190 Note 3 fuck 190 Note 3 2 7 V EVppo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 100 pF Rb 2 7 KQ 1 190 Note 3 1 190 Note 3 1 190 Note 3 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note 2 Co 100 pF Rb 5 5 1 fuck 190 Note 3 1 190 Note 3 1 190 Note 3 Data hold time transmission Note 1 Note 2 Note 3 Caution tHD DAT
210. xt generated request source e When status flags of interrupt sources applicable status flags of the timer RD are set to 0 and their interrupts are disabled in timer RD interrupt enable register i TRDIERI use either one of the following methods to c Set 00H all interrupts disabled to timer RD interrupt enable register i TRDIERI and write 0 to applicable status flags b When there are bits set to 1 enabled in timer RD interrupt enable register i TRDIERI and status flags of interrupt sources related to their bits are 0 write to applicable status flags Example To clear the IMFB bit to 0 when bits IMIEA and OVIE are set to 1 interrupt enabled and the IMIEB bit is set to 0 interrupt disabled Timer RD Interrupt Enable Register i TRDIERI Interrupt enabled TRDIERi a EB MEA Interrupt disabled Timer RD Status Register i TRDSRi Bit to be cleared to 0 UDF OVF IMFD IMFB IMFA As status flags OVF IMFA corresponding to the bit which is set to 1 interrupt enabled are 0 write 0 to the IMFB bit Go on to the next page c 2013 Renesas Electronics Corporation All rights reserved Page 9 of 50 stENESAS RENESAS TECHNICAL UPDATE TN RL A004C E Date October 2013 c When there are bits set to 1 interrupt enabled in timer RD interrupt enable register i TRDIERI and status flags of interrupt sources related to their bits are 1 write O to
211. y 32 MHz max fsuB Subsystem clock frequency XT1 clock oscillation frequency Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 34 NC SAS 13 RL78 G14 CHAPTER 35 ELECTRICAL SPECIFICATIONS TA 40 to 105 2 Flash ROM 96 to 256 KB of 30 to 100 pin products TA 40 to 105 2 4 V lt EVDD1 lt VDD lt 5 5 V Vss EVsso EVssi 0 V Parameter Operating mode HS high speed main mode Note 5 Conditions fuoco 64 MHz 32 MHz Note 3 Basic operation Voo 5 0 V 3 0 V fuoco 32 MHz 32 MHz Note 3 Basic operation Voo 5 0 V 3 0 V HS high speed main mode Note 5 fuoco 64 MHz 32 MHz Note 3 Normal operation 5 0 3 0 V fuoco 32 MHz 32 MHz Note 3 Normal operation 5 0 V 3 0 V fuoco 48 MHz 24 MHz Note 3 Normal operation Voo 5 0 V Voo 3 0 V fuoco 24 MHz fiH 24 MHz Note 3 Normal operation Voo 5 0 V Voo 3 0 V fuoco 16 MHz 16 MHz Note 3 Normal operation Voo 5 0 V Voo 3 0 V HS high speed main mode Note 5 fux 20 MHz Note 2 Voo 5 0 V Normal operation Square wave input Resonator connection fmx 20 MHz Note 2 Voo 3 0 V Normal operation Squar

Correction for Incorrect Description Notice RL78/G14 Descriptions in

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