Errata Sheet NG for P11
Contents
1. ee i Input Signal R22 2 KE L eee Internal Signal terratic interval tinterval PAD_X 001 Fig 3 Figure 5 Rising Edge Detection Approach If the time between the rising signal edge and the rising edge caused by a spike terratic 15 less than the ISR service time a workaround would be to clear the interrupt request IR flag before the return from interrupt is done The clearing of the IR flag will avoid a further erratic interrupt The preferred solution for interrupt handling is to use the rising edge detection 4 3 Rising Edge and Falling Edge Detection Approach The rising edge detection workaround works also if both edges are used as trigger for interrupt and the following conditions are valid t interval r interval f erratic interval SS and erratic interval Internal Signal terratic interval gt 4 p tinterval r Figure 6 Rising Edge and Falling Edge Detection Approach tinterval f PAD X 001 Fig 4 Errata Sheet 34 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description PARITY X 001 PMTSR Register Initialization The PMTSR register content after start up is 0100 meaning the parity logic for SBRAM is not in standard mode of operation Workaround If parity will be used as Memory Control mechanism for SBRAM it must be enabled by initializing the PMT2. finem 16 32 Bit Architecture XC2200N Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family Value Line Errata Sheet V1 7 2013 06 Microcontrollers Edition 2013 06 Published by Infineon Technologies AG 81726 Munich Germany 2013 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the
3. Errata Sheet 30 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Mt li 1 Input I I Signal l l 0 3 Re eee a T eee 0 1 Voor DE t SS cs emm mmm L 1 Internal l 1 1 Signal 1 Unexpected Edges 4 PAD X 001Fig 1 Figure 3 Example for a Slow Input Signal The first rising edge in Figure 3 of the internal signal is always valid The edges which are marked with Unexpected Edges must be ignored Measurements have shown that a spike can be generated under the following conditions Table11 Conditions for Additional Edges in the Input Signal Parameter Symbol Value Unit Note Digital supply voltage Vppp 45to5 5 V Upper Voltage Range Junction Temperature 7 fullrange C System frequency Jays all MHz Rising Slope f 21 Us The reaction to this spike generation strongly depends on the application hardware software internal and external noise Although it is not possible to define how the application will react in all cases it is possible to categorize how applications are typically affected as shown below Errata Sheet 31 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Applications which can be affected by a spike CCU6
4. CAPCOM2 and GPT inputs Port inputs e Interrupts input Applications which should not be affected by a spike due to faster rising slope t which is necessary for the application due the interface protocol or due multiple sampling of the hardware USIC CAN Others Workaround for Input Capture Conditions 1 Workaround for all Affected Applications Use rising edges with faster rising slope f than defined in Table 11 2 Workaround for CCU6 CAPCOM2 and GPT Inputs No generic solution is available for these applications Add or switch to a software solution For example the software could check whether the measured signal values are in the expected range 3 Workaround for Port Inputs 1 The captured time interval value should be checked whether it is in a reasonable range 2 The input pin should be read several times and a majority decision may be made to decide whether the edge was correct or erratic Only if 1 and 2 indicate that the edge was reliable the captured value should be used for further calculations Otherwise a substituted extrapolated value might be used Errata Sheet 32 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description 4 Workaround for Interrupt Inputs 4 1 Falling Edge Detection Approach 1 Measure the time interval since the last interrupt shown as finteryai in Figure 4 below and check that it is in the expected ti
5. MultiCAN AI H008 Effect of CANDIS on SUSACK When a CAN node is disabled by setting bit NCR CANDIS 1g the node waits for the bus idle state and then sets bit NSR SUSACK 1p Errata Sheet 48 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description However SUSACK has no effect on applications as its original intention is to have an indication that the suspend mode of the node is reached during debugging MultiCAN 002 Double Synchronization of receive input The MultiCAN module has a double synchronization stage on the CAN receive inputs This double synchronization delays the receive data by 2 module clock cycles If the MultiCAN is operating at a low module clock frequency and high CAN baudrate this delay may become significant and has to be taken into account when calculating the overall physical delay on the CAN bus transceiver delay etc MultiCAN TC H003 Message may be discarded before transmission in STT mode If MOFCRn STT 1 Single Transmit Trial enabled bit TXRQ is cleared TXRQ 0 as soon as the message object has been selected for transmission and in case of error no retransmission takes places Therefore if the error occurs between the selection for transmission and the real start of frame transmission the message is actually never sent Workaround In case the transmission shall be guaranteed it is not suitable to use the STT mode In this case M
6. 53 USIC ALHOOT1 i2 nee ee eee nde ed Rr ees 53 5516 1 002 mnm Perm piia Gina Rupee 54 USIC ALBOO09 usu Pa Adie ee Rule ome wale 54 6 4 Documentation Updates 55 EBC DOO T esos etos rero ste de He eC REIR LER eed fl 55 RESET X D001 scsi thn ol eee oe Eos Pe he de e eg 55 USIC X D002 Ene EROR ee RE RR RUE SETS REOR 56 Errata Sheet 5 V1 7 2013 06 ut XC2200N Derivatives Infineon XC2000 Family Value Line History List Change Summary 1 History List Change Summary Table 1 History List Version Date Remark 1 0 30 09 2008 First Errata Sheet release 1 1 30 01 2009 1 2 10 03 2009 New Marking Step new Errata Sheet layout 1 3 08 06 2009 Errata No 01486AERRA new Marking Step AA 1 4 12 10 2009 Errata No 01545AERRA 1 5 23 09 2010 Errata No 01872AERRA 1 6 22 01 2013 Errata No 02442AERRA 1 7 18 06 2013 Errata No 02622 Removed 5 ES AA references from Marking Step Added ES AB AB Marking Step references DPRAM 002 is fixed in AB step 1 Errata changes to the previous Errata Sheet are marked in Chapter 5 Short Errata Description Trademarks 166 TriCore V and DAVE are trademarks of Infineon Technologies AG We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or mis
7. bit times can be Errata Sheet 47 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description shorter or longer than nominal bit time length due to the CAN resynchronization events Workaround None MultiCAN AI H007 Alert Interrupt Behavior in case of Bus Off The MultiCAN module shows the following behavior in case of a bus off status REC 0x1 TEC 0x1 BOFF INIT 0 60 0 1 EWRN BOFF INIT REC 0x0 TEC 0x0 ALERT INIT 0 60 REC 0x60 EWRN Figure 7 Alert Interrupt Behavior in case of Bus Off When the threshold for error warning EWRN is reached default value of Error Warning Level EWRN 0x60 then the EWRN interrupt is issued The bus off BOFF status is reached if TEC gt 255 according to CAN specification changing the MultiCAN module with REC and TEC to the same value 0x1 setting the INIT bit to 15 and issuing the BOFF interrupt The bus off recovery phase starts automatically Every time an idle time is seen REC is incremented If REC 0x60 a combined status EWRN BOFF is reached The corresponding interrupt can also be seen as a pre warning interrupt that the bus off recovery phase will be finished soon When the bus off recovery phase has finished 128 times idle time have been seen on the bus EWRN and BOFF are cleared the ALERT interrupt bit is set and the INIT bit is still set
8. case of core timer overflow underflow see Table 12 below read Timer high T2 if Timer high is not equal to Timer high temp read Timer low T3 After execution of this algorithm Timer high and Timer low represent a consistent time stamp of the concatenated timers The equivalent number of system clock cycles corresponding to two basic clock cycles is shown in the following Table 12 Errata Sheet 45 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Table 12 Equivalent Number of System Clock Cycles Required to Wait for Two Basic Clock Cycles Setting of BPS1 BPS1 01 54 00 54 11 BPS1 10 Required Number of 8 16 32 64 System Clocks Setting of BPS2 BPS2 01 BPS2 00 52 11 BPS2 10 Required Number of 4 8 16 32 System Clocks In case the required timer resolution can be achieved with different combinations of the Block Prescaler BPS1 BPS2 and the Individual Prescalers TxI the variant with the smallest value for the Block Prescaler may be chosen to minimize the waiting time E g in order to run T6 at fsys 512 select BPS2 00g T6I 1115 and insert 8 NOPs or other instructions to ensure the required waiting time before reading Timer high the second time INT X H002 Increased Latency for Hardware Traps When a condition for a HW trap occurs i e one of the bits in register TFR is set to 15 the next valid inst
9. source 5 DMPMITCLR PVCMI2 and SCU DMPMITCLR PVC1I2 4 Clear the PVC interrupt request flag by writing to 5 INTCLR PVCMI2 and SCU INTCLR PVC1I2 5 Clear the selected SCU request flag default is 5 0 11C IR RESET X H003 How to Trigger a PORST after an Internal Failure There is no internal User Reset that restores the complete device including the power system like a Power On Reset In some applications it is possible to connect ESR1 or ESR2 with the PORST pin and set the used ESR pin as Reset output With this a WDT or Software Reset can trigger a Power On Reset A detailed description is in the Application Note AP16103 Errata Sheet 51 V1 7 2013 06 2200 Derivatives Infineon i XC2000 Family Value Line Detailed Errata Description RTC X H003 Changing the RTC Configuration The count input clock frre for the Real Time Clock module RTC can be selected via bit field RTCCLKSEL in register RTCCLKCON Whenever the system clock is less than 4 times faster than the RTC count input clock fays lt 4 Asynchronous Mode must be selected bit RTCCM 1 in register RTCCLKCON To assure data consistency in the count registers T14 RTCL RTCH the RTC module must be temporarily switched off by setting bit MODEN Og in register KSCCFG before register RTCCLKCON is modified i e whenever changing the operating mode Synchronous Asynchronous Mode in bit or changing t
10. the values given in the Datasheet Independent of the SWD is the internal start up and operation protected by the PVC which monitor the core voltage StartUp X H001 EBC is not Disabled in Fast Startup Mode The pin assignment to the External Bus Controller EBC is disabled after start up in all modes that do not need the external bus explicitly i e in all modes but External Start The special Fast Startup Mode FSM which can be entered in conjunction with Standby Mode 1 is an exception from this rule If the user executed code in FSM and needs one pin or some pins which can be assigned to EBC the user code must first disable this assignment by setting EBCMODO EBCDIS 1g Afterwards all the EBC pins are available to the user software as GPIOs or with their alternate functions USIC AI H001 FIFO RAM Parity Error Handling A false RAM parity error may be signalled by the USIC module which may optionally lead to a trap request if enabled for the USIC RAM under the following conditions areceive FIFO buffer is configured for the USIC module and after the last power up less data elements than configured in bit field SIZE have been received in the FIFO buffer and the last data element is read from the receiver buffer output register OUTRL i e the buffer is empty after this read access Once the number of received data elements is greater than or equal to the receive buffer size configured in bit field STZE th
11. 08 Effect of CANDIS on SUSACK 48 MultiCAN TC H002 Double Synchronization of receive input 49 MultiCAN TC H003 Message may be discarded before 49 transmission in STT mode MultiCAN TC H004 Double remote request 49 OCDS X H003 Debug Interface Configuration by User 50 Software PVC X H001 PVC Threshold Level 2 51 RESET X H003 How to Trigger a PORST after an Internal 51 Failure Errata Sheet 18 V1 7 2013 06 om a XC2200N Derivatives Infineon XC2000 Family Value Line Short Errata Description Table 9 Application Hints cont d Hint Short Description Chg Pg RTC X H003 Changing the RTC Configuration 52 SCU X H009 WUCR TTSTAT can be set after a Power 52 Up SWD X H001 Application Influence on the SWD 52 StartUp X H001 EBC is not Disabled in Fast Startup Mode 53 USIC AI H001 FIFO RAM Parity Error Handling 53 USIC AI H002 Configuration of USIC Port Pins 54 USIC AI H003 PSR RXIDLE Cleared by Software 54 Errata Sheet 19 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Short Errata Description 5 5 Documentation Updates Table 10 gives a short description of the documentation updates Table 10 Documentation Updates Documentation Short Description Chg Pg Updates EBC X D001 Visibility of Internal Cycles on 55 External Address Bus RESET X D001 Reset Types of Trap Registers 55 USIC X D002 USIC1 Channel 0 Connection
12. 1 7 2013 06
13. 29 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description For some peripherals the debug mode setting in SUMCFG is erroneously set to normal mode upon any reset instead upon a debug reset only It remains in this state until SUMCFG is written by software or the debug system Some peripherals will not re enter the state defined for debug mode after an application reset GPT12 2 and MultiCAN will resume normal operation like after reset i e they are inactive until they are initialized by software In case the RTC has been running before entry into debug mode and it was configured in SUMCFG to stop in debug mode it will resume operation as before entry into debug mode instead All other peripheral modules i e ADC CCU6 and USIC will correctly re enter the state defined for debug mode after an application reset in debug mode For Flash and CPU bitfield SUMCFG must be configured to normal mode anyway since they are required for debugging Workaround None PAD X 001 Additional Edges in the Input Signal The digital input and l O pins are designed using Schmitt trigger input structures with hysteresis Even with this structure it is possible that very slow rising edges may generate spikes resulting in unexpected additional edges at the input signal The next picture Figure 3 is an example for a slow input signal with spikes shown on the slow rising input signal
14. 7 2013 06 2200 Derivativ 5 5 Infineon 2 2000 Family Value Line Errata Device Overview 4 4 Documentation Updates Table 5 shows the dependencies oft documentation updates in the derivatives Table 5 Errata Device Overview Documentation Updates XC22xxN Documentation Updates EBC X D001 RESET X D001 USIC X D002 gt lt x gt lt 5 AB x Errata Sheet 14 V1 7 2013 06 om XC2200N Derivatives Infineon 2000 Family Value Line Short Errata Description 5 Short Errata Description This chapter gives an overview on the deviations and application hints Changes to the last Errata Sheet are shown in the column Chg 5 1 Errata Removed in this errata sheet Table 6 shows a short description of the errata removed from this version if errata shete Table 6 Errata removed in this Errata Sheet Errata Short Description Chg 002 Incorrect ECC Error Indication Applicable only to EES AA for DPRAM ES AA Marking Steps EES AA ES AA reference removed from this ES SWD_X P001 Supply Watchdog Level Applicable only to EES AA VSWD min too Low ES AA Marking Steps EES AA ES AA reference removed from this ES 5 2 Functional Deviations Table 7 shows a short description of the functional deviations Table 7 Functional Deviations Functional Short Description Chg Pg Deviation BROM_T
15. C 006 Baud Rate Detection for CAN Bootstrap 21 Loader BSL_CAN_X 001 Quartz Crystal Settling Time after PORST 21 too Long for CAN Bootstrap Loader DPRAM X 002 Undefined Data read from Dual Port RAM 22 DPRAM Errata Sheet 15 V1 7 2013 06 Cinfineon XC2200N Derivatives 2000 Family Value Line Short Errata Description Table 7 Functional Deviations cont d Functional Short Description Chg Pg Deviation ESR_X 002 ESREXSTAT1 and ESREXSTAT2 Status 26 Bits can be Cleared after a Write Access ESR_X 004 Wrong Value of SCU_RSTCONx Registers 27 after ESRy Application Reset 12 X 002 Effects of GPT Module Microarchitecture 28 OCDS X 003 Peripheral Debug Mode Settings cleared 29 by Reset PAD X 001 Additional Edges in the Input Signal 30 PARITY X 001 PMTSR Register Initialization 35 RESET_X 003 P2 2 0 and P10 12 0 Switch to Input 35 SCU_X 012 Wake Up Timer RUNCON Command 35 StartUp X 003 Debug Interface Configuration from Flash 36 can Fail Upon Power On USIC_AI 004 Receive shifter baudrate limitation 37 USIC_AI 005 Only 7 data bits are generated in mode 37 when TBUF is loaded in SDA hold time USIC_AI 016 Transmit parameters are updated during 38 FIFO buffer bypass WDT_X 002 Clearing the Internal Flag which Stores 38 Preceding WDT Reset Request Errata Sheet 16 V1 7 2013 06 Cinfineon XC2200N Derivatives 2000 Family Value Line Short
16. DX0C and 56 Errata Sheet 20 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description 6 Detailed Errata Description This chapter provides a detailed description for each erratum If applicable a workaround is suggested 6 1 Functional Deviations BROM TC 006 Baud Rate Detection for CAN Bootstrap Loader In a specific corner case the baud rate detected during reception of the initialization frame for the CAN bootstrap loader may be incorrect The probability for this sporadic problem is relatively low and it decreases with decreasing CAN baud rate and increasing module clock frequency Workaround If communication fails the host should repeat the CAN bootstrap loader initialization procedure after a reset of the device BSL CAN X 001 Quartz Crystal Settling Time after PORST too Long for CAN Bootstrap Loader The startup configuration of the CAN bootstrap loader when called immediately after PORST limits the settling time of the external oscillation to 0 5 ms For typical quartz crystal this settling time is too short The CAN bootstrap loader generates a time out and goes into Startup Error State Workaround For low performance CAN applications a ceramic resonator with settling time less than 0 5 ms can be used An alternative is the Internal Start from on chip Flash memory as startup mode after PORST Then switch the system clock to external sou
17. Errata Description 5 3 Deviations from Electrical and Timing Specification Table 8 shows a short description of the electrical and timing deviations from the specification Table 8 Deviations from Electrical and Timing Specification AC DC ADC Short Description Chg Pg Deviation FLASH_X P001 Test Condition for Flash parameter NER in 41 Data Sheets SWD X P002 Supply Watchdog SWD Supervision 41 Level in Data Sheet Errata Sheet 17 V1 7 2013 06 2200 Derivatives 2000 Family Value Line Cinfineon Short Errata Description 5 4 Application Hints Table 9 shows a short description of the application hints Table 9 Application Hints Hint Short Description Chg Pg ADC_AI H002 Minimizing Power Consumption of an 42 ADC Module 12 001 Enabling or Disabling Single Event 42 Operation CC6 X H001 Modifications of Bit MODEN in Register 44 CCU6x KSCFG ECC X H001 ECC Error Indication Permanently Set 44 GPT12 001 Modification of Block Prescalers BPS1 44 and BPS2 GPT12E_X H002 Reading of Concatenated Timers 45 INT_X H002 Increased Latency for Hardware Traps 46 INT_X H004 SCU Interrupts Enabled After Reset 47 MultiCAN_AI H005 TxD Pulse upon short disable request 47 MultiCAN_AI H006 stamp influenced by 47 resynchronization MultiCAN AI H007 Alert Interrupt Behavior in case of Bus 48 Off MultiCAN 0
18. OFCRn STT shall be O MultiCAN TC H004 Double remote request Assume the following scenario A first remote frame dedicated to a message object has been received It performs a transmit setup is set with clearing NEWDAT MultiCAN starts to send the receiver message object data frame but loses arbitration against a second remote request received by the same message object as the first one NEWDAT will be set Errata Sheet 49 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description When the appropriate message object data frame triggered by the first remote frame wins the arbitration it will be sent out and NEWDAT is not reset This leads to an additional data frame that will be sent by this message object clearing NEWDAT There will however not be more data frames than there are corresponding remote requests remote remote CAN Bus request request data data loss of arbitration MultiCAN X Uo clear clear set clear NEWDAT NEWDAT NEWDAT by HW by HW by HW Figure8 Loss of Arbitration OCDS X H003 Debug Interface Configuration by User Software If the debug interface must be re configured the sequence of actions to follow is activate internal test logic reset by installing 5 0 DBGPRR TRSTGT 0 disable debug interface by installing 5 DBGPRR DBGEN install desired d
19. SR register with 8000 RESET X 003 P2 2 0 and P10 12 0 Switch to Input During the execution of an Application Reset and Debug Reset the pins P2 2 0 and P10 12 0 are intermediately switched to input These pins return to their previous mode approximately 35 system clock cycles after the application reset counter has expired approx 0 6 with default reset delay at 80 MHz If such a pin is used as output make sure that this short interruption does not lead to critical system conditions Workaround External pull devices can be added to have a defined level on these pins during Application and Debug Reset SCU X 012 Wake Up Timer RUNCON Command The Wake Up Timer can be started and stopped by the WUCR RUNCON bit field Under the precondition that the Wake Up Timer is configured to stop when reaching zero WUCR ASP 1g and if two Wake Up Timer commands are executed successively e g start is directly followed by stop then the second command will be ignored and will not change the state of the Wake Up Timer Errata Sheet 35 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Workaround After executing the first command wait at least 4 Wake Up Timer cycles before writing again to the WUCR RUNCON bit field and requesting the second command StartUp X 003 Debug Interface Configuration from Flash can Fail Upon Power On This erratum only a
20. This provides an erased error free flash read during start up without installed flash Errata Sheet 36 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description redundancy of DBGPRR register value which allows start up from internal external memory and JTAG position A 2 fthese start up configurations are used during development a device that does not start up in the desired debug configuration should be replaced by another device 3 Alternatively select a debug interface not from Flash data but directly using configuration pins refer to the User s Manual With this it is not possible to start from external memory nor is JTAG position A available USIC AI 004 Receive shifter baudrate limitation If the frame length of SCTRH FLE does not match the frame length of the master then the baudrate of the SSC slave receiver is limited to f 2 instead of Workaround None USIC AI 005 Only 7 data bits are generated mode when TBUF is loaded in SDA hold time When the delay time counter is used to delay the data line SDA HDEL gt 0 and the empty transmit buffer TBUF was loaded between the end of the acknowledge bit and the expiration of programmed delay time HDEL only 7 data bits are transmitted With setting HDEL 0 the delay time will be type 4 x 1 delay approximately 60ns 80MHz Workaround Do not use the delay time counte
21. Up ER ie 42 12 X H001 ie daua 42 Errata Sheet 4 V1 7 2013 06 XC2200N Derivatives Infineon XC2000 Family Value Line CCE X MOOT pta e td whee ates Rude Peete etin 44 001 meretes ELE dp ERU RP eke heed 44 GPT12 ies oz o eo ceo E 44 GPT12bE 1002 ave SE Rc da rta Rec d E 45 INT 2 o ss Pc teak ae RR Em abr RO iere e cba 46 INT X HO04A eM Erg 47 MultiCAN 005 47 MultiCAN AI H006 ssssssssseee II 47 MultiCAN 007 48 MultiCAN 008 48 MultiCAN TC H002 zuo pe m y EE E EIE ERR e thue 49 sm m ER km ER han 49 MultiCAN 49 OGDS Ch003 e bce eh duri ete een Reo Kens ecol es 50 PVG SX MOOT Eoi Ene 51 RESET 51 RTE erdt n Rede ber ere 52 SCU 009 52 SWD XHOO01 Gerd tree i 52 StartUp X H001 2 i e cee ee hee e kem ener ee
22. dified during operation of the GPTx block disable related interrupts before modification of BPSx and afterwards clear the corresponding service request flags and re initialize those registers T2 T4 in block GPT1 and T5 T6 CAPREL in block GPT2 that might be affected by an unintended count capture reload event GPT12bE X H002 Reading of Concatenated Timers For measuring longer time periods a core timer T3 or T6 may be concatenated with an auxiliary timer T2 T4 or T5 of the same timer block In this case the core timer contains the low part and the auxiliary timer contains the high part of the extended timer value When reading the low and high parts of concatenated timers care must be taken to obtain consistent values in particular after a timer overflow underflow e g one part may already have considered an overflow while the other has not This is a general issue when reading multi word results with consecutive instructions and not necessarily unique to the GPT module microarchitecture The following algorithm may be used to read concatenated GPT timers represented by Timer high for auxiliary timer here T2 and Timer low for core timer here T3 In this example the high part is read twice and reading of the low part is repeated if two different values were read for the high part read Timer high temp T2 read Timer low T3 e wait two basic clock cycles to allow increment decrement of auxiliary timer in
23. e effect described above can no longer occur To avoid false parity errors it is recommended to initialize the USIC RAM before using the receive buffer FIFO This can be achieved by configuring a 64 entry transmit FIFO and writing 64 times the value 0 0 to the FIFO input register INOO to fill the whole FIFO RAM with OxO Errata Sheet 53 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description USIC ALH002 Configuration of USIC Port Pins Setting up alternate output functions of USIC port pins through registers before enabling the USIC protocol CCR MODE 0001 0010p 0011 or 0100 might lead to unintended spikes on these port pins To avoid the unintended spikes either of the following two sequences can be used to enable the protocol Sequence 1 Write the initial output value to the port pin through Enable the output driver for the general purpose output through Pn IOCRx Enable USIC protocol through CCR MODE Select the USIC alternate output function through IOCRx Sequence 2 Enable USIC protocol through CCR MODE Enable the output driver for the USIC alternate output function through Pn IOCRx Similarly after the protocol is established switching off the USIC channel by reseting CCR MODE directly might cause undesired transitions on the output pin The following sequence is recommended Write the passive outp
24. ebug interface configuration in 5 DBGPRR 11 0 activate pull devices if internal will be used by installing Px IOCRy accordingly 5 enable debug interface by installing 5 DBGPRR DBGEN 1 6 release internal test logic reset by installing 5 0 DBGPRR TRSTGT 1 Am These steps must be performed as separate sequential write operations Errata Sheet 50 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description PVC X H001 PVC Threshold Level 2 The Power Validation Circuits PVCM PVC1 compare the supply voltage of the respective domain DMP M 1 with programmable levels LEV1V and LEV2V in register 500 PVCMCONO or 5 0 PVC1CONO The default value of LEV1V is used to generate a reset request in the case of low core voltage LEV2V can generate an interrupt request at a higher voltage to be used as a warning Due to variations of the tolerance of both the Embedded Voltage Regulators EVR and the PVC levels this interrupt can be triggered inadvertently even though the core voltage is within the normal range It is therefore recommended not to use this warning level LEV2V can be disabled by executing the following sequence 1 Disable the PVC level threshold 2 interrupt request SCU PVCMCONO L21NTEN and SCU PVC1CONO L2INTEN 2 Disable the PVC interrupt request flag source 5 0 INTDIS PVCMI2 and SCU INTDIS PVC1I2 3 Clearthe PVC interrupt request flag
25. elow Workaround When T3 counts up and value x reload value is read from T3 value x should be replaced with the reload value for further calculations When counts down and value x gt reload value is read from value x should be replaced with the reload value for further calculations Alternatively if the intention is to identify the overflow underflow of T3 the T3 interrupt request may be used 2 Reload of from T2 with setting BPS1 015 and 731 000 When T2 is used to reload in the configuration with BPS1 01g and T3I 000 fastest configuration highest resolution of the reload of is performed with a delay of one basic clock cycle Workaround 1 To compensate the delay and achieve correct timing increment the reload value in T2 by 1 when T3 is configured to count up decrement the reload value in T2 by 1 when T3 is configured to count down Workaround 2 Alternatively use T4 instead of T2 as reload register for T3 In this configuration the reload of T3 is not delayed i e the effect described above does not occur with T4 OCDS X 003 Peripheral Debug Mode Settings cleared by Reset The behavior run stop of the peripheral modules in debug mode is defined in bitfield SUMCFG in the KSCCFG registers The intended behavior is that after an application reset has occurred during a debug session a peripheral re enters the mode defined for debug mode Errata Sheet
26. ely proportional to the converter active time Recommendation for Minimum Power Consumption In order to minimize the contribution of A D conversions to the total power consumption it is recommended 1 to select the internal operating frequency of the analog part near the maximum value specified in the Data Sheet and 2 to switch the ADC to a power saving state via ANON while no conversions are performed Note that a certain wake up time is required before the next set of conversions when the power saving state is left Note The selected internal operating frequency of the analog part that determines the conversion time will also influence the sample time ts The sample time ts can individually be adapted for the analog input channels via bit field STC 12 X H001 Enabling or Disabling Single Event Operation The single event operation mode of the 1 2 unit eliminates the need for software to react after the first compare match when only one event is required within a certain time frame The enable bit SEEy for a channel CCy is cleared by hardware after the compare event thus disabling further events for this channel One Channel in Single Event Operation As the Single Event Enable registers CC1 SEE CC2 SEE are not located in the bit addressable SFR address range they can only be modified by instructions Errata Sheet 42 V1 7 2013 06 2200 Derivative
27. escription 6 2 Deviations from Electrical and Timing Specification FLASH X P001 Test Condition for Flash parameter in Data Sheets The Flash endurance parameter Number of erase cycles for 15000 cycles is documented with a wrong Test Condition The Test Condition states today 5 years Valid for up to 64 user selected sectors data storage In fact the amount of Flash memory validated for this cycling rate is more limited and the Test Condition must therefore state the following 5 years Valid for Flash module 1 up to 64 kbytes Note The related use case for this parameter is data storage with high cycling rate in general and EEPROM emulation in particular For these applications concurrent operation of data storage to and program execution from Flash is assumed Refer also to parameter Npp SWD X P002 Supply Watchdog SWD Supervision Level in Data Sheet The Supply Watchdog SWD Supervision Level Vgywp tolerance boundaries for 5 5 V are changed from 0 15 V to 0 30 V Errata Sheet 41 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description 6 3 Application Hints ADC 002 Minimizing Power Consumption of an ADC Module For a given number of A D conversions during a defined period of time the total energy power over time required by the ADC analog part during these conversions via supply is approximat
28. events for CAPCOM channels concurrently operating in single event mode Modify register SEE only when it is ensured that no compare event in single event mode can occur i e when SEE 0x0000 or Modify register SEE only when it is ensured that there is a sufficient time distance to the events of all channels operating in single event mode such that none of the bits in CCn SEE can change in the meantime or e Use single event operation for one channel only i e only one bit SEMx may be 15 and or Use ofthe standard compare modes and emulate single event operation for a channel CCs by disabling further compare events in bit field MODs in register CCn Mz in the corresponding interrupt service routine Writing to register CCn Mz is uncritical as this register is not modified by hardware Errata Sheet 43 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description CC6_X H001 Modifications of Bit MODEN in Register CCU6x_KSCFG For each module setting bit MODEN 0 immediately switches off the module clock Care must be taken that the module clock is only switched off when the module is in a defined state e g stop mode in order to avoid undesired effects in an application In addition fora CCU6 module in particular if bit MODEN is changed to 0 while the internal functional blocks have not reached their de
29. ffects devices with a Date Code before DC1239 i e digit value 1239 XC2000 XE166 devices allow the user to select between a number of debug interface options including type JTAG DAP and pin assignment The primary selection is done by configuration pins upon power on where one of the supported options is to install the debug interface according to the value taken from dedicated locations in user Flash CO01F0 C001F3 This option is selected by configuration pin values HWCFG xxxxx111g code start from internal Flash or 1100000 code start from external memory The other configurations directly selecting a debug mode work correctly The start up procedure reads the dedicated locations in Flash too early before Flash redundancy is installed which can lead to an unrecoverable read error and terminate the boot process if the block from C001F0 to COO1FF is programmed by the user A limited number of devices are affected a rough estimation is below 195 from the production and the mis behavior is constant That means any device is either always error free or always failing if no programming of the block from to COO1FF is done after the last power on Note that only the two mentioned modes upon power on and only the read from dedicated locations during start up are affected but not in general Flash and debug interface functionality Workaround 1 Do not program the page from C00180 to COO1FF
30. fined stop conditions and later MODEN is set to 1 and the mode is not set to run mode this leads to a lock situation where the module clock is not switched on again ECC X H001 ECC Error Indication Permanently Set The ECC error flag of the ECCSTAT register for the DPRAM DSRAM PSRAM and SBRAM can not be cleared if a memory location with an ECC error is selected and the ECC is enabled The memory can be selected by an active or by the latest read or write access Workaround Select a memory location without ECC error in the respective memory e g make a read to another address and then clear the ECC error flag Be aware that the new selected address may also have an ECC error GPT12 ALHO001 Modification of Block Prescalers BPS1 and BPS2 The block prescalers BPS1 and BPS2 controlled via bit fields T3CON BSP1 and T6CON BPS2 determine the basic clock for the GPT1 and GPT2 block respectively After reset when initializing a block prescaler BPSx to a value different from its default value 00g it must be initialized first before any mode involving external trigger signals is configured for the associated GPTx block These modes include counter incremental interface capture and reload mode Otherwise unintended count capture reload events may occur Errata Sheet 44 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description In case a block prescaler BPSx needs to be mo
31. gure 1 Errata Sheet 23 V1 7 2013 06 um XC2200N Derivatives Infineon XC2000 Family Value Line Detailed Errata Description MOV OF804h R15 1 N2 0 other instructions 2 5 CP 0F7E6h Load R15 via PortA 25 Load new context Global register bank OF7E6 Store old 2 2 context Old context Register File DPRAM Figure 1 Context Switch with Pointer Passing in R15 Scenario 2 CoXXX Instructions In this scenario the problem may occur when one of the CoXXX instructions CoABS CoADD CoCMP CoLOAD CoMAC CoMAX CoMIN CoMUL CoSUB reads L or L via the addressing mode IDXi Note All other CoXXX instructions COASHR CoMOV CoNEG CoNOP CoRND CoSHL R CoSTORE and addressing modes are not affected 1 stands for all variants of the respective instruction 2 stands for all variants of the IDXi RWm addressing mode Errata Sheet 24 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description Analysis of Development Tools Summary of Supplier Feedback TASKING VX toolset for C166 latest version v3 1r1 Scenario 1 Context Switch In the most basic form without registerbank function qualifier the compiler uses push pop instructions to save restore registers in the interrupt frame i e the critical scenar
32. he RTC count source in bit field RTCCLKSEL In case power domain DMP 1 is switched off it is not required to switch the RTC to Asynchronous Mode since it will receive a reset in any case SCU X H009 wUCR TTSTAT can be set after a Power Up After power up the wake up clock fwy is selected for the Wake Up Timer WUT In this case the trim interrupt trigger cannot be used because the WUT trim trigger status bit WUCR TTSTAT might become set erroneously This happens sporadically and is therefore difficult to find in the development phase of an application If the trim interrupt trigger is enabled this may lead to unintended SCU interrupts that may also block other interrupt sources see INT_X H004 This can be avoided by executing the following sequence 1 Disable the trim interrupt source SCU_INTDIS WUTI 2 Clear the trim interrupt request flag by writing to INTCLR WUTI 3 Clear the selected SCU request flag default is ScU_1IC IR SWD X H001 Application Influence on the SWD The internal Supply Watchdog SWD monitors the external supply voltage of the pad I O domain Vpppg which is connected to the device Therefore adjustable threshold levels are defined over the complete supply voltage range Errata Sheet 52 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description These limits are also influenced by system environment and may deviate due to external influences slightly from
33. he WDT has already been exceeded once is stored in an internal flag In contrary to the documentation that this flag can be cleared by writing a 1g to bit WDTCS CLRIRF at any time clearing of the internal flag is only possible when the WDT is in Prewarning Mode Errata Sheet 38 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Workaround 1 Applications following the proposal of Application Note AP16103 section Using ESR pins to trigger a PORST reset to trigger a Power on Reset upon a WDT event will find the internal flag cleared upon the Power on Reset and thus will have no issue with this limitation Workaround 2 In case the WDT triggers a User Reset upon a WDT overflow the internal flag will not be cleared by the reset itself Any further overflow of the WDT will lead to a permanent reset of the device Applications which intentionally let the WDT exceed once e g in conjunction with an initial self test might want to have the internal flag cleared to prevent a permanent reset upon a real WDT overflow If the internal flag shall be cleared by software this must be done as a reaction overflow in the time frame the WDT is in Prewarning Mode before the permanent User Reset will be triggered The CPU is notified upon the WDT entering Prewarning Mode by issuing an interrupt request The application can react on this request and clear the internal flag n
34. he wrong 5 0 RSTCONx register value The critical time window occurs when the SSW is writing the SCU_RSTCONx registers and at the same time the ESRy reset request is processed by the reset circuitry The width of this critical window f i window IS less than 13 cycles Application Reset gt i ha window 1 1 Reset 1 by ESRy pin 1 l 1 1 SSW Start of Write Start of End of 1 SSW RSTCON SSW SSW l 1 11 Application Application NJ iu Application Software Runs 1 Runs Fog i ESR X 004 Fig 1 Figure 2 Critical application reset sequence Errata Sheet 27 V1 7 2013 06 XC2200N Derivatives Infineon XC2000 Family Value Line Detailed Errata Description Workaround e Initialize 5 0 RSTCONx registers by user software after any reset or assure that a second application reset request with an ESR pin does not occur during the critical time window 12 X 002 Effects of GPT Module Microarchitecture The present GPT module implementation provides some enhanced features e g block prescalers BPS1 BPS2 while still maintaining timing and functional compatibility with the original implementation in the C166 Family of microcontrollers Both the GPT1 and GPT2 blocks use a finite state machine to control the actions within each block Since multiple interactions are possible between the timers T2 T6 and register CAPREL these elements are processed sequentially
35. io does not occur Whenthe registerbank function qualifier is used to define a global register bank the user stack pointer R15 is copied and the context pointer is set to the new register bank This is rated as critical only if R15 is used to access the user stack within the interrupt routine Exception In the routine for the reset vector the user stack pointer is not copied makes no sense for the reset vector This is rated as uncritical Scenario 2 CoXXX Instructions The compiler currently does not use the IDXi addressing mode In setjmp src from the C library and macmull src from the runtime library CoSTORE instructions are used This is rated as uncritical Classic TASKING C166 ST10 toolset latest version v8 9r1 Scenario 1 Context Switch In all cases where the user stack pointer is copied register RO even register number is used This is rated as uncritical Scenario 2 CoXXX Instructions The compiler currently does not use the IDXi addressing mode In the runtime library modules cp w asm and udil asm umol asm CoXXX instructions may be used but none of them belongs to the category of critical instructions in the scope of this problem Keil C166 Development Tools Scenario 1 Context Switch Without the using attribute the critical scenario will not occur With the using attribute in all cases where the user stack pointer is copied register RO even register number is used Th
36. ions from Electrical and Timing Specification 17 Application Hints siis Re n eR eee eee 18 Documentation Updates 20 Detailed Errata Description 21 Functional Deviations 21 BROM TG 000 1x guess eterno ue e E kek eh 21 BSL CAN X001 1 2 ee 21 DPRAM X002 lu mes lm eee bee s 22 ESR 002 5 6 Eaten viui adt une 26 ESR X 004 cinis lin bore pi3 Y E 27 GPT12bE A002 oeri ea DPE EERE 28 OCDS X003 loose s d E imee bee 29 PAD 25001 Shae Belek Bak tnt a dedere trea wes 30 PARITY 2001 ui aon xm x wage sale Men DER EORR ER 35 003 55 51 5 8 0 Peach E Den ha E 35 SCU pel P 35 003 ge t Ente 36 DUSIC ALE004 ER EROR eee ee ale eka wee ROS Ross 80x 37 0051 6 41 005 pico pete bbe Rr RETO IE Red dus 37 USIC AL010 fic nnersbeURPOC ERR eaters ak earth Rabe 38 WD X002 Ree beer Rok e uon E Rune uite n renda 38 Deviations from Electrical and Timing Specification 41 FLASH 22 mei x 41 SWD X P002 necp ebrei REV RR un pao ene ences 41 Application Hints 0 000002 eee 42 ADC ALHO002 nsiet PES
37. is is rated as uncritical Analysis also applicable to derived free toolsets VX toolset Lite Edition resp XE166 toolset Errata Sheet 25 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Scenario 2 CoXXX Instructions The compiler including the intrinsics currently does not use the IDXi addressing mode Workaround Scenario 1 assembler level do not perform a context switch of the global register bank in case locations in the DPRAM corresponding to the location of a register Rx with an odd register number are written by software see example for critical scenario in Figure 1 With the compiler of the TASKING VX toolset do not use the registerbank function qualifier to define a global register bank With the compiler of the Classic TASKING C166 ST10 toolset no workaround for this scenario is required see analysis above With the compiler of the Keil C166 toolset no workaround for this scenario is required see analysis above Workaround Scenario 2 On assembler level do not use the CoXXX instructions 5 CoADD CoCMP CoLOAD CoMAC CoMAX CoMIN CoMUL CoSUB with the addressing mode IDXi RWm Instead use e g the other addressing modes of these instructions For compilers of the Keil and TASKING toolsets no workaround is required see analysis above Usage of 3 Party Software When using ope
38. ity of occurring at the next power off on cycle The addresses of L and L may vary from device to device and from one power off on cycle to the next but will not change for a given device until the next power off on cycle i e if L and L are not read via port A in one of the critical scenarios described below the problem has no effect on the application Scenario 1 Context Switch In this scenario the problem may occur under the following sequence of conditions all conditions must be met 1 L and or L are located in the DPRAM in an area that is used to store the context of a global register bank and Errata Sheet 22 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description 2 Anexplicit software write operation i e no context switch to L and or L is performed and 3 The Context Pointer register CP is modified e g by MOV POP SCXT CP in one of the following instructions leading to a context store old context and a context load new context of the global bank into from DPRAM and 4 One of the General Purpose Registers Rx with an odd register number x x 1 3 15 is loaded from locations L or L3 In this case the contents of Rx may be incorrect This scenario may typically occur at the beginning of interrupt routines when a GPR e g R15 used as user stack pointer is saved into the new GPR context in DPRAM as shown in the following Fi
39. ives Table 3 Errata Device Overview Deviations from Electrical and Timing Specification XC22xxN AC DC ADC Deviation FLASH_X P001 SWD_X P002 AA x AB Errata Sheet 11 V1 7 2013 06 Cinfineon XC2200N Derivatives XC2000 Family Value Line 4 3 Application Hints Errata Device Overview Table 4 shows the dependencies of application hints in the derivatives Table 4 Application Hints Errata Device Overview Hint XC22xxN AI H002 CAPCOM12 X H001 CC6 X H001 ECC X H001 GPT12 AI H001 12 X H002 INT X H002 INT X H004 MultiCAN 005 MultiCAN 006 MultiCAN 007 MultiCAN 008 MultiCAN TC H002 MultiCAN TC H003 MultiCAN TC H004 OCDS X H003 PVC X H001 RESET X H003 x x xx xx x x x x x x x OK ox ox ox gt lt gt lt OK OK X x x ES AB AB Errata Sheet 12 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Errata Device Overview Table 4 Errata Device Overview Application Hints cont d XC22xxN Hint RTC X H003 SCU X H009 SWD X H001 StartUp X H001 USIC AI H001 USIC AI H002 USIC AI H003 X x AB x x x AA Errata Sheet 13 V1
40. me range In the example an erratic edge would cause the measured time interval terratic interval tO be approximately 50 of the expected value The state of the input pin that caused the interrupt could be read several times in the interrupt service routine and a majority decision made to check if the input pin really is at a low level to determine whether this is a genuine falling edge interrupt or whether the interrupt was triggered by a spike generated by a slow rising edge 0 7 Input Signal Internal Signal L 4 L1 1 I I 1 ERR r I 1 Unexpected Edges 1 5 1 terratic interval tinterval PAD_X 001 Fig 2 Figure 4 Falling Edge Detection Approach Only if 1 and or 2 indicate that the edge was reliable should the rest of the interrupt service routine be executed 4 2 Rising Edge Detection Approach In case of rising edge detection multiple interrupts would be generated when the spike occurs The time interval since the last interrupt can be measured if it is very small compared to the expected value this would indicate a spike and the interrupt should be ignored Errata Sheet 33 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description 0 7 u
41. n XC2000 Family Value Line Errata Device Overview 4 Errata Device Overview This chapter gives an overview of the dependencies of individual errata to devices and steps An X in the column of the sales codes shows that this erratum is valid 4 1 Functional Deviations Table 2 shows the dependencies of functional deviations in the derivatives Table 2 Errata Device Overview Functional Deviations XC22xxN Functional Deviation BROM TC 006 BSL CAN X 001 DPRAM X 002 ESR X 002 ESR X 004 12 X 002 OCDS X 003 PAD X 001 PARITY X 001 RESET X 003 SCU X 012 StartUp X 003 USIC 1 004 x ES AB x x x x x x x x X X X X X OK X x Errata Sheet 9 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Errata Device Overview Table 2 Errata Device Overview Functional Deviations cont d z x x N N 5 Functional Deviation a lt 5 77 USIC 005 USIC 1 016 WDT X 002 X X 1 From AA step to AB step 1 erratum has been fixed Errata Sheet 10 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Errata Device Overview 4 2 Deviations from Electrical and Timing Specification Table 3 shows the dependencies of deviations from the electrical and timing specification in the derivat
42. ow by writing a 1 to bit WDTCS CLRIRF e g within an ISR Workaround 3 Some applications may not want to use or rely on the interrupt logic in conjunction with a WDT overflow event The proposed remedy in this case is to initiate a Power Reset to clear the internal flag by changing the settings of the active Supply Watchdog SWD as follows 1 Disable SFR protection 2 Write the inverted value of bit LxALEV to register SWDCONO where x stands for the number of the comparator which currently would trigger a Power Reset In doing so a Power Reset for VDDI_1 and VDDI_M will be activated clearing the internal flag The application may store information on preceding WDT events in the Standby SRAM This can be done any time after the WDT reset without timing limitations or the need to use the interrupt logic Errata Sheet 39 V1 7 2013 06 e XC2200N Derivati atives Infineon 2 2000 Family Value Line Detailed Errata Description Note Although the supply for the DPRAM DSRAM and PSRAM will be switched off during the active reset phase it depends on the external buffer capacitance at the 1 pins the actual system clock frequency andthe environmental conditions whetherthe content of these RAMS will be preserved in this case or not However the Standby RAM itself is not cleared upon this reset Errata Sheet 40 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata D
43. pins Those in turn can cause unwanted switching activity on attached device input stages Therefore attached devices should be equipped with an input hysteresis filter to avoid unwanted switching activity 2 After an internal LXBus access is completed the address of the location accessed last on the LXBus becomes visible on the external address bus unless an external bus cycle immediately follows the LXBus cycle Due to this behavior switching activity on the address bus can be observed even if no external access is active Note A functional impact due to this behavior is not expected because external bus control signals are held inactive during the internal LXBus access RESET X D001 Reset Types of Trap Registers The reset type of SCU registers TRAPDIS TRAPSET TRAPNP and 1 is an Application Reset In the next revision of the user s manual the reset type of this registers will be changed from a Power on Reset to an Application Reset Errata Sheet 55 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description USIC X D002 USIC1 Channel 0 Connection and The connectivity description for USIC1 channel 0 DXOC and DXOD in the User s Manual V2 0 chapter Universal Serial Interface Channel table I O Connections of USIC1 is not correct The correct I O connection for USIC1 channel 0 DXOC is P10 12 and for DXOD is P10 13 Errata Sheet 56 V
44. r i e use only HDEL 0 default or write TBUF before the end ofthe last transmission end of the acknowledge bit is reached Errata Sheet 37 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description USIC AL016 Transmit parameters are updated during FIFO buffer bypass Transmit Control Information TCI can be transferred from the bypass structure to the USIC channel when a bypass data is loaded into TBUF Depending on the setting of TCSR register bit fields different transmit parameters are updated by TCI When SELMD 1 PCR CTR 20 16 is updated by BYPCR SELO applicable only in SSC mode When WLEMD 1 SCTR WLE and TCSR EOF are updated by BYPCR BWLE When FLEMD 1 SCTR FLE 4 0 is updated by BYPCR BWLE When 1 SCTR HPCDIR and SCTR DSM are updated by BHPC When all of the xxMD bits are 0 no transmit parameters will be updated However in the current device independent of the xxMD bits setting the following are always updated by the TCI generated by the bypass structure when TBUF is loaded with a bypass data WLE HPCDIR and DSM bits in SCTR register EOF and SOF bits in TCSR register e PCR CTR 20 16 applicable only in SSC mode Workaround The application must take into consideration the above behaviour when using FIFO buffer bypass WDT X 002 Clearing the Internal Flag which Stores Preceding WDT Reset Request The information that t
45. rating systems and or other 379 party software or libraries please check with your supplier ESR X 002 ESREXSTAT1 and ESREXSTAT2 Status Bits can be Cleared af ter a Write Access During a write access to any register bits in registers ESREXSTAT1 2 can be cleared inadvertently ESREXSTAT1 2 store event s that can trigger various ESR functions Errata Sheet 26 V1 7 2013 06 XC2200N Derivatives Infineon XC2000 Family Value Line Detailed Errata Description Workaround Make sure that the trigger signals are still active when the associated service routine runs so the trigger source can be evaluated by software ESR X 004 Wrong Value of scu RsTCONx Registers after ESRy Applica tion Reset SCU RSTCONx registers are reset only by Power On but they may be wrongly affected after a second application reset requested by an ESRy pin This may lead to the SCU_RSTCONx register values being set to zero which could unexpectedly disable reset sources within the user application The conditions which lead to this behavior are 1 First an application reset by SW software CPU Central Processing Unit MP Memory WDT Watchdog Timer or ESRy External Service Request y occurs 2 Following this an application reset on an ESRy pin occurs 3 If the above mentioned ESRy reset occurs during a critical time window of the SSW startup software then it s possible that the application will operate with t
46. rce and trigger a software reset with CAN bootstrap loader mode selected Now the Errata Sheet 21 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description device starts with a CAN bootstrap loader without limitation of the oscillator settling time DPRAM X 002 Undefined Data read from Dual Port RAM DPRAM Under special conditions undefined data may be read from up to two word locations L L in the DPRAM address range F600 FDFF The problem affecting L and or L is due to a redundancy circuit that may not be properly disabled during the internal power up reset sequence The problem may only occur when an operand that was written via port B is later read via port A of the DPRAM This is only the case when dual read transfers are performed on both port A and B in parallel which can only happen in the two scenarios described below Note Field experience has shown that the probability for this problem is relatively low as it further depends on several other conditions e g For an initial power on reset without residual voltage the problem is less likely to occur at room temperature and above The problem is more likely to occur when a residual voltage at VDDI1 was present at the last power off on cycle If the problem does occur then it is latched at power up If it hasn t occurred in the current power cycle then the problem only has the possibil
47. ruction that reaches the Memory stage is replaced with the corresponding TRAP instruction In some special situations described in the following a valid instruction may not immediately be available at the Memory stage resulting in an increased delay in the reaction to the trap request 1 When the CPU is in break mode e g single stepping over such instructions as SBRK or BSET TFR x where x one of the trap flags in register TFR will have no immediate effect until the next instruction enters the Memory stage of the pipeline i e until a further single step is performed 2 When the pipeline is running empty due to mispredicted branches and a relatively slow program memory with many wait states servicing of the trap is delayed by the time for the next access to this program memory even if vector table and trap handler are located in a faster memory However the situation when the pipeline prefetcher are completely empty is quite rare due to the advanced prefetch mechanism of the C166S V2 core Errata Sheet 46 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description INT X H004 SCU Interrupts Enabled After Reset Following a reset the SCU interrupts are enabled by default register SCU INTDIS 0000 This may lead to interrupt requests being triggered in the SCU immediately even before user software has begun to execute In the SCU multiple interrupt sources are ORed
48. s Infineon XC2000 Family Value Line Detailed Errata Description operating on data type WORD This is no problem when only one channel of a CAPCOM unit is used in single event mode Two or more Channels in Single Event Operation When two or more channels of a CAPCOM unit are independently operating in single event mode usually an OR instruction is used to enable one or more compare events in register CCn SEE while an AND instruction may be used to disable events before they have occurred In these cases the timing relation of the channels must be considered otherwise the following typical problem may occur Inthe Memory stage software reads register CCn SEE with bit SEEy 1g event for channel CCy has not yet occurred Meanwhile event for CCy occurs and bit SEEy is cleared to 0 by hardware Inthe Write Back stage software writes CCn SEE with bit SEEx 1g intended event for CCx enabled via OR instruction and bit SEEy 7 1g e as inverse procedure software writes CCn SEE with bit SEEx intended event for CCx disabled via AND instruction and bit SEEy 1 In these cases another unintended event for channel CCy is enabled To avoid this effect one of the following solutions depending on the characteristics of the application is recommended to enable or disable further compare
49. safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Qafineon 16 32 Bit Architecture 2200 Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family Value Line Errata Sheet V1 7 2013 06 Microcontrollers XC2200N Derivatives Infineon XC2000 Family Value Line Table of Contents 1 2 3 4 4 1 4 2 4 3 4 4 5 5 1 5 2 5 3 5 4 5 5 6 6 1 6 2 6 3 History List Change Summary 6 General Ea bid ohne E FER 7 Current Documentation elles 8 Errata Device 9 Functional Deviations 9 Deviations from Electrical and Timing Specification 11 Application Hints 12 Documentation Updates 14 Short Errata Description 15 Errata Removed in this errata sheet 15 Functional Deviations 15 Deviat
50. sing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Errata Sheet 6 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line General 2 General This Errata Sheet describes the deviations of the XC2200N Derivatives from the current user documentation Each erratum identifier follows the pattern Module Arch TypeNumber Module subsystem peripheral or function affected by the erratum e Arch microcontroller architecture where the erratum was firstly detected Al Architecture Independent TC TriCore X XC166 XE166 XC2000 Family Type category of deviation none Functional Deviation P Parametric Deviation H Application Hint D Documentation Update Number ascending sequential number within the three previous fields As this sequence is used over several derivatives including already solved deviations gaps inside this enumeration can occur This Errata Sheet applies to all temperature and frequency versions and to all memory size variants of this device unless explicitly noted otherwise Note This device is equipped with a C166S V2 Core Some of the errata have workarounds which are possibly supported by the tool vendors Some corresponding compiler switches need possibly to be set Please see the respective documentation of yo
51. to a common interrupt node of the CPU interrupt controller Due to the ORing of multiple interrupt sources only one interrupt request to the interrupt controller will be generated if multiple sources at the input of this OR gate are active at the same time If user software enables an interrupt in the interrupt controller SCU x1C which shares the same node as the SCU interrupt request active after reset it may lead to the effect of suppressing the intended interrupt source So for all SCU interrupt sources which will not be used make sure to disable the interrupt source SCU INTDIS and clear any pending request flags SCU_xIC IR before enabling interrupts in interrupt controller MultiCAN AI H005 TxD Pulse upon short disable request If a CAN disable request is set and then canceled in a very short time one bit time or less then a dominant transmit pulse may be generated by MultiCAN module even if the CAN bus is in the idle state Example for setup of the CAN disable request MCAN KSCCFG MODEN 0 and then KSCCFG MODEN 1 Workaround Set all INIT bits to 1 before requesting module disable MultiCAN AI H006 Time stamp influenced by resynchronization The time stamp measurement feature is not based on an absolute time measurement but on actual CAN bit times which are subject to the CAN resynchronization during CAN bus operation The time stamp value merely indicates the number of elapsed actual bit times Those actual
52. ur compiler For effects of issues related to the on chip debug system see also the documentation of the debug tool vendor Some errata of this Errata Sheet do not refer to all of the XC2200N Derivatives please look to the overview Table 2 for Functional Deviations Table 3 for Deviations from Electrical and Timing Specification Table 4 for Application Hints Table 5 for Documentation Updates Errata Sheet 7 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Current Documentation 3 Current Documentation The Infineon XC2000 Family comprises device types from the XC2200 group the XC2300 group and the XC2700 group The XC22xxN device types belong to the XC2200 group Device XC22xxN Marking Step AA ES AB AB Package PG LQFP 64 PG LQFP 100 This Errata Sheet refers to the following documentation e XC2200N Derivatives User s Manual e XC223xN Data Sheet e XC226xN Data Sheet Documentation Addendum if applicable Make sure you always use the corresponding documentation for this device available in category Documents at www infineon com xc2200 The specific test conditions for EES and ES are documented in a separate Status Sheet Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only Errata Sheet 8 V1 7 2013 06 infir XC2200N Derivatives nrineo
53. ut value to the port pin through OMR Enable the output driver for the general purpose output through Pn IOCRx Disable USIC protocol through CCR MODE USIC AI H003 PSR RXIDLE Cleared by Software If PSR RXIDLE is cleared by software the USIC is not able to receive until the receive line is detected IDLE again see User s Manual chapter Idle Time For UART based busses with higher traffic e g LIN it is possible that sometimes the next frame starts sending before PSR RXIDLE is set 1 by hardware again This generates an error A solution is that the PSR RXIDLE bit is not cleared in software Errata Sheet 54 V1 7 2013 06 2200 Derivatives Infineon XC2000 Family Value Line Detailed Errata Description 6 4 Documentation Updates EBC X D001 Visibility of Internal LXBus Cycles on External Address Bus EBC chapter Access Control to LXBus Modules receives the following correction In the first paragraph the term read mode is replaced by tri state mode The following is added Despite the above mentioned measures accesses to internal LXBus modules are to some extent reflected on the non multiplexed address pins A 23 0 of the external bus 1 During an internal LXBus access the external address bus is tri stated The switch to tri state mode occurs in the same cycle as the internal LXBus access This may induce residual voltage which can lead to undefined logic levels on the address bus
54. within each block in different states However all actions are normally completed within one basic clock cycle The GPT2 state machine has 4 states 2 states when BPS2 01g and processes T6 before T5 The GPT1 state machine has 8 states 4 states when BPS1 01g and processes the timers in the order T2 all actions except capture T4 T2 capture In the following two effects of the internal module microarchitecture that may require special consideration in an application are described in more detail 1 Reading T3 by Software with T2 T4 in Reload Mode When T2 or T4 are used to reload on overflow underflow and is read by software on the fly the following unexpected values may be read from T3 when is counting up 0000 or 0001 may be read from directly after an overflow although the reload value in T2 T4 is higher 0001 may be read in particular if BPS1 01g and 0005 when is counting down FFFF or FFFE may be read from directly after an underflow although the reload value in T2 T4 is lower FFFE may be read in particular if BPS1 01g and 000p Errata Sheet 28 V1 7 2013 06 infir XC2200N Derivatives nrineon XC2000 Family Value Line Detailed Errata Description Note All timings derived from T3 in this configuration e g distance between interrupt requests PWM waveform on T3OUT etc are accurate except for the specific case described under 2 b
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