Description des registres de Mimosa22 :
Contents
1. Internal Simulation Resolution Range Experimental DAC Code DacInternal Output Code Name Code current uA value Codey IKIMO 64 100 100 1V 10 mV From 0 up to 2 55 V IPIX 32 50 50 20uA lpA From 0 up to 255 uA IVTST2 71 113 113 1 182 V 10 mV From 1 up to 1 5 V IVTSTI 8C 140 140 1 183 V 250 uV From 30 up to 34 mV IDIS2 20 32 32 5 uA 156 nA From 0 up to 255 uA IDIS1 20 32 32 10uA 312nA From 0 up to 255 pA IVDREF2 71 113 113 1 182 V 10 mV From 1 up to 1 5 V IVDREFI 80 128 128 1 182 V 250 uV From 30 up to 34 mV 1 IAnaBUF 32 50 50 500 uA 10 uA From 0 up to 255 uA ILVDS 20 32 32 7uA 218 nA From 0 up to 255 uA ID2PWRS A 10 10 100nA 10nA From 0 up to 255 uA IDIPWRS A 10 10 100nA 10nA From 0 up to 255 uA IBufBias A 10 10 10pA lpgA From 0 up to 255 pA IPwrS WBias A 10 10 10pA lpgA From 0 up to 255 pA ICLPDISC 64 100 100 2 1V 10 mV From 1 2 up to 3 2 V 1 Referenced with respect to IVDREF2 The threshold voltage of the discriminators AVth is defined as Vref1 Vref2 Vrefl Vref2 AVth November 2007 Mimosa22 User Manual V 1 0 13 Mimosa22 Bias synthetic block diagram Oo El Oo E ia a a Lal LJ iex C d H VCLPDIS ex Discriminators Sj E E F Or CH CH Y VTEST VTEST2 VDREHM VDREF2 DISCLP Power Pulse Pulse IAnaBU Gy s WEI Ge Py 5 q LEI JO GT BUFBIAS PWRSWBIAS _IDIS1 IDIS2 ID1 PWRSID2 PWRS 3 3 Setting the Readout2. November 2007 Mimosa22 User Manual V 1 0 3 Mimosa22 Digital Analog Supplies Supplies gnd vdd vdd latch vdd diode vdda gnd V Clp Bias Tests VKIMO Tempout NN IPIX VTEST2 VTEST4 input IDIS2 Ref Tests IDIS1 VDR2 VCLPDIS VH Vrefi IAnaBUF Vref2 ILVDS Viet BUFBIAS Vtst2 PWRSWBIAS DISCLP ITEST Pix CSG10 D2RadTol Pix CSG10ActRst D2 Pix CSG10 D2 Pix CSG D2RadTol Pix CSG7ActRst D2 Pix CSG D2 Pix CSG5 D2 Pix lt 575 135 gt Pix_CSG5_D1 Pix lt 575 0 gt Ctrl Pixel Discri Power Supplies CMOS Signals LVDS Signals TempOut Tes Aout 7 Aout 0 A 1D v 2 o a Mimosa22 functional view Does not correspond to the floorplan neither for the core neither for the pad ring November 2007 Mimosa22 User Manual V 1 0 Analogue Signals Mimosa22 Test Row Circuit type i A Vdd_ Row Name matrix addresses diode Number range 5 V High gain CS CSTVF tstl Time variant feedback 31 16 High gain CS Time variant 3 8x3 8 2 1 2 4 feedback 79 32 High gain CS Time variant 3 8x3 8 2 1 2 4 feedback 95 80 High gain CS Time variant 3 8x3 8 2 1 2 4 feedback CSTVF tst2 CSTVF RadTol 1 CSTVF RadTol poverlap 1 159 96 High gain CS Time variant 3 8x3 8 2 1 2 4 feedback 223 160 High gain CS Self biased 287 224 High gain CS 64 Self biased 303 288 High gain CS CSFB_tst1 Self biased 319
3. iPHC Institut Plyridisci linaire URIEN Bert SERIEN Mimosa22 User Manual Preliminary version A Himmi G Bertolone A Brogna W Dulinski C Colledani A Dorokhov Ch Hu F Morel I Valin Institut de Recherches Subatomiques IN2P3 CNRS ULP Strasbourg France Y Degerli F Gilloux CEA Saclay DAPNIA SEDI u IN2P3 B DELA RECHERCHE Zz SCIENTIFIQUE UNIVERSIT M LOUIS PASTEUR Istrrur NATIONAL DE us SIQUE n CL ARE BE STRASBOURG ET DE Puysigue ves Pa d IPHC Institut Pluridisciplinaire Hubert CURIEN STRASBOURG Document histor November 2007 Based on Mimosal6 Version Mimosa22 chip Submitted October 07 AMS 035 Opto Version 576 x 136 pixels NL Ops N 2 P 3 ul En E p SCIENTIFIQUE d 5 UNIVERSIT M LOUIS PASTEUR Instrrur NariONAL mp PuvsiQue NucL AIE STRASBOURG ET DE PHYSIQUE DES PARTICULES Mimosa22 NEM UV ED 3 2 Coombr Mier aCe E 5 2 1 JTAG struction S toise E m m I TU 6 MEE UN TSEI UU eSI Mc 6 2I Instruction EE 7 2 2 2 DEV E E 7 2 2 3 Bypass Register eieren ERE AA E A iE 7 2 2 4 Boundary Scan Register sisse esame Suv prO tme EDD MR OD Grimm n teda epus 7 2 25 BIAS DAC BSEISIBEL e poii itii dot irse poi Gu beue ae eerie tees 7 2 2 6 RO MODEQ Duc 8 2 2 7 RO MODE uc o M 9 2 2 8 CONTROL JEECEBRBEISIBE iiie uci eiie idi qe Ii p eh bii UP UE ede 9 2 2 9 SEQUENCER REG Re GUC aoier t ttes tato in Hone ari
4. Int 74 F gt Rst 574 i Clamp 574 a Caib 0 DW FU E Bi Latch 0 L For Sub arrays S10 S17 the Pwr_On signal is not used for pixel November 2007 Mimosa22 User Manual V 1 0 11 Mimosa22 2 2 10 DIS DISCRI Register The DIS DISCRI register is 128 bits large The purpose of this register is to disable the discriminator on a specific column if it is noisy by gating Latch signal and setting the output discriminator at 0 The default value of the DIS_DISCRI register is 0 it means that all discriminators are activated Setting a bit to 1 disables the corresponding discriminator In Mimosa22 the DisableLatch lt 127 gt is on the left hand side while DisableLatch 0 is on the right hand side 127 Msb 0 Lsb DisableLatch 127 DisableLatch lt 0 gt 2 2 11 LINEPAT_REG Register The LINEPAT_REG register is 128 bits large The purpose of this register is to emulate discriminators outputs rows in En_LineMarker and Pattern_Only modes When Pattern_Only is active during the readout of matrix the value of LINEPAT_REG is read to emulate discriminators outputs of each matrix row This mode corresponds to debug mode it allows verify the digital processing In the En_LineMarker mode it adds two rows at the end of matrix for a readout chip and the LINEPAT_REG register is read to emulate the discriminators outputs of these two supplementary rows This mode allows generating pattern marker in matrix data frame to detect chip readout desync
5. x j1 o 2 2 2 DEV ID Register The Device Identification register is implemented It is 32 bits long and has fixed value hardwired into the chip When selected by the ID CODE instruction or after the fixed value is shifted via TDO the JTAG serial output of the chip Mimosa22 ID CODE register value is 0x4D323201 Default value Code 31 0 ID CODE Device Identification register 4D323201 2 2 3 Bypass Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction 2 2 4 Boundary Scan Register The Boundary Scan Register according with the Jtag instructions tests and set the IO pads The Mimosa22 BSR is 10 bits long and allows the test of the following input and outputs pads 5 SPEAK Input SPEAK Active Readout Marker Clock s fams mm amos emos er 0 mo smkr ulli LVDS CkRdLn CkRdLp ClkLvds ETS CMOS signal after LVDS Receiver s MKgKp EE o era Pup Tei RedowTexPal 2 2 5 BIAS DAC Register The BIAS DAC register is 120 bit wide it sets simultaneously the 15 DAC registers As show bellow these 8 bit DACs set voltage and current bias After reset the register is set to 0 a value which fixes the minimum power consumption of the circuit The current values of the DACs are read while the new values are downloaded du
6. 0 16 Mimosa22 N Baseline H Cursor Baseline v Name v Cursor v ns 160us _ g00us 240us H 1 0 o 1 Ee Jens continuous LATCH 1 35065e 10 v Hi 1 AR continuous C ALIB 2 29512e 08 v HI E E d i continyous LATCH 1 95065e 10 v H4 E E3 33181V MN continuous EnTstMk essem ni i ft 010070230 y 78 LastRow 0 Er CUCA o 2 92017 E continuous Aout t 2 39376 v u b 1 Kr continucus Aout D 2 38976 v EI a E T351743V Reset Jtag access Int UU 1rst row readout j Successive row readouts Figure 1 3 6 2 Readout synchronisation 15 ns after the first rise edge clock of CK100M when START signal is rising the internal reset SeqRstB signal is generated The data sequencer_reg is loaded to a state machine Readout Controller Name Cursor v 88 000ns 88 400ns T 89 200ns D E 1 T 1 START SeqhstB ckSOM CkDivi amp SynMxRov Readout of matrix starts SLoad CkLoad Fa On 575 Sit Row Int 575 When SyncMux is rising ap E the multiplexer of data Cimping7S f discriminators 8 to 1 starts Data are serialized on fall edge clock of ClikMux same of CLKD When Sload signal is rising the state machine After the end of START signal of Readout Controller generates usefull When the first fall edge clock of CKDiv16 signals for pixel and discriminator readout arri
7. 304 A gain CS CSFB_tst2 Pix_CSG10_D2RadTol G 351 320 High gain CS 3 85x3 95 Reset 383 352 High gain CS Pix CSGIOActRst D2 Time variant 3 375x4 5 feedback mx pe tres esas p 18 rT S14 479 448 Time 3 375x4 5 24 32 Pix CSG7AGIRst D2 variant feedback mu step Genes asas nr us leen S17 575 544 CS Reset 3 45x3 625 21 1 05 Pix _CSG5_ DI CSTVF STD CSFB RadTol UI CSFB STD Summary of pixel matrix 1 For the RadTol pixel the Voltage name RadTolPixGate is set to 0 V by default value or can be adjustable 2 Control Interface The control interface of Mimosa22 complies with Boundary Scan JTAG IEEE 1149 1 Rev1999 standard It allows the access to the internal registers of the chip like the bias Register and the different registers control On Power On Reset an internal reset for the control interface is generated The finite state machine of the Test Access Port TAP of the controller enters in the Test Logic Reset state and the ID register is selected Mimosa22 has been designed in order to be fully adjustable via the control interface Nevertheless several voltages level can be set both via the control interface a via a pad November 2007 Mimosa22 User Manual V 1 0 5 Mimosa22 2 1 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access In
8. 5 4 MODE SPEAK is set to 0 and for Figure 5 b MODE SPEAK is set to 1 November 2007 Mimosa22 User Manual V 1 0 19 Mimosa22 3 6 3 Main Signal Specifications Mate TAG READOUT CKRDDuyCyde sog id START Setup Hold Time 5 nS Chip Initialisation CMOS signal Input Dynamic range 0 0 0 00 0 0 0 0 0 00 Mime Deme m S 20 OUO mewun Cid Dario Sd 4 Pad Ring The pad ring of Mimosa22 is build with Pads full custom designed for some of the analogue signals and power supplies Pads from the AMS library for the digital signals and power supplies The pad ring is split in 8 functional independent parts CMOS JTAG and Test purpose pads LVDS Read Out Drivers Digital outputs Read Out Analogue Outputs Bias Test Analogue and Digital Power supplies Test structure 1 Test structure 2 Each part has its own supply pads November 2007 Mimosa22 User Manual V 1 0 20 Mimosa22 4 1 Mimosa22 Pad Ring and Floor Plan View They are used for internal test P TlandP T2 don t have to be connected November 2007 93 P TI 112 113 RaT Piae vi pal TS Geen G3 pit P_T2 TS_Dignin_G7 wi D TS D s 010 pal TS Doten Bias 4D TS Daps n Pils pi TS Dopein Porn 4D 124 vst P D4 pai 161 a P_A3 E PDS vsih P_D6 asas ARda 173 cemoe Discriminator P_A2 P_D3 P_Al pui KEN vide
9. Configuration Registers If the desired operating mode does not correspond to the default one set RO MODEO RO MODEI CONTROL REG SEQUENCER REG LINEPAT REG registers following the 2 2 6 82 2 7 82 2 8 82 2 9 822 11 3 4 Readout 3 4 4 Signal protocol After JT AG registers have been loaded the readout of Mimosa22 can be initialized with following signal protocol e Start readout clock CK100M e Set SPEAK signal to 0 e Set START signal to 1 during 500 ns minimum The internal reset is created after 15 ns on the rising edge of START After this reset CIKSOM input clock with a 1 2 ratio and CkDiv16 input clock with 1 16 ratio are generated e The readout controller starts at the first falling edge of CkDiv16 after START set to 0 Signal markers allow the readout monitoring and the data outputs analogue and digital sampling gt CLKA and CLKD are running when readout controller starts CLKA is signal which is generated by logic OR between Read and Calib signals And CLKD corresponds to CIK50M gt When SPEAK signal is active markers of synchronisation for analogue and digital outputs are generated on MK CLK A and MK CLK D pads November 2007 Mimosa22 User Manual V 1 0 14 Mimosa22 3 4 2 Successive frames and resynchronisation Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the START token again Previous fram
10. User Manual V 1 0 9 Mimosa22 The purpose of this array is to describe the internal signals which can be checked using 2 test pads Tst1 Pad and tst2Pad The internal signals can be selected with SelPad1 and SelPad2 bits SelPad1 Tst1Pad Purpose SelPad2 Tst2Pad Purpose MK Test A Analogue marker is shifted MK Test D Digital marker of 80 ns to MK A signal corresponding to last This signal rises up at the serialized digital data beginning read phase and It depends of falls down at the end of RowMkd selection Calib phase It depends of parameter RowMka selection parameter Mk Rd Analogue marker PwrOns Same signal as PwOn corresponding to Rd phase but shifted of 16 main of readout pixel It depends clock of RowMka selection parameter Mk Calib Analogue marker Activate power corresponding to Calib supply for pixel phase of readout pixel It depends of RowMka selection parameter EBENE LU CkDiv16 signal is devised SlcRowInt Connect pixel output by 2 to common column NES A Analogue marker Set reference voltage corresponding to readout for clamping pixel sequence It depends of RowMka selection parameter Set reference voltage for 5 RstDiode Set reference voltage clamping for diode Latch Latch state of the Sample before discriminator clamping 7 CkDiv16 Main Clock is devised by 16 7 Calib Sample after clamping 2 2 9 SEQUENCER_REG Register The SEQUENCER_REG registers are 128 bits large this register contains all
11. Grp Data Ana Row 575 1 Er St Row pl E gt RsT 0 Fa Clampingp Data Ana Row 0 gt f E gt Latch E MK CLK A Ee CLKA 0 0 1 d 0 0 0 0 0 0 1 FA Pan Dol E 0 0 0 1 0 0 0 0 0 LE MK CLK D D Last bit frame of serialization 40 20 10 08 04 02 En LineMarker O MODE SPEAK 1 30 500ns i30 600ns En LineMarker MODE SPEAK SPEAK CkL CkDivi amp Par On 575 Siet Row int 75 Rst 575 Clamping 575 lt Data Discri Row 574 I lt Data Discri Row 575 Data Discri Row 0 l l 90 700ns 90 900ns Data Ana Row O St Row Into Rst 0 Clamping O Data Ana Row 5 Eo os lt r e iF MK_CLI_A MK_CLK_D MuxL 7 0 CLKD CLKA 0 1 1 d H H 0 0 0 Pwr Del o H 0 0 1 0 0 o o 1 1 0 Data Discri Row 574 l M A AAAI I First bit frame 1 IE or E or tZ rp see Peo Kao Xeo Yao Yos Yos yoz Yor Yeq Mao Veo Yao Yos Yoa Xoz Yo ten Yao Yeo Yao Yos Yos Yo Yor Yeo _ IWRERENHEERERERHNE A Z TS ann POUL RERWREREREN Data Discri Row 575 I l l l Data Discri Row O Start CLK ANA in First row frame Figure 5 Figure 5 shows the last row readout followed by the first row of the next frame when En LineMarker is set to 0 For Figure
12. Process Design Kit V3 70 has been provided by CMP The design tools are CADENCE DFII 5 1 with DIVA ASSURA CALIBRE rules The chip has been submitted in a Multi Chip Run via CMP the 26 October 2007 in the run 4 A35C5 4 The sensor matrix is composed by 576 x 136 pixels of 18 4 um pitch which are based on self biased diode and the reset diode architectures The chip consists of seventeen sub array of pixels 128 column level discriminators for signal sparsification a fully programmable digital sequencer and output multiplexers for binary outputs The operation sequence of Mimosa22 is 1 Power On Reset or Reset on RstB pad active at low level 2 Setup of the chip with programmable registers accessed via an embedded slow control Jtag interface e Load the DACs which bias the analogue blocks e If necessary load the ReadOut Register with a specific configuration The default setup on power on reset allows a normal readout once the biases have been set 3 Readout of the chip e The chip is driven by a 100 MHz clock The readout starts when the input START token has its rising signal sampled by the internal 100 MHz clock e Few digital markers are available for the control of the readout process e Pixels are sequentially read out in a specific order explained later in the document e Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the START token again
13. aa IUa EA MES 10 2 2 10 DIS DISCRI E t 12 22011 LINEPAT REG Resistor t2gccccscedetscenecttcacactsiacdoes iced siiani 12 3 R nnins e a a aa ie aa e Ea a iE 13 3 1 PATUCE TESEL E 13 3 2 Erasme MNOS PP n 13 3 3 Setting the Readout Configuration Register 14 De C v Tm 14 3 4 1 Signal ee eissis 14 3 4 2 Successive frames and resynchronisation sccecesecessseceeseecesseeeeeeeeeeseeeees 15 3 5 Analogue and digital Data Format aeo pedido pap apum pU SEP tO eI AR VIDA T MiEE 15 3 5 1 Normal mode data format econtra EAR e FDA e M d ae ai eid pud DRIN EMEN 15 3 5 2 Eeler 16 3 0 Mimosa22 Chron nograms EE 16 3 6 1 Normal ero m GN 16 3 6 2 Readout Sync salle do Dr iE PUPA ee 17 3 6 3 Main Signal Speciications issccscaccsscecccsssdscactssusadesaatocedsaahssensibydacdasubsccvanceeedbens 20 4 Pad o c 20 4 1 Mimosa22 Pad Ring and Floor Plan View eerte entretiens 21 4 2 RE 22 November 2007 Mimosa22 User Manual V 1 0 Mimosa22 1 Introduction Mimosa22 is intermediate prototype before the final sensor chip of EUDET JRAI beam telescope for the ILC vertex detector studies Its architecture is based on the Mimosal6 which is a fast binary readout Monolithic Active Pixel Sensor MAPS Mimosa22 has been designed in AMSC35B401 CMOS Opto 0 35 um This CMOS Opto process has 4 metal layers and 2 poly layers and uses 14 um epitaxial wafers The
14. e Current frame i Next frame i Last frame gt gt lt gt LastRow SPEAK j i i i LastRow LastRow MK_SYNC_CLK_A MODE SPEAK 0 Al d UU r com MK SYNC CLK E MODE SPEAK70 LastRow LastCo 7 5 TIRE M Reac Calib CIk5cM v ue Disable MK SYNC CLK A and MK SYNC CLK D MK SYNC CLK E MODE SPEAK7 i d i i 1 MK SYNC CLK A j i T SPEAK signal allows to generate markers signals which are used by DAQ When SPEAK signal is set to 1 during the current frame analogue marker appears on MK SYNC CLK A pad and digital marker appears on MK SYNC CLK D pad during next frame In the MODE SPEAK 0 see Figure 5 a the MK SYNC CLK A marker corresponds to last row of the frame and the MK SYNC CLK D marker corresponds to last bit frame In the MODE SPEAK I see Figure 5 b MK SYNC CLK A signal corresponds to a sampling clock for analogue outputs data same as CLKA which starts at the first row of frame MK SYNC CLK D signal corresponds to readout clock for digital data same as CLKD which starts at the first bit frame When SPEAK signal is set to 0 MK SYNC CLK A and MK SYNC CLK D are set to 0 3 5 Analogue and digital Data Format Two Types of signal can be generated on analogue outputs e Normal pixel signal e Test signal In concern to digital outputs two ty
15. gue Ground periphery amp core 68 vdda Core logic and periphery cells supply _ AVDD3ALLP Analogue Supplies periphery amp core 69 PWRSWBIAS Analog I O pad 0 Q serial APRIOP___ Discri Power Pulse Voltage Bias 80 vdda Joe logic and periphery cells supply AVDD3ALLP Analogue Supplies periphery amp core 83 IDIS1 Analog I O pad 0 Q serial APRIOP DAC output Discriminator Bias 1 84 vdda Core logic and periphery cells supply AVDD3ALLP Analogue Supplies periphery amp core 85 VTEST2 Analog I O pad 0 Q serial APRIOP DAC output VTEST2 86 VTESTI Analog T O pad 0 Q serial APRIOP DAC output VTESTI 89 vdda Core logic and periphery cells supply AVDD3ALLP Analogue Supplies periphery amp core 90 VKIMO Analog I O pad 0 Q serial APRIOP A reference voltage from DAC output Analog I O pad 0 serial APRIOP POLY Gate voltage for Andrei RadTol Pix Core logic and periphery cells gnd AGND3ALLP Analogue Ground periphery amp core November 2007 Mimosa22 User Manual V 1 0 24 Mimosa22 Pad ring segment 1 P DA Pad Name IPad General Function PadType Functionforthechip 140 TMS CMOS Input Buffer Pull Up ICUP JTAG Control Signal 146 vdd Output buffer supply VDD30P Output buffer supply Pad General Function 163 165 166 Pad General Function PadType Function for the chip 167 Core logic and periphery cells supply VDD3ALLP Suppl
16. hronization Purpose Basic configuration value Code 127 0 LinePatReg Emulate discriminators rows AAFFFFFF AAAAAAAA 55555555 22FFFFl1 1 1 Example of pattern used in simulation November 2007 Mimosa22 User Manual V 1 0 12 Mimosa22 3 Running Mimosa22 The following steps describe how to operate Mimosa22 3 1 After reset On RstB active low signal All BIAS registers are set to the default value i e 0 DIS DISC is set to 0 i e all columns are selected RO MODEO is set to 0 RO_MODE is set to 0 CONTROL REG is set to 0 SEQUENCER REG is set to 0 LINEPAT REG is set to O JTAG state machine is in the Test Logic Reset state JTAG ID CODE instruction is selected Then the bias register has to be loaded The same for the RO MODEO RO MODEI CONTROL REG SEQUENCER REG LINEPAT REG and DIS DISC registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode 3 2 Biasing Mimosa22 The BIAS DAC register has to be loaded before operating Mimosa22 The 15 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 uA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias
17. ies periphery amp core for DAC 168 gnd Core logic and periphery cells gnd GND3ALLP Ground periphery amp core for DAC November 2007 Mimosa22 User Manual V 1 0 25 Mimosa22 Pad ring segment 1 P D6 Pad Name PadGeneral Function PadType Functionforthechip 171 CkRdLn LVDS In Full Custom Readout Clock Signal Pad ring segment P T1 Pad 94 to 112 and Pad ring segment P T2 Pad 113 to 124 are used only for internal test November 2007 Mimosa22 User Manual V 1 0 26
18. internal START by accessing JTAG Start bit JTAG Start signal is realized by three JT AG access First step this bit is set to 0 second step it is set to 1 and at last it is set to 0 November 2007 Mimosa22 User Manual V 1 0 8 Mimosa22 2 2 7 RO MODEF1 Register The RO MODEI registers are 8 bits large they allow selecting specific analogue mode of the chip E NUES Reserved Nov 5 N03 a Ne Dee 5 JN JResmedNoUsd TP 4 DisBufRef Disabletheinternalreferene Select Internal Buffer 3 JN Reserved NotUsed TP 2 En AOP Disc EnablethePowerpulse Amplifier 0 Normalmode 1 En PulsDiscri Enable the discri power pulse mode 0 Normalmode LO En TstDis Enable the discri test mode 0 Normal mode 2 2 8 CONTROL_REG Register The CONTROL_REG registers are 40 bits large they allow setting parameters of the readout controller Basic configuration value Coder EE EREECHEN 3230 Sela SecionbiofTeF 0 MK TstDsemi 29 20 RowMkLast Row number of the frame It depends of Normal mode the number of row readout mode matrix is 576 When the En_HalfMatrx mode is active the value is 0x013F otherwise 0x023F When the En_LineMarker mode is active add two rows at the end of matrix marker MK_Test_D matrix during the readout EN dd marker MK Test A of matrix during the readout November 2007 Mimosa22
19. ld of the discriminator Voltages can be adjustable via 2 DACS or can be provided via 2 pads November 2007 Mimosa22 User Manual V 1 0 15 Mimosa22 Output pad Digital output Msb Lsb Dout lt 12 gt Col 103 Col 102 Col 101 Col 100 Col 99 Col 98 Col 97 Col 96 Col 63 Col 62 Col 61 Col 60 Col 59 Col 58 Col 57 Col 56 Dout lt 1 gt CoL15 Col 14 CoL13 Col 12 Col 11 Col 10 Col9 CoL8 Dout 0 CoL7 Col6 Col5 Cold Col3 Col 2 Coll CoL0 3 5 2 Test mode data format This test readout mode allows obtain the transfer function of discriminator and calibrate the pixel readout chain During the test mode the pixel matrix is not connected to discriminators and output analogue buffers Instead of this two test levels Vtstl Vtst2 are connected to discriminator inputs to emulate pixel signal The Vtstl voltage is applied to the positive discriminator input during the Read phase and the Vtst2 voltage is applied during the Calib phase Voltages can be adjustable via 2 DACS or can be provided via 2 pads The difference voltage Vtstl Vtst2 corresponds to the pixel output signal 3 6 Mimosa22 Chronograms The following chronograms describe typical access to the chip Reset JTAG download sequence and then the readout 3 6 1 Normal Readout Figure 1 show the beginning of typical data readout mode After Reset and JTAG setting one can see the initialisation phase of the readout of the first pixel row November 2007 Mimosa22 User Manual V 1
20. nnnnanhnnanan nannnannaannnnnnnannnnn CkDiv16 Se Gr 35 Pur OnE7S c e EE n s r M aaa C C C Sa Se a ee Set Bo DEZ irst Row adc i econd Row add Rst 575 Clamp S75 Sk GI Fa Op Sict Row up RST 0 Clamping 0 Read Calib Latch CLKD CLKA MK CLK A MK CLK D fi OutL 7 0 Weu 1 y i a eee Last bit frame i of serialization Last Row of frame E E We ET Keo Lon Log X10 Kos 04 Yo2 X01 Leg Lag Log 1008 04 Yoo pi Leg ad Lon 10 Yos 04 02 Yo1 Xeo Yso Log V10 Yos Xos J02Y01 Yen Lag X20 10 Kos fos Yoo X01 Ke e ee be e e ee e e e e e bb Rn bn ra c LinePatReg e LinePatReg e Data Discri Row 0 j I Data Discri Row 575 During Read phase Vtest1 is selected in analogue outputs And during Calib phase Vtest2 is selected Figure 4 Figure 4 shows the last row readout followed by the first row of the next frame when En LineMarker is set to 1 and MODE SPEAK is set to 0 These options are set via the RO MODEO register November 2007 Mimosa22 User Manual V 1 0 18 Mimosa22 M En LineMarker 0 MODE SPEAK 0 273 600ns Name v 273 700ns 273 800ns 273 900ns e We En LineMarker iis MODE SPEAK WI SPEAK Lg o p CkDiv16 pE Sie_Gr 35 E Pwr On 575 d i Set Row int 575 Ex papa pr Clamp 75 Lt Sk
21. parameters to generate readout pixel and discriminator sequence Basic configuration value Code Signal Name common column WE OO diode clamping 79 64 DataCalib Sample after clamping 3C00 63 48 DataRdDsc Sample before clamping 001C 47 32 DataLatch Latch state of the 6000 1 Latch discriminator pixel November 2007 Mimosa22 User Manual V 1 0 10 Mimosa22 1 Example Generation of Latch Signal AME Dg LO Ig Li 14 DX Bg L2chs Li L4 CES 3 Latch mE Lsb Msb 15 7 DataLatch 0 0 e Related timing with fcx 2100 MHz Read Calib Latch signals are used by the column readout circuitry Baseline v FA Cursor Baseline ss 160ns Name J CkL B Sict Row int FE Pat L 4HW Clamp Lr eg T Calo gt Latch For Sub arrays S6 S9 S11 and S14 the Rst signal is not used for pixel e This is readout sequence of the pixel and discriminator for 2 successive rows of matrix In the wave form the indexation of internal signal vectors is reversed compared with the Mimosa22 functional view for example the signal Pwr On 575 corresponds to the row at the top of matrix Cursc PID 02 900ns 03 000ns i 03 100ns 103 200ns CRL gt Pwr On 575 gt Set Row Int 575 1 ra RetS75 geb RE e EE i F2 Pur On 74 gt Set Row
22. pes of signal can be generated e Digitalization pixel signal by discriminator e Test pattern read to LINEPAT_REG register 3 5 1 Normal mode data format The chip has columns parallel process readout The first 128 columns are connected to discriminators multiplexed onto 16 outputs The last 8 columns of 136 are connected to output analogue buffers Their analogue outputs can be observed directly on the output pads The digital part includes three blocks One is JTAG controller interface which allows configure the internal registers used to readout chip The second circuit generates the patterns necessary for addressing resetting and double sampling of the signals in pixels in a column parallel way The rows are selected sequentially using a multiplexer every 16 clock cycles The last circuit realizes a temporal multiplexing of the binary outputs at a frequency value half that of the main clock frequency For Mimosa22 Col 127 is at the left of matrix and Col 0 is at the right The row at the top of matrix is read out first 16 multiplexers 8 1 serialize the digital row data onto 16 output pads The bit which is first selected in the serial 8 bits stream corresponds to the Msb bit see the table below Data are serialized on falling edge clock of CLKD The Vrefl voltage is applied to the negative discriminator input during the read phase and the Vref2 voltage is applied during the Calib phase The difference voltage Vrefl Vref2 set the thresho
23. ring the access to the register An image of the value of each DAC can be measured on its corresponding test pad November 2007 Mimosa22 User Manual V 1 0 7 Mimosa22 range Name Test Pad 3932 Dat ID2PWRS jDiscriminatorbias2 modelowconsp 3124 DAC3 IDIPWRS jDiscriminatrbiasl modelowconsp DACO ICLPDISC Discriminator Clamping bias DISCLP 2 2 6 RO MODEO Register The RO MODEO registers are 8 bits large they allow the user to select specific digital mode of the chip Bit Basic configuration value IT ee ae NN VTEST shift register selected DisLVDS Disable LVDS and active clock CMOS 0 LVDS selected 4 En LineMarker Add two rows at the end of matrix for a chip Readout Normal mode The LINEPAT REG register is selected to emulate discriminators outputs For analogue outputs the 2 Test Levels VTEST1 and VTEST2 are selected which emulate a pixel output 3 MODE SPEAK Select Marker signal or Readout Clock for digital and 0 Marker signal active analogue data MK_CLKA and MK CLKD pads 2 Pattern Only Test Mode Select LINEPAT REG to emulate Normal mode discriminators outputs 1 En ExtStart Enable external START input synchronisation 1 O Normal mode o JTAG Start Enable Jtag START input synchronisation Qlol 4 1 The minimum wide of asynchronous external START is 500 ns and this signal is active at high level 2 When En ExtStart is disabled it s possible to generate
24. struction BIAS GEN OF BIAS DAC User instruction 1 Instruction codes implemented but not the corresponding registers To be fixed in the next version 2 2 JTAG Register Set JT AG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first INSTRUCTIONREG 5 R W____ Instruction Register i O DEV D 33 ROny TI BYPASS II ROny TI BSR do RW G BIAS DAC 120 RW____ Previous value shifted out during write RO MODEO Is RAW__ Previous value shifted out during write RO MODEL Is RAW_ Previous value shifted out during write CONTROL_REG 40 RW__ Previous value shifted out during write SEQUENCER_REG 128 R W____ Previous value shifted out during write DIS_DISCRI 128 R W____ Previous value shifted out during write LINEPAT_REG 128 RW__ Previous value shifted out during write LNULNU2 NU9 o Not implemented Forfutureuse November 2007 Mimosa22 User Manual V 1 0 6 Mimosa22 2 2 1 Instruction Register The Instruction register is a part of the Test Access Port Controller defined by the IEEE 1149 1 standard The Instruction register of Mimosa22 is 5 bits long On reset it is set with the ID CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction x x
25. v dp guit pat POMA Er ER PD2 vidit 31 Mimosa22 User Manual PDI V 1 0 Mimosa22 4 2 Pad List The bonding of the power supply pads specified in red colour is mandatory Pad ring segment 1 P DI Pad Name PadGeneral Function PadType Functionforthechip 6 Dou 12 Tri State Output Buffer 2 m BT2P Digital Output ch 103 96 S8 Dou ll Tri State Output Buffer 2 mA BT2P Digital Output ch 05 88 9 vdd Output buffer supply VDD3OP Output buffer supply 17 gnd Output buffer ground GND30P Output buffer ground Tri State Output Buffer 2 mA BT2P Digital Output ch 55 48 Core logic and periphery cells gnd GND3RP Digital ground periphery amp core 19 gnd Tri State Output Buffer 2 mA BT2P Digital Output ch 47 40 Core logic and periphery cells supply Digital supply periphery amp core Pad ring segment 1 P D2 Pad Name Pad General Function PadType Function for the chip vdd latch Core logic and periphery cells supply AVDD3ALLP Supplies periphery amp core only for LATCH gnd Core logic and periphery cells ground AGND3ALLP Ground periphery amp core only for LATCH November 2007 Mimosa22 User Manual V 1 0 22 Mimosa22 Pad ring segment 1 P A1 Pad Name Pad General Function PadType Functionforthechip Core logic and periphery cells supply Analogue Supplies peripher
26. ved the sequence of sequencer reg is actived for state machine Readout Controller during the low level period of SLoad signal Figure 2 Figure 2 zoom on the readout start After a latency of 5 CkDiv16 cycles readout of matrix starts November 2007 Mimosa22 User Manual V 1 0 17 Mimosa22 EP Curse Name Cursor v 3 200ns g9 300ns 83 400ns 83 50Cns 89 600ns Sam Pwr On 75 Set Row Int 575 Rst 575 Clamping S75 Fa On 574 Set Row Int 574 Rst 574 Clamping 574 Data Ana Row 0 Data Ana Row 1 A Il A t SyncMux D 28 MuxL 7 0 H E CLK D 02 l Data Digcri Row Sample before clamping of Row 0 Read oes Fog p nj p w iod P od je d el d does d ssl dmm I IRI ar RI SAA RI SI Sample after clamping of EXPE Tl SIS LEI Zu Doutet5s Row 0 Calib IS 3 Bl SI SI 1 Bl Si ase ese OL OL Qu Ex ep s l p 2 E wt ak d l Lb 2 Metti at A Ape d l pode cg w n l Hee ae cup cogo ode s II elle al el al el el lb o zl sl cb Dodbe II 8I GI amp amp Si GI SI ol ol gl OI gol ol e EIERE EC ee ee l To ao Et up ege cul Figure 3 Figure 3 shows the first row of the readout matrix and the beginning of digital data serialization sequence En LineMarker 1 MODE SPEAK 0 Ki Cursor Name v C e73 700ns ie73 000ns 273 900ns 274 000ns 274 100ns 274 200ns 274 300ns 274 400ns i SPEAK hnnnnnnnnnnnnnnnnnnnnnnannn
27. y amp core Core logic and periphery cells gnd Analogue Ground periphery amp core Core logic and periphery cells gnd Analogue Ground periphery amp core Clamping voltage for pixel array Core logic and periphery cells supply Analogue Supplies periphery amp core Core logic and periphery cells supply Analogue Supplies periphery amp core Core logic and periphery cells gnd Analogue Ground periphery amp core External injection of Vtest2 Detection diode supply Dapnia Design External injection of Vtest1 44 Aoc0 DIRECTPAD Analogue output 46 Aocl DIRECTPAD Analogue output 48 Ao 22 JDIRECTPAD Analogue output 50 Aout lt 3 gt DIRECTPAD Analogue output 52 Aouts4 gt 1 1 1 DIRECTPAD Analogue output S4 Aoucs 1 DIRECTPAD Analogue output S lAouc DIRECTPAD Analogue output S8 Aou 7 DIRECTPAD Analogue output 60 VCLPDIS JDIRECTPAD External injection of Discri clamping UV DIRECTPAD External injection of Discri Refl 62 Vre2 DIRECTPAD External injection of Discri Ref2 gnd Supplies periphery amp core only for DAC November 2007 Mimosa22 User Manual V 1 0 23 Mimosa22 Pad Name Pad General Function PadType Functonforthechip G6 gnd Core logic and periphery cells gnd AGNDGALLP Analo
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