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DM6910 User`s Manual

1. 16 3 0 F2 7 0 6 FOI Ds 10 Clear jumper selectable interrupt Set Port 0 1 digital I O clear mode Clear Port 0 1 digital interrupt Set Port 2 3 digital I O clear mode Clear Port 2 3 digital interrupt Set Port 4 5 digital I O clear mode Clear Port 4 5 digital interrupt Send EOI command to 8259 Your code goes here Do not use any DOS functions Cc Po Gui rt BaseAddress 7 Po ec Po Port BaseAddress 16 rt BaseAddress 3 Port BaseAddress Port BaseAddress rt BaseAddress 11 c Port BaseAddress Po end rt 20 20 0 2 0 6 Oo 0 10 Clear jumper selectable interrupt Set Port 0 1 digital I O clear mode Clear Port 0 1 digital interrupt Set Port 2 3 digital I O clear mode Clear Port 2 3 digital interrupt Set Port 4 5 digital I O clear mode Clear Port 4 5 digital interrupt Send EOI command to 8259 7 6 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the
2. 11 IRQ Source Register Bits 0 and 1 Select the clear mode initiated by a read write operation at BA 10 or the control register you talk to at BA 10 Port 4 Direction Port 5 Direction or Port 4 5 EPLD IRQ Select Register Bit 2 IRQ Polarity sets the edge of the digital input signal that generates the interrupt Bit 3 Enables EPLD strobe input used with JP5 header Bit 4 Disables enables digital interrupts The IRQ channel is determined by the jumper setting on JP1 and JP2 Bit 5 Sets the clock rate at which the digital lines are sampled when in a digital interrupt mode Available clock sources are the 8 MHz system clock and the output of the 8254 Counter 16 bit programmable clock When a digital input line changes state it must stay at the new state for two edges of the clock pulse 62 5 nanoseconds when using the 8 MHz clock before it is recognized and before an interrupt can be generated This feature eliminates noise glitches that can cause a false state change on an input line and generate an unwanted interrupt This feature is detailed in Chapter 5 Bit 6 Read only Strobe status Bit 7 Read only digital IRQ status 4 9 BA 12 8254 Timer Counter 0 Read Write This address is used to read write timer counter 0 A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 13 8254 Timer Counter 1 Read Wri
3. IMR is programmed through port 21H sas os a ae as as as a oso For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOD Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H 7 4 What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DM6910 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was i
4. and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above 4 13 4 14 CHAPTER 5 DIGITAL VO This chapter explains the bit programmable digital I O circuitry on the DM6910 5 1 5 2 The DM6910 has 48 buffered bit programmable TTL CMOS digital I O lines available for digital control applications These lines are grouped in six 8 bit ports and can be independently programmed as input or output Bit Programmable Digital I O The eight Port 0 Port 1 Port 2 Port 3 Port 4 and Port 5 digital lines are individually set for input or output by writing to the respective port Direction Registers at BA 2 BA 6 and BA 10 The input lines are read and the output lines are written at BA 0 BA 1 BA 4 BA 5 BA 8 and BA 9 Direction Register zm o7 0s os a os 02 bs vc i So PX 7 X 6 X2 PX 1 Digital Interrupts Each EPLD chip contains the digital I O circuitry for two ports or 16 bit programmable lines There are three EPLDs Port 0 1 Port 2 3 and Port 4 5 One line on each chip can be programmed as a digital interrupt by program ming the IRQ select register with the digital line to be monitored selecting an IRQ channel on JP1 or JP2 and setting the IRQ enable bit high in the Control Register If for example you wanted to use Por
5. 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely 6 3 Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again Appendix C provides the 8254 data sheet 6 4 CHAPTER 7 INTERRUPTS Thischapterexplains JP4 jumper selectable interrupts digital interrupts and basic i
6. 1 2 2 Module Installation Keep the module in its antistatic bag until you are ready to install it in your cpuModule or other PC 104 based system When removing it from the bag hold the module at the edges and do not touch the components or connectors Before installing the module in your system check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable module operation and erratic response The DM6910 comes with a stackthrough bus connector The stackthrough connector lets you stack another module on top of your DM6910 To install the module follow the procedures described in the computer manual and the steps below 1 2 3 Turn OFF the power to your system Touch a metal rack to discharge any static buildup and then remove the module from its antistatic bag Select the appropriate standoffs for your application to secure the module when you install it in your system two sizes are included with the module Holding the module by its edges orient it so that the CNI bus connector s pin 1 lines up with pin 1 of the expansion connector onto which you are installing the module After carefully positioning the module so that the pins are lined up and resting on the expansion connector gently and evenly press down on the modul
7. 7 and 11 This scheme is easily understood once you review the register descriptions on the following pages The base address designated as BA can be selected using DIP switch SW1 located on the edge of the module as described in Chapter 1 Module Settings This switch can be accessed without removing the module from the stack The following sections describe the register contents of each address used in the I O map Table 4 1 DM6910 I O Map Address Register Description Read Function Decimal Digital I O Port O Read Port 0 digital input lines Program Port 0 digital output lines BA 0 Digital 1 O Port 1 Read Port 1 digital input lines Program Port 1 digital output lines BA 1 Clear digital IRQ status flag read Port Clear digital chip program Port 0 Clear IRQ Program Port O direction Port 1 direction or IRQ direction Port 1 direction or IRQ Direction amp IRQ Source source dependent on BA 3 source dependent on BA 3 BA 2 Read Digital IRQ Status Set Digital Control Register Read digital interrupt status word Program digital control register BA 3 Digital I O Port 2 Read Port 2 digital input lines Program Port 2 digital output lines BA 4 Digital I O Port 3 Read Port 3 digital input lines Program Port 3 digital output lines BA 5 Clear digital IRQ status flag read Port Clear digital chip program Port 2 Clear IRQ Program Port 2 direction Port 3 direction or IRQ direction Port 3 direction or IRQ Direction amp IRQ Sour
8. Interrupt Vector 7 7 Common Interrupt Mistakes ade 7 7 APPENDIX A DM6910 SPECIFICATIONS 20us0000s2000220002000000000020000220000000000000 seen s seta ss ense sena A 1 APPENDIX B CONNECTOR PIN ASSIGNMENTS 220u000000000020000200002200020000000000 sense 000000000000 B 1 APPENDIX C COMPONENT DATA SHEETS 2202200000000000000000002200020000200000000000000 0200000000000 C 1 APPENDIX D WARRANTY ee eeeee ee ense etta senta se tn sesto osse tasse ots tote etos s sense seta sees sets e etos oops vesers D 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 1 3 1 3 2 6 1 7 1 List of Illustrations Module Layout Showing Factory Configured Settings sse 1 4 Interrupt Channel Select Jumpers JP1 and JP2 sse eene nennen 1 5 Pulling Down the Interrupt Request Lines eese ener netten nnne 1 5 8254 Clock and Gate Sources Jumpers IP 1 6 8254 Circuit Diagraim eae DR ede e e eem NM 1 6 Strobe Input Enable Jumper RN sees Ire ag raa ues 1 7 Interrupt Source Select Jumper JPA osien aa ane o r a E 1 7 Base Address Switch SW scu EELER 1 8 Port 0 Pull up Pull down Resistor Connections IPo nennen 1 9 CNS HCH Connector Pin Assignments iii ini in ged 2 4 DM6910 Block Diagram nee eee ede iiti e e eie des dee 3 3 Timer Counter Circuit Block Diagram sesssssssssseeseeeeneeneeene eren ennemi 3 4 8254 Timer Counter Circuit Block Diag
9. Mode Read Write sese 4 5 BA 4 Digital VO Port 2 Read Write AA 4 6 BA 5 Digital I O Port 3 Read Wiite eet ect EL pere hls detain ui 4 6 BA 6 Clear IRQ Program Port 0 Port 1 Direction IRQ Source Registers Read Write 4 6 BA 7 Read Digital I O Status Program Digital Mode Read Write sss 4 7 BA 8 Digital VO Port 4 Read Write A 4 8 BA 9 Digital VO Port HE OH 4 8 BA 10 Clear IRQ Program Port 0 Port 1 Direction IRQ Source Registers Read Write 4 8 BA 11 Read Digital I O Status Program Digital Mode Read Write sse 4 9 BA 12 8254 Timer Counter 0 Read Write esses eene nnne 4 10 BA 13 8254 Timer Counte r Read Witt iia I OH ERR eie 4 10 BA 14 8254 Timer Counter 2 Read Write ccccccccscccssscessccessesesecessecesseceseccssscessecesseseseeeseecsseeeesnseeesaees 4 10 BA 15 8254 Timer Counter Control Word Write Only sse 4 10 BA 16 Clear IRQ IRQ Enable ReadiWrte eene nnne 4 10 R ck TRO Status Read Online 4 11 BAF 182 Reserved EE EEN 4 11 BA 19 Reserved EE 4 11 Programming re D Meedecher tdo 4 12 Clearing and Setting Bits il a Portada bat 4 12 CHAPTER 5 DIGITAL VO E 5 1 Bit Programmable Digital VO iere 2 2a er dees deed bes e ede 5 3 Digital Intett pts 2 rr e EES Pe ere dte Petite 5 3 Resetting the Digital Crew ee r
10. and off These motors turn on when the digital lines controlling them are high By pulling these lines down you can ensure that when the data acquisition system is first turned on the motors will not switch on before the port is initialized Pull up pull down resistors have been factory installed on the module and jumpers have been installed in the pull up position on JP6 through JP11 for all 48 I O lines Each port and bit is labeled on the module JP6 connects to the resistors for Port 0 JP7 connects to the resistors for Port 1 and so on The pins are labeled G for ground on one end and V for 5V on the other end The middle pin is common Figure 1 9 shows JP6 with the factory installed jumpers placed between the common pin middle pin of the three and the V pin For pull downs install the jumper across the common pin middle pin and G pin To disable the pull up pull down resistor remove the jumper V G 0 c 5 1 o 2 U 2 3 4 4 o 5 6 7 Fig 1 9 Port 0 Pull up Pull down Resistor Connections JP6 1 10 CHAPTER 2 MODULE INSTALLATION The DM6910 is easy to install in your cpuModule or other PC 104 based system This chapter tells you step by step how to install and connect the module After you have installed the module and made all of your connections you can turn your system on and run the 6910DIAG board diagnostics program included on your example software disk to verify that your module is working 2
11. called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR 7 5 Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the firs
12. clock rate at which the digital lines are sampled when in a digital interrupt mode Available clock sources are the 8 MHz system clock and the output of the 8254 Counter 16 bit programmable clock When a digital input line changes state it must stay at the new state for two edges of the clock pulse 62 5 nanoseconds when using the 8 MHz clock before it is recognized and before an interrupt can be generated This feature eliminates noise glitches that can cause a false state change on an input line and generate an unwanted interrupt This feature is detailed in Chapter 5 Bit 6 Read only Strobe status Bit 7 Read only digital IRQ status 4 5 BA 4 Digital I O Port 2 Read Write This port transfers the 8 bit Port 2 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Port 2 Direction Register at BA 6 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared D7 D6 D5 Da D3 D2 ol DO P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 BA 5 Digital I O Port 3 Read Write This po
13. disabled Le Connects interrupt source jumpered on JP4 to an AT JP2 interrupt channel no jumper JP4 JP5 JP6 JP7 JP8 JP9 CLKO OSC CLK1 OTO CLK2 0T1 GT2 EG2 JP3 Sets the clock and gate sources for the 8254 timer counter timer counters cascaded Selects one of four interrupt sources for interrupt generation OT2 Enables and connects a strobe input to Port 0 2 and or 4 through the EXT INT line DIS disabled Activates pull up pull down resistors on Port O digital I O All bits pulled up jumpers installed lines between COM amp V Activates pull up pull down resistors on Port 1 digital I O All bits pulled up jumpers installed lines between COM amp V Activates pull up pull down resistors on Port 2 digital I O All bits pulled up jumpers installed lines between COM amp V Activates pull up pull down resistors on Port 3 digital I O All bits pulled up jumpers installed lines between COM amp V Activates pull up pull down resistors on Port 4 digital I O All bits pulled up jumpers installed JP10 lines between COM amp V Activates pull up pull down resistors on Port 5 digital I O All bits pulled up jumpers installed JP11 lines between COM amp V Sets the base address 300 hex 768 decimal 220W p e EEES O p ooo y ec Ho sw1 09000 eN U3 i i ur Moo a T om 0 0 o 1 e CH m Hiis gt 0 3 2 Se e
14. ens niii gt GE 6 9 O 3 a les o o mm amp Ch munis 555 Ir z e ii Beet oo oo 1804 Belt lt HIE s M mm uina nnn se iii E m a HE J tunm e qi 2 can WIS gr O mo osc Us si aao SE 4 9 0 gt c u oo oo gt SES Ge el Wu i Fig 1 1 Module Layout Showing Factory Configured Settings JP1 JP2 Interrupt Channel Select Factory Setting Jumper installed on G IRQ Disabled These header connectors shown in Figure 1 2 lets you connect any one of four jumper selectable JP4 interrupt sources and the Advanced Digital Interrupt sources to an interrupt channel IRQ2 through IRQ15 XT channels 2 through 7 are jumpered on JP1 and AT channels 10 through 15 are jumpered on JP2 In AT computers channels 2 and 9 are the same channel To activate a channel you must install a jumper vertically across the desired IRQ channel s pins Only one channel on either JP1 or JP2 should be jumpered at any time Figure 1 2a shows the factory settings This module supports an interrupt sharing mode where the pins labeled G connect a 1 kilohm pull down resistor to the output of a high impedance tri state driver which carries t
15. module should have the G jumper installed The rest should be disconnected Whenever you operate a single module the G jumper should be installed Whenever you operate the module with interrupt sharing disabled the G jumper should be removed ONDARON orn d WO errr ro o Fig 1 2 Interrupt Channel Select Jumpers JP1 and JP2 PROGRAMMABLE INVERT JP4 INTERRUPT SOURCE INTERRUPT REGISTER CLR PORT 0 1 DIGITAL CLK INTERRUPT INTERRUPT REGISTER CLR PORT 2 3 DIGITAL INTERRUPT INTERRUPT REGISTER CLR PORT 4 5 DIGITAL INTERRUPT INTERRUPT REGISTER CLR P di m JP4 IRQ STATUS BA 17 BIT 3 INTERRUPT O JP1 i ING PORT 0 1 DIGITAL IRQ STATUS BA 17 BIT 0 PORT 2 3 DIGITAL IRQ STATUS BA 17 BIT 1 PORT 4 5 DIGITAL IRQ STATUS BA 17 BIT 2 Fig 1 3 Pulling Down the Interrupt Request Lines JP3 8254 Clock and Gate Source Select Factory Settings See Figure 1 4 This header connector shown in Figure 1 4 lets you select the clock sources for the three 8254 16 bit timer counters Figure 1 5 shows a block diagram of the timer counter circuitry to help you in making these connections The clock source for Counter 0 is selected by placing a jumper on one of the two leftmost pairs of pins on the header OSC or ECO OSC is the on board 8 MHz clock and ECO is an external clock source which can be con nected through I O connector CN3 pin 55 Counter 1 has three clock so
16. 2 The DM6910 has two major circuits the digital I O lines and the timer counters Figure 3 1 shows the block diagram of the module This chapter describes the hardware which makes up the major circuits 8 MHz osc 8254 PIT 9 ADDRESS ADDRESS DECODE ET INTERRUPT CONTROL tc 3 X 8 BIT e 3 BYTE m m PROGRAMMABLE z o DIGITAL 110 Z o o i 3 X 8 BIT BIT PROGRAMMABLE EVENT MATCH DIGITAL I O DATA CONTROL 5 VOLTS CONTROL K Fig 3 1 DM6910 Block Diagram Digital I O The 48 bit programmable digital I O lines can be used to transfer data between the computer and external devices Six ports Ports 0 1 2 3 4 and 5 each provide eight bit programmable lines which can be independently set for input or output The digital I O circuitry is contained in three EPLD chips on the module 16 lines per chip grouped as follows Port 0 1 EPLD Port 2 3 EPLD and Port 4 5 EPLD One line per chip can be used to generate a digital interrupt Chapter 5 details digital I O operations and Chapter 7 explains digital interrupts Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Figure 3 2 shows the timer counter circuitry Each 16 bit timer counter has two inputs CLK in and GATE in and one output timer counter OUT Each can be programmed as binary or BCD down counters by writing the appropriate data to the command wo
17. 6910 Characteristics Typical 25 C Interface Switch selectable base address UO mapped Jumper selectable interrupts Digital UO Number of lines 0 0 2 ceccececececeeeeeeeeecceeeeeeeeeeeesneeseeecneeseeeeeeeeeesaaes 48 bit programmable ISOUICO EE EE 12 mA A A add AU 24 mA Time r Gounters iii dc a drid CMOS 82C54 Three 16 bit down counters 6 programmable operating modes Counter input source sssesssee External clock 8 MHz max or on board 8 MHz clock Counter outputs sssene Available externally used as PC interrupts Counter gate Source c ooooocoinccccccccocococnconcconnananncanccnn nano External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 5 volts 12 volts ground Power Requirements 5V 238 mA 1 18W typical Connectors CN3 68 pin right angle connector Mating Connector Manufacturer and Part 3M 82068 6000 Environmental Operating temperature ssssssssseseseeeeeeeneeen nennen nennen 0 to 70 C Storage temperature sssssssssssseee eene 40 to 85 C H mlidity esor e lp ia 0 to 90 non condensing Size 3 55 L x 3 775 W x 0 6 H 90mm x 96mm x 15mm A 3 A 4 APPENDIX B CONNECTOR PIN ASSIGNMENTS B 2 CN3 Connector P4 060 Ps 7 P4 6 OO P5 6 P4 5 D 5 6 P5 5 P44 7 P5 4 pas P5 3 P4 2 c P5 2 A Seil P4 1 P5 1 x pao ado P5 0 gt PIN 2 DIGITAL GND M
18. A DIGITAL GND PD P2 7 P3 7 o P26 OO P3 6 gt P2 5 3 P3 5 pc SET P2 4 G9 P3 4 e B P2 3 DG P3 3 PIN 1 SS P2 2 P3 2 E P21 6262 P3 1 E ET P2 0 63 P3 0 DIGITAL GND 5 DIGITAL GND EY Po 7 6 P1 7 gt P0 6 P1 6 pc _ P0 5 P1 5 I P0 4 P1 4 P0 3 P1 3 SET P0 2 P1 2 z Z P0 1 P1 1 ELE P0 0 P1 0 d DIGITAL GND 63663 EXT INT 2 gt gt gt PIN 68 EXT CLK 0 6968 EXT GATE o Tic our o 62689 T c our EXT CLK 1 EXT GATE 1 EXT CLK 2 EXT GATE 2 T C OUT 2 EXT INT 1 5 VOLTS DIGITAL GND 5 VOLTS DIGITAL GND CN3 Mating Connector Part Number Manufacturer 82068 6000 Part Number B 4 C 1 APPENDIX C COMPONENT DATA SHEETS Intel 82C54 Programmable Interval Timer Data Sheet Reprint APPENDIX D WARRANTY D 2 LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before return
19. DM6910 User s Manual e D O Real Time Devices USA Inc Accessing the Analog World Publication No 6910 03 08 00 DM6910 User s Manual Tao REAL TIME DEVICES USA INC Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices USA Inc P O Box 906 State College PA 16804USA Copyright 2000 by Real Time Devices Inc All rights reserved Printed in U S A Table of Contents INIA AAPP s aieas nia En NEE eo RK EEE EEEREN NETRE OS NEENAKE REN Eero i 1 Digital VO ii ini Ink a a a aie i 3 A de tet e teat ee RIPE Ne IU rendi i 3 What Comes With Your Module itte abi nus ade me i 3 Module ACCeSSOFIgS x 45e to es in ol os lira oed idus ieiunia kei i 3 Usig This Manual EE i 3 When You Need Help 23 nore acra ee RC rms i 3 CHAPTER 1 MODULE SETTINGS 5 2 ocior teuer cea etae ee eese eee oe otia a eae esee Genes o ero ca aEo 1 1 Factory Configured Switch and Jumper Settings sssssssssssssseseseeeeeneee eene enne 1 3 JP1 JP2 Interrupt Channel Select Factory Setting Jumper installed on G IRQ Disabled 1 4 JP3 8254 Clock and Gate Source Select Factory Settings See Figure 1 4 1 6 JP5 Strobe Input Enable Factory Setting Disabled sse 1 7 JP4 Interrupt Source Select Factory Setting OT2
20. GES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE D 3 DM6910 User Settings hex decimal
21. P4 4 1000 P5 0 1100 P5 4 0001 P4 1 0101 P4 5 1001 P5 1 1101 P5 5 0010 P4 2 0110 P46 1010 P5 2 1110 P5 6 0011 P4 3 0111 P4 7 1011 P5 3 1111 P5 7 This register programs the bit to be used to generate a digital interrupt for the Port 4 5 EPLD A digital interrupt is generated when the selected bit goes from low to high or high to low depending on the IRQ Polarity bit below If the Strobe input is enabled the strobe signal will generate the interrupt BA 11 Read Digital I O Status Program Digital Mode Read Write Digital IRQ Status 0 no digital interrupt 1 digital interrupt BA 10 Register Select IRQ Polarity Strobe Enable Probe RANE Digital IRQ Enable A D i ig Digital Sample mane Clock Select A read shows you whether a digital interrupt or a strobe has occurred and lets you review the states of the other bits in this register If bit 6 is high then an input strobe has taken place This bit will be reset when the data is read If bit 7 is high then a digital interrupt has taken place This provides the same status information as BA 17 bit 0 Digital Mode Register Reserved Reserved Digital Sample Clock Select 0 8 MHz system clock 1 programmable clock Digital IRQ Enable Strobe Enable 0 disabled 0 disabled 1 enabled 1 enabled BA 10 Register Select IRQ Polarity 00 clear mode 0 rising edge 01 Port 4 Direction Register 1 falling edge 10 Port 5 Direction Register
22. Register Select bit 7 is high then a digital interrupt has taken place This provides the same status information as BA 17 bit 0 Digital Mode Register Reserved Reserved Digital Sample Clock Select Ine Polarity 0 8 MHz system clock 0 rising edge 1 falling edge 1 programmable clock Digital IRQ Enable Strobe Enable 0 disabled 0 disabled 1 enabled 1 enabled Bits 0 and 1 Select the clear mode initiated by a read write operation at BA 6 or the control register you talk to at BA 6 Port 2 Direction Port 3 Direction or Port 2 3 EPLD IRQ Select Register BA 6 Register Select 00 clear mode 01 Port 2 Direction Register 10 Port 3 Direction Register 11 IRQ Source Register Bit 2 IRQ Polarity sets the edge ofthe digital input signal that generates the interrupt Bit 3 Enables EPLD strobe input used with JP5 header Bit 4 Disables enables digital interrupts The IRQ channel is determined by the jumper setting on JP1 and JP2 Bit 5 Sets the clock rate at which the digital lines are sampled when in a digital interrupt mode Available clock sources are the 8 MHz system clock and the output of the 8254 Counter 1 16 bit programmable clock When a digital input line changes state it must stay at the new state for two edges of the clock pulse 62 5 nanoseconds when using the 8 MHz clock before it is recognized and before an interrupt can be generated This feature el
23. at multiple ports can be strobed from the same signal e e SS Ce LALA c c a a Fig 1 6a Strobe Disabled Fig 1 6b Port 0 Strobe Factory Setting Enabled Fig 1 6 Strobe Input Enable Jumper JP5 JP4 Interrupt Source Select Factory Setting OT2 This header connector shown in Figure 1 7 lets you select one of four interrupt sources for interrupt generation These sources are not part of the EPLD digital interrupt circuitry The four sources are EIl external interrupt 1 CN3 64 El external interrupt 2 CN3 54 OTI the output of timer counter 1 and OT2 the output of timer counter 2 To connect an interrupt source place the jumper across the desired set of pins v7 N e E O O EI2 Bar W tdf Fig 1 7 Interrupt Source Select Jumper JP4 SW1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your module is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the module attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the DM6910 has an easily accessible DIP switch SW1 which lets you select any one of 16 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by sett
24. ce source dependent on BA 7 source dependent on BA 7 BA 6 Read Digital IRQ Status Set Digital Control Register Read digital interrupt status word Program digital control register BA 7 Digital I O Port 4 Read Port 4 digital input lines Program Port 4 digital output lines BA 8 Digital I O Port 5 Read Port 5 digital input lines Program Port 5 digital output lines BA 9 Clear digital IRQ status flag read Port Clear digital chip program Port 4 Clear IRQ Program Port 4 direction Port 5 direction or IRQ direction Port 5 direction or IRQ Direction amp IRQ Source source dependent on BA 11 source dependent on BA 11 BA 10 Read Digital IRQ Status Set Digital Control Register Read digital interrupt status word Program digital control register 8254 TC Counter 0 Read value in Counter 0 Load count in Counter 0 BA 12 BA 11 8254 TC Counter 1 Read value in Counter 1 Load count in Counter 1 BA 13 8254 TC Counter 2 Read value in Counter 2 Load count in Counter 2 BA 14 8254 Control Word Program counter mode BA 15 Geseent are Clear IRQ IRQ Enable Clear interrupt line JP4 interrupt sharing BA 16 IRQ Status BA 17 Reserved BA 18 Reserved Reserved BA 19 BA Base Address 4 3 BA 0 Digital I O Port 0 Read Write This port transfers the 8 bit Port 0 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by wr
25. cription of the problem You can also contact us through our E mail address techsupport rtdusa com i 3 CHAPTER 1 MODULE SETTINGS The DM6910 has jumper and switch settings you can change if necessary for your application The module is factory configured as listed in the table and shown on the layout diagram in the beginning of this chapter Should you need to change these settings use these easy to followinstructions before you stack the module with your computer system Also note that by setting the jumpers as desired on header connec tors JP6 through JP11 you can configure each digital I O line to be pulled up or pulled down This procedure is explained at the end of this chapter Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switch on the DM6910 module Fig ure 1 1 shows the module layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of SW1 the base address switch to avoid address contention when you first use your module in your system Table 1 1 Factory Settings Switch Factory Settings Function Controlled Jumpers Installed Connects a JP4 jumper selectable or digital interrupt source to an interrupt channel pulls tri state buffers to Jumper installed on G ground for ground G for multiple interrupt applications buffer interrupt channels
26. dling What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DM6910 can interrupt the processor when a variety of conditions are met By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controll
27. e interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being
28. e to be recognized by the circuit Figure 7 1 shows a diagram of this circuit Selecting the Interrupt Channel The IRQ channel is selected by installing a jumper on header connector JP1 or JP2 across the desired pair of pins as described in Chapter 1 A jumper is also installed across the G pins if you are using the interrupt sharing feature The jumper selectable interrupt source and the digital interrupt sources are OR d together and can use the same interrupt channel To determine which interrupt source has generated an interrupt you must check bits 0 through 3 of the status word read at BA 17 Then service the interrupt that has occurred and clear the interrupt the jumper selectable interrupt is cleared by reading BA 16 and the digital interrupts are cleared by setting bits 1 and 0 in the corre sponding port s Control Register to 0 and performing a read at the Port Direction IRQ Source Register address CLOCK DIGITAL INPUT IRQ OUT Fig 7 1 Digital Interrupt Timing Diagram Interrupt Sharing This module is capable of sharing interrupts with multiple modules This circuit is described in chapter 1 If you are not planning on using shared interrupts or you are not sure that your CPU can support shared interrupts you should disable this sharing circuit by setting bit 2 at BA 16 to a 1 By doing this the board works in normal interrupt mode and is compatible with all CPUs 7 3 Basic Programming For Interrupt Han
29. e until it is secured on the connector NOTE Do not force the module onto the connector If the module does not readily press into place remove it and try again Wiggling the module or exerting too much pressure can result in damage to the DM6910 or to the mating module After the module is installed connect the cable to I O connector CN3 on the module Make sure all connections are secure External I O Connections Figure 2 1 shows I O connector pinout for CN3 Refer to this diagram as you make your I O connections 2 3 Pa7 06 P5 7 P4 6 3 P5 6 P4 5 266 P5 5 P44 DO P5 4 P4 3 69 P5 3 P4 2 6263 P5 2 P41 A P5 1 P4 0 969 P5 0 DIGITAL GND 1268 DIGITAL GND P2 7 P3 7 P2 6 6262 P3 6 P2 5 3 4 P3 5 P2 4 5 e P3 4 P2 3 7 8 P3 3 P2 2 P3 2 P2 1 6962 P3 1 P2 0 6362 P3 0 DIGITAL GND 5 6 DIGITAL GND Po 7 6269 P1 7 P0 6 P1 6 P0 5 P1 5 P0 4 P1 4 P0 3 P1 3 P0 2 P1 2 P0 1 P1 1 P0 0 6962 P1 0 DIGITAL GND 63663 EXT INT 2 EXT cLK 0 6966 EXT GATE 0 Tic ouro 6268 T C our 1 EXT CLK 1 EXT GATE 1 EXT CLK 2 EXT GATE 2 T C OUT 2 EXT INT 1 5 VOLTS DIGITAL GND 5 VOLTS DIGITAL GND Fig 2 1 CN3 I O Connector Pin Assignment Connecting the Digital I O For all digital I O connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is c
30. en write the resulting value to the port In BASIC this is programmed as V_SAVE V_SAVE AND 223 OUT PortAddress V 4 12 To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pascal this is programmed as V_Save V_Save OR 8 Port PortAddress V_Save Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 24 2 and then write the resulting value to the port In C this is programmed as v_save v_save amp 171 outportb port_address v_save To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 22 2 2 and then write the resulting value back to the port In assembly language this is programmed as mov al v_save or al 168 mov dx Po
31. er checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the module 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ and so on Ifa bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The
32. first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the DM5812 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled nterrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for se
33. he interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active Whenever an interrupt request is made the tri state buffer is enabled forcing the output high and generating an interrupt There are four IRQ circuits one for the P14 jumper selectable interrupts and one each for the digital interrupts available at Ports 0 2 and 4 Their outputs are tied together through an OR gate allowing all interrupt sources to share the same IRQ channel To determine which circuit has generated an interrupt on the selected IRQ channel read the status byte I O address location BA 17 and check the status of bits 0 through 3 as described in Chapter 4 After the interrupt has been serviced you must return the IRQ line low disabling the tri state buffer and pulling the output low again This is done by clearing the IRQ for the source which generated the interrupt You also can have two or more modules that share the same IRQ channel You can tell which module issued the interrupt request by monitoring each module s IRQ status bit s If you are not planning on sharing interrupts or if you are not sure that your CPU supports interrupt sharing it is best to disable this feature and use the interrupts in the normal mode This will insure compatibility with all CPUs See chapter 4 for details on disabling the interrupt sharing circuit NOTE When using multiple modules sharing the same interrupt only one
34. igen o diee ee ette ba der 5 3 Strobing Data into Ports 0 1 2 3 and A8 5 3 CHAPTER 6 TIMER COUNTERS cree e eren ee ee esee n seen netta asta se toss tone seen sesta conoce stone etos seen ase 6 1 CHAPTER 7 INTERRUPTS 202000000000000220002000000000000000000002000000000 se tones toss seen seen ccoo setas s ense eene 7 1 JP4 Jumper Selectable Interrupts 2 22 iip ps nte eni E e nee eri aedes 7 3 Digital l tettupts inue tete eeu s ASA e terat ed re tp aan 7 3 Sampling Digital Lines for Change of State 7 3 Selecting the Interrupt Channel reU dete beta iie etes 7 3 Interrupt Sharing ren Des reet meme m tt emm nube diea inus 7 3 Basic Programming For Interrupt Handling eese nennen nnne 7 4 Whatls an TEE 7 4 Interrupt Request Lies iia Sik eel e os ER 7 4 8259 Programmable Interrupt Controller ee eeeeesccsessecseeeeceecsceececsseeecsseesceseesesseesesseesesseesesanseeaeeaeeaeeaees 7 4 Interrupt Mask Register IMR eet cse tre i e ia 7 4 End of Interrupt EOD Commandes a E OEE E R E O RE aia 7 4 What Exactly Happens When an Interrupt Occurs uuuensessessensessennensennensensensensensensenensonsensensensnnensennsennnnn 7 5 Using Interrupts in Your Programs ron nr nn nc nr non nan nee nennen tenere inneren nns 7 5 Writing an Interrupt Service Routine USR 7 5 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector esee 7 7 Restoring the Startup IMR and
35. iminates noise glitches that can cause a false state change on an input line and generate an unwanted interrupt This feature is detailed in Chapter 5 Bit 6 Read only Strobe status Bit 7 Read only digital IRQ status 4 7 BA 8 Digital I O Port 4 Read Write This port transfers the 8 bit Port 4 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Port 4 Direction Register at BA 10 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared D7 D6 D5 D4 D3 D2 D1 DO P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 BA 9 Digital I O Port 5 Read Write This port transfers the 8 bit Port 5 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Port 5 Direction Register at BA 10 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value o
36. ing any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMA
37. ing the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 4 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your module record the value in the table inside the back cover Figure 1 8 shows the DIP switch set for a base address of 300 hex 768 decimal Table 1 2 Base Address Switch Settings SW1 Base Address Switch Setting Base Address Switch Setting Decimal Hex 4321 Decimal Hex 4321 1000 544 220 800 320 1001 1010 1011 1100 1101 1110 1 736 2E0 0111 992 3E0 111 0 closed 1 open Fig 1 8 Base Address Switch SW1 JP6 through JP11 Pull up Pull down Resistors on Digital I O Lines The DM6910 has 48 TTL CMOS compatible digital I O lines which can be interfaced with external devices These lines are divided into six ports Port 0 through Port 5 with eight bit programmable lines per port You can connect pull up or pull down resistors to any or all of these lines on a bit by bit basis You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull lines down for connection to relays which control turning motors on
38. irection or Port 0 1 EPLD IRQ Source A write clears the digital chip or programs one of the three control registers depending on the setting of bits 0 and at BA 3 When bits and 0 at BA 3 are 00 the read write operations clear the digital IRQ status flag read and the digital chip write When these bits are set to any other value one of the three Port 0 1 digital I O registers is addressed Port 0 Direction Register BA 3 bits 1 and 0 01 For all bits 1 output PO 7 P0 6 P0 5 DO A P0 3 PO 2 PO 1 PO 0 This register programs the direction input or output of each bit at Port 0 Port 1 Direction Register BA 3 bits 1 and 0 10 For all bits P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 1 output This register programs the direction input or output of each bit at Port 1 4 4 Port 0 1 EPLD IRQ Source Register BA 3 bits 1 and 0 11 D7 D6 D5 D4 D3 D2 D1 DO Port 0 1 IRQ Select 0000 P0 0 0100 P0 4 1000 P1 0 1100 P1 4 0001 P0 1 0101 P0 5 1001 P1 1 1101 P1 5 0010 P0 2 0110 P0 6 1010 P1 2 1110 P1 6 0011 P0 3 0111 P0 7 1011 P1 3 1111 P1 7 This register programs the bit to be used to generate a digital interrupt for the Port 0 1 EPLD A digital interrupt is generated when the selected bit goes from low to high or high to low depending on the IRQ Polarity bit below If the Strobe input is enabled the strobe signal will generate the interrupt BA 3 Read Digital I O Status Prog
39. iting to the Port 0 Direction Register at BA 2 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared D7 D6 D5 D4 D3 D2 D1 DO P0 7 P0 6 P0 5 DO A P0 3 P0 2 PO 1 PO O BA 1 Digital I O Port 1 Read Write This port transfers the 8 bit Port 1 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Port 1 Direction Register at BA 2 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 BA 2 Clear IRQ Program Port 0 Direction Port 1 Direction IRQ Source Registers Read Write A read clears the IRQ status flag or provides the contents of one of three control registers Port 0 Direction Port 1 D
40. ive falling edge of the pulse Bit 2 is used to enable and disable the interrupt sharing circuit If you are not using shared interrupts it is best to disable this feature to ensure compatibility with all CPUs 4 10 BA 17 IRQ Status Read Only A read shows the status ofthe three EPLD digital interrupt circuits and the jumper selectable interrupt circuit so that you can determine which circuit generated an interrupt X X X JP4 IRQ Status Port 0 1 EPLD 0 2 no IRQ IRQ Status 1 IRQ 0 no IRQ Port 4 5 EPLD E IRQ Status Port 2 3 EPLD 0 S no IRQ IRQ Status 1 IRQ 0 no IRQ 1 IRQ BA 18 Reserved BA 19 Reserved Programming the DM6910 This section gives you some general information about programming and the DM6910 The module is programmed by reading from and writing to the correct I O port locations These I O ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages BASIC Data INP Address OUT Address Data Turbo Pascal Data Port Address Port Address Data mov dx Address mov dx Address Assembly in al dx mov al Data out dx al In addition to being able to read write the I O ports on the DM6910 you must be able to perform a variety of operations that you might not normally use in yo
41. nterrupt programming techniques 7 1 7 2 The DM6910 has four interrupt circuits which can generate interrupts on any IRQ channel 2 through 15 depend ing on the setting of the jumper on JP1 or JP2 JP4 Jumper Selectable Interrupts The DM6910 circuitry has four jumper selectable interrupt sources which can be set by installing a jumper across the desired pair of pins at JP4 To use these interrupts an interrupt source must be jumpered on JP4 an interrupt channel must be jumpered on JP1 or JP2 and the IRQ enable must be set high BA 16 bit 0 BA 16 bit 1 sets the polarity of the interrupt Digital Interrupts Each EPLD Port 0 1 Port 2 3 and Port 4 5 supports a digital interrupt using one of the digital I O lines as the interrupt source The interrupt source is software programmable as described in Chapter 5 Sampling Digital Lines for Change of State In the Digital Interrupt mode the digital lines are sampled at a rate set by the 8 MHz system clock or the clock programmed in the timer counter depending on the setting of bit 5 in the Control Register When bit 5 is low the 8 MHz clock is selected and when it is high the timer counter output is selected With each clock pulse the digital circuitry looks at the state of the next bit To provide noise rejection and prevent erroneous interrupt generation because of noise spikes on the digital lines a change in the state of any bit must be seen for two edges of a clock puls
42. nterrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your DM6910 program disk for a better under standing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status flag of the DM69 10 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when th
43. onnected to the DIGITAL GND Connecting the Timer Counter I O External connections to the timer counters on the DM6910 can be made by connecting the high side of the external device to the appropriate signal pin on I O connector CN3 and the low side to a DIGITAL GND Connecting the External Interrupt The DM6910 can receive externally generated interrupt signals EXT INTI through I O connector CN3 pin 64 and EXT INT2 through I O connector CN3 pin 54 and route them to an IRQ channel through on board header connectors JP4 JP1 and JP2 Interrupt generation is enabled through software When interrupts are enabled a rising or falling edge on the EXT INT line will cause the selected IRQ line to go high depending on the setting of BA 16 bit 1 and the IRQ status bit will change from 0 to 1 The pulse applied to the EXT INT pin should have a duration of at least 100 nanoseconds 2 4 Running the 6910DIAG Diagnostics Program Now that your module is ready to use you will want to try it out An easy to use menu driven diagnostics program 6910DIAG is included with your example software to help you verify your module s operation You can also use this program to make sure that your current base address setting does not contend with another device 2 5 2 6 CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the features of the DM6910 hardware The major circuits are the digital I O lines and the timer counters 3 1 3
44. ram Digital Mode Read Write Digital IRQ Status 0 no digital interrupt 1 digital interrupt Strobe Status 0 no strobe 1 strobe BA 2 Register Select IRQ Polarity Strobe Enable Digital IRQ Enable Digital Sample Clock Select A read shows you whether a digital interrupt or a strobe has occurred and lets you review the states of the other bits in this register If bit 6 is high then an input strobe has taken place This bit will be reset when the data is read If bit 7 is high then a digital interrupt has taken place This provides the same status information as BA 17 bit 0 Digital Mode Register Reserved Reserved n BA 2 Register Select Digital Sample Clock Select IRQ Polarity DE clear Moge riei 01 Port O Direction Register 0 8 MHz system clock 0 rising edge g 1 programmable clock 1 falling edge e S ne en Digital IRQ Enable Strobe Enable 0 disabled 0 disabled 1 enabled 1 enabled Bits 0 and 1 Select the clear mode initiated by a read write operation at BA 2 or the control register you talk to at BA 2 Port 0 Direction Port 1 Direction or Port 0 1 EPLD IRQ Select Register Bit 2 IRQ Polarity sets the edge of the digital input signal that generates the interrupt Bit 3 Enables EPLD strobe input used with JP5 header Bit 4 Disables enables digital interrupts The IRQ channel is determined by the jumper setting on JP1 and JP2 Bit 5 Sets the
45. ram nennen 6 3 Digital Interrupt Timing Diagrami iieiaeie aana aana eiei aa aree eikai o e RERE 7 3 iii iv INTRODUCTION The DM6910 digital I O dataModule turns your IBM PC compatible cpuModule or other PC 104 computer into a high performance control system Ultra compact for embedded and portable applications the module fea tures 48 bit programmable digital I O lines Pull up pull down resistors on each bit Three 16 bit timer counters and on board 8 MHz clock Operation from single 5V supply DOS example programs with source code in BASIC and C Diagnostics software The following paragraphs briefly describe the major functions of the module A detailed discussion of module functions is included in subsequent chapters Digital I O The DM6910 has 48 bit programmable buffered TTL CMOS digital I O lines which are grouped into six 8 bit ports Port 0 through Port 5 Three EPLD chips handle the digital I O circuitry with each EPLD carrying two ports or 16 bit programmable digital I O lines Bit configurable pull up or pull down resistors are provided for all 48 lines Instructions for activating these pull up pull down resistors are given at the end of Chapter 1 Module Settings 8254 Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of user timing and counting functions What Comes With Your Module You receive the following items in your mod
46. rd as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are 3 3 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Event Counter Interrupt on Terminal Count Hardware Retriggerable One Shot Rate Generator Square Wave Mode Software Triggered Strobe Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C TIMER COUNTER TIMER COUNTER TIMER COUNTER XTAL 8 MHz CLK 45V GATE OUT CLK 45V GATE OUT CLK 45V GATE OUT Fig 3 2 Timer Counter Circuit Block Diagram ON BOARD VO CONNECTOR CN3 PIN 55d EXT CLK 0 PIN 56 L EXT GATE 0 PIN 57 T C OUT 0 PIN 59 EXT CLK 1 PIN 60 EXT GATE 1 PIN 58 T C OUT 1 PIN 61 EXT CLK 2 PIN 62 EXT GATE 2 T C OUT 2 O l l PIN 63 l CHAPTER 4 VO MAPPING This chapter provides a complete description of the I O map for the DM6910 general programming information and howto set and clear bits ina port 4 1 4 2 Defining the I O Map The I O map for the DM6910 is shown in Table 4 1 below As shown the board occupies 20 consecutive I O port locations To conserve the use of I O space the structure of the I O map is such that some of the registers control what operation you are performing at other addresses The digital registers you address at BA 2 6 and 10 are selected at BA 3
47. rt transfers the 8 bit Port 3 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Port 3 Direction Register at BA 6 For all bits set as inputs a read reads the input values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared D7 D6 D5 Da D3 D2 D1 DO P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 BA 6 Clear IRQ Program Port 2 Direction Port 3 Direction IRQ Source Registers Read Write A read clears the IRQ status flag or provides the contents of one of three control registers Port 2 Direction Port 3 Direction or Port 2 3 EPLD IRQ Source A write clears the digital chip or programs one of the three control registers depending on the setting of bits 0 and 1 at BA 7 When bits and 0 at BA 7 are 00 the read write operations clear the digital IRQ status flag read and the digital chip write When these bits are set to any other value one of the three Port 2 3 digital I O registers is addressed Port 2 Direction Register BA 7 bits 1 and 0 01 For all bits 1 output P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 This register program
48. rtAddress out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v_save v_save amp 199 v_save v_save 40 outportb port_address v_save A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place ofthe methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 ofa port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits 0 to 4 will be unaffected
49. s the direction input or output of each bit at Port 2 Port 3 Direction Register BA 7 bits 1 and 0 10 For all bits oziu D7 D6 D5 D4 D3 D2 D1 Do 1 output P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 This register programs the direction input or output of each bit at Port 3 4 6 Port 2 3 EPLD IR Source Register BA 7 bits 1 and 0 11 D7j D6 D5 D4 D3 D2 D1 DO Port 2 3 IRQ Select 0000 P2 0 0100 P2 4 0001 P2 1 0101 P2 5 0010 P2 2 0110 P2 6 0011 P2 3 0111 P2 7 This register programs the bit to be used to generate a digital interrupt for the Port 2 3 EPLD A digital interrupt is generated when the selected bit goes from low to high or high to low depending on the IRQ Polarity bit below If the Strobe input is enabled the strobe signal will generate the interrupt BA 7 Read Digital I O Status Program Digital Mode Read Write Digital IRQ Status 0 no digital interrupt 1 digital interrupt Strobe Status 0 no strobe 1 strobe Strobe Enable Digital IRQ Enable Digital Sample Clock Select A read shows you whether a digital interrupt or a strobe has occurred and lets you review the states of the other bits in this register If bit 6 is high then an input strobe has taken place This bit will be reset when the data is read If 1000 P3 0 1001 P3 1 1010 P3 2 1011 P3 3 IRQ Polarity 1100 P3 4 1101 P3 5 1110 P3 6 1111 P3 7 BA 6
50. t 0 bit 6 to generate an interrupt you would select the desired IRQ channel on JP1 or JP2 and set bits 4 1 and 0 at BA 3 high to access the IRQ Source Register and enable digital interrupts Then you would write 0110 in the bottom four bits at BA 2 to select digital I O line P0 6 Every time P0 6 goes from low to high depending on the IRQ polarity bit at BA 3 an interrupt is generated If the Strobe input is enabled the strobe signal will generate the interrupt regardless of the setting of the IRQ source register Resetting the Digital Circuitry When a digital chip clear is issued all of the digital I O lines are set up as inputs and their corresponding output registers are cleared Strobing Data into Ports 0 1 2 3 and 4 5 External data can be strobed into any or all of the three digital I O EPLDs Port 0 1 Port 2 3 and Port 4 5 by connecting the EPLD s strobe jumper on JP5 and enabling the strobe by setting bit 3 high in the Control Register The strobe input is the EXT INTI signal CN3 64 5 3 5 4 CHAPTER 6 TIMER COUNTERS This chapter explains the 8254 timer counter circuit on the DM6910 6 1 6 2 An 8254 programmable interval timer provides three 16 bit 8 MHz timers for timing and counting functions such as frequency measurement event counting and interrupts These timer counters can be configured in a number of ways to support your application Figure 6 1 shows a block diagram of the timer counter circ
51. t run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt status flag for the source which caused the interrupt Clear jumper selectable interrupt status flag by reading BA 16 Clear the Port 0 1 digital interrupt flag by setting bits and 0 at BA 3 to 00 and reading BA 2 Clear the Port 2 3 digital interrupt flag by setting bits and 0 at BA 7 to 00 and reading BA 6 Clear the Port 4 5 digital interrupt flag by setting bits and 0 at BA 11 to 00 and reading BA 10 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like Only the clear interrupt command sequence for the source which caused the interrupt needs to be included In C void interrupt ISR void Your code goes here Do not use any DOS functions inportb BaseAddress ou inportb BaseAddress 4 ou inportb BaseAddress tportb BaseAddress ou inportb BaseAddress ou In Pascal tportb BaseAddress tportb BaseAddress tportb 0x20 0x20 Procedure ISR Interrupt begin
52. te This address is used to read write timer counter 1 A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 14 8254 Timer Counter 2 Read Write This address is used to read write timer counter 2 A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 15 8254 Timer Counter Control Word Write Only D7 D6 D5 Da D3 D2 D1 DO BCD Binary 0 binary 1 BCD Counter Select 00 Counter 0 01 Counter 1 10 Counter 2 Read Load Counter Mode Select 000 Mode 0 event count 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe This address is used to write to the control register for the 8254 The control word is defined above BA 16 Clear IRQ IRQ Enable Read Write A read clears the JP4 jumper selectable IRQ status flag at BA 17 bit 3 IRQ Enable Register JP4IRQ Enable IRQ Sharing Ges ag 92 sed 1 disable IRQ Polarity 0 positive edge 1 negative edge A write enables JP4 interrupts and selects whether the interrupt will occur on the positive rising edge or negat
53. tting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQI and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the DM6910 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR 7 7 7 8 APPENDIX A DM6910 SPECIFICATIONS A 2 DM
54. uessensennserseensennnennennnnnnenneenne nennen nennen 1 7 SW1 Base Address Factory Setting 300 hex 768 decimal sse 1 8 JP6 through JP11 Pull up Pull down Resistors on Digital UO Lines eene 1 9 CHAPTER 2 MODULE INSTALLATION eee eere eee een nee eta aee tasse tetas e teta sese ta aee te 0000000 2 1 Module Installation 2 nene Ruben Renee ENEE Seen 2 3 External I O C nnections x eet petet dte ege ws e E p yide ana eich 2 3 Connecting the Digital VO sce e ete ee HE Nana e ERER 2 4 Gonnecting the Timer Counter VO rt ig o e OO e e e te ein ius 2 4 Connecting the External Interrupt ineeie aa i a eria i e EES aer TE e e iae EES 2 4 Running the 6910DIAG Diagnostics Program 0 ccccescesseeseeeseeseeeseeceeseensecceesecesecececaeenseceesseeeaesneeesueeeaeeeseeaees 2 5 CHAPTER 3 HARDWARE DESCRIPTION cssccsssssscosssssscssssccsssssccsssssccssscscscssssscssssssscess 3 1 Digital VO A in oh Ca RR LED RER ee de e qe 3 3 TIME COMES EE 3 3 CHAPTER 4 V O MAPPING E 4 1 Defining th VO Map ce eects ee et Ee ge ER dep e Pec nehme kein 4 3 BA 0 Digital I O Port 0 Read Write sssssssssseseeseeeeeneeneeenenne nnne nnne 4 4 R ck Digital I O Port 1 Read Write oer nat 4 4 BA 2 Clear IRQ Program Port 0 Port 1 Direction IRQ Source Registers Read Write 4 4 BA 3 Read Digital I O Status Program Digital
55. uitry ON BOARD 1 0 CONNECTOR CN3 I XTAL 8 MHz l COUNTER CLK PIN 55 EXT CLK 0 5 V GATE PIN 56 EXT GATE 0 PIN 57 1 T C OUT O OUT TIMER PIN 59 EXT CLK 1 COUNTER CLK o 5 V GATE PIN 604 EXT GATE 1 PIN T T1 Gifr 58 T C OU l l l PIN 61d EXT CLK 2 TIMER COUNTER CLK l 5 V l GATE PIN 62 EXT GATE 2 l OUT PIN 63 gt T C OUT 2 l l Fig 6 1 8254 Timer Counter Circuit Block Diagram Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map discussion in Chapter 4 The timer counter outputs are available at CN3 where they can be used for interrupt generation as an A D trigger or for timing and counting functions The timers can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches
56. ule package DM6910 interface module with stackthrough bus header Mounting hardware Example programs in BASIC and C with source code amp diagnostics software User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Module Accessories Hardware accessories for the DM6910 include the XD68 cable and TB68 terminal block board Using This Manual This manual is intended to help you install your new module and get it running quickly while also providing enough detail about the module and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own application programs When You Need Help This manual and the example programs in the software package included with your module provide enough information to properly use all of the module s features If you have any problems installing or using this dataModule contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief des
57. ur programming The table below shows you some of the operators discussed in this section with an example of how each is used with C Pascal and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB Integer C 96 amp a b c a b c a b amp c a b c Bases MOD DIV AND OR a b MOD c a bDIVc a bANDc a b ORc MOD OR Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the DM6910 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation Note that most registers in the DM6910 cannot be read back therefore you must save the value in your program To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 ina port Read in the current value of the port AND it with 223 223 255 2 and th
58. urces OTO which cascades it to Counter 0 OSC which is the on board 8 MHz clock and EC1 which is an external clock source connected through I O connec tor CN3 pin 59 Counter 2 has three clock sources OTI which cascades it to Counter 1 OSC which is the on board 8 MHz clock and EC2 which is an external clock source connected through I O connector CN3 pin 61 The gate of Counter 2 can be connected to the output of Counter 1 OT 1 or to an external gate source EG2 connected through I O connector CN3 pin 62 When no external gate source is connected this line is tied high JP3 OSC ECO OTO OSC EC1 OT1 Osc EC2 OT1 EG2 CND MI MT Ga Fig 1 4 8254 Clock and Gate Sources Jumpers JP3 ON BOARD VO CONNECTOR CN3 l l XTAL 8 MHz l TIMER PIN 55 EXT CLK 0 COUNTER Q 0 45V PIN 56 b EXT GATE 0 PIN 57 T C OUT 0 l l TIMER PIN 59 EXT CLK 1 COUNTER O 1 PIN 60 ENT GATE 1 PIN 58 L T C OUT 1 PIN 61 A EXT CLK 2 TIMER H PIN 62 EXT GATE 2 COUNTER 2 PIN el T C OUT 2 l l Fig 1 5 8254 Circuit Diagram JP5 Strobe Input Enable Factory Setting Disabled This header connector shown in Figure 1 6 connects an external signal through CN3 64 EXT INT1 to the strobe input of Port 0 Port 2 and or Port 4 To enable the strobe input on the digital I O chip of a selected port you must remove the jumper from the DIS disable pins and place it across the desired port Note th
59. ut to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared D7 D6 D5 D4 D3 D2 pl DO P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 BA 10 Clear IRQ Program Port 4 Direction Port 5 Direction IRQ Source Registers Read Write A read clears the IRQ status flag or provides the contents of one of three control registers Port 4 Direction Port 5 Direction or Port 4 5 EPLD IRQ Source A write clears the digital chip or programs one of the three control registers depending on the setting of bits 0 and 1 at BA 11 When bits 1 and 0 at BA 11 are 00 the read write operations clear the digital IRQ status flag read and the digital chip write When these bits are set to any other value one of the three Port 4 5 digital I O registers is addressed Port 4 Direction Register BA 11 bits 1 and 0 01 For all bits 1 output P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 This register programs the direction input or output of each bit at Port 4 Port 5 Direction Register BA 11 bits 1 and 0 10 For all bits P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 1 output This register programs the direction input or output of each bit at Port 5 4 8 Port 4 5 EPLD IRQ Source Register BA 11 bits 1 and 0 11 D7 D6 D5 D4 D3 D2 D1 DO Port 4 5 IRQ Select 0000 P4 0 0100

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