SH6620A
Contents
1. 400KHz 4MHz 480 45 460 40 X 440 X 35 420 E 30 400 25 2 0 4 0 6 0 2 0 3 0 4 0 5 0 VDD Volts VDD Volts Typical RC oscillator Frequency vs Vpp for reference only 410 400 4200 N 390 4000 380 N 3800 370 3600 360 3400 2 0 3 0 4 0 5 0 3909 Volts 2 0 3 0 4 0 5 0 Volts Typical RC oscillator Resistor vs Frequency for reference only R F VDD 3 0 500 450 400 350 T 300 lt 250 C 200 150 100 50 0 100 1000 10000 F KHz 19 SH6620A 5 6620 Application Circuits for reference only AP1 a Operating voltage 3 0V b Oscillator Crystal 32 768KHz c PORTA C I O V0c299HS AP2 a Operating voltage 5 0V b Oscillator Crystal 4MHz c PORTA C I O o I o o N gt Hs 1 20 20 Operating voltage 5 0 Oscillator Ceramic 400KHz c PORTA C I O AP4 a Operating voltage 5 0V b Oscillator RC 400KHz c PORTA C I O d TimerO input TO V0c99HS 21 V0c99HS SH6620A 5 6620 5 Reset Protection Circuit 1 V0299HS RESET will be pulled to GND when goes lower than Zener voltage 0 7V AP6 Reset Protection Circuit 22. R1 5 10 R2 5 40 V0cC99HS RESET will be pulled to GND when X R1 R1 R2 is lower than 0 7V 22 Bonding Diagram Pad No OAN DOA A OUN gt NOTE 1 GND1 GND2 amp GND3 BONDING TO GROUND 2 SUBSTRATE CONNECT TO GROUND Designation GND1 PA 2 TO RESET GND PBO PB 1 PB2 PB3 GND2 164 40 422 80 543 80 700 60 700 60 697 80 754 40 605 50 485 50 353 10 213 75 586 55 586 55 586 55 584 30 441 40 284 70 537 75 586 55 586 55 586 55 586 55 23 10 11 12 13 14 15 16 17 18 Designation PCO PC 1 PC2 PC3 VDD GND3 OSCO OSCI 1 430 40 562 80 701 95 717 50 713 70 717 05 717 05 717 05 721 30 598 80 5 6620 unit um 586 55 586 55 586 55 276 80 95 10 34 40 188 10 311 10 586 55 586 55 5 6620 Ordering Information SH6620AH yyxxx 000HR Chip Form SH6620A yyxxx 018DU 18L DIP SH6620AM yyxxx 018MU 18L SOP Note 1 yy means 2 bits option and means 3 bits code number If the product is OTP type and in blank order those
3. SINO WEALIH Features W SH6610C based single chip 4 bit micro controller W ROM 1K X 16 bits B RAM 64 X4 bits Data memory Operation voltage 2 2V 6 0V Typical 3 0V or 5 0 12 CMOS bi directional I O pins E 4 level subroutine nesting including interrupts One 8 bit auto re loadable timer counter E Warm up timer for power on reset Powerful interrupt sources Internal interrupt TimerO External interrupts PortB amp PortC Falling edge General Description SH6620A Mask 4 bit Microcontroller Oscillator code option X tal oscillator 32 768KHz 4MHz Ceramic resonator 400K 4MHz RC oscillator 400K 4MHz External clock 30K 4MHz W Instruction cycle time 4 32 768KHz 122us for 32 768KHz OSC clock 4 4MHz 1us for 4 2 OSC clock Two low power operation modes HALT and STOP Built in watchdog timer code option SH6620A is 4 bit microcontroller This chip integrates the SH6610C 4 bit CPU core with SRAM 1K program of ROM Timer and Ports Pin Configuration 2 2 3 4 5 6 7 8 9 V0Z99HS PORTA 1 PORTA O OSCI OSCO PORTC 3 PORTC 2 1 0 2 5 5 6620 WATCHDOG TIMER 3 BIT 3 0 3 0 3 0 UP COUNTER WDT TIME OUT TIMER INTERRUPT 1 64 X 4BIT 1 1 1
4. Option By code Code Option 1 OSC 0562 osc1 oscO OSC type 0 0 0 External Default 1 0 0 RC 1 1 0 X tal 400K 4MHz 1 0 1 Ceramic 1 1 1 X tal 32 768KHz 2 WDT EN 0 Enable Default 1 Disable 14 SH6620A 5 6620 Absolute Maximum Rating Comments DC Supply 0 3V to 7 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input Output Voltage GND 0 2V to VDD 0 2 These are stress ratings only Functional operation of this device under these or any other conditions above those Operating Ambient Temperature 10 C to 60 C indicated in the operational sections of this specification is not implied or intended Exposure to the absolute maximum Storage Temperature 55 C to 125 rating conditions for extended periods may affect device reliability DC Electrical Characteristics Voo 5 0V GND OV Ta 25 Fosc 4MHz unless otherwise specified Parameter in Condition Operating voltage All output pins unloaded Execute NOP instruction Stand by current HALT All output pins unloaded Operating current All output pins unloaded Stand by current STOP off If LPD on IsB2x IsB2 WDT off If WDT on IsB2x IsB2 150 Input Low voltage I O ports pins tri state Input Low voltage RESET Input
5. GND Pin Description 1 2 PORTA2 programmable pins Timer Clock Counter Schmitt Trigger input RESET Reset input Active Low Schmitt Trigger input enD ss _ 10 otprogrammabie VO Voor nerupi heiva taling edee Ps oso osc opan Tere Spal ita regions oF Tor RC mode osa 1 an be comet io oysir or etal ressor Functional Description 1 CPU The CPU contains the following function blocks Program Counter Arithmetic Logic Unit ALU Carry Flag Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and Stack 1 1 PC Program Counter The Program Counter is used to address the 1K program ROM It consists of 12 bits Page Register PC11 and Ripple Carry Counter PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO The program counter normally increases by one 1 with every execution of an instruction except in the following cases 1 When executing a jump instruction such as JMP BAO BC 2 When executing a subroutine call instruction CALL 3 When an interrupt occurs 4 When the chip is at the INITIAL RESET mode The program counter is loaded with data corresponding to each instruction 1 2 ALU and CY ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI
6. TOS TO signal source 0 OSC 1 4 Power on initial 1 Transition on TO pin 5 6620 TIMERO 8BITS TO 3 BUILT IN RC OSCILLATOR 2 0 3 amp WARM UP 4 COUNTER WDT TIMEOUT System register 1E on ow mw se wr _w si wor imei te one onn The input clock of watchdog timer is generated by a built in RC oscillator Thus the WDT will always run even in the STOP mode SH6620A generates a RESET condition when the watchdog times out The watchdog can be enabled or disabled permanently by user option To prevent it timing out and generating a device RESET condition you can write this bit as 1 before timing out The WDT has a time out period of more than 7ms 5V If longer time out periods are needed per scaler with a division ratio of up to 1 2048 can be assigned to the WDT under the software control by writing to the TMO register Pre scaler divide ratio valid for 5V Pre scaler divide ratio Timer out period 224ms 896ms 3 584ms O RC OSC 14 336ms 512 2048 1 1 1 7 0 1 2 14 1 1 4 28ms 0 1 8 56ms 1 1 32 0 1 128 1 1 512 0 1 2048 Power on initial WDT Time WDT 0 875ms Internal out Period 7ms PRESCALER SCALER 1 18 ii 7 id em Final WDT Time OUT perio
7. Vector Address Area 000 to 004 The program is sequentially executed There is an area address 000 through 004 that is reserved for a special interrupt service routine such as the starting vector address Address Instruction Remarks 000H JMP instruction Jump to RESET service routine 001H NOP Reserved 002H JMP instruction Jump to TIMERO service routine 003H NOP Reserved 004H JMP instruction Jump to PBC service routine 5 6620 3 Built in RAM consists of general purpose data memory and a system register Direct addressing in one instruction can access data memory and the system register The following is the memory allocation map 000 01F System register and 020 05F Data memory 64 X 4 bits The configuration of the system register is as follows Address Remarks 00 Interrupt enable flags 01 Interrupt request flags 02 TimerO Mode register Pre scaler 03 Reserved 04 TimerO load counter register low digit 05 TimerO load counter register high digit 06 Reserved 07 LPD2 LPD1 LPDO LPD Enable Control LPD3 0 1010 LPD Enable Default 0101 LPD Disable 08 PA 2 PA 1 PA 0 PORTA 09 PB 2 PB 1 0 0 2 1 0 0B 00 Reserved 0E TBR 2 1 TBR O
8. 3 0V 3 0 Crystal oscillator 3 0 2 7 3 0 Crystal oscillator C1 C2 5 30P Ceramic resonator OSC F 3 0 F 2 7 F 3 0 Include supply voltage and chip to chip variation Parameter Oscillator start time Oscillator start time Oscillator start time WDT period Frequency stability crystal Frequency variation crystal Frequency stability ceramic Frequency Variation RC Operation frequency vs IsB1 IsB1x Frequency 4MHz x IsB1 Operation frequency vs loP Frequency 4MHz x lop 32K Max Halt current 32KHz Halt current lt 5uA 3V WDT is disabled 17 5 6620 Parameter 1 orowan orrom gh puse w 1 1 Unit Condition m ns High pulse width 1 2 tiw LOW pulse width 1 2 tiw Timing Waveform To Input Waveform M gt TiwL TO RC OSCO Timing Waveform T1 T2 14 T5 16 T7 18 T1 T2 T3 14 15 T6 RC OSC 95 OSCO RC Built in RC Oscillator RESET o OSC 1 T WDT Built in RC 1 NES 2 2 Twdt gt Tosc2 Tosc3 Typical RC oscillator Resistor vs Vpp for reference only
9. Decimal adjust for addition subtraction DAA DAS Logic 2 ROM SH6620A operations AND EOR OR ANDIM EORIM ORIM Decision BAO BA1 BA2 BA3 BAZ BC Logic Shift SHR The Carry Flag CY holds the ALU overflow which the arithmetic operation generates During an interrupt servicing or call instruction the carry flag is pushed into the stack and restored back from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator Accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with ALU data transfer between the accumulator and system register or data memory can be performed 1 4 Stack A group of registers are used to save the contents of CY amp PC 11 0 sequentially with each subroutine call or interrupt It is organized 13 bits X 4 levels The MSB is saved for CY 4 levels are the maximum allowed for subroutine calls and interrupts The contents of Stack are returned sequentially to the PC with the return instructions RTNI RTNW Stack is operated on a first in last out basis This 4 level nesting includes both subroutine call and interrupt requests Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4 and the bottom of stack will be shifted out The SH6620A can be addressed up to 1024 X 16 bit of program area from 000 to 3FF Service routine as the starting vector address
10. FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will proceed This can also be used to wake the CPU from HALT mode 4 3 0 mode register The timer can be programmed in several different pre scaler ratios by setting the Timer Mode Register TMO The 8 bit counter counts pre scaler overflow output pulses The timer mode registers TMO are 3 bit registers used for timer control as shown in Table1 These mode registers select the input pulse sources into the timer Table 1 Timer 0 Mode Register 02 Pre scaler Divide Ratio Ratio N 12 2048 initial 512 4 4 External Clock Event as Source When an external clock event input is used for TMO it is synchronized with the CPU system clock Therefore the external source must follow certain constrains The output from TOM multiplex is TOC It is sampled by the system clock in instruction frame cycle Thus it is necessary for TOC to be HIGH for at least 2 tosc and LOW for at least 2 tosc When the pre scaler ratio selects 20 TOC is the same as the system clock input The requirement is as follows TOCH TO high time gt 2 tosc TOL TOCL TO low time gt 2 tosc AT When other pre scaler ratio is selected the TMO is scaled by the asynchronous ripple counter and the pre scaler output is symmetrical Then N TO 2 TOC high time TOC low time Where TO Time
11. 5 6620 SOP 18L Outline Dimensions unit inches mm Dimensions inches Dimensions in mm 0 110 Max 2 79 Max 0 004 Min 0 10 Min 0 092 0 005 2 33 0 13 0 016 0 004 0 41 0 10 0 002 0 05 0 010 0 004 0 25 0 10 0 002 0 05 0 05005 55 03 05 05 105 oenm osnon Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e1 is for PC Board surface mount pad pitch design reference only 4 Dimension S includes end flash 26 5 6620 Data Sheet Revision History 5 4 3 1 0 27
12. Low voltage OSCI Driven by external clock Input High Voltage I O ports pins tri state Input High Voltage Input High Voltage OSCI Driven by external Clock A GND lt lt VDD For OSCI ports 10mA 6 0V 5 0 7 Vpp 6 0V ports loL 20mA Vpp 6 OSCORc lor 1 6mA 6 0V Output High Voltage Output Low Voltage 0 6 15 5 6620 AC Electrical Characteristics Voo 5 0V GND OV 25 4MHz unless otherwise specified Parameter Condition Oscillator start time X tal Osc 32 768KHz 5 0V for refer Oscillator start time Ceramic Osc 400KHz Vpb 5 0V for refer Oscillator start time RC Osc 400KHz Vpp 5 0V for refer WDT period 5 0V Frequency stability crystal Crystal oscillator F 5 0 F 4 5 F 5 0 Frequency variation crystal Crystal oscillator C1 C2 5 30P Frequency stability ceramic Ceramic resonator Osc F 5 0 F 4 5 F 5 0 Frequency Variation User Notice Max Max Max Max Max Max RC Current into 50mA Current out of Vss 150mA Output current sunk by any port 25 Output current sourced by any I O port 20mA Include supply voltage and chip to chip variation Outp
13. Table Branch Register INX 2 INX 1 1 0 Pseudo index register 10 DPL 2 DPL 1 DPL O Data pointer for INX low nibble 11 DPM 2 DPM 1 0 Data pointer for INX middle nibble 12 DPH 2 DPH 1 DPH 0 Data pointer for INX high nibble 13 15 Reserved 16 PA2OUT PA1OUT PAOOUT Set PORTA to be output port 17 PB2OUT PB1OUT PBOOUT Set PORTB to be output port 18 PC3OUT 200 PC1OUT PCOOUT Set PORTC to be output port 19 1B Reserved 1C TOS TOE TO signal edge TO signal source 1D Reserved 1 WDT time out bit write one only 1F Please refer to SH6610C user s manual for the System Register 00 12 Reserved 5 6620 Low Power Detection LPD The LPD function monitors the supply voltage and applies an internal reset in the micro controller at battery replacement If the applied circuit satisfies the following conditions the LPD can be incorporated by the software control W If high reliability is not required W f power supply voltage is lt 2 2 to 6 0 V E If operating ambient temperature is 20 C to 70 C Functions of LPD Circuit The LPD circuit has the following functions Generates an internal reset signal when lt VLPD Cancels the
14. bits should be none 2 The data after mark in Part No block is the package and packing information for ordering 3 The size of those package types are showed in Package Information Page25 2 4 Any other package or packing request please refer to following table Normal package size and in tray packing QFP Normal package size and in tube packing CHIP Normal package size and in tape amp reel packing J CER DIP Larger package size and tray packing SKINNY Larger package size and in tube packing PLCC Larger package size and tape amp reel packing SOP Smaller package size and in tray packing omes Srater package size andin tube pacing S660 DE ON WAFER N Sater package sze andin tape amp reel pacha 08s wen LL we 1 1 24 IM SH6620A Package Information DIP 18L Outline Dimensions unit inches mm D eem Base Plane Seating Plane Symbol 0 018 0 004 0 46 0 10 0 002 0 05 0 060 0 004 1 52 0 10 0 002 0 05 0 010 0 004 0 25 0 10 0 002 0 05 22 86 Typ 23 37 Max 6 35 Typ 6 65 Max Symbol om Notes 1 The maximum value of dimension D includes end flash 2 Dimension E1 does not include resin fins 3 Dimension S includes end flash 25
15. AC ANDM X B 00110 1bbb xxx xxxx AC Mx lt Mx amp AC SHR 11110 0000 000 0000 0 gt AC 3 AC 0 5 CY AC shift right one bit Immediate Type C nemoris Funcion EORM 04100 xr CT ORM X 01101 AC Mx MIE 211 ANDIM X 01110 xxx AC Mx lt Mx amp the assembler ASM66 V1 0 EORIM mnemonic is EORI However EORI has the same operation identical with EORIM The same for the ORIM with respect to ORI and ANDIM with respect to ANDI Decimal Adjustment Mnemonic Instruction Code Function FlaaChanae 11001 0110 xxx xxxx AC lt Decimal adjustment for add DAS X 11001 1010 xxx xxxx AC lt Decimal adjustment for sub Transfer Instruction Mnemonic Instruction Code Function FlaaChanae LDA 00111 STA 8 00111 1bbb xx xox Mx eac 0 y 01111 ilii xxxx Mx amp 12 5 6620 Control Instruction ST 1 11000 PC X Not including p 57 lt hhhh RTNWH L 11010 000h hhh 1111 oF Where 2 00 01 00 c AC Complement of accumulator EIN Logical OR Carry flag Logical AND Immediate data Logical exclusive OR ROM page 0 Table Branch Register 13
16. Hz VDD Fosc 4 4 External input clock 30KHz 4MHz OSC External clock source OSCO 10 5 6620 LPD Initial States Hardware After power on reset Program counter 000 CY Undefined Data memory Undefined System register Undefined AC Undefined Timer counter 0 Timer load register 0 WDT counter 0 WDT pre scaler 0 ports TOS TOE WDT LPD 11 5 6620 Instruction Set All instructions are one cycle and one word instructions The characteristic is memory oriented operation Arithmetic and Logical Instruction Accumulator Type Mnemonic Instruction Code Function Flaa Chanae ADC X B 00000 Obbb xxx xxxx AC lt CY ADCM X B 00000 1bbb lt ADD X B 00001 Obbb xxx xxxx AC ADDM X B 00001 1bbb xxx xxxx Mx lt 58 X B 00010 Obbb xxx xxxx AC lt Mx AC CY SBCM X B 00010 1bbb xxx xxxx Mx lt AC CY SUB X B 00011 Obbb xxx AC Mx AC 1 SUBM 8 00011 1bbb lt 1 00100 Obbb lt Mx 6 AC EORM X B 00100 1bbb xxx xxxx Mx lt OR X B 00101 Obbb xxx xxxx AC lt Mx AC ORM X B 00101 1bbb xxx xxxx Mx lt X B 00110 Obbb xxx xxxx AC lt Mx amp
17. d 4 TimerO SH6620A has one 8 bit timer The timer counter has the following features 8 bit timer counter Readable and writable Automatic re loadable counter 8 prescaller scale is available Internal and external clock select Interrupt on overflow from FF to 00 Edge select for external event Following is a simplified timer block diagram 8 BIT COUNTER PRE SCALER TO TOE TOS 4 1 Configuration and Operation Read Operation consists of 8 bit write only timer load register High nibble first TLOL TLOH and an 8 bit read only timer counter TCOL LOW nibble following TCOH The counter and load register both have LOW order digits and HIGH order digits The timer counter can be initialized by writing data into the timer load register TLOL TLOH Load register programming Write the LOW order digit first and then the HIGH order digit The timer counter is loaded with the contents of load register automatically when Load Reg L Load Reg H the HIGH order digit is written or counter counts overflow from FF to 00 8 bit timer counter Timer Load Register Since register H controls the physical READ and WRITE operation please follow these rules Latch Reg L Write Operation Low nibble first HIGH nibble to update the counter SH6620A 5 6620 4 2 0 Interrupt The timer overflow will generate an internal interrupt request when the counter counts overflow from
18. internal reset signal when gt VLPD Below power supply voltage VLPp LPD detect voltage it is about 1 6 1 7V and lower than Vpp MIN 2 2V LPD Control Register The LPD circuit is controlled by software enable flag LPD Enable Control LPD3 0 LPD3 LPD2 LPD1 LPDO 1010 LPD Enable Default 0101 LPD Disable LPD3 LPD2 LPD1 LPDO LPD Enable Disable flag 1 0 1 0 Enable LPD circuit Power on initial 0 1 0 1 Disable LPD circuit 5 6620 System register 16 18 mu ww PA3OUT PA2OUT PA1OUT PAOOUT Description Set PORTA to be output port PB20UT PB1OUT PBOOUT Set PORTB to be output port PC3OUT 200 PC1OUT PCOOUT Equivalent circuit for a single I O pin Set PORTC to be output port VDD DATA 1 D DATA WRITE 3 CK QB RESET p PIN DATA IN CONTROL p PXXOUT OR WRITE RESET o RESET V Mm 1 control register PAXOUT PBXOUT PCXOUT X 0 1 2 3 1 Set I O as an output buffer 0 Set I O as an input buffer Power on initial TO amp WDT System Register 1C 1C TOS TOE W TO signal edge Bit1 TO signal source TOE TO signal edge 0 Increment on low to high transition TO pin Power on initial 1 Increment on high to low transition TO pin
19. rO input period pre scaler value The requirement is therefore N TO 5 2 gt 2tosc The limitation is applied for To period time only The pulse width is not limited by this equation It is summarized as follows 4 tosc 2AT TO TimerO period gt N 5 6620 5 Port Interrupt PBC interrupt PORTB amp C 8bits falling edge is controlled by Port I O register Only Input Port has Port Interrupt Thus if an interrupt enable flag IEP is setto 1 amp one port bit high goes low been touched and that the condition is the other port bits are high level 6 System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals Instruction cycle time 1 4 32 768KHz 122us for 32 768KHz system clock 2 4 4MHz 1us for 4MHz system clock Oscillator 1 Crystal oscillator 32 768KHz AMHz C1 C1 C2 Setting Crystal 32 768KHz Crystal C1 C2 lt 56 Vpn 5V 32 768 4MHz C1 C2 lt 56 Von 3V Crystal 4MHz C1 C2 lt 33 5V C1 C2 lt 10 Von 3V C2 2 Ceramic resonator 400KHz 4AMHz C1 C1 C2 Setting Ceramic 400KHz Ceramic 20 lt C1 C2 lt 470p Voo 5V 400K 20 lt C1 C2 lt 150p Voo Ceramic 4MHz 20 lt C1 C2 lt 100p Voo 5V C1 C2 lt 10 Voo C2 3 RC oscillator 400KHz 4AM
20. ut current sunk by all ports A B C 50mA Output current sourced by all ports A B C 40mA 16 5 6620 DC Electrical Characteristics Voo 3 0V GND OV 25 4MHz unless otherwise specified Parameter Condition Operating voltage 4 5 Operating current 1 3 All output pins unloaded Execute NOP instruction Stand by current HALT 0 2 All output pins unloaded Stand by current STOP 2 All output pins unloaded off If LPD on IsB2x IsB2 3uA WDT off If WDT on IsB2x IsB2 5uA Input Low Voltage GND 0 2 X ports pins tri state Input Low Voltage GND 0 15 X RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock 0 8 X VDD 0 85 Input High Voltage 0 85 X VDD OSCI Driven by external Clock Leakage Current mi 1 ua CND Wo Vb Current ma Input High Voltage 1 ports pins tri state Input High Voltage 1 ports 7mA 5 0 7mA ports loL 8mA OSCOrc lor 1 0mA Output High Voltage Output Low Voltage Condition Crystal Osc 32 768KHz Vpp 3 0V Ceramic Osc 400KHz 3 0 RC Osc 400KHz
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