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ATPL230A USER GUIDE

1. 0 dB ES T Atmel Enabling Unlimited Possibilities Click the Next button to continue Figure 6 38 TX Test Parameters tab 3 Atmel PLC PHY Teste Product Information Tx Test Parameters Configuration Summary Description This tab allow to configure all necessary parameters related with a tranmission test Parameters are Time Interval interval between frame transmmition Number of Frames number of frames to be transmitted Message ascii message to be tranmitted Test Parameters Time Interval ms 100 Number of Frames 100 Message Atmel Enabling Unlimited Possibilities Atmel Enabling Unlimited Possibilities ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 59 Previous figure shows the TX Test Parameters tab Figure 6 38 This tab is where transmission test parameters are configured e Time Interval milliseconds desired interval between frame transmissions e Number of Frames number of frames to be transmitted e Message ASCII message to be transmitted These parameters must match the reception test parameters Figure 6 33 for the test to be successful Default parameters are selected Click the Next button to continue Figure 6 39 Configuration Summary tab Lu Atmel PLC PHY Tester Tool v2 3 Help Welcome Product Information Transmission Parameters Tx Test Parameters Configuration Summary
2. Connected Serial COM4 B115200 Server 9099 On the other hand once the Service node board is powered the green led D5 LED O is blinking Once the boards are connected to the mains the PRIME network begins to form The Service Node listens to the Base Node beacons and starts the registration process shown This process is shown in the Figure 6 83 ATPL230A EK Kit User Manual USER GUIDE 93 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 94 Figure 6 83 PRIME registration process REG RE REG Rsp REG _ACK The Service Node sends the registration request and waits for the base node respond When the Base node sends a PLC message the TX led of the coupling board is toggled And when the Service node sends a message the TX led of the coupling board is toggled You can use them to check if boards are sending PLC messages properly If tool establishes the communication with the COM port of Base node the status bar at the bottom of the window will show the current setup and status of the tool On a PRIME network the main window will look like as the Figure 6 84 Main window displays a table with the current log It is updated in real time as frames are received from the hardware sniffer Figure 6 84 Atmel PRIME Manager tool main window when is connected to a Base Node P E3 ATMEL PRIME MANAGER v1 1 12 lo
3. Interface Xplained PRO Target DBG VARTs i D D CP vol vO f Si GND VIS vussi 7 12 o keen 3 UR R t wp TEP SUSTENDRI SCI a oe GIDE DED SCI eu DNP a Se GPIOLDTR SCH Ro Supra GEI Dep SC CTS SCH DNF co Aimy a ee Ot a et ep SC RIK d i 2 ve z Le 3 i A A Li 3 p EG Sp SK ATI Se 9 10 d d AN Np i Header 2N7H FB ge Sh axp WZ T me GND WA Figure A 9 ATPL230AMB components location in top layer ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 N Ras ee aoo P AN L i EE DT Swi gz PLO RST BN MIMO pene Jost tan aes Se ZE cz ai AE H 6 aen S at RO 19 10 T a3 LF e mee LA re rT if on Kg b La e visite Rew Description File date 10 8 2014 i Sheet 8 of Author JLC Project ATPL2xxAMB vi Verified A R File Interface SchDoc Code number TITLE Interface ATPL2xxAMB A2 ATPLCOUPO001v1 schemes This section contains the schemes of the ATPLCOUP001 PLC Coupling board e PLC Coupling transmission scheme e Components location in top and bottom layers Figure A 10 ATPLCOUP001 PLC Coupling transmission scheme ATPLCOUPO01 N CENELEC A NR EMITO NR EMITI 22R_EMIT2 Di
4. Note the displayed warning message before to select the values In this example we select Figure 6 37 the following values e PLC coupling board We select ATPLCOUP001_v1 This parameter must match with the reception parameter Figure 6 32 for the test to be successful e Channel We select Ch 1 This parameter must match with the reception parameter Figure 6 32 for the test to be successful e Frame Type We select PRIME 1 3 6 e Modulation Scheme We select TypeA PRIME v1 3 6 e Attenuation level We select 0 dB e Branch configuration We select Auto 58 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Perform EVM Test Disabled Figure 6 37 Transmission Parameters tab ju Atmel PLC PHY Tester Transmission Parameters Tx Test Parameters Configuration Summary This tab allow to configure all necessary parameters in order to make a transmission Counpling Selecti AA weng vou must to select the same couping you have plugged in the board h Check the coupling identifier that you can find in the coupling board If current coupling is not the proper one for the channel you want to transmit please remove it and connect the proper one Also verify that Vdd is the correct for the coupling board selected Otherwise the board could be seriously damaged Select Coupling ATPLCOUPO00_v2 d Transmission Parameters Ch 1 Type A PRIME v1 3 6 e E
5. 6 1 6 Atmel Software Framework ASF The Atmel Software Framework ASF is a collection of embedded software for the Atmel Flash MCUs megaAVR AVR XMEGA AVR UC3 and SAM devices lt simplifies the use of our microcontrollers by providing an abstraction to the hardware and high value middleware ASF is designed to be used for evaluation prototyping design and production phases The intention of ASF is to provide a rich set of proven drivers and code modules developed by Atmel experts to reduce customer design time It simplifies the usage of microcontrollers providing an abstraction to the hardware and high value middleware ASF is integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC IAR compilers ASF can be downloaded for free ASF is an open source code library designed to be used for evaluation prototyping design and production phases The Atmel Software Framework is split in six main parts the avr32 directory the xmega directory the mega directory the common directory the sam directory and the thirdparty directory These six directories represent the Atmel AVR UCS architecture the Atmel megaAVR the Atmel AVR XMEGA architecture and the Atmel SAM architecture what are common between all architectures and finally third party libraries Each architecture and the common directory is split into several subdirectories these directories contain the various modules boards drive
6. Atmel ATPL230A ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL AT PL230A EK Kit User Manual UserGuide_03 Nov 2015 Introduction ATPL230A EK is an evaluation kit for the ATPL230A modem for Power Line Communication from Atmel Corporation ATPL230A is a power line communications base band modem compliant with the PHY layer of PRIME Power Line Intelligent Metering Evolution specification ATPL230AMB is PLC multi purpose modem board based on the ATPL230A transceiver and on Atmel Smart SAM4C ARM Cortex M4 microcontroller This development board provides a full featured platform to develop a complete communications system over Power Line Communication technology This guide describes how to use the kit and get start with it Contents e Welcome letter that presents you the e Cables evaluation kit and the contents e Two micro A B type USB cables e Boards e Two power cord cables IEC320 e Two ATPL230AMBv4 modem C8 boards D Jumpers e Two ATPLCOUPO01v1_ coupling e Two voltage jumper with pitch boards 5 08mm e Two ATPLCOUPOO6v1_ coupling e Two erase jumper with pitch boards 2 54mm Features e ATPL230A is a compact and high efficient device for a wide range of Smart Grid applications such as Smart Metering Smart Meters and Data Concentrators Lighting Industrial Home Automation Home and Building Energy Management Systems Solar Energy and Plug in Hybrid Electric Vehicle PHEV Charging Stations e AT
7. Description This tab shows a brief of the configuration fixed in previous steps at the tab there is a little explanation of how to proceed with the test Configuration Summary Parameter Serial Port COMS5 Enhanced Test Type TX Frame Interval ms 100 Number of Frames 100 Message Atmel Enabling Unlimited Possibilities Attenuation evel NAR Attention In order to obtain correct result for the test please start before Rx board than Tx board Altmel Enabling Unlimited Possibilities The previous tab shows a table where all the configuration parameters and their selected values are listed It is recommended to check that all values correspond to the desired configuration before continue To start the process click the Start Test button A new tab Test Executions reports of TX process will appear with the frame sent and the TX result of the transmission process Now you can observe the transmission and reception process in both Test Executions windows If messages are different the receiver will not recognize them as a valid If the configured interval and number of frames are different the statistics computed at the end of the test may be inaccurate In both board s displays the transmitted received messages are showed gt During the transmission process the TX led of the coupling board is toggled You can use it to check if the PLC messages are sent When all frames are sent both Test Execu
8. S CAUsers raul navarro Desktop thirdparty prime workspace atp 230amb thirdparty prime phy atpl230 apps phy_tester_tool phy_tester_tool c 1 e file A 9 APPS_PHY_TESTER_TOOL a Dependencies brief ATMEL PLC Phy Tester Example a Output Fil aj Libraries Solution Copyright c 2014 Atmel Corporation All rights reserved e r m i c p g a mex K asf_license_start e Explorer page License A sam a boards Redistribution and use in source and binary forms with or without atpl230amb modification are permitted provided that the following conditions are met gt E drivers 1 Redistributions of source code must retain the above copyright notice d sri a this list of conditions and the following disclaimer abe 4 thirdparty 2 Redistributions in binary form must reproduce the above copyright notice E CMSIS this list of conditions and the following disclaimer in the documentation a prime and or other materials provided with the distribution D a phy Atmel Studio gt am atpl230 3 The name of Atmel may not be used to endorse or promote products derived a Geence tit from this software without specific prior written permission Editor a B config ul conf_board h 4 This software may only be redistributed and used in connection with an i conf_buart_if h Atmel microcontroller product ahi conf_busart_if h THIS SOFTWARE IS PROVIDED BY ATMEL AS IS AND ANY EXPRESS OR I
9. We recommend characterizing the potential impact of the selected IMPORTANT SMPS for customer designs on the PRIME transmission channel Vpp could be two different voltages 16 volts or 12 volts depending on the jumper position If the jumper is not placed the voltage Vpp is 16 volts If the jumper is placed in J16 Vpop is 12 volts By default the board has not a jumper so board provides 16 volts These different voltages are used to supply the PLC coupling driver board ATPL230A EK Kit User Manual USER GUIDE 17 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 x DANGER Be careful with this issue because the PLC coupling driver board ATPLCOUPXXX could be damaged See the features of these boards to know the working voltage Figure 3 5 Vpbp selection in ATPL230AMB board EN Jumper ap bo 4 orar configuration EnA gt c95 IS di Bic d HM Bo rns ates M j j 7 96 MN g AA of a Ti XP AINED PRO EXTA Jumper J16 ATPL230AMB can also be powered from USB connector J9 Figure A 8 or Xplained PRO interface J12 without requiring connection to mains Note that in these cases Vpp is not available so the PLC amplifier cannot be used The following test points and LEDs allow checking that these power supplies are running properly see Figure A 2 e Von TP6 and green LED D17 e 5V TP5 and green LED D3 e 3V3 TP13 and green LED D13 e GND TP3 amp TP4 3
10. ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 71 Completing the Atmel ATPL Multiprotocol Sniffer Setup Wizard Atmel ATPL Multiprotocol Sniffer has been installed on your computer Click Finish to dose this wizard lt Back Cancel Click Finish Now the program is installed in your computer and a shortcut should have been created in your desktop 6 4 2 Supplying the boards Please refer to 6 2 2 in order to know how to supply the ATPL230AMB board 6 4 3 USB connection Please refer to 6 2 3 in order to know how to connect the micro USB cable with the ATPL230AMB board 6 4 4 Programming the embedded files We have commented in section 6 2 4 the way to program a board To program the board as PLC sniffer process will be the same building the IDE project and downloading into the board Open the IDE tool used Atmel Studio or IAR Embedded Workbench Select the PHY sniffer tool project APPS_PHY_SNIFFER_TOOL atsin or APPS_PHY_SNIFFER_TOOL eww and now build it to generate the output file Note that kits do not provide a J Link ARM or SAM ICE JTAG probe in order to connect to the user s host PC and the boards to download and debug the projects Remember that every PHY example project is contained in the following folder Software PRIME_vaa bb cc dd phy atol230amb thirdparty prime_ng phy atpl230 apps oh y_sniffer_tool sam4c16c_atpl230amb And also i
11. Frame Symbols 5 Frame Duration 13 246 ms Tx Mean Interval 100 00 ms Effective Baudrate Peak 23551 bps Effective Baudrate Real 3120 bps Raw Baudrate Peak 34420 bps Raw Baudrate Real 4560 bps Channel lsane 13 25 Altmel Enabling Unlimited Possibilities Cancel ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 61 62 Figure 6 41 Reception test result Rx Test Parameters TestExecution Copy Table Frame Frame Type Mod Scheme RSSI dBuV SNR dB EVM db Data Rx Interval Payl TYPE A DBPSK 118 27 00 24 00 Atmel Enabling Unlimited Possibilities 100 Ok TYPE A DBPSK 118 25 50 22 50 Atmel Enabling Unlimited Possibilities 100 Ok TYPE A DBPSK 118 23 75 Atmel Enabling Unlimited Possibilities 100 TYPE A DBPSK 118 23 75 Atmel Enabling Unlimited Possibilities 100 Final Time 17 12 2014 12 58 35 560 Frame Error Info Total Frames Received 100 Total Frames Bad Header CRC 0 Total Frames Bad Header LEN 0 Total Frames Bad Payload 0 Total Frames Received OK 100 Cancel Atmel Enabling Unlimited Possibilities While tests are executing a row is added to the top table with information about the frame currently transmitted received The columns that contain these tables are the following Table 6 1 Transmission Reception parameters showed in columns Transmission parameters s
12. 1 A welcome letter ATPL230A EK_WL which presents you the evaluation kit and the contents 2 ATPL230A EK Kit User Manual doc43075 3 Hardware folder contents a ATPL230A datasheet doc43053 b Some application notes about hardware issues different Atmel PLC coupling boards crystal selection guidelines layout recommendations critical design guidelines etc c Schemes PCBs layout Gerbers and BOM files of ATPL230AMB ATPLCOUPO001 and ATPLCOUPO06 boards 4 Software folder contents a PRIME_vaa bb cc dd folder contains several projects for IAR and Atmel Studio e Three PHY example projects in an unique workspace see phy atol230amb zip file Apps Phy_Tester_Tool This application configures PRIME PHY layer and its serial interface to communicate with Atmel PLC PHY Tester Tool to send and 8 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 receive PLC messages from to the PLC line and check the PLC transmission reception processes between ATPL230AMB boards Atmel PLC PHY Tester tool can be downloaded from the PC Tools folder Apps Phy_Tx_Test_Console This application lets the user to configure a proper set up to perform both EMC emissions and immunity tests on ATPL230AMB board These tests are based on the use of PRIME PHY layer with a terminal console firmware that eases the configuration of several transmission parameters such as modulation frame data length and ti
13. Atmel PLC PHY Tester Tool in your PC users can interface with the device and start exploring its capabilities for example checking the point to point PLC transmissions between the two ATPL230AMB boards Take into account that the ATPL230A EK provides two coupling boards for CENELEC A band Figure 2 4 set over the ATPL230AMB board In addition to the ATPLCOUP001 boards evaluation kit adds two coupling boards for FCC bands PRIME channels 3 4 5 6 7 and 8 Figure 2 5 So the Atmel PLC PHY Tester Tool lets you send and receive PLC messages with both coupling boards according to the board selected in the PC tool And depending on the board selected you will select the PHY parameters and the PLC channel So that with ATPLCOUP001 board only lets you send and receive PLC messages in CENELEC A band And with ATPLCOUP0O06 board in FCC bands Please refer to chapter 6 2 for further information 12 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 2 4 ATPLCOUPO01 Coupling board ATPL230A EK Kit User Manual USER GUIDE 13 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 ATPL230AMB Hardware 3 1 3 2 14 Overview This section summarizes the Atmel ATPL230AMB board design It introduces system level concepts such as power supply MCU PLC coupling memories peripherals and interface board ATPL230AMB is a PRIME multi purpose development
14. Atmel PLC PHY Tester tool Installation 000nn00nnnnannnnannnnannnnennnnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnne 44 6 2 2 Supplying the Te E 47 SE E Eeer EE 48 6 2 4 Programming the embecdded ie 49 6 2 5 Running the PLC application example e 51 4 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 3 PLC application example 2 PHY TX Test CGonsole n 63 63 1 Supplying the S 2 110 E 64 632 Os ee EE 64 6 3 38 Programming the embecdded mie 64 6 3 4 Running the PLC application example 72 65 6 4 PLC application example 3 PHY Sniffer cee cccccccceeseeseeeeeeeeeaeeseeeeeeeeeeaeaaeeeeeeseeseeaseeeeeeeseaaaneeeees 68 6 4 1 ATPL Multiprotocol Sniffer tool Installation 2 0 00 eeeeecceceeeeeeeeseeeeeeeeeeaeeseeeeeeeeeeaeeeeeeeseeseaaees 69 6 4 2 Eeer tere EE 72 DAS USB CONNECCION EE 72 6 4 4 Programming the embecdded mies 72 6 4 5 Running the PLC application example 3 73 SE Introducionio PRIME ie EE 76 SE GN 4 EN 79 Co ae 2 6 E 79 6 5 3 Atmel PRIME Stack Giruciure nnn 80 6 6 PLC application 5 PLG NetWOIK scsseitisassi cnerisenernansnrrutkanara ien Enia EHE nnn Nan EEEE NEER PANKER REPA ONEN EENEN 86 6 6 1 Atmel PRIME Manager tool installation cccccecccccsseeeeseseeeeeeeeeeseeeeeeseeeeesaaeeeeseeeeessaeeeesaees 87 6 6 2 Supplying the DOS cceicc A acensaccachccedeccennsteeseses fecdenssscaeeedd Gidnctdatouaetededdasiendeca
15. BATS4S NR EMITS NR EMIT4 22R_ EMITS B Q2 DMN2075U D4 YELLOW DMN2075t Bel Description Date fO aor File date 5 23 2014 Sheet 1 of 1 maoo Atmel ATPLCOUPO01 Z2RBRRRRREB i SE A ZE L Ab ei n FIDI FID2 SALA ST Figure A 11 ATPLCOUP001 component location in top and bottom layers ATPL230A EK Kit User Manual USER GUIDE 119 Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 ATMEL EVALUATION BOARD KIT IMPORTANT NOTICE AND DISCLAIMER This evaluation board kit is intended for user s internal development and evaluation purposes only It is not a finished product and may not comply with technical or legal requirements that are applicable to finished products including without limitation directives or regulations relating to electromagnetic compatibility recycling WEE FCC CE or UL Atmel is providing this evaluation board kit AS IS without any warranties or indemnities The user assumes all responsibility and liability for handling and use of the evaluation board kit including without limitation the responsibility to take any and all appropriate precautions with regard to electrostatic discharge and other technical issues User indemnifies Atmel from any claim arising from user s handling or use of this evaluation board kit Except for the limited purpose of internal development and evaluation as specified above no license express or implied by estoppel o
16. EE 19 SN E ee Te te E 20 Cho fo POPAO eege 23 3 5 6 Interface Ports secon ccteeeseetenceinn ene steamed qesexsiinebeusesndedertieeesieinciebaetiesemuepedaneocetiutaieaseeeandeneenesecteranencmases 25 4 ATPLCOUPO01 Hardwatr e ccccccceseeceseceneeceseeenseeensecenesoaseeensecanesensesenesonseseneess 27 BN HOM EE 27 Be EE 27 4 3 Mechanical and user considerations ccccceeeeeceeceeeeeeeecaeeeeeeeeaeeeeeeeseeeeeeeeseeeeeeessaeeeeeseegeeeeesaeeeeeseaas 28 4 4 Hardware description 28 5 ATPLCOUPOO6 Fran wy al EEN 29 N EE 29 De EE 29 5 3 Mechanical and user considerations 000nnn0annnannnnea1nnnnnnnennnnnnrrnrnrrnnnrrnnnrrnnnrrnnnrrnnnrrennrrnnnrrennrrnne 29 5 4 Hardware description EE 30 6 ATPL230A Evaluation Kit Getting starte eekeEKRREEERSEERREENRREEE RRE RREEE RE EENRR EEN 31 6 1 Introduction to the embedded system cccccceeeeceecceeeeceeceeeseeeeesaeeeeeeesauseeeeeseaeeeesseaseeeeesaaneeeeessaeeeees 31 6 1 1 IAR Embedded Workbench n nnnn0nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrrnnnrnnnnrrnnnrrnnnrrnnnrrnnnrrnnnnrnennne 31 Ce re Ee e G eee A A E A 31 E Atmel SAM ICE JTAG e 32 6 1 4 J Link SAM ICE JTAG Probe Software amp Documentation Pack 32 6 1 5 Downloading a file using command script les 34 6 1 6 Atmel Software Framework GE 39 6 1 7 Firststeps ue E 36 6 1 8 First steps with Atmel Gpudop 39 6 2 PLC application example 1 PHY Tester 43 6 2 1
17. For example the prime_service_modem_aipl230amb uses Serial Profile and PLME MLME and prime_service_dimsemu_ui atol230amb project uses Serial Profile It involves that different tabs of the tool run with different applications See following tables In this example we will use the modem example so prime_service_modem_aipl230amb project Table 6 4 Protocols for Software projects Project example Serial Profile PLME MLME thirdparty apps prime_service_prime_ng dilmsemu_fi atpl230amb thirdparty apps prime_service_prime_ng dlmsemu_ui atpl230amb thirdparty prime_ng apps prime_service_modem_230 Table 6 5 Tool tabs and protocols Protocol PLME MLME Serial used PIBs Profile MAC 4 32 PLME MLME Certification as So in window Settings select the option PLME MLME protocol for the examples 6 7 5 1 6 7 5 2 and 6 7 5 3 Figure 6 99 Protocol PLME MLME selected Protocol used for application requests PLME MLME Serial Profile In case the embedded sniffer is enabled the database file to store the traffic must be configured So in the Settings window select the database file name and the location to store the sniffer log and click OK button Figure 6 100 Furthermore overwrite or append option can be selected Database files can hold longer logs without having to split them in pieces Also log stored files can be opened to review the file Figure 6 100 Database Settings Sniffer Options Enable Sniffer Sniffer Databa
18. IAR Embedded Workbench IDE choose File gt Exit You will be asked whether you want to save any changes to editor windows the projects and the workspace before closing them File Edit View Project Debug Disassembly J Link Tools Window Help Dae Sls SBEloO VRUERP SP Eh WR S Dd e EE DEES Sx Workspace Z phy_tester_tool main x Disassembly R Files i oe Main code entry point ii Disassembly 3 amp apps_phy_tester_tool_flash Debug v gt CRC 01004832 04939 LDR N Ri EJ m O common gi 0x1004834 0x2000 MOVS RO er sam A ifdef CONF BOARD LCD EN 021004836 0x7008 STRB RO F Ha O boards status_code_t status a G atpl230amb endif m 0x1004838 Oxf04f 0x6080 MOV W RO Ha O arivers Ox100483c 0x4937 LDR N R1 E Ha G services ul_count_ms 500 count ms to blink led Ox100483e 0x6008 STR RO F Laugs Ha G thirdparty Prepare the hardware 0x1004840 0x2210 MOVs R2 1 CaM prime_ng prvSetupHardware 7 0x1004842 0x2100 MOS R1 at Haha 0x1004844 0x4620 MOV RO R Log D igdes SE 0x1004846 Oxf7ff Oxfdbe BL Lo eens Le atpl230 A ARE ET te_start TC_1MS TC_1MS_CHN ha G addons Ge Ox100484a 0x4620 MOY RO Ri Bam i i 0x100484c Oxe8bd 0x4010 POP V R4 1 0x1004850 0x2100 MOVS Ri at am aide CONF BOARD LCD_EN 0x1004852 Oxf7ff Oxbda2 BN Le Ste Initialize the C42364A LCD glass c
19. Nov 2015 51 Figure 6 27 Welcome instance LA Atmel PLC PHY Tester Tool v2 3 Help Welcome Summary Welcome to Atmel Multiplatform PhyTester this application allow you to test basic functionality of Atmel PLC products Please select the serial port in wich your Atmel board is connected to your PC Connection Serial Port ee BF 1616018 L BaudRate 401017 Enabling Unlimited Possibilities The first to do is configure the corresponding COM port for each board In this window we select the serial connection configuration e Select in the Serial Port combo box the proper port to connect see Figure 6 28 As it is explained in section 6 2 3 communication is by the Enhanced COM UARTO If your COM port does not appear see section 6 2 3 press Find Ports button e Select the BaudRate combo box of 115200 bauds Figure 6 28 Serial port selection Connection Serial Port COMMS Enhanced COMES Enhanced COMA Standard BaudRate Once COM port is selected click the Connect button As soon as the button is clicked the button text will change to Connecting Then the application and the board start a process of identification and after few seconds the button text will change to Disconnect This means that the identification process has finished A new Tab Product Information is appended to the wizard and Next button is enabled allowing the user to go to the following step of the configuration
20. PC tools software examples and hardware provided and giving you the necessary documents to create your PLC application by means of small and easy examples 2 1 Design support To make it faster and easier for you to evaluate prototype develop and program with Atmel products we offer a variety of design resources including development tools software boards kits and documentation For any technical support request please refer to our Design Support webpage http www atmel com design support There any user can search the Atmel knowledge base to find tips help topics and answers to common questions In case that the obtained information is not helpful any user can Open a Support Case indicating a description of the case product information etc 2 2 ATPL230A EK contents Additional information of this user guide as hardware documentation software projects and PC tools to get started can be found in our Atmel website http www atmel com tools ATPL230A EK aspx To download this information you need a myAtmel account www aitmel com myAimel After that please contact with plc atmel com to get the password access kit contents site Once you have access to the ATPL230A Evaluation Kit Project you can find the available releases for the ATPL230A EK You can get these items navigating through the different folders of the packing kit Please do not hesitate to visit our web site to get the last kit updates Packing kit contents are
21. PRIME Stack Structure The PRIME specification currently describes the following architecture from bottom to top e PHY layer capable of achieving rates of uncoded 128 kbps It transmits and receives MPDUs MAC Protocol Data Units between Neighbor Nodes using orthogonal frequency division multiplexing OFDM e MAC layer for the power line environment It provides core MAC functionalities of system access bandwidth allocation connection establishment maintenance and topology resolution e Convergence layer for adapting several specific services It classifies traffic associating it with its proper MAC connection this layer performs the mapping of any kind of traffic to be properly included in MSDUs MAC Service Data Units It may also include header compression functions Several SSCSs Service Specific Convergence Sublayer are defined to accommodate different kinds of traffic into MSDUs e Management Plane enables a local or remote control entity to perform actions on a Node In the Management Plane there are two modules called MLME MAC Layer Management Entity and PLME PHY layer Management Entity that allow the external configuration of the MAC and PHY layers respectively This module also includes the firmware upgrade capability The Atmel PRIME Firmware stack is able to run on a system with an Operative System or without it running in microcontroller mode The OSS intends to transform the microcontroller mode operation into a
22. Rx Test Parameters Configuration Summary Description This tab allow to configure all necessary parameters related with a reception test Parameters are Time Interval expected interval between frame transmmition Number of Frames number of frames to be received Message asdi message expected Test Parameters Time Interval ms 100 Number of Frames 100 Message Atmel Enabling Unlimited Possibilities Atmel Enabling Unlimited Possibilities Default parameters are selected Click the Next button to continue Figure 6 34 Configuration Summary tab This tab shows a brief of the configuration fixed in previous steps at the tab there is a little explanation of how to proceed with the test Configuration Summary Parameter Serial Port COM Enhanced Test Type RX Frame Interval ms 100 Number of Frames 100 Message Atmel Enabling Unlimited Possibilities Attention In order to obtain correct result for the test please start before Rx board than Tx board Atmel Enabling Unlimited Possibilities srt ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 The previous figure Configuration Summary tab shows a table where all the configuration parameters and their selected values are listed It is recommended to check that all values correspond to the desired configuration before to continue To start the process click the S
23. The main window of the Atmel PRIME Manager PC interface is shown in Figure 6 78 Figure 6 78 Atmel PRIME Manager tool window fi E3 ATMEL PRIME MANAGER v1 1 12 o 8 2 Disconnected Serial COM47 B115200 Server 9099 Once the application is launched the COM port for the board needs to be configured The COM port selection window is available by choosing File gt Seitings Input A new window Settings will appear as shown in Figure 6 79 Select the connection options e Click Run local USI server option e Select device type as Base ATPL230A EK Kit User Manual USER GUIDE 91 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 e Click the Serial option and select the COM port it can be checked in the Windows Device Manager Com Port section select the enhanced port UARTO and set the speed Default speed for this application is 115200 bauds Also this tool is able to connect to a remote device through the TCP IP protocol This option requires the IP address of the server and the port opened by the server Figure 6 79 Settings window fas Settings Run local USI server Connect to remote USI server Server options Device type 9 Base Service Serial Port COM47 Enhanced BaudRate CH TCPAP Host 10 140 228 11 Port 8216 Internal Requests Protocol MME 9 Serial Profile Log Options E ust UST_Log bet Browse Base Management el PRIME Manager_1 1 12 FUpg_Log txt Sni
24. Tue Nov 16 2014 08 11 50 Hardware reset with strategy 0 was performed Tue Nov 18 2014 08 11 50 Target reset Tue Nov 18 2014 08 11 50 execUserReset EB g Tue Nov 18 2014 08 11 50 GE PC Reset a inion a Si z o z Debug Log Build x Ready ed aa e ml ga Et ml ee For examples of building application and library projects see the tutorials in the Information Center For more information about building library projects see the IAR C C Development Guide for ARM First steps with Atmel Studio 6 2 Atmel Studio 6 2 supports the SAM4C core Once Atmel Studio 6 2 is installed in your computer launch Atmel Studio 6 2 Click the Start button on the Windows taskbar and choose All Programs gt Atmel gt Aitme Studio 6 2 The workspace file has the filename extension atsin If you double click a workspace filename the IDE starts Note Opening Atmel Studio 6 2 takes some time The following figure shows the main window and its default layout ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 39 aAa dga aala e MAAL O a l eas O ORARAA an OCRA Og M ajo n db o Stee THe n Oa Sy li Bi l li a No Device NoTool Get Started Tools Help Latest News aa New Project Welcome Links and Resources New Example Project VT Open Project oes cums Welcome to Atmel Studio Get to know Atmel Stud
25. agreement to install Atmel ATPL Multiprotocol Sniffer Nullsoft Install System v2 46 os Les Read and accept term and conditions expressed in the End User License Agreement Click Agree to continue 70 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 53 Installation process slide 4 otocol Sniffer Setup Choose Components Choose which features of Atmel ATPL Multiprotocol Sniffer you want to install Check the components you want to install and uncheck the components you don t want to install Click Next to continue Je i Description Select components to install Atmel ATPL Multipratocol e a Position your mouse over a component to see its description Space required 51 46 Nullsoft Install System v2 46 Choose Install Location Choose the folder in which to install Atmel ATPL Multiprotocol Sniffer Setup will install Atmel ATPL Multiprotocol Sniffer in the following folder To install in a different folder dick Browse and select another folder Click Install to start the installation Destination Folder ogram Files x86 Atmel ATPL Multiprotocol Sniffer_1 1 7 Space required 51 4 B Space available 302 6GB fullsoft Install System v2 46 Setup will install the program in the Destination Folder To install in a different folder click Browse and select your destination folder Click Install to start the installation process
26. application window e e ta ATMEL PRIME MANAGER v2 0 7 Emam File Connection View Help PRIME Management Deivce ID ATMService01 PingPong Atmel Enabling unlimited possibilities Num Chars 38 05 06 2015 12 15 21 505 CL432_ESTABLISH_request sent device id ATMService0 1 05 06 2015 12 16 21 624 CL432_ESTABLISH_confirm received device d ATMService01 dst_address 2 base_address 0 05 06 2015 12 18 03 145 CL452_DL DATA REQUEST 38 bytes sent to base 05 06 2015 12 18 04 270 CL432 DL DATA confirm received det Jeep 1 src_lsap 16 dst_address 0 tx_status 0 Binary format DATA Figure 6 107 Base node tool application window WE Certification MFG Test Banned MACs Broadcast Ping Pong Z Binary format DATA nm chars 0 05 06 2015 12 16 21 662 CL432_JOIN_INDICATE Serial ATMService0 1 Address 2 MAC 01 40 90 87 00 74 05 06 2015 12 18 03 321 DL432_DATA_INDICATION 38 bytes received from node 2 Atmel Enabling unlimited possibilities Lamm Connected Serial COM47 B115200 Server 9098 6 7 5 3 Closing a 4 32 connection After the interchange of messages is time to close the 4 32 connection The PRIME process to close the 4 32 connection is shown in the Figure 6 108 108 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 108 PRIME 4 32 connection close BASE NODE ON CLS_ ON_CLS B Remem
27. board Process to load the output file is commented in sections 6 1 7 1 or 6 1 8 1 b Another way could be using the Device Programming Instance of the Atmel Studio IDE Once the output file has been created you can load the program in the flash memory In the menu bar go to ools gt Device Programming Select the tool device and interface and press Apply button Then press Read button of Device signature Go to Memories window select the output file hex or elt and press Program button When finished power cycle the board to run the program Remember that every PHY Tester tool example project is contained in the following folder Software PRIME_vaa bb cc dd phy atpl230amb thirdparty prime_ng phy atpl230 apps oh y_tester_toollsam4c16c_atpl230amb And also in the PHY common workspace ATPL230A_PLC_examples which is contained in following Software folder ooftware PRIME_vaa bb cc dad phy atol230amb thirdparty prime_ng apps wrkspcs Figure 6 24 Device Programming instance Tool Device Interface Device signature Target Voltage ATSAMAC16C_0 OxA64COCEO Read 33v E bh e Interface settings Device Tool information Erase Chip sl Erase now evice information Flash 1024 KB atp 230 apps phy_tester_tool sam4c16c_atp 230amb as5_arm Debug APPS_PHY_TESTER_TOOLhex e JL GPNVM Bits Wi Erase Flash before programming G i Program Verify Read Lock bits Security JLink Config JLink Control Pan
28. br SG Hel Firmware Upgrade G x Nodes MAC SID LNID LSID fuState Version Vendor M 4 32 Address ALV Rx Tx Coverage 01 40 90 87 00 74 0 11 255 01 03 09 02 ATMEL 2 2 2 100 mg 100 2015 06 05 10 15 26 gt gt NetEvent MAC 01 40 90 87 00 74 STATE Registering Ss 2015 06 05 10 15 26 gt gt NetEvent MAC 01 40 90 87 00 74 STATE Terminal E 2015 06 05 10 16 16 gt gt FUP_ACK From Process FUP_VERSION_REQUEST Info OK 2015 06 05 10 16 17 gt gt Version MAC 01 40 90 87 00 74 vendor ATMEL Zz model SAM4CP 16BMB version 01 03 09 02 E Time Configurations Delay Restart 60 Safety Timer 21600 File Configuration el Match Rules Vendor Model Page Size AUTO MA ARQ v Multicast Nodes 1 Switches 0 Reload Tree Start Stop PRIME Management G x PLME MLME PIBs SerialProfile PRIME Profile 432 wu Certification MFGTest BannedMACs macMinSwitchSearchTime 0x0010 Gete Set PIB 1 byte 0 to 255 or Ox Connected Serial COM47 B115200 Server 2099 Al t mM el The main window is split into three different areas Network Topology view This is the basic presentation in the main application window and it is always visible when is connected to a Base Node This view displays the logical network structure The structure is inferred analyzing the network events received from the Base Node In addition this view shows node information such as MAC LNID LSID SID firmware upgrade state firmware version model and ve
29. header files with functions definitions and PIB attributes for the MAC layer e mngp header file with functions for the Management Plane e conv header files with functions and definitions for the Convergence Layer including the Null SSCS and the IEC 4 32 SSCS e oss header and code files for OSS if using an OS Users must not modify any of the provided files except from the configuration files the HAL and the OSS Users are free to use the example applications as templates to create new user applications Users can also develop their own applications in the apps directory The first important thing to notice is that the user application and the PRIME FW stack are integrated as separated software applications Therefore Atmel provides two independent projects which generate two different files one binary file for the PRIME FW stack and another one for the user application They are e PRIME FW stack project prime_service_bin Zip e User application projects A PRIME user application project DLMS application It is an application example that shows how the PRIME API should be used This application configures the ATPL230AMB board as a Service Node with DLMS capabilities and simulates the data exchange between the Base Node and the Service Node The Service Node responds dummy DLMS messages after receiving data requests from the Base Node For this example a PRIME Concentrator is required Depending on the operation mode as a Rea
30. in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death Safety Critical Applications without an Atmel officer s specific written consent Safety Critical Applications include without limitation life support devices and systems equipment or systems for the operation of nuclear facilities and weapons systems Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military grade Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive grade
31. in the 32 bit address space mlong calls In order to build the project click on the Bui d Solution button or on Build gt Build Solution Make sure the SAM ICE cable is connected from your board to your PC through the J13 connector Power the ATPL230AMB board Then download the program in the internal flash of the SAM4C16C by clicking on the Start Debugging ol and break button ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 The first time Atmel Studio will ask to select the Debug Tool Select the on board SAM ICE the serial number in parenthesis differs from one board to another and check the programming settings combo box see Figure 6 12 Figure 6 12 Select tool instance APPS PHY_TESTER_TOOL X Build Build Events Toolchain Selected debuager programmer Dee SAM ICE 28011489 w Interface LAG el int Contant Panell E gege JTAG Clock 4 00MHz Manual Clock v JTAG Daisy chain settings Target device is not part of a JTAG daisy chain sce Position Name IRLength Device at position 1 has TDI pin connected directly to debugger Programming settings Erase entire chip v Boot selection Unchanged z Once programmed start the code execution by clicking on the green arrow P When the debug session is running the Stop button d allows you to stop the program execution and exit the debug session If you ju
32. in the Terminal window Figure 6 46 Main menu EP COMAS PuTTY The description of each field is the following e 0 Select buffer to transmit e 1 Select the attenuation level In this example is OO of attenuation and every step increments the attenuation in 3dB In the current firmware the maximum attenuation value is 10 S0dB e 2 Select scheme to transmit In this example we choose 4 that is DBPSK VTB e 3 Disable RX in transmission In this example is 0 e 4 Select mode to transmit In this example is PRIME 1 3 6 e 5 Select time period between messages to transmit ms 1000ms in this example 66 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 Enter data to transmit In this example data is fixed Select channel to transmit In this example is 1 Select coupling board in use ATPLCOUP001Vv1 in this example Config Auto Detect impedance Auto in this example View Tx configuration values Press v key of keyboard to check default configuration Execute transmission application Press e key in the keyboard to begin transmission and reception mode in both boards And press x key of keyboard to stop the transmission process e OD lt ON OH Default configuration is configured for ready for EMC tests e Coupling board ATPLCOUP001v1 CENELEC A band coupling board e TX channel 0 PRIME channel 1 e Buffer 0 Buffer O e Attenuation
33. is an application example that shows how to serialize the PRIME API when the user application is running in an external device See prime_service_modem atpl230amb zZip file e Atmel provides a USI Host drivers example usi host zip These files allow the user to integrate them in his own application and start the PRIME operation via serial communication with the PLC module It is composed by a set of functions identical to the ones described in the PRIME specification See doc43085 for more information e Scripts folder It contains the bin files and scripts to download easily the Service node PRIME stack and DLMS or modem application commented previously in the boards kit Also it contains a PRIME Base Lite Node script Atmel provides a binary file of a PRIME Base Lite Node This Atmel PRIME Base Lite Node version is limited to manage up to 10 Service Node connections This Base Node Lite lets us to communicate with ATMEL PLC tools and uses it to evaluate the Atmel PRIME Service nodes b Common software documentation folder It contains some application notes as the description of the Atmel PRIME firmware stack doc43085 It describes in detail all layers from the Atmel PRIME implementation as well as configuration options provided target ATPL230A EK Kit User Manual USER GUIDE 9 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 platforms default architecture all vendor specific PIBs and the provided solutions by At
34. level 0 0 dB e Modulation scheme PROTOCOL DBPSK VTB Differential BPSK with ViTerBi e Disable RX 0 RX enabled while board is emitting e PRIME mode MODE_TYPE_A PRIME 1 3 6 e Time period between frames 7000 1000ms e Data length 64 64bytes e Impedance Fix high High branch emission fixed Figure 6 47 Default configuration menu a a I kl IS rs le 1 bh j I In phy_tx_test_console C file are all the possible values of the parameters from main menu fields So for example if you want to use another coupling board Table 3 1 you have to change the coupling board default parameter So the possible values are e 1 ATPLCOUPOOO v2 e 2 ATPLCOUPOO1 vi e 3 ATPLCOUPOO02 vi e 4 ATPLCOUPO002 v2 ATPL230A EK Kit User Manual USER GUIDE 67 Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 e 5 ATPLCOUPO003_v1 e 6 ATPLCOUPO004 vi e 7 ATPLCOUPOO5 vi e 8 ATPLCOUPOOE6 vi During the transmission green led LEDO is blinking indicating test is running And the yellow led PLC on ATPLCOUP001 board blinks every time a PLC frame is sent Terminal window shows the following messages see Figure 6 48 In the reception board the red led LED1 blinks in every PLC frame reception i Respond to every action of main menu takes some time to the boards is not executed immediately Be patient Figure 6 48 Transmission messages EP COMAS PuTTY In case the configuration default h
35. non optimized FW the PHY Tester Tool project included in the kit with a default configuration in Tx mode and in Rx mode from a power consumption point of view and they highly depend on the architecture of the power supplies These measurements correspond to the whole PCBA design and not only to ATPL230A device All PCB peripherals are supplied i e SAM4C16C and ATPLCOUPO001 coupling board is emitting in channel 1 Refer to Atmel ATPL230A datasheet for an optimized power consumption measurement result 2 Output current of a 3Volts CR1225 battery ATPL230A EK Kit User Manual USER GUIDE 7 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 2 Evaluation Kit Overview ATPL230A is a PRIME modem for Power Line Communication that implements PRIME CENELEC FCC and ARIB profiles It has been conceived to be bundled with an external Atmel MCU ATPL230A is oriented in a wide range of Smart Grid applications such as Smart Metering Lighting Industrial Home Automation Home and Building Energy Management Systems Solar Energy and Plug in Hybrid Electric Vehicle Charging Stations ATPL230AMB is PLC multi purpose modem board based on the ATPL230A transceiver and on SAM4C ARM Cortex M4 microcontroller This development board provides a full featured platform to develop a complete communications system over Power Line Communication technology This document describes how to starting to work with the Atmel ATPL230 EK by explaining the
36. r n A G phy_tester_tool while 1 Ha G sam4ci6c_atpl230amb r Haier F E cont_board h DN conf_clock h c42364a_set_contrast 15 conf_hal h c42364a_clear_all H conf_phy h c42364a_show_icon C42364A_ICON_ATMEL son uat senalh c42364a_show_icon C42364A_ICON_USB Lp CES e c42364a_show_text const uint8_t PHYTST KI E conf_usi h _ CapMan E E coupling config Init process timers a Pott SCH F initTimerims h conf_atpl230 Ha G include Init Phy Layer La 4 source phy init void hal_app api SERIAL IF ENABLE La Output while 1 blink led 0 apps_phy_sniffer_tool_flash apps_phy_tester_toolflash oppe Oh f D S H Messages File Line Message mes Linking WI ndow Total number of errors 0 Total number of warnings 0 Status Ba bar 0 Warnings 0 Ln 38 Col 31 System NUM Let s have a closer look to the environment now Basically the environment is split into five different areas e Editor window allows you to edit the source files e Workspace window shows the project structure e Message window displays messages from the compiler e The Menu bar lets us the menu commands e The IDE toolbar available from the View menu provides buttons for the most useful commands on the IDE menus and a text box for typing a string to do a quick search e The Status bar at the bottom of the IAR Embedded Workbe
37. recently used version of your IAR Embedded Workbench that uses that file type regardless of which version the project file was created in The following figure shows the main window and its default layout 36 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 5 The IAR Embedded Workbench window Menu bar amea PLC examples TAR Embedded Workbench IDE Edit View toe sii Tools Window Help Fi Toolbar eeng e Blo cl SEA AHC EENEG DDD Debug PS Files SD Weg Main code entry point HO apps_phy_tester_tool_flash Debug v int saint void Ha G common af Ha Asam ifdef CONF_BOARD LCD EN Ha O boards status_code_t status a O atpl230amb endif Ha G arivers Ha G services ul_count_ms 500 count ms to blink led La G utils Ed t Ha G cmsis Prepare the hardvare or La samde prvSetupHardware S header_files d CR EI ifdef CONF_BOARD_UART_CONSOLE WI n OW Ha O preprocessor or Space R compiler h d UART ees LR F tat CES configure_dbg_ console e EE puts STRING_HEADER window E genase aG prime_ng Chal ifdef CONF BOARD LCD EN Ls ph Initialize the C42364A LCD glass component La G atpl230 status c42364a_init Ha G addons a if status STATUS OK Ha G apps puts LCD Initialization fails
38. signal can be isolated from the mains grid and that connector allows performing measurements of transmitted and received PLC signal without side effects noise coming from the grid 3 5 4 2 Reception stage The reception stage adapts the received analog signal to be properly captured by the internal reception chain Reception circuit is independent of the PLC channel which is being used It basically consists of e Anti aliasing filter RC Filter R49 amp C43 Figure A 5 e Automatic Gain Control AGC circuit The AGC circuit avoids distortion on the received signal that may arise when the input signal is high enough to polarize the protective diodes in direct region D10 Figure A 5 e Driver of the internal ADC The driver to the internal ADC comprises a couple of resistors and a couple of capacitors This driver provides a DC component and adapts the received signal to be properly converted by the internal reception chain 3 5 4 3 Transmission stage The transmission stage adapts the EMIT signals and amplifies them if required Figure A 4 It can be composed by e Driver A group of resistors which adapt the EMIT signals to either control the Class D amplifier or to be filtered by the next stage e Amplifier If required a Class D amplifier which generates a square waveform from O to Vopp is included e Bias and protection A couple of resistors and a couple of Schottky barrier diodes provide a DC component and provide protection from rece
39. the Base Node will not upgrade this node e Page Size Size of the data packets sent through the PLC line By default the AUTO option is 64 bytes e ARQ Enable or disable the ARQ protocol in the Base Node e Multicast Enable or disable PRIME multicast capabilities to transfer the firmware to a list of devices Figure 6 90 Firmware Upgrade view Firmware Upgrade oO x 2015 06 05 10 15 26 gt gt NetEvent MAC 01 40 90 87 00 74 STATE Registering 2015 06 05 10 15 26 gt gt NetEvent MAC 01 40 90 87 00 74 STATE Terminal 2015 06 05 10 16 16 gt gt FUP_ACK From Process FUP_VERSION REQUEST Info OK 2015 06 05 10 16 17 gt gt Version MAC 01 40 90 87 00 74 vendor ATMEL model SAM4CP 16BMB version 01 03 09 02 4 VI Time Configurations Delay Restart 60 Safety Timer 21600 File Configuration Page Size ARO Multicast Start Stop The Firmware Upgrade tab is used to update the PLC version of the Service Nodes For that e Click on the Firmware Update tab e Select the bin file that it has to be upgraded vendor and model must be the same between different versions e Keep the default values for all the parameters e Select the Service Nodes that need to be upgraded e Click the Start button To cancel a FU process use the Stop button or abort it from the Network Topology view The firmware upgrade process consists of two phases e Transferring the bm file from PRIME Network Manager to the Base Node by UART
40. 230A EK Kit User Manual UserGuide_03 Nov 2015 These J1 and J2 connectors are in bottom layer of ATPLCOUPO06 and they have the following part numbers e J1 SAMTEC FTR 130 54 L S e J2 SAMTEC FTR 124 54 L S The ATPLCOUPO06 board is directly powered from mains grid so hazardous voltage is present on the board To avoid user access to dangerous parts ATPLCOUP0O06 must always be used in its enclosure ATPLCOUPOO06 is a CE mark product that passes EN 50065 1 EN 50065 2 3 EN60065 7 EMC and FCC as current carrier system standards It also satisfies Pb Free and ROHS directive ATPLCOUPO06 dimensions are 51 5mm x 39 5mm x 18mm LxWxH The operating temperature range is about 40 to 85 C 5 4 Hardware description Hardware files are contained in the Hardware folder Hardware HW SCH amp PCB ATPLCOUPOO06v 7 ATPLCOUPO06v1 board is a PLC coupling driver board with double branch design and galvanic voltage isolation ATPLCOUPO06 has been designed to transmit in ARIB and FCC band especially in PRIME band from 151 to 472 kHz PRIME channels 3 4 5 6 7 and 8 lt has a good performance in terms of transmitted channel power over a range of load impedance values complying with FCC standard as current carrier system see FCC normative ATPLCOUPO06 is com posed of two transmission branches which only differ on the filtering stage A 12V power supply voltage for the class D amplifier is recommended to be used with ATPLCOUPO06 For more inform
41. 5 Figure 6 69 Jumper to enable AppEmu NI AU Uli P RESET Sw a XPLAINED PRO EXT See R31 Neg el ary Lab mo S et A oft E ei Doss E ogg Beet D4 d 5 ka Kaes ap Das Once T node opens a connection and Base node accepts it the exchange data test starts up automatically and the Service node shows the statistics of the test by UART1 If you want to see the Service node statistics in a serial interface tool i e PuTTy terminal you have to enable the define APP_EMU_DEBUG_ENABLE in app_emu h file see Figure 6 70 Figure 6 70 Enabling statics in UART1 58 INDENT ON 59 endcond di EE mode t app 53 APP Emu Task Rate 64 define APP_EMU_TASK_RATE 100 portTICK_RATE_MS 66 APP Emu Task Stack priority 67 define TASK_APP_EMU_PRIO tskIDLE_PRIORITY 2 GC APP Emu Task Stack definition 70 define TASK_APP_EMU_ STACK configMINIMAL_STACK_SIZE 5 Connect the USB cable to the micro B USB connector J9 and now configure the terminal Remember to select the COM port number assigned to the Standard COM Port so that UART1 After that set 115200 in the Speed field and in the Serial Category change the Flow Control to None The other fields should already be correctly configured Finally click Open E This application is only to configure the ATPL230AMB board as Service node Atmel does not provide the Base node application Modem application T
42. 5 1 1 Control of 3 3 volts power supply The ATPL230AMB provides activate or deactivate the 3 3 volts regulator by SHUTDOWN pin SHDN User can be deactivate the 3 3 volts regulator before enter in a low mode power consumption of SAM4C16C that can be powered by the battery This allows decrease the consumption of the board J4 lets us enable the 3 3 volts regulator always independently of SHDN pin By default this option is deactivated 3v3 is always on independently of the value of SHDN to activate this option remove the jumper in J4 Figure A 6 18 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 3 6 J4 enabling 3 3 volts jumper PRO E By default jumper J4 is set 3 5 1 2 Zero crossing detector A simple isolated circuitry U10 Figure A 2 is used to detect mains zero crossing events This VNR signal is used directly in the ATPL230A VZ Cross as well as in SAM4C16C microcontroller through an input PB11 port as another wake up condition Note By default the zero crossing detector circuit is not populated 3 5 2 ATPL230A PLC Transceiver 3 5 2 1 ATPL230A Overview The ATPL230AMB includes an ATPL230A U1 Figure A 3 PLC transceiver that is a PRIME compliant ASIC specifically designed for PLC Base and Service nodes PHY layer implementation ATPL230A has been conceived to be bundled with an ATMEL MCU running the Physical Layer API and being controlled by m
43. 6 explains the setup and operations required to create a smart PLC network using the included PRIME Service Node example and Base Node Lite binary This network communicates by means of PRIME PoweR line Intelligent Metering Evolution Finally chapter 6 7 introduces you the Atmel PRIME Manager tool This tool lets you establish a serial communication with the boards by means of Atmel Universal Serial Interface Note The software described in this manual is under the Atmel s Evaluation License Agreement pdf document You can find it in the Software folder 6 1 Introduction to the embedded system The purpose of this section is to guide new users through the initial settings of IAR Embedded Workbench or Atmel Studio AS and compile a PRIME PHY project The section shows setup of a PRIME project to generate a debug target that can be loaded into the microcontroller Kit projects are supported by IAR 7 10 1 version or AS 6 2 version or above From this point on it is assumed that a working copy of this IDE is installed in your computer The IAR s homepage http www iar com is a suitable source to download e 30 day time limited evaluation license And the Atmel s homepage http www atmel com is suitable for downloading the Atmel Studio 6 free download 6 1 1 IAR Embedded Workbench IAR Embedded Workbench is a high performance C C compiler assembler linker librarian text editor project manager and C SPY Debugger in an int
44. 65535 result D OL_432_ RESULT SUCCESS ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 109 Figure 6 110 Base node tool application window MIME Certification MFGTest Banned MACs Broadcast e E Ping Pong E Binary format DATA pen 05 06 2015 12 16 21 662 CL432_JOIN_INDICATE Serial ATMService01 Address 2 MAC 01 40 90 87 00 74 05 06 2015 12 18 03 321 DL432_DATA_INDICATION 38 bytes received from node 2 Atmel possibilities 05 06 2015 12 19 05 016 CL432_LEAVE_INDICATE Address 2 Connected Serial COM47 B115200 Server 9098 6 7 5 4 Using the Certification features tab Process to use the certification mode with the Atmel PRIME Manager tool for Base Node and Service Node should be e Select the Certification tab of Base node instance e Select the PHY in the combo box e Click Set CERT mode e Select the Certification tab of Service node instance e Select PHY v7 3 6 in the combo box e Click Set CERT mode e Select D8PSK in the Modulation combo box e You can modify the number of messages attenuation In this example we do not modify anything e Click Start Transmission e The executed operations appear in the Log output windows of both instances Notes 1 The Service Node must be registered in the Base node to perform this operation 2 For this example the Service node requires Serial protocol so it has been progra
45. 7 and 8 ATPLCOUPO06 mounts a double branch with voltage isolation from mains to the PLC coupling driver board The goal of this design is provided to the customers with a full performance transmission board in FCC band This board is not set by default in the ATPL230AMB board of the ATPL230A EK Figure 5 1 FCC and ARIB bands 3 3 3 S E S gt z e 3 kHz 73 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz kHz 42 89 97 144 151 198 206 253 261 308 315 362 370 417 424 471 5 2 Features The ATPLCOUPO06v1 board includes the following features e Specially designed to communicate in ARIB and FCC frequency bands 151 367 471 68 kHz e Voltage Isolation from mains with a transformer VAC 160403K5024X044 soldered in top layer board e Double branch each one for a range of impedances Low impedance optimized High impedance optimized Figure 5 2 ATPLCOUPO06v1 PLC coupling board Test point Test point Test point to measure the PLC signal TX led indication PLC transformer provides the voltage isolation from mains Beem Test point ATPLCOUPO06 vi Ab 5 3 Mechanical and user considerations ATPLCOUPO0O6 is delivered with the ATPL230A EK Board to board SMD connectors J1 and J2 are used to connect the ATPLCOUPO06 into connectors J6 and J7 of ATPL230AMB board Figure A 4 ATPL230A EK Kit User Manual USER GUIDE 29 Atmel 43075E ATPL ATPL
46. ER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure A 2 ATPL230AMB Power supply scheme La C24 DII 4 TuF SOV SMBJ48A V GND C65 KO 25 cls OOnF SOV DNP Cio wc DNP GND 1 14VA 2x115 2x12 230V gt D Jumper P2 P3 LISV gt D Jumper P1 P2 and P3 P4 10 CS 104 330pF MP2562 pm 3 R98 243K Figure A 3 ATPL230AMB Transceiver 2 Power Supply LOOnF W Fie aaie 000a Shot 2 of 8 echte Proed ATPL HAMBVA _ Vernea an L Power Supp soros TLP185 DI QSGREEN A Description ioma we _ Date Author Sheet 2 of 8 Atmel Code number me Power Supply TP C62 Q 27pF Cm3 C63 xxMHz 27pF PLC RX AGC 0 5 VRC VIPA VIMA PLCTX EL EMIT O 11 TXRXO TXRXI TXRXI PLC TX gt ATPL2xxA AKU Y PLC SPI MISO MOSI SCK CS EINT MISO MOSI SCK EINT PLC RST EE PLL INIT ARST SRST SRST ATPL230A C66 LOnF d frm ra oe SSES cx EE ggg VIPA Jkkiclelkielei DISIS S SIS S SIO S A vl se So author JG Propaan eg Fle ATPL2wAScHOo Description 11 17 2014 Sheet 3 of 8 11 14 2014 Date C103 100nF E Atmel Code ber ATPL230A EK Kit User Manual USER GUIDE 115 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure A 4 ATPL230AMB PLC Coupling Transmission scheme I 2 3 H PLC Cou
47. Le mains grid connection has been removed the analog comparator interrupt is triggered e Before going to backup mode configure PB23 as wake up port to return to active mode once power supply is available again The wake up events allow the microcontroller to exit the backup mode When a wake up event is detected the Supply Controller performs a sequence which automatically enables the core and the SRAM power supply and clocks See Figure A 7 for details Lack of activity on VZ CROSS signal PB11 can also be used to enter in backup mode 3 5 5 4 Tamper and Wake Up The purpose of backup mode is to achieve the lowest possible power consumption in a system that executes periodic wake ups to perform tasks but which does not require fast start up time Wake up events allow the device to exit backup mode Force Wake Up pin FWUP can be used as a wake up source In ATPL230AMB board FWUP has been connected to switch button SW3 Anti tamper pins TMP0 TMP3 detect intrusion for example into a smart meter case Upon detection through a tamper switch automatic asynchronous and immediate clear of registers in the backup area and time stamping in the RTC will be performed Anti tamper pins can be used in all modes Date and number of tampering events are stored automatically Tampering input 0 TMPO is connected to switch button SW2 Wake up pins multiplexed with anti tampering functions are possible sources of wake up as well in case an anti tamp
48. Link version is a USB powered JTAG emulator supporting Atmel ARM based microcontrollers Atmel SAM ICE is a JTAG emulator designed for Atmel SAMA5 SAM3 SAM4 SAM7 and SAM9 ARM core based microcontrollers including the Thumb mode It supports download speeds up to 720 Kbytes per second and maximum JTAG speeds up to 12 MHz It also supports Serial Wire Debug SWD and Serial Wire Viewer SWV from SAM ICE hardware V6 SAM ICE support is integrated in most professional integrated development environments IDEs such as IAR Keil and many others More details are available here http www atmel com tools ATMELSAM ICE aspx Figure 6 2 Atmel SAM ICE JTAG Note Evaluation kit does not provide an Atmel SAM ICE To use Segger tools with Atmel Studio 6 2 download Atmel s latest USB driver driver atmel bundle 7 0 712 exe from the following link https gallery atmel com Products Details 07bf16c1 444f 4ac8 8f40 9d4005575dca or take it from the PCTools folder PC Tools SAM ICE_Drivers And install the file J Link SAM ICE JTAG Probe Software amp Documentation Pack The J Link SAM ICE JTAG software and documentation pack includes ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 e GDB Server Support for GDB and other debuggers using the same protocol GUI amp command line version e J Link Configurator Free utility to manage a various number of J Links co
49. ME Manager Choose Users GP Choose for which users you want to install Atmel PRIME Manager p Select whether you want to install Atmel PRIME Manager for yourself only or for all users of this computer Click Next to continue Install for anyone using this computer Install just for me Select the users permissions and click Next Figure 6 73 Atmel PRIME Manager Installation process Welcome to Atmel PRIME Manager Setup Setup will guide you through the installation of Atmel PRIME Manager It is recommended that you close all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your computer Click Next to continue Click Next to continue ATPL230A EK Kit User Manual USER GUIDE 87 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Choose which features of Atmel PRIME Manager you want to install Check the components you want to install and uncheck the components you don t want to install Click Next to continue Select components to install Atmel PRIME Manager v1 Space required 89 8MB Nullsoft Install System v3 0a1 Choose the folder in which to install Atmel PRIME Manager Setup will install Atmel PRIME Manager in the following folder To install in a different folder dick Browse and select another folder Click Install to start the installation Space required 89 8MB S
50. MPLIED a conf_clock h WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF an conf_phy h MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT ARE oy conf_pplc_if h EXPRESSLY AND SPECIFICALLY DISCLAIMED IN NO EVENT SHALL ATMEL BE LIABLE FOR Gk cont suck cesta ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL ai BEE DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS gt SS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION ah HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE gt r a E TE Cy Solution il phy_tester_tool c Show output from XDK Packaging Output Window Error List El Output KREE Let s have a closer look at the environment now Basically the environment is split into three different areas e Atmel Studio Editor allows you to edit the source files e Solution Explorer shows the project structure e Output Window displays messages from the GCC compiler Once you have opened the apps phy tester tool ats n project you can see the PRIME PHY project structure expand the tree structure in the solution explorer area That structure is showed in the Figure 6 9 Building programming and debugging
51. Mac button This action is showed in section 6 7 5 5 6 7 5 Running the PLC application example 7 As you can see in Figure 6 91 the example s boards are plugged into the same power line In this PLC example one board is the Base Lite Node and the other one is the Service Node And users have to execute an instance of the Atmel PRIME Manager tool which has been previously installed in the host PC in order to enable communication between the Service node board and the PC In this example please note that it is only necessary to establish a serial connection between the board acting as a Service node and the host PC so only one instance of the PC tool is required This PC application can be found in the PC Tools folder PC Tools Atmel PRIME Manager SN Please remember that the provided PRIME Base Node is a lite version i e it is limited to manage up to 10 Service Node connections Default coupling board configuration for the projects is configured for ATPLCOUP001v1 coupling board When the Service node board is powered the green led D5 LEDO is blinking The Service node communicates with the Atmel PRIME Manager tool by means of a serial interface The main window of the Atmel PRIME Manager PC interface is shown in Figure 6 97 ATPL230A EK Kit User Manual USER GUIDE 103 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 97 PRIME Management view ATMEL PRIME MAN File Connection Vi
52. O e Transferring the bn file from the Base Node to the Service Nodes by PLC communication Once the firmware upgrade process has finished get the new PRIME version right click on the Service Node and compare with the previous PRIME version 98 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 i Atmel Studio projects provided in the kit do not support firmware upgrade process only IAR projects To uninstall the Atmel PRIME Manager tool from your computer go to Start gt All Programs gt ATMEL gt Atmel PRIME Manager vX Y Z gt Uninstall For further information of the Atmel PRIME Manager tool please refer to the tool s embedded help in the menu bar 6 7 PLC application 6 ATMEL PRIME Manager tool The Atmel Universal Serial Interface USI is a peripheral in the HAL that enables the handling of the different serial interfaces described in the PRIME specification through one or more serial ports always an UART It can also handle the serialization of the PRIME API in order to facilitate communication between an external application and the PRIME FW stack In this chapter we are going to describe the Atmel PRIME Manager tool for Service node Tool has the following tabs e PLME MLME PIBs e Serial Profile e MAC e 4 32 e PLME e MLME e Certification e ManuFacturinG MFG Test As the figure below shows the setup is composed of three different pa
53. PHY H INCLUDE 46 47 Select Coupling Board Config 43 define BOARD COUPLING 49 5 endif CONF_PHY_H INCLUDE gt 51 ation see values in atpl238 E ny ATPLCOUP 1_v1l gt Check the Table 3 1 for the characteristics of the available ATPLCOUP boards 6 4 5 Running the PLC application example 3 As you can see in Figure 6 49 the boards are plugged into the same power line Users have to execute an instance of the ATPL Multiprotocol Sniffer tool which has been previously installed in the host PC in order to enable communication between the sniffer board and the PC The ATPL Multiprotocol Sniffer tool is used to monitor data traffic on the network You can also use the ATPL Multiprotocol Sniffer tool to monitor the PLC messages which they do not belong the PRIME standard then the messages will be showed in red color and without PduType The main window of the Sniffer PC interface is shown in Figure 6 57 Figure 6 57 ATPL Multiprotocol Sniffer tool window i Am Maroc Saas File Configure Capture View About B57600 DB File ATPL log APPEND Once the application is launched the COM port for the board needs to be configured The COM port selection window is available by choosing Configure gt Input Ctrl l A new window Input Settings will appear as shown in Figure 6 58 First of all select the Power Line Communication protocol in this case PRIME After that select
54. PL230A PRIME device includes enhanced features such as additional robust modes and frequency band extension ATPL230A is able to operate in independently selectable transmission bands up to 472 kHz achieving baud rates ranging from 5 4 kbps up to 128 6 kbps e ATPL230A has been conceived to be bundled with an external Atmel MCU ATPL230AMB modem board mounts the ATPL230A transceiver and on SAM4C ARM Cortex M4 microcontroller This development board provides a full featured platform to develop a complete communications system over Power Line Communication technology e Evaluation platform performance for the Atmel ATPL230A to develop a complete communications system based on PLC technology Channel characterization Noise level measurement Sensitivity level measurement Maximum reachable distance Power consumption Possibility to verify the different standard frequency bands complying with the existing regulations CENELEC FCC ARIB setting the different PLC couplings boards Atransformer lets you supplied the board with universal 115 230 Vac 50 60 Hz power input 2 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Boards have a JIAG interface for MCU debugging and programming purposes and two debugging UARTs And also it provides Battery Backup and slow crystal oscillator to support SAM4C embedded Real time Clock RTC and low power modes Sev
55. PL230AMB board for the connection of a compatible ARM JTAG emulator interface such as the SAM ICE from Segger Notes 1 The NRST signal is connected to SW1 system button and also to an external reset signal available on the Base Node MIMO interface connector 2 The 0 ohm resistor R26 may be removed in order to isolate the JTAG port from this system reset signal 3 The TDO pin is in input mode with the pull up resistor disabled when the Cortex M4 is not in debug mode To avoid current consumption on VDDIO and or VODCORE due to floating input the internal pull up resistor corresponding to this PIO line must be enabled Please refer to the SAM4C16C datasheet for a further description of JTAG debug port 3 5 6 4 Debugging UARTs ATPL230AMB uarts UARTO and UART1 are user accessible by means of micro USB type B connector J9 Figure A 8 A single chip bridge is used to convert UARTs TTL CMOS to USB levels U8 Figure A 8 Note that this bridge is powered from USB 5V power supply so it is only available when USB cable is attached to any other USB host port That single chip drive CP2105 F01 GM of Silicom Labs has two ports The enhanced port is connected to UARTO and the standard port is connected to UART1 It is possible to power ATPL230AMB directly from USB connector However due to power limitations this option does not allow PLC transmissions Nevertheless this option is very useful for several applications such as FW downloading or debugg
56. See Figure 6 29 52 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 29 Communication enabled Welcome Product Information Summary Welcome to Atmel Multiplatform PhyTester this application allow you to test basic functionality of Atmel PLC products Please select the serial port in wich your Atmel board is connected to your PC Connection Serial Port BaudRate Altmel Enabling Unlimited Possibilities In case the tool cannot establish a communication with the board the tool shows the following error message Figure 6 30 Communication error a Description This tab shows information related with product identification model of the PCB and information about firmware version At the bottom of the tab it s necessary to select a choice between Transmision and Reception test Product Info lia Atmel PLC PHY Tester Tool d s Board is not responding please check serial port Test Selection Transmission Reception Atmel Enabling Unlimited Possibilities fe Il Next gt gt ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 53 Click the OK button and press Prev button to get back to Welcome tab Now press Disconnect button and check your connections Either you have not selected the right Enhanced COM port or the board is not supplied or the downloaded fi
57. TimeStamp Modulation mbc SNR ExSNR RSSI Channel Di e i 012091720178 0 255 Registered Number of nodes 365 2013 10 10T12 06 44 DBPSKCC 2 5 13 131 0 Connected Nodes SE ee ee ee eee D 0 061231824 3 3 6 Time s Number of Switches Number of switches 0 0 0 6 12 18 24 3 3 6 Time s Ti CAPTURING USB Serial Port COM100 B115200 DB File ATPL log sql APPEND To uninstall the ATPL Multiprotocol Sniffer tool from your computer go to Start gt All Programs gt ATMEL gt ATPL Multiprotocol Sniffer va Y Z gt Uninstall For further information please refer to the tool s embedded help in the menu bar 6 5 Introduction to PRIME Stack PLC is a medium with such special characteristics asymmetry noise variation in time etc that makes ita hostile environment for successful communication when users are not familiar with these issues The PRIME PoweR line Intelligent Metering Evolution initiative is a solution for an entire Smart Grid environment which will contribute definitively to energy efficiency improvement and ultimately to addressing the pressing issue of climate change PRIME defines lower layers of a PLC narrowband data transmission system over the electric grid All the system has been created to be low cost and high performance PRIME system is composed of sub networks each of them defined in the context of a transformer station A sub network is a tree with two types of nodes the Base Node and the S
58. _modem sam4c16c_atol230ambl as5_arm Software PRIME_vaa bb cc da prime_service_modem atpl230amb thirdparty prime_ng a pps prime_service_modem sam4c16c_atpl230amb llar Remember that the J Link USB drivers must have been downloaded previously from the Segger webpage see section 6 1 4 and they depend on your operating system An alternative process to load the Service node project and Base Lite node files should be as is explained below 1 Place the JTAG connector of the J Link or SAM ICE in the J13 JTAG connector of the board Check pin number 1 of J13 connector to place the cable in the right position 2 Switch on the power supply of the board 3 Go to script folder of Service Node Sofiware_vaa bb cc dd Scripts SN and edit the file pro gram_bin jlink Uncomment the apps_prime_service_modem_flash bin file and comment the apps_prime_service_dimsemu_ui_flash bin file After that save and close it 4 Download the binary file using a command script file see section 6 1 5 To do easier to load the bin file Atmel provides you a script for Service node program _bin bat and Base Lite node program_bin bai which lets you download the bn files in the right flash memory position You can find them in the following directories Software_vaa bb cc dd Scripts SN and Soft ware_vaa bb cc dd Scripts BN These scripts load the files and show an error when program ming process falls A typical error could be whe
59. a node unable to register Take into account that the projects store a MAC address in the Base Lite Node and another one in the Service Node If you have more Service Nodes the same MAC address is stored in all of them Since the MAC address must be unique for each node you should be careful in this situation because MAC must be unique By default every board has a MAC number preprogrammed which coincides with the serial number of the board label fixed in the enclosure Anyway if you want to change it see section 6 6 4 1 6 6 4 1 Setting MAC number In the Service Node project MAC address is defined but the user is free to change it A way could be configure the board in Manufacturing Test mode and sending a PIB to write the MAC Process should be setting the board in MTP mode send the PIB MTP_PHY_ENABLE Ox808E and send the PIB macEUI48 0x8100 with the desired MAC number You can use the Atmel PRIME Manager Tool go to PRIME management view and select MFG Test tab Once the Manufacturing mode has been enabled write the MAC number in the box and press Set Mac button This action is showed in section 6 7 5 5 6 6 5 Running the PLC application example 6 As you can see in Figure 6 77 the boards are plugged into the same power line In this PLC example one board is the Base Lite Node and the other one is the Service Node And users have to execute an instance of the Atmel PRIME Manager tool which has been previously installed in the
60. a project with AS Now you can create build program and debug the Atmel PRIME PHY Examples using the AS But before to do this you can configure and customize your project For example it is very important to enable line number display feature in Atmel Studio 6 2 editor For that e Access to Editor Function by clicking on Tools gt Options and access to All Languages window in the Text Editor tab e Enable the Display Line numbers function ATPL230A EK Kit User Manual USER GUIDE 41 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 42 Figure 6 10 Line numbers enabling Options b Environment Statement completion b Projects and Solutions Auto list members b Source Control E Hide advanced members 4 Text Editor e Parameter information General File Extension Settings All Languages Enable virtual space General Word wrap Tabs Assembler _ Show visual glyphs for word wrap Apply Cut or Copy commands to blank lines when there is no selection b Basic b CSS p GCC TTT d HTML VliLine numbers THrccecccessccveensseneasensccenees Display b JScript E Enable single click URL navigation b PL SQL E Navigation bar b Plain Text Note This page sets options for all languages To change options for only one language select the desired language from the tree on the left Another important feature is to disable the optimization in Atmel Stu
61. anager File Action View Help o gt co B oo S e Re a n ZARDTO024 E Batteries gt JE Computer gt Disk drives KS Display adapters gt vi DVD CD ROM drives gt De Human Interface Devices gt 4g IDE ATA ATAPI controllers gt Er Jungo gt 2 Keyboards gt D Mice and other pointing devices gt kk Monitors gt Sr Network adapters s Y Ports COM amp LPT Se Communications Port COM1 2 WW LE Silicon Labs Dual CP210x USB to UART Bridge Enhanced COM Port COM22 2 Ia Silicon Labs Dual CP210x USB to UART Bridge Standard COM Port COM23 gt D Processors gt e Sound video and game controllers gt 5 System devices F Universal Serial Bus controllers As you can see in the figure above the CP210x USB to UART Bridge Virtual COM Port VCP appears as two COM ports Enhanced and Standard COM ports in the Device Manager They are assigned the lowest available COM ports for operation In the ATPL230AMB design the Enhanced COM port corresponds to UARTO and the Standard COM port to UART1 so select the Enhanced COM Port when you use the Atmel PHY Tester PC tool 6 2 4 Programming the embedded file The boards of the kit are programmed with the embedded PLC PHY Tester tool firmware for SAM4C16C device apps phy tester _tool bin In this chapter we explain how to load an embedded file The process and tools to load the embedded file in the ATPL230AMB boards are always the same Remember that all the
62. ards It also satisfies Pb Free and ROHS directive ATPLCOUP0O01 dimensions are 51 5mm x 39 5mm x 18mm LxWxH The operating temperature range is about 40 to 85 C 4 4 Hardware description Hardware files are contained in the Hardware folder Hardware HW SCH amp PCB ATPLCOUPOO1v7 ATPLCOUP001 is a galvanic isolated reference design which provides a cost optimized PLC coupling reference design between 41 kHz and 89 kHz within the CENELEC A band It is based on a single branch design which filtering stage has a flat band pass response with typical field impedances ATPLCOUP0O01 has a good performance in terms of transmitted channel power with low impedances and complies with EN5065 1 EN5065 2 3 and EN5065 7 normative For more information see PLC coupling reference designs document doc43052 Take into account that when ATPLCOUP001 is connected to ATPL230AMB Von voltage must be 16 volts to avoid damaging the coupling board so jumper in J16 must not be set see section 3 5 1 and Figure A 2 By default the jumper is not placed Figure 4 3 Vpp selection in ATPL230AMB board a LULIS Jumper configuration Jumper J16 28 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 5 ATPLCOUP006 Hardware 5 1 Overview ATPLCOUP006 is a PLC coupling board designed to communicate in ARIB and FCC bands especially in PRIME band from 151 to 472 kHz PRIME channels 3 4 5 6
63. as been changed the board keeps the configuration unless power shutdown If board is reset while keeping power supply on it will restart the configuration mode after start up 6 4 PLC application example 3 PHY Sniffer In this example we present you the PRIME PHY Sniffer project APPS PHY _ SNIFFER TOOL PRIME PHY Sniffer project is able to monitor data traffic on the PRIME network by means of an ATPL230AMB board and the PC application ATPL Multiprotocol Sniffer For this example only one ATPL230AMB board is required and obviously a PRIME network to be monitorized The circuitry in the coupling boards has an influence in the reception itself As a consequence each coupling board is intended to be used in their corresponding frequency channel s only The application behaves properly when this correspondence is maintained 68 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 Figure 6 49 ATPL230AMB board connection scheme Atmel PRIME PHY Sniffer 6 4 1 ATPL Multiprotocol Sniffer tool Installation To install ATPL Multiprotocol Sniffer tool in a Windows Operating System execute the provided installer in the PCTools folder PCTools ATPL_Multiprotocol_Sniffer ATPL Multiprotocol Sniffer va Y Z exe and follow the installation wizard The installer wizard should open To follow the installation click Next process slide 1 Select whether you want to install Atm
64. as been installed on your computer Click Finish to dose this wizard Click Finish Now the program is installed in your computer and a shortcut should have been created in your desktop Supplying the boards Kits are provided with power cord cables in order to connect the boards to the mains Mains connector is shown below in Figure 6 20 Please connect the provided power cord cable with the kit to the Power Cord Connector J1 in order to supply the board Figure 6 20 ATPL230AMB mains and voltage jumper selector Jumper Voltage Selector 230 Vac option 4 i g Genee T JI eax Dk eo Note that the ATPL230AMB board can be supplied either with 100Vac or 230Vac by setting the proper jumpers in the voltage selector J2 as depicted in the Figure 6 21 By default voltage jumper is set for 230Vac For more information about power supply section see section 3 5 1 Figure 6 21 Jumper configuration for 100Vac or 230Vac Z230VAC 115VACI ATPL230A EK Kit User Manual USER GUIDE 47 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 2 3 USB connection By default the programmed firmware for Atmel PHY Tester tool establishes serial communication with UARTO Boards have such UARTO available either by micro B USB connector J9 or the triple pin row CMOS connector J16 See the figure below and sections 3 5 6 4 for more information about the USB device Kits are provided with tw
65. ation see PLC coupling reference designs document doc43052 Take into account that when ATPLCOUP0O06 is connected to ATPL230AMB Von voltage must be 12 volts to avoid damaging the coupling board so jumper in J16 must be set See section 3 5 1 and Figure A 2 By default the jumper is not placed Figure 5 3 Vpbp selection in ATPL230AMB board ms Ei ge STL pm 2 cna r Jumper configuration LP RAS AS A MEN Ea XPLAINED PRO EXT 1 0 Jumper J16 30 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 ATPL230A Evaluation Kit Getting started The purpose of this chapter is to introduce you the Atmel ATPL230A device and its functionalities First of all the software is presented to create build program and debug your application using the appropriate IDE tools section 6 1 Chapter 6 2 describes a simple PLC application that lets you check the device communication in a point to point connection PHY layer example Chapter 6 3 describes the PHY TX Test Console application which lets you configure a proper setup to perform both EMC emissions and immunity tests on ATPL230AMB board Chapter 6 4 describes the PRIME PHY Sniffer project which is able to monitor data traffic on the PRIME network Chapter 6 5 describes the PRIME Stack and we present you the structure of a PRIME project and how to create a final application Chapter 6
66. ber for this example the Service node requires PLME MLME protocol so it has been programed with prime_service_modem_atpl230amb project Process to close a 4 32 connection with the Service node tool instance should be e Select the 4 32 tab e Click Release e The executed operations appear in the Log output windows of both the Service and Base nodes tool instances See the figures below e f you see the Base node tool instance you have received the leave indication message and in the Service node window appears the release confirm Note The Service Node must be registered in the Base Node to perform this operation Figure 6 109 Service node tool application window ATMEL POE meet lll ca File Connection View Help PRIME Management _PLME MLMEPIBs Serial Profile MAC 432 E Run DUMS Emu Deivee ID ATMService0 1 Ping Pong F Binary format DATA Atmel Enabling unlimited possibilities Num Chars 38 05 06 2015 12 16 21 505 CL432_ESTABLISH request sent device_id ATMService01 05 06 2015 12 16 21 624 CL432_ES5TABLISH_confirm received device_id AlMServiceO1 dst_address 2 base address 0 05 06 2015 12 18 03 145 CL432_DL_DATA REQUEST 38 bytes sent to base 05 06 2015 12 18 04 270 CL432_DL_DATA confirm received deit kan 1 src_Isap 16 dst_address 0 be status 0 05 06 2015 12 19 04 858 CL432_ RELEASE request sent dst_address 2 05 06 2015 12 19 05 003 CL432_RELEASE confirm received dst_address
67. board based on the ATPL230A PRIME PLC transceiver and on the SAM4C16C ARM Cortex M4 microcontroller ATPL230AMB modem board provides a platform to develop a complete communications system over PRIME PLC technology Figure 3 1 ATPL230AMBV4 board Features The ATPL230AMBV4 board includes the following features e Power supply Non switched ACDC isolated power supply 100 230Vac 50 60HZz 5 volts rail is accessible by means of a DC Jack connector J15 e ATPL230A PRIME Transceiver Power Line Carrier modem for 50 and 60 Hz mains 97 carriers OFDM PRIME compliant DBPSK DQPSK D8PSK modulation scheme available Additional enhanced modes available Robust modes Configurable single transmission channel from 42 kHz to 472 kHz CENELEC A FCC ARIB Baudrate selectable from 5400 to 128600 bps Automatic Gain Control AGC and signal amplitude tracking Viterbi soft decoding and PRIME CRC calculation 128 bit AES encryption ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Channel sensing and collision pre detection e Support to PRIME PLC coupling boards ATPLCOUPXXxX e Mains zero crossing detector circuit e SAM4C16C MCU ARM Cortex M4 e External Memories Serial EEPROM do not populate DataFlash memory e Peripherals Voltage monitor Back up battery holder Users LEDs Force Wake Up switch button Tamper switch but
68. c overviews of the libraries used and the description of the whole system integration FreeRTOS PRIME PLC ATPL230A and the SAM4C in one project using the ASF structure FreeRTOS FreeRTOS is a real time kernel or real time scheduler on top of which Cortex M3 M4 microcontroller applications can be built to meet their hard real time requirements It allows Cortex M3 M4 microcontroller applications to be organized as a collection of independent tasks to be executed The kernel decides which task should be executed by examining the priority assigned to each by the application designer In the simplest case the application designer could assign higher priorities to tasks that implement hard real time requirements and lower priorities to tasks that implement soft real time requirements This would ensure that hard real time tasks are always executed ahead of soft real time one Thanks to the FreeRTOS scheduler we are able to optimize PRIME code and memory usage Although the SAM4C16C has two cores we will run the PRIME project only in the core 0 ASF Integration As it was explained before ASF has a defined structure ASF root folder contains the common directory the sam directory and the thirdparty directory The components contents of thirdparty directory are showed in the following figure That is the way to integrate the whole platform in this structure PRIME PLC SAM4C and FreeRTOS Figure 6 66 SAM4C amp PRIME Integration in thir
69. cription This tab shows information related with product identification model of the PCB and information about firmware version At the bottom of the tab it s necessary to select a choice between Transmision and Reception test Product Info Product Id SAM4CP 16B Model Id 0x0000 Firmware Id 0x23000200 Reception Alttmel Enabling Unlimited Possibilities Once the transmission option is selected click the Next button The Transmission Parameters tab appears Figure 6 37 that allows you to configure the PLC coupling board plugged and the transmission parameters e PLC coupling board Different boards are defined for different band plans and isolation modes e Channel It allows selecting the channel in which the frames are going to be transmitted depending on the coupling plugged to the board different channels can be available e Frame Type Configure the board to transmit frame type A B or C e Modulation Scheme Configure the modulation scheme for frames e Attenuation Level It allows attenuating the output certain amount of dBs 0 21 dB e Branch Configuration It configures the output stage depending on the kind of impedance presented to the board e Perform EVM Test Selecting the option Perform EVM Test you can change the message and interval of transmission in order to make a test that evaluates the PHY layer performance For more information check application note 43072 PHY_Performance_Verification
70. cted a Service Node starts in a disconnected state In this state a node is not capable of communicating or switching the traffic of another node The primary function of a Service Node in this state is to search for an operational network in its proximity and to try to register itself to it e Terminal in this state a Service Node is capable of communicating by establishing connections But it is not capable of switching the traffic of any other node e Switch in this state a Service Node is capable of performing all Terminal functions Additionally it is capable of forwarding data to and from other devices in the sub network It is a branch point in the tree ATPL230A EK Kit User Manual USER GUIDE 77 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 The current PRIME standard specifies a transmission system based on OFDM modulations scheme The OFDM PRIME PHY specification uses the frequency band from 41 992 kHz to 88 867 kHz 47 kHz bandwidth This is achieved by using OFDM modulation with signal loaded on 97 96 data and one pilot equally spaced subcarriers Differential modulation is used with one of three possible constella tions DBPSK DQPSK or D8PSK The ATPL230A architecture provides enhanced performances over the PRIME specification with the new robust modes and the ARIB FCC frequency band extension The PRIME 1 4 has two additional robust modes e Robust DQPSK e Robust DBPSK Thanks to this new performa
71. d Otherwise the board could be seriously damaged Select Coupling ATPLCOUPOO1 vi mA Reception Parameters Channel Ch 1 Perform EVM Test Altmel Enabling Unlimited Possibilities This tab allows you to configure the channel reception of the PLC coupling board and the PLC coupling board plugged Note the warning message displayed before to continue check the proper voltage to use Vpp selection In this tab you can select one of the eight channels 1 to 8 and one of the five PLC coupling boards designed by Atmel In this example the firmware load is for ATPLCOUP001 board so that it is only designed for PRIME channel 1 Selecting the option Perform EVM Test you can change the message and interval of transmission in order to make a test that evaluates the PHY layer performance For more information check application note doc43072 The Perform EVM Test box is disabled by default Click the Next button to continue The next tab shows the RX Test Parameters see Figure 6 33 This tab is where the following reception test parameters are configured e ime Interval milliseconds expected interval between frame transmissions e Number of Frames number of frames to be received e Message ASCII message expected ATPL230A EK Kit User Manual USER GUIDE 55 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 56 Figure 6 33 RX test parameters Product Information Reception Parameters
72. dialog The available options in this dialog depend on whether a firmware upgrade process is running or not If not running nodes can be added to and removed from the list When the process starts the Remove option is disabled but the Abort option is enabled so that the upgrade process can be cancelled any time It is always possible to add nodes to the list Figure 6 89 FU dialog ex r FU Manage Dp Add to FU list O Remove from FU list Abort FU BABA 30 01 84 ZE This dialog only adds the nodes to the Firmware Upgrade but the process does not start when the OK button is clicked The next section describes how to start the Firmware Upgrade Process 6 6 5 2 Firmware Upgrade In case you want to upgrade the firmware of the Service nodes from the Base node you have to use the Firmware Upgrade tab There are some parameters to configure the FUP ATPL230A EK Kit User Manual USER GUIDE 97 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 e Delay Restart Time in seconds that a device must wait before performing a restart after receiving the new firmware e Safety Timer Time in seconds that a device waits to get back to the previous firmware version if the upgraded node is not able to register e File Filename of the new firmware version e Match Rules When marked the Base Node checks that vendor and model firmware of the Service Node match those of the new firmware If they do not match
73. dio 6 2 editor when you are in Debug mode to avoid jumping into the lines of code without order due to the optimization For that e Access to Project Properties by clicking on Project gt Properties and access to Toolchain window in the Project Properties tab e Select Optimization option in ARM GNU C Compiler main tree e Select None option in the display Optimization Level function Figure 6 11 Optimization option window APPS_PHY_TESTER_TOOL GE Build Configuration Active Debug k Platform Active ARM hd Build Events T Ich ER Configuration Manager oolchain Device agf ARM GNU Common ARM GNU C Compiler z Optimization EF General Tool E OutputFiles Optimization Level None O0 hd 4 IS ARM GNU C Compiler Advanced g General Other optimization flags fdata sections Preprocessor Symbols V Prepare functions for garbage collection ffunction sections Prepare data for garbage collection fdata sections 4 Linz G E Warnings E Miscellaneous 4 Z ARM GNU Linker Ef General EF Libraries Ef Optimization E Memory Settings E Miscellaneous E Ej ARM GNU Assembler Ef General Debugging 4 El ARM GNU Preprocessing Assen General bi Symbols EF Debugging d m r Enable unsafe math optimizations funsafe math optimizations E Enable fast math ffast math Generate position independent code fpic d Allow called functions be located anywhere
74. dparty folder se PRIME Library layer stack SEHR E FreeRTOS components PER WE Hardware components Software Stack Drivers i H PLC ATPL230AMB Low evel MCU driv rs SAM4C family SAM4C1 6C mmm Hardware board abstraction ed AVR Target Board We integrate the different parts according to the ASF structure e Boards The ATPL230AMB board hardware mapping is defined here e Drivers The drivers for the SAM4C Family e Services We offer the PLC modem as a service e ThirdParty We add in this point the PRIME and FreeRTOS libraries ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 19 It happens that last version of the Atmel Software Framework provided version in the web link at this moment release ASF 3 27 September 2015 does not coincide with the PLC libraries of the projects from the kit s Software folder PLC libraries of the kit are an above version that ASF gt In the release notes document about the PRIME version appears the individual version layers of PHY MAC and SSCS432 Take into account previous to download futures releases of ASF if it is supported by these kit s version boards In case you do not know the ASF version downloaded in Atmel Studio go to Helo gt Atme Studio Select in the combo box of the new window the component Atmel Software Framework After that all the versions installed are showed 6 5 3 Atmel
75. e SAM4C16C The ATPL230AMB Multi purpose board includes the possibility to mount a serial EEPROM memory connected by Two Wires Interface U2 Figure A 7 with the SAM4C16C Please refer to AT24Cxx datasheet for a further description on Atmel s website ATPL230A EK Kit User Manual USER GUIDE 23 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 3 5 5 2 SAM4C MCU Real Time Clock and back up battery SAM4C16 MCU embedded Real Time Clock RTC can be used as calendar and time base counter A back up battery Figure A 6 slow clock crystal and low power modes are required to keep the RTC running during power down or mains unplugged conditions The ATPL230AMB includes a Battery BT1 Figure A 6 for maintain active the RTC when the power supply of 3v3 shutdown and SAM4C16C enter in a low power mode J18 jumper lets us supply the board with the battery setting the jumper between VDDBU and BATT position Figure 3 10 J18 jumper in battery position By default jumper J18 sets VDDBU to 3V3 supply 3 5 5 3 Voltage Monitor The ATPL230AMB monitors Vpop and 5V voltage rails to detect backup mode entering conditions and also wake up events by means of its dedicated hardware 5V falling condition is the most recommended trigger event to enter backup mode on ATPL230AMB design e Configure PB23 as positive input of analog comparator and compare it with AREF e Once 5V rail falls below 4 5V depending on R70 R74 values
76. e boards must not be subject to high electrostatic discharge We recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments Avoid touching the components pins or any other metallic elements on the board Note that kit does not provide any battery The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM4C device when the board is switched off 10 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 2 1 Packed Atmel ATPL230A EK a U ech oO co E sl Figure 2 2 Unpacked Atmel ATPL230A Evaluation Kit Atmel ATPL230A EK Ke Ba s x E be AE ZE Ki wi da zs 3 te di vr o gt War a 3 CD Se On eg i Sa U 309 j SS II c 534 SS S ATPL230A EK Kit User Manual USER GUIDE 11 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 2 3 ATPL230AMB Modem board NNN AU Lan i LF UU Seat ro al eile a Gs VUEN XPLAINED PRO ExT It T ITEL a Ti H i cr es HF vu SS ey oo J 3 f a ua a oa a _ ii i em WW ATPL230AMB v4 E i ai ATELZS0AMB vi iia i Be e Both ATPL230AMB boards are provided with an example application preprogrammed the PHY Tester embedded software for SAM4C16C After installing the
77. eO 1 Address 2 MAC 01 40 90 87 00 74 Connected Serial COM47 B115200 Server 9098 When the 4 32 connection is opened the Service Node receives a confirmation Figure 6 105 Service node tool application window t ATMEL PRIME MANAGER 207 Te File Connection View Help PRIME Management Run DLMS Emu Deivee ID ATMServiceO1 Binary format DATA Nu Chars o 05 06 2015 12 16 21 505 CL432_ESTABLISH_request sent device Wl ATMService01 05 06 2015 12 16 21 624 CL432_ESTABLISH_confirm received device_id ATMService01 dst_address 2 base_address 0 6 7 5 2 Sending messages Once the communication is established we can send data between Service node and Base node For example in this case we send a message from Service node to Base node Process should be e Inthe 4 32 tab type a message as Atmel Enabling unlimited possibilities e Click Send e Inthe Log output of the Base node instance we receive the sent data ATPL230A EK Kit User Manual USER GUIDE 107 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Note The Service Node must be registered in the Base Node to perform this operation Maximum size of the 4 32 packet that we are able to manage is 1000 bytes When the option Binary format DATA is marked the messages must be introduced in hexadecimal format otherwise ASCII format is used The received messages are also shown in such format Figure 6 106 Service node tool
78. eans of a serial synchronous communication interface SPI Please refer to ATPL230A datasheet on the Atmel website or in doc43053 for a detailed description 3 5 2 2 ATPL230A Clocking ATPL230A requires a 20MHz crystal oscillator Y3 Figure A 3 And SAM4C16C requires a 12 MHz crystal oscillator Y1 Figure A 6 The 20MHz clock signal could be used as internal reference time of the PLC modem ATPL230A and also to generate a 12MHz So it could be connected the output clock signal CLKOUT of ATPL230A like an input clock CLKIN of SAM4C16C when ATPL230A is configured in bypass mode In this way only one high frequency crystal oscillator is required For this option that is mounted by default in the board R85 is soldered but R67 and R68 are not populated and remember that ATPL230A must be configured properly Clocking item is widely detailed in the datasheet doc43053 3 5 3 SAM4C16C Flash Microcontroller 3 5 3 1 SAM4C16C Overview The Atmel SAM4C16C microcontroller U4 Figure A 6 is a system on chip solution for smart energy applications built around two high performance 32 bit ARM Cortex M4 RISC processors It operates at a maximum speed of 120 MHz and feature up to 1MB of embedded Flash 152 Kbytes of SRAM and on chip cache for each core ATPL230A EK Kit User Manual USER GUIDE 19 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 The peripheral set includes advanced cryptographic engine anti tamper floating poin
79. ed ATPL230AMB is a CE mark product which passes EN60950 1 safety standard and EN50065 1 EN50065 2 3 EN600065 7 EMC and FCC as current carrier system standards It also satisfies Pb Free and ROHS directive ATPL230AMB supply voltage is taken from mains grid 100 230Vac 50 60Hz J1 connector ATPL230AMB dimensions are 165mm x 114mm x 30mm LxWxH and the enclosure dimensions are 174 4mm x 123 9mm x 38 5mm LxWxH 16 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 The operating temperature range is about 10 to 85 C 3 5 Hardware description In this section the modules of the ATPL230AMBv4 board are described Take into account that the board s BOM is not a final design so they include devices that could be no necessary in the customer designs once the design has been optimized Hardware files are contained in the Hardware folder Hardware HW SCH amp PCB ATPL230AMBv4 3 5 1 Power supply ATPL230AMB board can be powered either with 100Vac or 230Vac by setting the proper jumpers in the voltage selector J2 Figure A 2 J1 IEC 320 C8 connector allows cable connection to mains grid This design uses an encapsulated transformer T1 Figure A 2 plus a full bridge rectifier D1 Figure A 2 to obtain a DC voltage without increasing noise in PLC frequency bands 42 to 472 kHz as may occur with switched ACDC power supplies F1 and VR1 are used as protective devic
80. eddsGecectidieaicedeases 89 6693 USB CONMECH OM ccacnissenareeoqccosesiisatecoctseudecuicsenodeceecunaeawsahosaeesoucacnssenodeamsausaectaetureuesansacnnseneceieseveast 89 6 6 4 Programming the embecdded ies 89 6 6 5 Running the PLC application example pe 90 6 7 PLC application 6 ATMEL PRIME Manager Tool 99 6 7 1 Atmel PRIME Manager tool installation ccccccccccsseeecseeeeeeeeeeeeceeeeeeseeeeeeeeeeeesaeeeeesaeeeenas 100 672 Supplying ihe Doai ieres oiei ieie aeai a ieoi aaeei eia 102 Oro EE COSC e E 102 6 7 4 Programming the embecdded ies 102 6 7 5 Running the PLC application example 103 la E e e 113 Appendix A Board schemes ccccccsceeseeeesecenseeeseeenseeeneeeesesenseoeneeeaseeeneeoeseneaeeoeaes 114 A1 AIPL230AMBv4 Ee 114 A2 AIPLCOUPOUTV Een E 119 PROVISION HMISIOTY E 121 ATPL230A EK Kit User Manual USER GUIDE 5 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 1 Evaluation Kit Specifications 1 1 Safety recommendations These development boards must be only used by expert technicians ATPL230AMB is directly powered from mains grid so hazardous voltage 100 230Vac is present on the board To avoid user access to dangerous parts ATPL230AMB must always be used within its enclosure All required connectors and configuration jumpers are easily accessible without electrical shock risk A normal use of ATPL230AMB does not require removing the IMPORTANT enclosure cover I
81. egrated development environment for applications based on 8 16 and 32 bit microcontrollers IAR Embedded Workbench is compatible with other ARM EABI compliant compilers and supports the SAM4C core family example projects are developed only for 7 10 1 versions or above 6 1 2 Atmel Studio 6 Atmel Studio 6 is the integrated development platform IDP for developing and debugging Atmel ARM Cortex M and Atmel AVR microcontroller MCU based applications The Atmel Studio 6 IDP gives you a seamless and easy to use environment to write build and debug your applications written in C C or assembly code Atmel Studio 6 is free of charge and is integrated with the Atmel Software Framework ASF a large liorary of free source code with 1 600 ARM and AVR project examples ASF strengthens the IDP by providing in the same environment access to ready to use code that minimizes much of the low level ATPL230A EK Kit User Manual USER GUIDE 31 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 32 design required for projects Use the IDP for our wide variety of AVR and ARM Cortex M processor based MCUs including our broadened portfolio of Atmel SAM3 ARM Cortex M3 and M4 Flash devices Figure 6 1 Atmel Studio 6 a Atmel Powered by Visual Studio Download the latest version from the following link http www atmel com microsite atmel_studio6 Atmel SAM ICE JTAG Probe Atmel SAM ICE a dedicated Atmel J
82. el Reading device ID OK Getting daisy chain configuration OK PHY Tester Tool project has been created for the default PLC coupling board ATPLCOUPO01v1 So if you are going to use another coupling board you must build the PHY Tester Tool project with the correct configuration For that open the IDE tool used and open the project application apps _phy_tester_tool atsin or apps Div Tester Tool ew After that select the file conf_phy h that tt is located in the PHY project configuration directory Software PRIME_vaa bb cc dd ohy atol230amb thirdparty prime_ng phy atol230 apps phy_tester_to ol sam4ci6c_atpl230amb find the define function to select the coupling board configuration see Figure 6 25 Change the board name to desire board and build to generate the output file 50 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 2 5 Figure 6 25 Coupling board configuration definition 44 Ei ifndef CONF_PHY_H INCLUDE 45 define CONF PHY H INCLUDE 46 47 Select Coupling Board Configuration see values in atpl230 h 48 deTine BOARD COUPLING ATPLCOUP 1 w1 49 Sp endif CONF Div H INCLUDE 51 Running the PLC application example 1 The Atmel PLC PHY Tester tool is used to control the application running on the SAM4C16C ATPL230A As you can see in Figure 6 26 the two boards are plugged into the same power line Users have to execute two
83. el ATPL Multiprotocol Sniffer for yourself only or for all users of this computer Click Next to continue Install for anyone using this computer 5 Install just for me Nullsoft Install System v2 46 Select the users permissions and click Next ATPL230A EK Kit User Manual USER GUIDE 69 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Welcome to the Atmel ATPL Multiprotocol Sniffer Setup Wizard This wizard will guide you through the installation of Atmel ATPL Multiprotocol Sniffer It is recommended that you dose all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your computer Click Next to continue Click Next to continue Figure 6 52 Installation process slide 3 gt Atmel ATPL Multiprotocol Sniffer Setup your employer Licensee and Atmel Corporation Atmel By cdicking the I Accept button or by downloading installing or using any of the software available for download Licensed Software you are indicating that you are binding Licensee to the terms of this Agreement and that you are duly authorized by Licensee to do so If you are not authorized to bind Licensee to the terms of this Agreement or if Licensee does not agree to be bound by all of the terms of this Agreement do not dick the I Accept If you accept the terms of the agreement dick I Agree to continue You must accept the
84. er a system restart is avoided and the user application can continue execution although the PRIME FW stack has changed 6 6 PLC application 5 PLC Network In this chapter the example proposed is used to show the capabilities of the ATPL230A in a network of smart devices One ATPL230AMB board acts as a Base Node i e the device that controls the whole network whereas the other one ATPL230AMB board acts as Service Node A PC tool is used to monitor and manage the Base Lite node called Atmel PRIME Manager v1 a b This tool allows you to monitor data traffic on PRIME networks and gather information of a PRIME network 86 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 And even displays information about the devices connected to the network MAC address logical address and status and the evolution of the network Following sections explain to you how to install the PC tool select the projects supplying the boards select the COM ports to communicate with the ATPL230A and run the application 6 6 1 Atmel PRIME Manager tool installation To install Atmel PRIME Manager v1 a b tool in a Windows Operating System execute the provided installer in the PC Tools folder PC Tools Atmel_PRIME_Manager BN and follow the installation wizard The installer wizard should open To follow the installation click Next Figure 6 72 Atmel PRIME Manager Installation process Atmel PRI
85. er Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 101 6 7 2 6 7 3 6 7 4 102 Click Finish Now the program is installed in your computer and a shortcut should have been created in your desktop Supplying the boards Please refer to 6 2 2 in order to know how to supply the ATPL230AMB boards USB connection Please refer to 6 2 3 in order to Know how to connect the micro USB cable with the ATPL230AMB board Programming the embedded files It is commented in section 6 6 4 the way to program a board To program the board as Service node process should be the same building the IDE projects and downloading into the board Note that kits do not provide a J Link ARM or SAM ICE JTAG probe in order to connect to the user s host PC and the boards to download and debug the projects Remember that PRIME FW Stack project is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic e binisam4cp16b_sam4cp16bmb_gcc as5_arm Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic e bin isam4co16b_sam4cpo16bmb_iar iar Remember that modem application project running as microcontroller mode is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc da prime_service_modem atpl230amb thirdparty prime_ng a pps prime_service
86. eral wake up conditions are available such as mains crossover detection and voltage rails recovery condition e Software application examples available based on PRIME Stack Atmel provides an Atmel PRIME PHY layer library which is used by the external MCU to take control of ATPL230A PHY layer device Three example projects about the PRIME PHY layer are provided with the kit And also the Atmel PRIME Stack for Service Node and some user applications ATPL230A EK Kit User Manual USER GUIDE 3 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Table of Contents 1 Evaluation Kit Specifications cccccceseseesseseeceneesenseeceseeeenseseeseesensesenneeseneesoeseeseas 6 11 Safety recommendations isieseseriece eanes Annaa SE EEEE EEOSE ESENE KESE ENESESSE 6 1 2 Electrical characteristics A 6 2 Evaluation Kit OVErview cccccccsseessseeeneeceseeenseceneecassseasesensecasesoaeesenssensesenseoenesons 8 ig Bosign SUDO EE 8 22 ATITPL2S0A EK COMING egene 8 e ZE a TE CH Ee UE 14 aa VENON eee ee ee eee ee 14 EE 14 T HIGH CACM EE 16 3 4 Mechanical and user considerations 00nnnnannnnannnnennnnennnnnnrnnunrrnnrrnnnrnrnnrrnnnrrnnnrrnnnrrnnnrrennrrnnrreneni 16 3 5 Hardware description WE 17 Sal PONS ele EE 17 352 ATPL2ZG0A PLC TranSCe iver sicccncnccanscedencesceudesnsasuainasncedccosneadeamasismdesmnacedgesserwaceacoanedienenlandcomecdoties 19 35 0 SAM4C16C Flash MICKOCOMU ONCE
87. ering event is detected 24 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 3 5 5 5 User leds The board incorporates two user LEDs LEDO amp LED1 green and red D5 amp D6 Figure A 7 connected to PB14 and PB15 respectively of the SAM4C16C 3 5 6 Interface Ports 3 5 6 1 Reset circuitry ATPL230AMB can be manually reset by using a push button SW1 Figure A 8 or by means of an external reset signal available on the Base Node MIMO interface connector This reset restarts the SAM4C16C and the ATPL230A include his PLL Also ATPL230A shall be reset from SAM4C16C with an asynchronous reset by PC6 and with a synchronous reset by PC7 see Figure A 8 3 5 6 2 ATPL230A SPI ATPL230AMB provides the option to connect the SPI the Reset and the interruption signal of ATPL230A device with an external microcontroller This option is available in a 5 pin dual row male header J3 Figure A 8 allowing others Atmel development boards make use of the ATPL230A PLC transceiver For enable this option is necessary do not placed R17 R32 R35 R39 and R41 and solder R2 R18 R33 R38 R40 R42 and R50 lt is recommended to avoid unintentional reset do not placed R43 R44 and R45 3 5 6 3 SAM4C JTAG Debug Port The SAM4C16C JTAG interface is available in a standard 20 pin male header J13 see Figure A 8 for debugging and programming purposes The JITAG ICE connector is implemented on the AT
88. ervice Node 76 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 63 A typical PRIME network Base Node UPLINK a Sa Level 0 DOWNLINK Level 2 The Base Node is the root of the tree and acts as master node that provides connectivity to the sub network It manages the sub network resources and connections There is only one Base Node ina sub network This Base Node is initially the sub network itself and other nodes should follow a process of registering in order to join this sub network Any other node in the sub network is a Service Node Service Nodes are either leaves of the tree or branch points of the tree These nodes start in a disconnected state and follow certain procedures to establish network connectivity Each of these nodes is one point in the mesh of the sub network These nodes have two responsibilities connecting themselves to the sub network and switching the data of their neighbors in order to propagate connectivity Service Nodes change their behavior dynamically from Terminal functions to Switch functions and vice versa Changing of functional states occurs based on certain predefined events in the network Figure 6 64 Functional states of a Service Node Unregister Promote jow q Register Unregister Terminal As shown in the previous figure the three functional states of a Service Node are e Disconne
89. ervice node which opens the 4 32 connection The process is the showed in Figure 6 102 Figure 6 102 PRIME 4 32 connection request BASE NODE ON REQ_S ON pe Note For this example the Service node requires PLME MLME protocol so it has been programed with prime_service_modem_atol230amb project Process to open a 4 32 connection with the Atmel PRIME Manager tool in the Service node should be e Select the 4 32 tab e Click Establish e The executed operations appear in the Log output windows of both the Atmel PRIME Manager tool in the Service and Base nodes instances See the figures below Note The Service Node must be registered in the Base Node to perform this operation Service Node sends the request and when the 4 32 connection is opened the service node receives a confirmation 106 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 103 Service node tool application window ee File Connection View Help PRIME Management Run DLMS Emu Deivee ID ATMService01 Ping Pong Binary format DATA um chars 0 05 06 2015 12 16 21 505 CL432_ESTABLISH_request sent device id ATMService01 At the same time you will receive the 4 32 notification in the Base node Tool instance Figure 6 104 Base node tool application window Z Ping Pong Z Binary format DATA one 05 06 2015 12 16 21 662 CL432_JOIN_INDICATE Serial ATMServic
90. es in the equipment input and F2 protects the transformer output against over current situations x By default the voltage jumpers configuration is for 230Vac See Figure 6 20 The maximum transformer output power of 14VA is oversized compared to the maximum current consumption of ATPL230AMB when it is used as a PLC Service node However this design is intended to power up other development kits which may have considerable power consumption if they include components such TFT displays The unregulated DC voltage is used as input of the DCDC buck converter high frequency step down switching regulator U11 Figure A 2 which generates the configurable Vpp voltage Von is mainly used as power supply of the PLC class D amplifier and also as input of the 5V DCDC buck converter high frequency step down switching regulator U12 Figure A 2 5V voltage rail is only used to provide an external power supply by means of DC jack connector J15 Figure A 8 3V3 is linearly regulated U13 Figure A 2 and is used to power up ATPL230A and all other digital devices To measure the current consumption of the 3volts power supply connect an ammeter instead of the jumper J17 Figure 3 4 Power supply diagram Transformer 12 16V 5V 3V3 amp Buck Buck 5V LDO Ve Rectifier Conveter Conveter Switching frequency of DCDC buck converters used in this evaluation kit has been chosen to be higher than maximum PLC frequency band supported by ATPL230A device
91. ew Help E Once the application is launched the COM port for the board needs to be configured The COM port selection window is available by choosing File gt SettingslInput A new window Settings will appear as shown in Figure 6 98 Figure 6 98 Settings window KE Settings e Connection Options Run local USI server Connect to remote USI server Server options Device type Service TCP IP Host 10 140 228 11 Port 8216 Protocol used for application requests PLME MLME Serial Profile Log Options F USI c USI_Log txt DIN Browse Sniffer Options Enable Sniffer Sniffer Database c Sniffer_DB sql Browse Overwrite Append L oe 1 caei 104 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Select the connection options e Click Run local USI server option e Click the Serial option and select the COM port it can be checked in the Windows Device Manager Com Port section select the enhanced port UARTO and set the speed Default speed for this application is 115200 bauds Also this tool is able to connect to a remote device through the TCP IP protocol This option requires the IP address of the server and the port opened by the server This tool could use different protocols for the requests Depending on the application loaded in the service node board it uses kind of protocol
92. f this action is necessary it must be performed by qualified staff after being sure that mains connection has been previously removed Be careful it is only for indoor use This development board does not have any switch on mains connection to switch on or off it It must always be connected to an easy accessible mains socket Do not connect any probe to high voltage sections if the board is not isolated from the mains supply to avoid damaging of measurement instruments This board can be used with coin lithium batteries which are highly contaminated products Used batteries must always be recycled WARNING The boards kits are shipped in a protective anti static package The board system must not be subjected to high electrostatic discharge We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments offices with synthetic carpet for example without enclosure Avoid touching the component pins or any other metallic element on the board ATPL230AMB is a CE mark product which passes EN60950 1 safety standard EN50065 1 EN50065 2 3 EN600065 7 EMC and FCC as current carrier system standards It also satisfies Pb Free and ROHS directive WARNING ATMEL does not assume responsibility for the consequences arising from any improper use of this board Boards kits are intended for further engineering development demonstration or evaluation purposes on
93. ffer Options Enable Sniffer Sniffer Database PRIME Manager_1 1 12 Sniffer_DB sal i Overwrite Append In case the embedded sniffer is enabled the database file to store the traffic must be configured So in the Settings window select the database file name and the location to store the sniffer log and click OK button Figure 6 80 Furthermore overwrite or append option can be selected Database files can hold longer logs without having to split them in pieces Also log stored files can be opened to review the file Figure 6 80 Database Settings Sniffer Options Enable Sniffer Sniffer Database c Sniffer_DB sql O Overwrite Append At this point the tool is ready to start capturing data If board is not powered this is the point to supply it Click on the menu Connection gt Connect to begin logging data In case the serial COM port is not the proper or board is not powered tool shows an error window as the figure 92 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 81 Error window Figure 6 82 Atmel PRIME Manager tool main window ta ATMEL PRIME MANAGER v1 1 12 File Connection View Help MAC SID LNID LSID f Time Configurations Delay Restart Safety Timer File Configuration oi Match Rules Vendor Model Page Size ARO Multicast looStart Stop Set PIB i byte 0 to 255 or Ox
94. gt Atmel recommends to load the binary generated with the last PHY Tester Tool project released in the kit to evaluate the board with last improvements After installing the Atmel PLC PHY Tester tool in your PC s connect the two boards to the grid and to the host s PC s as shown in the following figure Figure 6 13 ATPL230AMB Boards connection scheme Following chapters explain to you how to install the PC tool supply the boards and select the UARTO to communicate with the SAM4C16C Load the firmware and run the application 6 2 1 Atmel PLC PHY Tester tool Installation To install Atmel PLC PHY Tester tool in a Windows Operating System execute the provided installer in the Tools folder PCTools ATMEL_PLC_PHY_Tester ATMEL_PLC_PHY_Tester_Tool_vxX Y Z exe and follow the installation wizard The installer wizard should open To follow with the installation click Next Figure 6 14 Installation process slide 1 Atn F Choose Users Choose for which users you want to install Atmel PLC PHY Tester Tool CH Select whether you want to install Atmel PLC PHY Tester Tool for yourself only or for all users of this computer Click Next to continue Install for anyone using this computer Install just for me MullsoFt Install System w2 46 o oi im i i i i iii 44 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Select the users per
95. hat these two instances may or may not run on the same computer Figure 6 43 PHY TX Test Console concept Serial Link gt se Power Line For this example a serial interface tool is required HyperTerminal is not installed on Windows 7 You can use a PuTTY terminal instead Once you have the serial terminal in your computer open puiiy exe and connect to the COM port number assigned to the micro B USB cable see Figure 6 22 As is commented in section 3 5 6 4 UART 1 is available by USB connector J9 UART1 CMOS signals are also available in a triple row male connector J5 see Figure 6 22 Remember to select the Standard COM Port UART1 Figure 6 44 COM Port selection Device ana ger File Action View Help e 9 Eu m U e NE 4 9 ZARDT0024 E U i gt Je Batteries Specify the destination you want to connect to JE Computer T Serial line Speed b Disk drives bk a SE ei b a KS Display adapters Se COM36 ES b Ai DVD CD ROM drives oh Connection type gt DS Human Interface Devices 7 Wi Raw Telnet Rilogin SSH Seral D 4g IDE ATA ATAPI controllers E gt E Jungo i A Load save or delete a stored session gt D Keyboards bd Saved Sessions J Mice and other pointing devices er b Monitors po a E Network adapters E EH Default Settings E Broadcom NetLink TM Gigabit Ethernet sol KC Cisco Systems VPN Adapter for 64 bit Windows Fos E Real
96. his application configures the ATPL230AMB board as a Service node It is an application example that shows how to serialize the PRIME API when the user application is running in an external device Open prime service modem atpl230amb zip file and select the APPS _PRIME_SERVICE_MODEM project Remember that Modem application project is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_modem atpl230amb thirdparty prime_ng a pps prime_service_modem sam4c16c_atol230amb as5_arm Software PRIME_vaa bb cc dd prime_service_modem atpl230amb thirdparty prime_ng a pps prime_service_modem sam4c16c_atpl230amb lar Basic procedure for performing this integration firmware configuration is commented widely in the Atmel PRIME Firmware Stack doc43085 Basic requirements are Memory allocation The allocation address of the PRIME FW stack is allocated at the highest address and uses the shown addresses in Figure 6 71 This memory distribution has been chosen to ease the firmware upgrade process Addresses can be changed to fit the user s needs as long as they respect the indicated sizes There are two regions reserved for the PRIME FW stack one ATPL230A EK Kit User Manual USER GUIDE 85 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 to run the stack and the other one to store an old new stack version The user application is responsible for managing the p
97. hnology is purely digital and does not require external DAC ADC thus simplifying the external required circuitry Generally Atmel PLC coupling reference designs make use of few passive components plus a Class D amplification stage for transmission Figure A 4 and Figure A 5 show external components required by ATPL230A for PLC reception and transmission respectively PLC coupling reference design is composed by the same sub circuits e Coupling Stage e Reception Stage e Transmission Stage e Filtering Stage 20 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 3 8 PLC Coupling example RECEPTION STAGE TO MAINS COUPLING STAGE FILTERING STAGE EMIT1 EMIT2 TRANSMISSION EMIT3 EMIT4 EMITS TXRXO ATPL230A 3 5 4 1 Coupling stage The coupling stage blocks the DC component of the line to from which the signal is injected received Le 50 60 Hz of the mains This is carried out by a high voltage capacitor C26 Figure A 4 Coupling stage could also voltage isolate the coupling circuitry from the external world by means of a 1 1 PLC transformer Capacitor is laying out in ATPL230AMB The optional PLC transformer is included in ATPLCOUP001 board voltage isolated see section 4 Footprint of BNC connector J11 Figure A 4 is included in the board but is not mounted by default Removing the R12 and R13 and soldering R88 and R89 resistors the PLC coupling
98. host PC in order to enable communication between the Base Node board and the PC In this example please note that it is only necessary to establish a serial connection between the board acting as a Base Node and the host PC so only one instance of the PC tool is required The Atmel PRIME Manager tool allows you to gather information of a PRIME network This tool displays information about the devices connected to the network MAC address logical address firmware version vendor identity etc and the amount of registered nodes over time The PRIME Network Manager tool can also upgrade the firmware of all devices connected to the Base Node and it is used to monitor data traffic on and manage the PRIME network This PC application can be found in the PC Tools folder PC Tools Atmel PRIME Managern BN Please remember that the provided PRIME Base Node is a lite version i e it is limited to manage up to 10 Service Node connections Default coupling board configuration for the projects is configured for ATPLCOUP001v1 coupling board 90 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 77 PRIME Network concept Once the Base Lite node board is powered the green led D5 LEDO is blinking The Base Node Lite communicates with the Atmel PRIME Manager tool by means of a serial interface and it retrieves information about the network structure and data traffic
99. howed Reception parameters showed Parameter Description Parameter Description It indicates the number of frame ae i It indicates the number of frame received Frame transmitted It is useful to track Frame It is useful to track the test progress the test progress It indi he result of transmis SE Seale EE It indicates the frame type of the frame Tx Result sion If an error occurs a Frame type Res received descriptive text will appear It shows the message transmitted Modulation It indicates the modulation scheme of the Data l in ASCII format scheme frame EA It indicates the strength of the signal Tx Interval the transmission of the current RSSI I H received in dBuV frame and the previous one SNR Signal Noise Ratio is a parameter calculated as is defined in the PRIME spec dB Error Vector Magnitude is a parameter EVM calculated as is defined in the PRIME spec dB It is the received info in ASCII format ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Transmission parameters showed Reception parameters showed It is the interval of time between the Rx Interval reception of the current frame and the previous one Payload It shows if the content of the frame is correct Integrity or not After all frames have been transmitted received or the test has been cancelled at the bottom of the tab it will appear a text box with information ab
100. ication 2015 ATPL230A EK Kit User Manual USER GUIDE 113 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Appendix A Board schemes A 1 ATPL230AMBv4 schemes This section contains the schemes of the ATPL230AMB multipurpose board e Top level scheme e Power supply scheme e ATPL230A transceiver e PLC Coupling transmission scheme e PLC Coupling reception scheme e ATSAM4C16C MCU e Peripherals e Interface e Components location in top layer Figure A 1 ATPL230AMB Top level scheme 2 3 ATPL230AMB v4 Top Level LU Power Supply Power Supply SchDoc U_PLC Coupling Tx KL PLC Coupling Tx SchDoc MAINS ha SS U_ATPL2xxA ATPL2xxA SchDoc U_PLC Coupling Rx PLC Coupling Rx SchDoe U_SAM4 SAM4 SchDoc LU Interface Interface SchDoc Ee E EH JUMPERS CONFIGURATION T lt S N J Peripherals S lt y Peripherals SchDoc S DESIGNATOR DEFAULT 230Vac position 115 230Vac selection 3V3 force on ees Open 16V Vdd 16 12V selection Close Close to enable 3V3 Erase flash memory 7 318 Close va Selection of VDDBU 3V3 or VBATT vi First Revision mm FID mp FID4 SSCS Pie GC TITLE 2 3 Xplained PRO ATPL2xxA connection JTAG BN MIMO Interface UARTs 11 14 2014 JL Description Author o ee LECTIE NY NY NY NY NPY NY PCB Code number ATPL2xxAMB 114 ATPL230A EK Kit User Manual US
101. in the following folder PC Tools SAM ICE Driver Once drivers have been installed you may verify the driver installation by consulting the Windows device manager If the driver is installed and your SAM ICE is connected to your computer the device manager should list the J Link driver as a node below Universal Serial Bus controllers as shown in the following screenshot ATPL230A EK Kit User Manual USER GUIDE 33 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 3 Device manager E Device Manager e Emlee ales VMBASIC 8 Batteries H m Computer HEJ Disk drives H 5 Display adapters ey DYD CD ROM drives IO vn Floppy disk controllers o Gel Floppy disk drives IDE ATAZATAPI controllers E 3 Keyboards H De Mice and other pointing devices HEN Network adapters ft Ports COM amp LPT E Bi Sound video and game controllers P gt System devices E Universal Serial Bus controllers JL mk driver Intel 8237 148 EB PCI to USB Universal Host Controller USB Root Hub 6 1 5 Downloading a file using command script files J Link Commander can also be used in script mode that allows the user to use this application for batch processing and without user interaction When using J Link commander in script mode the path of a script file is passed to it The syntax in the script file is the same as when using regular commands in J Link commander one line per command To do ea
102. includes ATPLCOUP001 and ATPLCOUPOO6 boards which are described in chapters 4 and 5 respectively Other coupling boards have been designed The Application Note doc43052 provides a description of the PLC Coupling Reference Designs available and all the features and characteristics 3 5 4 5 ATPLCOUP boards Table 3 1 summarizes the main characteristics of currently available PLC coupling reference designs Please refer to Atmel doc43052 for a complete description of ATPLCOUP boards Table 3 1 ATPLCOUP boards Set He deih Branch Electrical PRIME CENELEC ARIB Ecc Isolation Channel Band ATPLCOUPODe emm Dowie ves nenn ATPLCOUPO ams Dowie enn ATPLCOUPODS ams me enn mens mae Dowie Yes 345678 Xx X Although different ATPLCOUPXXX can be used on the same ATPL230AMB board they may require different voltage for the class D amplifier Vpp As is commented in 3 5 1 VoD can be regulated to 16 or 12 volts depending on J16 jumper position It is important to note that ATPLCOUPO01 must be used with 16V The PRIME PHY 1 3 specification uses the frequency band from 41 992 kHz to 88 867 kHz 47 kHz bandwidth This is achieved by using OFDM modulation with signal loaded on 97 96 data and one 22 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 pilot equally spaced subcarriers Differential modulation is used with one of three possible constellatio
103. ing Furthermore UARTs CMOS signals are also available in a triple row male connector J5 Figure A 8 3 5 6 5 Xplained PRO Master Xplained Pro is an Atmel s proprietary interface port intended to connect different development boards such as metering and PLC communication boards This point to point interface offers SPI and USART ATPL230A EK Kit User Manual USER GUIDE 25 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 communication capabilities and requires one target board master and an extension module slave ATPL230AMB is an Xplained Pro target device with power supply extension connector ATPL230AMB Xplained Pro provides the following features e SPI from the SPI1 e UART from the USART1 e 12C from the TWIO e 2ADC inputs from PA4 and PB13 e 1 IRQ input from PA17 e 5 GPIO s from PA18 PB19 PB20 PB21 and PC8 ATPL230AMB is an Xplained Pro Master device with power supply extension connector J12 Figure A 8 26 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 4 ATPLCOUP0O01 Hardware 4 1 Overview ATPLCOUP001 is a PLC coupling board designed to communicate in CENELEC A band especially in PRIME band from 41 to 89 KHz PRIME channel 1 ATPLCOUPO01 mounts a single branch with voltage isolation from mains to the PLC coupling driver board The goal of this design is provided to the customers with a cost optimized perfor
104. instances of the PHY Tester tool which has been previously installed in the host s PC s in order to enable communication between both boards Please note that these two instances may or may not run on the same computer Figure 6 26 Atmel PLC PHY Tester concept Si g D Sc PLC lt Serial Link D In order to know if the boards were programmed successfully you can check if the green led LEDO D5 is blinking This indicates that the PHY Tester Tool application is running on SAM4C16C device Power Line You must select the same coupling boards to plug in both ATPL230AMB boards Check the coupling identifier that you can find in the coupling board send receive otherwise please remove them and connect the proper ones By default ATPL230AMB board sets an ATPLCOUPO01 coupling board so Vpp voltage of ATPL230AMB must be 16 volts Voo can be regulated to 16 or 12 volts depending on the J16 jumper position In this situation jumper J16 must not set See section 3 5 1 and Figure A 2 for more information These coupling boards must be the proper one for the frequency band you want to Other coupling boards may require different voltage for the class D amplifier Von Once the application is launched Starting Window will appear see Figure 6 27 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03
105. io Recent Projects User Guide 1 Getting Started Programming Dialog e Atmel Software Framework Video Tutorials Close page after project load Extending Atmel Studio Show page on startup VA View VA Outline CG Solution Explorer Show output from ja lesza To avoid problems depending on the length of the path with Atmel Studio we recommend install the Software folder contents of the evaluation kit in the root C And now you can open the PRIME PHY workspace for SAM4C16C platform ATPL230AMB_PLC_examples atsin For that you have to click on Open Project or on File gt Open gt Project Solution on the Start page and select the project in the folder Software PRIME_vaa bb cc dd phy atol230amb thirdparty prime_ng apps wrkspcs as_ solution Once you have loaded the workspace select the apps phy tester too project The Solution should appear in the integrated development environment as in the figure below 40 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 1 8 1 a PS_PHY_TES dee aed File Edit View VAssistX ASF Project Build Debug Tools Window Help fae 8 f e SE Ee F ao Eaa a Gda aaa a E A E Eu Debug 1 v63StackinitTask RQA RA E E EE EE AER FSS egagog Slimal oo bls wee zue EA Sle A Al a Ale Ile we oe A Bt Bt el HIE St em ArewceCH TI Neie H phy_tester_tool c X phy_tester_tool c
106. it is showed in Figure 6 71 the Flash address to store the program should be 0x010F0000 Open the IDE tool used Atmel Studio or IAR Embedded Workbench Select the PRIME user application select the project running as Microcontroller operation mode APPS_PRIME_SERVICE_DLMSEMU_UI atsin or apps_prime_service_dimsemu_ul eww and now build it to generate the output file As it is commented in section 6 5 3 2 and it is showed in Figure 6 71 the Flash address to store the program should be 0x01000000 or 0x 010EC000 AS Note that kits do not provide a J Link ARM or SAM ICE JTAG probe in order to connect to the user s host PC and the boards to download and debug the projects Remember that PRIME FW Stack project is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic oe binisam4cp16b_sam4cp16bmb_gcc as5_arm Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic e bin isam4co16b_sam4cp16bmb_tar ar Remember that DLMS application project running as microcontroller mode is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_dimsemu_ult atol230amb thirdparty orime _ng apps prime_service_dimsemu_ui sam4c16c_atpl230amb as5_arm Software PRIME_vaa bb cc dd prime_service_dimsemu_ult atol230amb thirdparty orime _ng apps prime_service_dimsem
107. ith the current log It is updated in real time as frames are received from the hardware sniffer The data shown are idFrame Timestamp Modulation Symbols SNR ExSNR RSSI Channel Duration Delta CRC Up Down NAD Level PduType GenType Lcid Sid Lnid and Length While the PLC traffic is logged into a database the software tries to infer the PLC network structure and status as seen by the Base node This information is shown in several docking views They are available on the menu View e Hexa view shows the hexadecimal display of the selected frame in the main view e Packet view shows the disassembled data of the selected frame in the main window All the specified fields on the PRIME specification are shown e Network view shows the current status of the inferred network by the software It is refreshed every time a change in the network is detected ATPL230A EK Kit User Manual USER GUIDE 75 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 e Nodes Switches plot shows the evolution of the network as seen by the sniffer It plots the number of active nodes and switches on the network versus time It is useful to detect problems of stability on the PLC network e Filter view allows selecting the frames shown in the main view table Figure 6 62 ATPL Multiprotocol Sniffer tool main window and several docking windows File Configure Capture View About O O mN Nodes LNID MAC SID LSID Status idFrame
108. ived disturbances ATPL230A EK Kit User Manual USER GUIDE 21 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Transmission stage shall be always followed by a filtering stage 3 5 4 4 Filtering stage The filtering stage is composed by band pass filters which have been designed to achieve high performance in field deployments complying at the same time with the proper normative and standards The in band flat response filtering stage does not distort the injected signal reduces spurious emission to the limits set by the corresponding regulation and blocks potential interferences from other transmission channels The filtering stage has three aims e Band pass filtering of high frequency components of the square waveform generated by the transmission stage e Adapt Input Output impedances for optimal reception transmissions This is controlled by TXRX signals e And in some cases Band pass filtering for received signals When the system is intended to be connected to a physical channel with high voltage or which is not electrically referenced to the same point then the filtering stage must be always followed by a coupling stage These components are not lying out on ATPL230AMB board because are dependent on the application parameters such frequency band transmission A set of boards known as ATPLCOUPXXxX have been design by Atmel to implement any possible transmission scheme supported by ATPL230A ATPL230A EK
109. l It is automatically refreshed every time a change in the network is detected for example a new device is registered or promoted to switch lt is also possible to refresh this view with the Reload Tree button which requests the registered nodes to the Base Node in order to rebuild the network structure There is a right click menu in this view with further options as shown in the following figure Figure 6 87 Right Click menu BASE Fis D i Info Request Network Management FU Management PIB Request Info Request dialog This dialog allows requesting information from the Service Nodes by means of the Base Management Protocol Available information to be requested is firmware version model and vendor and firmware state The firmware state is only returned when a firmware upgrade process Is running ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 88 Info Request dialog t Info Request O k Info requested FW Version Model Vendor FU State To Selected Nodes All Nodes BA BA SD 01 84 7E The information can be requested to all registered nodes or just the selected nodes multiple selections are enabled in Windows OS mode Network Management dialog This dialog lets the user to manage the network with available functions Unregister Promote Demote and Reboot Firmware Upgrade Management
110. l Operating System or as Microcontroller there are two projects prime_service_dimsemu_fi atpl230amb zip file for OSS based on FreeRTOS and prime_service_dimsemu_ui atpl230amb zip file A PRIME user application project modem application This application configures the ATPL230AMB board as a Service Node It is an application example that shows how to serialize the PRIME API when the user application is running in an external device See prime_service_modem atol230amb zip file With this architecture both parts can be updated separately even when they are running in the same board Furthermore this means that the memory must be correctly managed in order to be able to allocate all binary files 6 5 3 1 PRIME FW stack The PRIME FW stack project APPS PRIME SERVICE BIN contains the PRIME library together with the configuration files This project is required in order to generate the PRIME binary file that is later loaded into the board Remember that PRIME FW Stack project is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic ATPL230A EK Kit User Manual USER GUIDE 83 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 oe binisam4cp16b_sam4cp16bmb_gcc as5_arm Software PRIME_vaa bb cc dd prime_service_bin thirdparty prime_ng apps prime_servic e_bin isam4co16b_sam4co16bmb_iar iar This project ca
111. llectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDENTAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS AND PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel products are not intended authorized or warranted for use as components in applications intended to support or sustain life SAFETY CRITICAL MILITARY AND AUTOMOTIVE APPLICATIONS DISCLAIMER Atmel products are not designed for and will not be used
112. ly It is not a finished product except as may be otherwise noted on the board kit 1 2 Electrical characteristics This section shows the electrical characteristics of the kit s boards See the following tables Table 1 1 Power Supply Requirements Parameter Condition Min Typ Max Unit Isolation Voltage hn eis ye ang 3000 PLC coupling transformer 6 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Note that the ATPL230AMB can be supplied either with 100Vac or 230Vac by setting the proper jumpers pitch 5 08mm in the voltage selector J2 as depicted in the Figure 6 20 By default voltage jumper is set for 230Vac For more information about power supply see section 3 5 1 Note This current is measured when board is supplied with 100Vac and board is in worst consumption conditions That is when it emits against very low impedance in higher channel and it is supplying an extra board through the DC jack J15 Table 1 2 Power Consumption Parameter Condition Max Power Consumption ACDC maximum output power FW PHY Tester Tool App Low Impedance Load PRIME LISN Measured on Vpp 16V DCDC TX Power Consumption output FW PHY Tester Tool App High Impedance Load CISPR LISN Measured on Vpp 16V DCDC output RX Power Consumption Measured on 3 3V LDO output Low Power Mode Current Consumption Notes 1 These measurements were taken with a
113. mance transmission board in CENELEC A band for PRIME channel 1 This board is set by default in the ATPL230AMB board of the ATPL230A EK Figure 4 1 CENELEC bands cB E od well Gel EI 116 WO YY GA Val 4 2 Features The ATPLCOUP001v1 board includes the following features e Specially designed to communicate in CENELEC A frequency band 41 992 88 867 kHz e Voltage Isolation from mains with a transformer MSR EXL 324 soldered in top layer board e Single branch Low impedance optimized Kam Test point ND EES TX led indication Va V DAS Test point PLC transformer provides the voltage isolation from mains ATPL230A EK Kit User Manual USER GUIDE 27 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 4 3 Mechanical and user considerations ATPLCOUP0O01 is delivered with the ATPL230A EK Board to board SMD connectors J1 and J2 are used to connect the ATPLCOUP0O01 into connectors J6 and J7 of ATPL230AMB board Figure A 4 These J1 and J2 connectors are in bottom layer of ATPLCOUP001 and they have the following part numbers e J1 SAMTEC FTR 130 54 L S e J2 SAMTEC FTR 124 54 L S The ATPLCOUP001 board is directly powered from mains grid so hazardous voltage is present on the board To avoid user access to dangerous parts ATPLCOUPO001 must always be used in its enclosure ATPLCOUP0O01 is a CE mark product that passes EN 50065 1 EN 50065 2 3 and EN60065 7 EMC stand
114. me interval between frames Apps Phy_Sniffer_Tool This application configures PRIME PHY layer to monitor the PLC data traffic on ATPL230AMB boards and sends via serial communication this traffic to the ATPL Multiprotocol Sniffer tool This tool can be downloaded from the PC Tools folder Every coupling board is intended to be used in their corresponding channel s only By default sniffer project is compiled for ATPLCOUP001 board This means that only PRIME channel 1 is supported e A PRIME Service Node project which is composed of several projects for both IDE tools APRIME FW stack project prime_service_bin zip file A PRIME user application project DLMS application It is an application example that shows how the PRIME API should be used This application configures the ATPL230AMB board as a Service Node with DLMS capabilities and simulates the data exchange between the Base Node and the Service Node The Service Node responds dummy DLMS messages after receiving data requests from the Base Node For this example a PRIME Concentrator is required Depending on the operation mode as a Real Operating System or as Microcontroller there are two projects prime_service_dimsemu_fi atol230amb zip file for OSS based on FreeRTOS and prime_service_dimsemu_ul atpl230amb zip file running as microcontroller A PRIME user application project modem application This application configures the ATPL230AMB board as a Service Node It
115. med with prime_service_modem_atpl230amb project or prime_service_dimsemu_ul atol230amb project Figure 6 111 Service node tool application window t anme rme mance 207 TT ae File Connection View Help PRIME Management Certification F Run AppEmu Current Certification state PHY v1 3 6 msg 2000 Att dB o G Duty 50 24 Modulation DPSK Y 05 06 2015 12 00 30 509 MNGP_SET_ REQUEST sent pib_attrib 0x8120 pib_value 0x01 05 06 2015 12 00 37 562 MNGP_SET REQUEST sent pib_attib 0x8121 pib_value 0x07d002003200 110 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 112 Base Node tool window _PLME MLME PIBs Serial Profile PRIME Profile 432 MLME Set Cert Mode Clear Rx Stats msg 2000 gt Att dB 0 Duty 50 gt Modulation Start Transmission 05 06 2015 12 00 19 433 MLME_SET REQUEST sent 05 06 2015 12 00 19 506 MLME_SET_CONFIRM PIB 0x8120 PRIME_MLME_RESULT_SUCCESS Connected Serial COM47 B115200 Server 9099 Once 2000 frames have been sent during every transmission TX led and green led LEDO of Service node board are on we have to ask to Base node the number of frames received Process should be e Select the Serial profile tab of Base node tool e Select the phyStatsRxTotalCount Ox00a4 in the combo box e Click Get PIB e The value of the PIB appears in the Log o
116. mel Also each layer is specified with its corresponding primitives and access points c Evaluation License Agreement document 5 PCTools folder contents a Atmel PLC PHY Tester tool for checking the point to point PLC transmissions between ATPL230AMB boards b ATPL Multiprotocol Sniffer tool to monitor data traffic on PRIME networks and gather information of a PRIME network c Atmel PRIME Manager tool that displays information about the devices connected to the network and manages the PRIME network As well as it lets you to the firmware upgrade of the service nodes and monitors the data traffic sniffer function There are two versions one for Base Lite node 1 x x and another one for Service node 2 x x d SAM ICE Drivers Users may need to install this driver the first time the SAM ICE is connected to the PC e USB Drivers Silicon usb drivers Users may need to install these drivers the first time the ATPL230AMB board is connected to the host PC by means of a serial USB connection We recommend installing the evaluation kit contents in the root C to avoid problems with very long paths Unpack and inspect the kit carefully Contact your local Atmel distributor should you have any issues concerning the contents of the kit The two ATPL230AMB boards with the ATPLCOUP001 are encapsulated with enclosures and shipped in protective anti static foam The two coupling boards ATPLCOUPO06 are shipped in shielded bags Th
117. mission Test Modulation Att dB 0 Len bytes 16 Interval ms 100 Random 0 NumMsgs 40 4 Stats Get Tx Time Get Rx Params Get Rx Total Count Get Instant RMS Calc Get Mean RMS Calc 05 06 2015 09 50 04 911 MNGP_GET_confirm pib_attrib 0x808e pib_value 0x 00 0 05 06 2015 09 51 57 665 MNGP_SET request MTP on pib_attrib 0x808e pib_value 0x01 05 06 2015 09 51 57 719 MNGP_GET_confirm pib_attrib 0x808e pib_value 0x01 1 05 06 2015 09 52 01 598 MNGP_GET_confirm pib_attrib 0x8100 pib _value 0x0 14090870074 Connected Serial COM46 B115200 Serwer 9098 MAC State Mot Registered Ati el To uninstall the Atmel PRIME Manager tool from your computer go to Start gt All Programs gt ATMEL gt Atmel PRIME Manager vX Y Z gt Uninstall For further information of the Atmel PRIME Manager tool please refer to the tool s embedded help in the menu bar 112 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 7 References 1 CENELEC EN 50065 1 Signaling on low voltage electrical installations in the frequency range 3 KHz to 148 5 kHz 2 FCC Part 15 Subpart B 3 doc43053 ATPL230A Datasheet 2015 4 doc11102 SAM4C Series Datasheet 2014 5 doc43085 Atmel PRIME Firmware Stack User Guide 2015 6 PRIME Specification PRIME Spec_R1 3 6 1 2014 7 doc43052 PLC coupling reference designs 2015 8 doc43072 PHY Performance Verif
118. missions and click Next Figure 6 15 Installation process slide 2 3 Atmel PLC PHY Tester To Welcome to the Atmel PLC PHY Tester Tool Setup Wizard This wizard will guide you through the installation of Atmel PLC PHY Tester Tool It is recommended that you dose all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your Click Next to continue Click Next to continue Figure 6 16 Installation process slide 3 PLC PHY Tester Tool Setup License A greem ent Please review the license terms before installing Atmel PLC PHY Tester Tool Press Page Down to see the rest of the agreement This Evaluation License Agreement Agreement is a legally binding agreement between your employer Licensee and Atmel Corporation Atmel By dicking the I Accept button or by downloading installing or using any of the software available for download Licensed Software you are indicating that you are binding Licensee to the terms of this Agreement and that you are duly authorized by Licensee to do so If you are not authorized to bind Licensee to the terms of this Agreement or if Licensee does not agree to be bound by all of the terms of this Agreement do not click the I Accept If you accept the terms of the agreement dick I Agree to continue You must accept the agreement to install Atmel PLC PHY Tester Tool Mullsoft Install System v2 d
119. n be reused whenever a new PRIME library is available it would only be necessary to exchange the library file in the project and update the PRIME firmware version in the corresponding configuration file In this project users must only modify the available configuration files according to their application needs e Management Plane configuration conf_mngp h e PAL configuration conf_pal h e PHY configuration conf_phy h e PRIME Stack configuration conf_prime_stack h 6 5 3 2 User application This firmware stack has been intended to hold the application code developed by the user So the user can integrate his application code in the firmware package delivered by Atmel The user application project is independent from the PRIME FW stack project It contains only header and configuration files related to the PRIME FW stack so that users can develop their applications and later load them into the board at the allocated address without disturbing the PRIME FW stack gt The HAL is also part of the user application project and users can allocate it at any address within their region The pointer to the HAL functions will be passed to the PRIME FW stack at initialization Users are also responsible for initializing starting and running the HAL There are two PRIME user application projects e DLMS application This application configures the ATPL230AMB board as a Service node with DLMS capabilities and simulates the data exchange be
120. n the J Link tool is a different version of the written in the script or in a different path To solve it edit the path according to your installation folder in the bat file ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Please make sure all nodes Base and Service have valid MAC addresses An invalid MAC makes a node unable to register Take into account that the projects store a MAC address in the Base Lite Node and another one in the Service Node If you have more Service Nodes the same MAC address is stored in all of them Since the MAC address must be unique for each node you should be careful in this situation because MAC must be unique E By default every board has a MAC number preprogrammed which coincides with the serial number of the board label fixed in the enclosure Anyway if you want to change it see section 6 6 4 1 6 7 4 1 Setting MAC number In the Service Node project MAC address is defined but the user is free to change it A way could be configure the board in Manufacturing Test mode and sending a PIB to write the MAC Process should be setting the board in MTP mode send the PIB MTP_PHY_ENABLE Ox808E and send the PIB macEUI48 0x8100 with the desired MAC number You can use the Atmel PRIME Manager Tool go to PRIME management view and select MFG Test tab Once the Manufacturing mode has been enabled write the MAC number in the box and press Set
121. n the PHY common workspace ATPL230A_PLC_examples which is contained in following Software folder Software PRIME_vaa bb cc dd phy atol230amb thirdparty prime_ng apps wrkspcs Remember that the J Link USB drivers must have been downloaded previously from the Segger webpage see section 6 1 4 and they depend on your operating system As we commented in a previous section every coupling board is intended to be used in their corresponding channel s only By default sniffer project is compiled for ATPLCOUPO01 board This means that only CENELEC A frequency band PRIME channel 1 is supported 72 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 If you are going to use another coupling board you must build the PHY sniffer project with the correct configuration For that open the IDE tool used and open the PHY sniffer project application APPS_PHY_SNIFFER_TOOL atsin or APPS _PHY_SNIFFER_TOOL eww After that select the file cont_phy h which tt is in the PHY project configuration directory Software PRIME_vaa bb cc dd ohy atol230amb thirdparty prime phy atol230 apps phy_sniffer_tool s am4ci6c_atpl230amb find the define function to select the coupling board configuration see Figure 6 56 Change the board name to desire board and build to generate the output file Figure 6 56 Coupling board configuration definition 44 S ifndef CONF_PHY_H INCLUDE 45 define CONF
122. nce it is possible to achieve a highest robust mode gain compared to PRIME up to 14 5 dB more Table 6 2 PRIME modulations PRIME Band Extension Modulation PRIME 1 3 Cenelec A DBPSK DQPSK D8PSK E DBPSK DQPSK D8PSK Rob PRIME 1 4 FCC 3 cK DBPSK Robust DQPSK ARIB The current PRIME standard is adapted to European regulations The evolution of PRIME has as one of its key features a frequency band extension that allows choosing up to 8 different channels This performance makes PRIME becoming into a more flexible platform Figure 6 65 PRIME Frequency Band Extension PRIME 1 4 23 kHz 73 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz Nie eeeed ttteeate D Z Irr trtr Itrtrtt kHz 42 89 97 144 151 198 206 253 261 308 315 362 370 417 424 gt 47 5 This technology only allows one channel active at a time The limits of each channel are shown in the next table and can be compared with the figure above Table 6 3 Frequency Band Limits of each Channel Start freq kHz End freq kHz CENELEC ARIB FCC 41 992 88 867 x 2 96 68 143 555 x x x 3 151 367 198 242 x x 4 206 055 252 93 x x m 260 742 307 617 x x e 315 43 362 305 x x TE 370 117 416 992 x x 78 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 5 1 6 5 2 8 424 805 471 68 X In the following sections there are basi
123. nch IDE main window available from Op the View menu contains useful help about how to arrange windows that they can be enabled from the View menu en the PRIME PHY workspace for SAM4C16C platform A7PL230AMB_PLC_examples eww For that on the start page click on File gt Open gt Project Solution And select the project in the folder Software PRIME_vaa bb cc dd phy atol230amb thirdparty prime_ng apps wrkspcs iarew_workspace 7J Once you have loaded the workspace select the apps_phy_tester_tool project Now you can see the PR IME PHY project structure expand the tree structure in the workspace window That structure is showed in the Figure 6 5 6 1 7 1 Building programming and debugging a project with IAR Now you can create build program and debug the Atmel PRIME Examples using the IAR But before to do this you can configure and customize your project as you want i e adding the Output window show the line numbers change the language options etc Tool Output window is available by choosing View gt Messages gt Ioo Output The Tool Output window displays any messages output by user defined tools in the Tools menu provided that you have selected ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 37 the option Redirect to Outout Window in the Configure Tools dialog box When opened by default this window is grouped together with the other mes
124. nd discard frame errors If it is enabled all frames received will be sent to the PC software While the PLC traffic is logged into a database the software tries to infer the PLC network structure and status as seen by the Base Node This information is shown in several docking views They are available on the menu View Hexa view shows the hexadecimal display of the selected frame in the main view Packet view shows the disassembled data of the selected frame in the main window All the specified fields on the PRIME specification are shown Network view shows the current status of the inferred network by the software It is refreshed every time a change in the network is detected Nodes Switches plot shows the evolution of the network as seen by the sniffer It plots the number of active nodes and switches on the network versus time It is useful to detect problems of stability on the PLC network Filter view allows selecting the frames shown in the main view table ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 95 6 6 5 1 Network Topology view 96 The Network Topology View looks like the following figure Figure 6 86 Network Topology view Nodes MAC SID LNID LSID fuState Version Vendor M 4 32 Address ALV Ry Tx Coverage 01 40 30 87 00 74 0 11 255 01 03 09 02 ATMEL 2 2 2 100 100 This view shows the current status of the network inferred by the too
125. ndor 4 32 address ALV message count and coverage Firmware Upgrade view This view displays firmware upgrade options and information about the current upgrade process It is always visible when is connected to a Base Node ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 PRIME Management This view allows requesting information and other functionalities provided by the different protocols available in the tabs It is available in both Base and Service Node connection but they are different Besides this main window a new window is shown with the Sniffer The aspect and working are the same as the ATPL Multiprotocol Sniffer Tool See section 6 4 5 for more information Figure 6 85 ATPL Multiprotocol Sniffer tool main window z prome manacen SF Gc Capture View O 0 mN idFrame TimeStamp Modulation Sym SNR RSSI Duration Delta Up Down Level Pdulype GenType LOD SID LNID Lentgh The capture window has a tool bar with four commands Pause command will stop the update of the scroll view while the logging process will continue To restart showing the live stream of PDUs click Play button Channel combo box allows selecting the PRIME channel to listen Obviously the compatible PLC coupling board must be used Thunder button will set the CRC configuration on the hardware device If it is enabled the hardware device will calculate the CRC on all the frames a
126. nnected to the PC via USB or Ethernet e J Link Commander Simple command line utility primarily for diagnostics and trouble shooting es J Link Remote Server Free utility which provides the possibility to use J Link J Trace remotely via TCP IP e SWO Viewer Free tool which shows terminal output of the target performed via SWO pin e J Mem Memory viewer e J Link DLL Updater Allows updating 3rd party applications which use the J Link DLL e Free flash programming utilities Simple command line utilities which allow programming a bin file into the internal external flash memory of popular evaluation boards e USB driver Includes driver for J Links with CDC functionality e Manuals UM08001 J Link User Guide UM08003 J Flash User Guide UM08004 RDI User Guide UM08005 GDB Server User Guide UM08007 Flasher ARM User Guide e Release notes for J Link DLL J Flash and J Link RDI DLL e J Flash including sample projects for most popular evaluation boards e J Link RDI Support for ARM RDI standard Makes J Link compatible with RDI compliant debuggers Installing the software will automatically install the J Link USB drivers It also allows the update of applications that use the J Link DLL The last version of the driver for the SAM ICE JTAG Probe can be downloaded from the http www segger com website using the following link http www segger com jlink software html The package for Windows Setup _JLinkARM_V496b zip is located
127. ns DBPSK DQPSK or D8PSK The ATPL230A architecture provides enhanced performances over the PRIME specification with the new robust modes and the ARIB FCC frequency band extension PRIME has two additional robust modes e Robust DQPSK e Robust DBPSK The current PRIME standard is adapted to European regulations The evolution of PRIME has as one of its key features a frequency band extension that allows choosing up to 8 different channels PRIME 1 4 This performance makes PRIME becoming into a more flexible platform Figure 3 9 FCC amp ARIB bands 3 kHz 73 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz 7 3 kHz kHz 42 og 97 144 151 198 206 253 261 308 315 362 370 417 424 S 471 gt This technology only allows one channel active at a time The limits of each channel are shown in the next table and can be compared with the figure above Table 3 2 Frequency Band limits for each channel Channel Start freq kHz End freq kHz CENELEC ARIB FCC 41 992 s8867 J x x x 96 68 me kk bk 151 367 GENEE oaa o xX X X Ke 1 ee 1 ep LL 3 IL 3 Eleng rear XX PS a o 7 ow nese eS o e smo ms i d o a XXX X 3 5 5 Peripherals These peripherals are not necessary to implement a PRIME device they are included to show some features of the ATPL230A for a customer designs 3 5 5 1 External Memories The ATPL230AMB Modem Board includes a Flash Memory connected mean a SPI interface U3 U12 Figure A 7 with th
128. o micro USB cables in order to connect the user s host s PC s with the two boards Figure 6 22 UART amp JTAG connectors s VARTs Connectors k es i F E RI BC a an a E i Les r d J i 5 DCH CC A ocan gi e aND i i i ai i Tur hyr bah a ete oo ie re l Ki wile W Cs A E D LA mit i d E gipdptitut TT E t j 1 A UAR e dei if l e r E trr ICR al D Te ES Leg p ag ei at mm lt J TAG Connector Connect the USB cable to the micro B USB connector and the host PC If the PC does not recognize the USB download the USB driver from the manufacturer webpage or take it from the PC Tools folder PCTools USB_ Drivers Once the driver is downloaded unpack the driver archive to a folder on the host PC s hard disk Connect the USB cable to the board The new hardware installation will recognize the new board and will guide you through the USB driver installation When the wizard asks for the driver to install navigate to the directory where the driver archive has been unpacked to Identify the new hardware in the Windows Device Manager The assigned COM port number is needed when configuring the PHY Tester tool application later See the following figure for an example of a COM port assignment 48 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 23 Windows device manager Device M
129. ointer to the correct region Figure 6 71 FLASH memory allocation for projects compiled with IAR IDE 0x01000000 User App 896 kB 0x010DFFFF 0x010E0000 0x010EFFFF 0x010FO000 0x010FFFFF Note Different memory allocation of PRIME Stacks for projects compiled with AS e The PRIME API is the only one that users need to use to develop their PRIME applications e Initialization In order to start using the Atmel PRIME firmware stack it is necessary to initialize different parameters and to call the corresponding initialization functions These actions are independent of the operation mode e Operation modes It is up to the user to decide the operation mode to run their application There are two different modes as Microcontroller or as a Real Operating System Atmel pro vides an Operating System Support OSS based on FreeRTOS e Configuration files The configuration files in the user application project allow the application to configure its own resources e Firmware upgrade management In order to upgrade the PRIME FW stack two regions are reserved in the memory one for the current running stack and the other one to store the new stack The PRIME FW stack manages the FU process as described in the PRIME specification whereas users are responsible for handling the pointers to these regions and controlling the PRIME FW stack version running according to the indications received in the HAL By just up dating the point
130. omponent int maint void i status c42364a_init if status STATUS_OK main puts LCD Initialization fails r n Je E conf_phy h E while 1 ul_count_ms 500 7 count ms to blink le D cont_uart_serial h 0x1004858 Ox4c2d LDR N R4 E D cont _usi h 7 Ox100485a Oxf44f Ox70fa MO H RO Le F phy_tester_tool c 0x100485e 0xb085 SUB SP SE Ha G coupling_config c42364a_set_contrast 15 d 0x1004860 0x6060 STR RO F Ha E cont_atpl230 c See I sysclk_init E E conf_atpl230 h EEN ATMEL 7 0x1004862 Oxf000 Oxf931 BL syscll Ha 3 include BEE 28 A 0x1004866 Oxf64f Ox02ff MOVW R2 Ca source mm c42364a_show_text const uint8_t PHYTSI UE ae ae or ee es ere La E Output 0x100486a 0x482d LDR N RO E eet mag CS ap _ Ox100486c 0x6801 LDR R1 F initTimerims SCB gt AIRCR reg_value Ox100486e Ox4011 ANDS Rl Ri apps_phy_tester_tool_flash apps_phy_tx_test_console_tlash Lol fe Tnit ae s sh g Awinan wf NAt ep he CEP 1 Di G i x Log Tue Nov 18 2014 08 11 49 Hardware reset with strategy 2 was performed Tue Nov 18 2014 08 11 50 26376 bytes downloaded into FLASH and verified 11 55 Kbytes sec Tue Nov 18 2014 08 11 50 Loaded debugee C Users blanca melguizo Desktop thirdparty prime_ng workspace atpl230amb thirdparty prime_ng phy atpl230 apps phy_tester_tool sam4cl 6c_atpl230amb iar Debug Exe apps_phy_tester_tool_flash out
131. ossible to update relevant system files without having to reboot your computer Click Next to continue Click Next to continue 100 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 dee 2 94 Atmel PRIME Manager Installation procin Choose which features of Atmel PRIME Manager you want to install Check the components you want to install and uncheck the components you don t want to install Click Next to continue Select components to install Space required 90 1MB Description Atmel PRIME Manager v2 Bea TOORE Click Next to continue Bi a 95 Atmel PRIME Manager Installation sal Choose Install Location Choose the folder in which to install Atmel PRIME Manager Ep Setup will install Atmel PRIME Manager in the following folder To install in a different folder dick Browse and select another folder Click Install to start the installation Destination Folder Space required 90 1MB Space available 285 6GB Nullsoft Install System v2 46 eae will install the program in the Destination Folder To install in a different folder click Browse and select your destination folder Click Install to start the installation process Figure 6 96 Atmel PRIME Manager Installation proceza Completing Atmel PRIME Manager Setup Atmel PRIME Manager has been installed on your computer Click Finish to dose Setup ATPL230A EK Kit Us
132. ot part of the PRIME FW stack For more information about the Atmel PRIME software Stack see the doc43085 and the PRIME specification ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 81 Figure 6 68 Atmel PRIME Service Node Project ATPL230AMB gt Hardware gt SAMAC Family definition SAM4C16C header files preprocessor gt FreeRTOS Library iec 4 32 null gt PRIME Stack atpl230_prime _fatpl230 prime_api Note This figure is only to give a general idea about the distribution of the folders and the libraries in a basic Atmel PRIME Service node project 82 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Where prime_ng directory contains the following folders e apps it contains the workspace with all the example applications provided by Atmel including the configuration files and the project to generate the PRIME FW stack binary file New user applications must be developed in this directory too e libs it contains the library file that implements the complete PRIME FW stack e hal header and code files for the HAL e phy header and code files of the PHY layer for the PLC modem e pal header and code files of the PAL to interface PRIME with the PHY layer e prime_apri header and code files to manage the PRIME API e mac
133. out the test First of all it will appear information about starting and ending time this information is measured by the PC application After that there is a section of information called Frame Error information that shows information about transmitted received frames and possible errors Finally another section shows a resume of the transmission reception tests this information contains much information as modulation scheme message length total frame received that is pretty straight forward but other fields must be explained For that please refer to the tool s embedded help in the menu bar Once the values have been received you can copy all values to check and analyze them by your own clicking Copy Table button on the instances the reception and transmission Click the Restart button to start the test again It does first in the reception instance to avoid lose some frames The same TX RX processes could be done using another ATPL coupling board For that after power down the ATPL230AMB remove the ATPLCOUP001v1 board and set the new coupling board Take into account that the new coupling board could require to set the jumper in J16 connector of the ATPL230MB board Check the characteristics of the available ATPLCOUP boards And even you have to download over ATPL230AMB boards a new firmware build for the new coupling board in which the coupling board configuration has been changed see Figure 6 25 For further informa
134. p i Mi Click Agree to continue ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 45 Choose which features of Atmel PLC PHY Tester Tool you want to install Check the components you want to install and uncheck the components you don t want to install Click Next to continue Select components to install Atmel PLC PHY Tester Tod GE Position Your mouse over a component to see its description Space required 53 7MB Nullsoft Install System v2 46 Click Next Figure 6 18 Installation process slide 5 Atmel PLC PHY Tester Tool Setup Choose Install Location Choose the folder in which to install Atmel PLC PHY Tester Tool Setup will install Atmel PLC PHY Tester Tool in the following folder To install in a different folder dick Browse and select another folder Click Install to start the installation Destination Folder 6 Atmel tnel PLC PHY Tester Tool Space required 53 7MB Space available 302 8GB Nullsoft Install System v2 46 Setup will install the program in the Destination Folder To install in a different folder click Browse and select your destination folder Click Install 46 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 2 2 DEE 6 19 Installation process slide 6 Completing the Atmel PLC PHY Tester Tool Setup Wizard Atmel PLC PHY Tester Tool h
135. pace available 315 3GB Nullsoft Install System v3 0al Setup will install the program in the Destination Folder To install in a different folder click Browse and select your destination folder Click Install to start the installation process Completing Atmel PRIME Manager Setup Atmel PRIME Manager has been installed on your computer Click Finish to close Setup 88 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 6 2 6 6 3 6 6 4 Click Finish Now the program is installed in your computer and a shortcut should have been created in your desktop Note Take into account that for this example you have to use Atmel PRIME Manager version 1 a b and not later versions as 2 a b Supplying the boards Please refer to 6 2 2 in order to know how to supply the ATPL230AMB boards USB connection Please refer to 6 2 3 in order to Know how to connect the micro USB cable with the ATPL230AMB board Programming the embedded files It is commented in section 6 2 4 the way to program a board To program the board as Service node process should be the same building the IDE projects and downloading into the board Open the IDE tool used and select the PRIME FW Stack for AS and IAR IDE so APPS_PRIME_SERVICE_BIN atsin or APPS_PRIME_SERVICE_BIN eww projects of prime_service_bin And now build it to generate the output file As it is commented in section 6 5 3 2 and
136. pling Tx ATPLCOUPxxx Board PLC TX E NEE SCT erer a E pc nar ce ra aa pe Venea AR Fie PLC Coping Teso rar PLC Cong TXRXI I 2 3 4 h h nr PLC RX a m AGC 0 5 Vira YRC VIPAT vipa VIMA vine a WEE Lat omoa we Dae dedo Author nra ce faa 1 Atmel Vernea an Fie PLC Couing rSeroc me PLC Covina 116 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A Ek Kit User Manual UserGuide_03 Nov 2015 Figure A 6 SAM4C MCU 1 2 3 4 gau Ze GE KEE SES NPAT 70 D I pal FF Neue Ey ial KE Ge SE SES SE ey dw Re VBE s Numa SC E f ZAJ zB ZS ATSAMACI6CA AU aes we Si C56 PBI RIG DEER Wen Ire Vergers R67 ONE PA30 ES 107 2014 S ei vi Bel Description Date Author paras 2 echte Fels Ait nel Vernea an Fie Smesno Code number mme same S Figure A 7 ATPL230AMB Peripherals I 2 3 H Peripherals USER LEDS d PBI4 LEDO VOLTAGE MONITOR GREEN d PBIS LEDI SERIAL EEPROM 2Kb TAMPER amp FORCE WAKEUP VDDBU Tip TP47 aS hae Lv First Revision Rev Description Date Author Description mo e faea At mel Vernea AR Fie Porproraissenoos Code number Gs ATPL230A EK Kit User Manual USER GUIDE 117 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 118 Figure A 8 ATPL230AMB Interface
137. r otherwise to any Atmel intellectual property right is granted hereunder ATMEL SHALL NOT BE LIABLE FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES RELATING TO USE OF THIS EVALUATION BOARD SKIT ATMEL CORPORATION 1600 Technology Drive San Jose CA 95110 USA 120 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Revision History Doc Hey Date Comments 43075E 10 2015 Updating PRIME software version 43075D 06 2015 Updating PRIME software version and data information 43075C 03 2015 Updating kit s software project examples 43075B 11 2014 Updating kt e boards 43075A 04 2014 Initial document release ATPL230A EK Kit User Manual USER GUIDE 121 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Altmel Enabling Unlimited Possibilities lefolzfe Atmel Corporation 1600 Technology Drive San Jose CA 95110 USA T 1 408 441 0311 F 1 408 436 4200 www atmel com 2015 Atmel Corporation Rev Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Atmel Atmel logo and combinations thereof and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others DISCLAIMER The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any inte
138. rmware is not the right After these operations you can retry to establish the communication again between the board and the computer Once the communication is right Product Information tab of the PHY Tester tool is shown below in Figure 6 31 Figure 6 31 Product Information tab of the Atmel PLC PHY Tester tool Lay Atmel PLC PHY Tester Tool v2 3 Help Product Information Reception Parameters Rx Test Parameters Configuration Summary Description This tab shows information related with product identification model of the PCB and information about firmware version At the bottom of the tab it s necessary to select a choice between Transmision and Reception test Product Info Product Id SAM4C 16C PRIME Model Id 0x0000 Firmware Id 0x23000200 Test Selection Transmission Alttmel Enabling Unlimited Possibilities The Product Information Tab shows basic information of the type of board connected to and also asks the user to select the kind of test to be performed The showed information is related to the physical layer implemented in the firmware of the board e Product ID it shows a text string that identifies the Atmel PLC product platform e Model ID It is a 16 bit unsigned integer that identifies the model of the board e Firmware ID It is a 32 bit unsigned integer that identifies the physical layer firmware running in the board Now the user has to do a selection depending on whether the u
139. rs components services and utilities See the list below and Figure 6 4 for an overview of how the various modules are wired together e Boards contain mapping of all digital and analog peripheral to each I O pin of Atmel s development kits e Drivers is composed of a driver c and Oriver h file that provides low level register interface functions to access a peripheral or device specific feature The services and components will interface the drivers e Components is a module type which provides software drivers to access external hardware components such as memory e g Atmel DataFlash SDRAM SRAM and NAND flash displays sensors wireless etc e Services is a module type which provides more application oriented software such as a USB classes FAT file system architecture optimized DSP library graphical library etc e Utilities provide several linker script files common files for the build system and C C files with general usage define macros and functions e Applications provide application examples that are based on services components and drivers modules These applications are more high level and might have multiple dependencies into several modules ATPL230A EK Kit User Manual USER GUIDE 35 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 4 ASF modules structures Download link for more information http www atmel com tools AVRSOFTWAREFRAMEWORK aspx Please do not hesitate to visi
140. rts one ATPL230AMB board acts as a Base Lite node the other one ATPL230AMB board acts as Service node and the User Computer Figure 6 91 Atmel PRIME Manager setup Service Node User K Mains 230Vac Following sections explain to you how to install the PC tool select the projects supplying the boards select the COM ports to communicate with the ATPL230A and run the application ATPL230A EK Kit User Manual USER GUIDE 99 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 7 1 Atmel PRIME Manager tool installation To install Atmel PRIME Manager v2 a b tool in a Windows Operating System execute the provided installer in the PC Tools folder PC Tools Atmel_PRIME_Manager SN and follow the installation wizard The installer wizard should open To follow the installation click Next Choose for which users you want to install Atmel PRIME Manager p Select whether you want to install Atmel PRIME Manager for yourself only or for all users of this computer Click Next to continue Install for anyone using this computer Install just for me Select the users permissions and click Next Figure 6 93 Atmel PRIME Manager Installation process Atmel PRIME Manage le lg Welcome to Atmel PRIME Manager Setup Setup will guide you through the installation of Atmel PRIME Manager It is recommended that you close all other applications before starting Setup This will make it p
141. sage windows Figure 6 6 Tool Output window Output The Language options are available by choosing ools gt Options Use this page to specify the language to be used in windows menus dialog boxes etc For example it is very useful to enable line number display feature For that show the editor window and tick the Show line numbers options Editor options window is available in ools gt Options In addition to this you can use this window to configure the editor In order to build the project choose a build configuration in the combo box of the workspace window By default the IDE creates two build configurations when a project is created Debug and Release Every build configuration has its own project settings which are independent of the other configurations For example a configuration that is used for debugging would not be highly optimized and would produce output that suits the debugging Conversely a configuration for building the final application would be highly optimized You can build your project either as an application project or a library project You have access to the build commands both from the Project menu and from the context menu that appears if you right click an item in the Workspace window To build your project as an application project choose one of the three build commands Make F7 Compile Ctrl F7 and Rebuild All They will run in the background SO you Can continue editing or working with
142. se c Sniffer_DB sql Overwrite Append ATPL230A EK Kit User Manual USER GUIDE 105 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 At this point the tool is ready to start capturing data If board is not powered this is the point to supply it Click on the menu Connection gt Connect to begin logging data In case the serial COM port is not the proper or board is not powered tool shows an error window as the figure Figure 6 101 Error window mme t ATMEL PRIME MANAGE Error Sniffer could not be enabled Timeout error No response received If tool establishes the communication with the COM port of Service node the status bar at the bottom of the window will show the current setup and status of the tool On the other hand once the Base Lite node board is powered the green led D5 LEDO is blinking Once the boards are connected to the mains the PRIME network begins to form The Service Node listens to the Base Node beacons and starts the registration process shown This process is shown in the Figure 6 83 The Service Node sends the registration request and waits for the base node respond When the Base node sends a PLC message the TX led of the coupling board is toggled And when the Service node sends a message the TX led of the coupling board is toggled You can use them to check if boards are sending PLC messages properly 6 7 5 1 Opening a 4 32 connection PRIME specifies that is the s
143. se tools and performance are described in chapter 6 1 To be able to develop applications build binaries and program the firmware on the SAM4C16C device you can use the IAR Workbench or the Atmel Studio IDE In order to program the firmware on the board the JTAG connector is used see section 3 5 6 3 about JTAG programming mode and JTAG probe is required See previous Figure 6 22 which shows the JTAG connector J13 of the board Note that kits do not provide a J Link ARM or SAM ICE JTAG probe in order to connect to the user s host PC and the boards to download and debug the projects The process to load the file should be as is explained below in that process we use a programming tool J Link Tool Remember that the J Link USB drivers must have been downloaded previously from the Segger webpage see section 6 1 4 and they depend on your operating system A Place the JTAG connector of the J Link or SAM ICE in the J13 JTAG connector of the board Check pin number 1 of J13 connector to place the cable in the right position See the Figure 6 22 B Switch on the power supply of the board C There are two ways to program the board a Launch the IAR or AS IDE and select the PHY Tester tool project Build the project apps phy _tester eww or apps phy tester atsin to generate the output file Now you can ATPL230A EK Kit User Manual USER GUIDE 49 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 download the file to the
144. ser selects transmission or reception test different tabs are added For reception tests Reception Parameters and Rx Test Parameters tabs are added For transmission tests Transmission Parameters and Tx Test Parameters tabs are added Finally independently of the kind of selected test two more tabs are added Configuration Summary and Test Execution First we will describe the process to configure a board as receptor and after that we will describe how to configure the other board as emitter Selecting the Reception option and clicking the Next button a tab appears as the following image Figure 6 32 54 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 32 Reception Parameters tab tC Atmel PLC PHY Tester Tool v2 3 Reception Parameters Rx TestParameters Configuration Summary Description This tab allow to configure the channel in which board is going to receive the messages This is the only configuration needed by the PHY layer in order to receive messages Coupling Selection A Warning You must to select the same coupling you have plugged in the board A Check the coupling identifier that you can find in the coupling board If current coupling is not the proper one for the channel you want to receive please remove it and connect the proper one Also verify that Vdd is the correct for the coupling board selecte
145. sier to load the bin files of the Service and Base Lite nodes software examples Atmel provides you a script program _bin bat that lets you download the proper bin files in the right memory address position You can find them in the following directory Software PRIME_vaa bb cc dd Scripts SN or Software_vaa bb cc da Scripts BN Example Scripts to load SN Service Node with DLMS capabilities running as microcontroller mode show an error when programming process falls A typical error could be when the J Link tool is a different version of the written in the script or in a different path To solve it edit the path according to your installation folder in the bat file program_bin bat file code c Program Files x86 SEGGER JLink V496b JLink exe program bin jlink Note Edit the path to JLink exe according to your installation folder and J Link version program_bin jlink file code exec device ATSAM4C16C device speed 0 E reset h halt load bin files loadbin apps prime service dlmsemu_ui 230 bin 0x01000000 loadbin apps prime service modem flash bin 0x01000000 loadbin prime service Stack bp OxOTOFO000 Loadbin prime service Steck bin OxO10HO000 34 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 r reset g go OC quit and close Note Take into account that the previous memories allocation are to load binaries compiled with IAR
146. st want to stop the program and keep the debug session active simply click on the Pause button If you modify any of the files of the project you need to do a Rebuild and not only a Build Do a right click on the project name in the Solution Explorer and then click on the Rebuild button In case you only want to download the program on the SAM4C16C without debugging clicking on the Start Without Debugging button H Close the project on the toolbar File gt CloseSolution For further information please refer to the tool s embedded help in the menu bar or visit the webpage http www atmel com microsite atmel_ studio6 default aspx 6 2 PLC application example 1 PHY Tester The boards of the kit by default are programmed with the embedded PLC PHY Tester tool firmware for SAM4C16C device apps phy tester too bin It is an application example that shows the capabilities of the ATPL230A in a point to point connection physical layer This application requires a pair of boards and a PC tool Atmel PLC PHY Tester tool which has to be installed in the user s host PC to interface with the boards ATPL230A EK Kit User Manual USER GUIDE 43 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 In any case if you want to load this file again you have to build the project apps _phy_tesier_ tool to generate the output file to program See section 6 2 4 to know more about programming the ATPL230AMB boards
147. t our web site to get the last library updates 6 1 7 First steps with IAR When working with programming in general it is important to have some structure in your coming projects and code IAR Embedded Workbench is made to support such demands The upper abstraction of a task is called Workspace within each workspace you can add projects The projects added ina workspace could be supporting the same device or have something in common Each project contains code and settings for each target So what we need to do is first make a workspace then add a new project to this workspace When this is done you should be able to include an application code to your project and make all the settings for the target SAM4C16C on your ATPL230AMB board IAR Embedded Workbench supports the SAM4C core family preferred 7 10 1 versions or above Once the IAR Embedded Workbench has been installed Open IAR Embedded Workbench Click the Start button on the Windows taskbar and choose All Programs gt lAR Systems gt lIAR Embedded Workbench for ARM gt IAR Embedded Workbench The file aridePm exe is located in the common bin directory under your IAR Systems installation in case you want to start the program from the command line or from within Windows Explorer The workspace file has the filename extension eww If you double click a workspace filename the IDE starts If you have several versions of IAR Embedded Workbench installed the workspace file is opened by the most
148. t unit FPU five USARTs two UARTs two Wis up to seven SPls as well as a PWM timer two 3 channel general purpose 16 bit timers temperature compensable low power RTC running on backup area down to 0 5 UA and a 50 x 6 segmented LCD controller The ERASE pin can be used to reinitialize the Flash content so setting a jumper in J14 connector Figure A 6 the flash content is erased This pin integrates a pull down resistor of about 100kQ so that it can be left unconnected for normal operations When the ERASE pin is tied high during less than 100 ms it is not taken into account The pin must be tied high during more than 220 ms to perform a Flash erase operation Please refer to SAM4C datasheet doc1 1102 for a further description on Atmel s website Figure 3 7 J14 jumper ERASE fled hoc ene EN alll SEHR Ce ECK KR RR e TZ a R SCCII WE T J Ts We TE Ke ART wg r r 3 wv ZZ P Ty e R Ride N sasssa ds RET SS ERAS Por m gt le N d gt N oa bead m S Ps aah Ee gt l d r rr y j R Kai 3 5 3 2 SAM4C16C Clocking A 12 MHz Crystal oscillator is used as SAM4C16 clock input Y1 Figure A 6 But board uses the clock output of ATPL230A A slow clock crystal oscillator of 32 768 kHz Y2 Figure A 6 is used as SAM4C16 clock base in low power mode and for the embedded Real Time Clock RTC 3 5 4 PLC Coupling Atmel PLC tec
149. tart Test button A new tab is enabled at first the table is empty because any frame has been received Note that there is a timeout to wait the frame reception Figure 6 35 Test Execution tab Lu Atmel PLC PHY Tester Tool v2 3 Help Product Information Reception Parameters Rx Test Parameters Configuration Summary TestExecution Atmel Enabling Unlimited Possibilities lt lt Prev Restart Once the receiver board has been configured the emitter board must be configured Launch another Atmel PLC PHY Tester tool and once the transmission board is supplied and USB cable connected configure the corresponding COM port for the board in the window Starting Window Once COM port is selected click the Connect button As soon as the button is clicked the button text will change to Connecting Then the application and the board start a process of identification and after few seconds the button text will change to Disconnect This means that the identification process has finished A new Tab Product Information is appended to the wizard and Next button This time we select in Product Information tab the Transmission process Figure 6 36 ATPL230A EK Kit User Manual USER GUIDE 57 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 36 Transmission option selection Lu Atmel PLC PHY Tester Tool v2 3 Help Product Information Tx Test Parameters Configuration Summary Des
150. task mode operation typical of operating systems In order to do that it creates and manages a single task where all active layers and interfaces are included The user does not need to take care of controlling how the PRIME stack is running and can create their applications normally The current implementation of the OSS is based on FreeRTOS but the user could modify it appropriately to use any other RTOS The Service Node project provided in the kit only provides the Atmel PRIME layers The Physical layer provided is in source code The Figure 6 67 shows the Atmel PRIME Stack structure and the Figure 6 68 shows the PRIME FW Stack project structure for the SAM4C16C according to the ASF structure The Atmel PRIME FW stack modules are from the bottom up e Physical Layer PHY e Physical Abstraction Layer PAL e Medium Access Control MAC layer e Convergence Layer CL e Management Plane MNGP 80 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 67 Atmel PRIME Firmware structure PRIME Stack PRIME API As it can be seen in the previous figure the only entry point to the PRIME Firmware stack is through the PRIME API which contains the interfaces defined in the PRIME specification as well as stack control functions Furthermore it must be noticed that the Hardware Abstraction Layer HAL including the Atmel Universal Serial Interface USI is n
151. ted in section 6 2 4 the way to program a board Open the IDE tool used Atmel Studio or IAR Embedded Workbench Select the project apps _phy_tx_test_console aisin or apps_phy_tx_test_console eww and build it to generate the output file Now you can download the file to the board Note that kits do not provide a J Link ARM or SAM ICE JTAG probe in order to connect to the user s host PC and the boards to download and debug the projects Remember that the J Link USB drivers must have been downloaded previously from the Segger webpage see section 6 1 4 and they depend on your operating system Remember that every PHY TX Test console example project is contained in the following folder Software PRIME_vaa bb cc dad phy atol230amb thirdparty prime_ng phy atpl230 apps oh y_tx_test_console sam4c16c_atpl230amb And also in the PHY common workspace ATPL230A_PLC_examples which is contained in following Software folder Software PRIME_vaa bb cc dd phy atol230amb thirdparty prime_ng apps wrkspcs 64 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 3 4 Running the PLC application example 2 As the PLC application example 1 boards are plugged to the mains see Figure 6 42 Users have to execute an instance of the serial interface tool which has been previously installed to the host PC in order to enable communication between both boards Please note t
152. tek RTL8139 810x Family Fast Ethernet NIC 2 a Y Ports COM amp LPT 727 Communications Port COM1 A Silicon Labs Dual CP210x USB to UART Bridge Enhanced COM Port COM35 Basic options for your PuTTY session PF Silicon Labs Dual CP210x USB to UART Bridge Standard COM Port COM36 gt Kl Processors Close window on exit b es vive and game controllers Always Never Only on clean exit gt gM System devices p P Universal Serial Bus controllers Set 115200 in the Speed field In the Serial Category change the Flow Contro to None The other fields should already be correctly configured Finally click Open ATPL230A EK Kit User Manual USER GUIDE 65 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 45 PuTTY Configuration instance Sen coger a Category Session Options controlling local serial lines Logging B Terminal Keyboard Serial line to connect to COM36 Bell Features 6 Window Speed baud Appearance Behaviour Translation Stop bits Selection i Colours Panty Connection Flow control Data Proxy Telnet 7 Rlogin Select a serial line Configure the serial line Data bits Once board is supplied leds LEDO and LED1 blinks several times After that main menu is displayed press Reset button in case board has been supplied previously to connect USB cable
153. th the COM port of the ATPL230AMB the status bar at the bottom of the window will show the current setup and status of the tool On a PRIME network the main window will look like as the Figure 6 60 Main window displays a table with the current log It is updated in real time as frames are received from the hardware sniffer 74 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 60 ATPL Multiprotocol Sniffer tool main window r ATPL Multiprotocol Sniffe File Configure Capture View About O O mN idFrame TimeStamp Modulation Symbols SNR ExSNR RSSI Channel Duration Delta CRC Up Down Level Pdulype GenType Lcid Sid Lnid CAPTURING USB Serial Port COM100 B115200 DB File ATPL log sql APPEND The capture window has a tool bar with four commands see Figure 6 61 e Pause command will stop the update of the scroll view while the logging process will continue e Torestart showing the live stream of PDUs click Play button e Channel combo box allows selecting the PRIME channel to listen Obviously the compatible PLC coupling board must be used e Thunder button will set the CRC configuration on the hardware device If it is enabled the hardware device will calculate the CRC on all the frames and discard frame errors If it is enabled all frames received will be sent to the PC software Figure 6 61 Tool bar O 0 feu JIN Main window displays a table w
154. the COM port and set the speed The default port is UARTO enhanced COM port and the speed for this ATPL230A EK Kit User Manual USER GUIDE 73 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 application is 256000 bauds Also this tool is able to connect to a remote device through the TCP IP protocol Figure 6 58 Input Settings window Input Settings Protocol Connection Serial Port Input GC TCP AP Input Serial Port Communications Port COM1 TCP IP Connection Host IP 197 0 0 1 Port s0820 The database file to store the traffic must be configured If output logs are required and the location to store these choose Configure gt Database Ctrl D A new window Database Settings will appear as shown in Figure 6 59 select the file name and click OK button Database files can hold longer logs without having to split them in pieces Also log stored files can be opened to review the file The three options when you create a log database depends on if you want to keep the previous data or not And it is possible to build your own scripts for example in Python to analyze the data Figure 6 59 Database Settings window Append Overwrite Datetime Suffix At this point the tool is ready to start capturing data If board is not powered this is the point to supply it Click on the menu Capture gt Start to begin logging data If tool establishes the communication wi
155. the IDE while your project is being built Error messages are displayed in the Build window If your source code contains errors you can jump directly to the correct position in the appropriate source file by double clicking the error message in the error listing in the Build window or selecting the error and pressing Enter After you have resolved any problems reported during the build process you can directly start debugging the resulting code at the source level Process to build compile load and debug the project over the board could be DDP 1 Choose Project gt Make or click the Make button 2 on the toolbar The part should compile with no errors 2 Connect the SAM ICE JTAG probe 3 Supply on the board 4 Choose Project gt Download and Debug or click the Download and Debug button amp on the toolbar to download your program to the board 5 The file phy tester _tool c is now open in the editor window and the program is stopped at the start Choose Debug gt Go or click the Go button Zi on the toolbar to start the application Your IAR IDE window should now look like Figure 6 7 6 Once the board is powered the green led D5 LEDO is blinking DOG 7 To stop C SPY click the Break button _ on the debug bar 38 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 6 1 8 8 To exit C SPY click the Stop Debugging button x on the toolbar 9 To exit the
156. tion about the tool please refer to the tool s embedded help in the menu bar 6 3 PLC application example 2 PHY TX Test Console This example explains how to use the project application called APPS PHY TX TEST CONSOLE This application lets the user to configure a proper setup to perform both EMC emissions and immunity tests for ATPL230AMB board These tests are based on the use of PRIME PHY layer with a terminal console firmware apps _phy tx test console bin that eases the configuration of several transmission parameters such as modulation frame data length and time interval between frames Following chapters explain to you how to supply the board select the UART1 to communicate with the ATSAM4C16C load the firmware and run the application The setup is shown in the following figure ATPL230A EK Kit User Manual USER GUIDE 63 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 42 Boards connection scheme 6 3 1 Supplying the boards Please refer to 6 2 2 in order to Know how to supply the ATPL230AMB boards 6 3 2 USB connection Please refer to 6 2 3 in order to Know how to connect the micro USB cable with the ATPL230AMB board Remember to select the Standard COM Port UART1 As is commented in section 3 5 6 4 UART 1 is available by USB connector J9 UART1 CMOS signals are also available in a triple row male connector J5 see Figure 6 22 6 3 3 Programming the embedded file We have commen
157. tions windows show some statistics See the following figures 60 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 Figure 6 40 Transmission test result Product Information Tx Test Parameters Configuration Summary Frame z TxResult RMS Calc Data Tx Interval Tx Succesful 3184 Atmel Enabling Unlimited Possibilities 99 Tx Succesful Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3186 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3190 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3191 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3181 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3190 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3172 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3172 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3189 Atmel Enabling Unlimited Possibilities 100 Tx Succesful 3188 Atmel Enabling Unlimited Possibilities 100 Total Frames Transmitted 100 Total Bytes Transmitted 4200 Total Phy Layer Error Frames 0 Frames Not Transmitted due to Busy Tx 0 Frames Not Transmitted due to Busy Channel 0 Frames Not Transmitted due to Bad Len 0 Frames Not Transmitted due to Bad Format 0 Frames Not Transmitted due to Timeout 0 Tx Test Frame Type Type A PRIME v1 3 6 Modulation Scheme DBPSK Message Atmel Enabling Unlimited Possibilities Message Length 39 bytes
158. ton Reset button e Interface JTAG debugging port Xplained PRO Master Slave Interface UARTs over USB and CMOS levels ATPL230A SPI Control of 3V3 power supply Figure 3 2 ATPL230AMBv4 multi purpose modem board BN MIMO XPLAINED PRO TARGET E 5V Buck 3V3 A Conveter LDO 12 16V 12 16V ett Buck PLC DRIVER S 3V3 SHDN USARTO eines Conveter DATAFLASH Zero Crossing Detector USART2 Transformer Sy lt voosu DT D 1c _ SPIO INT RST PLC FILTER d Ser as ATPL230A SPI SPI INT RST SPI INT RST NAAA rm ATPL230A EK Kit User Manual USER GUIDE 15 Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 3 3 Block diagram Figure 3 3 ATPL230AMBv4 Block diagram ih L T DRUI 3 4 Mechanical and user considerations Zem IT ATPL230A kl Q _ Q 5 E L Y Leem U EE KE This development board is directly powered from mains grid so hazardous voltage is present on the board To avoid user access to dangerous parts ATPL230AMB must always be used in its enclosure All required connectors and configuration jumpers are easily accessible without removing the enclosure cover gt A normal use of the ATPL230AMB does not require removing the enclosure cover If this action is necessary it must be performed by qualified staff being sure that mains connection has been previously remov
159. tween the PRIME Base Node and the Service Node The Service Node responds dummy DLMS messages after receiving data requests from the Base Node It is an application example that shows how the PRIME API should be used Depending on the operation mode as a Real Operating System or as Microcontroller there are two projects APPS PRIME_SERVICE_DLMSEMU_U running as microcontroller mode APPS _PRIME_SERVICE_DLMSEMU_Flrunning as OSS mode Remember that DLMS application project running as microcontroller mode is contained in the following folders depending on the IDE tools used Software PRIME_vaa bb cc dd prime_service_dimsemu_ult atol230amb thirdparty orime _ng apps prime_service_dimsemu_ui sam4c16c_atol230amb as5_arm Software PRIME_vaa bb cc dd prime_service_dimsemu_ult atol230amb thirdparty orime _ng apps prime_service_dimsemu_ui sam4c16c_atol230amb as5_arm iar DLMS application project also implements the AppEmu Application Emulation application for PRIME certification This application is required for certification purposes see Test Cases of PRIME Certification document To enable the AppEmu PC3 pin should be at 0 volts So previous to supply the board you must set a jumper between the PC3 pin and ground GND For that set a jumper in J10 connector XPLAINED PRO as is showed in the following figure 84 ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 201
160. u_ui sam4c16c_atol230amb as5_arm iar Remember that the J Link USB drivers must have been downloaded previously from the Segger webpage see section 6 1 4 and they depend on your operating system An alternative process to load the Service node project and Base Lite node files should be as is explained below 1 Place the JTAG connector of the J Link or SAM ICE in the J13 JTAG connector of the board Check pin number 1 of J13 connector to place the cable in the right position 2 Switch on the power supply of the board ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 89 3 Download the binary file using a command script file See section 6 1 5 To do easier to load the bin file Atmel provides you a script for Service node program_bin bat and Base Lite node program_bin bat which lets you download the bin files in the right flash memory position You can find them in the following directories Software_vaa bb cc dd Scripts SN and Soft ware_vaa bb cc dd Scripts BN This script loads the files and shows an error when it falls A typical error could be when the J Link tool is a different version of the written in the script or in a different path To solve it edit the path according to your installation folder in the bat file See section 6 1 5 for more information Please make sure all nodes Base and Service have valid MAC addresses An invalid MAC makes
161. utput window Figure 6 113 Base node results PRIME Management O x Serial rofl SS Banned MACS phyStatsRxTotalCount 0x00a4 Get PIB Gelb 4 bytes 0 to 4294967295 or Ox 05 06 2015 12 10 14 530 PIB 0x00a4 Value 0x000007d8 2008 Connected Serial COM4 6115200 Server 9098 Ati el 6 7 5 5 Using the Manufacturing Test features tab Process to use the Manufacturing test mode with the Atmel PRIME Manager tool for Service node should be e Select the MFG Test tab e Click Enable e Click Get MAC e The MAC number appears in the MAC box and the executed operation appears in Log output window e Write anew MAC number in the box e Click Set MAC e The executed operation appears in Log output window See the figure below e To finish click Disable Note For this example the Service node requires Serial protocol so it has been programed with prime_service_modem_atpol230amb project or prime_service_dimsemu_ul atol230amb project ATPL230A EK Kit User Manual USER GUIDE Atmel 43075E ATPL ATPL230A EK Kit User Manual UserGuide_03 Nov 2015 111 Figure 6 114 Setting the MAC with the Service node tool application ATMEL PRIME MANAGER w2 0 7 File Connection View PRIME Management PLME MLMEPIBs SerialProfle MAC 432 PLME MIME Certification MFG Test MAC PHY SW version 01 40 90 87 00 74 ID Version MAC SW version SNA 00 00 00 00 00 00 ID Trans

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