ProceV - GiDEL
Contents
1. FPGA IP LVDS MTBF PCB PLL PSDB RTL IC Preliminary ProceV Data Book Application Specific Integrated Circuit Double Data Rate Dynamic Random Access Memory Field Programmable Gate Array Intellectual Property Low Voltage Differential Signaling Mean Time Between Failures Printed Circuit Board Phased Locked Loop ProceV Daughterboard Register Transfer Logic System on Chip Integrated Circuit 16 0 Revision History 16 1 PCB History Table 31 PCB History Revision Changes Rev 1 Initial PCB e Changes of HS connector data Rev 2 o Removal of HS A connector o HS B pin out change 16 2 Firmware History Table 32 Firmware History Revision Changes Rev 46 Initial code 16 3 ProceV Data Book History Table 33 Data Book History Date Changes 10 2012 Initial document e Update of ProceV models 12 2012 e Update according to PCB Rev 2 e Update of System Diagram e Addition of high speed reference clocks for Stratix V transceivers 05 2013 Update of board models including an option for 36 Mb DDR SRAM option Update of model numbering Updated Fig 3 Components Side 01 2014 Connectors Updated the HS connector connectivity Table 9 10 11 Preliminary ProceV Data Book2. Reset signal when driven 0 by the Open Collector host cxp_int_reset INT_L RESET_L VO Interrupt signal when driven 0 by the module Table 7 CXP Top Level Signals Preliminary ProceV Data Book Connectors 7 3 SFP Connectors J18 The ProceV has dual SFP cage suitable also for 2 x 10 Gigabit Ethernet cupper and Optical Transport Network Connector A Connector B Equivalent FPGA I O Description Top Level Top Level SFP Direction Signals Signals Protocol Name sfp_tx_fault_a sfp_tx_fault_b TX_FAULT Module Transmitter Fault sfp_tx_disable_a sfp tx disable b TX_DISABLE Transmitter Disable sfp_sda_a sfp_sda_b A Open C Data collector 1 0 SD SCL sfp_scl_a sfp_scl_b Open C Clock collector 1 0 sfp_mod_abs_a sfp_mod_abs_b MOD_ABS Input 1 Module Absent 0 Module assembled E Input Signal Indication Input Output Output Table 8 SFP Top Level Signals Preliminary ProceV Data Book Connectors 7 4 High Speed Inter Board Connectors J6 7 The ProceV has two HS High Speed inter board connectors for board to board and daughterboards connectivity These connectors are designated HS B and HS C respectively The HS connectors have Rx and Tx differential pairs that are connected to a Stratix V 600 Mb s 12 5 14 1 Gb s transceivers The Rx pair are designated hs_rxp X and hs_rxn X and the Tx pair are designated hs_txp X and hs_rxn X The Rx and Tx pairs together provide a full duplex lane
3. The PSDBs enable to connect to Ethernet and to external I O lines and to interface with video applications including DVI SDI and Camera Link standards For detailed list of GIDEL s PSDB daughterboards refer to the PSDB Compatiblity Data Sheet Note that the ProceV supports PSDB type 1 daughterboards only Preliminary ProceV Data Book 13 0 Appendix 13 1 Throughput Calculations 13 1 1 M20K Throughput Calculations gt Largest bit width configuration of the M20K block 40 gt Width in true dual port mode 2x40 bit 80 bit 10 Byte gt Maximum M20K blocks usage in a 5SGXAB device 2640 gt Typical performance 300 MHz M20K throughput 10 x 2640 x 300 7 920 GB s 13 1 2 Stratix V MLAB Throughput Calculations gt Largest bit width configuration of the MLAB block 20 gt Width in true dual port mode 2x20 bit 40 bit 5 Bytes gt Maximum MLAB blocks in single 5SGXAB device 17960 gt Typical performance 300 MHz MLAB throughput 5 Bytesx17960x300 MHz 26 940GB s 13 1 3 On board SRAM Memories Throughput Calculations gt Onboard memory performance 400 MHz DDR gt Bus Width 36 bit 4 Bytes gt Number of optional on board memory modules 2 On board Memory throughput 400x2 x4x2 6 4 GB s Preliminary ProceV Data Book Appendix 13 1 4 DDR3 SDRAM SODIMM Throughput Calculations SODIMM Bank B and C gt Bank SODIMM performance 1600 Mb s DDR gt Bus width 8 byte gt
4. Daughterboards Preliminary ProceV Data Book Table of Contents 13 0 Appendix 13 1 Throughput Calculations 13 1 1 M20K Throughput Calculations 13 1 2 Stratix V MLAB Throughput Calculations 13 1 3 On board SRAM Memories Throughput Calculations 13 1 4 DDR3 SDRAM SODIMM Throughput Calculations 13 1 5 Additional Devices Needed 14 0 References 14 1 References 15 0 Glossary 16 0 Revision History 16 1 PCB History 16 2 Firmware History 16 3 ProceV Data Book History Preliminary ProceV Data Book Figures Figure 1 ProceV System Block Diagram Figure 2 ProceV Clock System Figure 3 Components Side CS Connectors Figure 4 Print Side PS Connectors Figure 5 ProceV Mechanical Dimensions in mm Preliminary ProceV Data Book Tables Table 1 ProceV Memory Throughput Table 2 GiDEL ProceV Standard Models Table 3 DMA Performance Benchmark System Table 4 DMA Performance Table 5 Component Side Connector Description Table 6 Print Side Connector Description Table 7 CXP Top Level Signals Table 8 SFP Top Level Signals Table 9 HS B Connector J6 Pin out Table 10 HS C Connector J7 Pin out Table 11 HS Connectors Top Level Signals Table 12 PSDB_L J4 connector pin out Table 13 PSDB_L J4 pin out in LVDS Mode Table 14 J3 General Purpose IO Connector Assignments Table 15 IO Working Frequency Table 16 88E1118R PHY Top Level Signals Table 17 Power Connector Pin Map cable side Table 18 P
5. The PSDB connector J4 is located on the Print side of the ProceV board as shown in Figure 4 J4 is 120 pin multi purpose connector that can also be used in LVDS mode Table 12 and Table 13 provide pin out information for the J4 PSDB connector The PSDB connector is a multi purpose connectors that can function in single ended or LVDS mode as detailed in Table 12 and Table 13 respectively All the signals marked as Reserved are reserved for GiDEL use These pins must be left unconnected on the user s PSDB When a GiDEL PSDB is connected to the ProceV the generated FPGA top level bus names that appear in the tables below will be changed to match the relevant PSDB functionality Preliminary ProceV Data Book Table 12 PSDB_L J4 connector pin out Pin PSDB Signal Connectors PSDB Signal LO L60 CLK_OUT1 L61 L1 L_1017 DBO L62 L2 Reserved L63 L_IN1 L39 L64 L4 L40 L_1018 CO Nj on AIJNI L3 L_1010 L65 L5 L41 L66 L42 L67 L7 L43 L 1019 L6 L EO L68 L8 L44 L69 IL OW L45 L70 L10 L46 L_IN6 Le IHO12 L71 L11 L47 L_IN7 IL Oi L48 Le L13 L49 12V 0 3A Liz L_1013 L73 L14 L50 CLK_OUTO Mo L51 GND L16 L52 GND
6. a part of GIDEL Proc Developer s Kit Each memory can be used for parallel data streaming and for debug data capture Flexible clocking System Temperature monitoring Supported by GiDEL s Proc Developer s Kit management software Drivers for Windows and Linux 64 bit Operating Systems Preliminary ProceV Data Book Key Features 3 1 ProceV Performance The ProceV system provides high performance capabilities Table 1 details the ProceV s throughput and memory capacity Note that the performance is dependent on Proc board model Table 1 ProceV Memory Throughput Memory Capacity Typical Data Rate Throughput Structure Per Single Data Bit Embedded Up to 2640 x 300 MHz 8 000 GB s in FPGA M20K Blocks Optional 2 x 144Mb or 800 Mb s 6 4 GB s On Board 2 x 36Mb SRAM Memory 36 bit SODIMM 2 x 8GB DDR3 1600 Mb s 19 2 GB s Modules Refer to the Appendix for throughput calculations paragraph 13 1 For further information regarding the embedded memory blocks refer to the Altera Stratix V Handbook Preliminary ProceV Data Book 4 0 Standard Models This chapter details the standard models product available The model names have the following structure Proceaa bcdeefg where aa Type of Stratix V devices GX Device A3 A7 AB GS Device D8 b Speed grade A 1 speed grade B 2 speed grade 3 speed grade c CXP Option X CXP Blank without CXP d SFP option S with SFP A and B Blank without SFP ee
7. must be lt 54W or 57 for 5 power supply accuracy Preliminary ProceV Data Book Technical Specifications 10 5 ProceV Timing Model 10 5 1 Groups Skew Table 26 Groups Skew epe O e Skew ps Bo PCle_tx 7 0 PCle_rx 7 0 CXP_tx 11 0 CXP_rx 11 0 HS _rx 3 0 B or C HS_tx 3 0 B or C SODIMM bank B or C all DQ groups SODIMM SODIMM bank B or C DQ Group 1 SODIMM bank B or C Address amp Control 2 SRAM SRAM bank D or E Address amp Control 3 SRAM SRAM bank D or E Data amp Clock 4 25 PSDB LVDS tx_ 27 0 Notes 1 Every group of SODIMM DQ contains 8 lines of DQ 1 of Diff DQS 1 of DM 2 Every group of SODIMM CONTROL contains 2 lines of Diff CK Addresses BA RASn CASn ODT CKE Sn and WEn 3 Every group of SRAM Address amp Control contains Diff line of K Addresses LDn odt qvid and R Wn 4 Every group of SRAM Data amp Clock contains Diff line of CQ BWSn and DQ Preliminary ProceV Data Book 10 5 2 Clock Accuracy Table 27 Clock Accuracy Description Technical Specifications Maximal Deviation Oscillator accuracy 10 5 3 System I O Frequency Table 28 System I O Frequency Bus 10 ppm Maximum Frequency PSDB Single Ended L_IN L_IO L_IO L 300 Mb s PSDB LVDS Memory bank B and C SODIMM Memory bank D and E SRAM Frequencies are PSDB design dependent Preliminary ProceV Data Book 1 25 Gb s 1600 Mb s 800 DDR 900 Mb s 45
8. strobes coupled with differential pairs DQSn 0 8 dqsn_b 0 8 dqsn_c 0 8 DQSn 0 8 Data strobe differential data strobes coupled with differential pairs DQS 0 8 ba_b 0 2 ba_c 0 2 BA 0 2 Output Bank address inputs define the device bank to which an ACTIVE READ WRITE or PRECHARGE command is being applied ck_b 0 1 ck_c 0 1 CK 0 1 Output Clock differential clock inputs these signals coupled with differential pairs CKn 0 1 ckn_b 0 1 ckn_c 0 1 CKn 0 1 Output Clock differential clock inputs coupled with differential pair CK 0 1 Preliminary ProceV Data Book Memories cke_b 0 1 cke_c 0 1 CKE 0 1 Output Clock enable Enables registered HIGH and disables registered LOW internal circuitry and clocks on the DRAM cs_b 0 1 cs_c 0 1 S 0 1 n Output Chip select Enables registered LOW and disables registered HIGH the command decoder resetn_b resetn_c Resetn Output Reset RESETn is an active LOW LVCMOS asychronous Output that is connected to each DRAM and the registering clock driver odt_b 0 1 odt_c 0 1 ODT 0 1 Output On die termination Enables registered HIGH and disables registered LOW termination resistance internal to the DDR3 SDRAM event_b event_c EVENTn Temperature event The EVENTn pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded sda sda SDA 1 O Serial data Used to transfer addresses and data into and out of the tem
9. such as FPGA loading DMA interfaces interrupt service routines board clocking system setups and board information acquisition such as the number of FPGAs their size the speed grade etc The Upper Layer is automatically generated by ProcWizard This class inherits from the Proc class and implements all the application specific functionality It loads the Stratix V devices sets up the board clocking and initializes all the class members to allow simple access to the board application from the user workspace Preliminary ProceV Data Book GiDEL Accessories The ProcWizard can also automatically generate the following HDL code interface module entity Verilog VHDL or AHDL that communicates with the software driver ProcMultiPort on board memory controller instantiations Basic PLLs to control external memories Top level design that connects all instantiations with user modules entities and the on board local bus and memories Device constraints including FPGA pin out pin power voltage VCCIO Quartus operation recommendations etc The ProcWizard also enables the user to Test and debug the design in a PC environment Access the board with a structural browser and macros scripts Load save and compare memory files to check data transfers Real time access to the registers memories defined in the design Documentation generation in HTML or DOC format that describes in detail the generated features For more inf
10. used as a slow emulation clock Clk2 s frequency is derived from clkO divided by an even number Memory reference clocks mem_ref_clk is a 125 Mhz clock used as SODIMM Bank B and Bank C reference clocks The mem_ref_clk is fixed at 125 Mhz for all GIDEL boards enabling code migration and a fixed frequency source 5 3 2 ProceV Individual Clocks External clock inputs ext_clk is an external clock received from the SMA connector J17 In single ended mode J4 PSDB _L has two external dedicated clock inputs I 35 and I 38 mode and in LVDS mode two differential receive locks clk_rx 1 0 J4 PSDB Lis a PSDB type 1 connector with 2 backward compatible output clocks clk_out 1 0 On the ProceV clk_out 1 0 may also be used as regular I Os Preliminary ProceV Data Book 13 Board Architecture 5 3 3 ProceV High Speed Reference clocks The high speed reference clocks are generated from an external high precision PLL and are in particularly intended for driving the Stratix V transceivers There are four high speed reference clocks two connected to the left side and two to the right side of the Stratix V device as follows Preliminary ProceV Data Book 6 0 DMA Controller The ProceV board has 32 DMA channels The DMA channels enable the board to have master control over the PCle while keeping simple internal logic and random access as Slave only The DMA is controlled by a driver and enables easy and effective usage of memory
11. 0 DDR 11 0 Installation 11 1 Requirements To compile HDL designs for ProceV boards the following system requirements are necessary v The installed Quartus version must support Stratix V devices and their specific packages v The user s computer must be at least a I7 with sufficient memory normally 6GB Vv 64 bit OS v 8 lane PCle slot GiDEL Proc Developer s Kit and ALTERA Quartus software may run on the same or different computers 11 2 Installing the ProceV board Inserting removing the ProceV board to from the PCI Express slot when power is ON is NOT PERMITTED Inserting removing daughterboards to from ProceV daughterboard connectors is NOT PERMITTED when power is ON These operations might damage ProceV board devices or the daughterboard Preliminary ProceV Data Book Installation 11 3 Loading Designs in PCI Express Mode Configuring the Stratix V FPGA rbf file loading via the PCI Express bus by one of the following methods 1 The GiDEL ProcWizard GiDEL s development software can be used to automatically load the device s at startup In addition ProcWizard provides a command that reloads the FPGA in real time 2 The user software can load the FPGA via the Application Driver automatically generated by the ProcWizard The design is automatically loaded upon creation of the Application Driver class object or later on by using the InitIC API method For further information please refer to the Pro
12. 1Gbit Ethernet PHY Option 1G with PHY Blank without PHY f SRAM Option M 2x36 Mb 450 Mhz DDRII SRAMs Blank without SRAM other combinations are available for a quantity if 10 or more boards g External Clock Option CK External clock Blank without external clock The following table is a list of the available ProceV models Table 2 GiDEL ProceV Standard Models Ordering Code StratixV Speed DDRIII LEs M20K 18x18 Basic Models Device Grade SODIMM Blocks Multipliers Sockets ProceVA3 C 5SGXA3 2 957 512 ProceVA3 CX 5SGXA3 957 512 ProceVA3 CS 5SGXA3 512 5SGXA3 512 512 ProceVA3 BX 5SGXA3 512 ProceVA3 BS 5SGXA3 512 mh YN NN amp amp amp w ProceVA3 B 5SGXA3 ProceVA3 BXS 5SGXA3 512 Preliminary ProceV Data Book Board Architecture Table 2 continued from previous page Ordering Code StratixV Speed DDRIII LEs M20K 18x18 Basic Models Device Grade SODIMM Blocks Multipliers Sockets ProceVA7 BXS 5SGXA7 E 2 560 512 ProceVAB BXSM 5SGXAB 2 640 704 ProceVD8 BXSM 5SGSD8 3 926 LE Logic Element For further information on the Stratix V LEs refer to Stratix V Device Handbook Altera Corporation Eor other ProceV models contact GiDEL NOTE Default transceivers are K2 12 5 Gb s for transceivers K1 14 1 Gb s please contact GiDEL Preliminary ProceV Data Book 5 0 Architecture This chapter details the ProceV architecture and components 5 1 ProceV Block Dia
13. DB GND pins must be connected to GND These are virtual signals The PSDB connectors have two power strips in the middle Signals 121 124 are connected to the top middle strip and signals 125 128 are connected to the bottom one The top strip must be connected to GND and the bottom strip to the PSDB 3 3V source Should not be connected in LVDS mode OO CO N OD oy Bio Po a o oif of of oa a of of ao O CO N OD oO AIIN oO N Oo ine N N N wo NO A N o N O N N N oe N ao l a N s kk Preliminary ProceV Data Book Connectors 7 6 External I O Connector J3 The ProceV provides 12 bidirectional buffered LVTTL general purpose IO lines via the J3 connector The J3 connectivity is divided into two IO data groups IO 7 0 and IO 11 8 The ext_io_dir0 and ext_io_dir1 signals define the data transmission direction relative to the STRATIX V FPGA When the ext_io_dir pin is driven high the data is outputted from the FPGA and when the pin is driven low the data is inputted to the FPGA On power up all 12 I O lines are automatically configured as inputs The following table describes the J3 I O connect
14. GS D5 D8 FPGAs Gen 3 8 lane PCI Express host interface and stand alone option Four level memory structure 16 GB v Up to 2640 M20K 20K bit SRAM blocks 50 Mb 8 000 GB s typical throughput v Up to 17 960 Enhanced MLAB 640 bit SRAM blocks 8 Mb v 2 x DDR3 ECC SODIMMs Banks with up to a total of 16 GB ata sustain throughput of 19 2 GB s y Optional 2 x 144Mb or 2 x 36Mb DDRII SRAM memories up to 450Mhz Typical system frequency of 150 450MHz Up to 32 DMA channels Up to 3 926 of 18x18 bit multipliers implemented in Stratix V devices Optional 1 CXP connector cage suitable for 100 Gigabit Ethernet 100GBASE CR10 100GBASE SR10 3x40 Gigabit Ethernet or single Infiniband 12xQDR link Optional 2 SFP cage suitable for 10 Gigabit Ethernet and Optical Transport Network Optional RJ45 port suitable for 1000MBase T and 100MBase TX 2 High Speed Inter Board connectors up to 12x14 1 Gb s for board to board and Proc High Speed PHS daughterboards connectivity PHS daughterboards enabling additional protocol and connectivity options such as CoaXPress QSFP and SAS SATA 12 general purpose LVTTL External IOs Support for a single PSDB type 1 daughter board used for a GiDEL s off the shelf or user add on Interface including logic Analyzer mictors Camera Link SDI DVI and other interfaces Immediate and simple high bandwidth use of the on board memories with the innovative GIDEL ProcMultiPort configurable IP
15. Internal Bus 5 2 4 General purpose I O Bus 5 3 ProceV Clocking System 5 3 1 ProceV Global Clocks 5 3 2 ProceV Individual Clocks 5 3 3 ProceV High Speed Reference clocks 6 0 DMA Controller 6 1 DMA Performance 7 0 Connectors 7 1 Board Connectors Overview 7 2 CXP Connector J1 7 3 SFP Connectors J18 7 4 High Speed Inter Board Connectors J6 7 7 5 PSDB Connector J4 7 6 External I O Connector J3 7 7 RJ45 Connector J8 7 8 External Power 12V Connector J2 Preliminary ProceV Data Book Table of Contents 8 0 Memories 8 1 Two level structure Stratix V embedded memory 8 2 On board Memory Blocks DDRII SRAM optional 8 3 ECC DDR3 DRAM SODIMM Modules 72 bit wide 8 4 SODIMM Connectivity 8 5 SRAM Connectivity 9 0 LEDs 9 1 Power LEDs 9 2 Status LEDs 9 3 General Purpose User LEDs 9 4 SFP LEDs 10 0 Technical Specifications 10 1 Electrical and Mechanical Environment 10 1 1 Humidity 10 1 2 Temperature 10 2 MTBF 10 3 ProceV Mechanical Description 10 4 Power Consumption 10 5 ProceV Timing Model 10 5 1 Groups Skew 10 5 2 Clock Accuracy 10 5 3 System I O Frequency 11 0 Installation 11 1 Requirements 11 2 Installing the ProceV board 11 3 Loading Designs in PCI Express Mode 12 0 GiDEL Accessories 12 1 GiDEL Proc Developer s Kit 12 2 GiDEL ProcWizard 12 3 GiDEL ProcMultiPort 12 4 GiDEL ProcMegaDelay 12 5 GiDEL ProcMegaFIFO 12 6 GIDEL PSDB
16. L15 G N D L17 L53 GND L_lO3 vec L19 L55 vec L18 vcc L20 Vcc L104 L22 L21 le L23 Lt Reserved for GiDEL use must be disconnected on the user s PSDB GND pins must be connected to GND These are virtual signals The PSDB connectors have two power strips in the middle Signals 121 124 are connected to the top middle strip and signals 125 128 are connected to the bottom one The top strip must be connected to GND and the bottom strip to the PSDB 3 3V source Preliminary ProceV Data Book Connectors Table 13 PSDB_L J4 pin out in LVDS Mode Pin PSDB PSDB Signal Signal RXp0 TXp19 TXp0 RXn23 RXn0 CLK_RXp1 TXn19 DBO NC RXp24 RXp1 Reserved TXp20 TXn0 TXp11 RXn24 RXn1 CLK_RXn1 TXn20 TXp1 TXn11 RXp25 RXp2 RXp17 TXp21 TXn1 TXp13 RXn25 RXn2 RXn17 TXn21 TXp2 TXn13 RXp26 RXp3 RXp18 TXp22 TXn2 TXp14 RXn26 RXn3 RXn18 TXn22 TXp3 TXn14 RXp27 RXp4 RXp19 TXp23 TXn3 TXp15 RXn27 RXn4 RXn19 12V 0 3A TXp4 TXn15 NC RXp5 RXp20 TXn23 TXn4 TXp16 GND RXn5 RXn20 GND TXp5 TXn16 GND RXp6 RXp21 GND TXn5 TXp17 vcc RXn6 RXn21 vcc TXp6 CLK_RXp0 TXn17 VeEC RXp7 NCc RXp22 vcc TXn6 DB1 TXp18 RXn7 TXp12 RXn22 TXp7 CLK_RXn0 TXn18 RXp8 Reserved for GiDEL use must be disconnected on the user s PS
17. Preliminary Data Book January 2014 GiDEL products and their generated products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or other critical applications 1993 2014 by GiDEL Lid All rights reserved GiDEL ProceV PSDB ProcWizard ProcMultiPort and other product names are trademarks of GiDEL Ltd which may be registered in some jurisdictions This information is believed to be accurate and reliable but GiDEL LTD assumes no responsibility for any errors that may appear in this document GiDEL reserves the right to make changes in the product specifications without prior notice Windows Stratix V TMS320C6414 DDRII CameraLink and other brand and product names are trademarks or registered trademarks of their respective holders USA Worldwide 1600 Wyatt Drive Suite 1 2 Ha ilan Street P O Box 281 Santa Clara Or Akiva CA 95054 USA Israel 30600 Tel 1 408 969 0389 Fax 972 4610 2501 Fax 1 408 465 7361 Tel 972 4610 2500 sales usa GiDEL com sales eu GiDEL com Web www GiDEL com info GiDEL com Contents Contents Figures Tables 1 0 Scope 2 0 Introduction 3 0 Key Features 3 1 ProceV Performance 4 0 Standard Models 5 0 Architecture 5 1 ProceV Block Diagram 5 2 ProceV Signal Buses 5 2 1 PSDB Connector J4 Buses Single Ended Mode 5 2 2 PSDB Connector J4 Buses LVDS mode 5 2 3
18. ProcMultiPort controller DRAM access rate efficiency 75 gt Number of Bank B SODIMM modules 1 Throughput per SODIMM 1600 Mb sx8x0 75x1 9600 MB s Total Throughput Bank B C 9 6 GB s 9 6 GB s 19 2 GB s 13 1 5 Additional Devices Needed PSDB connector sockets QTH 060 XX F D A Samtec Where XX specifies the connector height as shown in Table 29 Table 29 PSDB Connector Heights Height 5 00 198 8 00 316 11 00 434 14 00 552 16 00 630 19 00 748 22 00 25 00 30 00 22 00 866 25 00 984 30 00 1 181 The GiDEL default standard PSDB connector size is 0 434 11 0mm Preliminary ProceV Data Book 14 0 References 14 1 References Stratix V Device Handbook Altera Corporation ProcWizard User s Manual ProcMultiPort IP User Guide Proc Internal Bus Data Book PSDB1 Reference Guide PCle Gen 3 Specifications CXP Specifications SFP Specifications Marvel s 88E1118R Data Sheet Micron MT18KSF1G72HZ 1G6 8GB ECC DDR3 SODIMM Data Sheet Apacer 78 C2GCT ATO0C 8GB ECC DDR3 SODIMM Data Sheet Micron MT18KSF51272HZ 1G4 4GB ECC DDR3 SODIMM Data Sheet Apacer 78 B2GCS AT00C 8GB ECC DDR3 SODIMM Data Sheet Cypress CY7C1650KV18 450BZC 144Mb DDRIIl SRAM Data Sheet Cypress CY7C1250KV18 450BZXC 3Mb DDRII SRAM Data Sheet SAMTEC HQDP High Speed Cable Data Sheet Preliminary ProceV Data Book Table 30 Table of Acronyms ACRONYMS 15 0 Glossary DESCRIPTION ASIC DDR DRAM
19. Status2 Indicates that the board has established link with the PCI Express slot Note The status LEDs name at the FPGA top level is status_ledn Preliminary ProceV Data Book 9 3 General Purpose User LEDs ProceV boards contain four general purpose user LEDs connected to the Stratix V FPGA The user LEDs name at the top level is ledn 3 0 accordingly The LEDs are active low Asserting a logical 0 to a LED signal will illuminate it 9 4 SFP LEDs ProceV boards contain four SFP LEDs located in CS Component Side close to the SFP connector these LEDs may be used for SFP trafix information or as User defined Preliminary ProceV Data Book eP Hm 10 0 Technical Specifications 10 1 Electrical and Mechanical Environment 10 1 1 Humidity The ProcevV is operational under the following conditions Humidity 10 90 non condensing 10 1 2 Temperature ProceV board is equipped with an on board temperature controller The maximal operating temperature of the on board STRATIX V FPGA is 85 C If an FPGA exceeds this temperature the user logic will be reset At 70 C an interrupt will be issued indicating that the temperature is approaching critical level The ProceV operating limits depend on the IC type the computer ambient temperature and the computer air flow as detailed in the following table Table 23 ProceV Operating Conditions Max Power Min consumption Computer Computer per IC W Ambient Air F
20. age and on the system frequency For precise power consumption information refer to Quartus power analyzer report 2 The VCCINT is limited to 16A for the ProceV models of Altera s Startix V GX A3 FPGA with Speed Rates of 3 and 4 3 The 3 3V is the total current available for the following modules SFP A and B CXP External_lO J3 PSDB J4 4 The VCCMEM1 is the current that can be supplied to both SRAMs and the FPGA s 1 8V VCCIO The current values depend on the SRAM capacity and the frequency rate For more information on the SRAM refer to their manufacturer s data sheet 5 The VCCMEM2 current Max current supplied to both of the SODIMMs the FPGA s 1 35V VCCIO The current values depend on the SODIMM capacity and the sustain rate For more information on the SODIMM refer to their manufacturer s data sheet Preliminary ProceV Data Book Technical Specifications 6 The VCCIO supplies power to the PSDB IOs The power consumption is dependent on I O frequency and toggle rate For precise power consumption information refer to Quartus power analyzer report Total power consumption of ProceV can be calculated according to the following formulas Prota 4 0W Pwodues 1 1 Prpaa Pmemories Pepea FPGA power dissipation Pmodules 1 1 2 3 3V power modules and external dependencies 2 12V power modules and external dependencies Pmemories SUM Of SODIMM 1 35V and SRAM power dissipation Note Prota
21. and system resources User s hardware design may control the data flow on DMA channels For this purpose the customer should use the user_dreq bus Each bit within the bus corresponds to a specific DMA channel for example user_dreq 3 corresponds to DMA channel 3 After the software has initialized a DMA channel the DMA controller starts transferring data Data continues to be transferred as long as the user_dreq signal remains low for that channel When the user_dreq signal rises the DMA controller holds the transfer This may take up to 10 local clocks Data transfer resumes upon asserting user_dreq signal low 1 It is not mandatory to control user_dreq signals If user_dreq signals are not connected once the DMA channel has been initialized by the software it will operate continuously until all data has been transferred 2 The DMA controller may stop and resume the DMA transfer based on the PCle bus internal bus and system activities Preliminary ProceV Data Book DMA Controller 6 1 DMA Performance The DMA performance depends on v Block size v Active PCI Express payload v Host mother board and chipset Table 3 and Table 4 detail the Benchmark system and the DMA performance respectively Table 3 DMA Performance Benchmark System Table 4 DMA Performance Test Results Board to PC TBD speed PC to board TBD speed Preliminary ProceV Data Book 7 0 Connectors The following chapter details the P
22. cWizard User s Manual NOTE Please contact GiDEL for availability of the noted automatic FPGA configuration loading and partial reconfiguration via PCle Alternatively you may upload the code via the JTAG connector or store the design in the EPC device For users that do not use the Proc Developer s kit they may use any other Altera options Preliminary ProceV Data Book 12 0 GIiDEL Accessories 12 1 GIDEL Proc Developer s Kit GiDEL Proc Developer s Kit for ASIC SoC IP amp System Development is a set of building blocks designed for fast high productivity system development It is a complete system solution including boards software tools IPs and optional daughterboards The main software tools and IPs are detailed in the following paragraphs 12 2 GiDEL ProcWizard GiDEL ProcWizard is an innovative tool providing a convenient developer environment that automatically generates the hardware software interface for project level user applications It has been developed for high system performance The ProcWizard automatically interfaces between the SW and the HDL applications running on the ProceV system It generates an application driver a C class for each application configuration The application driver can be generated for Windows environment The driver is built in two layers a Lower Layer and an Upper Layer The Lower Layer the Proc class supplied with the ProcWizard implements basic board functionality
23. cWizard generates the top level design and entity module interconnectivity in Verilog VHDL or AHDL format including all the ProceV buses as is described in the following sections The buses are assigned names accordingly However the generated names may change if a PSDB daughterboard is added to the ProceV board In such a case buses that are connected to that PSDB will be named according to the corresponding buses on the PSDB The single ended buses on ProceV boards are designed to provide maximum connectivity flexibility However user must take care to avoid bus contention Always use one source at a time for a single signal To improve EMC characteristics it is recommended to drive all unused connectivity pins to 0 from one source The PSDB connector J4 can operate in two unique modes single ended mode and differential LVDS mode The following sections detailed the connectivity buses of each of the noted modes 5 2 1 PSDB Connector J4 Buses Single Ended Mode The PSDB connector J4 in single ended mode includes the L 84 0 L_IN 7 0 L_IO 19 0 and clk_out 1 0 buses as follows PSDB IN buses I_in _in for backward compatibility is used as dedicated 8 bit input from PSDB to the STRATIX V FPGA If needed L_IN signals may also operate as outputs Note The L_IN bus connects the FPGA to the PSDB connector J4 as shown in Figure 1 PSDB I O buses I_ io _io is a 20 bit bidirectional I O bus connect
24. connected directly to the Stratix V device The SRAM maximum working frequency is up to 450 Mhz Preliminary ProceV Data Book Memories 8 3 ECC DDR3 DRAM SODIMM Modules 72 bit wide For additional memory Stratix V device is supported by two DDR3 Modules slots 204 Pin un buffered SODIMM with ECC Each DDR3 slot has a maximum capacity of 8GB The two SODIMM memory modules are designated Block B and Block C respectively The GiDEL ProcMultiPort controller can be used with the SODIMM modules to enable new design methodologies by replacing large and complicated designs and reducing development time For further information refer to the ProcMultiPort Data Book Altera or any other DRAM controller may also be used Preliminary ProceV Data Book Memories 8 4 SODIMM Connectivity The following table shows the SODIMM memory modules top level connectivity Table 19 SODIMM Top Level Signals Bank B Bank C Equivalent I O Description Top Level Top Level SODIMM Directions Signals Signals Signal Name addr_b 0 15 addr_c 0 15 A 0 15 Address Outputs dq_b 0 63 dq_c 0 63 DQ 0 63 1 0 Data input output bidirectional data bus cb_b 0 7 cb_c 0 7 CB 0 7 1 0 Check bits used for system error detection and correction dqm_b 0 8 dqm_c 0 8 DM 0 8 Output Data mask x8 devices only DM is an Output mask signal for the SODIMM to write data dqs_b 0 8 dqs_c 0 8 DQS 0 8 I O 1 0 Data strobe differential data
25. frames or to write video stream as it arrives and read it frame by frame for further processing For more information please refer to the ProcMegaDelay IP User s Guide 12 5 GiIDEL ProcMegaFIFO ProcMegaFIFO is a GiDEL IP that provides a simple and convenient way to transfer data to from GiDEL Proc boards With ProcMegaFIFO using the on board memory as a very large FIFO data may be transferred between the host PC and user s sub designs or between sub designs ProcMegaFIFO eliminates the need to take care of synchronization when transferring data between designs The software no longer needs to respond to the hardware in real time Hardware designs may now transfer data in bursts and withdraw it in a continuous stream ProcMegaFIFO uses special arbitration techniques when transferring data between the host PC and user s sub designs These techniques prevent memory overflows underuse thus using the maximum available bandwidth for data transfers Request and Acknowledge signals ensure correct data transfers On the software side the Proc class methods perform automatic initialization of the FIFO logic and enable easy data transfers by using DMA For more information please refer to the ProcMegaFIFO IP User s Guide Preliminary ProceV Data Book GiDEL Accessories 12 6 GIDEL PSDB Daughterboards GiDEL provides a diverse line of off the shelf daughterboards referred to as PSDBs that mount directly onto the ProceV board
26. gram The ProceV system Block Diagram is shown in Figure 1 115 fast single ended lines or 24 Tx 28 Rx 2 clk LVDS lines Figure 1 ProceV System Block Diagram Preliminary ProceV Data Book Board Architecture The ProceV system includes the following components One ALTERA Stratix V GX or GS FPGA in 1517 package 8 lane PCI Express Gen 3 interface Optional 2 x 144 Mb or 2x36 Mb DDRII SRAM 450MHz on board memories optional 2 x 8 GB DDR3 SODIMM sockets Optional 1 CXP connector cage suitable for 100 Gigabit Ethernet 100GBASE CR10 100GBASE SR10 3x40 Gigabit Ethernet or single Infiniband 12xQDR link up to 12x14 1 Gb s supports splitter cable 1 to 12 Optional 2 x SFP cage suitable for Fiber Channel Gigabit Ethernet and Optical Transport Network up to 14 1 Gb s SFP Optional RJ45 port suitable for 1000MBase T and 100MBase TX 2x High Speed connectors up to 12x14 1 Gb s for inter board and proprietary daughterboards connectivity 12 general purpose LVTTL External lOs External clock input via an SMA connector 1 PSDB Type 1 Proc Daughterboard connector with 115 I Os or 24 LVDS TX 28 LVDS RX and 2 LVDS clock inputs channels JTAG connection for the STRATIX V FPGA Stand alone capability Preliminary ProceV Data Book Board Architecture 5 2 ProceV Signal Buses The ProceV connectivity is automatically generated by the ProcWizard software included in Proc Developer s Kit The Pro
27. ing the STRATIX V FPGA device to its PSDB Preliminary ProceV Data Book Board Architecture PSDB I O buses l lis an 85 bit bidirectional I O bus connecting the STRATIX V FPGA device to its PSDB The I 35 and I 38 lines are connected to optional global clock input pins of the Stratix V device They may be used as bus clock signals or clock inputs For information on J4 pin out refer to section 7 2 5 2 2 PSDB Connector J4 Buses LVDS mode The PSDB connector J4 in LVDS mode includes 24 differential transmit lines tx 23 0 28 differential receive lines rx 27 0 and 2 differential receive reference clocks clk_rx 1 0 as detailed in section 7 2 Preliminary ProceV Data Book Board Architecture 5 2 3 Internal Bus GiDEL ProcWizard generates an Avalon bus and a simple logic bus that delivers direct access to internal memory mapped I Os and a simple interface to the internal memories The simple bus generated by the ProcWizard is called the Internal bus For further information please refer to the Proc Internal Bus Data Book 5 2 4 General purpose I O Bus The ProceV provides 12 bidirectional buffered LVTTL general purpose IO lines via the J3 connector The J3 connectivity is divided into two IO data groups IO 7 0 and IO 11 8 The j3_ext_io_dirO and j3_ext_io_dir1 signals define the data transmission direction for lO 7 0 and lO 11 8 respectively direction is relative to the STRATIX V FPGA When
28. j3_ext_io_dir 1 0 is driven high the data is outputted from the FPGA and when the pin is driven low the data is inputted to the FPGA On power up all 12 I O lines are automatically configured as inputs Some of the I Os are connected to pull up and pull down resistors ensuring a stable default high or low at power up These signals may be connected via optocoupler differential buffer or other type of buffers on a dedicated interface board 5 3 ProceV Clocking System GiDEL ProceV boards have a flexible clocking system The clocks in ProceV boards are routed as shown in the following diagram Stratix V Board Controller GCK_LO 125MHz K_R1 322MHz GCK_L1 322M Figure 2 ProceV Clock System Preliminary ProceV Data Book Board Architecture 5 3 1 ProceV Global Clocks ref_clk is a 25Mhz oscillator input that is used to generate internal clocks The clkO clk and clk2 frequencies can be set via the ProcWizard development software clkO The clkO is used for backward design compatibility It is the main system clock that drives the Stratix V FPGA Within the FPGA device individual clocks for internal logic can be derived from this clock clk clk is used as main logic clock and it is equal to c kO x 2or clkO x 3 Icik Iclk is the Local bus clock that drives the Stratix V FPGA local bus related logic Iclk frequency is up to 250 MHz clk2 clk2 is an auxiliary clock that may be
29. k Connectors 7 8 External Power 12V Connector J2 The External Power connector J2 is 75W in accordance to the PCI Express REV 3 0 ver 0 9 2 x 3 Auxiliary Power Specification The J2 connector is specifically used for connecting the ProceV to a 25W slot or when operating in stand alone mode Table 17 Power Connector Pin Map cable side Table 18 Power Connector J2 Pin out aster a 2 fiw Spay 4 eno 5 GND Sense0 e enD Preliminary ProceV Data Book 8 0 Memories The ProceV system memory has a four level structure as follows Two level structure of Stratix V embedded memories with ultra high bandwidth 1 MLAB Memory Logic Array Blocks 640 bit Memories 2 M20K Blocks 52 Mb Memories Additional two level structure of peripheral on board memory blocks 3 SRAM optional 2 x 144 36 Mb 36 bit wide 4 DDR3 DRAM SODIMM 2x8GB 72 bit wide 8 1 Two level structure Stratix V embedded memory The Stratix V embedded memory includes two different sizes of embedded memory Each embedded memory block can be configured depth x width via the Quartus software to be a single port RAM dual port RAM ROM or shift register For further information on the Stratix V embedded memories refer to Stratix V Device Handbook Altera Corporation 8 2 On board Memory Blocks DDRII SRAM optional The GiDEL ProceV board has up to two 144 Mb or 36Mb DDRII SRAM 36 bits wide devices Block D and E
30. lications including SDI DVI and Camera Link standards ProceV supports new simple SerDes based fast connections between boards and accessories of up to 169 Gb s full duplex The ProceV system is suitable for the following applications v High speed low latency networking and network analysis v Trading v Life science Applications v ASIC and SoC Prototyping v DSP Digital Signal Processing and HPRC High Performance Reconfigurable Computing Surveillance Machine Vision and Imaging v High performance acquisition systems Preliminary ProceV Data Book Introduction The ProceV all inclusive system composed of on board controllers and automatic code generation application software eliminates the need to vy Write a PCI Express driver v Write an application driver layer v Define board constraints Design memory controller v Write environment FPGA code With the ProceV system and supporting development tools designers can focus on their proprietary value added design instead of spending valuable time recreating standard design components GiDEL s soft IPs and automatic HDL code generation enable high speed and easy to use parallel access to large memories User designs may be in HDL C based Simulink graphical design or any combination of them For information on other design entry tools please contact GiDEL Preliminary ProceV Data Book 3 0 Key Features Support Altera Stratix V GX A3 A7 AB and
31. low Temp C 10 2 MTBF The Mean Time Between Failures MTBF for the ProceV board is 700 000 Hours Note For Models with a limited VCCINT of up to 16A the MTBF is 900 000 Hours Preliminary ProceV Data Book Technical Specifications 10 3 ProceV Mechanical Description ProceV mechanical dimensions shown in Figure 5 comply with the PCI Express standard half length form factor 165 354 157 734 164 338 Figure 5 ProceV Mechanical Dimensions in mm For ProceV daughterboard PSDB mechanical dimensions please refer to the specific PSDB s Data Book Note The blue circles in the figure indicate mounting location for stand alone Preliminary ProceV Data Book Technical Specifications 10 4 Power Consumption ProcevV is powered by 12V supplied either by the PCI Express slot by an external power supply or both The maximum allowable current is summarized in the following table Table 24 Maximum current Limits External amp PCle Slot The following table summarizes the ProceV internal voltage sources available for user controlled resources Table 25 ProceV Internal Voltage Sources Max Allowable Current VCCINT 0 9V Stratix V core voltage A Voltage Description Modules and cable 5 AA connected peripherals power supply DDRIII SODIMM 5 PSDB VCCIO 2 5V 2 PSDB I O power supply 1 The VCCINT current consumption depends on the FPGA logic us
32. or pin out Pe Sere Sina Name Resistance 0e Signal Name Resistance a vec Na NIA foo ee opurp froe oe eeo 10K purrdown voes o eeo 10K purup voes o eeo 10K putrup VOBus e on eoc 10K purdown 1OBus Table 14 J3 General Purpose IO Connector Assignments Default input resistance at power up and when the rbf is not loaded The J3 connector maximum IO working frequencies are as follows Table 15 IO Working Frequency Cable Length Maximum Frequency 0 5 meter 40 Mb s 6 0 meters 5 Mb s Preliminary ProceV Data Book Connectors 7 7 RRJ45 Connector J8 The ProceV has a single RJ45 port suitable for 1000MBase T and 100MBase TX The RJ45 is connected to the FPGA via Marvel s 88E1118R Alaska Gigabit Ethernet Transceiver Top Level FPGA I O Description Signals Direction Hardware Reset 0 Reset 1 Normal phy_mdio Open Management Data with an on board collector I O pull up Resistor phy_md Output Management Clock data Reference for the serial Management Interface phy_rx_clk Input RGMII Receive Clock provides a 125Mhz 25 Mhz or 2 5 Mhz reference clock derived from the received data stream phy_rx_ctrl RGMII Receive Control phy_rxd 3 0 RGMII Receive Data phy_tx_ctrl RGMII Transmit Control phy_tx_clk Output RGMII Transmit Clock provides a 125Mhz 25 Mhz or 2 5 Mhz reference clock phy_txd 3 0 RGMII Transmit Data Table 16 88E1118R PHY Top Level Signals Preliminary ProceV Data Boo
33. ormation please refer to the ProcWizard User s Manual 12 3 GiDEL ProcMultiPort ProcMultiPort is a GiDEL IP that provides an advanced controller for on board memories This controller has up to 16 ports each port featuring a simple FIFO or random access All ports are connected to the same memory domain and can be accessed independently or simultaneously with individual clock domains and data widths ProcMultiPort segmented mode provides the ability to logically enlarge the FPGA memory size The innovative ProcMultiPort concept enables new design methodologies that can replace many large and complicated designs thus reducing the development effort For example it can replace swappable double buffers or implement multiple logical memories in the same physical memory For more information please refer to the ProcMultiPort IP User s Guide Preliminary ProceV Data Book GiDEL Accessories 12 4 GiDEL ProcMegaDelay ProcMegaDelay is a GiDEL IP that provides a simple and convenient way to create large delay lines frame delays ProcMegaDelay eliminates the need to use standard delay lines utilizing internal FPGA memories Instead it uses the on board memory thus enabling generation of very large delay lines ProcMegaDelay is typically used for 2D 3D video processing where very large quantities of data must be stored in memory and extracted later ProcMegaDelay makes it possible to compare two not necessary consecutive video
34. ower Connector J2 Pin out Table 19 SODIMM Top Level Signals Table 20 SRAM Top Level Signals Table 21 Power LEDs Table 22 Status LEDs Table 23 ProceV Operating Conditions Table 24 Maximum current Limits Table 25 ProceV Internal Voltage Sources Table 26 Groups Skew Table 27 Clock Accuracy Table 28 System I O Frequency Table 29 PSDB Connector Heights i e iozcecceeleca ics ccdeeandeeteeeene ant icda sehen ede ees eed eacetea nance 51 Table 30 Table of Acronyms Table 31 PCB History Table 32 Firmware History Table 33 Data Book History Preliminary ProceV Data Book 1 0 Scope The purpose of this data book is to provide architectural hardware and installation information for the ProceV system This data book is organized in the following chapters Introduction Board description and purpose Key Features Main features and performance Standard Models Standard product models available Architecture Board architecture components busses and clocks DMA Controller DMA operation and performance Connectors Board connectors description and pin out Memories Memory structure LEDs LEDs functions Technical Specifications Electrical mechanical and other technical specifications Installation Requirements and installation instructions GIDEL Accessories GiDEL management software and IPs Appendix Additional information References List of referenced documen
35. perature sensor SPD EEPROM on the I2CC bus s S Output Serial clock for temperature sensor SPD EEPROM Preliminary ProceV Data Book Memories 8 5 SRAM Connectivity The ProceV has an optional dual DDR Il synchronous SRAM memory modules referred to as Bank D and Bank E There are two SRAM device options 1 SRAM 144 Mb Cypress CY7C1650KV18 2 SRAM 36 Mb Cypress CY7C1250KV18 450BZXC The following table shows the 144 Mb SRAM memory modules top level connectivity Table 20 SRAM Top Level Signals Bank D U13 Bank E U14 FPGA I O Description Top Level Top Level Direction Signals Signals addr_d 21 1 addr_e 21 1 Address 1 dq_d 35 0 dq_e 35 0 DQ Data input output cq_d cq_e Differential Synchronous echo clock Input outputs cqn_d cqn_e Differential Synchronous echo clock Input outputs this signal is coupled with its differential pair cq_d e r_wn_d r wne Output When LDn low 1 Read operation 0 Write operation kd ke Differential Positive clock Output Output kn_d kn_e Differential Negative clock Output This Output signal is coupled with its differential pair k_ bwsn_ 3 0 bwsn_e 3 0 Output Byte write select BWS Active low Used to select which byte is written into the device 2 Synchronous load A d LE e Input Valid Input indicator The Q Valid indicates valid Input data QVLD is edge aligned with CQ and CQn 1 The Address is in 72 bit wide data One address per DDR data Fo
36. r lower cost SRAM the address lines are reduced Preliminary ProceV Data Book Memories In some SRAMs AO may be added to have address at 36 bit resolution 2 BWS 0 controls D 8 0 BWS 1controls D 17 9 BWS 2 controls D 26 18 and BWS 3 controls D 35 27 For further information regarding the 144Mb SRAM refer to the Cypress SRAM CY7C1650KV18 datasheet doc 001 44061 For further information regarding the 36Mb SRAM refer to the Cypress SRAM CY7C1250KV18 450BZXC datasheet doc 001 57834 Note Outputs are Synchronous to K clock Inputs are Synchronous to CQ echo clock Preliminary ProceV Data Book 9 0 LEDs All of the ProceV LEDs accept SFP LEDs are located on the top of the PS Print Side of the board 9 1 Power LEDs The ProceV board has four power LEDs as follows Table 21 Power LEDs ee 12 V when LED illuminates it indicates there is power Vccint 0 9 or 0 85 V when LED illuminates it indicates a power failure 2 5V 2 5 V when LED illuminates it indicates that there is power 3V 3 0 V when LED illuminates it indicates that there is power 9 2 Status LEDs The ProceV board has three Status LEDs as follows Table 22 Status LEDs LED Function Name StatusO Temperature indicator Blinking LED indicates that temperature is approaching to critical level Constant illuminated LED indicates overheating Status 1 Blinking to indicate that card is operational
37. roceV connectors functionality and pin out 7 1 Board Connectors Overview Figure 3 Components Side CS Connectors Connector Function _ _ _ _ CXP optional J8 RJ45 1000MBase T and 100MBase TX optional DDR3 SODIMM Bank B JTAG SMA for external clock optional J18 A and B 2 x SFP optional Table 5 Component Side Connector Description Preliminary ProceV Data Book Connectors E PROCe VA3 B iT X En C AS J12 Figure 4 Print Side PS Connectors Table 6 Print Side Connector Description DDR3 SODIMM Bank C Preliminary ProceV Data Book Daughterboard PSDB To connect via the PC s panel you must use PSDB _6C cable kit Connectors 7 2 CXP Connector J1 The ProceV board has a single CXP connector cage enabling up to 12 full duplex transceivers at 600 Mb s 12 5 14 1 Gb s suitable for 100 Gigabit Ethernet 100GBASE CR10 100GBASE SR10 3x40 Gigabit Ethernet 12x 10Gigabit Ethernet or a single 120Gb s Infiniband 12xQDR link The CXP connector interfaces with the FPGA via the following top level signals FPGA Equivalent CXP FPGA I O Description Top Level Protocol Name Direction Signal cxp_rx 11 0 Rx 11 0 p n FPGA SerDes data inputs Differential FPGA SerDes data outputs this cxp_tx 1 1 0 Tx 11 0 p n Output signals are coupled with their p differential pair cxp_txn 0 11 1 CXP module is absent l PRSNT_L Input Open collector bi directional signal
38. ts Glossary Term definitions and acronyms Revision History Board and document revision history Preliminary ProceV Data Book 2 0 Introduction The ProceV system provides a high capacity high speed FPGA based platform along with 16 GB of memory with 20GB s sustain access rate The combination of high speed direct communication to the FPGA via PCle gen 3 CXP SFP RJ45 and General Purpose physical layer interface makes the ProceV ideal for HPC High Performance Computing and high performance low latency networking applications The ProceV architecture based on Altera s Stratix V FPGA technology is capable of running at typical system speeds of 150 450 MHz The ProceV is 8 lane PCI Express hosted offering both high performance and flexible architecture based on massive memory and diverse add on daughterboards for large application needs In addition to two SODIMM sockets 1 6Gb s each providing up to 16 GB of ECC DDR3 memory the ProceV provides an option for 2x144 Mb or 2x36 Mb on board DDRII SRAM memory This vast memory conjoined with PCle connection permits strong co processing between a PC with standard OS and the FPGA accelerator The ProceV system supported by GiDEL s ProcDeveloper s Kit management software and soft IPs offers an incredible improvement in time to market In addition the ProceV is enhanced by GiDEL s line of PSDB daughterboards enabling interfacing with external I O lines and video app
39. ust use the following SAMTEC cable or an equivalent cable HQDP 020 KX XX TBR TTL 2 B where XX XX specifies the length in inches This cable crosses left side pins with right side pins e g pin1 with pin2 Note The 12V supplies up to 0 5A per connector Preliminary ProceV Data Book Connectors Table 11 HS Connectors Top Level Signals HS B Signals HS C Signals HS FPGA I O Description J6 J7 Connector Direction Name hs_rx_b 7 0 hs_rx_c 3 0 hs_rxp n Input 8 4 Differential receivers hs_tx_b 7 0 hs_tx_c 3 0 hs_txp n Output 8 4 Differential transmitters hs_refck_c hs_refck n Input Differential reference clock hs_prsnt_b hs_prsnt_c hs_present Input 1 the connector is not used 0 Other board daughterboard is connected single ended daisy HS_C gt FPGA All receive and transmit lines are directly connected to the Stratix V transceiver with a throughput rate of 600 Mb s 12 5 14 1 Gb s If one of the HS_B C is not connected the connection will be by passed on the board The daisy chain protocol may be user defined or TBD Preliminary ProceV Data Book Connectors 7 5 PSDB Connector J4 The ProceV board supports a single PSDB type 1 daughterboards The PSDBs enable I O connectivity to the FPGA in such standards as Camera Link SDI HDMI etc All the PSDBs are automatically identified by the ProcWizard For further information on PSDB type 1 refer to PSDB1 Reference Guide
40. with a throughput of up to 14 1 Gb s Connector HS B has up to 8 full duplex lanes and connector HS C has up to 4 full duplex lanes Each of the transmit lines is connected to a 100 nF serial capacitor The following tables list the HS connectors pin out Table 9 HS B Connector J6 Pin out PM asennon esenpuon Description Description 1 hs_rxp0 2 hs_txp0 5 nsp 6 nso 7 n 8 stent 9 thse 10 hs pe M hson 12 nsina 13 ns rpa 4 hs tps 15 hss 16 hss 17 nspa 18 hs pa 19 hsna 20 nsina 21 ns p5 22 hs tps hs_rxn5 24 hs_txn5 25 ns pe 26 hs tps 27 nsns 28 nse hs p7 30 hs t7 hs_rxn7 32 hs_txn7 33tiav Ja ev 35 rssch f hssdo 37 hs preset 38 ann 39 nss 4 hsso Preliminary ProceV Data Book Connectors Table 10 HS C Connector J7 Pin out Desernton pesenna Description Description 1 hs_rxp0 2 hs_txp0 5 hsp 6 hsp 7 hem 8 hs tent hs mp2 10 hs w2 RL j nsmn 12 nsin oe 14 hns ip3 L 5 nsmns 16 nsis 17 hs rep 18 ann 19 ns retn 20 Gnd 21 Reserved 22 Reserved 23 Reseved 24 Reserved Reserved 26 Reserved 27 Reserved 28 Reserved Reserved 30 Reserved 31 Reserved 32 Reserved piv a tv 35 hs sai 36 hs 37 hs present 38_ ano 39 hs sci a0 hs hs_sci Ss sco To interconnect between two HS connectors you m
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