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LPC82x - NXP Semiconductors

1. Symbol Parameter Conditions Min Typ Max Unit Static characteristics Vref cmp comparator reference pin PIOO_6 VDDCMP configured for 15 l 3 6 V voltage function VDDCMP Ipp supply current VP gt VM Tamb 25 C Vpp 33V B 90 pA VM gt VP Tamb 25 C Vpp 3 3V B 60 uA Vic common mode input voltage 0 Vpp V DVo output voltage variation 0 Vpp V Vot set offset voltage Vic 0 1 V Vpp 2 4 V Tamb 105 C 2 4 mV Vic 1 5 V Vpp 2 4 V Tamb 105 C 2 2 mV Vic 2 9 V Vpp 2 4 V Tamb 105 C 2 4 mV Dynamic characteristics tstartup start up time nominal process Vpp 3 3 V Tamb 13 us 25 C LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 64 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 24 Comparator characteristics continued Tamb 40 C to 105 C unless noted otherwise Vpp 1 8 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit tpp propagation delay HIGH to LOW Vpp 3 0 V Tamb 105 C Vic 0 1 V 100 mV overdrive input L II2II4 140 ns Vic 0 1 V rail to rail input pua 190 ns Vic 1 5 V 100 mV overdr
2. pin 1 index CY 4 L detail X DIMENSIONS mm are the original dimensions UNIT Ai A2 A3 bp c D EO 0 15 0 95 030 02 66 45 mm f ii oos oso 079 19 01 64 43 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT360 1 MO 153 Et Q dicke Fig 43 Package outline SOT360 1 TSSOP20 ISSUE DATE LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 72 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller HVQFN33 plastic thermal enhanced very thin quad flat package no leads 32 terminals body 5 x 5 x 0 85 mm terminal 1 index area A A1 pe detail X C ei v MCAB Y1 C gt hy wc 17 v EE cr e A
3. 20 40 60 80 loH mA LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 47 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller aaa 013964 40 loL mA 0 0 1 0 2 0 3 0 4 0 6 0 5 VoL V Conditions Vpp 1 8 V on pins PIOO 10 and PIOO 11 60 aaa 013972 loL mA 40 C 45 Me 25 C 90 S 105 C 30 15 0 0 0 1 0 2 0 3 0 4 0 5 0 6 VoL V Conditions Vpp 3 3 V on pins PIOO 10 and PIOO 11 Fig 26 I C bus pins high current sink Typical LOW level output current lo versus LOW level output voltage VoL 10 aaa 013975 15 aaa 013976 lot loL mA mA 5 40 C 12 40 C 25 C f po C 9 105 6 3 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 0 1 0 2 0 3 0 4 0 5 0 6 Vot V Vor V Conditions Vpp 1 8 V standard port pins and high drive pin PIOO 12 Conditions Vpp 3 3 V standard port pins and high drive pin PIOO 12 Fig 27 Typical LOW level output current Io versus LOW level output voltage Vo LPC82x All information provided in this document is subject to legal disclaimers NXP S
4. WKT running with external 32 kHz clock Clock input waveform square wave with rise time and fall time of 5 ns Deep power down mode Typical supply current lpp versus temperature for 20 80 temperature C different supply voltages Vpp external 32 kHz input clock 110 aaa 014389 25 IDD HA 20 Fig 22 15 3 3 V VDD 3 6 V 10 2M 1 8V petet WKT running with external 1 MHz clock Clock input waveform square wave with rise time and fall time of 5 ns Deep power down mode Typical supply current lpp versus temperature for 20 80 temperature C different supply voltages Vpp external 1 MHz input clock 110 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 44 of 81 NXP Semiconductors LPC82x LPC82x 11 5 CoreMark data 32 bit ARM Cortex M0 microcontroller 25 aaa 014006 coremark score iterations SA Mle CPU performance efficiency 2 1 5 default low current 1 0 5 0 Conditions Vpp 3 3 V Tamb 25 C active mode all peripherals except one UART and
5. 80 temperature C 110 Conditions Frequency values are typical values 12 MHz 1 5 accuracy is guaranteed for 2 7 V Vpp 3 6 V Variations between parts may cause the IRC to fall outside the 12 MHz 1 5 accuracy specification for voltages below 2 7 V Fig 32 Typical Internal RC oscillator frequency versus temperature Table 14 Dynamic characteristics Watchdog oscillator Symbol Parameter Conditions Min Typ Max Unit fosc nt internal oscillator DIVSEL Ox1F FREQSEL Ox1 IS 94 l kHz frequency in the WDTOSCCTRL register DIVSEL 0x00 FREQSEL OxF IIS 2300 kHz in the WDTOSCCTRL register 1 Typical ratings are not guaranteed The values listed are at nominal supply voltages 2 The typical frequency spread over processing and temperature Tamb 40 C to 105 C is 40 96 3 See the LPC82x user manual All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 52 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 12 3 1 I O pins Table 15 Dynamic characteristics I O pins Tamb 40 C to 105 C 3 0 V lt Vpp lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configur
6. Symbol Parameter Conditions Max min Unit HVQFN33 package Rih ra thermal resistance from JEDEC 4 5 in x 4 in still air 40 15 C W junction to ambient single layer 4 5 in x 3 in still 114 4 15 C W air Rth c thermal resistance from 18 4 15 C W junction to case LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 32 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 11 Static characteristics 11 1 General operating conditions Table 7 General operating conditions Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit folk clock frequency internal CPU system clock 30 MHz Vpp supply voltage core 1 8 3 3 3 6 V and external rail Vref reference voltage on pin VREFP 2 4 Vpp V Oscillator pins Vi xtal crystal input voltage on pin XTALIN 0 5 1 8 1 95 V Vo xtal crystal output voltage on pin XTALOUT 0 5 1 8 1 95 V Pin capacitance Cio input output pins with analog and digital 2 7 1 pF capacitance functions 1 C bus pins PIOO 10 and 2l 2 5 pF PIOO 11 pins with digital functions only 2 2 8 pF 1 Typical ratings are not guaranteed The values listed are for room temperature 25 C nominal supply voltages 2 Inc
7. NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 74 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of HVQFN33 package see detail X p DBRSSERS je O gt IL L J Lj Lu L l1 i D SLx zi E 0 60 solder land 0 30 Solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C nSPx nSPy 0 5 5 95 595 425 4 25 0 85 3 3 HH Issue date 11 11 20 002aag766 Fig 46 Reflow soldering of the HVQFN33 package 5x5 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 75 of 81 NXP Semiconductors LPC82x 17 Abbreviations 32 bit ARM Cortex M0 microcontroller Table 31 Abbreviations Acronym Description AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output PLL Phase Locked Loop RC Resistor Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver Transmitter 18 Refer
8. Product data sheet Rev 1 1 October 2014 20 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 8 17 Multi Rate Timer MRT The Multi Rate Timer MRT provides a repetitive interrupt timer with four channels Each channel can be programmed with an independent time interval and each channel operates independently from the other channels 8 17 1 Features 31 bit interrupt timer Four channels independently counting down from individually set values Bus stall repeat and one shot interrupt modes 8 18 Windowed WatchDog Timer WWDT The watchdog timer resets the controller if software fails to service the watchdog timer periodically within a programmable time window 8 18 1 Features Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect feed sequence causes reset or interrupt if enabled Flag to indicate watchdog reset Programmable 24 bit timer with internal prescaler e Selectable time period from Tcytwpcik x 256 x 4 to Tcy wpcik x 224 x 4 in multiples of Tcy wpctk x 4 The WatchDog Clock WDCLK is generated by th
9. Rev 1 1 October 2014 59 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 13 Characteristics of analog peripherals 13 1 BOD Table 21 BOD static characteristics Tamb 25 C Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 1 assertion 2 25 V de assertion 2 40 V interrupt level 2 assertion 2 54 V de assertion 2 68 V interrupt level 3 assertion 2 85 V de assertion 2 95 V reset level 0 assertion 1 46 V de assertion 1 61 V reset level 1 assertion 2 05 V de assertion 2 20 V reset level 2 assertion 2 34 V de assertion 2 49 V reset level 3 assertion 2 63 V de assertion 2 78 V 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see the LPC82x user manual Interrupt level 0 is reserved LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 60 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 13 2 ADC Table 22 12 bit ADC static characteristics Tamo 40 C to 105 C unless noted otherwise Vpp 2 4 V to 3 6 V VREFP Vpp VREFN Vss Symbol Parameter Condit
10. ACMP IS ADC 2 A ACMP I3 Analog comparator common input 3 A ADC 2 ADC input 2 PIOO 15 11 15 Bl PU IO PIOO 15 General purpose port 0 input output 15 PIOO 16 10 4 PU IO PIOO 16 General purpose port 0 input output 16 PIOO 17 ADC 9 2 32 B il PU IO PIOO 17 General purpose port 0 input output 17 A ADC 9 ADC input 9 PIOO 18 ADC 8 31 2 PU IO PIOO 18 General purpose port 0 input output 18 A ADC 8 ADC input 8 PIOO 19 ADC 7 30 2 il PU IO PIOO 19 General purpose port 0 input output 19 A ADC 7 ADC input 7 PIOO 20 ADC 6 29 B il PU IO PIO0_20 General purpose port 0 input output 20 A ADC_6 ADC input 6 PIOO 21 ADC 5 28 Bl PU IO PIOO 21 General purpose port 0 input output 21 A ADC 5 ADC input 5 PIOO 22 ADC 4 27 B il PU IO PIOO 22 General purpose port 0 input output 22 A ADC 4 ADC input 4 PIOO 23 ADC 3 1 26 B il PU IO PIO0_23 General purpose port 0 input output 23 ACMP l4 A ADC 3 ADC input 3 A ACMP 14 Analog comparator common input 4 PIOO 24 14 BI i PU IO PIOO 24 General purpose port 0 input output 24 PIOO 25 13 BI Ji PU IO PIOO 25 General purpose port 0 input output 25 PIOO 26 12 BI PU IO PIOO 26 General purpose port 0 input output 26 PIOO 27 11 BI i PU IO PIOO 27 General purpose port 0 input output 27 PIOO 28 5 BI l PU IO PIOO 28 General purpose port 0 input output 28 This pin can WKTCLKIN host an externa
11. C to 105 C Vpp over specified ranges Symbol Parameter Min TypEl Max Unit fosc oscillator frequency 1 25 MHz Toy cik clock cycle time 40 1000 ns tcHcx clock HIGH time Toyelk x 0 4 ns tcLox clock LOW time Tey cik x 0 4 ns tci cH clock rise time 5 ns tcucL clock fall time 5 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are for room temperature 25 C nominal supply voltages aaa 004648 Fig 31 External clock timing with an amplitude of at least Viigus 200 mV Internal oscillators Table 13 Dynamic characteristics IRC Tamb 40 C to 105 C 2 7 V lt Vpp lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit fosRc internal RC 11 82 12 12 18 MHz oscillator frequency 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are for room temperature 25 C nominal supply voltages All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 51 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller aaa 014008
12. F LPC82x Bus 32 bit ARM Cortex M0 microcontroller up to 32 kB flash and 8 kB SRAM 12 bit ADC comparator Rev 1 1 October 2014 Product data sheet 1 General description The LPC82x are an ARM Cortex M0 based low cost 32 bit MCU family operating at CPU frequencies of up to 30 MHz The LPC82x support up to 32 KB of flash memory and 8 KB of SRAM The peripheral complement of the LPC82x includes a CRC engine four IC bus interfaces up to three USARTS up to two SPI interfaces one multi rate timer self wake up timer and state configurable timer with PWM function SCTimer PWM a DMA one 12 bit ADC and one analog comparator function configurable I O ports through a switch matrix an input pattern match engine and up to 29 general purpose I O pins For additional documentation related to the LPC82x parts see Section 18 2 Features and benefits W System ARM Cortex MO processor revision r0p1 running at frequencies of up to 30 MHz with single cycle multiplier and fast single cycle I O port ARM Cortex M0 built in Nested Vectored Interrupt Controller NVIC System tick timer AHB multilayer matrix Serial Wire Debug SWD with four break points and two watch points JTAG boundary scan BSDL supported MTB E Memory Up to 32 KB on chip flash programming memory with 64 Byte page write and erase Code Read Protection CRP supported 8 KB SRAM B ROM
13. Rev 1 1 October 2014 36 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 9 Static characteristics electrical pin characteristics continued Tampo 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vi input voltage Vpp 2 1 8 V 0 5 0 V Vpp 20V 0 3 6 V Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 4 V Vou HIGH level output lou 20 mA 2 5 V lt Vpp lt 3 6 V Vpp 0 4 V voltage lou 12 mA 1 8 V lt Vpp lt 2 5 V Voo 0 4 V VoL LOW level output lol 4 mA 0 4 V voltage lou HIGH level output Vou Vpp 0 4 V 20 mA current 2 5 V lt Vpp lt 3 6 V Vou Vpp 0 4 V 12 mA 1 8 V lt Vpp lt 2 5 V lot LOW level output VoL 0 4 V 4 mA current 2 5 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 5 V 3 mA lois LOW level short circuit Voi Vpp 1 50 mA output current loa pull down current Vi 5V 8 10 50 150 uA lou pull up current Vi 0V 8 10 50 85 uA Vpp V lt 5V 0 0 0 uA I C bus pins PIOO 10 and PIOO 11 Vin HIGH level input 0 7Vpp V voltage Vit LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 05Vpp V lot LOW level output VoL 0 4 V 12C bus pins
14. 100 KQ PIOO 8 XTALIN alle C1 Note 1 DGND Le xe mc RESET PIOO_5 FIERI SOSIAEGUT T DGND DGND Note 2 Vpp 2 to 5 pins LPC82x I e 33V 0 1 pF 0 01 pF V AGND PIOO 12 DGND ISP select pin Note 5 ADC 1 Note 3 VDDCMP PIOO_6 ADC_1 VDDCMP Note 5 Note 3 I I 33V 0 1 uF 0 1 uF 10 pF AGND AGND YY DGND aaa 015073 1 See Section 14 1 XTAL input for the values of C1 and C2 2 Position the decoupling capacitors of 0 1 uF and 0 01 uF as close as possible to the Vpp pin Add one set of decoupling capacitors to each Vpp pin 3 Position the decoupling capacitors of 0 1 uF as close as possible to the VREFN and Vpp pins The 10 uF bypass capacitor filters the power line Tie VREFP to Vpp if the ADC is not used Tie VREFN to Vss if ADC is not used 4 Uses the ARM 10 pin interface for SWD 5 When measuring signals of low frequency use a low pass filter to remove noise and to improve ADC performance Also see Ref 4 Fig 42 Power clock and debug connections 14 4 Termination of unused pins Table 29 shows how to terminate pins that are not used in the application In many cases unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Pro
15. PLL disabled 24 MHz IRC enabled PLL enabled 30 MHz system oscillator enabled PLL enabled Fig 15 Sleep mode Typical supply current lpp versus temperature for different system clock frequencies aaa 013983 l 180 Vpp 3 6 V DD 3 3 V uA 27V 170 zy 18V 160 150 140 130 120 40 10 20 50 80 110 temperature C Conditions BOD disabled all oscillators and analog blocks disabled in the PDSLEEPCFG register PDSLEEPCFG 0x0000 18FF Fig 16 Deep sleep mode Typical supply current Ipp versus temperature for different supply voltages Vpp All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 41 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller 25 aaa 013984 IDD uA 20 15 10 40 Conditions BOD disabled all oscillators and analog blocks disabled in the PDSLEEPCFG register PDSLEEPCFG 0x0000 18FF Fig 17 Power down mode Typical supply current lpp versus temperature for different supply voltages Vpp 80 110 temperature C aaa 013985 Ipp HA WKT not running Fig 18 Deep power down mode Typical supply current lpp versus temperature for different sup
16. Product data sheet Rev 1 1 October 2014 80 of 81 NXP Semiconductors LPC82x 13 1 13 2 13 3 14 14 1 14 2 14 3 14 4 14 5 15 16 17 18 19 20 20 1 20 2 20 3 20 4 21 22 Comparator and internal voltage reference Application information XTAL Inp t Lis ee Oda XTAL Printed Circuit Board PCB layout guidelines 00 00 eee eee Connecting power clocks and debug TUNGUONS s 1 orien a eden ead deter Saee Termination of unused pins Pin states in different power modes Package outline 1 1 2 0c eee eee Soldering bei eed ue m Ete Roos Abbreviations lessen References 0 c eee eee eee Revision history 00 0 ee eee eens Legal information 00 0eeeeeee Data sheet status 00 Definitions i2 nen Re eRe EE Disclaimers 000200 cee eee eee Trademarks 00002 0c e eee eee Contact information Lus Contents tsm EIS eei dows ERE 60 61 64 32 bit ARM Cortex M0 microcontroller Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2014 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 1 October 2014 Docu
17. A o 2 PU IO PIO0_0 General purpose port 0 input output 0 In ISP mode this is the UO_RXD pin In boundary scan mode TDO Test Data Out A ACMP_l1 Analog comparator input 1 PIOO 1 ACMP I2 CLKIN TDI 12 16 Bl ii PU IO PIOO 1 General purpose port 0 input output 1 In boundary scan mode TDI Test Data In A ACMP 12 Analog comparator input 2 CLKIN External clock input SWDIO PIOO 2 TMS 8 7 A l PU IO SWDIO Serial Wire Debug I O SWDIO is enabled by default on this pin In boundary scan mode TMS Test Mode Select O PIOO 2 General purpose port 0 input output 2 SWCLK PIOO 3 TCK 7 6 A PU l SWCLK Serial Wire Clock SWCLK is enabled by default on this pin In boundary scan mode TCK Test Clock IO PIO0_3 General purpose port 0 input output 3 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 7 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol o o Reset Type Description N 6 ao z statel l Oo LL E e z PIOO_4 ADC_11 6 4 BI PU IO PIOO 4 General purpose port 0 input output 4 TRSTN WAKEUP In boundary scan mode TRST Test Rese
18. Eight states LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 19 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Four inputs Each input is configurable through an input multiplexer to use one of four external pins connected through the switch matrix or one of four internal sources The maximum input signal frequency is 25 MHz Six outputs Connected to pins through the switch matrix Counter timer features Each SCTimer is configurable as two 16 bit counters or one 32 bit counter Counters can be clocked by the system clock or selected input Configurable as up counters or up down counters Configurable number of match and capture registers Up to eight match and capture registers total Upon match create the following events interrupt stop limit halt the timer or change counting direction toggle outputs Counter value can be loaded into capture register triggered by a match or input output toggle PWM features Counters can be used with match registers to toggle outputs and create time proportioned PWM signals Upto six single edge or dual edge PWM outputs with independent duty cycle and common PWM cycle length Event creation features The following conditions define an event a counter match condition an
19. VREFP not to exceed Vpp voltage level Burst conversion mode for single or multiple inputs Hardware calibration mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 23 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 8 22 Clocking and power control SYSCON AHB clock 0 core system main clock CLOCK DIVIDER system clock always on SYSAHBCLKDIV memories and peripherals peripheral clocks SYSAHBCLKCTRL 1 29 system clock enable CLOCK DIVIDER FRACTIONAL RATE USARTO UARTCLKDIV GENERATOR USART1 gt USART2 watchdog oscillator MAINCLKSEL main clock select sci 7 CLOCK DIVIDER IOCON IOCONCLKDIV glitch filter IRC oscillator IRC oscillator un mU system oscillator eR CLKOUT pin inus OSCILLATOR SYSTEM PLL watchdog oscillator CLKIN CLKOUTSEL CLKOUT clock select SYSPLLCLKSEL system PLL clock select watchdog oscillator WWDT IRC oscillator WKT low power oscillator WKT aaa 012136 Fig 9 LPC82x clock generation 8 22 1 Crystal and internal oscillators The LPC82x include four independent oscillators 1 The crystal oscillator SysOsc operating at frequencies between 1 MHz and 25 MHz 2 The internal RC Oscillator IRC with a fixed frequency of 12 MHz 3 The internal low power low fr
20. current configured as standard mode pins 2 5 V lt Vpp lt 3 6 V 3 5 mA 1 8 V lt Vpp lt 2 5 V 3 mA loL LOW level output VoL 0 4 V I2C bus pins current configured as Fast mode Plus pins 2 5 V lt Vpp lt 3 6 V 20 mA 1 8 V lt Vpp lt 2 5 V 16 mA lu input leakage current Vi Vpp 9 2 4 uA Vi 5V 10 22 uA 1 Typical ratings are not guaranteed The values listed are for room temperature 25 C nominal supply voltages 2 Based on characterization Not tested in production 3 Low current mode PWR_LOW_CURRENT selected when running the set power routine in the power profiles 4 Including voltage on outputs in 3 state mode LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 37 of 81 NXP Semiconductors LPC82x 5 6 7 32 bit ARM Cortex M0 microcontroller Vpp supply voltage must be present 3 state outputs go into 3 state mode in Deep power down mode Allowed as long as the current limit does not exceed the maximum current allowed by the device 8 Pull up and pull down currents are measured across the weak internal pull up pull down resistors See Figure 12 9 To Vss VDD loL Ipd pin PIOO_n loH lou pin PIOO n aaa 010819 Fig 12 Pin input output current measurement LPC82x All information provided
21. disabled system PLL disabled 6 BOD disabled 7 All peripherals disabled in the SYSAHBCLKCTRL register Peripheral clocks to USART CLKOUT and IOCON disabled in system configuration block 8 IRC enabled system oscillator disabled system PLL enabled 9 IRC disabled system oscillator enabled system PLL enabled 10 All oscillators and analog blocks turned off 111 WAKEUP pin pulled HIGH externally LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 35 of 81 NXP Semiconductors LPC82x 11 3 Electrical pin characteristics 32 bit ARM Cortex M0 microcontroller Table 9 Static characteristics electrical pin characteristics Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit Standard port pins configured as digital pins RESET li LOW level input current V 0 V on chip pull up resistor 0 5 1012 nA disabled ly HIGH level input Vi Vpp on chip pull down resistor 0 5 10 21 nA current disabled loz OFF state output Vo 0 V Vo Vpp on chip 0 5 10 21 nA current pull up down resistors disabled Vi input voltage Vpp 1 8 V 5 V tolerant pins 4 i0 5 V except PIOO 12 6 Vpps0V 0 3 6 V Vo output voltage output active 0 Vpp V Vin HIGH
22. driven LOW and configured as GPIO output by software VREFP Tie to VDD VREFN Tie to VSS 1 l Input O Output IA Inactive no pull up pull down enabled F floating PU Pull Up 14 5 Pin states in different power modes Table 30 Pin states in different power modes Pin Active Sleep Deep sleep Power Deep power down down PlOn m pins not As configured in the IOCONCJ Default internal pull up Floating 12C enabled PIOO 4 PIOO_5 As configured in the IOCONUI Floating open drain I2C bus pins RESET Reset function enabled Default input internal pull up Reset function disabled floating if the part enabled is in deep power down mode the RESET pin needs an external pull up to reduce power consumption PIOO 16 As configured in the IOCONU WAKEUP function inactive Wake up function enabled can be disabled WAKEUP by software 1 Default and programmed pin states are retained in sleep deep sleep and power down modes LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 71 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 15 Package outline TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1
23. except the open drain pins PIOO 10 and PIOO 11 Table 19 SPI dynamic characteristics Tamb 40 C to 105 C C 20 pF input slew 1 ns Simulated parameters sampled at the 30 and 70 level of the rising or falling edge values guaranteed by design Delays introduced by the external trace or external device are not considered Symbol Parameter Conditions Min Max Unit SPI master tps data set up time 1 8 V lt Vpp lt 3 6 V 2 ns tpH data hold time 1 8 V lt Vpp lt 3 6 V 6 ns twa data output valid time 1 8 V lt Vpp lt 3 6 V 3 4 ns SPI slave tps data set up time 1 8 V lt Vpp lt 3 6 V 2 ns tpH data hold time 1 8 V lt Vpp lt 3 6 V 4 ns twa data output valid time 3 0 V lt Vpp lt 3 6 V 0 26 ns 1 8 V lt Vpp lt 3 0 V 0 35 ns All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 56 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Toy clk SCK CPOL 0 Y SCK CPOL 1 mE M Max SSEL m ee EN M a MOSI CPHA 0 twa ie lt tQ DATA VALID MSB DATA VALID DATA VALID LSB IDLE DATA VALID MSB MISO CPHA 0 S H d DATA VALID MSB DATA VALID DATA VALID LSB IDLE DATA VALID MSB MOSI CPHA 1 twa je
24. in active mode as low as 90 uA MHz in low current mode using the IRC as the clock source Integrated PMU Power Management Unit to minimize power consumption Reduced power modes Sleep mode Deep sleep mode Power down mode and Deep power down mode Wake up from Deep sleep and Power down modes on activity on USART SPI and I2C peripherals Timer controlled self wake up from Deep power down mode LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 2 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Power On Reset POR Brownout detect BOD 3 Applications Unique device serial number for identification Single power supply 1 8 V to 3 6 V Operating temperature range 40 C to 105 C Available in a TSSOP20 and HVQFN33 5x5 package Sensor gateways Industrial Gaming controllers 8 16 bit applications Consumer Climate control Simple motor control Portables and wearables Lighting Motor control 4 Ordering information Fire and security applications Table 1 Ordering information Type number Package Name Description Version LPC824M201JHI33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads n a 33 t
25. in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 38 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 11 4 Power consumption Power measurements in Active Sleep Deep sleep and Power down modes were performed under the following conditions Configure all pins as GPIO with pull up resistor disabled in the IOCON block Configure GPIO pins as outputs using the GPIO DIR register Write 1 to the GPIO CLR register to drive the outputs LOW 4 aaa 013992 lop 30 MHz 24 MHz on 12 MHz Po 6 MHz 3 4 MHz 3 MHz 2 MHz 1 MHz 2 0 1 8 24 3 Vpp V Conditions Tamb 25 C active mode entered executing code while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 MHz 6 MHz external clock IRC PLL disabled 12 MHz IRC enabled PLL disabled 24 MHz IRC enabled PLL enabled 30 MHz system oscillator enabled PLL enabled Fig 13 Active mode Typical supply current lpp versus supply voltage Vpp LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 39 of 81 NXP Semiconductors LPC82
26. input or output condition such as a rising or falling edge or level a combination of match and or input output condition Selected events can limit halt start or stop a counter or change its direction Events trigger state changes output toggles interrupts and DMA transactions Match register 0 can be used as an automatic limit n bidirectional mode events can be enabled based on the count direction Match events can be held until another qualifying event occurs e State control features A state is defined by events that can happen in the state while the counter is running A state changes into another state as a result of an event Each event can be assigned to one or more states State variable allows sequencing across multiple counter cycles One SCTimer match output can be selected as ADC hardware trigger input 8 16 2 SCTimer PWM input MUX INPUT MUX LPC82x Each input of the SCTimer PWM is connected to a programmable multiplexer which allows to connect one of multiple internal or external sources to the input The available sources are the same for each SCTimer PWM input and can be selected from four pins configured through the switch matrix the ADC threshold compare interrupt the comparator output and the ARM core signals ARM_TXEV and DEBUG_HALTED All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved
27. is 10 Mbit s in synchronous mode master mode and 10 Mbit s in synchronous slave mode Remark USART functions can be assigned to all digital pins The characteristics are valid for all digital pins except the open drain pins PIOO 10 and PIOO 11 Table 20 USART dynamic characteristics Tamb 40 C to 105 C 1 8 V lt Vpp lt 3 6 V unless noted otherwise C 10 pF input slew 10 ns Simulated parameters sampled at the 30 96 70 96 level of the falling or rising edge values guaranteed by design Symbol Parameter Conditions Min Max Unit USART master in synchronous mode tsu D data input set up time 3 0 V lt Vpp lt 3 6 V 31 ns 1 8 V lt Vpp lt 3 0 V 37 th D data input hold time 0 ns twa data output valid time 0 5 ns USART slave in synchronous mode tsu D data input set up time 6 ns th D data input hold time 2 ns twa data output valid time 3 0 V lt Vpp lt 3 6 V 0 28 ns 1 8 V lt Vpp lt 3 0 V 0 37 ns je Toy clk gt Un SCLK CLKPOL 0 f Un_SCLK CLKPOL 1 twQ gt lt twa tsu D th D aaa 015074 In master mode Toyo U_PCLK BRGVAL See the LPC82x User manual Fig 36 USART timing LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet
28. level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 4 V Vou HIGH level output lou 4 mA 2 5 V lt Vpp lt 3 6 V Vpp 0 4 V voltage loH 3 mA 1 8 V lt Vpp lt 2 5 V mra V VoL LOW level output loi 4 mA 2 5 V lt Vpp lt 3 6 V 0 4 V voltage lo 3 mA 1 8 V lt Vpp lt 2 5 V 04 V lou HIGH level output Vou Vpp 0 4 V 4 mA current 2 5 V lt Vpp lt 3 6 V 1 8 V lt Vpop lt 2 5 V 3 mA lot LOW level output VoL 0 4 V 4 mA current 2 5 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 5 V 3 mA lous HIGH level short circuit Vop 0 V 7 45 mA output current lois LOW level short circuit Voi Vpp 7 50 mA output current lod pull down current Vi 5V 10 50 150 uA lou pull up current Vi 0 V 2 0 V lt Vpp lt 3 6 V 15 50 85 uA 1 8 V lt Vpop lt 2 0 V 10 50 85 Vpp VI 5M 0 0 0 uA High drive output pin configured as digital pin PIOO 2 PIOO 3 PIOO 12 PIOO 13 lit LOW level input current V 0 V on chip pull up resistor 0 5 1012 nA disabled liH HIGH level input Vi Vpp on chip pull down resistor 0 5 10821 nA current disabled loz OFF state output Vo 0 V Vo Vpp on chip 0 5 10121 nA current pull up down resistors disabled LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet
29. line which fits the ideal curve See Figure 38 8 The full scale error voltage or gain error Eg is the difference between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 38 9 Tamb 25 C maximum sampling frequency f 2 Msamples s and analog input capacitance Cia 0 1 pF 10 Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including Cia and Cio Zi 1 fs x Ci See Table 8 for Cio LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 61 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller R4 0 25 kQ 2 5 KQ ADCn 0 Rew 5 Q 250 m Cio ADOn 1 11 Fig 37 ADC input impedance Cio aaa 011748 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved LPC82x Product data sheet Rev 1 1 October 2014 62 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller offset gain error error Eo Ec ee NN 4095 4094 4093 4092 4091 l 4090 EN X E code out 6 5 H 4 9 qe 2 1 H 1
30. open drain modes can be programmed through the IOCON block for each GPIO pin see Figure 7 Direction input output can be set and cleared individually Pin direction bits can be toggled Pin interrupt pattern match engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC The pattern match engine can be used with software to create complex state machines based on pin inputs Any digital pin independently of the function selected through the switch matrix can be configured through the SYSCON block as input to the pin interrupt or pattern match engine The registers that control the pin interrupt or pattern match engine are on the IO bus for fast single cycle access Features Pin interrupts Upto eight pins can be selected from all digital pins as edge or level sensitive interrupt requests Each request creates a separate interrupt in the NVIC Edge sensitive interrupt pins can interrupt on rising or falling edges or both Level sensitive interrupt pins can be HIGH or LOW active All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 16 of 81 NXP Semiconductors LPC82x 8 12 8 12 1 8 12 2 8 13 8 13 1 LPC82x 32 bit ARM Cortex M0 microcontroller Pin interrupts can wake up t
31. pulled up above Vpp The pins are not 5 V tolerant when Vpp is grounded Program the input glitch filter with different filter constants using one of the IOCON divided clock signals IOCONCLKCDIV see Figure 9 LPC82x clock generation You can also bypass the glitch filter e Invert the input signal Hysteresis can be enabled or disabled e For pins PIOO 10 and PIOO 11 select the I2C mode and output driver for standard digital operation for I2C standard and fast modes or for I2C Fast mode The switch matrix setting enables the analog input mode on pins with analog and digital functions Enabling the analog mode disconnects the digital functionality Remark The functionality of each I O pin is flexible and is determined entirely through the switch matrix See Section 8 9 for details Standard I O pad configuration Figure 7 shows the possible pin modes for standard I O pins with analog input function Digital output driver with configurable open drain output Digital input Weak pull up resistor PMOS device enabled disabled Digital input Weak pull down resistor NMOS device enabled disabled All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 14 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Digital input Repeater mode enabled disabled Digital
32. the SCT disabled in the SYSAHBCLKCTRL register BOD disabled internal pull up resistors enabled Measured with Keil uVision 5 10 1 MHz 6 MHz external clock IRC PLL disabled 12 MHz IRC enabled PLL disabled 24 MHz IRC enabled PLL enabled 30 MHz system oscillator enabled PLL enabled Fig 23 CoreMark score 18 24 system clock frequency MHz 30 aaa 014007 8 IDD mA 6 default 4 CPU pertormance efficiency low current 2 0 0 6 12 18 Conditions Vp Measured with Keil uVision 5 10 1 MHz 6 MHz external clock IRC PLL disabled 12 MHz IRC enabled PLL disabled 24 MHz IRC enabled PLL enabled 30 MHz system oscillator enabled PLL enabled p 3 3 V Tamb 25 C active mode all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register BOD disabled internal pull up resistors enabled Fig 24 Active mode CoreMark power consumption lpp 24 30 system clock frequency MHz All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 45 of 81 NXP Semiconductors LPC82x 11 6 Peripheral power consumption 32 bit ARM Cortex M0 microcontroller The supply current per peripheral is measured as the difference i
33. the SysOsc the external clock source or the PLL are needed by the application software must enable these features and wait for them to stabilize before they are used as a clock source Power conirol The LPC82x supports the ARM Cortex MO Sleep mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition a register is provided for shutting down the clocks to individual on chip peripherals allowing to fine tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile API The API is accessible through the on chip ROM The power configuration routine configures the LPC82x for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optimized processing capability Efficiency mode corresponding to optimized balance of current consumption and CPU performance Low current mode corresponding to lowest power consumption In addition the power profile includes routines t
34. the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values In Deep power down mode an external pull up resistor is required on the RESET pin 20 ns RC reset aumrcH FILTER lt Vss aaa 004613 Fig 10 Reset pad configuration 8 23 2 Brownout detection LPC82x The LPC82x includes up to four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt Alternatively software can monitor the signal by reading a dedicated status register Four threshold levels can be selected to cause a forced reset of the chip All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 28 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 8 23 3 Code security Code Read Protection CRP CRP provides different levels of security in the system so that access to the on chip flash and use of the Serial Wire Debugger SWD and In System Programming ISP can be restricted Programming a specific pattern into a dedicated flash location invokes CRP IAP commands are not affe
35. the pin interrupt block a watchdog timer interrupt or an interrupt from the USART if the USART is configured in synchronous slave mode the SPI or the I2C blocks in slave mode Any interrupt used for waking up from Deep sleep mode must be enabled in one of the SYSCON wake up enable registers and the NVIC Deep sleep mode saves power and allows for short wake up times Power down mode In Power down mode the LPC82x is in Sleep mode and all peripheral clocks and all clock sources are off except for watchdog oscillator or low power oscillator if selected In addition all analog blocks and the flash are shut down In Power down mode the application can keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection The LPC82x can wake up from Power down mode via a reset digital pins selected as inputs to the pin interrupt block a watchdog timer interrupt or an interrupt from the USART if the USART is configured in synchronous slave mode the SPI or the I2C blocks in slave mode Any interrupt used for waking up from Power down mode must be enabled in one of the SYSCON wake up enable registers and the NVIC Power down mode reduces power consumption compared to Deep sleep mode at the expense of longer wake up times Deep power down mode In Deep power down mode power is shut off to the entire chip except for the WAKEUP pin and the self wake up timer if enabled Four general purpose register
36. up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog I O for the system oscillator When configured for XTALIN and XTALOUT the digital section of the pin is disabled and the pin is not 5 V tolerant The WKTCLKIN function is enabled in the DPDCTRL register in the PMU See the LPC82x user manual The digital part of this pin is 3 V tolerant pin due to special analog functionality Pin provides standard digital I O functions with configurable modes configurable hysteresis and an analog input When configured as an analog input the digital section of the pin is disabled Table 4 Movable functions assign to pins PIOO 0 to PIOO 28 through switch matrix Function name Type Description UO TXD O Transmitter output for USARTO UO RXD Receiver input for USARTO UO RTS O Request To Send output for USARTO UO CTS Clear To Send input for USARTO UO SCLK y o Serial clock input output for USARTO in synchronous mode U1 TXD O Transmitter output for USART1 U1 RXD Receiver input for USART1 U1 RTS O Request To Send output for USART1 U1 CTS Clear To Send input for USART1 U1 SCLK 1 0 Serial clock input output for USART1 in synchronous mode U2_TXD O Transmitter output
37. 0 0x4007 0000 0x4006 C000 0xA000 8000 0xA000 4000 0xA000 0000 0x4006 8000 0x4006 4000 reserved 0x4006 0000 0x4005 C000 0x5000 C000 0x5000 8000 SCTimer PWM 0x5000 4000 0x5000 0000 reserved 0x4005 8000 0x4005 4000 0x4008 0000 1GB APB peripherals l ox40000000 0x4003 C000 0x1000 1000 4 KB SRAMO 0x1000 0000 reserved 1 0x4003 8000 Tasi 0 5 GB 0x2000 0000 0x4003 0000 n input mux 0x4002 C000 E reserved z 10 DMA TRIGMUX 0x4002 8000 ice 1 analog comparator 12 KB boot ROM okr odon 3 1 iia 0x4002 4000 m d 8 PMU 0x4002 0000 reserved oann 7d 12 bit ADC 0x4001 C000 4 KB MTB registers 6 reserved x1400 0000 0x4001 8000 51 reserved 0x4001 4000 reserved 43 reserved 0x4001 0000 0x1001 2000 3 switch matrix 0x4000 C000 4 KB SRAM1 21 self wake up timer 0x4000 8000 0x4000 4000 0x4000 0000 o ENS reserved E 0x0000 8000 0x0000 00CO 32 KB on chip flash active interrupt vectors Ox0000 0000 0GB 0x0000 0000 aaa 015072 Fig 6 LPC82x Memory mapping 8 6 Nested Vectored Interrupt Controller NVIC The Nested Vectored Interrupt Controller NVIC is part of the Cortex M0 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 8 6 1 Features e Nested Vectored Interrupt Controller is a part of the ARM Cortex M0 LPC82x All information provided in this document is subject to lega
38. 82x 14 2 LPC82x 32 bit ARM Cortex M0 microcontroller LPC800 T XTALIN XTALOUT CL CP XTAL ii Rs Cx1 CX2 EE A i aaa 004647 Fig 41 Oscillator modes and models oscillation mode of operation and external crystal model used for Cy4 Cy evaluation Table 27 Recommended values for Cx1 Cx2 in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cxy1 Cx 1 MHz to 5 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF lt 300 Q 39 pF 39 pF 30 pF lt 300 Q 57 pF 57 pF 5 MHz to 10 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF 200 0 39 pF 39 pF 30 pF 1000 57 pF 57 pF 10 MHz to 15 MHz 10 pF 1600 18 pF 18 pF 20 pF 600 39 pF 39 pF 15 MHz to 20 MHz 10 pF 800 18 pF 18 pF Table 28 Recommended values for Cy4 Cyz in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cxy1 Cx2 15 MHz to 20 MHz 10 pF 1800 18 pF 18 pF 20 pF 100 0 39 pF 39 pF 20 MHz to 25 MHz 10 pF 1600 18 pF 18 pF 20 pF 800 39 pF 39 pF XTAL Printed Circuit Board PCB layout guidelines The crystal shoul
39. 9 122 I2C2 52 127 I2C3 57 142 SPIO 55 136 SPI1 55 136 USARTO 50 124 USART1 54 134 USART2 56 138 Comparator ACMP 34 82 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 46 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 10 Power consumption for individual analog and digital blocks continued Peripheral Typical supply current in pA Notes Main clock frequency n a 12 MHz 30 MHz ADC 57 141 Digital controller only Analog portion of the ADC disabled in the PDRUNCFG register 57 141 Combined analog and digital logic ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 1 in the ADC CTRL register ADC in low power mode 1990 2070 Combined analog and digital logic ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 0 in the ADC CTRL register ADC powered DMA 324 793 CRC 34 85 11 7 Electrical pin characteristics aaa 013973 4 8 12 20 24 loH mA Conditions Vpp 1 8 V on pin PIOO 12 3 5 VoH V Conditions Vpp 3 3 V on pin PIOO 12 Fig 25 High drive output Typical HIGH level output voltage Voy versus HIGH level output current loy aaa 013974
40. API support Boot loader On chip ROM APIs for ADC SPI I2C USART power configuration power profiles and integer divide Flash In Application Programming IAP and In System Programming ISP W Digital peripherals High speed GPIO interface connected to the ARM Cortex MO IO bus with up to 29 General Purpose I O GPIO pins with configurable pull up pull down resistors programmable open drain mode input inverter and digital filter GPIO direction control supports independent set clear toggle of individual bits High current source output driver 20 mA on four pins NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller High current sink driver 20 mA on two true open drain pins GPIO interrupt generation capability with boolean pattern matching feature on eight GPIO inputs Switch matrix for flexible configuration of each I O pin function CRC engine DMA with 18 channels and 9 trigger inputs B Timers State Configurable Timer SCTimer PWM with input and output functions including capture and match for timing and PWM applications Each SCTimer PWM input is multiplexed to allow selecting from several input sources such as pins ADC interrupt or comparator output Four channel Multi Rate Timer MRT for repetitive interrupt generation at up to four programmable fixed rates Self Wake up Timer WKT clocked from either the IRC a low power low frequ
41. LSB ideal 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 5 Via LSB offset error ta LSBidea Eo VREFP V 1LSB NGA TU SS 4096 002aaf436 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity E agj 5 Center of a step of the actual transfer curve Fig 38 12 bit ADC characteristics LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 63 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 13 3 Comparator and internal voltage reference Table 23 Internal voltage reference static and dynamic characteristics Tamb 40 C to 105 C Vpp 3 3 V hysteresis disabled in the comparator CTRL register Symbol Parameter Conditions Min Typ Max Unit Vo output voltage Tamb 25 C to 105 C 860 940 mV Tamb 25 C 904 mV 0 910 aaa 014424 Vo V 0 905 0 900 0 895 0 890 40 10 20 50 80 110 temperature C Vpp 3 3 V characterized through bench measurements on typical samples Fig 39 Typical internal voltage reference output voltage Table 24 Comparator characteristics Tamb 40 C to 105 C unless noted otherwise Vpp 1 8 V to 3 6 V
42. OUT 13 417 BI i PU IO PIOO 9 General purpose port 0 input output 9 A XTALOUT Output from the oscillator circuit PIOO 10 22CO SCL 10 9 I8 Inactive I F PIOO 10 General purpose port 0 input output 10 open drain I2C0 SCL Open drain I2C bus clock input output High current sink if 12C Fast mode Plus is selected in the I O configuration register PIOO 11 22CO0 SDA 9 8 I8 Inactive F PIOO 11 General purpose port 0 input output 11 open drain I2C0 SDA Open drain I C bus data input output High current sink if 12C Fast mode Plus is selected in the I O configuration register PIOO 12 4 2 A l PU IO PIOO 12 General purpose port 0 input output 12 ISP entry pin A LOW level on this pin during reset starts the ISP command handler PIOO 13 ADC 10 3 1 2l PU IO PIOO 13 General purpose port 0 input output 13 A ADC 10 ADC input 10 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 8 of 81 NXP Semiconductors LPC82x Table 3 Pin description 32 bit ARM Cortex M0 microcontroller Symbol S 8 Reset Type Description E lt state 9 S E GE PIOO 14 20 25 2 l PU IO PIOO 14 General purpose port 0 input output 14
43. Sleep mode 26 8 4 On chip ROM aoaaa aaaea raaraa io See P CORS oare LE i peyis 85 Memory map 12 Con E ui EPOR E ee cata Se NC ay a oie ae 22 6 ower down mode 0 5 1 irc ei Intent Controller VIN VIG 8 22 6 5 Deep power down mode 27 p pe RIEN ET dU 8 23 System control 0 0 e eee ee eee 28 8 6 2 Interrupt SourceS 000 0 eee 14 8 23 4 Reset 28 8 7 System tick timer 0 00e eeu ee 14 pode a Re ice eee S 88 VO configuration 14 8 23 2 Brownout detection 4 28 EL Se qo ES 8 23 3 Code security Code Read Protection CRP 29 8 8 1 Standard I O pad configuration 14 8234 APBinterface 29 8 9 Switch Matrix GWM 00005 15 8235 AHBLite 23 Eii aaia ded MI a aaa eo 29 8 10 Fast General Purpose parallel I O GPIO 16 8 24 Emulation and debugging 30 8 10 1 Features i ns esas sme ea ce eae ee eee 16 posed 8 11 Pin interrupt pattern match engine 16 pi E ben Mod E LL ALD x 8 11 1 PalifaSos ceo ond Econ RR Ren 16 ermal characteristics 8 12 DMA controller 17 11 Static characteristics 33 8 12 1 F6a3til8S 2 niuleeeiearee aaa 17 11 1 General operating conditions 33 8 12 2 DMA trigger input MUX TRIGMUX 17 112 Supply pins 00000 eee 34 8 13 USARTOA 2 0 eee 17 11 3 Electrical pin characteristics 36 8 13 1 Features oiaoi ot
44. VDD 3 3 V s LPC82x 100 kQ VTREF lt SND SWDIO lt gt rom connector SWELK T nRESET GND 10 kQ alls 100 kQ DGND PIOO_12 ISP ent m aaa 015075 Fig 11 Connecting the SWD pins to a standard SWD connector LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 30 of 81 NXP Semiconductors LPC82x 9 Limiting values 32 bit ARM Cortex M0 microcontroller Table 5 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Conditions Min Max Unit Vpp supply voltage core and external 2 0 5 44 6 V rail Vref reference voltage on pin VREFP 0 5 Vpp V Vi input voltage 5 V tolerant I O pins Vpp 3II4 0 5 45 5 V 1 8 V on I2C open drain pins 5 0 5 45 5 V PIOO 10 PIOO 11 3 V tolerant I O pin PIOO 6 6 0 5 43 6 V ViA analog input voltage Pils 0 5 4 6 V 9 Vi xtal crystal input voltage 21 0 5 42 5 V Ipp supply current per supply pin 100 mA Iss ground current per ground pin 100 mA latch I O latch up current 0 5Vpp lt Vi lt 1 5Vpp 100 mA Tj lt 125 C Tstg storage temperature 10 _65 150 C Tjmax maximum junction temperature 150 C Ptot pack total power dissipation per based on package heat 1 5 W package transfer not device power consump
45. a sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 20 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a P
46. addresses nxp com LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 79 of 81 NXP Semiconductors LPC82x 22 Contents 32 bit ARM Cortex M0 microcontroller 1 General description 1 8 20 1 FeatureS 0000 eee eee eee 22 2 Features and benefits 5 1 821 Analog to Digital Converter ADC inati 8 21 1 Features oe sce iene aeoea e sa y PBBIIESQOn SN eO HELL LM DN 8 22 Clocking and power control 24 Ordering information A 2 8 22 1 Crystal and internal oscillators 24 41 Ordering options sisse 3 8224 1 Internal RC Oscillator IRC 25 5 Marking esee 4 82242 Crystal Oscillator SysOsc 25 6 Block diagram eesees 5 8 22 1 3 Internal Low power Oscillator and Watchdog 7 Pinning information 00e000 6 or eae WDOsc seen zi 7 1 PINN eae aie paed anir te ida been 6 22 ockinput sien nnn 7 2 Pin description 0 0 00 eee eee 7 ree se di Spe ae E i 22 OCK output llle esee E 1 e a Ec EN LEN He 8 22 5 Wake up procesS 2 05 26 Baha Ct Mea eee EM M 8 22 6 Power control 26 Be On enip fash Te sss ss mei 12 8226 1 Power profiles sess 26 8 3 On chip SRAM 020 00 cee eee 12 82262
47. ched off the SDA and SCL pins connected to the I CO bus are floating and do not disturb the bus e 2C1 2 3 support standard and fast mode with data rates of up to 400 kbit s Independent Master Slave and Monitor functions Supports both Multi master and Multi master with Slave functions Multiple 12C slave addresses supported in hardware One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple IC bus addresses 10 bit addressing supported with software assist Supports SMBus 8 16 SCTimer PWM The state configurable timer can perform basic 16 bit and 32 bit timer counter functions with match outputs and external and internal capture inputs In addition the SCTimer PWM can employ up to eight different programmable states which can change under the control of events to provide complex timing patterns The inputs to the SCT are multiplexed between movable functions from the switch matrix and internal connections such as the ADC threshold compare interrupt the comparator output and the ARM core signals ARM TXEV and DEBUG HALTED The signal on each SCT input is selected through the INPUT MUX All outputs of the SCT are movable functions and are assigned to pins through the switch matrix One SCT output can also be selected as one of the ADC conversion triggers 8 16 1 Features Each SCTimer PWM supports Eight match capture registers Eight events
48. cj A Cc ay 1 E i e2 1 2 e ci Y 24 terminal 1 index area 32 25 Dn 0 d A i L 1 1 Dimensions mm are the original dimensions scale Uni A AY b c DD p EU E e e e L v w y y max 0 05 0 30 51 375 51 375 0 5 mm nom 0 85 0 2 05 35 35 0 1 0 05 0 05 0 1 min 0 00 0 18 49 345 49 345 0 3 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvgfn33f po i References Outline bak Furopean Issue date version IEC JEDEC JEITA projection 440 44 MO 220 E 11 10 17 Fig 44 Package outline HVQFN33 5x5 LPC82x All information provided in this document is subject to legal disclaimers Rev 1 1 October 2014 NXP Semiconductors N V 2014 All rights reserved 73 of 81 Product data sheet NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 16 Soldering SOT360 1 Footprint information for reflow soldering of TSSOP20 package UEM B ee mE IT NS ri ZA i A Ai W ay By Ay ETETE E mia le D2 4x Ld D1 Generic footprint pattern Refer to the package outline drawing for actual layout 7 solder land Occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0 650 0 750 7 200 4 500 1 350 0 400 0 600 6 900 5 300 7 300 7 450 sot360 1_fr Fig 45 Reflow soldering of the TSSOP20 package LPC82x All information provided in this document is subject to legal disclaimers
49. control and any GPIO as an RTS output Received data and status can optionally be read from a single register Break generation and detection Receive data is 2 of 3 sample voting Status flag set when one sample differs Built in Baud Rate Generator A fractional rate divider is shared among all UARTs Interrupts available for Receiver Ready Transmitter Ready Receiver Idle change in receiver break detect Framing error Parity error Overrun Underrun Delta CTS detect and receiver sample noise detected Separate data and flow control loopback modes for testing Baud rate clock can also be output in asynchronous mode Supported by on chip ROM API 8 14 SPIO0 1 All SPI functions are movable functions and are assigned to pins through the switch matrix 8 14 1 8 15 LPC82x Features Maximum data rates of up to 30 Mbit s in master mode and up to 18 Mbit s in slave mode for SPI functions connected to all digital pins except the open drain pins Data frames of 1 to 16 bits supported directly Larger frames supported by software Master and slave operation Data can be transmitted to a slave without the need to read incoming data which can be useful while setting up an SPI memory Control information can optionally be written along with data which allows very versatile operation including any length frames One Slave Select input output with selectable polarity and flexible usage Remark Texas Instruments SSI a
50. cted by the CRP In addition ISP entry via the ISP entry pin can be disabled without enabling CRP For details see the LPC82x user manual There are three levels of Code Read Protection 1 CRP1 disables access to the chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased 2 CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP This mode effectively disables ISP override using the ISP entry pin as well If necessary the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART CAUTION AN If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device LPC82x 8 23 4 8 23 5 In addition to the three CRP levels sampling of the ISP entry pin for valid user code can be disabled For details see the LPC82x user manual APB interface The APB peripherals are located on one APB bus AHBLite The AHBLite connects the CPU bus of the ARM Cortex MO to the flash memory the main static RAM the CRC the DMA the ROM an
51. d be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors Cx1 Cx2 and Cyg in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plain Loops must be made as small as possible in All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 68 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Values of C44 and Cys should be chosen smaller according to the increase in parasitics of the PCB layout 14 3 Connecting power clocks and debug functions Figure 42 shows the basic board connections used to power the LPC82x connect the external crystal and provide debug capabilities via the serial wire port LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 69 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 3 3 V 3 3V SWD connector 10 KQ 100 KQ Note 4 SWDIO PIOO 2 SWCLK PIOO 3 10 KQ
52. d the APB peripherals All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 29 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 8 24 Emulation and debugging Debug functions are integrated into the ARM Cortex M0 Serial wire debug functions are supported in addition to a standard JTAG boundary scan The ARM Cortex MO is configured to support up to four breakpoints and two watch points The Micro Trace Buffer is implemented on the LPC82x The RESET pin selects between the JTAG boundary scan RESET LOW and the ARM SWD debug RESET HIGH The ARM SWD debug port is disabled while the LPC82x is in reset The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode on pins PIOO 0 to PIOO 3 see Table 3 To perform boundary scan testing follow these steps Erase any user code residing in flash Power up the part with the RESET pin pulled HIGH externally Wait for at least 250 us Pull the RESET pin LOW externally Perform boundary scan operations Once the boundary scan operations are completed assert the TRST pin to enable the SWD debug mode and release the RESET pin pull HIGH O c FWD Remark The JTAG interface cannot be used for debug purposes
53. d up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 25 of 81 NXP Semiconductors LPC82x 8 22 4 8 22 5 8 22 6 8 22 6 1 8 22 6 2 LPC82x 32 bit ARM Cortex M0 microcontroller its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset and may be enabled by software The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is nominally 100 us Clock output The LPC82x features a clock output function that routes the IRC the SysOsc the watchdog oscillator or the main clock to the CLKOUT function The CLKOUT function can be connected to any digital pin through the switch matrix Wake up process The LPC82x begin operation at power up by using the IRC as the clock source allowing chip operation to resume quickly If
54. disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 6 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 7 2 Pin description The pin description table Table 3 shows the pin functions that are fixed to specific pins on each package These fixed pin functions are selectable through the switch matrix between GPIO and the comparator ADC SWD RESET and the XTAL pins By default the GPIO function is selected except on pins PIOO 2 PIOO 3 and PIOO_5 JTAG functions are available in boundary scan mode only Movable function for the I2C USART SPI and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin s fixed functions The following exceptions apply Do not assign more than one output to any pin However more than one input can be assigned to a pin Once any function is assigned to a pin the pin s GPIO functionality is disabled Pin PIOO 4 triggers a wake up from Deep power down mode If the part must wake up from Deep power down mode via an external pin do not assign any movable function to this pin The JTAG functions TDO TDI TCK TMS and TRST are selected on pins PIOO 0 to PIOO 4 by hardware when the part is in boundary scan mode Table 3 Pin description Symbol Reset Type Description statel PIOO 0 ACMP 11 TDO TSSOP20 I HVQFN33
55. driven by a clock in slave mode it is recommended to couple the input through a capacitor with C 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground C which attenuates the input voltage by a factor C C Cg In slave mode a minimum of 200 mV RMS is needed LPC800 aaa 004646 Fig 40 Slave mode operation of the on chip oscillator In slave mode the input clock signal should be coupled with a capacitor of 100 pF Figure 40 with an amplitude between 200 mV RMS and 1000 mV RMS This corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 41 and in Table 27 and Table 28 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cys must be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C and Rs Capacitance Cp in Figure 41 represents the parallel package capacitance and should not be larger than 7 pF Parameters Fosc Ci Rs and Cp are supplied by the crystal manufacturer see Table 27 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 67 of 81 NXP Semiconductors LPC
56. duct data sheet Rev 1 1 October 2014 70 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull up disabled To configure a GPIO pin as output and drive it LOW select the GPIO function in the IOCON register select output in the GPIO DIR register and write a 0 to the GPIO PORT register for that pin Disable the pull up in the pin s IOCON register In addition it is recommended to configure all GPIO pins that are not bonded out on smaller packages as outputs driven LOW with their internal pull up disabled Table 29 Termination of unused pins Pin Default Recommended termination of unused pins statel RESET PIOO 5 l PU In an application that does not use the RESET pin or its GPIO function the termination of this pin depends on whether Deep power down mode is used Deep power down used Connect an external pull up resistor and keep pin in default state input pull up enabled during all other power modes Deep power down not used and no external pull up connected can be left unconnected if internal pull up is disabled and pin is driven LOW and configured as output by software all PlOn m not I PU Can be left unconnected if driven LOW and configured as GPIO output with pull up open drain disabled by software PlOn m I2C open drain IA Can be left unconnected if
57. e Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 78 of 81 NXP Semiconductors LPC82x Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this speci
58. e dedicated watchdog oscillator WDOSC 8 19 Self Wake up Timer WKT The self wake up timer is a 32 bit loadable down counter Writing any non zero value to this timer automatically enables the counter and launches a count down sequence When the counter is used as a wake up timer this write can occur prior to entering a reduced power mode 8 19 1 Features 32 bit loadable down counter Counter starts automatically when a count value is loaded Time out generates an interrupt wake up request The WKT resides in a separate always on power domain The WKT supports three clock sources an external clock on the WKTCLKIN pin the low power oscillator and the IRC The low power oscillator is located in the always on power domain so it can be used as the clock source in Deep power down mode LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 21 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller The WKT can be used for waking up the part from any reduced power mode including Deep power down mode or for general purpose timing 8 20 Analog comparator ACMP The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages After power up and after switching the input channels of the comparator the output of the volta
59. ed as output 3 0 5 0 ns tr fall time pin configured as output 2 5 5 0 ns 1 Applies to standard port pins and RESET pin 12 3 2 WKTCLKIN pin wake up clock input Table 16 Dynamic characteristics WKTCLKIN pin Tamb 40 C to 105 C 1 8 V lt Vpp x 3 6 V Symbol Parameter Conditions Min Max Unit folk clock frequency deep power down mode and 1 MHz power down mode deep sleep sleep and active mode 10 MHz tcHcx clock HIGH time 50 ns tcLcx clock LOW time 50 ns 1 12 3 3 Assuming a square wave input clock SCTimer PWM output timing Table 17 SCTimer PWM output dynamic characteristics Tamb 40 C to 105 C 2 4 V lt Vpp lt 3 6 V C 10 pF Simulated skew over process voltage and temperature of any two SCT output signals routed to standard I O pins sampled at the 50 level of the falling or rising edge values guaranteed by design Symbol Parameter Conditions Min Typ Max Unit tsk o output skew time 4 ns 12 3 4 I C bus Table 18 Dynamic characteristic I2C bus pins Tamb 40 C to 105 C values guaranteed by design 2 Symbol Parameter Conditions Min Max Unit fscL SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz Fast mode Plus on 0 1 MHz pins PIOO 10 and PIOO 11 tr fall time I4IISIISI7 of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 x Cp 300 ns Fas
60. ed herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC82x All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications a
61. ek the device was manufactured during that year Field R states the chip revision LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 4 of 81 NXP Semiconductors LPC82x 6 Block diagram 32 bit ARM Cortex M0 microcontroller LPC82xM SWITCH MATRIX Fig 3 LPC82x block diagram SWCLK SWD 29x PIOO HIGH SPEED ee GPIO PIN INTERRUPTS oO PATTERN MATCH SCT PIN 3 0 scTIMER PWM INPUT MUX SCT_OUTI6 0 CORTEX M0 TEST DEBUG INTERFACE ARM FLASH SRAM 16 32 KB 4 8 KB slave slave slave U AHB LITE BUS master slave AHB TO APB BRIDGE MISO MOSI 4 spon TXD RTS RXD CTS ARTO 1 2 SCLK US 0 1 SCK SSEL SCL SDA gt 12C0 1 2 3 XTALOUT XTALIN __ _ _ RESET CLKIN CLKOUT ADC 11 0 ACMP 4 1 COMPARATOR Gray shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers C owe CoL o MULTI RATE TIMER I l C gt SELF WAKE UP TIMER ALWAYS ON POWER DOMAIN CLOCK GENERATION POWER CONTROL SYSTEM FUNCTIONS clocks and controls aaa 014399 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconducto
62. emiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 48 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 013977 18 aaa 0139 35 aaa 013978 4 5 6 16 loH mA lon mA Conditions Vpp 1 8 V standard port pins Conditions Vpp 3 3 V standard port pins Fig 28 Typical HIGH level output voltage Voy versus HIGH level output source current lou 0 aaa 013979 0 aaa 013980 Ipu lpu uA uA 14 28 us 1053 40 C 42 90 C 56 25 C 16 70 0 0 7 1 4 2 1 2 8 3 5 0 1 2 3 4 vi V Vi V Conditions Vpp 1 8 V standard port pins Conditions Vpp 3 3 V standard port pins Fig 29 Typical pull up current Ipy versus input voltage Vj LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 49 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 35 aaa 013981 80 aaa 013982 Ipd Ipd uA pA 60 40 C 40 25 C 90 105 C 20 0 0 0 7 1 4 2A 2 8 3 5 0 1 2 3 4 Vi V Vi V Conditions Vpp 1 8 V standard p
63. ences LPC82x 1 3 4 LPC82x User manual UM10800 http Avww nxp com documents user_manual UM10800 pdf LPC82x Errata sheet http Awww nxp com documents errata_sheet ES_LPC82X pdf I2C bus specification UM10204 Technical note ADC design guidelines http www nxp com documents technical note TN00009 pdf All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 76 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 19 Revision history Table 32 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC82X v 1 20141001 Product data sheet LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 77 of 81 NXP Semiconductors LPC82x 20 Legal information 32 bit ARM Cortex M0 microcontroller 20 1 Data sheet status Document status I 2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short dat
64. ency internal oscillator or an external clock input in the always on power domain Windowed Watchdog timer WWDT W Analog peripherals One 12 bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 1 2 Msamples s The ADC supports two independent conversion sequences Comparator with four input pins and external or internal reference voltage W Serial peripherals Three USART interfaces with pin functions assigned through the switch matrix and one common fractional baud rate generator Two SPI controllers with pin functions assigned through the switch matrix Four I C bus interfaces One I2C supports Fast mode Plus with 1 Mbit s data rates on two true open drain pins and listen mode Three I2Cs support data rates up to 400 kbit s on standard digital pins W Clock generation 12 MHz internal RC oscillator trimmed to 1 5 96 accuracy that can optionally be used as a system clock Crystal oscillator with an operating range of 1 MHz to 25 MHz Programmable watchdog oscillator with a frequency range of 9 4 kHz to 2 3 MHz PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator the external clock input or the internal RC oscillator Clock output function with divider that can reflect all internal clock sources B Power control Power consumption
65. equency Oscillator with a nominal frequency of 10 kHz with 4096 accuracy for use with the self wake up timer 4 The dedicated Watchdog Oscillator WDOsc with a programmable nominal frequency between 9 4 kHz and 2 3 MHz with 4096 accuracy LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 24 of 81 NXP Semiconductors LPC82x 8 22 1 1 8 22 1 2 8 22 1 3 8 22 2 8 22 3 LPC82x 32 bit ARM Cortex M0 microcontroller Each oscillator except the low frequency oscillator can be used for more than one purpose as required in a particular application Following reset the LPC82x operates from the IRC until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency See Figure 9 for an overview of the LPC82x clock generation Internal RC Oscillator IRC The IRC may be used as the clock source for the WWDT and or as the clock that drives the PLL and then the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 5 accuracy over the entire voltage and temperature range The IRC can be used as a clock source for the CPU with or without using the PLL The IRC frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL Upon power up or any chip reset the LPC82x
66. er input MUX TRIGMUX Each DMA trigger is connected to a programmable multiplexer which connects the trigger input to one of multiple trigger sources Each multiplexer supports the same trigger sources the ADC sequence interrupts the SCT DMA request lines and pin interrupts PININTO and PININT1 and the outputs of the DMA triggers 0 and 1 for chaining DMA triggers USART0 1 2 All USART functions are movable functions and are assigned to pins through the switch matrix Features e Maximum bit rates of 1 875 Mbit s in asynchronous mode and 10 Mbit s in synchronous mode for USART functions connected to all digital pins except the open drain pins All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 17 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 7 8 or 9 data bits and 1 or 2 stop bits Synchronous mode with master or slave operation Includes data phase selection and continuous clock option Multiprocessor multidrop 9 bit mode with software address compare RS 485 possible with software address detection and transceiver direction control Parity generation and checking odd even or none One transmit and one receive data buffer RTS CTS for hardware signaling for automatic flow control Software flow control can be performed using Delta CTS detect Transmit Disable
67. erminals body 5 x 5 x 0 85 mm LPC822M101JHI33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads n a 33 terminals body 5 x 5 x 0 85 mm LPC824M201JDH20 TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1 LPC822M101JDH20 TSSOP20 _ plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1 4 1 Ordering options Table 2 Ordering options Type number Flash SRAM USART lC SPI ADC Comparator GPIO Package KB KB channels LPC824M201JHI33 32 8 3 4 2 12 Y 29 HVQFN33 LPC822M101JHI33 16 4 3 4 2 12 Y 29 HVQFN33 LPC824M201JDH20 32 8 3 4 2 5 Y 16 TSSOP20 LPC822M101JDH20 16 4 3 4 2 5 y 16 TSSOP20 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 3 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 5 Marking 20 Terminal 1 index area x A z X Z E Terminal 1 index area aaa 014766 aaa 014382 Fig 1 TSSOP20 package marking Fig 2 HVQFN33 package marking The HVQFN33 packages typically have the following top side marking 82xJ XX XX yywwxR The TSSOP20 packages typically have the following top side marking LPC82x Mx01J XXXXXXXX zzywwxR In the last line field y or yy states the year the device was manufactured Field ww states the we
68. ettling to 99 of voltage H 18 us time ladder output value 1 Characterized on typical samples not tested in production LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 65 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller Table 26 Comparator voltage ladder reference static characteristics Vpp 1 8 V to 3 6 V Tamp 40 C to 105 C external or internal reference Symbol Parameter Conditions Min Typ U Max Unit Ev o output voltage error decimal code 00 2 l 6 mV decimal code 08 1 decimal code 16 1 decimal code 24 1 926 decimal code 30 1 decimal code 31 1 1 Characterized though limited samples Not tested in production 2 All peripherals except comparator temperature sensor and IRC turned off All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 66 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 14 Application information 14 4 XTAL input LPC82x The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is
69. f the SCL signal it must output the next data bit to the SDA line trmax tsu pAr 1000 250 1250 ns according to the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 54 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller tSU DAT SDA SCL aaa 004643 Fig 33 I C bus pins clock timing LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 55 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 12 3 5 SPI interfaces LPC82x In master mode the maximum supported bit rate is limited by the maximum system clock to 30 Mbit s In slave mode assuming a set up time of 3 ns for the external device and neglecting any PCB trace delays the maximum supported bit rate is 1 2 x 26 ns 3 ns 17 Mbit s at 3 0 V lt VDD lt 3 6 V and 13 Mbit s at 1 8 V lt VDD lt 3 0 V The actual bit rate depends on the delays introduced by the external trace and the external device Remark SPI functions can be assigned to all digital pins The characteristics are valid for all digital pins
70. fic NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 21 Contact information 32 bit ARM Cortex M0 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 20 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to sales
71. for USART2 U2 RXD Receiver input for USART2 U2 RTS O Request To Send output for USART1 U2 CTS Clear To Send input for USART1 U2 SCLK y o Serial clock input output for USART1 in synchronous mode SPIO SCK O Serial clock for SPIO SPIO_MOSI O Master Out Slave In for SPIO SPIO_MISO VO Master In Slave Out for SPIO SPIO_SSELO I O Slave select 0 for SPIO SPIO SSEL1 O Slave select 0 for SPI1 SPIO_SSEL2 O Slave select 0 for SPI2 SPIO_SSEL3 O Slave select 0 for SPI3 SPI1_SCK O Serial clock for SPI1 SPI1_MOSI O Master Out Slave In for SPI1 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 10 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller Table 4 Movable functions assign to pins PIOO 0 to PIOO 28 through switch matrix Function name Type Description SPI1 MISO VO Master In Slave Out for SPI1 SPI1 SSELO O Slave select 0 for SPI1 SPI1 SSEL1 O Slave select 1 for SPI1 SCT_PINO l Pin input 0 to the SCT input multiplexer SCT_PIN1 l Pin input 1 to the SCT input multiplexer SCT_PIN2 l Pin input 2 to the SCT input multiplexer SCT_PIN3 l Pin input 3 to the SCT input multiplexer SCT OUTO O SCT output 0 SCT OUT O SCT output 1 SCT OUT2 O SCT output 2 SCT OUT3 O SCT
72. ge ladder must be allowed to settle to its stable value before it can be used as a comparator reference input Settling times are given in Table 24 The analog comparator output is a movable function and is assigned to a pin through the switch matrix The comparator inputs and the voltage reference are enabled through the switch matrix pP l COMPARATOR ANALOG BLOCK VDD VDDCMP I I l 4 32 1 7 comparator il level ACMP O ADC trigger I e e I comparator edge NVIC l i ADC 0 I internal 1 voltage reference 4 ACMP_I 4 1 X I aaa 012135 Fig 8 Comparator block diagram 8 20 1 Features Selectable 0 mV 10 mV 5 mV and 20 mV 10 mV 40 mV 20 mV input hysteresis Two selectable external voltages Vpp or VDDCMP on pin PIOO 6 fully configurable on either positive or negative input channel Internal voltage reference from band gap selectable on either positive or negative input channel 32 stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 22 of 81 NXP Semic
73. he LPC82x from sleep mode deep sleep mode and power down mode Pin interrupt pattern match engine Upto eight pins can be selected from all digital pins to contribute to a boolean expression The boolean expression consists of specified levels and or transitions on various combinations of these pins Each minterm product term comprising the specified boolean expression can generate its own dedicated interrupt request Any occurrence of a pattern match can be also programmed to generate an RXEV notification to the ARM CPU The RXEV signal can be connected to a pin The pattern match engine does not facilitate wake up DMA controller The DMA controller can access all memories and the USART SPI I2C and ADC peripherals using DMA requests or triggers DMA transfers can also be triggered by internal events like the ADC interrupts the pin interrupts PININTO and PININT1 the SCTimer DMA requests and the DMA trigger outputs Features 18 channels with each channel connected to peripheral request inputs DMA operations can be triggered by on chip events or by two pin interrupts Each DMA channel can select one trigger input from 9 sources Priority is user selectable for each channel e Continuous priority arbitration Address cache with two entries Efficient use of data bus Supports single transfers up to 1 024 words Address increment options allow packing and or unpacking data DMA trigg
74. hip SRAM The LPC82x contain a total of 8 KB on chip static RAM data memory in two separate SRAM blocks with one combined clock for both SRAM blocks On chip ROM The on chip ROM contains the bootloader and the following Application Programming Interfaces APIs In System Programming ISP and In Application Programming IAP support for flash including IAP erase page command Power profiles for configuring power consumption and PLL settings 32 bit integer division routines e APIs to use the following peripherals SPI USART 12C ADC Memory map The LPC82x incorporates several distinct memory regions Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The ARM private peripheral bus includes the ARM core registers for controlling the NVIC the system tick timer SysTick and the reduced power modes All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 12 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller LPC82x TOB OxFFFF FFFF gt reserved 0xE010 0000 APB peripherals private peripheral bus 0x4008 0000 OxEO000 0000 30 31 reserved 0x4005 0000 oxto04 co00 ur reserved GPIO PINT GPIO 0x4007 8000 0x4007 400
75. input Programmable input digital filter selectable on all pins Analog input Selected through the switch matrix Vpp Vpp open drain enable T strong output enable pull up data output pin configured strong as digital output pull down driver Vss VDD weak E pull up pull up enable repeater mode LOST LE weak enable pull down pull down enable PROGRAMMABLE data input Cf lt 1 DIGITAL FILTER pin configured 9 as digital input select data inverter SWM PINENABLE for analog input analog input pin configured as analog input aaa 014392 Fig 7 Standard I O pad configuration 8 9 Switch Matrix SWM The switch matrix controls the function of each digital or mixed analog digital pin in a highly flexible way by allowing to connect many functions like the USART SPI SCT and I2C functions to any pin that is not power or ground These functions are called movable functions and are listed in Table 4 Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix These functions are called fixed pin functions and cannot move to other pins The fixed pin functions are listed in Table 3 If a fixed pin function is disabled any other movable function can be assigned to this pin LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All right
76. ions Min Typ Max Unit Via analog input voltage 0 Vpp V Viet reference voltage on pin VREFP 24 Vpp V Cia analog input 0 32 pF capacitance folk ADC ADC clock frequency 2 7 V lt Vpp lt 3 6 V 2 30 MHz 2 4 V lt Vpp 2 7 V BI 25 MHz fs sampling frequency 2 7 V lt Vpp lt 3 6 V 2 1 2 Msamples s 2 4 V lt Vpp lt 2 7 V 3 1 Msamples s Ep differential linearity Tamb 105 C SI 2 5 LSB error EL adj integral non linearity Tamb 105 C 6 4 2 5 LSB Eo offset error Tamb 105 C 714 4 5 LSB Verr ts full scale error voltage 1 2 Msamples s Tamb 105 C SIA 0 5 96 Zi input impedance f 1 2 Msamples s 2 0 1 MO 1 The input resistance of ADC channel 0 is higher than for all other channels See Figure 37 2 In the ADC TRM register set VRANGE 0 default 3 Inthe ADC TRM register set VRANGE 1 default 4 Based on characterization Not tested in production 5 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 38 6 The integral non linearity E aq is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 38 7 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight
77. ive input L II2II4 130 ns Vic 1 5 V rail to rail input 2 120 ns Vic 2 9 V 100 mV overdrive input L II2II4 220 ns Vic 2 9 V rail to rail input niz 80 ns tpp propagation delay LOW to HIGH Vpp 3 0 V Tamb 105 C Vic 0 1 V 100 mV overdrive input L II2II4 240 ns Vic 0 1 V rail to rail input IUE 60 ns Vic 1 5 V 100 mV overdrive input L II2II4 160 ns Vic 1 5 V rail to rail input IUE 150 ns Vic 2 9 V 100 mV overdrive input L II2II4 150 ns Vic 2 9 V rail to rail input IUE 260 ns Vhys hysteresis voltage positive hysteresis Vpp 3 0 V 3 Vic 1 5 V Tamp 105 C settings 5mvV 6 mV 10 mv 11 mV 20 mV 23 mV Vhys hysteresis voltage negative hysteresis Vpp 3 0 V pis Vic 1 5 V Tamb 105 C settings 5mV 10 mV 10 mV 15 mV 20 mV 27 mV Riad ladder resistance 1 MQ 1 CL 2 10 pF 2 Characterized on typical samples not tested in production 3 Input hysteresis is relative to the reference input channel and is software programmable 4 100 mV overdrive corresponds to a square wave from 50 mV below the reference Vic to 50 mV above the reference Table 25 Comparator voltage ladder dynamic characteristics Tamb 40 C to 105 C Vpp 1 8 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit ts pu power up settling to 99 of voltage H 17 uS time ladder output value ts sw switching s
78. l with respect to the Vin min of the SCL signal to bridge the undefined region of the falling edge of SCL 5 Cp total capacitance of one bus line in pF 6 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified tr 7 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 8 The maximum typ pat could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ par OF typ Ack by a transition time see UM10204 This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 9 tsu par is the data set up time that is measured with respect to the rising edge of SCL applies to data in 10 LPC82x transmission and the acknowledge A Fast mode I2C bus device can be used in a Standard mode I C bus system but the requirement tsu pAr 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period o
79. l clock for the self wake up timer To use the pin as a self wake up timer clock input select the external clock in the wake up timer CTRL register The external clock input is active in all power modes including deep power down Vpp 15 119 Supply voltage for the I O pad ring the core voltage regulator and the analog peripherals VSS 16 33 Ground VREFN 17 20 ADC negative reference voltage VREFP 18 21 ADC positive reference voltage Must be equal or lower than Vpp 1 Pin state at reset for default function Input Al Analog Input O Output PU internal pull up enabled pins pulled up to full Vpp level IA inactive no pull up down enabled F floating For pin states in the different power modes see Section 14 5 Pin states in different power modes For termination on unused pins see Section 14 4 Termination of unused pins 2 5 V tolerant pin providing standard digital I O functions with configurable modes configurable hysteresis and analog input When configured as an analog input the digital section of the pin is disabled and the pin is not 5 V tolerant LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 9 of 81 NXP Semiconductors LPC82x 3 7 8 9 10 32 bit ARM Cortex M0 microcontroller 5 V tolerant pad pro
80. l disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 13 of 81 NXP Semiconductors LPC82x 8 6 2 8 7 8 8 8 8 1 LPC82x 32 bit ARM Cortex M0 microcontroller Tightly coupled interrupt controller provides low interrupt latency Controls system exceptions and peripheral interrupts Supports 32 vectored interrupts e n the LPC82x the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation using the ARM exceptions SVCall and PendSV Supports NMI Interrupt sources Each peripheral device has at least one interrupt line connected to the NVIC but can have several interrupt flags Individual interrupt flags can also represent more than one interrupt source System tick timer The ARM Cortex MO includes a 24 bit system tick timer SysTick that is intended to generate a dedicated SysTick exception at a fixed time interval typically 10 ms I O configuration The IOCON block controls the configuration of the I O pins Each digital or mixed digital analog pin with the PIOO n designator except the true open drain pins PIOO 10 and PIOO 11 in Table 3 can be configured as follows Enable or disable the weak internal pull up and pull down resistors Select a pseudo open drain mode The input cannot be
81. lt twa DATA VALID LSB J DATA VALID DATA VALID MSB IDLE DATA VALID MSB MISO CPHA 1 S tH DATA VALID LSB DATA VALID DATA VALID MSB IDLE DATA VALID MSB aaa 014969 Tey clk CCLK DIVVAL with CCLK system clock frequency DIVVAL is the SPI clock divider See the LPC82x User manual Fig 34 SPI master timing LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 57 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller SCK CPOL 1 SSEL MISO CPHA 0 MOSI CPHA 0 MISO CPHA 1 MOSI CPHA 1 Fig 35 SPI slave timing iQ gt DATA VALID MSB DATA VALID MSB Toy clk tva DATA VALID LSB DATA VALID LSB SCK CPOL 0 NE EMT E S DATA VALID a DATA VALID DATA VALID MSB DATA VALID MSB DATA VALID MSB DATA VALID MSB DATA VALID MSB aaa 014970 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 58 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 12 3 6 USART interface The maximum USART bit rate
82. luding bonding pad capacitance Based on simulation not tested in production LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 33 of 81 NXP Semiconductors LPC82x 11 2 Supply pins Table8 Static characteristics supply pins Tamb 40 C to 105 C unless otherwise specified 32 bit ARM Cortex M0 microcontroller Symbol Parameter Conditions Min Typ Max Unit Ipp supply current Active mode code while 1 executed from flash system clock 12 MHz default 2J3II4 1 85 mA mode Vpp 3 3 V 617 system clock 12 MHz 2103114 1 04 mA low current mode Vpp 3 3 V eit system clock 30 MHz default BILS 3 95 mA mode Vpp 3 3 V PI system clock 30 MHz 21316 3 2 mA low current mode Vpp 3 3 V 719 Sleep mode system clock 12 MHz default 21 31 4 1 35 mA mode Vpp 3 3 V 617 system clock 12 MHz 2134 0 8 mA low current mode Vpp 3 3 V eit system clock 30 MHz default BINS 2 55 mA mode Vpp 3 3 V 617 system clock 30 MHz 2319 2 1 mA low current mode Vpp 3 3 V et Ipp supply current Deep sleep mode BINO Vpp 3 3 V Tamb 25 C 158 300 uA Tamb 105 C g 400 uA Ipp supply current Power down mode BINO V
83. ment identifier LPC82x
84. n supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG for analog blocks registers All other blocks are disabled in both registers and no code accessing the peripheral is executed Measured on a typical sample at Tamb 25 C Unless noted otherwise the system oscillator and PLL are running in both measurements The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz Table 10 Power consumption for individual analog and digital blocks Peripheral Typical supply current in pA Notes Main clock frequency n a 12 MHz 30 MHz IRC 261 x a System oscillator running PLL off independent of main clock frequency IRC output disabled System oscillator at 12 MHz 274 2 IRC running PLL off independent of main clock frequency Watchdog oscillator 2 System oscillator running PLL off independent of main clock frequency BOD 39 Independent of main clock frequency Main PLL 301 E CLKOUT 67 150 Main clock divided by 4 in the CLKOUTDIV register ROM 27 68 GPIO pin interrupt pattern 95 233 GPIO pins configured as outputs and set to match LOW Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register SWM 59 145 IOCON 45 110 SCTimer PWM 168 411 MRT 89 220 WWDT 29 71 I2C0 54 132 I2C1 4
85. nd National Microwire modes are not supported I2C bus interface 12C0 1 2 3 The I C bus is bidirectional for inter IC control using only two wires a serial clock line SCL and a serial data line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 18 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C is a multi master bus and can be controlled by more than one bus master The I2CO0 bus functions are fixed pin functions All other I2C bus functions for 12C1 2 3 are movable functions and can be assigned through the switch matrix to any pin However only the true open drain pins provide the electrical characteristics to support the full I2C bus specification see Ref 3 8 15 1 Features e 2C0 supports Fast mode Plus with data rates of up to 1 Mbit s in addition to standard and fast modes on two true open drain pins e True open drain pins provide fail safe operation When the power to an I C bus device is swit
86. nd products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or th
87. o select the optimal PLL settings for a given system clock and PLL input clock Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 26 of 81 NXP Semiconductors LPC82x 8 22 6 3 8 22 6 4 8 22 6 5 LPC82x 32 bit ARM Cortex M0 microcontroller In Sleep mode execution of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses Deep sleep mode In Deep sleep mode the LPC82x core is in Sleep mode and all peripheral clocks and all clock sources are off except for the IRC and watchdog oscillator or low power oscillator if selected The IRC output is disabled In addition all analog blocks are shut down and the flash is in standby mode In Deep sleep mode the application can keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection The LPC82x can wake up from Deep sleep mode via a reset digital pins selected as inputs to
88. of the device Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime 8 If the comparator is configured with the common mode input Vic Vpp the other comparator input can be up to 0 2 V above or below Vpp without affecting the hysteresis range of the comparator function 9 Itis recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin 10 Dependent on package type LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 31 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 11 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kQ series resistor 10 Thermal characteristics The average chip junction temperature T C can be calculated using the following equation T Tamo Pa Raga 1 Tamb ambient temperature C Rthj a the package junction to ambient thermal resistance C W e Pp sum of internal and I O power dissipation The internal power dissipation is the product of Ipp and Vpp The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications Table 6 Thermal resistance
89. onductors LPC82x 32 bit ARM Cortex M0 microcontroller Voltage ladder source voltage is selectable from an external pin or the main 3 3 V supply voltage rail Voltage ladder can be separately powered down for applications only requiring the comparator function Interrupt output is connected to NVIC Comparator level output is connected to output pin ACMP_O One comparator output is internally collected to the ADC trigger input multiplexer 8 21 Analog to Digital Converter ADC The ADC supports a resolution of 12 bit and fast conversion rates of up to 1 2 MSamples s Sequences of analog to digital conversions can be triggered by multiple sources Possible trigger sources are the pin triggers the SCT output SCT_OUTS the analog comparator output and the ARM TXEV The ADC includes a hardware threshold compare function with zero crossing detection Remark For best performance select VREFP and VREFN at the same voltage levels as Vpp and Vss When selecting VREFP and VREFN different from VDD and VSS ensure that the voltage midpoints are the same VREFP VREFN 2 VREFN Vpp 2 8 21 1 Features LPC82x 12 bit successive approximation analog to digital converter 12 bit conversion rate of up to 1 2 MSamples s Two configurable conversion sequences with independent triggers Optional automatic high low threshold comparison and zero crossing detection Power down mode and low power operating mode Measurement range VREFN to
90. oniana 17 11 4 Power consumption 000 39 8 14 SPIO Loue henner nee de ee 18 11 5 CoreMark data 0 0 cece eee 45 8 14 1 Features oe pU RE EY ees 18 11 6 Peripheral power consumption 46 8 15 I2C bus interface I2C0 2 8 18 11 7 Electrical pin characteristics 47 8 15 1 Features pr 19 12 Dynamic characteristics Lus 50 8 16 SCTimer PWM 0000 eee eee 19 124 Flash EEPROM memory issus 50 8 16 1 Features Rp rs c uae MARS 19 122 External clock for the oscillator in slave mode 50 8 16 2 SCTimer PWM input MUX INPUT MUX 20 12 3 Internal oscillators 00 51 8 17 Multi Rate Timer MRT 545 Pl 49394 VO PINS 225 usc nrdaniabed seiner teed ts 53 8 17 1 Features ee aon on on on n om on mon 9 on o3 m o3 9 o o3 on 9 on on 21 12 3 2 WKTCLKIN pin wake up clock input HEC 53 8 18 Windowed WatchDog Timer WWDT 21 42 3 3 SCTimer PWM output timing 53 8 18 1 Features pete e e ne eee 21 12 34 on C MMRRRERCENEMFEFEEUN 53 o MEE ud ALL E 21 4285 SPI interfaces cese ene ne 56 8 19 1 Features 00 00 eee eee eee 21 12 3 6 USART Interfac esu ve LLL 59 5 0 Analog comparator SOME edaesdug eitis ee 13 Characteristics of analog peripherals 60 continued gt gt LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved
91. ort pins Conditions Vpp 3 3 V standard port pins Fig 30 Typical pull down current lpp versus input voltage Vi 12 Dynamic characteristics 12 1 12 2 LPC82x Flash EEPROM memory Table 11 Flash characteristics Tamb 40 C to 105 C Based on JEDEC NVM qualification Failure rate lt 10 ppm for parts as specified below Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 111140000 100000 cycles tret retention time powered 10 20 years not powered 20 40 years ter erase time page or multiple 95 100 105 ms consecutive pages sector or multiple consecutive sectors torog programming 21 0 95 1 1 05 ms time 1 Number of program erase cycles 2 Programming times are given for writing 64 bytes to the flash Tamb lt 85 C Flash programming with IAP calls see LPC82x user manual External clock for the oscillator in slave mode Remark The input voltage on the XTALIN and XTALOUT pins must be x 1 95 V see Table 8 For connecting the oscillator to the XTAL pins also see Section 12 2 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 50 of 81 NXP Semiconductors LPC82x 12 3 LPC82x 32 bit ARM Cortex M0 microcontroller Table 12 Dynamic characteristic external clock XTALIN input Tamo 40
92. output 3 SCT OUTA4 O SCT output 4 SCT OUT5 O SCT output 5 l2C1 SDA I O I2C1 bus data input output 12C1_SCL O I2C1 bus clock input output l2C2 SDA I O I2C2 bus data input output 12C2_SCL O I2C2 bus clock input output l2C3 SDA I O I2C3 bus data input output 12C3_SCL O I2C3 bus clock input output ADC_PINTRIGO ADC external pin trigger input 0 ADC_PINTRIG1 ADC external pin trigger input 1 ACMP_O O Analog comparator output CLKOUT O Clock output GPIO_INT_BMAT O Output of the pattern match engine All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 11 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller 8 Functional description LPC82x 8 1 8 2 8 3 8 4 8 5 ARM Cortex M0 core The ARM Cortex MO core runs at an operating frequency of up to 30 MHz using a two stage pipeline The core revision is rOp1 Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints The ARM Cortex M0 core supports a single cycle I O enabled port for fast GPIO access The core includes a single cycle multiplier and a system tick timer On chip flash program memory The LPC82x contain up to 32 KB of on chip flash program memory The flash memory supports a 64 Byte page size with page write and erase On c
93. ply voltages Vpp 10 20 50 80 110 temperature C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 42 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller aaa 013991 IDD pA 2 5 Vpp 3 6 V 3 9 V 1 5 2 4V yj V 0 5 40 WKT running with internal 10 kHz low power oscillator Fig 19 Deep power down mode Typical supply current lpp versus temperature for different supply voltages Vpp internal clock 50 110 80 temperature C aaa 014386 WKT running with external 10 kHz clock Clock input waveform square wave with rise time and fall time of 5 ns Fig 20 Deep power down mode Typical supply current Ipp versus temperature for different supply voltages Vpp external 10 kHz input clock 50 80 110 temperature C All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 43 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller aaa 014388 IDD pA Fig 21 2 5 Vpp 3 6 V 33V 1 5 27V in V 0 5
94. pp 3 3 V Tamb 25 C 1 6 10 uA Tamb 105 C 3 50 uA Ipp supply current Deep power down mode Vpp Bm 3 3 V 10 kHz low power oscillator and self wake up timer WKT disabled Tamb 25 C E 0 2 1 uA Tamb 105 C 4 uA LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 34 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 8 Static characteristics supply pins continued Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Ipp supply current Deep power down mode Vpp 1 1 uA 3 3 V 10 kHz low power oscillator and self wake up timer WKT enabled Deep power down mode Vpp 0 4 uA 3 3 V external clock input WKTCLKIN 10 kHz with self wake up timer enabled Deep power down mode Vpp 0 7 uA 3 3 V external clock input WKTCLKIN 9 32 kHz with self wake up timer enabled 1 Typical ratings are not guaranteed The values listed are for room temperature 25 C nominal supply voltages 2 Tamb 25 C 3 Ibo measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled 4 IRC enabled system oscillator disabled system PLL disabled 5 System oscillator enabled IRC
95. roduct data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 20 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products describ
96. rs N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 5 of 81 NXP Semiconductors LPC82x 7 Pinning information 32 bit ARM Cortex M0 microcontroller 7 1 Pinning PIO0_23 ADC_3 ACMP_14 PIOO 17 ADC 9 PIOO 13 ADC 10 PIOO0 12 RESET PIOO 5 PIOO 4 ADC 11 WAKEUP TRST SWCLK PIOO 3 TCK SWDIO PIOO 2 TMS PIOO 11 I2CO0 SDA PIOO 10 I2CO0 SCL PIOO 14 ADC 2 ACMP I3 OQ TSSOP20 aaa 011391 PIOO0 O0 ACMP I1 TDO VREFP VREFN Vss Vpp PIOO 8 XTALIN PIOO 9 XTALOUT PIOO 1 ACMP I2 CLKIN TDI PIOO 15 Fig4 Pin configuration TSSOP20 package xm aad zz O O Xxx 9 9 1 e j Tj ON OOO00 0 90 Q Cy O 0O GOG O O G O af 2 242 2 2S EPRA ANG el el el el el el eoo terminal 1 9999999 9 D n 0 n n 0 a index area amp 5 8 8 SJ 9 8 9 PIOO 13 ADC 10 1 24 Plo0 o ACMP 1 TDO PIO0_12 D 23 Ploo_6 ADC_1 VDDCMP PIOO_5 RESET 3 22 Plo0 z ADC 0 PIOO 4 ADC 11 TRST 4 21 VREFP PIOO_28 WKTCLKIN 5 20 VREFN SWCLK PIOO 3 TCK 6 19 Voo SWDIO PIOO 2 TMS 7 18 PlO0 8 XTALIN PIOO 11 I2CO SDA 8 17 Ploo_9 XTALOUT eo Oo AA 2 ofAaa ae Oo B ool o o o o E aaa 011396 20000006E Onnnanaaa t S o S ol a e z z 2 Mi o n Transparent top view Fig 5 Pin configuration HVQFN33 package LPC82x All information provided in this document is subject to legal
97. s are available to store information during Deep power down mode The LPC82x can wake up from Deep power down mode via the WAKEUP pin or without an external signal by using the time out of the self wake up timer see Section 8 19 The LPC82x can be prevented from entering Deep power down mode by setting a lock bit in the PMU block Locking out Deep power down mode enables the application to keep the watchdog timer or the BOD running at all times All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 27 of 81 NXP Semiconductors LPC82x 8 23 8 23 1 32 bit ARM Cortex M0 microcontroller When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH Pull the RESET pin HIGH to prevent it from floating while in Deep power down mode System control Reset Reset has four sources on the LPC82x the RESET pin the Watchdog reset power on reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller A LOW going pulse as short as 50 ns resets the part When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from
98. s reserved Product data sheet Rev 1 1 October 2014 15 of 81 NXP Semiconductors LPC82x 8 10 8 10 1 8 11 8 11 1 LPC82x 32 bit ARM Cortex M0 microcontroller Fast General Purpose parallel I O GPIO Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Multiple outputs can be set or cleared in one write operation LPC82x use accelerated GPIO functions e GPIO registers are on the ARM Cortex M0 IO bus for fastest possible single cycle I O timing allowing GPIO toggling with rates of up to 15 MHz Anentire port value can be written in one instruction Mask set and clear operations are supported for the entire port All GPIO port pins are fixed pin functions that are enabled or disabled on the pins by the switch matrix Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin Except for pins SWDIO PIOO 2 SWCLK PIOO 3 and RESET PIOO 5 the switch matrix enables the GPIO port pin function by default Features Bitlevel port registers allow a single instruction to set and clear any number of bits in one write operation Direction control of individual bits e All I O default to GPIO inputs with internal pull up resistors enabled after reset except for the I C bus true open drain pins PIOO 10 and PIOO 11 Pull up pull down configuration repeater and
99. t In ISP mode this pin is the UO TXD pin This pin triggers a wake up from Deep power down mode If the part must wake up from Deep power down mode via an external pin do not assign any movable function to this pin This pin should be pulled HIGH externally before entering Deep power down mode A LOW going pulse as short as 50 ns causes the chip to exit Deep power down mode and wakes up the part A ADC 11 ADC input 11 RESET PIOO 5 5 3 7l i PU IO RESET External reset input A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 In deep power down mode this pin must be pulled HIGH externally The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed and the Deep power down mode is not used PIOO_5 General purpose port 0 input output 5 PIOO 6 ADC 1 23 10 PU IO PIOO 6 General purpose port 0 input output 6 VDDCMP A ADC_1 ADC input 1 A VDDCMP Alternate reference voltage for the analog comparator PIOO 7 ADC 0 22 2 l PU IO PIOO 7 General purpose port 0 input output 7 A ADC_0 ADC input 0 PIO0_8 XTALIN 14 118 8 PU IO PIO0_8 General purpose port 0 input output 8 A XTALIN Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 95 V PIOO 9 XTAL
100. t mode Plus 120 ns on pins PIOO 10 and PIOO 11 LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 53 of 81 NXP Semiconductors LPC82x 32 bit ARM Cortex M0 microcontroller Table 18 Dynamic characteristic I2C bus pins Tamb 40 C to 105 C values guaranteed by design 2 Symbol Parameter Conditions Min Max Unit tLow LOW period of Standard mode 4 7 us the SOE eee Fast mode 1 3 a us Fast mode Plus on 0 5 us pins PIOO 10 and PIOO 11 tHIGH HIGH period of Standard mode 4 0 us the SCL clock Fast mode 0 6 us Fast mode Plus on 0 26 us pins PIOO 10 and PIOO 11 tHD DAT data hold time BIAI Standard mode 0 us Fast mode 0 us Fast mode Plus on 0 us pins PIOO_10 and PIOO 11 tsu DAT data set up 9 10 Standard mode 250 ns time Fast mode 100 ns Fast mode Plus on 50 ns pins PIOO_10 and PIOO 11 1 See the I2C bus specification UM10204 for details 2 Parameters are valid over operating temperature range unless otherwise specified 3 tup par is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 4 A device must internally provide a hold time of at least 300 ns for the SDA signa
101. tion Vesd electrostatic discharge voltage human body model all pins m 3500 V charged device model 1200 V HVQFN33 package 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Maximum minimum voltage above the maximum operating voltage see Table 8 and below ground that can be applied for a short time 10 ms to a device without leading to irrecoverable failure Failure includes the loss of reliability and shorter lifetime of the device cs sux e 6 Vpp present or not present Including the voltage on outputs in 3 state mode Applies to all 5 V tolerant I O pins except true open drain pins PIOO 10 and PIOO 11 and except the 3 V tolerant pin PIOO 6 Vpp present or not present Compliant with the I2C bus standard 5 5 V can be applied to this pin when Vpp is powered down An ADC input voltage above 3 6 V can be applied for a short time without leading to immediate unrecoverable failure Accumulated exposure to elevated voltages at 4 6 V must be less than 108 s total over the lifetime
102. use the IRC as the clock source Software may later switch to one of the other available clock sources Crystal Oscillator SysOsc The crystal oscillator can be used as the clock source for the CPU with or without using the PLL The SysOsc operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL Internal Low power Oscillator and Watchdog Oscillator WDOsc The nominal frequency of the WDOsc is programmable between 9 4 kHz and 2 3 MHz The frequency spread over silicon process variations is 40 The WDOsc is a dedicated oscillator for the windowed WWDT The internal low power 10 kHz 40 accuracy oscillator serves as the clock input to the WKT This oscillator can be configured to run in all low power modes Clock input An external clock source can be supplied on the selected CLKIN pin directly to the PLL input When selecting a clock signal for the CLKIN pin follow the specifications for digital I O pins in Table 8 Static characteristics supply pins and Table 15 Dynamic characteristics I O pinsi An 1 8 V external clock source can be supplied on the XTALIN pins to the system oscillator limiting the voltage of this signal see Section 14 1 The maximum frequency for both clock signals is 25 MHz System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplie
103. viding digital I O functions with configurable pull up pull down resistors and configurable hysteresis This pin is active in Deep power down mode and includes a 20 ns glitch filter active in all power modes In Deep power down mode pulling the WAKEUP pin LOW wakes up the chip The wake up pin function can be disabled and the pin can be used for other purposes if the WKT low power oscillator is enabled for waking up the part from Deep power down mode See Table 16 Dynamic characteristics WKTCLKIN pin for the WKTCLKIN input 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis includes high current output driver 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis True open drain pin 12 C bus pins compliant with the I2C bus specification for I2C standard mode 2C Fast mode and 12C Fast mode Plus Do not use this pad for high speed applications such as SPI or USART The pin requires an external pull up to provide output functionality When power is switched off this pin is floating and does not disturb the 12C lines Open drain configuration applies to all functions on this pin See Figure 10 for the reset pad configuration This pin includes a 20 ns glitch filter active in all power modes RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake
104. x 32 bit ARM Cortex M0 microcontroller 4 aaa 013993 e 30 MHz 24 MHz mA 12 MHz 6 MHz 4 VIZ 3 MHz 2 MHz 1 MHz 2 0 40 10 60 110 temperature C Conditions Vpp 3 3 V active mode entered executing code while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 MHz 6 MHz external clock IRC PLL disabled 12 MHz IRC enabled PLL disabled 24 MHz IRC enabled PLL enabled 30 MHz system oscillator enabled PLL enabled Fig 14 Active mode Typical supply current lpp versus temperature LPC82x All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 1 1 October 2014 40 of 81 NXP Semiconductors LPC82x LPC82x 32 bit ARM Cortex M0 microcontroller aaa 013994 a 30 MHz 24 MHz mA wie 2 6 MHz 4 MHz 3 MHz ee ee e 1 5 1 MHz 1 0 5 0 40 10 60 110 temperature C Conditions Vpp 3 3 V sleep mode entered from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled low current mode 1 MHz 6 MHz external clock IRC PLL disabled 12 MHz IRC enabled

LPC82x - NXP Semiconductors

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