Hardware User`s Manual - Everest Pacific Group
Contents
1. Hardware User s Manual Table of Contents 1 Hardware Accessories 2 MCU models that it can support 3 Installation 4 Manual for Panel Use Rev 1 1 1 Hardware Accessories 1 1 ICE 1 set 1 2 TM8795 Writer Board 1 set 1 3 DC Adapter 1 pcs 1 4 Printer port cable 1 pcs 1 5 Bus line 16pin 1 pcs 1 6 Bus lines 40pin 2 pcs 1 7 Installation CD 1 pcs 1 8 One copy of hardware installation 2 MCU Models that it can support This development can support the following 4bit MCU products TM8704 TM8705 TM8706 TM8712 TM8713 TM8740 note 1 TM6811 TM6814 TM6820 TM6840 TM6841 TM8795 note 2 Note 1 If clients need to develop TM8740 products the products have to be used together with TX9010 EV Board For details please contact our sales department Note 2 TM8795 is a OPT product the products have to be used together with TM8795 Writer Board 2 Rev l l 3 Installation 3 1 Step1 Please make sure the printer port on the computer is set to be EPP Mode 3 2 Step2 Connect printer port cable to the computer and the printer port on ICE as shown in Figure 1 Figure 1 3 3 Step3 Insert the DC Adapter to ICE as shown in Figure 2 Figure 2 3 4 Step4 Turn Power switch to ON position 3 5 Hardware is installed on your computer successfully 3 5 Now you can start to install software First put the CD disk into the computer Then follow the instructions to install software Application Aft2. ar f j 1 j Figure 6 5 Rev 1 1 3 External pins for External clock Fast R and Slow R amp C Note 1 3 1 Example Refer to Figure 7 for the way of connecting Fast R pin Figure 7 3 2 Example Refer to Figure 8 for the way of connecting Slow R amp C pin Figure 8 4 RFC external pins RR RT RH and CX 4 1 Example Refer to Figure 9 for the way of connecting RR RT RH and CX pin Figure 9 6 Rev 1 1 5 Reset INT buttons 5 1 Reset chip reset request signal 5 2 INT External interrupt request signal 5 3 For details please refer to each Chip user s manual 6 LED Status Display Hi gt ON Lo gt OFF o 000 889 VDDC ICE POWER ON Hi OFF Lo ECSF Fast Slow clock status Fast Hi Slow Lo OU STACK Over Underflow status STACK Over Underflow Hi normal Lo HALT HALT status HALT mode Hi HALT release Lo STOP STOP status STOP mode Hi HALT release Lo STEP Free run Single step status Free run Lo Single step Hi MATCH Compare H W swl sw2 sw3 setup with S W opt file setup the same Hi TCK2 ICE CONF These three LED statuses are for engineering certification Therefore clients do not need to pay attention to them 7 EXT V VDDC GND 7 1 EXT V External VDDO pin Note 2 7 2 VDDC 5 voltage 7 3 GND ground 8 DC IN 9V DC input 9 Printer port connect PC 10 Power switch 7 Rev 1 1 11 JP7 TM8740 Bus line for externally connected bo
3. ards Please refer to Figure 9 Figure 9 12 JP10 TM8740 Bus line for externally connected boards Please refer to Figure10 Note 3 TIE RES Su at TUB 8 Rev 1 1 Tablel POWER SETTING SW1 of VDDO settint Table2 CUPO CUP2 CAP SETTING Doo fo o o ass o 0 1 am Cissus 0 0 41 4 Table3 VDD1 VDD4 CAP SETTING a To ao ENEN KEN av ie lo ao av is lo To fa avi lo Cl note ON O OFF o ER 9 Rev 1 1 Note 1 Note 2 Note 3 Under Debug mode step go all clocks are provided from ICE internal Therefore the external clock will only work during the execution of Free run mode It has to match SW1 and be adjusted to EXT V for the program to work TM8795 Writer Board Use a The bus line 16pin connect JP1O TICE87NB to JP1 TM8795 Writer Board b The JP2 signal connect to TM8795 OTP c Hardware finish 10 Rev 1 1
4. er the completion the operation may begin 3 Rev 1 1 4 Manual for Panel Use tenx technology Inc gt TICE87NB D sA o Sonn cas o DOC ESF OU HAT STOP TCR2S TEP ICE MATCH CONF Figure 3 PRINTER PORT To DC IN 9V 4 Rev l l 1 SW1 SW2 SW3 4 SWI setting the work voltage of chip and please refer the details to Table 1 SW2 setting LCD BIAS please refer the details to Table 2 SW3 setting LCD Pump voltage please refer the details to Table3 Example If the setting of the opt file from the clients is operating voltage of 3v and 1 4BIAS the setting of SWI SW2 and SW3 should be like Figure 5 89 Figure 3 2 JP8 JP9 connecting to external testing boards or LCD panel signal Please refer to Figure 6 LA ENE EN O ET GA EC CU imt CIA kun E Eis IE gt ia or o e NG pd 4 of o i E MR yas Pa PEK p a kor O pony do h 7 Meret tng RA a REAT na at ie a ae Pee 5 ki bh 3 ik i 1 i CAB j F Na Ed Ss O Cl dk fd Bo ch da Ia sa da h Co pa 23 L bi ne had etm ee Fo z i Pa Ng o z 7 a PAG CG ITS Pal owt 0 IN Ls Joe PR A Na NG ma 7 bUGRERSHEEERSNEGRMEEEGES RS LI CIA III Re NOS pa NAG Cara DE y a T ER i 5 DAA Eton Pali et Ni UN DN pm ft 2 ae a PATE LPA IA ee eee aye aM vets sa kay ALNG NG d at ae E MA Pal 7 ke Rs KS id ls Ku Ka Ls 3 bm a Lo rane i eric hs dah a an AK A BA ree prea nain Po ee ee RE P
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