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i.MX31ADS Application Development System User`s Manual

1. 6 37038 DO GND 39 40 GND GND 4142 GND GND 43 Figure 4 27 Address Connector P10 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary 4 52 Freescale Semiconductor ADS Connectors and Signals Table 4 35 Address Connector P10 Signal Description Pin Signal Description 1 TP38 TEST POINT 38 2 TP40 TEST POINT 40 3 GND SIGNAL GROUND 4 TP39 TEST POINT 39 5 BRW_B BUFFERED READ WRITE 6 BBCLK BASE BOARD CLOCK 7 RST_OUT_B RESET OUT Active low reset signal from the MCU 8 B_A15 BUFFERED ADDRESS 15 9 BCS4_B BUFFERED CHIP SELECT 4 10 B_A14 BUFFERED ADDRESS 14 11 BCS1_B BUFFERED CHIP SELECT 1 12 B_A13 BUFFERED ADDRESS 13 13 TP37 TEST POINT 37 14 B_A12 BUFFERED ADDRESS 12 15 TP36 TEST POINT 36 16 B_A11 BUFFERED ADDRESS 11 17 TP34 TEST POINT 34 18 B_A10 BUFFERED ADDRESS 10 19 B_A25 BUFFERED ADDRESS 25 20 9 BUFFERED ADDRESS 9 21 B_A24 BUFFERED ADDRESS 24 22 8 BUFFERED ADDRESS 8 23 B_A23 BUFFERED ADDRESS 23 24 B_A7 BUFFERED ADDRESS 7 25 B_A22 BUFFERED ADDRESS 22 26 B_A6 BUFFERED ADDRESS 6 27 B_A21 BUFFERED ADDRESS 21 28 B_A5 BUFFERED ADDRESS 5 29 B_A20 BUFFERED ADDRESS 20 30 B_A4 BUFFERED ADDRESS 4 31 B_A19 BUFFERED ADDRESS 19 32 B_A3 BUFFERED ADDRESS 3 33 B_A18
2. Pin Signal Description Al GND SIGNAL GROUND A2 EXT_CSI_D8 CMOS SENSOR INTERFACE DATA 8 Image Sensor input data A3 EXT_CSI_D10 CMOS SENSOR INTERFACE DATA 10 Image Sensor input data A4 EXT_CSI_D12 CMOS SENSOR INTERFACE DATA 12 Image Sensor input data A5 EXT_CSI_D14 CMOS SENSOR INTERFACE DATA 14 Image Sensor input data A6 EXT_CSI_PIXCLK CMOS SENSOR INTERFACE PIXEL CLOCK Data latch strobe A7 EXT_CSI_VSYNC CMOS SENSOR INTERFACE VERTICAL SYNC Control input A8 CSI_SCL CMOS SENSOR INTERFACE SERIAL CLOCK Serial clock bidirectional AQ CSI_CS1 CMOS SENSOR INTERFACE CHIP SELECT 1 Control signal bidirectional A10 CSI_CS2 CMOS SENSOR INTERFACE CHIP SELECT 2 Control signal bidirectional 11 12 A13 NC NO CONNECTION A14 B14 Wired connection A15 NC NO CONNECTION A16 3V3 3 VDC power B1 GND SIGNAL GROUND B2 NC NO CONNECTION B3 NC NO CONNECTION B4 EXT_CSI_D2 CMOS SENSOR INTERFACE DATA 2 Image Sensor input data B5 EXT_CSI_D3 CMOS SENSOR INTERFACE DATA 3 Image Sensor input data B6 EXT_CSI_D4 CMOS SENSOR INTERFACE DATA 4 Image Sensor input data B7 EXT_CSI_D5 CMOS SENSOR INTERFACE DATA 5 Image Sensor input data B8 EXT_CSI_D6 CMOS SENSOR INTERFACE DATA 6 Image Sensor input data B9 PM_VCAM POWER MANAGER VIDEO CAMERA B10 PM_VCAM POWER MANAGER VIDEO CAM
3. Signal Pin Description PWGT1_OUT 73 POWER MANAGEMENT PWGT1_OUT 75 POWER MANAGEMENT PWGT2_EN 169 POWER GATE 2 ENABLE PWGT2_OUT 45 POWER MANAGEMENT PWGT2_OUT 47 POWER MANAGEMENT PWR FAIL 181 POWER FAILURE RST OUT B 167 RESET OUT Active low reset signal from the MCU SCK3 15 Audio Port 3 Serial clock SCK6 11 Audio Port 6 Serial clock SCLKO 147 Audio Port 0 Serial clock SFS3 19 Audio Port 3 Frame Sync SFS6 9 Audio Port 6 Frame Sync SIMPDO 145 SIM CARD PRESENCE DETECT SRSTO 139 Audio Port 0 RESET SRXDO 137 Audio Port 0 RECEIVE DATA SRXD3 17 Audio Port 3 RECEIVE DATA SRXD6 7 Audio Port 6 RECEIVE DATA STXDO 143 Audio Port 0 TRANSMIT DATA STXD3 21 Audio Port 3 TRANSMIT DATA STXD6 5 Audio Port 6 TRANSMIT DATA SVENO 141 SIM CARD VCC Enable Port 0 USBH2_CLK 59 USB HOST CLOCK USBH2_DATAO 65 USB HOST DATA USBH2_DATA1 63 USB HOST DATA USBH2_DIR 55 USB HOST DIRECTION USBH2_NXT 51 USB HOST NEXT USBH2_STP 53 USB HOST STOP VSTBY 171 STANDBY VOLTAGE WATCHDOG_RST 179 WATCHDOG RESET M9328MX31ADS User s Manual Rev 1 Preliminary 4 14 Freescale Semiconductor 4 2 2 Base Board to MC13783 Board Connectors ADS Connectors and Signals ADS Base board connectors P5 and P6 mate with MC13783 board connectors J5 and J6 bottom side Figure 4 4 shows connector pin assignments Table 4 5 describe connector signals NC GND NC NC NC NC NC NC NC NC GND NC GND NC NC NC GND NC
4. 4 43 CE Bus Connector J19 Signal 4 44 SD MMC Connector Signal Description 4 45 SD MMC Connector Signal 4 45 PCMCIA Connector 030 Signal 4 46 SIMM Socket P8 Signal Description 4 47 Baseband Board Connector J24 Signal 4 49 Software Analysis Connector P9 Signal 4 51 Address Connector P10 Signal Description 4 53 CPLD Programming Connector J14 Signal 4 54 GPU Board C RR RR BREDA ES 4 55 Logic Analyzer Connector P2 Signal Description 4 58 Logic Analyzer Connector Signal Description 4 60 Logic Analyzer Connector P5 Signal Description 4 62 Logic Analyzer Connector Signal Description 4 64 Primary ETM Connector Signal 4 66 Alternate ETM Connector Signal 4 68 RV ICE JTAG Connector J8 Signal Description 4 69 PC Te
5. seater OE DENDUM 3 5 3 3 5 CPLD Memory Map eet iss BESS eee aS REESE 3 6 3 3 6 Register Descriptions 422 3 6 3 3 61 Version Bee ee EA RR 3 6 3 3 6 2 Board Status Register 1 3 7 3 3 6 3 Board Status Register 2 5 2 3 8 3 3 6 4 Board Control Register set EET es 3 9 3 3 6 5 Board Control Register 2 BCT REZ 3543 wild a Re SR S M e 3 10 3 3 6 6 Board Control Register 3 BC ERE 7 EY ER e 3 12 3 3 6 7 Board Control Register 4 3 13 3 3 6 8 Interrupt Status Clear Register 5 3 13 3 3 6 9 Interrupt Signal Status Register 55 3 14 3 3 6 10 Interrupt Mask Register IMR ERS BS 3 15 3 4 GPIO Interrupt Grouping and Non registered 3 15 3 5 On Board Memorya iae seu Peau esp ad 3 17 35 0 Deme i use ite bur a Pie en Mea 3 18 3 7 USB On The Go Interface 3 19 3298 USBOn The Go ULPIInterface HS ee uda ee ex 3 19 52 TDUSBHOSTULPLInetace HS
6. i MX31 3 UARTA TXD UART1 EN UARTA_RXD UARTA_CTS UARTS UARTA_RTS DTE UARTA_DTR DTR_DTE1 UARTA_DSR DSR_DTE1 UARTA_DCD DCD DTE1 UARTA RI RI DTE1 RS232 Transceiver uaRTA Mop EN 8 UARTA 5 UARTC_TXD EN dun UARTC_RXD U UARTC_CTS x UART1 UABIG RIS DCE UARTC DTR DTR DCE1 B UARTC DSR DSR DCE1 UARTC_DCD DCD DCE1 UARTC_RI RI_DCE1 R RS232 Transceiver EnB UARTC 5 UARTB_TXD EN als UARTB_RXD UARTB_CTS UART4 DTE RS232 Transceiver UART B UART2_TXD UART2_RXD IrDA MODE FIR EN B Figure 3 18 UARTs and IrDA Interface i MX31ADS User s Manual REV 1 Preliminary 3 22 Freescale Semiconductor ADS Operation 3 12 Ethernet Interface The ADS is equipped with a Cirrus Logic CS8900A Crystal LAN ISA Ethernet Controller The CS8900A has 10BaseT transmit and receive filters The interface can operate in interrupt driven mode and perform DMA transfers Chip select function is controlled by CPLD logic Figure 3 19 shows the Ethernet interface CS8900A CPLD_PBAO SAO B_A 11 0 SA 12 1 SA 19 13 B_D 15 0 SD 15 0 Isolation CPLD_AEN AEN Transformer CPLD_IOR_B IOR CPLD_IOW_B in IOW RXD CPLD_MEMR_B MEMR RJ45 Connector CPLD_MEMW_B MEMW SBHE CPLD ENET CSEL _ _ CHIPSEL ENET INT B c ENET_DMAREQ lt NVRAM DI li EEDATAIN NVRAM DO 40 EEDATAOUT
7. 4 50 4 2 21 2 Address que eb 4 50 4 2 21 3 CPLD Programming Connector se dor ed n E Pade EHE Fea ltd d 4 50 4 2 21 4 One wire EEPROM 4 50 4 3 CPI Board oes oom ucro ets as d Raa Ue 4 55 4 3 1 Logic Analyzer Connectors DRIVEN v eee RSREISED S 4 56 4 3 2 RE er LER I COS 4 65 4 3 3 her eek A 4 69 4 3 4 o ee o adve die reae ise ed e MISSE S 4 70 4 3 5 In circuit Serial Programming 1 4 71 4 3 6 NAND Fl sh Connectors ae tac i hue be 4 71 4 3 7 Memory Stick Connectors 220 ave e edt ily qt nan T E Rd 4 73 4 3 8 Subminiature Clock Connectors us Ehe 4 73 4 3 9 Power Connectors casos vex RO Dp BRE NW v eR eV dr eS 4 73 44 IMCS Board Connectors E VN Rice esa dads Ter e eR t Cet 4 74 4 4 1 P wet Connectotss ten e Ep ent 4 75 4 4 2 s tt oak dera csi 4 75 4 4 2 1 Miniature Audio Jacks du aee s ete os Lese h
8. A parallel port and a Multi ICE device not included e A 5 VDC 2 4 A power supply with 2 mm female inside positive power connector included CAUTION Never supply more than 5 5 volts power to the 1 MX31ADS Doing so can damage board components 14 ADS Specifications Table 1 1 shows 1 MX31ADS specifications Table 1 1 Specifications Characteristic Specifications Clock speed Selectable 32 768 kHz or 26 MHz Temperature Operating 10 to 50 C Storage 40 to 85 C Relative humidity 0 to 90 noncondensing Power requirements 4 5V tO 5 5 VDC 2 4 A Dimensions 10 75 x 11 875 in 273 mm x 302 mm i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor Configuring and Connecting the ADS Chapter 2 Configuring and Connecting the ADS 2 1 Introduction This section contains configuration information connection descriptions and other operational information that may be useful during the development process 2 2 Base Board Configuration 2 2 1 Base Board Configuration Switches The Base board has one four switch DIP module SW1 and two eight switch DIP modules SW2 and SW3 Figure 2 1 shows the location of the switches 25 444 H y Figure 2 1 Base Board Configuration Switches 2 2 1 1 SW1 UART Enable Switches Table 2 1 shows SW1 switch functions Each ADS UART transceiver can be connected to two differ
9. 28 LED MD2 29 30 LED MD4 31 32 GND 33 34 LED 35 e 36 DVDD 1 8V 37 e 38 GPIO1 39 e 40 IPU_LDO IPU_LD2 IPU_LD4 IPU_LD17 IPU LD7 IPU PAR RST IPU WR 3V3 IPU_LD10 GND IPU LD12 IPU LD14 IPU LD16 PM VBLITE LED MD3 NC CVDD 2 775V NC NVCC7 GPIO2 Figure 4 9 Parallel LCD Connector I J9 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary 4 30 Freescale Semiconductor ADS Connectors and Signals Table 4 13 Parallel LCD Connector I J9 Signal Description Pin Signal Description 1 VSYNCHO VERTICAL SYNCH 0 2 IPU LDO LCD DATA 0 3 IPU LD1 LCD DATA 1 4 IPU LD2 LCD DATA 2 5 IPU LD3 LCD DATA 3 6 IPU_LD4 LCD DATA 4 7 IPU_LD5 LCD DATA 5 8 IPU_LD17 LCD DATA 17 9 IPU LD8 LCD DATA 8 10 IPU LD7 LCD DATA 7 11 IPU LD6 LCD DATA 6 12 PAR RESET PARALLEL INTERFACE RESET 13 LCDRSTO LCD RESET 0 14 IPU WR PARALLEL INTERFACE WRITE 15 IPU LD9 LCD DATA 9 16 3V3 3 VDC SUPPLY 17 IPU_LD11 LCD DATA 11 18 IPU_LD10 LCD DATA 10 19 IPU_LD13 LCD DATA 13 20 GND SIGNAL GROUND 21 IPU_LD15 LCD DATA 15 22 IPU_LD12 LCD DATA 12 23 IPU_LCSO LCD CHIP SELECT 24 IPU_LD14 LCD DATA 14 25 IPU RD PARALLEL INTERFACE READ 26 IPU LD16 LCD DATA 16 27 LED MD1 MAIN DISPLAY LIGHT EMMITING DIODE 28 PM VBLITE LCD PANEL BACKLIGHT VOLTAGE 29 LED MD
10. AOA Gl 2 1 2 2 BaseB ard Confeuratlob ss eaae sa ve celeste Fatal ha ue abe eet ed Ca a 2 1 2 24 Configuration edu eb d Tw be e e Ra X SS STER 2 1 2 2 1 1 SWI UART Enable Switches 2 1 221 2 SW2 RS 232 MBaud Shut Down WDI and Buzzer Enable Switches 2 2 2 2 1 3 SW3 User Defined 5 2 3 222 J ttpet Headers aeu ce d qu 2 3 2 3 Board Configuration pertapan oh Ree paces 2 7 2 3 1 Mg saat decd ee beta 2 7 2 3 1 1 Sl 2 7 2 3 1 2 SW cease Paha GROW 2 7 2 3 1 3 SW2 Mode Switches 2 8 2 3 1 4 SW2 Power On Reset Switch n Are 2 8 2 3 1 5 SW2 Reset Out Switch 22525244508 ROC nm AC GR qe RR Da PUR ee oes 2 8 2 3 1 6 5W2 Tamper Detect Switch is ER ee ha C epi d 2 8 222 Jumper Headers Sis ouo eee a d rd 2 8 23 5 arce cuoi tue a tsa cen e A 2 11 2 4 1 CC PETAT 2 11 2 4 1 1
11. CSPI signal bidirectional CSPI1_SS1 33 SLAVE SELECT 1 CSPI signal bidirectional CSPI1_SS2 31 SLAVE SELECT 2 CSPI signal bidirectional CVDD_2 775V 153 155 2 775 VDC SUPPLY CVDD_2 7V 91 93 2 7 VDC SUPPLY DVDD_1 8V y 88 1 8 VDC SUPPLY DVS SW1A 165 CONDITIONED POWER SUPPLY FROM PM DVS SW1B 161 CONDITIONED POWER SUPPLY FROM PM DVS SW2A 163 CONDITIONED POWER SUPPLY FROM PM DVS SW2B 159 CONDITIONED POWER SUPPLY FROM PM 13 23 52 64 57 61 83 87 96 97 107 135 GND 136 138 SIGNAL GROUND 160 164 175 180 191 215 166 GENERAL PURPOSE GPIO1_1 168 GENERAL PURPOSE I O GPIO1_2 170 GENERAL PURPOSE I O GPIO1_3 172 GENERAL PURPOSE I O GPIO1_4 174 GENERAL PURPOSE I O M9328MX31ADS User s Manual Rev 1 Preliminary 4 12 Freescale Semiconductor Table 4 3 Base Board to CPU Board Connector P2 Signal Description continued ADS Connectors and Signals Signal Pin Description GPIO1_5 176 GENERAL PURPOSE I O GPIO1 6 178 GENERAL PURPOSE I O KPCOLO 119 KEYPAD COLUMN SELECT KPCOL1 121 KEYPAD COLUMN SELECT KPCOL2 123 KEYPAD COLUMN SELECT KPCOLS3 125 KEYPAD COLUMN SELECT KPCOL4 127 KEYPAD COLUMN SELECT KPCOL5 129 KEYPAD COLUMN SELECT KPCOL6 131 KEYPAD COLUMN SELECT KPCOL7 133 KEYPAD COLUMN SELECT KPROWO 120 KEYPAD ROW SELECT KPROW1 122 KEYPAD ROW SELECT KPROW2 1
12. Connectors ence d du 3 27 Using the Samtec Logic Analyzer 3 28 Chapter 4 ADS Connectors and Signals 4 1 IS CIOCUON od n ees oe LA s eui ue d SEES 4 1 4 2 Base Board Connectors 2 9224 vu Xu buta 24 ex 4 1 4 2 1 Base Board to CPU Board 4 5 4 2 2 Base Board to MC13783 Board Connectors 4 15 4 2 3 Image Sensor and Extension 4 20 4 2 4 External Keypad Connector 95544 S Teu MEN 4 26 4 2 5 Display RUNS CERE REEL EE AS 4 28 4 2 5 1 Synchronous LCD Connector 4 28 4 2 5 2 Option Connectors ot eese de een teen kek Rae 4 29 4 2 5 3 Parallel LCD enneCtors 24 52 d reae doy 4 30 4 2 5 4 Serial Asynchronous LCD Connector 4 33 4 2 6 he ea its ur duct a dua 4 34 4 2 7 PUIG Connectors cohetes rats utra Sees S oa dn didus 4 35 4 2 7 1 Miniature Audio J36ks WR STORE RR 4 35 4 2 7 2 Speaker Terminals C e 4 35 4 2 8 Television Pucoder Connect
13. 25 e 26 LDO BO LD7 G1 27 e 28 LD6 GO LD183 R1 29 30 1012 RO TOP 31 e e 32 BOTTOM LEFT 33 34 RIGHT Figure 4 7 Synchronous LCD Connector J12 Pin Assignment Table 4 11 Synchronous LCD Connector J12 Signal Description Pin Signal Description 1 VCC 3 VDC POWER 2 GND SIGNAL GROUND 3 OE_ACD OUTPUT ENABLE ALTERNATE CRYSTAL DIRECTION 4 FLM_VSYNC_SPS FIRST LINE MARKER VERTICAL SYNCHRONIZATION 5 LP_HSYNC LINE PULSE HORIZONTAL SYNCHRONIZATION 6 LSCLK LCD SHIFT CLOCK Output to LCD 7 LD5_B5 LCD DATA 5 BLUE BIT 5 Output data to LCD 8 LD4_B4 LCD DATA 4 BLUE BIT 4 Output data to LCD 9 LD3_B3 LCD DATA 3 BLUE BIT 3 Output data to LCD 10 LD2_B2 LCD DATA 2 BLUE 2 Output data to LCD 11 LD11_G5 LCD DATA 11 GREEN 5 Output data to LCD 12 LD10_G4 LCD DATA 10 GREEN BIT 4 Output data to LCD 13 LD9_G3 LCD DATA 9 GREEN BIT 3 Output data to LCD 14 LD8_G2 LCD DATA 8 GREEN BIT 2 Output data to LCD 15 LD17_R5 LCD DATA 17 RED BIT 5 Output data to LCD 16 LD16_R4 LCD DATA 16 RED BIT 4 Output data to LCD 17 LD15_R3 LCD DATA 15 RED BIT 3 Output data to LCD 18 LD14_R2 LCD DATA 14 RED BIT 2 Output data to LCD M9328MX31ADS User s Manual Rev 1 Preliminary 4 28 Freescale Semiconductor ADS Connectors and Signals Table 4 11 Synchronous LCD Connector J12 Signal D
14. 98 2 2 E 8112112 E CONN UARTA DTE PCMCIA d BASEBAND CONN COME CARD 5 5 8S zARPICE o n 2 SLOT 8118115 amp SPK CONN UARTB DTE Figure 3 1 ADS Functional Block Diagram i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ADS Operation 3 2 ADS Memory Table 3 1 shows the memory map for the ADS None of the memories take up the entire address space of the associated chip selects software can access the same physical memory location at more than one range of addresses For instance DDR SDRAM occupies only 128MB of the 256MB space available to CSD0 so it appears in two different ranges of addresses Table 3 1 ADS Memory Map Peripheral Chip Select Address Range HEX DDR SDRAM CSDO 52 0x8000_0000 to Ox8FFF_FFFF 128M BYTES Burst FLASH cso 0xA000_0000 to OxA7FF_FFFF 32M BYTES CS5 0 60 0000 to OxB7FF_FFFF 16M BYTES Ethernet Controller 54 0 402 0000 to 0xB402_FFFF 64K BYTES External DUART cs4 0xB401_0000 to 0xB401_001F 32 BYTES YMU782B synth 54 0 403 0000 to OxB403 0004 2 BYTES CPLD amp MMIO C84 0xB400_0000 to 400 00IC 58 BYTES For I O operations only D 15 0 are used i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ADS Operation 3 3 Peripheral Bus Control CPLD The ADS requires glue logic for peripheral bus address decoding board
15. Freescale Semiconductor ADS Connectors and Signals 4 2 9 ATA Drive Controller Connector J3 is a 44 pin 2 row keyed header with 2 mm pin spacing It supports connection of small form factor ATA HDDs Figure 4 15 shows pin assignments and Table 4 19 describes the signals J3 3V3 1 2 GND ATA_D7 3 4 _ 8 ATA_D6 5 e 6 ATA D9 ATA D5 7 8 D10 ATA_D4 9 10 ATA D11 ATA_D3 11 12 ATA D12 02 13 e 14 D13 ATA Di 15 16 ATA_D14 ATA DO 17 e 18 D15 GND 19 e 20 NC ATA_DMARQ_B 21 22 GND ATA DION B 23 e 24 GND ATA DIOR 25 e e 26 GND ATA IORDY 27 28 CSEL ATA DMACK 29 e 30 GND ATA INTRO 31 e e 32 ATA IOCS16 DA1 33 e e 34 CBLID B ATA 35 e e 36 DA2 ATA 50 37 38 51 B DASPB 39 40 GND 3V3 411 42 3V3 GND 43 e 44 NC Figure 4 15 ATA Connector J3 Pin Assignment Table 4 19 ATA Connector J3 Signal Description Pin Signal Description 1 3V3 3 VDC POWER 2 GND SIGNAL GROUND 3 ATA_D7 ATA DATA 7 4 ATA_D8 ATA DATA 8 5 ATA_D6 ATA DATA 6 6 ATA_D9 ATA DATA 9 7 ATA_D5 ATA DATA 5 8 ATA_D10 ATA DATA 10 9 ATA_D4 ATA DATA 4 10 ATA_D11 ATA DATA 11 11 ATA_D3 ATA DATA 3 12 ATA_D12 ATA DATA 12 13 ATA_D2 ATA DATA 2 14 ATA_D13 ATA DATA 13 M9328MX31ADS User s Manual Rev 1 Preliminary
16. i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ADS Operation 3 5 On Board Memory The ADS has several on board memory devices A single MCP contains both a 16M x 16 Burst NOR Flash and an 8M x16 Burst PSRAM see Figure 3 12 The ADS is also equipped with 32M x 32 of DDR SDRAM see Figure 3 13 made up from two 32M x 16 parts A plug in card with 1G bit storage capacity and an 8 bit data bus interface is also included It is described later in this chapter Voc 8MX16 Bit Burst Flash 25 0 BCLK OE B OE RST OUT B RST D 15 0 D 15 0 CS5 B 8MX16 Bit PSRAM Figure 3 12 Burst Flash and PSRAM Interface i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 17 ADS Operation 32Mx16 Bit SDRAM CSDO B CS2 B SDCKEO SDCLK SDCLK B RAS B CAS B SDWE B SDA 13 0 MA10 SDBAO SDBA1 DQM1 DSQO DSQ1 SD 15 0 SD 31 16 DQM2 0502 0503 32Mx16 Bit SDRAM cs CKE CLK CLK RAS CAS WE A 13 0 10 BAO BA1 LDM UDM 1005 UDQS DQ 15 0 DQ 31 16 Figure 3 13 DDR SDRAM Interface 3 6 Using a NAND Flash Card CAUTION To avoid circuit damage do not plug in the NAND Flash card with power applied to the board Your i MX31 ADS comes with NAND Flash card installed Should it ever be removed connect P1 of the NAND Flash module to J9 on the CPU board Screws have been ad
17. 70 72 74 76 78 80 96 NC 98 100 110 NOT CONNECTED 116 118 120 122 146 148 152 153 156 157 159 160 162 166 169 170 172 176 178 184 186 188 190 201 111 113 115 PM_SW1A 117 119 121 SWITCHER OUTPUT PM_SW1B 147 149 151 SWITCHER OUTPUT PM_VDIG 97 99 VOLTAGE REGULATOR OUTPUT PM_VIOHI 61 63 65 VOLTAGE REGULATOR OUTPUT PM_VIOLO 53 55 57 VOLTAGE REGULATOR OUTPUT PM_VRF_CP 168 VOLTAGE REGULATOR OUTPUT PM_VRF_REF 112 114 REGULATOR REFERENCE VOLTAGE PM_VUSB_3V 33 36 37 VOLTAGE REGULATOR OUTPUT Table 4 5 Base Board to MC13783 Board Connector P6 Signal Description Signal Pin Description 5V 72 74 76 5V INPUT ADIN4 37 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN5 39 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN6 43 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN7 47 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN8 51 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN9 55 GENERAL PURPOSE ANALOG TO DIGITAL INPUT ADIN10 59 GENERAL PURPOSE ANALOG TO DIGITAL INPUT M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 5 Base Board to MC13783 Board Connector P6 Signal Description continued Signal Pin Description ADOUT 99 GENERAL PURPOSE ANALOG TO DIGITAL OUTPUT ADTRIG 60 ANALOG TO DIGITAL TRIGGER ATLAS_IN 38 MC13783 IN I
18. J20 ON1 B 1 2 LEDR1 ON2_B 3 4 LEDR2 ON3_B 5 6 LEDR3 NC 7 8 LEDG1 PM_VBLITE 9 10 LEDG2 NC 11 e 12 LEDG3 GND 13 14 LEDB1 LEDB3 15 e 16 LEDB2 Figure 4 12 Funlight Connector J20 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary 4 34 Freescale Semiconductor ADS Connectors and Signals Table 4 16 Funlight Connector J20 Signal Description Pin Signal Description 1 ON1_B ON FUNLIGHT 1 2 LEDR1 LED 1 RED SEGMENT ON 3 ON2 B ON FUNLIGHT 2 4 LEDR2 LED 2 RED SEGMENT ON 5 B ON FUNLIGHT 3 6 LEDR3 LED 3 RED SEGMENT ON 7 NC NO CONNECTION 8 LEDG1 LED 1 GREEN SEGMENT ON 9 PM_VBLITE LCD PANEL BACKLIGHT VOLTAGE 10 LEDG2 LED 2 GREEN SEGMENT ON 11 NC NO CONNECTION 12 LEDG3 LED 3 GREEN SEGMENT ON 13 GND SIGNAL GROUND 14 LEDB1 LED 1 BLUE SEGMENT ON 15 LEDB3 LED 3 BLUE SEGMENT ON 16 LEDB2 LED 2 BLUE SEGMENT ON 4 2 7 Audio Connectors All the audio connectors on the Base board provide connections to the Yamaha YMU782B music synthesizer chip See the manufacturer s specification sheet on the ADS CD for detailed signal and drive specifications 4 2 7 1 Miniature Audio Jacks Audio connectors J25 through J29 are all standard stereo mini jacks Figure 4 13 shows jack terminals Table 4 17 describes the signals and termination Figure 4 13 Audio Jack Diagram 4 2 7
19. Sheek BPRS SS 3 20 3 10 USB HOST Interface FS LS 3 21 3 11 UART Internal and IrDA 3 21 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 Table of Contents Ethernet Inlet AC Creuse eps nd d ed SRE Gnd e PS 3 23 oe gusce pe A tad en allie ap 3 23 Keypad Jas od aa pee a iy ua ae ued Su oaks Dead adi e apa a 3 23 Audio Indicator ai ca Lye uud RU RR RE KCN Rat e Rana 3 24 LED F dicatof 3 24 Sound 3 25 Using the TFT LCD Display 3 25 Using the Keypad oor xac hed bd ees 3 25 Using the Image Sensor Daughter Sar 3 25 Bine the TV Encoder sae ah ae ees 3 26 Using a Plug in Memory Cal 2 sad 3 26 a PCMCIA esa 3 26 Using a Mini ATA Hard cs ttd A 3 27 Using the MC13783 Power Management Board 3 27 Using the E
20. 205 115 116 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 206 208 207 151 210 209 154 153 156 155 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 212 211 214 213 215 GND CPU_BRD_VERO CPU BRD VER1 CPU BRD VER2 BRD GND BCS5 B BCS1 B BCSO B GND GND GND NVCC6 NVCC6 KPCOLO KPCOL1 KPCOL2 KPCOL3 KPCOL4 KPCOL5 KPCOL6 KPCOL7 GND SRXO SRSTO SVENO STXO SIMPDO SCLKO NVCC9 NVCC9 GND GND CVDD 2 775 CVDD 2 775 PWGT1 EN DVS SW2B DVS SW1B DVS SW2A DVS SW1A RST OUT B PWGT2 EN VSTBY PM RST B GND PM CLK32K WATCHDOG RST PWR FAIL PM RSTMCU B PM MEM CS NVCC1 NVCC1 GND GND GND Figure 4 3 Base Board to CPU Board Connectors P1 and P2 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 2 Base Board to CPU Board Connector P1 Signal Description Signal Pin Description 5V Ph 5VDC Supply Voltage 4 6 8 ATA CSO 38 CHIP SELECT 0 ATA controller signal ATA CS1 36 CHIP SELECT 1 ATA controlle
21. 24 NFCLE TRACE DATA 25 SFS6 TRACE DATA 26 NFALE TRACE DATA 27 SCK6 TRACE DATA 28 NFRE_B TRACE DATA 29 SRXD6 TRACE DATA 30 GND SIGNAL GROUND 31 STXD6 TRACE DATA 32 GND SIGNAL GROUND 33 SFS3 TRACE DATA 34 DVDD_1 8V 1 8V VCC POWER 35 SCK3 TRACE DATA 36 USBH2_DATAO TRACE CONTROL 37 SRXD3 TRACE DATA 38 NFWE_B TRACE DATA 39 44 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary 4 66 Freescale Semiconductor NC NC GND GND PM_RST_MCU_B TDO RTCK TCK TMS TDI TRST_B CSPI_MOSI SFS6 SCK6 SRXD6 STXD6 SFS3 SCK3 SRXD3 GND GND GND 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 1 ADS Connectors and Signals NC NC KPROW4 GND GND DVDD_1 8V 5V KPCOL7 KPCOL6 KPCOL5 KPCOL4 KPCOL3 KPROW7 KPROW6 GND GND DVDD_1 8V KPROWS KPROW5 GND GND NC Figure 4 35 Alternate ETM Connector P1 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 67 ADS Connectors and Signals Table 4 43 Alternate ETM Connector P1 Signal Description Pin Signal Description 1 4 NC NOT CONNECTED 5 GND SIGNAL GROUND 6 KPROW4 TRACE CLOCK 7 8 GND SIGNAL GROUND 9 MCU POWER MANAGEMENT MCU RESET 10 GND SIGNAL GROUND 11 JTAG DATA OUT 12 DVDD_1 8V 1 8V VCC POWER 13 RTCK
22. 93 94 95 96 MA10 59 DDR ADDRESS 3 4 71 72 75 76 NC 83 84 87 88 91 NOT CONNECT 92 97 98 99 100 SDAO 7 DDR ADDRESS SDA1 11 DDR ADDRESS SDA2 51 DDR ADDRESS SDA3 23 DDR ADDRESS SDA4 55 DDR ADDRESS SDA5 19 DDR ADDRESS SDA6 47 DDR ADDRESS SDA7 35 DDR ADDRESS SDA8 15 DDR ADDRESS SDA9 31 DDR ADDRESS SDA11 43 DDR ADDRESS SDA12 39 DDR ADDRESS SDA13 27 DDR ADDRESS TP5 79 NOT CONNECT TP6 80 NOT CONNECT M9328MX31ADS User s Manual Rev 1 Preliminary 4 58 Freescale Semiconductor GND NC GND DQMO GND DQM1 GND NFRB GND NC GND NC GND SDCKEX GND 0050 GND 0951 GND SDWE_B GND CAS_B GND RAS_B GND CSDX_B GND SDBA1 GND SDBA2 GND DQM2 GND DQM3 GND NC GND NC GND SDCLK_B GND NC GND NC GND NC GND GND NC NC 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 P3 2 GND 4 NC 6 GND 8 10 GND 12 001 14 GND 16 DQ2 18 GND 20 DQ3 22 GND 24 004 26 GND 28 005 30 GND 32 DQ6 34 GND 36 DQ7 38 GND 40 DQ8 42 GND 44 009 46 GND 48 0010 50 GND 52 0011 54 GND 56 0012 58 GND 60 0013 62 GND 64 0014 66 GND 68 0015 70 GND 72 NC 74 GND 76 NC 78 GND 80 SDCLK 82 GND 84 NC 86 GND 88 NC 90 GND 92 NC 94 GND 96 GND 98 NC 100 NC ADS Connectors and Signals Figure 4 31 Logic Analyzer Connector P3 Pin Assignment M9328MX31ADS
23. ADS Operation Table 3 8 Board Control Register 1 Bit Definitions Name Description Settings ENET_RST Ethernet Reset Reset the Ethernet controller This bit must 0 Ethernet controller reset signal negated be set for the desired duration of the reset signal then cleared Bit 0 1 Ethernet controller reset signal asserted to remove the reset signal External UART Reset Reset external UART controller This bit must be set for the desired duration of the reset signal then signal negated Bit 1 1 UART controller reset signal asserted cleared to remove the reset signal F 0 UART A transceiver enabled Bit 2 UART A Enable Enable UART A transceiver 1 UART A transceiver disabled UB EN B F 0 UART B transceiver enabled Bit 3 UART B Enable Enable UART B transceiver 1 UART B transceiver disabled UCE_EN_B 0 UART C transceiver enabled Bit 4 UART C Enable Enable UART C transceiver 1 UART C transceiver disabled IRDA EN B 0 IRDA transmitter enabled Bit 5 IRDA Enable Used to enable the IRDA transmitter 1 IRDA transmitter disabled LEDO_B LED 0 on Used to turn LED 0 on This is used as a general 0 LED O is off Bit 6 purpose status indicator 1 LED Ois on LED1_B LED 1 on Used to turn LED 1 on This is used as a general 0 LED 1 is off Bit 7 purpose status indicator 1 LED 1 is on CCTL1 2 0 CSI1 Contro
24. CSP12 550 CSP12 552 GND CLK 26M GND IPU LD17 M9328MX31ADS User s Manual Rev 1 Preliminary 3V3 3V3 3V3 B_DO B_D1 B_D2 B_D3 B_D4 B_D5 B_D6 B_D7 B_D8 B_D9 B_D10 B D12 B D13 D14 D15 GND GND B A15 B A14 B A13 B A12 B A11 B A10 GND B A9 GND ADS Connectors and Signals NVCC2 NVCC2 STXD6 SRXD6 SFS6 SCK6 GND SCK3 SRXD3 SFS3 STXD3 GND CSPI1_SCLK CSPI1_MISO CSPI1_MOSI CSPI1_SS2 CSPI1_SS1 CSPI1_SSO CSPI1_SPI_RDY GND GND GND PM_BKUP_DDR PM_BKUP_DDR NC PWGT2_OUT PWGT2_OUT NC USBH2_NXT USBH2_STP USBH2_DIR GND USBH2_CLK GND USBH2_DATA1 USBH2_DATAO PM_SW1A PM SW1A PC POE PWGT1 OUT PWGT1 OUT GND GND DVDD 1 8V DVDD 1 8V NC GND BBCLK GND NC CVDD 2 7V CVDD 2 7V BLBA B Freescale Semiconductor ADS Connectors and Signals IPU_VSYNCHO GND IPU_DRDYO 5 PAR RS IPU D3 REV IPU CONTRAST NVCC7 NVCC7 GND GND NVCC7 IPU D3 SPL IPU DE CLS IPU RD IPU WR IPU FPSHIFT IPU HSYNCH SD D I IPU SD D IO GND IPU SD CLK GND GND CSI HSYNCH GND CSI VSYNCH GND CSI PIXCLK GND GND GND GND NVCCA NVCCA CSI MCLK GND I2C1 GND I2C1 DAT GND UART1 RTS CTS UART1_TXD UART1_RXD GND UART2_RTS UART2_CTS UART2_TXD UART2_RXD CE_CONTROL NVCC8 GND GND 98 97 100 99 102 101 104 103 106 105 108 107 110 109 112 111 114
25. Each pair of terminals provides one power input connection and one power ground connection 4 4 2 Audio Connectors All the audio connectors on the MC13783 board provide connections to the audio function pins of the MC13783 See the specification sheet on the ADS CD for detailed signal and drive specifications M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 75 ADS Connectors and Signals 4 4 2 1 Miniature Audio Jacks Audio connectors J1 J4 J7 and J8 are standard stereo mini jacks Figure 4 41 shows jack terminals Table 4 51 describes the signals and termination Figure 4 41 Audio Jack Diagram Table 4 51 Audio Jack Signal Descriptions Termination Jack 1 2 3 4 5 1 RXINL NC NC RXINR GND 2 RXOUTL NC NC RXOUTR GND 3 GND NC NC 21 GND 4 MC1RIN NC NC MC1LIN GND 7 TXIN NC NC GND GND 8 HSL NC GND HSR GND Signal Description RXINL RX IN LEFT RXINR RX IN RIGHT RXOUTL RX OUT LEFT RXOUTR RX OUT RIGHT MC2IN MICROPHONE 2 ANALOG INPUT MC1RIN MICROPHONE 1 ANALOG INPUT RIGHT MC1LIN MICROPHONE 1 ANALOG INPUT LEFT TXIN TX INPUT HSL HEADSET ANALOG OUTPUT LEFT HPOUTR HEADSETANALOG OUTPUT RIGHT GND SIGNAL GROUND 4 4 2 2 Audio Terminals CN1 CN2 and CN6 are pairs of wire clamp terminals that provide for connection of external speakers CNI and CN6 provide connections for left and right stereo speakers CN6 provides a c
26. Freescale Semiconductor 4 3 2 ETM Connectors ADS Connectors and Signals P4 and P1 are the CPU board ETM connectors P4 is the primary connector and is the alternate connector Figure 4 34 shows P4 pin assignments and Table 4 42 describes P4 signals Figure 4 35 shows P1 pin assignments and Table 4 43 describes P1 signals NC NC GND GND PM RST MCU B TDO RTCK TCK TMS TDI TRST B MOSI SFS6 SCK6 SRXD6 STXD6 SFS3 SCK3 SRXD3 GND GND GND 41 43 NC NC USBH2 DATA1 GND GND 1 8V 5V STXD3 NFRB NFCE_B NFWP_B NFCLE NFALE NFRE_B GND GND DVDD_1 8V USBH2_DATAO NFWE_B GND GND NC Figure 4 34 Primary ETM Connector P4 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 65 ADS Connectors and Signals Table 4 42 Primary ETM Connector P4 Signal Description Pin Signal Description 1 4 NC NOT CONNECTED 5 GND SIGNAL GROUND 6 USBH2_DATA1 TRACE CLOCK 7 8 GND SIGNAL GROUND 9 PM RST MCU POWER MANAGEMENT MCU RESET 10 GND SIGNAL GROUND 11 TDO JTAG DATA OUT 12 DVDD_1 8V 1 8V VCC POWER 13 RTCK JTAG RETURN CLOCK 14 5V 5V VCC POWER 15 TCK JTAG CLOCK 16 STXD3 TRACE DATA 17 TMS JTAG MODE 18 NFRB TRACE DATA 19 TDI JTAG DATA IN 20 NFCE_B TRACE DATA 21 TRST_B JTAG RESET 22 NFWP_B TRACE DATA 23 CSPI_MOSI TRACE DATA
27. Freescale Semiconductor 4 37 ADS Connectors and Signals Table 4 19 ATA Connector J3 Signal Description continued Pin Signal Description 15 ATA_D1 ATA DATA 1 16 ATA_D14 ATA DATA 14 17 ATA_DO ATA DATA 0 18 ATA_D15 ATA DATA 15 19 GND SIGNAL GROUND 20 NC NO CONNECTION 21 ATA DMA REQUEST 22 GND SIGNAL GROUND 23 ATA_DIOW_B ATA DATA INPUT OUTPUT READ 24 GND SIGNAL GROUND 25 ATA_DIOR_B ATA DATA INPUT OUTPUT WRITE 26 GND SIGNAL GROUND 27 ATA_IORDY_B ATA INPUT OUTPUT READY 28 CSEL CHIP SELECT TIED HIGH 29 ATA DMACK ATADMA ACKNOWLEDGE 30 GND SIGNAL GROUND 31 ATA INTERRUPT REQUEST 32 ATAIOIS16_B ATA IO PORT IS 16 BIT 33 DA1 ATA REGISTER ADDRESS SIGNAL 34 ATA CBLID B ATA CABLE ID 35 DAO ATA REGISTER ADDRESS SIGNAL 36 DA2 ATA REGISTER ADDRESS SIGNAL 37 ATA CSO B ATA CHIP SELECT 38 ATA CS1 B ATA CHIP SELECT 39 ATA DASP B ATA DRIVE 1 IS PRESENT 40 GND SIGNAL GROUND 41 3V3 3 VDC POWER 42 3V3 3 VDC POWER 43 GND SIGNAL GROUND 44 NC NO CONNECTION 4 2 10 RS 232 Connectors ADS RS 232 interfaces are controlled either by MCU UARTs or by a DUART on the Base board Transceivers on the Base board drive the MCU signals to RS 232 levels MCU UARTS switch selectable on the Base board There are three DCE ports and two DTE ports 4 2 10
28. NC GND GND GND NC NC GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND NC NC NC NC NC NC NC NC NC NC P5 NC GND NC NC NC NC GND NC GND NC NC NC NC NC NC NC PM_VUSB_3V PM_VUSB_3V PM_VUSB_3V GND GND GND NC NC NC NC NC NC NC PM_VIOLO PM_VIOLO PM_VIOLO NC PM_VIOHI PM_VIOHI PM_VIOHI NC 5V 5V 5V 5V GND GND NC GND NC NC NC NC NC NC NC NC M9328MX31ADS User s Manual Rev 1 Preliminary VIB_EN DVS_SW1_B LED_MD1 LED_MD2 LED_MD3 LED_MD4 LED_AD1 LED_AD2 LED_KP ATLAS_UTX_ENB GND ATLAS_UDATVP ATLAS USE 0VM GND ATLAS URCVD GND ATLAS URXVP ATLAS URXVM ATLAS IN GND GND PM VUSB 3V PM VUSB 3V PM RST B VSTBY DVS SW1A BB STBY DVS SW2A PM RSTMCU B PM VIOLO PM VIOLO ADTRIG BB SEC INT PM VIOHI PM VIOHI BB VCC REGEN 5V 5V 5V GND GND GND DVS_SW2B GND PM_VDIG PM_VDIG PM_PWRRDY GPIO1_1 GND PM_GP01_BUFF PWR_FAIL USER_OFF GPIO1_0 PM_GP02_BUFF LEDR1 LEDR2 LEDR3 LEDG1 LEDG2 LEDG3 LEDB1 LEDB2 LEDB3 GND TSX1 GND TSX2 GND TSY1 GND TSY2 GND ADIN4 GND GND GND 5 GND ADIN6 GND ADIN7 GND ADIN8 GND ADIN9 GND ADIN10 GND CPU_PRI_VCC GND PM_CLK32K_MCU GND PM_INT GND PM_CLIA GND GND CSPI2_SCLK CSPI2 550 CSPI2 MOSI CSPI2 MISO NC GND BB CSPI CLK BB 550 MOSI 5 Freescale Semiconductor
29. Table 4 51 Table 4 52 Table 4 53 viii Synchronous LCD Connector J12 Signal Description 4 28 Option Connector J11 Signal 4 30 Parallel LCD Connector I J9 Signal Description 4 3 Parallel LCD Connector II J8 Signal 4 32 Serial Asynchronous LCD Connector J6 Signal 4 34 Funlight Connector 720 Signal Description 4 35 Audio Jack Signal Description o ios aee e tub QD e UD EP TES 4 36 TV Encoder Connector P13 Signal 4 36 ATA Connector J3 Signal 4 37 RS 232 DCE Connectors and P7B Signal Description 4 39 RS 232 DCE Connector J7 Pin Signal Description 4 39 RS 232 DTE Connectors P11A and P11B Signal Description 4 40 I2C Connector JP13 Signal 4 40 CSPI Connector J15 Signal 4 4 Ethernet Connector Signal Description 4 42 USB Connectors andJ2 Signal 4 42 USB Host Connectors and J5 Signal
30. where some of them are grouped An Interrupt Mask Register can disable each interrupt source 3 3 6 1 The version register has three fields that show the version of the CPLD the CPU board and the Base board The CPLD version is an 8 bit programmed field that is changed when the CPLD design changes The CPU and BASE fields are implemented as two 4 bit fields and configured with external input signals connected to pull up and pull down resistors They represent the revision of the PCB which changes by letter revs marked in etch on the back side of the PCB The first revision is A and the revision code will read back 0000b The next revision B will read back 0001b and so on The CPU and BASE fields are muxed on the peripheral data bus Version Register i MX31ADS User s Manual REV 1 Preliminary 3 6 Freescale Semiconductor ADS Operation BIT 15 14 13 12 11 9 8 7 5 4 2 1 FIELD PBC CPU BASE OPER R R 3 3 6 2 Figure 3 2 Version Register Board Status Register 1 BSTAT1 5 contains several bits that represent the board status from different places on the board These registers are read only BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATLAS FLIP FLIP 502 1501 LIGHT KP NF_ FIELD ey ASV IN EM SEN
31. 13 Turn System Power On 1 On the CPU board slide S1 to the ON position 2 D1 illuminates indicating that external power is applied i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 21 es Configuring and Connecting the ADS i MX31ADS User s Manual REV 1 Preliminary 2 22 Freescale Semiconductor Chapter 3 ADS Operation This chapter describes how the ADS functions 3 1 Functional Block Diagram ADS Operation Figure 3 1 shows the functional blocks of the ADS in their approixmate locations in the system USB USB USB USB SD MMC SD MMC 2 OTG OTG HOST HOST W CD W CD Mobile ATA5 Conn IRDA Fast Med HS FS FS HS
32. 2 DETECT 7 MSHC2 MS 2 DATA 8 MSHC2_SCLK MS 2 SERIAL CLOCK 9 VSD2 MS 2 POWER 10 GND SIGNAL GROUND 4 3 8 Subminiature Clock Connectors Subminiature jacks J10 J11 and J12 provide external clock signal connections J10 provides an input for the 32 KHz low speed clock signal CKIL J11 provides the MCU CLKO output signal and J12 provides an input for the 26 MHz high speed clock signal CKIH 4 3 9 Power Connector J3 is the power connector for the CPU board and the ADS It is a DIN type barrel connector M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 73 ADS Connectors and Signals 4 4MC13783 Board Connectors The MC13783 Audio and Power Management chip is a multifunctional device with a number of capabilities The ADS Base board provides access to many of these functions but some are directly accessible on the MC13783 board itself Table 4 50 describes MC13783 Board connector functions Figure 4 40 shows the locations of the connectors on the MC13783 board See paragraph 4 2 for descriptions of MC13783 board connectors J5 and J6 which mate with connectors P5 and P6 of the Base board Table 4 50 MC13783 Board Connectors Connector Type Description CN1 Wire Clamp Terminals Right Stereo Speaker Output CN2 Wire Clamp Terminals Earpiece Speaker Output Mono CN3 USB Connector MC13783 USB Interface CN4 Submi
33. 4 15 ADS Connectors and Signals NC NC NC NC NC NC NC PM_VRF_REF PM_VRF_REF GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC PM_VRF_CP 98 97 100 99 102 101 104 103 106 105 108 107 110 109 112 111 114 113 202 201 204 203 205 115 117 116 118 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 206 208 207 210 209 154 153 156 155 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 212 211 214 213 215 PM_VDIG PM_VDIG NC NC NC NC NC OPM_SW1A OPM SW1A NC GND GND PM SW1A PM SW1A PM SW1A PM SW1A NC NC NC NC NC NC NC NC NC NC NC NC PM SW1B PM SW1B PM SW1B GND GND NC GND NC NC 3V3 3V3 3V3 GND GND GND PM_VRFDIG PM_VRFDIG PM_GP03_BUFF PM_VESIM PM_VESIM CLKO PC_CE2_B PC_OE_B BPC_POE GND GND PM_SW1A PM_SW1A NC NC NC NC NC NC CVDD_2 775V CVDD_2 775V NC STXD4 SRXD4 SFS4 SCK4 NC NC PM_SW1B PM_SW1B GND GND GND 2 GND NVCC2 PM_SW2A PM_SW2A NC PM_SW2B PM_SW2B NC PWGT1_OUT PWGT1_OUT NC PM_BKUP_DDR PM_BKUP_DDR ON1_B ON2_B ON3_B VSD2 VSD2 GND GND 98 97 100 99 102 101 104 103 106 105 108 107 110 109 112 111 114 1
34. A5 CSPI2 SS1 SLAVE SELECT 1 CSPI signal bidirectional A6 CSPI2 SS2 SLAVE SELECT 2 CSPI signal bidirectional A7 I2C1 SQUARED C CLOCK Serial clock bidirectional A8 2 DAT SQUARED C DATA Serial data bidirectional A9 SCK5 SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK Bidirectional output in master mode and input in slave mode A10 STXD5 SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA Serial output signal 11 SRXD5 SYCHRONOUS SERIAL INTERFACE RECEIVED DATA Serial input signal 12 SFS5 SYCHRONOUS SERIAL INTERFACE FRAME SYNC M3 SCK6 SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK Bidirectional output in master mode and input in slave mode 14 R_STXD6 SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA Serial output signal A15 R_SRXD6 SYCHRONOUS SERIAL INTERFACE RECEIVED DATA Serial input signal A16 R_SFS6 SYCHRONOUS SERIAL INTERFACE FRAME SYNC B1 USBGOTG_DATA3 USB OTG DATA 3 B2 USBGOTG_DATA4 USB OTG DATA 4 B3 USBGOTG_DATA1 USB OTG DATA 1 B4 USBGOTG_DATA2 USB OTG DATA 2 B5 USBGOTG_DATAO USB OTG DATA 0 B6 USBGOTG_DATA6 USB OTG DATA 6 B7 USBGOTG_DATA7 USB OTG DATA 7 B8 USBGOTG DATAS USB OTG DATA 5 9 R_PC_RST PCMCIA RESET signal 10 2 PCMCIA Battery Voltage Detect 2 B11 R_PC_BVD1 PCMCIA Battery Voltage Detect 1 B12 R_PC_VS2 PCMCIA Voltage Sense 2 signal B13 R_USBH2_DATA1 USB HOST DATA 1 B14 R_IOIS16 PCMCIA control signal B15 R_USBH2_DATAO USB
35. Assignment Table 4 21 RS 232 DCE Connector J7 Pin Signal Description Pin Signal Description 1 EXT_UB_DCD DUART CHANNEL B CARRIER DETECT 2 EXT UB RXD DUART CHANNEL TRANSMITTED DATA 3 EXT UB TXD DUART CHANNEL B RECEIVED DATA 4 EXT UB DUART CHANNEL B DATA TERMINAL READY 5 GND SIGNAL GROUND 6 EXT DSR DUART CHANNEL B DATA SET READ 7 EXT UB RTS DUART CHANNEL B READY TO SEND 8 EXT BU CTS DUART CHANNEL B CLEAR TO SEND 9 EXT UB RI DUART CHANNEL B RING INDICATOR 10 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 39 ADS Connectors and Signals 4 2 10 2 DTE Connectors DB connector connects to UART transceiver A which can be driven by MCU UARTI or UARTS DB9 connector P11B connects to UART transceiver B which can be driven by MCU UART3 or UART4 Figure 4 18 shows DB9 pin assignments and Table 4 22 describes connector signals Figure 4 18 RS 232 DTE Connectors P11A and P11B Pin Assignment Table 4 22 RS 232 DTE Connectors P11A and P11B Signal Description Pin Signal Description 1 CD CARRIER DETECT RS 232 input signal 2 RXD RECEIVED DATA 5 232 serial data input signal 3 TXD TRANSMITTED DATA RS 232 serial data output signal 4 DTR DATA TERMINAL READY RS 232 output signal 5 GND GROUND 6 DSR DATA SET READY RS 232 input signal 7 RTS READY TO SEND RS 232 output signal 8 CTS CLEAR TO SEND RS 232 inpu
36. CS EECS Figure 3 19 Ethernet Interface 3 13 LCD IPU Interfaces The ADS support several different types of LCD interfaces The asynchronous LCD interface J12 is where scan control is provided by 1 M X31 This is similar to the LCD interface of previous 1 processors Additionally there are connectors for smart LCD interfaces These LCD display types can buffer data and provide scan control without the help of the CPU Two connectors J8 J9 are parallel and one is serial J6 There is also a connector with CSPI3 signals available for serial LCD control J15 Besides control signals these connectors have power selects backlight controls and GPIO signals J20 connects to the three push button switches and the Fun Light connections on the MC13783 card To use the Fun Light signals the Fun Light components on the MC13783 card must be disabled by removing R136 through R144 3 14 Keypad The ADS includes an external keypad module that connects to the Base board at J21 The keys provide tactile feedback The keypad interface reads the pad via the KCOL 7 0 and KROW 7 0 signals The i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 23 ADS Operation interface has chording diodes to prevent ghost key presses The keys are labeled with numeric cursor control soft key and spare key functions but the actual functionality is determined by user software A few of the key
37. GND SIGNAL GROUND 11 RTCK RETURN CLOCK 12 GND SIGNAL GROUND 13 TDO JTAG TEST DATA OUTPUT 14 GND SIGNAL GROUND 15 PM RST MCU B POWER MANAGEMENT MCU RESET 16 GND SIGNAL GROUND 17 DE B DEBUG ENABLE 18 GND SIGNAL GROUND 19 GND SIGNAL GROUND 20 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 69 ADS Connectors and Signals 4 3 4 PC Test Connector J4 is the CPU board PC Test connector Figure 4 37 shows pin assignments and Table 4 45 describes signals J4 1 2 GND 3 4 GND 5 6 GND 7 8 GND NC e 10 NC Figure 4 37 PC Test Connector J4 Pin Assignment Table 4 45 PC Test Connector J4 Signal Description Pin Signal Description 1 DEBUG INTERNAL USE 2 GND SIGNAL GROUND 3 DEBUG INTERNAL USE 4 GND SIGNAL GROUND 5 DEBUG INTERNAL USE 6 GND SIGNAL GROUND 7 DEBUG INTERNAL USE 8 GND SIGNAL GROUND 9 NC NO CONNECTION 10 NC NO CONNECTION M9328MX31ADS User s Manual Rev 1 Preliminary 4 70 Freescale Semiconductor 4 3 5 ADS Connectors and Signals In circuit Serial Programming Connector J7 is the CPU board ISP connector Figure 4 38 shows pin assignments and Table 4 46 describes signals GND 2 GND 4 3V3 6 GND 8 NC 10 J7 TCK TMS TDI TDO NC Figure 4 38 ISP Connector J7 Pin Assignment Table 4 46 ISP Connector J7 Signal Descrip
38. J18 J20 J21 J22 J23 J24 and J25 2 5 3 Select QVCC and PLL Voltages CAUTION The CPU board regulators can be used with or without the MC13783 board but all the jumpers must be configured the same way 3 Jumper pins 1 and 2 of JP12 QARM JP17 JP20 01 2 JP32 X VCC and JP35 FVCC SEL to select the regulators on the CPU board see paragraph 2 3 2 4 Jumper pins 2 and 3 of JP12 QARM JP17 JP20 QL2 JP32 X VCC and JP35 FVCC SEL to select the voltage sources on the MC13783 board see paragraph 2 3 2 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 17 Configuring and Connecting the ADS 2 5 4 Select CPU Clock Source 1 Use JP22 to select which clock to enable 26 MHz CKIH or 32 kHz CKIL 2 Use either JP1 or JP26 select the source for that clock 2 5 5 Set Other CPU Board Jumpers Configure JP37 Fuse Pin Voltage FUSE VDD see paragraph 2 3 2 Configure JP6 Base Board LA DATA Enable Configure JP2 Reset Configuration Configure JP38 DRAM Power VDD SEL Configure JP31 SVCC Configure JP10 JTAG Mode SJC MOD Qv Uns BAR i MX31ADS User s Manual REV 1 Preliminary 2 18 Freescale Semiconductor Configuring and Connecting the ADS 2 5 6 Set CPU Board Switches Set Boot Mode Switches SW2 1 through SW2 5 Set Push Button Reset Connection Switches SW2 6 and SW2 7 Set POR RESET SW2 6 Set RESET OUT SW2 7 Set Tamper Detect SW2 8
39. JP11 NVCC6 Shunt JP12 QARM Power Select JP13 NVCC SEL6 amp 9 JP14 NVCC3 Shunt JP15 NVCC9 Shunt JP16 NVCC SEL4 JP17 QPER Power Select JP18 NVCC1 Shunt Freescale Semiconductor 2 9 Configuring and Connecting the ADS Table 2 6 CPU Board Jumper Headers continued Jumper Designation P 9 Connection JP19 182 Remove jumper to measure voltage drop across 1 Ohm resistor QL2 Shunt jumper is not required for normal operation JP20 Use on board voltage regulators use for stand alone mode QL2 Power Select Use MC13783 power JP21 182 Remove jumper to measure voltage drop across 1 Ohm resistor NVCCA Shunt jumper is not required for normal operation JP22 1 2 Use 26 MHz clock CKIH CLK SEL CPU Clock Select Use 32 kHz clock CKIL JP23 Select 2 7 VDC Source for NVCC7 remove when APMS is used NVCC SEL7 Select 1 8 VDC Source for NVCC7 remove when APMS is used 2 JP24 182 Remove jumper to measure voltage drop across 1 Ohm resistor NVCC10 Shunt jumper is not required for normal operation JP25 amp Remove jumper to measure voltage drop across 1 Ohm resistor NVCC7 Shunt jumper is not required for normal operation Use on board 26 MHz oscillator 1 2 re 2 3 Use MC13783 board 32 KHz clock Clock Input Select 23 Use MC13783 board 32 KHz clock Ci Use external clock source connected to J10 JP27 182 Remove jumper to measure voltage drop across 1 Ohm resistor XVCC Shunt jumper is not
40. Manual REV 1 Preliminary Freescale Semiconductor 3 5 ADS Operation CPLD Memory Map Table 3 5 CPLD Memory Map Name Description Address VERSION Version Register B400_0000 BSTAT2 Board Status Register 2 B400_0002 Board Control Register 1 set address B400_0004 BCTRL1 Board Control Register 1 clear address B400_0006 Board Control Register 2 set address B400_0008 BCTRL2 Board Control Register 2 clear address B400_000A Board Control Register 3 set address B400_000C BCTRL3 Board Control Register 3 clear address B400_000E Board Control Register 4 set address B400_0010 BCTRL4 Board Control Register 4 clear address 400 0012 BSTAT1 Board Status Register 1 400 0014 ISR Interrupt Status Register B400_0016 ICSR Interrupt Current Status Register B400_0018 E Interrupt Mask Register set address 400 001A Interrupt Mask Register clear address B400 001C External UART Port A 401 0000 5 16 652 External UART Port B B401_0010 Ethernet controller I O base address B402_0000 CS8900A Ethernet controller Memory base address B402_1000 Ethernet controller DMA base address B402_2000 YMU782B Audio synthesizer port B403_0000 3 3 6 Register Descriptions The CPLD has general control registers and interrupt control registers The number of ADS interrupt sources is larger than the number of MCU GPIO pins All ADS interrupts are routed through the CPLD
41. PORT 4 RECEIVE DATA SRXD5 155 AUDIO PORT 5 RECEIVE DATA STXD4 138 AUDIO PORT 4 TRANSMIT DATA STXD5 153 AUDIO PORT 5 TRANSMIT DATA TSX1 21 TOUCHSCREEN X PLATE TSX2 25 TOUCHSCREEN X PLATE TSY1 29 TOUCHSCREEN Y PLATE TSY2 33 TOUCHSCREEN Y PLATE USER_OFF 94 USER OFF MODE INPUT VESIM_EN 177 ESIM REGULATOR ENABLE VIB_EN 2 VIBRATOR REGULATOR ENABLE VSD1 187 189 VOLTAGE REGULATOR OUTPUT VSD2 188 190 VOLTAGE REGULATOR OUTPUT VSIM_EN 143 SIM REGULATOR ENABLE VSTBY 46 STAND BY INPUT 4 2 3 Image Sensor and Extension Connectors Connectors J10 J13 J17 J22 and J23 are three row 16 pin DIN connectors J10 and J13 are connectors for the image sensor module included with the ADS They are identical except for connector orientation on the Base board J10 is horizontal while J13 is vertical Extension connectors J17 J22 and J23 provide ADS signals for use with expansion cards and accessories The connector pin assignments are not identical J17 and J22 are horizontal while J23 is vertical Figure 4 5 shows pin numbering for these connectors Table 4 6 describes image sensor connector signals Table 4 7 Table 4 8 and Table 4 9 describe expansion connector signals M9328MX31ADS User s Manual Rev 1 Preliminary 4 20 Freescale Semiconductor ADS Connectors and Signals Figure 4 5 Image Sensor and Extension Connector Pin Numbering Table 4 6 Image Sensor Connectors J10 and J13 Signal Description
42. REV 1 Preliminary Freescale Semiconductor List of Tables Table 1 1 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 3 10 Table 3 11 Table 3 12 Table 3 13 Table 3 14 Table 3 15 Table 3 16 Table 3 17 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 rd aA redu uia nis uus REGGE HES 1 4 Base Board SW 1 Switch function SRS ae PRESS 2 2 Base Board SW2 Switch 2 2 SW3 Switch Setting Soses enti ee A eA A RR Rr S Not eA 2 3 Base Board Jumper Headers ees seen bade 24494 IHRE ERR RE 2 3 Boot Mode Switch Setingss as o echar yids RAW WR 2 8 CPU Board Jumper Headers c Et 2 9 MC13783 Board S4 USB Mode 2 13 MC13783 Board 55 Backup Source Select 2 13 MC13783 Board SW6 USB UDATVP and USBOVM Direction Select 2 13 MC13783 Board SW7 Buffer Enable and Direction 2 14 MC13783 Board SW8 and CLIB Source 2 14 MC13783 Board SW9 MC13783 Pow
43. RS eR ada ES 2 19 2 5 8 Set Base Board Switches alan data dea FOR aoo PEE I dcr 2 19 2 5 9 Connect the CPU Board to the Base Board 2 19 2 5 10 Configure the MC13783 Board 2 20 2 5 11 Connect MC13783 Board to the Base 2 21 2 5 12 Connect Power tothe CPU Boald amp ice scams a CARRE AAE 2 21 2 5 13 System Power ia Een Se Era RUP wt RUE Rl s 2 21 Chapter 3 ADS Operation 34 Functional Block Diagram uoc wea RE 3 1 3 2 AS Memory Map b Ve ws 3 2 33 Peripheral Bus Controll CPED one Cw SR A 3 3 3 3 1 jn c PTT 3 3 3 3 2 cota rure qd e ENE ARR eh ad dena 3 3 3 3 3 Peripheral cres S pde re a a peace SBS 3 4 3 3 3 1 Peripheral B s Cveles c ok tte ose ss da sen se a ti 3 4 3 3 3 2 DMA Operatii c od aces tera ES waste debe ue dope ele A 3 4 3 3 3 3 SC16C652C isre ee Red SS Poder eue Peu ROS 3 5 3 3 3 4 SC88900A Ethernet Decode s Oe ceto t te les 3 5 3 3 3 5 YMU782B Audio Synthesizer 3 5 3 3 4
44. Stick J6 Memory Card Memory Stick J7 10 pin header In circuit Serial Programming J8 20 pin header JTAG Interface J9 Edge Connector NAND Flash Connector J10 Subminiature Jack External 32 kHz Clock Input CKIL J11 Subminiature Jack MCU CLKO Output J12 Subminiature Jack External 26 MHz Clock Input CKIH P1 60 pin Alternate ETM P2 100 pin SAMTEC P3 100 pin SAMTEC P4 60 pin Primary ETM P5 100 pin SAMTEC P6 100 pin SAMTEC M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 55 ADS Connectors and Signals 4 J9 1 5 2 6 J10 J11 J12 NOTE J1 AND J2 ARE LOCATED ON THE UNDERSIDE OF THE BOARD Figure 4 29 CPU Board Connectors 4 3 1 Logic Analyzer Connectors P2 P3 P5 and P6 are the CPU board logic analyzer connectors All are 100 pin SAMTEC connectors Figure 4 30 shows P2 pin assignments and Table 4 38 describes P2 signals Figure 4 31 shows P3 pin assignments and Table 4 39 describes P3 signals Figure 4 32 shows P5 pin assignments and Table 4 40 describes P5 signals Figure 4 33 shows P6 pin assignments and Table 4 40 describes P6 signals M9328MX31ADS User s Manual Rev 1 Preliminary 4 56 Freescale Semiconductor GND NC GND SDAO GND SDA1 GND SDA8 GND SDA5 GND SDA3 GND SDA13 GND SDA9 GND SDA7 GND SDA12 GND SDA11 GND SDA6 GND SDA2 GND SDA4 GND MA10 GND DQS2 GND DQS3 GN
45. Table 4 30 SD MMC Connector P4 Signal Description Description Pin s Signal SD Card MMC Card 1 Bit Mode 4 Bit Mode 1 PC PWRON DATA LINE 3 Not Used DATA LINE 3 2 PC CD1 B COMMAND RESPONSE 3 GND SIGNAL GROUND 4 VDD 3 VDC POWER selectable VSD2 or 3V3 5 PC CD2 B CLOCK INPUT 6 GND SIGNAL GROUND 7 PC WAIT B DATA LINE 0 8 PC READY DATA LINE 1 INTERRUPT IRQ DATA LINE 1 or IRQ 9 PC VS1 DATA LINE 2 READWAIT RW DATA LINE 2 or RW 10 SD2 DET CARD DETECT 11 GND GROUND 12 NC NO CONNECTION 18 NC NO CONNECTION 14 NC NO CONNECTION 15 NC NO CONNECTION 16 SD2 WP WRITE PROTECT DETECT M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 45 ADS Connectors and Signals 4 2 18 PCMCIA Connector U30 is a standard 88 pin PCMCIA socket Table 4 31 describes U30 signals Table 4 31 PCMCIA Connector U30 Signal Description Pin Signal Description 1 GND SIGNAL GROUND 2 PC_D3 DATA 3 3 PC_D4 DATA 4 4 PC_D5 DATA 5 5 PC_D6 DATA 6 6 PC_D7 DATA 7 7 PC_CE1_B DATA 8 8 PC_A10 ADDRESS 10 9 OE_B OUTPUT ENABLE 10 PC_A11 ADDRESS 11 11 9 ADDRESS 9 12 8 ADDRESS 8 13 PC_A13 ADDRESS 13 14 PC_A14 ADDRESS 14 15 WE_B WRITE ENABLE 16 READY READY 17 VCC SWITCHED POWER 18 VPP SWITCHED POWER 19 PC A16 ADDRESS 16 20 PC A15 ADDRESS 15 21 PC A12 ADDRESS 12 22 PC A7 ADDRESS 7 23 PC A6 A
46. User s Manual Rev 1 Preliminary Freescale Semiconductor 4 59 ADS Connectors and Signals Table 4 39 Logic Analyzer Connector P3 Signal Description Signal Pin Description CAS_B 43 DDR CONTROL CSDX_B 51 DDR CONTROL DQO 8 DDR DATA 001 12 DDR DATA DQ2 16 DDR DATA DQ3 20 DDR DATA DQ4 24 DDR DATA DQ5 28 DDR DATA DQ6 32 DDR DATA DQ7 36 DDR DATA DQ8 40 DDR DATA DQ9 44 DDR DATA DQ10 48 DDR DATA DQ11 52 DDR DATA DQ12 56 DDR DATA DQ13 60 DDR DATA DQ14 64 DDR DATA DQ15 68 DDR DATA DQMO 7 DDR CONTROL DQM1 11 DDR CONTROL DQM2 63 DDR CONTROL DQM3 67 DDR CONTROL DQSO 31 DDR CONTROL DQS1 35 DDR CONTROL 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 30 33 34 37 38 41 42 45 46 49 50 53 GND 54 57 58 61 62 GROUND SIGNAL 65 66 69 70 73 74 77 78 81 82 85 86 89 90 93 94 95 96 3 4 19 23 71 72 75 76 83 84 87 NC 88 91 92 97 98 NOT CONNECT 99 100 NFRB 15 NAND FLASH READ RAS B 47 DDR CONTROL SDBA1 55 DDR CONTROL SDBA2 59 DDR CONTROL SDCKEX 27 DDR CONTROL SDCLK 80 DDR CLOCK SDCLK B 79 DDR CLOCK SDWE B 39 DDR CONTROL M9328MX31ADS User s Manual Rev 1 Preliminary 4 60 Freescale Semiconductor GND NC GND DO GND D1 GND D2 GND D3 GND D4 GND D5 GND D6 GND D7 GND D8 GND 09 GND D10 GND D11 GND D12 GND D13 GND D14 GND D15 GND N
47. When using the CPU board in standalone mode proceed to paragraph 2 5 12 Sy Na 2 5 7 Set Base Board Jumpers Configure JP1 HS OTG VUSB Source Configure JP2 HS HOST VUSB Source Configure JP3 SERIAL LCD CS Configure JP4 SD1 POWER Configure JP5 SD2 POWER Configure JP6 and JP7 2 connection FS OTG PHY Configure JP8 NVRAM Ethernet PHY Enable Configure JP12 Keypad LIGHT SENSE Configure JP14 IWIRE Enable 200 OY OR bor 2 5 8 Set Base Board Switches 1 Set SW1 UART EN Switches 2 Set SW2 RS 232 MBAUD Shut Down WDI and Buzzer Enable Switches 3 Set SW3 User Defined Switches 2 5 9 Connect the CPU Board to the Base Board Place the Base board on a flat work surface 2 Install the CPU board as shown in Figure 2 8 the connectors are keyed so the CPU board cannot be connected incorrectly i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 19 Configuring and Connecting the ADS Figure 2 8 Connecting the CPU Board to the Base Board 2 5 10 Configure the MC13783 Board If you are not using the MC13783 board proceed to paragraph 2 5 12 See paragraph 2 4 for information about MC13783 board jumpers and switches Set JMP2 Vibrator LED Select Set JMP4 TXIN Select Set JMP5 SW1A B Combination setting must match JMP7 Set JMP6 SW2A B Combination setting must match 8 Set JMP7 SW1A B Combination setting must match JMP5 Set JMP8 SW2
48. be set to 5V or left unconnected Hi Z These default to OFF and unconnected at reset You must supply a compatible PCMCIA card for use with the 1 MX31 ADS i MX31ADS User s Manual REV 1 Preliminary 3 26 Freescale Semiconductor ADS Operation 3 24 Using a Mini ATA Hard Drive The ADS provides an 5 compatible interface designed to work with mini hard drives J3 is a 44 pin header designed to be directly compatible with Hatachi mini drives The dual row 2mm spaced connector requires a ribbon cable to connect to the mini drive Neither the cable nor the drive is provided with the ADS Most of the ATA signals are multiplexed and then translated to 3 3V levels for the mini hard drive The CPLD controls the multiplexer enables and selects CAUTION Make sure that input power is disconnected or switched off before the mini hard drive is connected Connecting it with power applied can damage the mini hard drive and the Base board 3 25 Using the MC13783 Power Management Board The MC13783 Power Management Board APMB provides many functions beside power regulation It has audio interface and processing tri colored Fun Light LED controls touch panel controller backlight LED drivers programming interfaces to both a primary and secondary processors a vibratory actuator a USB OTG transceiver battery charging controller battery emulation for both the main and coin cell batteries and two 32KHz clock outputs Most regulators have
49. connectors allows the user to choose which signal group will be replaced by ETM signals i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 27 ADS Operation 3 27 Using the Samtec Logic Analyzer Connectors The CPU board has four specialized Samtec connectors designed to be compatible with Logic Analyzer cables from HP that use the mating connector This style of connector has lower capacitance than Mictor style connections All CPU connections required for memory interfacing are brought to these connectors i MX31ADS User s Manual REV 1 Preliminary 3 28 Freescale Semiconductor Chapter 4 ADS Connectors and Signals 4 1 Introduction This chapter describes connector pin assignments and signals for the M9328MX31ADS Base CPU and APM boards The tables in this section list signal names as they appear in the board schematics The use of _B at the end of a name indicates an active low signal 4 2 Base Board Connectors Table 3 1 shows the Base board connectors Figure 3 1 shows connector layout on the left hand side of the Base board Figure 3 2 shows connector layout on the right hand side of the Base board Connectors P 1 and P2 which mate with connectors J1 and J2 on the CPU board and P5 and P6 which mate with connectors J5 and J6 on the MC13783 board are described in this section Table 4 1 Base Board Connectors Co
50. control and status signals board revision registers and other functions This glue logic is implemented with a CPLD The following paragraphs describe the CPLD 3 3 1 Features The key features provided by the CPLD include e A16 bit slave interface to the CPU data bus Address decode and control for the Ethernet controller Address decode and control for the external UART controller Address decode for the audio synthesizer Control and status registers for various board functions Control and multiplexing for a variety of interrupt sources 3 3 2 CPU Interface The interface connects the 1 M X31 through the CPLD to peripherals with asynchronous and synchronous protocols The signal involved with this are listed in Table 3 2 The CPU provides several chip select signals that can be configured for different memory types The CPLD uses chip select signal CS4 with the following requirements e CS4 must occupy 32 Mbyte window in the address space e CS4 must be configured for 16 bit bus width asynchronous transfers e CS4 assertion window must be at least 150 ns Byte enables must be asserted at CS4 assertion time Byteenables must be negated at least 1 2 clock before CS4 negation during write cycles e Multiplexed transfers and synchronous transfers are not supported Table 3 2 CPU Signal Interface Signal Direction Description A 25 0 In Address bus not all address lines are used D 15 0 In Out D
51. for an LCD panel Figure 4 11 shows connector pin assignments and Table 4 15 describes the signals J6 DVDD 1 8V 1 52 3V3 IPU_SD_CLK 4 SD D IO SERLCD CS 5 e IPU_SER_RST LCDRST2 7 8 IPU SD D I GND 9 e e 10 CVDD_2 775V LED AD1 11 e 12 PM_VBLITE LED_AD2 13 14 LED GPIO1 15 e 16 GPIO2 Figure 4 11 Serial Asynchronous LCD Connector J6 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 33 ADS Connectors and Signals Table 4 15 Serial Asynchronous LCD Connector J6 Signal Description Pin Signal Description 1 DVDD_1 8V 1 8 VDC SUPPLY 2 3V3 3 VDC SUPPLY 3 IPU_SD_CLK SERIAL DATA CLOCK 4 IPU_SD_D_IO SERIAL DATA INPUT OUTPUT 5 SERLCD_CS SERIAL LCD CHIP SELECT 6 IPU SER RST SERIAL INTERFACE RESET 7 LCDRST2 LCD DISPLAY RESET 2 8 SD D I SERIAL DATA INPUT 9 GND SIGNAL GROUND 10 CVDD 2 775 2 775 VDC SUPPLY 11 LED AD1 AUXILARY DISPLAY LIGHT EMMITING DIODE 12 PM VBLITE LCD PANEL BACKLIGHT VOLTAGE 13 LED_AD2 AUXILARY DISPLAY LIGHT EMMITING DIODE 14 LED_KP KEYPAD LIGHT EMMITING DIODE 15 GPIO1 GENERAL PURPOSE I O LINE 1 16 GPIO2 GENERAL PURPOSE I O LINE 2 4 2 6 Funlight Connector Connector J20 provides control signals for three three segment RGB LCD funlights Figure 4 12 shows connector pin assignments and Table 4 16 describes the signals
52. interface can function as either a USB host or USB device The interface provides power on the USB bus in host mode This power may be supplied by the Phillips part or from the external 5 volt power source through a MIC2536 power switch For details on the operation of this USB interface refer to the i MX31 data sheet Figure 3 15 shows this USB interface connection i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 19 ADS Operation ULPI CONTROL ISP1504 J1 i MX31 USB Device HOST USB MINI AB USBOTG HS EN B MIC2536 2BM Figure 3 15 USB OTG HS ULPI Interface 3 9 USB HOST ULPI Interface HS The ADS provides a USB High Speed 480M bps interface that uses a Phillips ISP1504 USB ULPI transceiver connected to a type A USB connector J4 It can also operate at Full Speed or Low Speed The interface can function only as a USB host The interface provides power on the USB bus This power may be supplied by the Phillips part or from the external 5 volt power source through a MIC2536 power switch For details on the operation of this USB interface refer to the i M X31 data sheet Figure 3 16 shows the USB HOST interface connection ULPI CONTROL ISP1105W J2 i MX31 USB Device AP3 AP6 USB TYPE A USB_HSH_EN MIC2536 2BM Figure 3 16 USB HS HOST ULPI Interface i MX31ADS User s Manual REV 1 Preliminary 3 20 Freescale Semiconductor ADS Operation 3 10 USB HOST Interface FS L
53. low zero SW3 1 User Defined SO OFF OFF OFF OFF OFF OFF OFF OFF 2 2 2 Base Board Jumper Headers The Base board has 26 jumper headers JP1 to JP8 J12 and J14 set ADS operational parameters JP9 to JP11 and JP13 are used as external signal headers JP15 to JP26 select voltage sources when MC13783 power management functions are used Table 2 4 describes the Base board jumpers Figure 2 2 shows the jumpers on the left side of the board Figure 2 3 shows the jumpers on the right side of the board Table 2 4 Base Board Jumper Headers Jumper Designation Fin 9 Connection JP1 FLAG output of Switcher JP2 FLAG output of Switcher E SERIAL LCD CS JPS je I2C1 Must be same as JP7 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 3 Configuring and Connecting the ADS Table 2 4 Base Board Jumper Headers continued Jumper Designation Connection Pin JP7 8 1 2 1 1 1 1 Pme Pme 3 2 LIGHT SENSE JP12 Keypad Light Sense JP13 I2C Connection 2 DAT SIGNAL GROUND JP14 182 Jumper 1 wire EEPROM programming enabled 1 Wire Enable No jumper 1 wire EEPROM programming disabled 18 32 NVCC 1 2 3 PM_VIOHI ine PM VIOLO NVCC 3 PM VIOHI JP17 NVCC 3 JP18 NVCC 3 JP19 NVCC 3 JP20 NVCC 4 JP21 NVCC 5
54. programmable output voltages The switching regulators feature voltage scaling that can be used to minimize power consumption Back up power control for part of the ARM core and SDRAM memory is also provided Be careful to follow the configuration guide in chapter 2 when installing this board Plugging in the APMB will disable all power regulators on the CPU board including the 3 3V one However if jumpers for NVCC power selections are left installed on the CPU MC13783 regulator outputs could be shorted Plugging in the MC13783 enables the 3 3V regulator on the Base board This regulator features a buck boost configuration which can maintain the 3 3V output even if the input voltage is below 3 3V In fact it is designed to operate from 4 5 volts down to 2 5 volts the useful range of most lithium batteries This combined with MC13783 capabilities allows the system to operate from an external source in the useful voltage range of most battery applications Using actual batteries is possible but not really practical because the current consumption of the system has not been optimized 3 26 Using the ETM Connectors Two connectors for connecting the ARM based i MX31 CPU to an ARM supplied ETM Embedded Trace Macrocell are provided Since this capability is normally needed only during development the ETM functions are pin shared with other modules Using these pins for ETM will prohibit their use with the other modules Having Main and Alternate ETM
55. scan a keypad B4 KPROW2 KEYPAD ROW 2 Bidirectional signal used to scan a keypad B5 KPROW1 KEYPAD ROW 1 Bidirectional signal used to scan a keypad B6 KPROWO KEYPAD ROW 0 Bidirectional signal used to scan a keypad B7 KPCOL5 KEYPAD COLUMN 5 Bidirectional signal used to scan a keypad B8 KPCOL4 KEYPAD COLUMN 4 Bidirectional signal used to scan a keypad 9 KCOL3 KEYPAD COLUMN 3 Bidirectional signal used to scan a keypad M9328MX31ADS User s Manual Rev 1 Preliminary 4 22 Freescale Semiconductor ADS Connectors and Signals Table 4 7 Extension Connector J17 Signal Description continued Pin Signal Description B10 KPCOL2 KEYPAD COLUMN 2 Bidirectional signal used to scan a keypad B11 KPCOL1 KEYPAD COLUMN 1 Bidirectional signal used to scan a keypad B12 KPCOLO KEYPAD COLUMN 0 Bidirectional signal used to scan a keypad B13 SRXD4 SYCHRONOUS AUDIO PORT RECEIVED DATA serial data input B14 SFS4 SYCHRONOUS AUDIO PORT FRAME SYNC Bidirectional output in master mode input in slave mode B15 KPCOL7 KEYPAD COLUMN 7 Bidirectional signal used to scan a keypad B16 KPCOL6 KEYPAD COLUMN 6 Bidirectional signal used to scan a keypad C1 GND GROUND C2 CSPI1 MOSI MASTER OUT SLAVE IN CSPI data signal bidirectional C3 CSPI1 MISO MASTER IN SLAVE OUT CSPI data signal bidirectional C4 R_
56. standard six contact SIMM socket Table 4 32 describes socket signals Table 4 32 SIMM Socket P8 Signal Description Pin Signal Description 1 NVCC9 POWER 2 SRSTO RESET 0 3 SCLKO SERIAL CLOCK 0 4 GND GROUND SIGNAL 5 VPP PROGRAMING POWER 6 STXO BIDIRECTIONAL DATA M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 47 ADS Connectors and Signals 4 2 20 Baseband Board Connector J24 is a 64 pin socket for an optional baseband board Figure 4 25 shows pin assignments Table 4 33 describes P3 signals TP58 TP56 NC NC NC NC NC CSPI2 550 CSPI2 SS1 CSPI3 MISO CSPI3 MOSI CSPI1 SPI RDY CSPI3 SCLK NC BB CSPI 551 BB CSPI MISO BB CSPI MOSI BB 550 GND BB_CSPI_CLK GND IPC_USB_VMOUT IPC_USB_VPOUT GND RCSPI1_SS2 GND IPC_USB_VMIN IPC_USB_VPIN GND R_CSPI_SCLK GND GND J24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CVDD_2 775V TP55 BB_SEC_INT PM_RSTMCU_B RST_OUT_B BB_VCC BB_STBY NC PM_RSTMCU_B PM_PWRRDY MP_RST_B PWR_FAIL LOWBAT NC BB_BUF_EN_B NC GND NC GND R_SCK3 GND R_SFS3 R_STXD3 R_SRXD3 GND GND CSPI3_MISO CSPI3 MOSI CSPI3 SCLK CSPI1 SPI RDY GND GND Figure 4 25 Baseband Board Connector J24 Pin Assignment M9328MX31A
57. 0 33 34 37 38 41 42 45 46 49 50 GND 53 54 57 58 61 62 SIGNAL GROUND 65 66 69 70 73 74 77 78 81 82 85 86 89 90 93 94 95 96 LBA_B 12 CONTROL MA10 59 DDR ADDRESS 3 4 71 72 75 76 NC 83 84 87 88 91 92 NOT CONNECTED 97 98 99 100 NFALE 56 NAND FLASH CONTROL NFCE_B 48 NAND FLASH CONTROL NFCLE 52 NAND FLASH CONTROL NFRE_B 60 NAND FLASH CONTROL NFWE_B 68 NAND FLASH CONTROL NFWP_B 64 NAND FLASH CONTROL OE_B 16 EMI CONTROL PW_B 79 CONTROL RW_B 20 EMI CONTROL WAIT_B 8 CONTROL M9328MX31ADS User s Manual Rev 1 Preliminary 4 62 Freescale Semiconductor GND NC GND AO GND Al GND A2 GND A3 GND A4 GND 5 GND A6 GND A7 GND A8 GND A9 GND A10 GND A11 GND A12 GND A13 GND A14 GND A15 GND NC GND NC GND BCLK GND NC GND NC GND NC GND GND NC NC o010 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 P6 98 ADS Connectors and Signals GND NC GND A16 GND A17 GND A18 GND A19 GND A20 GND A21 GND A22 GND A23 GND A24 GND A25 GND RST OUT B GND PM RSTMCU B GND PM RST B GND WATCHDOG RST GND M GRNT GND M_RQST GND NC GND NC GND PC_POE GND NC GND NC GND NC GND GND NC 100 NC Figure 4 33 Logic Analyzer Connector P6 Pin Assignment M9328MX31
58. 1 DCE Connectors DB9 connector P7A connects to UART transceiver which can be driven MCU UARTI or UART2 DB9 connector P7B connects to DUART channel A Header J7 connects to DUART channel B Figure 4 16 shows DB9 pin assignments and Table 4 20 describes connector signals Figure Figure 4 17 shows J7 pin assignments and Table 4 21 describes J7 signals M9328MX31ADS User s Manual Rev 1 Preliminary 4 38 Freescale Semiconductor ADS Connectors and Signals Figure 4 16 RS 232 DCE Connectors P7A and P7B Pin Assignment Table 4 20 RS 232 DCE Connectors P7A and P7B Signal Description Pin Signal Description 1 CD CARRIER DETECT RS 232 output signal pulled active positive 2 TXD TRANSMITTED DATA RS 232 serial data output signal 3 RXD RECEIVED DATA RS 232 serial data input signal 4 DTR DATA TERMINAL READY RS 232 input signal the logic level signal is available at TP8 5 GND GROUND 6 DSR DATA SET READY RS 232 output signal pulled active positive 7 RTS READY TO SEND RS 232 input signal active positive 8 CTS CLEAR TO SEND 5 232 output signal active positive 9 RI RING INDICATOR RS 232 output signal forced inactive negative J7 EXT UB DCD 1 2 EXT UB RXD EXT UB TXD 3 4 EXT UB DTR GND 5 6 EXT UB DSR EXT UB RTS 7 8 5 9 e 10 GND Figure 4 17 RS 232 DCE Connector J7 Pin
59. 113 202 201 204 203 205 115 117 116 118 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 206 208 207 210 209 154 153 156 155 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 212 211 214 213 215 IPU_LD16 IPU LD15 IPU LD14 IPU_LD13 IPU_LD12 IPU_LD11 IPU_LD10 IPU_LD9 IPU_LD8 GND GND GND NVCC7 IPU_LD7 IPU_LD6 IPU_LD5 IPU_LD4 IPU_LD3 IPU_LD2 IPU_LD1 IPU_LDO GND CSI D15 CSI D14 CSI D13 CSI D12 CSI D11 CSI D10 CSI D9 CSI D8 NVCCA GND GND NVCCA CSI D7 CSI D6 CSI D5 CSI D4 GPIO3 0 1 GND DSR_DCE1 DCE1 DCD DCE1 DTR DCE1 DCD DTE1 DTR DCE2 DTE1 DTR DTE1 DSR_DTE1 NVCC8 NVCC8 GND GND GND 54 BEBO B BEB1 B BOE B BRW B PC CE1 B PC CE2 B PC OE B BPC POE GND GND 3V3 3V3 KPROWO KPROW1 KPROW2 KPROWS KPROW4 KPROW5 KPROW6 KPROW7 GND GND NC CARD2_SEL_B CARD1_SEL_B MSHC2_DET MSHC2 DET PM VGEN PM VGEN GND GND GND PM VDIG PM VDIG NF DET B GND CLKO GND GPIO1 0 GPIO1 1 GPIO1 2 GPIO1 3 GPIO1 4 GPIO1 5 GPIO1 6 GND RGST M GRNT ATLAS IN DVDD_1 8V DVDD_1 8V GND GND 98 97 100 99 102 101 104 103 106 105 108 107 110 109 112 111 114 113 202 201 204 203
60. 13 202 201 204 203 205 115 117 116 118 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 206 208 207 210 209 154 153 156 155 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 212 211 214 213 215 NC ADOUT LOWBAT NC PM_VCAM PM_VCAM NC PWGT2_OUT PWGT2_OUT GND GND GND PM_VGEN PM_VGEN NC NC NC NC NC NC NC NC NC NC NC PM_WDOG_RST VSIM_EN GND NC GND NC GND GND STXD5 SRXD5 SFS5 SCK5 NC NC PM_VRF1 PM_VRF1 PWGT1_EN PM_BP PM_BP PWGT2_EN VESIM_EN PM_MEM_CS PM_VBLITE PM_VBLITE NC VSD1 VSD1 GND GND GND Figure 4 4 Base Board to MC13783 Board Connectors P5 and P6 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary 4 16 Freescale Semiconductor ADS Connectors and Signals Table 4 4 Base Board to MC13783 Board Connector P5 Signal Description Signal Pin Description 3V3 185 187 189 3 VDC POWER 5V 69 71 73 75 5 VDCPOWER 3 4 13 17 22 26 34 40 48 79 150 154 GND 155 158 161 SIGNAL GROUND 167 171 177 191 215 1 2 5 12 14 16 18 21 23 25 27 32 36 38 39 41 45 47 52 54 56 58 60 62 64 66 68
61. 2 775 VDC POWER 5 2 CE BUS INTERRUPT 2 6 CE_INT1 CE BUS INTERRUPT 1 7 DCD_DCE1 UART1 DCE signal DCD 8 RI_DCE1 UART1 DCE signal Ring Indicator 9 DCD_DCE2 UART1 DCE signal DCD 10 DTR_DCE1 UART1 DCE signal DTR 11 UART1_RTS UART 1 READY TO SEND 12 UART1_CTS UART1 CLEAR TO SEND 13 UART1_TXD UART1 TRANSMIT DATA 14 UART1_RXD UART1 RECEIVE DATA 4 2 17 SD MMC Connectors P3 and P4 are SD MMC connectors Figure 4 24 shows pin assignments Table 4 29 describes P3 signals Table 4 30 describes P4 signals p 12 14 Figure 4 24 SD MMC Connector Pin Assignments M9328MX31ADS User s Manual Rev 1 Preliminary 4 44 Freescale Semiconductor ADS Connectors and Signals Table 4 29 SD MMC Connector P3 Signal Description Description Pin s Signal SD Card MMC Card 1 Bit Mode 4 Bit Mode 1 8501 DATA LINE 3 Not Used DATA LINE 3 2 SD1 CMD COMMAND RESPONSE 3 GND SIGNAL GROUND 4 VDD 3 VDC POWER selectable VSD2 or 3V3 5 SD1 CLK CLOCK INPUT 6 GND SIGNAL GROUND 7 8501 DATAO DATA LINE 0 8 501 DAT1 DATA LINE 1 INTERRUPT IRQ DATA LINE 1 or IRQ 9 SD1 DAT2 DATA LINE 2 READWAIT RW DATA LINE 2 or RW 10 SD1 DET CARD DETECT 11 GND GROUND 12 NC NO CONNECTION 18 NC NO CONNECTION 14 NC NO CONNECTION 15 NC NO CONNECTION 16 SD WP WRITE PROTECT DETECT
62. 2 MAIN DISPLAY LIGHT EMMITING DIODE 30 LED MD3 MAIN DISPLAY LIGHT EMMITING DIODE 31 LED MD4 MAIN DISPLAY LIGHT EMMITING DIODE 32 NC NOT CONNECTED 33 GND SIGNAL GROUND 34 CVDD 2 775V 2 775 VDC SUPPLY 35 LED KP KEYPAD LIGHT EMMITING DIODE 36 NC NOT CONNECTED 37 DVDD 1 8V 1 8 VDC SUPPLY 38 NVCC7 5 VDC SUPPLY 39 GPIO1 GENERAL PURPOSE I O LINE 1 40 GPIO2 GENERAL PURPOSE LINE 2 M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 31 ADS Connectors and Signals J8 IPU_VSYNCHO 1 2 100 IPU LD1 3 4 LD2 103 5 6 IPU 104 IPU 105 7 8 1017 108 9 e 10 107 106 11 e 12 PAR LCDRSTO 13 14 109 15 16 3V3 11 17 e 18 1010 LD13 19 20 GND LD15 21 22 1012 IPU_LLCSO 23 24 LD14 25 e 26 1016 LED MD1 27 e e 28 VBLITE LED MD2 29 e 30 LED LED 4 31 32 NC GND 33 34 CVDD_2 775V LED 35 e 36 NC DVDD 1 8V 37 e 38 NVCC7 GPIO1 39 40 2 Figure 4 10 Parallel LCD Connector II J8 Pin Assignment Table 4 14 Parallel LCD Connector J8 Signal Description Pin Signal Description 1 VSYNCHO VERTICAL SYNCH 0 2 IPU LDO LCD DATA 0 3 IPU LD1 LCD DATA 1 4 IPU
63. 2 Speaker Terminals provides two screw terminals for left and right channel analog stereo speaker output signals SPOUT 1 and SPOUT2 M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 35 ADS Connectors and Signals Table 4 17 Audio Jack Signal Description Termination Jack 1 2 3 4 5 25 NC NC NC TXOUT GND 26 NC NC NC EXTOUT GND 27 HPOUTL NC NC HPOUTR GND 28 NC NC NC RXIN GND 29 NC NC NC EXTIN GND Signal Description TXOUT TX OUT EXTOUT ANALOG LINE OUT HPOUTL HEADPHONE ANALOG OUTPUT LEFT HPOUTR HEADPHONE ANALOG OUTPUT RIGHT RXIN RX IN EXTIN ANALOG LINE IN 4 2 8 Television Encoder Connector P13 is the TV encoder connector Figure 4 14 shows pin assignments and Table 4 18 describes the signals P13 VCC 15 552 P5V I2C 14 NC 2 DATA 5555 6 NC GND 7 8 GND CLK_26M 9 e 10 GND Figure 4 14 Encoder Connector P13 Pin Assignment Table 4 18 TV Encoder Connector P13 Signal Description Pin Signal Description 1 VCC 3 VDC POWER 2 P5V 5 VDC POWER 3 2 2 CLOCK Serial clock bidirectional 4 NC NO CONNECTION 5 2 DATA I2 C DATA Serial data bidirectional 6 NC NO CONNECTION 7 GND SIGNAL GROUND 8 GND SIGNAL GROUND 9 CLK 26M 26 MHz CLOCK 8 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary 4 36
64. 24 KEYPAD ROW SELECT KPROWS3 126 KEYPAD ROW SELECT KPROWA 128 KEYPAD ROW SELECT KPROW5 130 KEYPAD ROW SELECT KPROW6 132 KEYPAD ROW SELECT KPROW7 134 KEYPAD ROW SELECT M GRNT 184 EMI CONTROL SIGNAL MASTER GRANT M RQST 182 EMI CONTROL SIGNAL MASTER REQUEST MSHC2 DET 146 MEMORY STICK 2 DETECT MSHC1 DET 148 MEMORY STICK 1 DETECT 43 49 81 NC 89 140 NOT CONNECTED NF DET B 158 NAND FLASH DETECT NVCC1 187 189 CONDITIONED POWER SUPPLY NVCC2 1 3 5 CONDITIONED POWER SUPPLY NVCC6 115 117 CONDITIONED POWER SUPPLY NVCC9 149 151 CONDITIONED POWER SUPPLY PC_CE1_B 108 PCMCIA CARD ENABLE1 PC_CE2_B 110 PCMCIA CARD ENABLE2 PC_OE_B 112 PCMCIA OUTPUT ENABLE PC_POE 71 PCMCIA OUTPUT ENABLE PM_BKUP_DDR 39 POWER MANAGEMENT DDR BACKUP PM_BKUP_DDR 41 POWER MANAGEMENT DDR BACKUP 2 177 POWER MANAGEMENT BOARD 32 KHz MCU CLOCK PM_MEM_CS 185 POWER MANAGEMENT MEMORY CHIP SELECT PM_RST_B 173 POWER MANAGEMENT RESET PM_RSTMCU_B 183 POWER MANAGEMENT MCU RESET PM_SW1A 67 POWER MANAGEMENT PM_SW1A 69 POWER MANAGEMENT PM_VDIG 154 POWER MANAGEMENT PM_VDIG 156 POWER MANAGEMENT PM_VGEN 150 POWER MANAGEMENT PM_VGEN 152 POWER MANAGEMENT PWGT1_EN 157 POWER GATE 1 ENABLE M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 13 ADS Connectors and Signals Table 4 3 Base Board to CPU Board Connector P2 Signal Description continued
65. 3 20 USB HS HOST Int rface ra ri an o cerae ee oes 3 20 USB FS LS HOST ME S QU RR REESE 3 2 UARTS and IrDA Interface e RR AA 3 22 Etheruet Interface Jevy ome om rung deir dp ed Lada 3 23 Base Board Connectors Left Side 4 3 Base Board Connectors Right Side 4 4 Base Board to CPU Board Connectors P1 and P2 Pin Assignment 4 6 Base Board to MC13783 Board Connectors P5 and P6 Pin Assignment 4 16 Image Sensor and Extension Connector Pin Numbering 4 21 External Keypad Connector P5 Pin 4 26 Synchronous LCD Connector J12 Pin Assignment 4 28 Option Connector Pin 4 29 Parallel LCD Connector I J9 Pin 4 30 Parallel LCD Connector II J8 Pin 4 32 Serial Asynchronous LCD Connector J6 Pin 4 33 Funlight Connector J20 Pin 4 34 i MX31ADS User s Manual REV 1 Preliminary List of Figures Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Fig
66. 5 13 BNFRB NAND FLASH READY BUSY 14 BD14 BIDIRECTIONAL DATA 14 15 BDO BIDIRECTIONAL DATA 0 16 BD13 BIDIRECTIONAL DATA 13 17 BD1 BIDIRECTIONAL DATA 1 18 BD12 BIDIRECTIONAL DATA 12 19 BD2 BIDIRECTIONAL DATA 2 20 BD11 BIDIRECTIONAL DATA 11 21 BD3 BIDIRECTIONAL DATA 3 22 BD10 BIDIRECTIONAL DATA 10 23 BD4 BIDIRECTIONAL DATA 4 24 BD9 BIDIRECTIONAL DATA 9 25 BD5 BIDIRECTIONAL DATA 5 26 BD8 BIDIRECTIONAL DATA 8 27 BD6 BIDIRECTIONAL DATA 6 28 30 GND GROUND 29 BD7 BIDIRECTIONAL DATA 7 M9328MX31ADS User s Manual Rev 1 Preliminary 4 72 Freescale Semiconductor 4 3 7 ADS Connectors and Signals Memory Stick Connectors J5 and J6 on the CPU board allows the ADS to interface Memory Stick modules Table 4 48 describes J5 signals Table 4 49 describes J6 signals Table 4 48 Memory Stick Connector J5 Signal Description Pin Signal Description 1 GND SIGNAL GROUND 2 MSHC1_BS MS 1 3 MSHC1_DATA 1 MS 1 DATA 1 4 MSHC1 DATAO MS 1 DATA 0 5 MSHC1 DATA2 MS 1 DATA 2 6 MSHC1_DET MS 1 DETECT 7 MSHC1 DATA3 MS 1 DATA3 8 MSHC1_SCLK MS 1 SERIAL CLOCK 9 VSD1 MS 1 POWER 10 GND SIGNAL GROUND Table 4 49 Memory Stick Connector J6 Signal Description Pin Signal Description 1 GND SIGNAL GROUND 2 MSHC2_BS MS 2 3 MSHC2_DATA 1 MS 2 DATA 1 4 MSHC2 DATAO MS 2 DATA 0 5 MSHC2 DATA2 MS 2 DATA 2 6 MSHC2_DET MS
67. 5 3 55 4 Function ON OFF ON ChargeSCt ON OFF OFF OFF Hold charge ON OFF OFF ON Discharge SC1 OFF ON OFF OFF External Li Cell CN9 2 4 1 4 S6 USB Buffer Control Switch Two of the four SPST slide switches in S6 control the MC13783 USB interface buffers Table 2 9 shows the valid switch combinations CAUTION To avoid damage to the ADS use only the valid switch settings Table 2 9 MC13783 Board SW6 USB UDATVP and USBOVM Direction Select S6 1 S6 2 S6 3 S6 4 Function OFF OFF X X DO NOT USE OFF ON X X Buffer drives from MC13783 to ADS ON OFF X X UTXENB controls buffer direction i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 13 Configuring and Connecting the ADS Table 2 9 MC13783 Board SW6 USB UDATVP and USBOVM Direction Select ON ON X X DO NOT USE 2 4 1 5 S7 Audio Buffer Enable and Direction Select Switch Pairs of the six SPST slide switches in S7 enable the on board audio buffers and determine the direction of data Table 2 10 shows the valid switch combinations CAUTION To avoid damage to the ADS use only the valid switch settings Table 2 10 MC13783 Board SW7 Buffer Enable and Direction Select S7 1 67 2 57 3 57 4 57 5 57 6 Function ON OFF GPO1_BUFF controls FS1 and BCL1 buffer direction OFF ON FS1 and BCL1 buffers drive from MC13783 to ADS OFF OFF FS1 and BCL1 buffe
68. 6 5 4 3 2 1 0 FIELD VESIM VSIM SYNTH CARD2 CARD1 Apa ea FSH_ HSH_ HSH_ FSH_ FSH a Mur RESET EN EN RST SEL SEL EN EN 5 EN MOD EN 5 SEL SEL OPER R W R W R W R W R W R W R W R W RW R W R W R W RW R W RESET 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 OUT OUT OUT OUT OUT IN OUT OUT OD OD OUT OUT OUT OD OD OD OUT OUT OUT OUT OUT OUT OUT Figure 3 7 Board Control Register 3 BCTRL3 Table 3 10 Board Control Register 3 Bit Definitions Name Description Setting OTG_FS_SEL 5 OTG Full Speed Select Select source of the 0 MC13783 board Bit 0 USB OTG Full speed interface 1 CPU OTG_FS_EN USB OTG Full Speed Enable Enable the USB 0 OTG Full Speed Interface enabled Bit 1 OTG Full speed interface on the CPU 1 OTG Full Speed Interface disabled FSH_SEL USB Full Speed Host Select Select source of the 0 Group A on the CPU Bit 2 USB Full speed Host interface 1 Group B on the CPU FSH_EN USB Full Speed Host Enable Enable the USB Full 0 Full Speed Host Interface enabled Bit 3 speed Host interface 1 Full Speed Host Interface disabled HSH_SEL USB High Speed Host Select Select The source 0 Group A on the CPU Bit 4 of the USB High speed Host interface 1 Group B on the CPU HSH_EN USB High Speed Host Enable Enable the USB 0 High Speed Host Interface enabled Bit 5 High speed Host interface 1 High Speed Host Interface disabled FSH MODE USB
69. A B Combination setting must match JMP6 Set JMP11 Power Select typically set for operation from on board regulator U4 Set USB Mode Selection Switches S4 1 to S4 4 Set Backup Source Selection Switches S5 1 to 55 4 typically 55 1 55 2 OFF 55 3 55 4 OFF 10 Set USB Buffer Direction Selection Switches S6 1 to S6 2 typically S6 1 ON S6 2 OFF 11 Set Buffer Enable and Direction Selection Switches S7 1 to S7 6 typically S7 1 OFF S7 2 ON 57 3 OFF 57 4 S7 5 OFF 57 6 OFF 12 Set CLIA CLIB Source Selection Switches S8 1 to S8 6 typically S8 1 ON S8 4 ON all others OFF 13 Set Power Up Mode Selection Switches S9 1 to S9 6 typically S9 1 ON S9 2 OFF S9 3 ON S9 4 OFF S9 5 ON S9 6 OFF O 4 QM aoe i MX31ADS User s Manual REV 1 Preliminary 2 20 Freescale Semiconductor Configuring and Connecting the ADS 2 5 11 Connect the MC13783 Board to the Base Board 1 Make sure the power jumpers on the Base board are correctly configured 2 Install the MC13783 board as shown in Figure 2 9 the connection is keyed so that it cannot be connected incorrectly Figure 2 9 Connecting the MC13783 Board to the Base Board 2 5 12 Connect Power to the CPU Board 1 Connect the female end of the A C cable to the power supply module 2 Attach any necessary power adaptor plugs to power supply module plug it into an A C outlet 3 Connect the barrel connector into J3 on the CPU board 2 5
70. ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 63 ADS Connectors and Signals Table 4 41 Logic Analyzer Connector P6 Signal Description Signal Pin Description AO 7 EMI ADDRESS Al 11 EMI ADDRESS A2 15 EMI ADDRESS 19 ADDRESS 4 23 EMI ADDRESS A5 27 EMI ADDRESS A6 31 EMI ADDRESS A7 35 EMI ADDRESS A8 39 EMI ADDRESS AQ 43 EMI ADDRESS A10 47 EMI ADDRESS 11 51 ADDRESS 12 55 ADDRESS 13 59 ADDRESS 14 63 EMI ADDRESS A15 67 EMI ADDRESS A16 8 EMI ADDRESS A17 12 EMI ADDRESS A18 16 EMI ADDRESS A19 20 EMI ADDRESS A20 24 EMI ADDRESS A21 28 EMI ADDRESS A22 32 EMI ADDRESS A23 36 EMI ADDRESS A24 40 EMI ADDRESS A25 44 EMI ADDRESS BCLK 79 BUFFERED CLOCK 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 30 33 34 37 38 41 42 45 46 49 50 GND 53 54 57 58 61 62 SIGNAL GROUND 65 66 69 70 73 74 77 78 81 82 85 86 89 90 93 94 95 96 M GRNT 64 EMI CONTROL M RQST 68 EMI CONTROL MA10 59 DDR ADDRESS 3 4 71 72 75 76 NC 83 84 87 88 91 92 NOT CONNECTED 97 98 99 100 PC POE 80 PCMCIA CONTROL PM RST B 56 PCMCIA CONTROL PM RSTMCU B 52 POWER MANAGEMENT MCU RESET RST OUT B 48 RESET OUT Active low reset signal from the MCU WATCHDOG RST 60 WATCHDOG RESET M9328MX31ADS User s Manual Rev 1 Preliminary 4 64
71. Address Connector P10 Pin Assignment 4 52 CPLD Programming Connector J14 Pin 4 54 CPU Board oS Oeo haa TER EM E nva e a add 4 56 Logic Analyzer Connector P2 Pin 4 57 Logic Analyzer Connector Pin 4 59 Logic Analyzer Connector P5 Pin 4 61 Logic Analyzer Connector Pin 4 63 Primary ETM Connector Pin 4 65 Alternate ETM Connector Pin 4 67 RV ICE JTAG Connector 78 Pin Assignment 4 69 PC Test Connector Pin 4 70 ISP Connector J7 Pin Assignment 4 7 NAND Flash Connector J9 Pin 4 71 MC13783 Board Connectors dese ay RUE 4 75 Audio Jack DISSrati oil RE Ene Sas o SELL 4 76 USB Connector CN3 Pin 4 77 Touchscreen Connector CN8 Pin 4 77 i MX31ADS User s Manual
72. BUFFERED ADDRESS 18 34 B_A2 BUFFERED ADDRESS 2 35 B_A17 BUFFERED ADDRESS 17 36 1 BUFFERED ADDRESS 1 37 B_A16 BUFFERED ADDRESS 16 38 B_AO BUFFERED ADDRESS 0 39 43 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 53 ADS Connectors and Signals TCK TMS TDI TDO NC gt Iv GND GND 3V3 GND NC Figure 4 28 CPLD Programming Connector J14 Pin Assignment Table 4 36 CPLD Programming Connector J14 Signal Description Pin Signal Description 1 TCK JTAG CLOCK 2 GND SIGNAL GROUND 3 TMS JTAG MODE 4 GND SIGNAL GROUND 5 TDI JTAG DATA IN 6 3V3 3 VDC POWER 7 TDO JTAG DATA OUT 8 GND SIGNAL GROUND 9 NC NO CONNECTION 10 NC NO CONNECTION M9328MX31ADS User s Manual Rev 1 Preliminary 4 54 Freescale Semiconductor ADS Connectors and Signals 4 3 CPU Board Connectors Table 4 37 shows the CPU board connectors Table 4 29 shows connector layout on the board See paragraph 4 2 for information about CPU board connectors J1 and J2 which mate with connectors and P2 of the Base board Table 4 37 CPU Board Connectors Connector Type Description J1 215 pin Base CPU 1 see Base board for connector description J2 215 pin Base CPU 2 see Base board for connector description J3 DIN ADS Power Input J4 10 pin header PC Test J5 Memory Card Memory
73. BUFFERED DATA MCU data bus B D11 30 BUFFERED DATA MCU data bus B D12 32 BUFFERED DATA MCU data bus B D13 34 BUFFERED DATA MCU data bus B D14 36 BUFFERED DATA MCU data bus M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 3 Base Board to CPU Board Connector P2 Signal Description continued Signal Pin Description B_D15 38 BUFFERED DATA MCU data bus BBCLK 85 BASE BOARD CLOCK BCSO 113 BUFFERED CHIP SELECT BCS1_B 111 BUFFERED CHIP SELECT BCS4_B 98 BUFFERED CHIP SELECT BCS5_B 109 BUFFERED CHIP SELECT BEBO_B 100 BUFFERED BITE ENABLE BEB1_B 102 BUFFERED BITE ENABLE BLBA_B 95 BUFFERED LOAD BASE ADDRESS BOE_B 104 BUFFERED OUTPUT ENABLE BPC_POE 114 PCMCIA OUTPUT ENABLE BRW_B 106 BUFFERED READ WRITE CARD1_SEL_B 144 MEMORY STICK1 CARD SELECT CARD2_SEL_B 142 MEMORY STICK2 CARD SELECT CLKO 162 CLOCK OUT CPU_BRD_VERO 99 CPU BOARD VERSION CPU BRD VER1 101 CPU BOARD VERSION CPU BRD VER2 103 CPU BOARD VERSION CPU BRD VERS 105 CPU BOARD VERSION CSPH MISO 27 MASTER IN SLAVE OUT CSPI data signal bidirectional CSPI1_MOSI 29 MASTER OUT SLAVE IN CSPI data signal bidirectional CSPI1_SCLK 25 SERIAL CLOCK Bidirectional CSPI1_SPI_RDY 37 READY CSPI serial burst trigger active low input CSPI1_SSO 35 SLAVE SELECT 0
74. C GND NC GND RW B GND NC GND NC GND NC GND GND NC NC 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 P5 98 GND NC GND WAIT_B GND LBA_B GND OE_B GND RW_B GND CS0 B GND GND CS4_B GND CS5_B GND EBO B GND EB1 B GND NFCE B GND NFCLE GND NFALE GND NFRE B GND NFWP B GND NFWE B GND NC GND NC GND CLKO GND NC GND NC GND NC GND GND NC 100 NC Figure 4 32 Logic Analyzer Connector P5 Pin Assignment ADS Connectors and Signals M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 61 ADS Connectors and Signals Table 4 40 Logic Analyzer Connector P5 Signal Description Signal Pin Description CLKO 80 CLOCK OUT 50 24 BUFFERED CHIP SELECT CS1 B 28 BUFFERED CHIP SELECT 54 B 32 BUFFERED CHIP SELECT CS5 B 36 BUFFERED CHIP SELECT DO 7 EMI DATA D1 11 EMI DATA D2 15 EMI DATA D3 19 EMI DATA D4 23 EMI DATA D5 27 EMI DATA D6 31 EMI DATA D7 35 EMI DATA D8 39 EMI DATA D9 43 EMI DATA D10 47 EMI DATA D11 51 EMI DATA D12 55 EMI DATA D13 59 EMI DATA D14 63 EMI DATA D15 67 EMI DATA EBO B 40 EMI CONTROL EB1 B 44 EMI CONTROL 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 3
75. CE signal Ring Indicator C15 DCD_DCE1 UART1 DCE signal DCD C16 3V3 3 VDC power 4 2 4 External Keypad Connector P5 is a connector for the ADS external keypad Figure 4 6 shows pin assignments and Table 4 10 describes connector signals P5 VCC 1 e o 2 NC UART2 RXD 4 2 5 UART2_TXD 5 ee 6 UART2 CTS KP COL5 7 8 5 KP 4 9 ee 10 KP 4 KP COL3 11 o 12 ROWS KP COL2 13 o 14 ROW2 KP COL1 15 e 16 1 KP COLO 17 o 18 KP ROWO NC 19 20 GND Figure 4 6 External Keypad Connector P5 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary 4 26 Freescale Semiconductor ADS Connectors and Signals Table 4 10 External Keypad Connector P5 Signal Description Pin Signal Description 1 3 volt power 2 NC NO CONNECTION 3 127 KEYPAD COLUMN 7 Bidirectional signal used to scan a keypad 4 221 KEYPAD ROW 6 Bidirectional signal used to scan a keypad 5 ME a KEYPAD COLUMN 6 Bidirectional signal used to scan a keypad 6 2 KEYPAD ROW 7 Bidirectional signal used to scan a keypad 7 KP_COL5 KEYPAD COLUMN 5 Bidirectional signal used to scan a keypad 8 KP_ROW5 KEYPAD ROW 5 Bidirectional signal used to scan a keypad 9 KP_COL4 KEYPAD COLUMN 4 Bidirectional signal used to scan a keypad 10 KP_ROW4 KEYPAD ROW 4 Bidirectional signal use
76. CSPI1_SCLK SERIAL CLOCK Bidirectional C5 550 SLAVE SELECT 0 CSPI signal bidirectional C6 R_CSPI1_SS1 SLAVE SELECT 1 CSPI signal bidirectional C7 552 SLAVE SELECT 2 CSPI signal bidirectional C8 R_CSPI1_RDY READY CSPI serial burst trigger active low input C9 SCK3 SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK Bidirectional output in master mode and input in slave mode C10 R_STXD3 SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA Serial output signal C11 R_SRXD3 SYCHRONOUS SERIAL INTERFACE RECEIVED DATA Serial input signal C12 R_SFS3 SYCHRONOUS SERIAL INTERFACE FRAME SYNC C13 SYCHRONOUS AUDIO PORT CLOCK Serial transmit clock bidirectional output in master mode input in slave mode C14 R_STXD4 SYCHRONOUS AUDIO PORT TRANMITTED DATA Serial data output C15 NC NOT CONNETED C16 3V3 3 VDC power M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 23 ADS Connectors and Signals Table 4 8 Extension Connector J22 Signal Description Pin Signal Description 1 CSPI2 MOSI MASTER OUT SLAVE IN CSPI data signal bidirectional A2 CSPI2 MISO MASTER IN SLAVE OUT CSPI data signal bidirectional CSPI2 SCLK SERIAL CLOCK Bidirectional A4 CSPI2 SSO SLAVE SELECT 0 CSPI signal bidirectional
77. D A12 DTR_DCE2 UART2 DCE signal DTR A13 NC NO CONNECTION A14 CSP12 SPI RDY SERIAL PERIPHERAL INTERFACE READY A15 NC NO CONNECTION A16 NC NO CONNECTION B1 NC NO CONNECTION B2 SCLKO SERIAL CLOCK 0 B3 SRSTO SERIAL RESET 0 B4 SVENO SERIAL ENABLE 0 B5 STXO SERIAL TRANSMIT 0 B6 CPLD SPO CUSTOM PROGRAMMED LOGIC DEVICE SP 0 B7 SIMPDO SIM CARD PRESENCE DETECT B8 GENERAL PURPOSE I O PORT 1 LINE 0 M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 25 ADS Connectors and Signals Table 4 9 Extension Connector J23 Signal Description continued Pin Signal Description 9 GPIO1_1 GENERAL PURPOSE I O PORT 1 LINE 1 B10 GPIO1_2 GENERAL PURPOSE I O PORT 1 LINE 2 B11 GPIO1_3 GENERAL PURPOSE I O PORT 1 LINE 3 B12 GPIO1_4 GENERAL PURPOSE I O PORT 1 LINE 4 B13 GPIO1 5 GENERAL PURPOSE I O PORT 1 LINE 5 B14 GPIO1 6 GENERAL PURPOSE I O PORT 1 LINE 6 B15 GPIO3_0 GENERAL PURPOSE I O PORT 3 LINE 0 B16 GPIO3_1 GENERAL PURPOSE I O PORT 3 LINE 1 C1 GND GROUND C2 NC NO CONNECTION C3 NC NO CONNECTION C4 NC NO CONNECTION C5 NC NO CONNECTION C6 NC NO CONNECTION C7 NC NO CONNECTION C8 NC NO CONNECTION C9 NC NO CONNECTION C10 OWDAT One Wire Data signal C11 RST OUT B RESET OUT Active low reset signal from the processor C12 DTR DCE1 UART1 DCE signal DTR C13 DSR_DCE1 UART1 DCE signal DSR C14 RI_DCE1 UART1 D
78. D NC GND NC GND TP5 GND NC GND NC GND NC GND GND NC NC 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 P2 98 GND NC GND DQ16 GND DQ17 GND DQ18 GND DQ19 GND DQ20 GND DQ21 GND DQ22 GND DQ23 GND DQ24 GND DQ25 GND DQ26 GND DQ27 GND DQ28 GND DQ29 GND DQ30 GND DQ31 GND NC GND NC GND TP6 GND NC GND NC GND NC GND GND NC 100 NC Figure 4 30 Logic Analyzer Connector P2 Pin Assignment ADS Connectors and Signals M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 57 ADS Connectors and Signals Table 4 38 Logic Analyzer Connector P2 Signal Description Signal Pin Description DQ16 8 DDR DATA DQ17 12 DDR DATA DQ18 16 DDR DATA DQ19 20 DDR DATA DQ20 24 DDR DATA DQ 1 28 DDR DATA DQ22 32 DDR DATA DQ23 36 DDR DATA DQ24 40 DDR DATA DQ25 44 DDR DATA DQ26 48 DDR DATA DQ27 52 DDR DATA DQ28 56 DDR DATA DQ29 60 DDR DATA DQ30 64 DDR DATA DQ31 68 DDR DATA DQS2 63 DDR CONTROL DQS3 67 DDR CONTROL 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 30 33 34 37 38 41 42 45 46 49 50 53 GND 54 57 58 61 62 GROUND SIGNAL 65 66 69 70 73 74 77 78 81 82 85 86 89 90
79. D 2 775V CONDITIONED POWER SUPPLY C15 NC NO CONNECTION C16 3V3 3 VDC POWER Table 4 7 Extension Connector J17 Signal Description Pin Signal Description 1 R_SD1_CLK SD MMC CLOCK Clock output to SD MMC card A2 R_SD1_CMD SD MMC COMMAND Serial command bit to SD MMC card bidirectional A3 R_SD1_DATA3 SD MMC DATA BIT 3 Serial data bit to SD MMC card bidirectional A4 SD1 DATA2 SD MMC DATA BIT 2 Serial data bit to SD MMC card bidirectional A5 R_SD1_DATA1 SD MMC DATA BIT 1 Serial data bit to SD MMC card bidirectional A6 R_SD1_DATAO SD MMC DATA BIT 0 Serial data bit to SD MMC card bidirectional A7 UART1_RTS UART1 REQUEST TO SEND Active low input signal A8 UART1_CTS UART1 CLEAR TO SEND Active low output signal AQ UART1_RXD UART1 RECEIVED DATA Serial input signal A10 UART1_TXD UART1 TRANSMITTED DATA Serial output signal 11 UART2_RTS UART2 REQUEST TO SEND Active low input signal 12 UART2 CTS UART2 CLEAR TO SEND Active low output signal A13 UART2_RXD UART2 RECEIVED DATA Serial input signal 14 UART2_TXD UART2 TRANSMITTED DATA Serial output signal A15 KPROW7 KEYPAD ROW 7 Bidirectional signal used to scan a keypad A16 KPROW6 KEYPAD ROW 6 Bidirectional signal used to scan a keypad B1 KPROW5 KEYPAD ROW 5 Bidirectional signal used to scan a keypad B2 KPROW4 KEYPAD ROW 4 Bidirectional signal used to scan a keypad B3 KPROW3 KEYPAD ROW 3 Bidirectional signal used to
80. DDRESS 6 24 PC A5 ADDRESS 5 25 PC A4 ADDRESS 4 26 PC A3 ADDRESS 3 27 PC A2 ADDRESS 2 28 PC A1 ADDRESS 1 29 PC 0 ADDRESS 0 30 PC DO DATA 0 31 PC D1 DATA 1 32 PC D2 DATA 2 33 IOIS16 WP PCMCIA control signal 34 GND SIGNAL GROUND 35 GND SIGNAL GROUND 36 R PC CD1 B PCMCIA Card Detect 1 37 PC D11 DATA 11 38 PC D12 DATA 12 39 PC D13 DATA 13 40 PC D14 DATA 14 41 PC D15 DATA 15 42 PC CE2 B PCMCIA CARD ENABLE2 M9328MX31ADS User s Manual Rev 1 Preliminary 4 46 Freescale Semiconductor ADS Connectors and Signals Table 4 31 PCMCIA Connector U30 Signal Description continued Pin Signal Description 43 VS1 PCMCIA Voltage Sense 1 signal 44 IORD B INPUT OUTPUT READ 45 IOWR B INPUT OUTPUT WRITE 46 PC A17 ADDRESS 17 47 PC A18 ADDRESS 18 48 PC A19 ADDRESS 19 49 PC A20 ADDRESS 20 50 PC A21 ADDRESS 21 51 VCC SWITCHED POWER 52 VPP SWITCHED POWER 53 PC A22 ADDRESS 22 54 PC A23 ADDRESS 23 55 PC A24 ADDRESS 24 56 PC A25 ADDRESS 25 57 VS2 PCMCIA Voltage Sense 2signal 58 RST PC PCMCIA RESET 59 WAIT PCMCIA WAIT 60 NC NO CONNECTION 61 REG B PCMCIA REGISTER ACCESS OUTPUT 62 BVD2 PCMCIA Battery Voltage Detect 2 63 BVD1 PCMCIA Battery Voltage Detect 1 64 PC D8 DATA 8 65 PC D9 DATA 9 66 PC D10 DATA 10 67 R PC CD2 B PCMCIA Card Detect 2 68 GND SIGNAL GROUND 69 88 NC NO CONNECTION 4 2 19 SIMM Socket P8 is a
81. DS User s Manual Rev 1 Preliminary 4 48 Freescale Semiconductor Table 4 33 Baseband Board Connector J24 Signal Description ADS Connectors and Signals Pin Signal Description 1 TP58 TEST POINT 58 2 CVDD_2 775V 2 775 VDC POWER 3 TP56 TEST POINT 56 4 TP55 TEST POINT 55 5 NC NO CONNECTION 6 BB_SEC_INT BASEBOARD SEC INTERRUPT 7 NC NO CONNECTION 8 RSTMCU POWER MANAGEMENT RESET MCU 9 NC NO CONNECTION 10 RST_OUT_B RESET OUT Active low reset signal from the MCU 11 NC NO CONNECTION 12 BB_VCC BASE BOARD VCC 13 NC NO CONNECTION 14 BB_STBY BASE BOARD STANDBY 15 CSPI2 SSO CSPI 2 SLAVE SELECT 0 16 NC NO CONNECTION 17 CSPI2 SS1 CSPI 2 SLAVE SELECT 1 18 PM RSTMCU POWER MANAGEMENT RESET MCU 19 CSPI3 MISO CSPI3 MASTER IN SLAVE OUT 20 PM PWRRDY POWER MANAGEMENT POWER READY 21 CSPI3 MOSI CSPI3 MASTER OUT SLAVE IN 22 PM RST B POWER MANAGEMENT RESET 23 CSPI SPI RDY CSPI1 SPI READY 24 PWR FAIL POWER FAILURE 25 CSPI3_SCLK CSPI3_SERIAL CLOCK 26 LOWBAT LOW BATTERY 27 NC NO CONNECTION 28 NC NO CONNECTION 29 BB_CSPI_SS1 BASE BOARD CSPI SLACE SELECT 1 30 BB BUF EN BASE BOARD BUFFER ENABLE 31 MISO BASE BOARD CSPI MASTER IN SLAVE OUT 32 NC NO CONNECTION 33 BB CSPI MOSI BASE BOARD MASTER OUT SLAVE IN 34 GND SIGNAL GROUND 35 BB 550 BASE BOARD CSPI SALVE SELEC
82. ECT 5 8 B_D15 BUFFERED DATA 15 9 BOE_B BUFFERED OUTPUT ENABLE 10 B D14 BUFFERED DATA 14 11 BRW B BUFFERED READ WRITE 12 B D13 BUFFERED DATA 13 13 BEB1 B BUFFERED EB 1 14 B D12 BUFFERED DATA 12 15 BEBO B BUFFERED EB 0 16 B D11 BUFFERED DATA 11 17 BCSO B BUFFERED CHIP SELECT 0 18 B D10 BUFFERED DATA 10 19 BLBA B BUFFERED LBA M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 51 ADS Connectors and Signals Table 4 34 Software Analysis Connector P9 Signal Description continued Pin Signal Description 20 B_D9 BUFFERED DATA 9 21 NC NO CONNECTION 22 B_D8 BUFFERED DATA 8 23 B_A7 BUFFERED ADDRESS 7 24 B_D7 BUFFERED DATA 7 25 B_A6 BUFFERED ADDRESS 6 26 B_D6 BUFFERED DATA 6 27 B_A5 BUFFERED ADDRESS 5 28 B D5 BUFFERED DATA 5 29 4 BUFFERED ADDRESS 4 30 B_D4 BUFFERED DATA 4 31 B_A3 BUFFERED ADDRESS 3 32 B_D3 BUFFERED DATA 3 33 B_A2 BUFFERED ADDRESS 2 34 B_D2 BUFFERED DATA 2 35 1 BUFFERED ADDRESS 1 36 B_D1 BUFFERED DATA 1 37 B_AO BUFFERED ADDRESS 0 38 B_DO BUFFERED DATA 0 39 43 GND SIGNAL GROUND P10 TP38 1 2 TP40 GND TP39 BRW_B 5 6 BBCLK RST_OUT_B B_D15 BCS4_B 90 10 B Di4 BCS1B 110 12 TP37 1314 B_D12 TP36 15016 B_D11 TP34 1718 B_D10 25 19 20 24 21 22 B_A23 23 24 22 25 26 21 27 28 20 2930 19 31 32 18 3334 17 35 36 UJ
83. ERA B11 EXT_CSI_D7 CMOS SENSOR INTERFACE DATA 7 Image Sensor input data B12 DVDD_1 8V POWER SUPPLY B13 EXT_CSI_D1 CMOS SENSOR INTERFACE DATA 1 Image Sensor input data B14 A14 Wired connection B15 EXT_CSI_DO CMOS SENSOR INTERFACE DATAO Image Sensor input data 16 3V3 3 VDC POWER C1 GND SIGNAL GROUND C2 EXT CSI D9 CMOS SENSOR INTERFACE DATA 9 Image Sensor input data C3 EXT CSI D11 CMOS SENSOR INTERFACE DATA 11 Image Sensor input data C4 EXT_CSI_D13 CMOS SENSOR INTERFACE DATA 13 Image Sensor input data M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 6 Image Sensor Connectors J10 and J13 Signal Description continued Pin Signal Description C5 EXT_CSI_D15 CMOS SENSOR INTERFACE DATA 15 Image Sensor input data C6 EXT CSI HSYNC CMOS SENSOR INTERFACE HORIZONTAL SYNC Control input C7 EXT CSI 5 SENSOR INTERFACE MASTER CLOCK Clock output to the sensor card C8 CSI SDA CMOS SENSOR INTERFACE SERIAL DATA Serial data bidirectional C9 CSI EN CMOS SENSOR INTERFACE ENABLE C10 CSI CTLO CMOS SENSOR CONTROL 0 Control output from MM I O C11 CSI CTL1 CMOS SENSOR CONTROL 1 Control output from MM I O C12 CSI CTL2 CMOS SENSOR CONTROL 2 Control output from MM C13 NC NO CONNECTION C14 CVD
84. ESET chip output from the system RESET OUT line 2 3 1 6 SW2 Tamper Detect Switch SW2 8 ON connects 6 pin of the MCU to ground for use as a tamper detect switch SW2 8 OFF disconnects GPIO1_6 pin of the MCU from ground and allows the signal to be pulled high 2 3 2 CPU Board Jumper Headers The CPU board has 38 jumper headers JP1 JP2 JP22 and JP26 determine the source of the system reset signal and clock JP6 and JP10 control the LA and JTAG interfaces JP3 to JP5 JP12 JP13 JP16 JP17 JP20 JP23 JP28 JP31 JP32 and JP35 to JP38 select power options The remaining two pin jumpers provide access to 1 Ohm shunt resistors for current power measurement Table 2 6 describes the CPU board jumpers Jumpers that are critical to stand alone and APMS operation are shaded Figure 2 5 shows the locations of the jumpers on the board i MX31ADS User s Manual REV 1 Preliminary 2 8 Freescale Semiconductor Configuring and Connecting the ADS CAUTION To avoid damage to the ADS remove the CPU board power jumper shunts when the MC13783 power management system is used Do not interchange them with other shunts Before connecting the MC13783 board move the power shunts to the Base board and use them to set MC13783 output voltages for the NVCC power rails Table 2 6 CPU Board Jumper Headers Jumper Designation Pn 9 Connection NC 23 23 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is n
85. FERED ADDRESS MCU address bus B_A4 66 BUFFERED ADDRESS MCU address bus B_A5 62 BUFFERED ADDRESS MCU address bus B_A6 60 BUFFERED ADDRESS MCU address bus B_A7 58 BUFFERED ADDRESS MCU address bus 8 56 BUFFERED ADDRESS MCU address bus 9 54 BUFFERED ADDRESS MCU address bus B_A10 50 BUFFERED ADDRESS MCU address bus 11 48 BUFFERED ADDRESS MCU address bus 12 46 BUFFERED ADDRESS MCU address bus 13 44 BUFFERED ADDRESS MCU address bus 14 42 BUFFERED ADDRESS MCU address bus B_A15 40 BUFFERED ADDRESS MCU address bus 16 76 BUFFERED ADDRESS MCU address bus B_A17 78 BUFFERED ADDRESS MCU address bus B_A18 80 BUFFERED ADDRESS MCU address bus B_A19 82 BUFFERED ADDRESS MCU address bus B_A20 84 BUFFERED ADDRESS MCU address bus 21 86 BUFFERED ADDRESS MCU address bus 22 88 BUFFERED ADDRESS MCU address bus B_A23 90 BUFFERED ADDRESS MCU address bus B_A24 92 BUFFERED ADDRESS MCU address bus B_A25 94 BUFFERED ADDRESS MCU address bus B_DO 8 BUFFERED DATA MCU data bus B_D1 10 BUFFERED DATA MCU data bus B_D2 12 BUFFERED DATA MCU data bus B_D3 14 BUFFERED DATA MCU data bus B 16 BUFFERED DATA MCU data bus B D5 18 BUFFERED DATA MCU data bus B D6 20 BUFFERED DATA MCU data bus B D7 22 BUFFERED DATA MCU data bus B D8 24 BUFFERED DATA MCU data bus B D9 26 BUFFERED DATA MCU data bus B D10 28
86. FS FS MEMORY MEMORY PWR REGULATORS RON CONFIGURATION STICK 1 STICK 2 NVCC 1 8 amp 2 7V INPUT S alla SWITCHES QVCC 1 3V PLL 2 E SYSTEM 3 3V R x Realview FUSE EG BASE BOARD ICE JTAG CPU L lt JE CARD TFE ALT PWR ETM 12 TORTOLA CLOCK SRC CONN umpers CPU 32KHz OSC Ethernet IF Phy amp SIMM CONN S 5 Controller BUFF 26 MHz OSC ETM CONTROL External SMA M M CONN CPLD MCP 5 512Mbit NOR 1 T Buzzer DATA ADD CTRL Burst FLASH CONFIG BUFFER io PSRAM SWITCHES P P 128Mbit x 16 R R x Logic Analizer 9 IMAGE SENSOR SHARED Samtec Conns 1 2 5 CONN ADDRESS BUFFER Mobile DDR Z ag 512Mb no 2 256 x 16 C 2 LOCK S go CPLD 133MHz CLK SMB CONNS 5 V 2 MMIO DECODE CADO MUX CTRL 8BIT IF C SW readable Brd Rev Other L ee Coin Cell EM USB Fun Lights 3 PERS and Battery EM OTG 2 2 Synthesizer Potentiometers o 6 lt 8 Vibrator S Sw CONFIGURATION SWITCHES 7 z 2 m odeTest Batt E e LA Analyzer Cin 2 Connectors VOICE 10k A Touch Screen AUDIO CODEC ANLG OUT m Controller Li Cell DC CONN ST HDPHN a 783 p ANLG IN lt 32KHz Clock BOARD Batt charge 22 2 2 n Connector 265 POWER REGS go y Bz Bz is Reset Controll Z gt Z 2 ese ontroiier SWITCH ERS BS EE RST push button AND LINEAR LT SPK B gt Status S CONN D LEDs 2 s 8 8 RT SPK
87. Full Speed Host Mode Selects Single ended 0 Differential mode Bit 6 differential mode on USB Host Full Speed interface 1 Single ended mode OTG HS EN USB OTG High Speed Enable Enable the USB 0 OTG High Speed Interface enabled Bit 7 OTG High speed interface on the CPU 1 OTG High Speed Interface disabled OTG VBUS USB OTG VBUS Enable Enable VBUS regulator 0 VBUS regulator is enabled Bit 8 on USB OTG interface PHY 1 OTG VBUS regulator is disabled FSH VBUS USB Full Speed Host VBUS Enable Enable USB 0 Full Speed Host VBUS regulator is enabled Bit 9 Full speed Host interface PHY VBUS regulator 1 Full Speed Host VBUS regulator is disabled CARD1_SEL 0 lines dedicated to 501 interface Bit 10 Card1 Select Select MUX pin for SD1 MS1 lines 1 lines dedicated to MS1 interface CARD2_SEL Card2 Select Select MUX pin for PCMCIA amp SD2 0 lines dedicated to PCMCIA amp SD2 interface Bit 11 MS2 lines 1 lines dedicated to MS2 interface SYNTH_RST Audio Synthesizer Reset Enable Audio 0 Reset audio Synthesizer Bit 12 Synthesizer reset signal 1 Normal operation VSIM_EN VSIM Enable Enable VSIM regulator on the 0 VSIM regulator is disabled Bit 13 MC13783 board 1 VSIM regulator is enabled VESIM_EN VESIM Enable Enable VESIM regulator on the 0 VESIM regulator is disabled Bit 14 MC13783 board 1 VESIM regulator is enabled SPI3_RESET CSPI3 Connector Reset Enable reset signa
88. GPIO2 Figure 4 8 Option Connector J11 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 29 ADS Connectors and Signals Table 4 12 Option Connector J11 Signal Description Pin Signal Description 1 LED MD1 MAIN DISPLAY LIGHT EMMITING DIODE 2 PM VBLITE LCD PANEL BACKLIGHT VOLTAGE 3 LED MD2 MAIN DISPLAY LIGHT EMMITING DIODE 4 LED MD3 MAIN DISPLAY LIGHT EMMITING DIODE 5 LED MD4 MAIN DISPLAY LIGHT EMMITING DIODE 6 NC NOT CONNECTED 7 GND SIGNAL GROUND 8 NC NOT CONNECTED 9 NC NOT CONNECTED 10 CVDD 2 775 2 775 VDC SUPPLY 11 LED KP KEYPAD LIGHT EMMITING DIODE 12 NC NOT CONNECTED 13 DVDD_1 8V 1 8 VDC SUPPLY 14 NVCC7 5 VDC SUPPLY 15 GPIO1 GENERAL PURPOSE I O LINE 1 16 GPIO2 GENERAL PURPOSE I O LINE 2 4 2 5 3 Parallel LCD Connectors Connectors J8 and J9 provide parallel interface signals for LCD panels J9 is Parallel Connector I and J8 is Parallel connector I Figure 4 9 shows J9 pin assignments and Table 4 13 describes J9 signals Figure 4 10 shows J8 pin assignments and Table 4 14 describes J8 signals J9 IPU_VSYNCHO 114 12 IPU_LD1 3 4 IPU_LD3 5 105 7 8 108 9 e 10 106 11 12 LCDRSTO 13 e 14 IPU_LLD9 15 e 16 LD11 17 18 1013 19 e 20 1015 21 e 22 IPU LCSO 23 24 RD 25 e e 26 LED MD1 27
89. HOST DATA 0 B16 R_PC_RW_B PCMCIA READ WRITE signal C1 GND GROUND C2 CAPTURE TIMER INPUT CAPTURE Timer input C3 COMPARE TIMER OUTPUT COMPARE Timer output C4 R PC CD2 B PCMCIA Card Detect 2 C5 R PC CD1 B PCMCIA Card Detect 1 M9328MX31ADS User s Manual Rev 1 Preliminary 4 24 Freescale Semiconductor Table 4 8 Extension Connector J22 Signal Description continued ADS Connectors and Signals Pin Signal Description C6 PC PWRON POWER ON SIGNAL C7 PC 51 PCMCIA Voltage Sense 1 signal C8 R PC RDY PCMCIA READY signal C9 R PC WAIT B PCMCIA WAIT signal C10 PWMO PULSE WIDTH MODULATOR OUTPUT C11 RST OUT B RESET OUT Active low reset signal from the processor C12 NC NO CONNECTION C13 USB OC USB OVER CURRENT input active low C14 USB PWR USB POWER C15 USB BYP USB BY PASS C16 VCC 3 VDC power Table 4 9 Extension Connector J23 Signal Description Pin Signal Description Al GND SIGNAL GROUND A2 NC NO CONNECTION A3 NC NO CONNECTION A4 NC NO CONNECTION 5 CPLD_SP4 CUSTOM PROGRAMMED LOGIC DEVICE SP 4 A6 CPLD_SP3 CUSTOM PROGRAMMED LOGIC DEVICE SP 3 A7 CPLD_SP2 CUSTOM PROGRAMMED LOGIC DEVICE SP 2 A8 CPLD_SP1 CUSTOM PROGRAMMED LOGIC DEVICE SP 1 A9 DSR_DTE1 UART1 DTE signal DSR A10 RI_DTE1 UART1 DTE signal Ring Indicator A11 DCD_DTE1 UART1 DTE signal DC
90. IO3_0 163 GENERAL PURPOSE I O GPIO3_1 165 GENERAL PURPOSE I O 2 162 SQUARED CLOCK Serial clock bidirectional I2C1 DAT 166 SQUARED C DATA Serial data bidirectional 101516 41 PCMCIA control signal IPU_CONTRAST 110 CONTRAST Synchronous LCD control signal IPU_D3_REV 108 D3_REV Synchronous LCD control signal IPU_D3_SPL 118 D3_SPL Synchronous LCD control signal IPU_DE_CLS 120 DE_CLS Synchronous LCD control signal IPU_DRDYO 102 DRDY Synchronous LCD control signal IPU_FPSHIFT 126 FPSHIFT Synchronous LCD control signal HSYNCH 128 HORIZONTAL SYNCH Synchronous LCD control signal IPU_LCSO 90 LCSO Synchronous LCD control signal IPU_LCS1 88 LCS1 Synchronous LCD control signal IPU LDO 131 DISPLAY DATA Synchronous LCD control signal IPU LD1 129 DISPLAY DATA Synchronous LCD control signal IPU LD2 127 DISPLAY DATA Synchronous LCD control signal IPU_LD3 125 DISPLAY DATA Synchronous LCD control signal IPU_LD4 123 DISPLAY DATA Synchronous LCD control signal IPU_LD5 121 DISPLAY DATA Synchronous LCD control signal IPU_LD6 119 DISPLAY DATA Synchronous LCD control signal IPU LD7 117 DISPLAY DATA Synchronous LCD control signal IPU LD8 113 DISPLAY DATA Synchronous LCD control signal IPU LD9 111 DISPLAY DATA Synchronous LCD control signal IPU LD10 109 DISPLAY DATA Synchronous LCD control signal IPU LD11 107 DISPLAY DATA Synchronous LCD control signal IPU LD12 105 DI
91. IT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG OTG 5 XUART_ XUART ENET_ FSH_ PB LOW FIELD RES 2 INT1 IRQ INTB INTA FS INT RES RES HES OVR FS IRQ BAT INT OVR OPER R R R R R R R R W1C R W1C R W1C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 9 Interrupt Status Clear Register ISCR Table 3 12 Interrupt Status Clear Register Bit Definitions Name Description Settings LOW_BAT Low Battery Low Battery signal from MC13783 0 No interrupt pending Bit 0 changed state 1 Interrupt active write a one to clear PB_IRQ Push button IRQ Push button switch circuit output 0 No interrupt pending Bit 1 has changed state 1 Interrupt active write a one to clear OTG FS USB OTG Full Speed Over Current USB OTG Full 0 No interrupt pending Bit 2 Speed Over Current bit has changed state 1 Interrupt active write a one to clear FSH_OVR USB Full Speed Host Over Current USB Full 0 No interrupt pending Speed Host interface overcurrent bit has changed Bit 3 State 1 Interrupt active write a one to clear RES Bits 4 5 6 7 amp 15 Reserved for future use N A INTI Ethernet Interrupt Ethernet controller interrupt 0 No interrupt from Ethernet controller Bit 8 request 1 Interrupt from Ethernet controller OTG_FS_INT USB Host Full Speed Interrupt USB Host full 0 No interrupt from USB Host full speed interface Bit 9 speed interfa
92. JP22 NVCC 6 amp 9 JP23 NVCC 7 JP24 NVCC 8 JP25 NVCC 6 amp 9 JP26 Selected by JP22 NVCC 9 PM VIOLO PM VIOHI PM VGEN VREF1 PM VGEN VREF1 PM VIOLO PM VIOHI PM VGEN VREF1 PM SIM i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor Configuring and Connecting the ADS JP6 JP7 JP1 JP2 JP4 JP5 8 JP13 JP14 Figure 2 2 Base Board Jumpers Left Side i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 5 Configuring and Connecting the ADS JP3 JP21 TO JP26 JP15 TO JP20 Figure 2 3 Base Board Jumpers Right Side i MX31ADS User s Manual REV 1 Preliminary 2 6 Freescale Semiconductor Configuring and Connecting the ADS 2 3 CPU Board Configuration 2 3 1 CPU Board Switches The CPU board has one SPST slide power switch S1 a push button reset switch SW1 and an eight switch DIP module SW2 Figure 2 4 shows the location of the switches SW1 5 2 Figure 2 4 CPU Board Switches 2 3 1 1 S1 Power Switch Slide S1 to ON to power up the CPU board in stand alone mode or to power up the ADS when the CPU board is connected to the Base board 2 3 1 2 SW1 Reset Switch Push SWI to reset the ADS
93. JTAG RETURN CLOCK 14 5V 5V VCC POWER 15 TCK JTAG CLOCK 16 KPCOL7 TRACE DATA 17 TMS JTAG MODE 18 KPCOL6 TRACE DATA 19 TDI JTAG DATA IN 20 KPCOL5 TRACE DATA 21 TRST B JTAG RESET 22 KPCOL4 TRACE DATA 23 CSPI_MOSI TRACE DATA 24 KPCOL3 TRACE DATA 25 SFS6 TRACE DATA 26 KPROW7 TRACE DATA 27 SCK6 TRACE DATA 28 KPROW6 TRACE DATA 29 SRXD6 TRACE DATA 30 GND SIGNAL GROUND 31 STXD6 TRACE DATA 32 GND SIGNAL GROUND 33 SFS3 TRACE DATA 34 DVDD_1 8V 1 8V VCC POWER 35 SCK3 TRACE DATA 36 KPROWS TRACE CONTROL 37 SRXD3 TRACE DATA 38 KPROW5 TRACE DATA 39 44 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary 4 68 Freescale Semiconductor 4 3 3 RV ICE JTAG Connector ADS Connectors and Signals J8 is the CPU board RV ICE JTAG connector Figure 4 36 shows pin assignments and Table 4 44 describes signals J8 NVCC6 1 e e 2 GND TRSTB 3 e 4 GND TDI 5 e e 6 GND TMS 7 e e 8 GND 9 e 10 GND RTCK 11 e e 12 GND 13 e 14 GND PM_RST_MCU_B 15 e e 16 GND DEB 17 e 18 GND GND 19 20 GND Figure 4 36 RV ICE JTAG Connector J8 Pin Assignment Table 4 44 RV ICE JTAG Connector J8 Signal Description Pin Signal Description 1 NVCC6 VDC POWER 2 GND SIGNAL GROUND 3 TRST_B TARGET RESET 4 GND TEST MODE SELECT 5 TDI TEST DATA INPUT 6 GND RETURN CLOCK 7 TMS TEST MODE SELECT 8 GND RESET IN 9 TCK TEST CLOCK 10
94. LD2 LCD DATA 2 5 IPU LD3 LCD DATA 3 6 104 LCD DATA 4 7 IPU_LD5 LCD DATA 5 8 IPU_LD17 LCD DATA 17 9 IPU LD8 LCD DATA 8 10 IPU LD7 LCD DATA 7 11 IPU LD6 LCD DATA 6 12 PAR RESET PARALLEL INTERFACE RESET 18 LCDRSTO LCD RESET 0 14 IPU WR PARALLEL INTERFACE WRITE 15 IPU LD9 LCD DATA 9 16 3V3 3 VDC SUPPLY 17 IPU_LD11 LCD DATA 11 18 IPU_LD10 LCD DATA 10 19 IPU_LD13 LCD DATA 13 20 GND SIGNAL GROUND 21 IPU_LD15 LCD DATA 15 M9328MX31ADS User s Manual Rev 1 Preliminary 4 32 Freescale Semiconductor ADS Connectors and Signals Table 4 14 Parallel LCD Connector J8 Signal Description continued Pin Signal Description 22 IPU LD12 LCD DATA 12 23 IPU LCSO LCD CHIP SELECT 24 IPU LD14 LCD DATA 14 25 IPU RD PARALLEL INTERFACE READ 26 IPU LD16 LCD DATA 16 27 LED MD1 MAIN DISPLAY LIGHT EMMITING DIODE 28 VBLITE LCD PANEL BACKLIGHT VOLTAGE 29 LED MD2 MAIN DISPLAY LIGHT EMMITING DIODE 30 LED MD3 MAIN DISPLAY LIGHT EMMITING DIODE 31 LED MD4 MAIN DISPLAY LIGHT EMMITING DIODE 32 NC NOT CONNECTED 33 GND SIGNAL GROUND 34 CVDD 2 775 2 775 VDC SUPPLY 35 LED_KP KEYPAD LIGHT EMMITING DIODE 36 NC NOT CONNECTED 37 DVDD_1 8V 1 8 VDC SUPPLY 38 NVCC7 5 VDC SUPPLY 39 GPIO1 GENERAL PURPOSE LINE 1 40 GPIO2 GENERAL PURPOSE LINE 2 4 2 5 4 Serial Asynchronous LCD Connector Connector J6 provides serial asynchronous control signals
95. NDICATOR ATLAS UDATVP 24 USB DATA V PLUS ATLAS URCVD 30 USB RECEIVE DATA ATLAS URXVM 36 USB RECEIVE MINUS ATLAS URXVP 34 USB RECEIVE MINUS ATLAS USE 0VM 26 USB SINGLE ENDED ZERO ATLAS UTX ENB 20 USB TRANSMIT ENABLE BB CSPI CLK 89 BASEBAND CONFIGURABLE SERIAL PERIPHERAL INTERFACE CLOCK BB CSPI MISO 95 BASEBAND CONFIGURABLE SERIAL PERIPHERAL INTERFACE MISO BB CSPI MOSI 93 BASEBAND CONFIGURABLE SERIAL PERIPHERAL INTERFACE MOSI BB CSPI SSO 91 BASEBAND CONFIGURABLE SERIAL PERIPHERAL INTERFACE SSO BB SEC INT 62 BASEBAND SECONDERY INTERRUPT BB STBY 50 BASEBAND STANDBY BB VCC 68 BASEBAND VCC BPC POE 114 PCMCIA OUTPUT ENABLE CLKO 108 CLKOUT CPU PRI 63 CPU PRIMARY VCC CSPI2 MISO 83 CONFIGURABLE SERIAL PERIPHERAL INTERFACE MISO CSPI2 MOSI 81 CONFIGURABLE SERIAL PERIPHERAL INTERFACE MOSI CSPI2 SCLK 77 CONFIGURABLE SERIAL PERIPHERAL INTERFACE CLOCK CSPI2 550 79 CONFIGURABLE SERIAL PERIPHERAL INTERFACE SSO CVDD_2 775V 132 134 2 775V VDCPOWER DVS_SW1B 4 DYNAMIC VOLTAGE SCALING INPUT FOR SWITCHER DVS_SW1A 48 DYNAMIC VOLTAGE SCALING INPUT FOR SWITCHER DVS_SW2A 52 DYNAMIC VOLTAGE SCALING INPUT FOR SWITCHER DVS_SW2B 78 DYNAMIC VOLTAGE SCALING INPUT FOR SWITCHER 19 22 23 27 28 31 32 35 41 45 49 53 GND 57 61 65 69 SIGNAL GROUND 73 80 87 88 145 149 156 191 215 LED_AD1 14 AUXILARY DISPLAY LIGHT EMMITING DIODE LED_AD2 16 AUXILARY DISPLAY LIGHT EMMITING DIODE LED_KP 18 KEYPAD LIGHT EMMITING DIODE LED_MD1 6 MAIN DISPLAY LIGHT EMMITI
96. NG DIODE LED_MD2 8 MAIN DISPLAY LIGHT EMMITING DIODE LED_MD3 10 MAIN DISPLAY LIGHT EMMITING DIODE LED_MD4 12 MAIN DISPLAY LIGHT EMMITING DIODE LEDB1 13 FUNLIGHT LED 1 BLUE SEGMENT LEDB2 15 FUNLIGHT LED 2 BLUE SEGMENT LEDB3 17 FUNLIGHT LED 3 BLUE SEGMENT LEDG1 7 FUNLIGHT LED 1 GREEN SEGMENT LEDG2 9 FUNLIGHT LED 2 GREEN SEGMENT M9328MX31ADS User s Manual Rev 1 Preliminary 4 18 Freescale Semiconductor ADS Connectors and Signals Table 4 5 Base Board to MC13783 Board Connector P6 Signal Description continued Signal Pin Description LEDG3 11 FUNLIGHT LED 3 GREEN SEGMENT LEDR1 1 FUNLIGHT LED 1 RED SEGMENT LEDR2 3 FUNLIGHT LED 2 RED SEGMENT LEDR3 5 FUNLIGHT LED 3 RED SEGMENT LOWBAT 101 LOW BATTERY 85 97 103 109 119 131 133 135 137 NC 139 146 148 NOT CONNECTED 151 161 163 164 170 176 185 NVCC2 158 VOLTAGE REGULATOR OUTPUT ON1_B 182 MC13783 POWER ON OFF BUTTON ON2_B 184 MC13783 POWER ON OFF BUTTON ON3_B 186 MC13783 POWER ON OFF BUTTON PC_CE2_B 110 PCMCIA CARD ENABLE PC_OE_B 112 PCMCIA OUTPUT ENABLE PM_BKUP_DDR 178 180 VOLTAGE REGULATOR OUTPUT PM_BP 171 173 BATTERY POWER PM_CLIA 75 CLOCK INPUT PM_CLK32K 154 32KHZ CLOCK OUTPUT PM CLK32K MCU 67 32KHZ CLOCK OUTPUT TO THE PROCESSOR BUFF 90 GENERAL PURPOSE OUTPUT GPO2 BUFF 96 GENERAL PURPOSE OUTPUT G
97. PO3 BUFF 102 GENERAL PURPOSE OUTPUT PM INT 71 INTERRUPT MEM CS 179 MEMORY CHIP SELECT PM PWRRDY 86 POWER READY PM RST B 44 RESET SIGNAL PM RSTMCU B 54 RESET SIGNAL to MCU PM SW1A 116 118 SWITCHER OUTPUT SW1B 150 152 SWITCHER OUTPUT PM SW2A 160 162 SWITCHER OUTPUT SW2B 166 168 SWITCHER OUTPUT VBLITE 181 183 VOLTAGE REGULATOR OUTPUT PM VCAM 105 107 VOLTAGE REGULATOR OUTPUT PM VDIG 82 84 VOLTAGE REGULATOR OUTPUT PM VESIM 104 106 VOLTAGE REGULATOR OUTPUT PM VGEN 115 117 VOLTAGE REGULATOR OUTPUT PM VIOHI 64 66 VOLTAGE REGULATOR OUTPUT PM VIOLO 56 58 VOLTAGE REGULATOR OUTPUT VRF1 165 167 VOLTAGE REGULATOR OUTPUT VRFDIG 98 100 VOLTAGE REGULATOR OUTPUT PM VUSB 3V 40 42 VOLTAGE REGULATOR OUTPUT WDOG RST 141 WADTCHDOG RESET PWGT1 EN 169 POWER GATE 1 ENABLE M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 5 Base Board to MC13783 Board Connector P6 Signal Description continued Signal Pin Description PWGT1_OUT 172 174 POWER GATE 1 OUTPUT PWGT2_EN 175 POWER GATE 2 ENABLE PWGT2_OUT 111 113 2 PWR 92 POWER FAIL INDICATOR REGEN 70 REGULATOR ENABLE SCK4 144 AUDIO PORT 4 SERIAL CLOCK SCK5 159 AUDIO PORT 5 SERIAL CLOCK SFS4 142 AUDIO PORT 4 FRAME SYNC SFS5 157 AUDIO PORT 5 FRAME SYNC SRXD4 140 AUDIO
98. R IN SLAVE OUT 9 GND SIGNAL GROUND 10 CVDD 2 775 2 775 VDC POWER 11 LED_AD1 AUXILARY DISPLAY LIGHT EMMITING DIODE 12 PM_VBLITE POWER MANAGER BACKGROUND LIGHT 13 LED_AD2 AUXILARY DISPLAY LIGHT EMMITING DIODE 14 LED_KP KEYPAD LIGHT EMMITING DIODE 15 GPIO1 GENERAL PURPOSE INPUT OUTPUT 1 16 GPIO2 GENERAL PURPOSE INPUT OUTPUT 2 17 R SRXD6 Audio Port 6 RECEIVE DATA 18 SCK6 SERIAL CLOCK 6 19 R STXD6 Audio Port 6 TRANSMIT DATA 20 SPI RDY CSPI3 INTERFACE READY M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 41 ADS Connectors and Signals 4 2 13 Ethernet Connector is the RJ 45 Ethernet connector for the ADS Figure 4 20 shows pin numbering and Table 4 25 provides signal descriptions for the connector Figure 4 20 Ethernet Connector 1 Pin Numbers Table 4 25 Ethernet Connector T1 Signal Description Pin Signal Description 1 TPO DIFFERENTIAL OUTPUT PLUS 2 TPO DIFFERENTIAL OUTPUT MINUS 3 DIFFERENTIAL INPUT PLUS 4 NC NO CONNECTION 5 NC NO CONNECTION 6 TPI DIFFERENTIAL INPUT MINUS 7 NC NO CONNECTION 8 NC NO CONNECTION 4 2 14 USB OTG Connectors and J2 are USB connectors is a high speed connector while J2 is a full speed connector Figure 4 21 shows pin assignments and Table 4 26 describes signals D D ID Cao Figure 4 21 USB OTG Connectors J1 and J2 Pin Assignment Table 4 26 USB OTG Connecto
99. RE ahaa 2 12 MC13783 Board Jumper Headers Vom noeud ERR xu E We Sue Weeks 2 16 Connecting the CPU Board to the Base 2 20 Connecting the MC13783 Board to the Base 2 21 ADS Functional Block 3 1 Version Register oto Sent pind ceed p Ubi eus Paw thea 3 7 Board Status Register 1 3 7 Board Status Register 2 5 2 3 8 Board Control Register 1 25222225256 oat 3 9 Board Control Register 2 bea eh ate C tk 3 10 Board Control Register 3 3 3 12 Board Control Register 4 4 3 13 Interrupt Status Clear Register eR 3 14 Interrupt Signal Current State Status Register 15 55 3 14 Interrupt Mask Register IMIR Lee vatua cesa EE RS 3 15 Burst Flash and Interface s coude ved ya eU eps Sq Seta 3 17 DDR SDRAM Interface case A aur Fat epa RA BE A SCR 3 18 TES S vs oaa emat a i eR EET od ON aaa 3 19 USB OTG HS ULPI Interface sid e ES eh Me PRO ede rar d VE
100. S The ADS provides a USB HOST interface that uses a Phillips ISP1105W USB transceiver connected to a type A USB connector J5 It can operate at Full Speed or Low Speed The interface can function only as a USB host The interface provides power on the USB bus This power is supplied by from the external 5 volt power source through a MIC2536 power switch For details on the operation of this USB interface refer to the 1 MX31 data sheet Figure 3 17 shows the USB interface connection ISP1105W J5 USBH2 AP6 AP3 CSPI1 AP6 USB FSH EN B USB HOST USB FSH SEL i MX31 USB TYPEA 45V USB FSH OVR FSH VBUSEN B MIC2536 2BM Figure 3 17 USB FS LS HOST Interface 3 11 UART Internal and IrDA Interfaces The ADS has three RS 232 compatible UART Interfaces that service the internal UARTS of the 1 31 UARTA and UARTB are DTE and UARTC is DCE UARTA and UARTC can have full modem support but not UART B three interfaces have a choice between two sets of UART signals from 1 MX31 There is also a FIR Fast Infra Red transceiver connected to UART2 of the 1 MX31 four interfaces can be enabled on power up based on SW1 switch settings Mux and enable controls can be software controlled through the CPLD Figure 3 18 shows how the UART and IrDA circuits are connected i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 21 ADS Operation
101. S Out Synthesizer chip select 3 3 3 1 Peripheral Bus Cycles The following peripheral bus cycles are implemented Table 3 4 Bus Cycles Cycle Transfer size Description IOREAD Byte Word Used to read 8 16 bit data from peripheral registers with IOR B signal IOWRITE Byte Word Used to write 8 16 bit data to peripheral registers with B signal MEMREAD Byte Word Used to read 8 16 bit data from peripheral memory using MEMR signal MEMWRITE Byte Word Used to write 8 16 bit data to peripheral memory using MEMW signal Used during Ethernet DMA transfers to read 16 bit data from Ethernet controiler DMAREAD Word buff ENET DMACK B signal 3 3 3 2 DMA Operation The CS8900A supports DMA slave transfers for received data frames The CPLD supports these DMA transfers using a single DMAREQ signal to the processor and a special DMA address space in the memory map DMAREQ signal from the CS8900A is forwarded to the CPU I F and used as a qualifier for DMA transfers A qualified read transfer to the DMA address space generates DMACK signal to the CS8900A i MX31ADS User s Manual REV 1 Preliminary reescale Semiconductor ADS Operation 3 3 3 3 5 16 652 UART Decode The CPLD provides address decodes and data path control for the SC16C652C DUART Data is transferred through the CPLD to and from the SC16C652C The CPLD hardware provi
102. S1 S2 S3 User Defined Push Buttons 2 12 2 4 1 2 54 USB Function Select USB Enable WDI Enable 2 12 2 4 1 3 55 Backup Source Select Switch 2 13 2 4 1 4 S6 USB Buffer Control 2 13 2 4 1 5 S7 Audio Buffer Enable and Direction Select 2 14 2 4 1 6 S8 and CLIB Source Select 2 14 2 4 1 7 S9 MC13783 Power up Mode Select Switch 2 15 242 J mper Headers 2 15 2 MEN IDA C rc 2 17 2 5 1 CPU Board Regulator Power Configuration 2 17 2 5 2 MC13783 Power 2 17 2 5 3 Select QVCC and PLL Voltages 2 17 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor Table of Contents 2 5 4 Select CPU Clock emer Vus org 2 18 2 5 5 Set Other CPU Board Jurmp ers or Ere e e eR ERES 2 18 2 5 6 DSL C PU Board Switches has e Pc ta e apa ala s oder eese 2 19 2 5 7 Set Base Board Jumpers 54 ache Rade A x e
103. SE2 SENSE1 WP WP RDY DASP CBLID 16 SENSE ON DET OPER R R R R R R R R R R R R R R R R 0 0 0 3 IN OUT IN IN IN IN IN IN IN IN IN IN IN IN IN Figure 3 3 Board Status Register 1 BSTAT1 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 7 ADS Operatio n 3 3 6 3 Board Status Register 2 BSTAT2 Table 3 6 Board Status Register 1 Bit Definitions Name Description Settings NF_DET TON 0 Nand Flash card is inserted Bit 0 NAND Flash Detect indicates Nand Flash card insertion 1 Nand Flash card is not inserted KP_ON un 0 Keypad is Bit 1 Keypad On Off indicates if keypad is on off 1 Keypad is OFF LIGHT SENSE Light sense This signal reflects the light sense output from the 0 Light sense is 0 Bit 2 keypad 1 Light sense is 1 ATA IOCS16 ATAIOCS16 This bit reflects the status of pin IOCS16 on the ATA 0 IOCS16 state is 0 Bit 3 connector 1 IOCS16 state is 1 CBLID ATA CBLID This bit reflects the status of pin CBLID on the ATA 0 CBLID state is 0 Bit 4 connector 1 CBLID state is 1 DASP ATA DASP This bit reflects the status of pin DASP on the 0 DASP state is 0 Bit 5 connector 1 DASP state is 1 PWR RDY m 0 2 MC13783 power is not ready Bit 6 Power Ready Power ready indication from MC13783 board 1 MC13783 power is ready SD1 WP 0 01 card is Writ
104. SPLAY DATA Synchronous LCD control signal 1013 103 DISPLAY DATA Synchronous LCD control signal IPU_LD14 101 DISPLAY DATA Synchronous LCD control signal IPU_LD15 99 DISPLAY DATA Synchronous LCD control signal IPU_LD16 97 DISPLAY DATA Synchronous LCD control signal IPU LD17 95 DISPLAY DATA Synchronous LCD control signal IPU PAR RS 106 PARALLEL RS Synchronous LCD control signal IPU RD 122 READ Synchronous LCD control signal M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 2 Base Board to CPU Board Connector P1 Signal Description continued Signal Pin Description IPU_SD_CLK 136 SERIAL DATA CLOCK Synchronous LCD control signal SD D I 130 SERIAL DATA IN Synchronous LCD control signal SD D IO 132 SERIAL DATA I O Synchronous LCD control signal IPU SER RS 104 SERIAL RESET Synchronous LCD control signal IPU VSYNCHO 98 VERTICAL SYNCH Synchronous LCD control signal VSYNCH3 94 VERTICAL SYNCH Synchronous LCD control signal IPU WR 124 WRITE Synchronous LCD control signal NVCC3 35 37 39 CONDITIONED POWER SUPPLY NVCC4 1917199 CONDITIONED POWER SUPPLY 154 156 NVCC5 E s CONDITIONED POWER SUPPLY NVCC7 CONDITIONED POWER SUPPLY NVCC8 CONDITIONED POWER SUPPLY OWDAT 80 One
105. SW2 6 and SW2 7 determine the actual effect of SWI i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 7 Configuring and Connecting the ADS 2 3 1 3 SW2 Boot Mode Switches SW2 1 to SW2 5 settings determine where the processor begins program execution Table 2 5 shows all valid combinations of the switches Other combinations are reserved and must not be used Table 2 5 Boot Mode Switch Settings Boot Mode Device BOOT4 BOOT3 BOOT2 BOOT1 BOOTO SW2 5 SW2 4 SW2 3 SW2 2 SW2 1 ON ON ON ON ON ON ON OFF UART USB bootloader ON 8 bit NAND Flash 2KB page Int ON 8 bit NAND Flash 512B page Int ON ON ON OFF OFF 16 bit NAND Flash 2KB page Int ON ON ON OFF OFF 16 bit NAND Flash 512B page Int ON ON OFF ON ON 16 bit CSO at D 15 0 Int ON ON OFF ON OFF M System Disk on Chip ON OFF ON ON ON 8 bit NAND Flash 2KB page Ext OFF ON ON ON ON 8 bit NAND Flash 512B page Ext OFF ON ON ON OFF 16 bit NAND Flash 2KB page Ext OFF ON ON OFF OFF 16 bit NAND Flash 512B page Ext OFF ON ON OFF OFF 16 bit CSO at D 15 0 Ext OFF ON OFF ON ON Test Mode OFF OFF ON OFF OFF 2 3 1 4 SW2 Power On Reset Switch SW2 6 ON connects the PB RESET output to the POR pin of the MCU SW2 6 OFF disconnects the PB RESET output from the POR pin of the MCU 2 3 1 5 SW2 Reset Out Switch SW2 7 ON connects RESET chip output to the system RESET OUT line SW2 7 OFF disconnects the R
106. SYNC Control input CSP12 MISO 81 MASTER IN SLAVE OUT CSPI data signal bidirectional CSP12 MOSI 79 MASTER OUT SLAVE IN CSPI data signal bidirectional CSP12 SSO 85 SLAVE SELECT 0 CSPI signal bidirectional CSP12 SS1 83 SLAVE SELECT 1 CSPI signal bidirectional CSP12 SS2 87 SLAVE SELECT 2 CSPI signal bidirectional CSP13 MISO 20 MASTER IN SLAVE OUT CSPI data signal bidirectional CSP13 MOSI 18 MASTER OUT SLAVE IN CSPI data signal bidirectional CSP13_SCLK 24 SERIAL CLOCK Bidirectional CSP13_SPI_RDY 22 READY CSPI serial burst trigger active low input CSPI2 SCLK 84 SERIAL CLOCK Bidirectional CSPI2 SPI RDY 82 READY CSPI serial burst trigger active low input DCD DCE1 173 UART1 DCE signal DCD DCD_DTE1 177 UART1 DTE signal DCD DSR_DCE1 169 UART1 DCE signal DSR DSR_DTE1 185 UART1 DTE signal DSR DTR_DCE1 175 UART1 DCE signal DTR M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals Table 4 2 Base Board to CPU Board Connector P1 Signal Description continued Signal Pin Description DTR_DCE2 179 UART2 DCE signal DTR DTR_DTE1 183 UART1 DTE signal DTR 16 26 29 49 56 59 66 86 89 92 93 96 100 133 GND Ur n Signal Ground 148 152 160 164 167 168 178 191 192 215 GP
107. T 0 36 NC NO CONNECTION 37 GND SIGNAL GROUND 38 GND SIGNAL GROUND 39 BB_CSPI_CLK BASE BOARD CSPI CLOCK 40 R_SCK3 SERIAL CLOCK 41 GND SIGNAL GROUND 42 GND SIGNAL GROUND 43 IPC_USB_VMOUT USB VOLTAGE MINUS OUT 44 R_SFS3 FRAME SYNC 45 IPC_USB_VPOUT USB VOLTAGE POSITIVE OUT M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 49 ADS Connectors and Signals Table 4 33 Baseband Board Connector J24 Signal Description continued Pin Signal Description 46 R_STXD3 SEIAL TRANSMIT DATA 47 GND SIGNAL GROUND 48 R_SRXD3 Audio Port 3 RECEIVE DATA 49 R_CSPI1_SS2 CSPI1 SLAVE SELECT 2 50 GND SIGNAL GROUND 51 GND SIGNAL GROUND 52 GND SIGNAL GROUND 53 IPC USB VMIN USB VOLTAGE MINUS IN 54 CSPI3 MISO CSPI3 MASTER IN SLAVE OUT 55 IPC USB 05 VOLTAGE POSITIVE IN 56 CSPI3 MOSI CSPI3 MASTER OUT SLAVE IN 57 GND SIGNAL GROUND 58 CSPI3_SCLK CSPI3 SERIAL CLOCK 59 R_CSPI_SCLK CSPI SERIAL CLOCK 60 R_CSPI1_SPI_RDY CSPHSPI READY 61 GND SIGNAL GROUND 62 GND SIGNAL GROUND 63 GND SIGNAL GROUND 64 GND SIGNAL GROUND 4 2 21 Debugging and Programming Connectors The Base board has two connectors that provide buffered MCU address data and control signals for debugging and two connectors that can be used to program the CPLD and the single wire EEPROM 4 2 24 4 Software Analysis Connector P9 is the software analysis conn
108. UART ENET_ FSH_ PB_ FEED INT2 INT1 IRQ INTB INTA RT INT HESS hes RES OVR oe IRQ LOW_BAT OPER R W RW R W R W R W R W R W RW RW RAW R W RW R W R W R W R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 11 Interrupt Mask Register IMR 3 4 GPIO Interrupt Grouping and Non registered Interrupts Some interrupt signals are not associated with a CPLD register but are routed to a GPIO pin inside the CPLD The SD and Memory Stick detect functions are compared in a logical OR because only one type can implemented at a time Table 3 14 shows interrupt grouping and Table 3 15 shows status bit descriptions Table 3 14 GPIO Interrupt Grouping GPIO Pin Interrupt Sources GPIO1_1 SD1 DET MS1 DET GPIO1 2 SD2 DET MS2 DET GPIO1 3 PRI INT MC13783 GPIO1 4 XUART XUART INT LOW BAT PB IRQ FS OVR OTG FS FSH_OVR SYNTH_IRQ CE_INT1 CE_INT2 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 15 ADS Operation Table 3 15 GPIO Interrupt Bit Descriptions Name Description Settings GPIO1_1 SD1 OR MS1 memory card detect status 5 1 EH GPIO1_2 SD2 OR MS2 memory card detect status E oe GPIO1 3 AMC13783 Primary Interrupt output status bit Mida aera GPIO1_4 Registered Interrupt Status bit eos
109. Wire Data signal PC_BVD1 7 PCMCIA Battery Voltage Detect 1 PC_BVD2 9 PCMCIA Battery Voltage Detect 2 PC_CD1_B 46 PCMCIA Card Detect 1 PC_CD2_B 44 PCMCIA Card Detect 2 PC_PWRON 12 PCMCIA Power ON PC_READY 45 PCMCIA READY PC_RST 5 PCMCIA RESET signal PC_RW_B 10 PCMCIA READ WRITE signal PC_VS1 47 PCMCIA Voltage Sense 1 signal PC_WAIT_B 43 PCMCIA WAIT signal PC_VS2 14 PCMCIA Voltage Sense 1 signal PWMO 11 PULSE WIDTH MODULATOR OUTPUT RI_DCE1 171 UART1 DCE signal Ring Indicator RI_DTE1 181 UART1 DTE signal Ring Indicator SCK4 54 Audio Port 4 Serial clock SCK5 58 Audio Port 5 Serial clock SD1_CLK 31 SD MMC CLOCK Clock output to SD MMC card SD1 CMD 33 SD MMC COMMAND Serial command bit to SD MMC card bidirectional SD1 DATAO 21 SD MMC DATA BIT 0 Serial data bit to SD MMC card bidirectional 501 DATA1 23 SD MMC DATA BIT 1 Serial data to SD MMC card bidirectional 501 DATA2 25 SD MMC DATA BIT 2 Serial data to SD MMC card bidirectional SD1 DATA3 27 SD MMC DATA BIT 3 Serial data to SD MMC card bidirectional SFS4 52 Audio Port 4 Frame Sync SFS5 62 Audio Port 5 Frame Sync SRXD4 50 Audio Port 4 Receive Data SRXD5 60 Audio Port 5 Receive Data STXD4 48 Audio Port 4 Transmit Data STXD5 64 Audio Port 5 Transmit Data UART1_CTS 172 UART1 CLEAR TO SEND M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 9 ADS Connectors and Signals Table 4 2 Base Board to CPU Board Conn
110. ale Semiconductor ADS Operation Table 3 9 Board Control Register 2 Bit Definitions Name Description Settings USELA UART A SELECT Select UART A source on the 0 the source is UART1 signals Bit 0 CPU 1 source is UART5 signals USELB UART SELECT Select UART B source the 0 the source is UARTS signals Bit 1 CPU 1 source is UART4 signals USELC UART C SELECT Select UART C source on the 0 source is UART2 signals Bit 2 CPU 1 source is UART1 signals UMODENA UART A MODEM Enable Enable UART 0 UART C MODEM signals enabled Bit 3 MODEM signals 1 UART C MODEM signals disabled UMODENC MODEM Enable Enable UART C 0 UART C MODEM signals enabled Bit 4 MODEM signals 1 UART C MODEM signals disabled CSI_EN 0 CSI enabled Bit 5 CSI Enable Enable the CSI Interface 1 CSI disabled ATA EN 0 ATA enabled Bit 6 ATA_Enable Enable the ATA interface 1 ATA disabled ATA_SEL ATA Select Select CPU signals connected to the 0 group A is connected to ATA interface Bit 7 ATA interface 1 group B is connected to ATA interface A transition from high to low while IRDA_TXD is low IRDA_MOD SIR MIR bandwidth Bit 8 IRDA Mode Select IRDA Transceiver bandwidth transition from high to low while IRDA_TXD is high FIR bandwidth LCDRSTO 0 smart parallel LCD 1 reset signal negated Bit 9 LCD 0 Reset Rese
111. ata bus 54 B In Chip select 4 used for peripheral access BEO B In Byte Enable 0 which corresponds with D 7 0 BE1 B In Byte Enable 1 which corresponds with D 15 8 OE B In Output Enable RW B In Read write signal RSTIN B In Reset signal DMAREQ Out DMA Request to CPU i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 3 49 Peripheral Interface The CPLD s peripheral interface provides address decode and control for the CS8900A Ethernet controller the SC16C652 DUART and the YMU782B audio synthesizer The signals involved with this activity are listed in Table 3 3 Table 3 3 Peripheral Interface Signals Signal DIR Description PBA 2 0 Out Peripheral Bus Address PBD 7 0 In Out Peripheral Bus Data used for DUART board version switches IOR B Out Read is asserted during read transfers and DMA transfers IOW B Out Write is asserted during 70 write transfers MEMRB Out Memory read to Ethernet controller is asserted during memory read transfers MEMW_B Out Memory write to Ethernet controller is asserted during memory write transfers AEN Out Address enable asserted during Ethernet controtier DMA transfers ENET_DMAREQ In DMA request from Ethernet controller ENET DMACK B Out DMA acknowledge to Ethernet controller ENET CS B Out Ethernet chip select CS B Out UART A chip select CS B Out UART B chip select SYNTH C
112. atures include i MX31ADS Features Three board system Base board with display and interface connectors CPU board with 1 31 ARM11 MCU Power management board with MC13783 chip 5 0 VDC 2 4 A universal power supply QVGA LCD display panel with touchscreen capability and LED backlight Keypad with 64 push button keys Image sensor camera Configurable intelligent management of system power Separate selectable voltage regulators for running the CPU board in stand alone mode Two selectable system clock sources 32 768 kHz and 26 MHz Onboard CPLD that manages memory mapped expansion I O interrupts and general purpose I O Multi ICE debug support 32 MB of 16 bit NOR burst flash memory 16 MB of 16 bit PSRAM 128 MB of 32 bit DDR SDRAM memory Two sets of two memory card connectors selectable as SD MMC on Base board or MS on CPU board with card sense functionality 1G bit x8 data NOR Flash on a removable card SIMM card connector PCMCIA connector NAND Flash card connector Three RS 232 interfaces with DB 9 connectors driven by UART channels internal to the MX31 Each interface has two UART options and power up enable DIP switches One supports DCE with optional full modem controls another is DTE with optional full modem controls and the third is DTE with RTS CTS controls only An external DUART configured as two RS 232 DCE channels one DB9 connector one 10 pin header Two USB host transceivers one full spee
113. ce interrupt request 1 Interrupt from USB Host full speed interface XUART_INTA External UART A interrupt External UART A 0 No interrupt from External UART A Bit 10 interrupt request 1 Interrupt from External UART A XUART_INTB External UART B interrupt External UART B 0 No interrupt from External UART B Bit 11 interrupt request 1 Interrupt from External UART B SYNTH_IRQ Audio Synthesizer IRQ Audio Synthesizer interrupt 0 No interrupt from Audio Synthesizer Bit 12 request 1 Interrupt from Audio Synthesizer CE_INT1 Communication Engine Interrupt 1 CE bus 0 No interrupt from CE INT1 Bit 13 interrupt request 1 1 Interrupt from CE INT2 Communication Engine Interrupt 2 CE bus interrupt 0 No interrupt from CE INT2 Bit 14 request 2 1 Interrupt from CE INT2 3 3 6 9 Interrupt Signal Status Register ISSR This register shows the state of each edge triggered interrupt source This register is a read only register BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSH ore PB FIELD RES RES RES RES RES RES RES RES RES RES RES RES gt FS gt LOW_BAT OVR OVR IRQ Figure 3 10 Interrupt Signal Current State Status Register ISCSSR i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ADS Operation Table 3 13 Interrupt Signal Status Register Bit Definitions Name Descrip
114. d and one high speed with standard USB host connectors Three USB OTG transceivers one full speed and one high speed on the Base board one full speed on the MC13783 board with mini AB connectors 10 Base T Ethernet controller with RJ 45 connector with built in data flow LED indicators IrDA Specification 1 4 transceiver supports fast medium and slow operating modes ATAS controller with 44 position dual row 2 mm header for small form factor disk drives I2C interface with one of two selectable MCU interfaces CSPI connector i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor General Information e Two CSI connectors with different image sensor orientations e Smart serial LCD display connector QVGA LCD display connector with touch screen interface plus companion connector with additional control signals Two smart parallel LCD display connectors TV encoder connector e Keypad connector Interface connector to baseband processor e Audio synthesizer chip with microphone and line inputs 3 5 mm jacks line voice and headphone outputs 3 5 mm jacks and speaker output screw terminals Eight DIP configuration switches with user definable functions Software readable CPU and Base board versions LED indicators for 5 IN 3 3V vibrator output and synthesizer output Two LED indicators for user defined function Piezoelectric audible alert and vibratory alert Three funlight indicators a
115. d to scan a keypad 11 KP_COL3 KEYPAD COLUMN 3 Bidirectional signal used to scan a keypad 12 ROW3 KEYPAD ROW 3 Bidirectional signal used to scan keypad 13 KP_COL2 KEYPAD COLUMN 2 Bidirectional signal used to scan a keypad 14 KP_ROW2 KEYPAD ROW 2 Bidirectional signal used to scan a keypad 15 KP_COL1 KEYPAD COLUMN 1 Bidirectional signal used to scan a keypad 16 KP_ROW1 KEYPAD ROW 1 Bidirectional signal used to scan a keypad 17 KP_COLO KEYPAD COLUMN 0 Bidirectional signal used to scan a keypad 18 KP_ROWO KEYPAD ROW 0 Bidirectional signal used to scan a keypad 19 NC NO CONNECTION 20 GND GROUND The signal name in italics is the function intended for operation with this connector It is multiplexed in the i MX31 processor with the listed signal M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 27 ADS Connectors and Signals 4 2 5 4 2 5 1 Display Connectors Synchronous LCD Connector J12 is a connector for a synchronous serial LCD panel interface Figure 4 7 shows pin assignments and Table 4 11 describes connector signals J12 VCC 15 552 GND OE ACD 4 FLM_VSYNC_SPS LP_HYSYNC 5 6 LSCLK LD5_B5 75 9918 LD4 B4 LD3 B3 9 e 10 102 BR LD11 G5 11 12 LD10_G4 LD9 G3 13 e 14 108 G2 1017 5 15 e e 16 LD16_R4 LD15 R3 17 e e 18 LD14_R2 CONTRAST 19 e e 20 LCDON SPL_SPR 21 e 22 REV PS 23 24 CLS LD1
116. ded to better hold the card in place and these will need to installed too The card provided with the ADS uses an 8 bit interface and has 1 gigabits of storage For details on the NAND Flash interface refer to the specification document on the documentation CD i MX31ADS User s Manual REV 1 Preliminary 3 18 Freescale Semiconductor ADS Operation 3 7 USB On The Go Interface FS LS The ADS provides a USB OTG Full Speed Low Speed interface that uses a Phillips ISP1301BS USB transceiver connected to J2 a mini AB USB connector The interface can function as either a USB host or USB device The interface provides power to the USB bus in host mode This power may be supplied by the Phillips part or from the external 5 volt power source through a MIC2536 power switch For details on the operation of this USB interface refer to the 1 3 data sheet Figure 3 14 shows this USB interface connection Note that if MC13783 OTG transceiver is used this interface cannot be used ISP1301BS J2 i MX31 USB Device HOST USBOTG DO0 7 TO MC13783 USB USBOTG FS SEL USBOTG FS 5V USB MINI AB OTG FS OVR OTG VBUSEN B MIC2536 2BM Figure 3 14 USB OTG FS LS Interface 3 8 USB On The Go ULPI Interface HS The ADS provides a USB OTG High Speed 480M bps interface that uses a Phillips ISP1504 USB ULPI transceiver connected to J1 a mini AB USB connector It can also operate at Full Speed or Low Speed The
117. des byte steering logic to transfer the correct byte to the SC16C652C during data transfers 3 3 3 4 SCS8900A Ethernet Decode The CPLD provides address decode and control for the CS8900A Ethernet controller Both 16 bit I O mode and memory mode are supported Memory mode operation allows direct access to the CS8900A internal registers and frame buffer A single DMA request line is provided for DMA transfers from the CS8900A buffer to system memory for increased performance Accesses to the CS8900A must satisfy the following requirements Provide a transition of the SBHE input after reset This is done with a dummy byte read to an odd location as for example a byte read to B400 0007 All reads and writes to the CS8900A must be 16 bits For memory mode operation the base address register must be set to 1000 This is a 20 bit register and the upper 4 bits must be 0 3 3 3 5 YMU782B Audio Synthesizer Decode The CPLD provides address decode and data path control for the YMU782B audio synthesizer Data is transferred through the CPLD to and from the YMU782B The CPLD provides byte steering logic to transfer the correct byte to the YMU782B during data transfers All reads and writes to the YMU782B must be eight bits 3 3 4 UART Multiplexing UARTC has one DTR line from the UART transceiver This line is muxed to either MCU or UART2 The muxing is determined by the UARTC SEL field in the BCTRL2 register i MX31ADS User s
118. e ADS Communication with this card takes place through the interface For details on image sensor operation refer to the data sheet on the documentation CD CAUTION To avoid circuit damage do not plug in the image sensor card with power applied to the board i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 25 ADS Operation To install the image sensor card plug its 48 position DIN connector into either J10 or J13 of the Base board When the image sensor card is installed at J10 the two boards are at a right angle to each other with the image sensor facing away from the Base board When the image sensor card is installed at J13 the two boards are parallel and the image sensor faces up away from the Base board 3 21 Using the TV Encoder A TV encoder card is supplied with the ADS The main component is a FS453 PC to TV Video Scan converter from FOCUS Enhancements Semiconductor For details on TV encoder operation refer to its data sheet available at http www focusinfo com CAUTION Make sure that input power is disconnected or switched off before the TV encoder card is installed Connecting the card with power applied can damage the TV encoder card and the Base board This TV encoder cannot be used at the same time as any parallel LCD display because they share IPU data connections To use the TV encoder module you must disconnect the TFT LCD board from J12 on the Base board and install the TV
119. e Protected Bit 7 01 Write Protect This bit reflects the Write Protect SD1 card 1 SD1 card is not Write Protected SD2 WP PUT 0 802 card is Write Protected Bit 8 SD2 Write Protect This bit reflects the Write Protect SD2 1 SD2 card is not Write Protected FLIP_SENSE1 Flip Sense 1 This bit reflects the status of pin Flip Sense1 on the 0 Flip Sense 1 on keypad is 0 Bit 9 keypad connector 1 Flip Sense 1 on keypad is 1 FLIP_SENSE2 Flip Sense 2 This bit reflects the status of pin Flip Sense2 on the 0 Flip Sense 2 on keypad is 0 Bit 10 keypad connector 1 Flip Sense 2 on keypad is 1 PTT PTT button This bit reflects the status of pin PTT on the keypad 0 PTT signal on keypad is 0 Bit 11 connector 1 PTT signal on keypad is 1 ATLAS_IN ATLAS IN This bit indicates if the power management board 0 MC13783 board is placed Bit 12 MC 13783 is placed on the board 1 2 MC13783 board is not placed RSV Bits 13 15 Reserved for future use Always reads 0 BSTAT2 contains several bits that represent the board status from different places on the board These registers are read only BIT 15 14 13 12 11 10 9 8 71654321 0 FIELD RSV RSV RSV RSV RSV RSV RSV DMA_REQ DSW OPER R R R R R R R R R Figure 3 4 Board Status Register 2 BSTAT2 Table 3 7 Board Status Register 1 Bit Defi
120. ector Figure 4 26 shows pin assignments and Table 4 34 describes the signals 4 2 21 2 Address Connector P10 is the software analysis connector Figure 4 27 shows pin assignments and Table 4 35 describes the signals 4 2 21 CPLD Programming Connector J14 is the CPLD programming connector Figure 4 28 shows pin assignments and Table 4 36 describes the signals 4 2 21 4 One wire EEPROM Programming One wire EEPROM programming is enabled by Jumper 14 See Chapter 2 for more information M9328MX31ADS User s Manual Rev 1 Preliminary 4 50 Freescale Semiconductor ADS Connectors and Signals P9 TP33 1g TP32 GND TP31 BCLKO 5 6 CODE_TEST_CS_B BCS5_B ge B D15 BOE B 90 10 B 014 BRWB 1112 013 1314 B_D12 1516 Di BCSOB 1718 110 _ 19 20 B_D9 21 22 23 24 6 25 26 27 28 4 29990 3132 2 33 34 1 35 36 A 37038 B DO GND 3940 GND GND 4142 GND GND 43 Figure 4 26 Software Analysis Connector P9 Pin Assignment Table 4 34 Software Analysis Connector P9 Signal Description Pin Signal Description 1 TP33 TEST POINT 33 2 TP32 TEST POINT 32 3 GND SIGNAL GROUND 4 TP31 TEST POINT 31 5 BCLKO BUFFERED CLOCK 0 6 CODE_TEST_CS_B CODE TEST CHIP SELECT 7 BCS5_B BUFFERED CHIP SEL
121. ector P1 Signal Description continued Signal Pin Description UART1_RTS 170 UART1 REQUEST TO SEND UART1_RXD 176 UART1 RECEIVED DATA UART1_TXD 174 UART1 TRANSMITTED DATA UART2_CTS 182 UART2 CLEAR TO SEND UART2_RTS 180 UART2 REQUEST TO SEND UART2_RXD 186 UART2 RECEIVED DATA UART2_TXD 184 UART2 TRANSMITTED DATA USB_BYP 68 USB BYPASS USB_OC 70 USB OUTPUT CONTROL USB_PWR 72 USB POWER USBOTG_CLK 57 USB OTG CLOCK USBOTG_DATAO 61 USB OTG DATA USBOTG_DATA1 63 USB OTG DATA USBOTG_DATA2 65 USB OTG DATA USBOTG_DATA3 67 USB OTG DATA USBOTG_DATA4 69 USB OTG DATA USBOTG_DATA5 71 USB OTG DATA USBOTG_DATA6 73 USB OTG DATA USBOTG_DATA7 75 USB OTG DATA USBOTG_DIR 53 USB OTG DIRECTION USBOTG_NXT 55 USB OTG NEXT USBOTG_STP 51 USB OTG STOP VSD1 17 19 CONDITIONED POWER SUPPLY FROM PM VSD2 40 42 CONDITIONED POWER SUPPLY FROM PM M9328MX31ADS User s Manual Rev 1 Preliminary 4 10 Freescale Semiconductor ADS Connectors and Signals Table 4 3 Base Board to CPU Board Connector P2 Signal Description Signal Pin Description 2 4 6 3V3 116 118 3 VDC POWER ATLAS_IN 186 ATLAS PM INPUT B_AO 74 BUFFERED ADDRESS MCU address bus 1 72 BUFFERED ADDRESS MCU address bus B_A2 70 BUFFERED ADDRESS MCU address bus B_A3 68 BUF
122. een 5V CPU 5 V power is D4 Green 3 3V CPU 3 3 V power is ON D5 Yellow STAT 0 BASE User status controlled by CPLD D6 Yellow STAT 1 BASE User status controlled by CPLD T1 Green ACTIVE BASE Blinking indicates LAN Activity T1 Yellow LINK BASE Link good or host controlled output T1 Red BSTAT BASE ISA bus activity D1 Yellow LED SYNTH BASE YUM782B output indicator D4 D10 Yellow LEDxx FORCE MC13783 Backlight LED indicator not provide D11 D12 D13 Yellow FUNLITES MC13783 Tri colored LEDs used for color mixing i MX31ADS User s Manual REV 1 Preliminary 3 24 Freescale Semiconductor ADS Operation Table 3 17 Function of LED Indicators Reference Color Name ADS BOARD Function D21 D40 Yellow PWRONX MC13783 ON indicates the MC13783 voltage active 3 17 Sound Synthesizer The ADS includes a Yamaha YUM783 mobile audio synthesizer This device can simultaneously generate up to 64 different voices 32 FM synthesized 32 wave table The CPLD decodes a sixteen bit chip select and provides the byte routing for the synthesizer A speaker connectors and a 3 5mm headphone jack are provided las well as low and high impedance inputs and outputs mono These signals can to connected to the MC13783 board audio interface using standard 3 5mm patch cables There is also a digital audio interface that may be used with MCU audio port 6 YUM783 data sheet is provided on the ADS data CD 3 18 Usin
123. encoder module in J12 and J1lof the Base board 3 22 Using a Plug in Memory Card The ADS provides several plug in memory cards Two Memory Stick card holders are on the CPU card J5 J6 The Base board has two SD MMC card holders P3 P4 as well as a SIMM card connector P8 The Memory Stick and SD MMC connectors share the same control signals from the i MX31 J5 MS1 shares with SD MMC1 16 MS2 shares with SD MMC2 The interface signals to the Memory Stick on the CPU card are multiplexed They are either routed to the cards or to the Base board where they may be used with the SD MMC cards or some other designated interface Each Memory Stick mux has an individual control signal from the CPLD Interface signals are provided by the 1 M X31 but write protect and card detect inputs read through the CPLD Power to the card requires the MC13783 card The associated NVCC power must also be set to select the same MC13783 provided power source You must obtain a compatible card for use with these connectors 3 23 Using a PCMCIA Card The ADS comes equipped with a PCMCIA card holder U30 on the Base board Most of the PCMCIA interface signals are buffered including the data and address that are shared with other system peripherals The card is powered by a LTC1472CS power switch Only 3 3V cards are supported and MC13783 power is not required The CPLD controls the LTC1472CS It can turn VCC power ON and OFF and VPP power can
124. ent MCU UART channels CPLD settings determine which UARTS are enabled at start up see paragraph 3 3 for more information The four SPST slide switches in SW1 control the power up status of the UARTs and the IrDA transceiver Setting a switch to ON makes the UARTA UARTB UARTC or FIR interface active on ADS power up Enabling an interface allows it to be used immediately by software without additional configuration Setting a switch to OFF disables an interface until it is enabled by software i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 1 Configuring and Connecting the ADS Table 2 1 Base Board SW1 Switch Function Switch Designation i MX31 UART Channel 5 ON ENABLED SW1 1 FIR Default UART OFF DISABLED UART3 ON ENABLED SW1 2 UARTB Default UART OFF DISABLED UART1 ON ENABLED SW1 UARTA Default UART OFF DISABLED UART2 ON ENABLED SW1 4 UARTC EN Default UART OFF DISABLED 2 2 1 2 SW2 5 232 MBaud Shut Down WDI and Buzzer Enable Switches Table 2 2 shows SW2 switch functions The eight SPST slide switches in SW2 control system baud rate shutdown watchdog interface and buzzer enable functions Set SW2 1 to ON to enable the MC13783 Watch Dog Interrupt function When enabled software must pulse this output within a window of time or the MC13783 will shut down the system Set SW2 2 to ON to connect the PWM output
125. ented JMP2 selects use of a vibratory or light LED alarm JMP4 selects the source of the TXIN signal JMP5 to JMP8 control whether the outputs of the switching supplies on the MC13783 are connected in parallel JMP11 selects a power source for the MC 13783 chip Table 2 13 shows Jumper functions Figure 2 7 shows the jumper locations CAUTION The settings of SW1 A B control jumpers JMP5 and JMP7 must be the same The settings of SW2 A B control jumpers JMP6 and JMP8 must be the same Table 2 13 MC13783 Board Jumper Headers Jumper Designation Pn 9 12 2 12 Vibrator Alarm Select LED i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 15 Configuring and Connecting the ADS Table 2 13 MC13783 Board Jumper Headers continued Jumper Designation Pin 9 Connection INP IMPS SWI Supply Combination IME SW2 Supply Combination 7 SWI Supply Combination IMPS SW2 Supply Combination Power Source Select e ese baa ai di d di di di 5 W j e 2 is 8 aise 2 Qa 1 ina T 2 diit F 53243 3 3 JMP6 8 JMP5 JMP7 JPM2 JMP11 Figure 2 7 MC13783 Board Jumper Headers i MX31ADS User s Manual REV 1 Prel
126. er Management System ATA CD CMOS CPLD CPU CSI CSPI DCE DDR DIN DIP DMA DTE DUART EEPROM EPROM FIR GPIO PC ICE IrDA ISA JTAG LAN LCD LED MB MCU MMC Hard drive interface spec Compact Disk Complementary Metal Oxide Semiconductor Custom Programmed Logic Devices Central Processing Unit Camera Sensor Imaging Serial Peripheral Interface Data Communications Equipment Double Data Rate Deutsches Institut f r Normung Dual In line Package Direct Memory Access Data Terminal Equipment Dual Universal Asynchronous Receiver Transmitter Electrically Eraseable Programmable Read Only Memory Eraseable Programmable Read Only Memory Infra Red General Purpose Input Output Inter Integrated Circuit In Circuit Emulator Input Output Infrared Data Association Instrumentation System and Automation Society Joint Test Access Group Local Area Network Liquid Crystal Display Light Emitting Diode Megabyte Microcontroller Unit Multi media Card i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor MCP MS NVRAM OTG PC PCMCIA PCB PCMCIA PHY POR PSRAM PWM QVGA RAM SD SDRAM SI SIMM SPST SSI TFT UART USB Multi chip product Memory Stick Non volatile Random Access Memory On the Go Personal Computer Personal Computer Memory Card International Association Printed Circuit Board Personal Computer Memory Card International Association Physical interface Pow
127. er On Reset Pseudo Random Access Memory Pulse Width Modulation Graphics Adapter Random Access Memory Smart Digital Synchronous Dynamic Random Access Memory Systeme International international system of units and measures Single In Line Memory Module Single Pole Single Throw Synchronous Serial Interface Thin Film Transistor Universal Asynchronous Receiver Transmitter Universal Serial Bus i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor xi i MX31ADS User s Manual REV 1 Preliminary xii Freescale Semiconductor Chapter 1 General Information 1 1 Description The 1 MX31ADS helps you develop multimedia communication applications using the i MX31 s ARMII MCU and the MC13783 audio and power management chip The ADS consists of a Base board a CPU board and an MC13783 board The system supports application software development target board debugging and optional circuit cards The CPU board can be run in stand alone mode for code development An LCD display panel an image sensor and a separate keypad are supplied with the ADS The image sensor can be connected to the base board in different orientations Figure 1 1 shows the major components of the ADS BASE BOARD MC13783 BOARD mue ma a NE KEYPAD Figure 1 1 i MX31ADS Application Development System i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 1 1 General Information 1 2 ADS fe
128. er up Mode 2 15 MC13783 Board Jumper 2 15 ADS M mory Map raed pex WINE 3 2 CPU M pde 3 3 Peripheral Interface Signals oe ad REN tes ee QI ASO 3 4 Bus Gyeleg c EE ENE ROR NOUO 3 4 CFED Memory cba deca ai he a bL qr 3 6 Board Status Register 1 Bit Definitions 3 8 Board Status Register 1 Bit Definitions 3 8 Board Control Register 1 Bit 3 10 Board Control Register 2 Bit 3 11 Board Control Register 3 Bit 3 12 Board Control Register 4 Bit 8 3 13 Interrupt Status Clear Register Bit 3 14 Interrupt Signal Status Register Bit Definitions 0 0 0 eee eee eee 3 15 GPIO Interr pt Grouping ten ba eas Bee 3 15 GPIO Interrupt Bit 3 16 Keypad Layout and Connections 1 3 24 Fu nc
129. escription continued Pin Signal Description 19 CONTRAST LCD bias voltage used as contrast control 20 LCDON LCD enable Active High Enables the Sharp LCD 21 SPL_SPR SAMPLING LEFT to RIGHT Horizontal scan direction 22 REV Signal for common electrode driving signal preparation Sharp panel dedicated signal 23 PS Control signal output for source driver Sharp panel dedicated signal 24 CLS Start signal output for gate driver This signal is inverted version of PS Sharp panel dedicated signal 25 LD1 B1 LCD DATA 1 BLUE BIT 1 Output data to LCD 26 LDO BO LCD DATA 0 BLUE BIT 0 Output data to LCD 27 LD7 G1 LCD DATA 7 GREEN BIT 1 Output data to LCD 28 LD6 GO LCD DATA 6 GREEN BIT 0 Output data to LCD 29 LD13 R1 LCD DATA 13 RED BIT 1 Output data to LCD 30 LD12 RO LCD DATA 12 RED BIT 0 Output data to LCD 31 TOP Negative pen Y analog input 32 BOTTOM Positive pen Y analog input 33 LEFT Negative pen X analog input 34 RIGHT Positive pen X analog input 4 2 5 2 Option Connector Connector J11 provides optional LCD panel control signals Figure 4 8 shows connector pin assignments and Table 4 12 describes connector signals J11 LED MD1 114 12 PM_VBLITE LED_MD2 3 14 LED_MD3 LED_MD4 5 6 GND 7 8 NC NC 9 e e 10 CVDD_2 775V LED 11 12 NC DVDD_1 8V 13 14 NVCC7 GPIO1 15 e 6
130. g the TFT LCD Display Panel The ADS is equipped with a Sharp LQ035Q7DB02 touch control enabled TFT LCD display assembly The ADS documentation CD contains specifications for the TFT LCD component CAUTION Make sure that the input power to the main board is disconnected or switched off before connecting the LCD module Connecting the module with power applied can damage the LCD module and or the main board To use the TFT LCD display connect the 34 conductor ribbon cable supplied with the ADS from J11 on the LCD module to J12 on the Base board The Touch Screen Controller is built into the MC13783 chip and therefore the MC13783 board is required for this function to operate The potentiometer VR1 which is to the left of the LCD panel just below controls flickering of the display screen This control is set at the factory and normally does not require adjustment However if the TFT LCD display flickers you may adjust to stabilize the display Use a suitable flat head or phillips head screwdriver Because the adjustment is normally done with power applied we recommend use of a plastic blade tool 3 19 Using the Keypad To use the keypad module connect the 30 conductor ribbon cable supplied with the ADS from connector P1 ofthe Keypad module to J21 of the Base board 3 20 Using the Image Sensor Daughter Card Connectors J10 and J13 are pre configured to operate directly with the IM8012 image sensor daughter card supplied with th
131. his is a new document Conventions Units and measures in this manual conform to the International System of Units SI as defined by United States National Institute of Standards and Technology Special Publication 811 Ranges of bits and signals are shown in square brackets A 15 0 Individual signals and bits within a range are shown with a numeric designator only A7 Logic level 0 is the voltage that corresponds to Boolean 0 logic level 1 is the voltage that corresponds to Boolean 1 When a signal is asserted it goes to the active logic state Active high signals go to logic level 1 active low signals go to logic level 0 When a signal is negated it goes to the inactive logic state Active high signals go to logic level 0 active low signals go to logic level 1 Setting a bit refers specifically to establishing logic level 1 on the bit clearing a bit refers specifically to establishing logic level 0 on the bit Ranges of bits may be set or cleared by a single operation Overbars are used to show active low or complemented signals and bits in text SIGNAL BIT Active low signal names are designated by the suffix b signal name b i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ix Acronyms and Abbreviations The following acronyms and abbreviations are used in this manual This list does not include signal register and software mnemonics ADS Application Development System APMSMC13783 Pow
132. i MX31ADS Application Development System User s Manual Document Number MCIMX31ADSRM UMS 00021 Rev 1 A 03 2006 e gt freescale semicon ductor Preliminary How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and soft
133. iminary 2 16 Freescale Semiconductor Configuring and Connecting the ADS 2 5 ADS Set up 2 5 1 CPU Board Regulator Power Configuration CAUTION Use this procedure to select NVCC power from on board regulators only when the CPU board is operated without the MC13783 board Configuring the power jumpers incorrectly can damage the ADS See paragraph 2 3 2 for more information about power jumper settings To use the CPU board with MC13783 power management refer to paragraph 2 5 2 1 Remove MC13783 Card if it is placed 2 Ifinstalled remove the following Baseboard jumpers J15 JP16 JP17 J18 JP19 720 J21 722 723 J24 JP25 and J26 Use these jumpers in step 3 3 Configure jumpers JP4 JP5 JP13 JP16 JP23 JP28 and JP36 for the desired voltage levels NOTE The jumpers are perpendicular to the other three pin jumpers on the board 4 Proceed to paragraph 2 5 3 2 5 2MC13783 Power Configuration CAUTION Use this procedure to select NVCC power only when the CPU board is operated with the MC13783 board Configuring the power jumpers incorrectly can damage the ADS See paragraph 2 2 2 for more information about power jumper settings To use the CPU board without MC13783 power management refer to paragraph 2 5 1 1 Remove jumpers JP4 JP5 JP13 JP16 JP23 JP28 and JP36 from the CPU board NOTE The jumpers are perpendicular to the other three pin jumpers on the board 2 Install the jumpers from 1 on Baseboard jumpers J15
134. l control provides a three bit field for o User defined function Bits 8 10 control of user defined functions on the CSI connector CCTL2 2 0 CSI2 Control CSI control provides a three bit field for Bits 11 13 control of user defined functions on the CSI connector Ei sn Internal register used as endian indicator Internal function LCDON 0 LCD is off Bit 15 LCD ON Used to turn the QVGA dumb LCD display on 1 LCD on 3 3 6 5 Board Control Register 2 BCTRL2 BCTRL2 contains several bits that control various board functions This register is implemented as a set register and a clear register To set a bit write a 1 to the bit at the set address To clear a bit write a 1 to the bit at the clear address BT 15 144 13 1 1 9 7 5 2 1 VOC_ VPP_ CT_ LCDIO_ LCD_ LCD_ LCD_ IRDA_ USE USE USE EN EN CS EN RST2 RST1 RSTO MOD SEL EN EN LC LB LA RW RW RW Aw RW RW Aw 1 1 121211011 1 1 IN OUT OUT OUT OUT n 1 Rd OUT OUT OUT OUT OUT OUT pda ae Figure 3 6 Board Control Register 2 BCTRL2 i MX31ADS User s Manual REV 1 Preliminary Freesc
135. lon 0 is reset Bit 15 connector 1 Normal operation i MX31ADS User s Manual REV 1 Preliminary 3 12 Freescale Semiconductor ADS Operation 3 3 6 7 Board Control Register 4 BCTRL4 BCTRL4 contains several bits to control various board functions This register is implemented as a set register and a clear register To set a bit write a 1 to the bit at the set address To clear a bit write a 1 to the bit at the clear address 15 14 13 12 1 10 9 7 5 4 3 2 1 0 PCMCIA USER REGEN CSI FIELD RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV 7 EN EN SEL MSE EN 8 RW R W R W R W R W 0 o 1 0 0 1 1 our our our our IN OUT OUT oD OD Figure 3 8 Board Control Register 4 BCTRL4 Table 3 11 Board Control Register 4 Bit Definitions Name Description Settings CSI EN 0 CSI Data 3 0 enabled Bit 4 1 CSI Data 3 0 disabled REGEN SEL Regulator Enable Select Select predefined programming for 13783 0 REGEN SEL active Bit 1 regulators 1 REGEN SEL not active CSI MSB Enable Enable CSI Data 3 0 from CSI interface USER OFF n t 0 normal operation Bit 2 U
136. nd funlight connector e Push button Reset CPU or reset control from MC13783 wire EPROM e Push button interrupt source Two Mictor LA SW Analysis Connectors Base board Four Samtec LA Connectors CPU Three Extension connectors two are compatible with the MX21 ADS Extension connectors Special MC13783 board features Stereo microphone jack normal microphone jack external TXIN jack headphone jack low level stereo input and output Jacks stereo and mono ear piece speaker terminals Main battery emulation from 5V Main battery connection terminals Back up battery emulation super cap Coin cell backup battery connection terminals Battery charger input terminals Backlight LED indicators Three Push button switches to act as power on off switches DIP switches to select default power up power and power sequencing USB mode USB enable and WDI disable DIP Switches Audio clock source selection DIP Switches Individual test point and LED indicator for each MC13783 voltage USB cables RS 232 serial cable and two RJ 45 Ethernet cables network and crossover i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 1 3 General Information 1 3 System and User Requirements To use the ADS you need e An PC or compatible computer that has A Microsoft Windows 98 Windows ME Windows 2000 Windows XP or Windows NT version 4 0 operating system
137. niature A External 32 kHz Clock Input CN5 Wire Clamp Terminals Battery Charger Input CN6 Wire Clamp Terminals Left Stereo Speaker Output CN7 Wire Clamp Terminals External Battery Input CN8 10 pin Header MC13783 Touch Screen Interface CN9 Wire Clamp Terminals Lithium Battery Input CN10 Subminiature A External Audio Bus Clock Input CLIA CLIB J1 Miniature Audio Jack RX Line Input Stereo J2 Miniature Audio Jack RX Line Output Stereo J3 Miniature Audio Jack Headset Microphone Input 2 Mono J4 Miniature Audio Jack Handset Microphone Input 1 Stereo J5 215 pin Connects MC13783 board to Base board J6 215 pin Connects MC13783 board to Base board J7 Miniature Audio Jack TX Line Input J8 Miniature Audio Jack Headphone Output Stereo M9328MX31ADS User s Manual Rev 1 Preliminary 4 74 Freescale Semiconductor ADS Connectors and Signals CN10 CN4 5 CN9 CN7 2660509002009 m trao enn n gt 2 der L id en Pat ae T 1247 898999980 Af VA3U 69 00 ASSY LOS CN8 J1 J2 J7 J4 J3 J8 CN2 CN1 NOTE J5 AND J6 ARE LOCATED ON THE UNDERSIDE OF THE BOARD Figure 4 40 MC13783 Connectors 4 4 1 Power Connectors CNS CN7 and CN9 are pairs of wire clamp terminals that provide for connection of external batteries and a battery charger
138. nitions Name Description Settings DSW 1 0 each bit switch is closed Bits 7 0 Debug switch This 8 bit field contains the value of the debug DIP switch 1 each bit switch is open DMA_REQ DMA Request this bit reflects the DMA request to CPU from the Ethernet 0 DMA Request is low Bit 8 controller 1 DMA Request is high i 15 Reserved These bits are reserved for future use Always read as 0 i MX31ADS User s Manual REV 1 Preliminary 3 8 Freescale Semiconductor ADS Operation 3 3 6 4 Board Control Register 1 BCTRL1 BCTRLI contains several fields to control various board functions This register is implemented as a set register and a clear register To set a bit write a 1 to the bit at the set address To clear a bit write a 1 to the bit at the clear address BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UB _ FIELD LCDON BEND CCTL2 CCTL1 LED1 B LEDO EN B EN BIEN BIEN B RST RST R W R W RAW RAW R W R W R W R W RW R W R W RESET 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OD OD OD OD OD OUT OUT OD OD OD OD OUT OUT Figure 3 5 Board Control Register 1 BCTRL1 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor
139. nnector Type Description Figure J1 Mini AB USB OTG high speed Figure 3 1 top J2 Mini AB USB OTG full speed Figure 3 1 top J3 44 pin header Small form factor ATA Figure 3 2 top J4 Standard USB Host USB host high speed Figure 3 1 top J5 Standard USB Host USB host full speed Figure 3 1 top J6 16 pin header Smart serial LCD Figure 3 2 right J7 10 pin header UART B ADS RS 232 DCE Figure 3 1 top J8 40 pin header Smart parallel LCD 2 Figure 3 2 right J9 40 pin header Smart parallel LCD 1 Figure 3 2 right J10 16 pin 3 row CSI 1 horizontal Figure 3 1 left J11 16 pin header Synchronous LCD option Figure 3 2 right J12 34 pin header Synchronous LCD Figure 3 2 right J13 16 pin 3 row CSI 2 vertical Figure 3 1 left J14 10 pin header CPLD in circuit programming Figure 3 1 left J15 20 pin header CSPI interface Figure 3 2 right J16 10 pin header TV encoder Figure 3 2 right J17 16 pin 3 row Expansion 1 horizontal Figure 3 1 left J18 20 pin header MC13783 A D not populated Figure 3 1 bottom J19 14 pin header CE bus Figure3 1 left J20 16 pin header Funlight Figure 3 2 right J21 30 pin header Keypad Figure 3 2 right J22 16 pin 3 row Expansion 1 horizontal Figure 3 1 left M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 1 ADS Connectors and Signals Table 4 1 Base Board Connectors continued Connecto
140. onal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners ARM is the registered trademark of ARM Limited ARM11 is the trademark of ARM Limited Freescale Semiconductor Inc 2005 2006 All rights reserved Preliminary Table of Contents About This Book Chapter 1 General Information 1 1 DESCHDUON ase hla ues gd Ped deti ged dues ede 1 1 22 amp MXIIADS te Cae 1 2 1 3 System and User Requirements 1 4 ADS eoxersc eo CEU A ae Pau e 1 4 Chapter 2 Configuring and Connecting the ADS 2 1 Introd RO Sut a eg ewe
141. onnection for an earpiece speaker All have one analog signal connection and one signal ground connection M9328MX31ADS User s Manual Rev 1 Preliminary 4 76 Freescale Semiconductor ADS Connectors and Signals 4 4 3 USB OTG Connector CN3 is a USB mini AB connector It connects to the MC13783 USB OTG interface Figure 4 42 shows pin assignments and Table 4 52 describes the signals SV D Dt ID Figure 4 42 USB OTG Connector CN3 Pin Assignment Table 4 52 USB Connector CN3 Signal Description Pin Signal Description 1 5V 5 VDC BUS VOLTAGE 2 D USB DATA MINUS 3 D USB DATA PLUS 4 ID BUS ID 5 GND GROUND 4 4 4 Touchscreen Connector CN8 connects to the MC13783 touch screen interface pins Figure 4 43 shows pin assignments and Table 4 53 describes the signals CN8 TCK 1 2 GND TMS 3 4 GND TDI 5 3V3 TDO 7 8 GND NC e 10 NC Figure 4 43 Touchscreen Connector CN8 Pin Assignment Table 4 53 Touchscreen Connector CN8 Signal Description Pin Signal Description 1 TSX1 TOUCH SCREEN X AXIS 1 2 GND SIGNAL GROUND 3 TSX2 TOUCH SCREEN X AXIS 2 4 GND SIGNAL GROUND 5 GND SIGNAL GROUND 6 GND SIGNAL GROUND 7 TSY1 TOUCH SCREEN Y AXIS 1 8 GND SIGNAL GROUND 9 TSY2 TOUCH SCREEN Y AXIS 2 10 GND NO CONNECTION M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semicond
142. onnectors Left Side M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 3 ADS Connectors and Signals J6 49 48 912 J11 J16 J15 J20 J21 J27 P6 J28 J29 P11A P11B Figure 4 2 Base Board Connectors Right Side M9328MX31ADS User s Manual Rev 1 Preliminary 4 4 Freescale Semiconductor 4 2 1 Base Board to CPU Board Connectors ADS Base board connectors P1 and P2 mate with CPU board connectors J1 and J2 bottom side Figure 4 3 shows connector pin assignments Table 4 2 and Table 4 3 describe connector signals PC_RW_B PC_PWRON PV_VS2 GND CSP13 MOSI CSP13 MISO CSP13 SPI RDY CSP13 SCLK GND ATA DMAC ATA RESET B ATA DIOW ATA DIOR ATA CS1 ATA CSO GND GND VSD2 VSD2 PC CD2 B PC CD1 B STXD4 SRXD4 SFS4 SCK4 GND SCK4 SRXD4 SFS4 STXD4 GND USB_BYP USB_OC USB_PWR NVCC5 NVCC5 GND GND GND NVCC5 OWDAT CSPI2 SPI RDY CSPI2 SCLK GND IPU LCS1 IPU LCSO GND GND P1 5V 5V PC_RST PC_BVD1 PC_BVD2 PWMO CAPTURE COMPARE VSD1 VSD1 501 DATAO SD1 DATA1 501 DATA2 501 DATA3 GND 501 501 NVCC3 NVCC3 GND GND GND NVCC3 0 516 PC_WAIT_B PC_READY PC_VS1 GND USBOTG_STP USBOTG_DIR USBOTG_NXT USBOTG_CLK GND USBOTG_DATAO USBOTG_DATA1 USBOTG_DATA2 USBOTG_DATA3 USBOTG_DATA4 USBOTG DATA5 USBOTG_DATA6 USBOTG_DATA7 GND GND NVCC5 CSP12 MOSI CSP12 MISO CSP12 551
143. or pese ERR 4 36 4 2 9 ATA Drive Controller Rd RE es 4 37 4 2 10 RS 232 Connectors ee a a a a eee a e e s 4 38 4 2 10 1 DCE Connectors eol a CRBS TRA Wiel e RA Mee 4 38 4 2 10 2 OD COPS 53 soutien e OU Starts 4 40 4 2 11 12 CODDe tor owen does aca Da Bak SO MAL Cote AE e 4 40 4 2 12 CSPEGonnectot PRO E MER ah 4 41 4 2 13 there Connector 4 5 eed Moos aros dM doas Ms E x eU adiecta 4 42 4 2 14 USB OTG Conn ctot onte EPOR 4 42 4 2 15 USB Host 4 43 4 2 16 CE Bus Connectors oo conet lado tetuer Eia b vb es C DON TE is 4 43 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor iii Table of Contents 4 2 17 CCOHBTIBCIDES Sy oak wed bad RACE Vtde S E 4 44 4 2 18 PCMCIA Connector BO RERO va o a 4 46 4 2 19 SIMM Socket 4 47 4 2 20 Baseband Board Connector sd Goo Soir as Oba P d 4 48 4 2 21 Debugging and Programming Connectors 4 50 4 2 21 1 Software Analysis
144. ot required for normal operation 182 Remove jumper to measure voltage drop across two 20 mOhm resistors jumper is not required for normal operation 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation 182 Jumper ARM JTAG interface enabled No jumper ARM JTAG interface disabled other JTAG can be used 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation 1 2 Use on board voltage regulators use for stand alone mode 2 3 Use MC13783 power 1 2 Select 2 7 VDC Source for NVCC6 amp 9 remove when APMS is used 2 3 Select 1 8 VDC Source for NVCC6 amp 9 remove when APMS is used 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation 1 2 Select 2 7 VDC Source for NVCCA remove when APMS is used 2 3 Select 1 8 VDC Source for NVCC4 remove when APMS is used 1 2 Use on board voltage regulators use for stand alone mode 2 3 Use MC13783 power 182 Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation i MX31ADS User s Manual REV 1 Preliminary JP2 Reset Source Select JP4 NVCC SEL8 JP5 NVCC SEL1 JP6 LA DATA enable JP7 NVCC5 Shunt JP8 QARM Shunt JP9 NVCC8 Shunt JP10 SJC_MOD JTAG Mode Select
145. pad functions must be read through the CPLD The default keypad can be replaced by a custom design Table 3 16 shows the key switch matrix to the keypad signals by function name as labeled on the PCB and the switch reference designators Table 3 16 Keypad Layout and Connections KCOL7 KCOL6 KCOLS KCOL3 KCOL2 KCOL1 KCOLO BACK SP L ENTER ON OFF SPACE SW52 SW53 SW54 SW55 SW56 SW57 SW58 SW59 U K J M N H B KROW6 swaa 5 45 SW46 SW47 SW48 swag SW50 SW51 ximus G V X Z CAPS SYMB TAB SW36 SW37 SW38 SW39 SW40 SW41 SW42 SW43 Y T R F E D S A KROW4 SW29 SW30 SW31 SW32 SW33 SW34 SW35 W Q REC 0 8 n 9 SW 1 SW22 sw23 SW24 SW25 SW26 SW27 6 7 8 VOLDWN 4 1 2 3 SW12 SW13 SW14 SW15 SW16 SW17 SW18 SWSW19 me APP4 APP3 APP2 VOLUP APPI HOME SEND KEY1 sw4 SW5 swe SW7 swe SW9 SW10 SW11 BACK END KEY 2 UP RIGHT DOWN LEFT SEL KHOWO SW1 SW2 SW3 3 15 Audio Indicator The ADS includes an audio indicator or buzzer BZ1 When SW2 2 is ON the PWMO pin of the ADS controls this function This buzzer operates from 1 KHz to 10 KHz The maximum sound level is reached when the frequency is 3 KHz and the duty cycle is 50 3 16 LED Indicators Table 3 17 shows the ADS LED indicators and their associated functions Table 3 17 Function of LED Indicators Reference Color Name ADS BOARD Function D1 Gr
146. r Type Description Figure J23 16 pin 3 row Expansion 1 vertical Figure 3 1 left J24 64 pin Baseband Figure 3 1 bottom J25 Mini jack Voice transmission output Figure 3 2 bottom J26 Mini jack External analog output Figure 3 2 bottom J27 Mini jack Stereo headphone output Figure 3 2 bottom J28 Mini jack Voice output Figure 3 2 bottom J29 Mini jack External analog input Figure 3 2 bottom JP13 3 pin jumper 12 source selectable Figure 3 1 left P1 215 pin Base CPU 1 Figure 3 2 top P2 215 pin Base CPU 2 Figure 3 1 top P3 Memory card SD MMC 1 Figure 3 1 top P4 Memory card SD MMC 2 Figure 3 1 top P5 215 pin Base MC13783 1 Figure 3 2 bottom P6 215pin 137832 X Figure 3 2 bottom P7A DB 9 UART C MCU RS 232 DCE Figure 3 1 left P7B DB 9 UART A ADS RS 232 DCE Figure 3 1 left P8 GSM SIM SIMM Figure 3 1 left P9 40 pin Software analysis Figure 3 1 left P10 40 pin Software analysis Figure 3 1 left P11A DB 9 UART A MCU RS 232 DTE Figure 3 2 left P11B DB 9 UART B MCU RS 232 DTE Figure 3 2 left T1 RJ45 Ethernet Figure 3 1 left TB1 Screw terminal Stereo speaker output Figure 3 1 bottom U30 PCMCIA PCMCIA Figure 3 1 bottom M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor ADS Connectors and Signals P7B P7A 7 ume J10 J13 J14 P9 J17 gt J19 P10 JP13 J23 J24 TB1 U30 J18 Figure 4 1 Base Board C
147. r signal ATA DIOR 34 DATA I O READ ATA controller signal ATA_DIOW 32 DATA I O WRITE ATA controller signal ATA_DMAC 28 DIRECT MEMORY ACCESS CONTROL ATA controller signal ATA_RESET_B 30 RESET ATA controller signal CAPTURE 13 Timer input capture CE_CONTROL 188 CE bus signal Signal muxing of the CE bus CLK_26M 91 26 MHz clock signal COMPARE 15 LCD BIAS VOLTAGE CSI_D4 161 CMOS SENSOR INTERFACE DATA 4 Image Sensor input data CSI_D5 159 CMOS SENSOR INTERFACE DATA 5 Image Sensor input data CSI D6 157 CMOS SENSOR INTERFACE DATA 6 Image Sensor input data CSI D7 155 CMOS SENSOR INTERFACE DATA 7 Image Sensor input data CSI D8 149 CMOS SENSOR INTERFACE DATA 8 Image Sensor input data CSI D9 147 CMOS SENSOR INTERFACE DATA 9 Image Sensor input data CSI D10 145 CMOS SENSOR INTERFACE DATA 10 Image Sensor input data CSI D11 143 CMOS SENSOR INTERFACE DATA 11 Image Sensor input data CSI D12 141 CMOS SENSOR INTERFACE DATA 12 Image Sensor input data CSI 139 CMOS SENSOR INTERFACE DATA 13 Image Sensor input data CSI D14 137 CMOS SENSOR INTERFACE DATA 14 Image Sensor input data CSI D15 135 CMOS SENSOR INTERFACE DATA 15 Image Sensor input data CSI HSYNCH 142 CMOS SENSOR INTERFACE HORIZONTAL SYNC Control input CSI MCLK 158 CMOS SENSOR INTERFACE MASTER CLOCK Clock output to sensor card CSI PIXCLK 150 CMOS SENSOR INTERFACE PIXAL CLOCK Data latch strobe CSI VSYNCH 146 CMOS SENSOR INTERFACE VERTICAL
148. required for normal operation JP28 1 2 Select 2 7 VDC Source for NVCC5 remove when APMS is used NVCC SEL 23 Select1 8 VDC Source for NVCC5 remove when APMS is used JP29 182 Remove jumper to measure voltage drop across 1 Ohm resistor NVCC2 Shunt jumper is not required for normal operation JP30 FVCC Shunt JP31 SVCC Connect Remove jumper to measure voltage drop across 1 Ohm resistor jumper is not required for normal operation Jumper SVCC connected to UVCC and MVCC normal connection No jumper SVCC floating disables ADS JP32 Use on board voltage regulators use for stand alone mode XVCC Power Select Use MC13783 power 1 2 2 3 QPER Shunt jumper is not required for normal operation IOQVDD Shunt jumper is not required for normal operation 2 3 JP35 Use on board voltage regulators use for stand alone mode FVCC Power Select 2 8 JP12 JP17 and JP 20 select either the on board regulators or APMS and all must be set the same JP32 and JP35 also select either the on board regulators or APMS and both must be set the same but i MX31ADS User s Manual REV 1 Preliminary 2 10 Freescale Semiconductor Configuring and Connecting the ADS JP32 and JP35 setting does not have to be the same as JP12 JP17 and JP20 setting JP31 must be in place for the ADS to operate The JP38 shunt must connect pins 1 and 2 in stand alone operation but either setting can be used in APMS opera
149. rs J1 andJ2 Signal Description Pin Signal Description 1 5V 5 VDC BUS VOLTAGE 2 D USB DATA MINUS 3 D USB DATA PLUS 4 ID BUS ID 5 GND GROUND M9328MX31ADS User s Manual Rev 1 Preliminary 4 42 Freescale Semiconductor 4 2 15 USB Host Connectors ADS Connectors and Signals J4 and J5 are USB host connectors J4 is a high speed connector while J5 is a full speed connector Figure 4 22 shows pin assignments and Table 4 27 describes signals Figure 4 22 USB Host Connectors J4 and J5 Pin Assignment Table 4 27 USB Host Connectors J4 and J5 Signal Description Pin Signal Description 1 VBUS VBUS 2 D USB DATA MINUS 3 D USB DATA PLUS 4 GND GROUND 4 2 16 CE Bus Connector Connector J19 is the CE bus header Figure 4 23 shows pin assignments and Table 4 28 describes signals UART1_TXD UART1_RTS DCE_DCE2 DCD_DCE1 CE_INT2 CE_CONTROL GND 13 11 919 UART1_RXD UART1_CTS DTR_DCE1 RI_DCE1 CE_INT1 CVDD_2 775V CVDD_2 775V Figure 4 23 CE Bus Connector J19 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 43 ADS Connectors and Signals Table 4 28 CE Bus Connector J19 Signal Description Pin Signal Description 1 GND SIGNAL GROUND 2 CVDD 2 775 2 775 VDC POWER 3 CE CONTROL CE BUS CONTROL 4 CVDD 2 775
150. rs drive from ADS to MC13783 ON ON DO NOT USE ON OFF GPO2_BUFF controls TX2 FS2 and BCL2 buffer direction OFF ON FS2 and BCL2 buffers drive from MC13783 to ADS OFF OFF FS2 and BCL2 buffers drive from ADS to MC13783 ON ON DO NOT USE ON X TX2 FS2 and BCL2 buffers enabled OFF X TX2 FS2 and BCL2 buffers disabled X ON TX1 FS1 and BCL1 buffers enabled X OFF TX1 FS1 and BCL1 buffers disabled 2 4 1 6 S8 CLIA and CLIB Source Select Switch The six SPST slide switches in S8 control the source of the CLIA and CLIB audio bus clock inputs of the MC13738 Table 2 11 shows the switch functions CAUTION Be careful not to enable more than one source for either CLIA or CLIB Table 2 11 MC13783 Board SW8 CLIA and CLIB Source Select S8 1 S8 2 S8 3 S8 4 S8 5 S8 6 Function ON X X X X X CLIA from J6 goes to CLIA of MC13783 X ON X X X X CLIA from J6 goes to CLIB of MC13783 X X ON X X X CLIB from J6 goes to CLIA of MC13783 X X X ON X X CLIB from J6 goes to CLIB of MC13783 X X X X ON X CN10 goes to CLIA X X X X X ON CN10 goes to CLIB i MX31ADS User s Manual REV 1 Preliminary 2 14 Freescale Semiconductor Configuring and Connecting the ADS 2 4 1 7 S9 MC13783 Power up Mode Select Switch The six SPST slide switches in S9 control the logic levels of the MC13783 PUMS 3 1 inputs during po
151. s x s iso NS EE esum 4 76 4 4 2 2 Audio Terminals eec do pese ua uu SEEN E e uid aes 4 76 4 4 3 USB OCT Gonfectot A Seu RES IUS neue MG EVO Tau teu 4 T 4 4 4 Touchscreen Connector ooh hoe NICA NUR Oe Ma TAN 4 T 4 4 5 Subminiature Clock Connectors y oeste rede RR LEN tua e 4 78 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor List of Figures Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Freescale Semiconductor i MX31ADS Application Development 1 1 Base Board Configuration 2 1 Base Board Jumpers Left 2 5 Base Board Jumpers Right 5 2 6 CPU B rd SWHCNCS AG QUI 2 7 CPU Bogrd Connectors CA 2 11 Board Switches i oos tac e
152. ser Off Indication Confirm user off mode after a power fail 1 user off confirmation VIB EN 0 Vibrator regulator disabled Bit 3 Vibrator Enable Enable the vibrator regulator on the MC13783 board 1 Vibrator regulator enabled PCMCIA_EN 0 buffer enabled Bit 4 PCMCIA Enable Enable the PCMCIA buffer 1 PCMCIA buffer disabled Reserved For future use Always reads 0 Bits 5 15 y 3 3 6 8 Interrupt Status Clear Register ISCR The ISCR reflects the status of each ADS interrupt source The register may be read at any time There are two types of interrupt requests level triggered and edge triggered Edge triggered interrupt requests are generated when the source signal changes active state These interrupts are enabled by setting the associated control bit in the ISCR Clearing a control bit leaves the status bit unaffected Level triggered interrupt requests are generated when a specified active level high or low is detected An interrupt service routine must restore the interrupt signal to the inactive state at the source Writing to level sensitive interrupt status bits has no effect It is assumed that the reset state of all level sensitive interrupts is inactive i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 3 13 ADS Operation B
153. st Connector Signal 4 70 ISP Connector J7 Signal Description 4 7 NAND Flash Connector J9 Signal 4 72 Memory Stick Connector J5 Signal 4 73 Memory Stick Connector J6 Signal 4 73 MC13783 Board Connectors issue eos wx CER PUE DOR IR RS 4 74 Audio Jack Signal Descriptions 4 76 USB Connector CN3 Signal Description 4 77 Touchscreen Connector CN8 Signal 4 77 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor About This Book This manual explains how to connect and operate the 1 MX31ADS Application Development System Audience The audience for this manual is handheld communication device designers It is assumed that users are engineers or technicians with experience using development systems Organization The manual consists of three chapters e Chapter 1 introduces the user to the features and capabilities of the ADS e Chapter 2 provides configuration and set up information e Chapter 3 provide operational information e Chapter 4 provides connector locations functions pin assignments and signal descriptions Revision History T
154. t be used i MX31ADS User s Manual REV 1 Preliminary 2 12 Freescale Semiconductor Configuring and Connecting the ADS Table 2 7 MC13783 Board 54 USB Mode Select 54 1 54 2 54 3 54 4 USB Mode Selected OFF OFF ON OFF Differential unidirectional 6 wire ON OFF OFF ON Differential bidirectional 4 wire OFF ON OFF ON 2 ended unidirectional 6 OFF OFF OFF ON Single ended bidirectional 4 wire S4 5 ON enable MC13783 USB OTG transceiver OFF disables it S4 6 ON pulls up the WDI input to MC13783 disabling that function MC13783 will not shut down due to a WDI time out OFF the WDI input of MC13783 must be pulsed periodically Note SW2 1 on the Base board also affects the WDI signal 2 4 1 3 S5 Backup Source Select Switch The four SPST slide switches in 55 control MC13783 back up power Table 2 8 shows valid switch combinations other combinations must not be used The Super Cap back up source is on the board Set 55 and 55 3 to ON to charge the Super Cap R150 controls peak charge and R108 controls charge rate Set S5 3 to OFF when charging is complete Set 55 4 to ON to allow the Super Cap to discharge The rate of discharge is controlled by R26 Connection to an external lithium cell is optional If a lithium cell is used it must be connected to CN9 and S5 2 must be set to ON Otherwise S5 2 must be OFF Table 2 8 MC13783 Board S5 Backup Source Select 55 1 55 2 5
155. t signal 9 RI RING INDICATOR RS 232 input signal 4 2 11 12C Connector JP13 is the I2C interface connector for the ADS The jumper block is used to connect directly to MCU I2C transceiver 1 Table 4 23 describes JP13 signals Table 4 23 2 Connector JP13 Signal Description Pin Signal Description 1 12C1 CLK 2 INTERFACE 1 CLOCK 2 2 DAT 2 INTERFACE 1 DATA 3 GND SIGNAL GROUND M9328MX31ADS User s Manual Rev 1 Preliminary 4 40 Freescale Semiconductor ADS Connectors and Signals 4 2 12 CSPI Connector J15 is the ADS CSPI connector Figure 4 19 shows pin assignments and Table 4 24 describes J15 signals J15 DVDD 1 8V 1 2 3V3 CSPI3_SCLK 4 CSPI3 MOSI R CSPI1 SSO 5 6 552 SPI3_RESET 7 8 CSPI3_MISO GND 9 10 CVDD_2 775V LED_ADi 11 e 12 PM_VBLITE LED_AD2 13 14 LED_KP GPIO1 15 16 GPIO2 R_SRXD6 17 18 SCK6 R_STXD6 19 e e 20 CSPI3 SPI RDY Figure 4 19 CSPI Connector J15 Pin Assignment Table 4 24 CSPI Connector J15 Signal Description Pin Signal Description 1 DVDD 1 8V 1 8 VDC POWER 2 3V3 3 VDC POWER 3 CSPI3_SCLK CSPI3 SERIAL CLOCK 4 CSPI3_MOSI CSPI3 MASTER OUT SLAVE IN 5 R_CSPI1_SSO CSPI1 SLAVE SELECT 0 6 CSPI1 552 1 SLAVE SELECT 2 7 SPI3_RESET SPI3 RESET FROM CPLD 8 CSPI3_MISO CSPI3 MASTE
156. t the smart parallel LCD 1 1 smart parallel LCD 1 reset signal asserted LCDRST1 0 smart parallel LCD 2 reset signal negated Bit 10 LCD parallel COD 2 1 smart parallel LCD 2 reset signal asserted LCDRST2 LCD 2 Reset Reset the smart serial LCD 0 smart serial LCD reset signal negated Bit 11 1 smart serial LCD reset signal asserted LCDIO_EN LCD GPIO Enable Enable GPIO1 and GPIO2 0 connection with GPIO1 GPIO2 is enabled Bit 12 interface with the LCD connectors 1 connection with GPIO1 and GPIO2 is disabled CT_CS Code Test Chip Select Select the Code Test 0 Code Test selected Bit 13 emulator 1 Code Test not Selected VPPEN 0 PCMCIA VPP power is off Bit 14 VPP Enable Enable VPP power for the PCMCIA 1 PCMCIA VPP power is VCC power 3 3V VCCEN 0 PCMCIA VCC power is off Bit 15 VCC Enable Enable VCC power for the PCMCIA 1 PCMCIA VCC power is 3 3V i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor ADS Operation 3 3 6 6 Board Control Register 3 BCTRL3 BCTRL3 contains several bits that control various board functions This register is implemented as a set register and a clear register To set a bit write a 1 to the bit at the set address To clear a bit write a 1 to the bit at the clear address BIT 15 14 13 12 11 10 9 8 7
157. tion Pin Signal Description 1 TCK JTAG CLOCK 2 GND SIGNAL GROUND 3 TMS JTAG MODE 4 GND SIGNAL GROUND 5 TDI JTAG DATA IN 6 3V3 3 VDC POWER 7 TDO JTAG DATA OUT 8 GND SIGNAL GROUND 9 NC NO CONNECTION 10 NC NO CONNECTION 4 3 6 NAND Flash Connector J9 on the CPU board allows the ADS to interface with a NAND Flash module Figure 4 39 shows pin assignments and Table 4 47 describes connector signals BNFCE_B 1 BNFCLE 3 BNFALE 5 BNFWE_B 7 BNFREB 9 BNFWP B 11 BNFRB 13 BDO 15 BD1 17 BD2 19 BD3 21 BD4 BD5 BD6 BD7 c 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 3V3 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 NF DET B GND Figure 4 39 NAND Flash Connector J9 Pin Assignment M9328MX31ADS User s Manual Rev 1 Preliminary Freescale Semiconductor 4 71 ADS Connectors and Signals Table 4 47 NAND Flash Connector J9 Signal Description Pin s Signal Description 1 FLASH CHIP ENABLE 2 NC NOT CONNECTED 3 BNFCLE FLASH COMMAND LATCH ENABLE 4 NC NOT CONNECTED 5 BNFALE FLASH ADDRESS LATCH ENABLE 6 NC NOT CONNECTED 7 BNFWE FLASH WRITE ENABLE 8 NC NOT CONNECTED 9 BNFRE_B NAND FLASH READ ENABLE 10 3V3 3 VDC POWER 11 BNFWP_B FLASH WRITE PROTECT 12 BD15 BIDIRECTIONAL DATA 1
158. tion JP12 JP2 JP17 SHUNT JUMPERS JP10 JP22 JP6 JP1 JP16 JP5 JP23 JP28 7 Y E JP3 JP13 JP20 SHUNT JUMPERS JP38 JP36 JP37 JP35 JP26 JP32 Figure 2 5 CPU Board Connectors 2 4MC13783 Board Configuration 2 4 1MC13783 Board Switches The MC13783 board has three user definable push button switches S1 S2 and S3 and six DIP switches SW4 controls USB port functions SW5 switch settings determine the source of back up power SW6 settings control the on board USB port SW7 settings control the on board buffers SW8 settings control board clocks SW9 settings control power up voltage levels Figure 2 6 shows the locations of the MC13783 board switches i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor 2 11 Configuring and Connecting the ADS S7 S8 S9 S4 S5 4 56 53 52 51 Figure 2 6 MC13783 Board Switches 2 4 1 1 51 S2 S3 User Defined Push Buttons The three push button switches are connected to the ON1B ON2B and ON3B inputs of the MC13783 and the signals are also routed to the Base board connector The lines are pulled up on the board Pushing a switch grounds the line 2 4 1 2 S4 USB Function Select USB Enable Enable Switches The first four SPST slide switches in S4 control USB port function Table 2 7 shows valid switch combinations other combinations must no
159. tion Settings LOW BAT Low Battery Low Battery Indicator signal from MC13783 Board Battery Bit 4 1 Normal operation PB_IRQ E 0 Push button is pressed Bit 5 Push Button IRQ Push button switch circuit 1 Push button is not pressed OTG_FS_OVR USB OTG Full Speed Over Current USB OTG Full Speed Over Current 0 Over Current indication Bit 6 indication 1 No Over Current indication FSH_OVR USB Full Speed Host Over Current The USB Full Speed Host interface 0 Over Current indication Bit 7 Over current indication 1 No Over Current indication 3 3 6 10 Interrupt Mask Register IMR The IMR enables and disables the corresponding interrupt source Setting a control bit enables the associated interrupt source clearing a bit disables masks the associated interrupt source When an interrupt is masked the associated status register bit still indicates whether an interrupt is pending However a masked interrupt source cannot cause the GPIO pin it is associated with to generate an interrupt request signal Modifying the IMR to enable an interrupt that is pending causes an interrupt request to be generated immediately This register is implemented as a set register and a clear register To set a bit write a 1 to the bit at the set address To clear a bit write a 1 to the bit at the clear address BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTG OTG _ XUART_ X
160. tionof LED Indicators sos ox exse a ra eder datu eet 3 24 Base Board TRE ERE FERIIS 4 Base Board to CPU Board Connector Signal 4 7 Base Board to CPU Board Connector P2 Signal 4 11 Base Board to MC13783 Board Connector P5 Signal Description 4 17 Base Board to MC13783 Board Connector P6 Signal Description 4 17 Image Sensor Connectors J10 and J13 Signal 4 21 Extension Connector J17 Signal Description 4 22 Extension Connector J22 Signal Description 4 24 Extension Connector J23 Signal Description 4 25 External Keypad Connector P5 Signal Description 4 27 i MX31ADS User s Manual REV 1 Preliminary Freescale Semiconductor vii List of Tables Table 4 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 4 20 Table 4 21 Table 4 22 Table 4 23 Table 4 24 Table 4 25 Table 4 26 Table 4 27 Table 4 28 Table 4 29 Table 4 30 Table 4 31 Table 4 32 Table 4 33 Table 4 34 Table 4 35 Table 4 36 Table 4 37 Table 4 38 Table 4 39 Table 4 40 Table 4 41 Table 4 42 Table 4 43 Table 4 44 Table 4 45 Table 4 46 Table 4 47 Table 4 48 Table 4 49 Table 4 50
161. to the buzzer circuit Set SW2 3 SW2 5 or SW2 7 to ON to shut down the associated RS 232 transceiver This minimizes current consumption when the transceivers are not used Set SW2 4 SW2 6 or SW2 8 to ON to enable the RS 232 transceivers for UARTC and DUART channels A and B to operate at rates up to 1 MBaud Lower rates can reduce system power consumption and EMI Table 2 2 Base Board SW2 Switch function N Connects the Watch Dog Reset to MC13783 SW2 1 WDI Enable Watch Dog Reset is not connected to MC13783 SW2 2 Buzzer Enable SW2 3 UARTC Shut Down SW2 4 UARTC MBAUD ON PWM output isnot connected to he buzzer ON FF__ UARTCwansceivrisenabled o ON PF Baud Rate imed to ops ON FF ExemaUARTAVenseerisenabed ON UARTA Baud Rate med Mbps ON FF External UARTB tansceherisenabled SW2 6 Ext UA MBAUD SW2 7 Ext UB Shut Down ON External UARTB Baud Rate limited to 250kbps SW2 8 Ext UB MBAUD OFF External UARTB Baud Rate limited to 1Mbps 2 i MX31ADS User s Manual REV 1 Preliminary 2 2 Freescale Semiconductor Configuring and Connecting the ADS 2 2 1 3 SW3 User Defined Switches Table 2 3 shows SW3 switch functions The settings of the eight SPST slide switches in SW3 may be read by software to implement user defined functions The switch settings are read on data bits D 7 0 Table 2 3 SW3 Switch Settings DO Reads
162. uctor 4 77 EE a ADS Connectors and Signals 4 4 5 Subminiature Clock Connectors Subminiature connectors CN4 and CN10 provide external clock signal connections CN4 provides an external input for the 32 KHz clock signal CN10 provides an input for the MC13783 audio bus clock signals CLIA and CLIB M9328MX31ADS User s Manual Rev 1 Preliminary 4 78 Freescale Semiconductor
163. ure 4 21 Figure 4 22 Figure 4 23 Figure 4 24 Figure 4 25 Figure 4 26 Figure 4 27 Figure 4 28 Figure 4 29 Figure 4 30 Figure 4 31 Figure 4 32 Figure 4 33 Figure 4 34 Figure 4 35 Figure 4 36 Figure 4 37 Figure 4 38 Figure 4 39 Figure 4 40 Figure 4 41 Figure 4 42 Figure 4 43 vi Jack Diagrama ieu VINE Ra E dew vore ves 4 35 TV Encoder Connector Pin 4 36 ATA Connector J3 Pin Assignment ead otis Pay eda va ey qu 4 37 RS 232 DCE Connectors and P7B Pin Assignment 4 39 RS 232 DCE Connector J7 Pin 4 39 RS 232 DTE Connectors P11A and P11B Pin 4 40 CSPI Connector J15 Pin 1 4 41 Ethernet Connector T1 Pin dd Sedes gan awe Peat ees 4 42 USB Connectors and J2 Pin 4 42 USB Host Connectors and J5 Pin 4 43 CE Bus Connector J19 Pin 4 43 SD MMC Connector Pin Assignments 4 44 Baseband Board Connector J24 Pin 4 48 Software Analysis Connector P9 Pin Assignment 4 5
164. ware implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where pers
165. wer up which determine operating power levels and start sequencing The switches operate in pairs Setting the low number switch to ON grounds the input setting the high number switch to ON pulls the input up When both switches are set to OFF the input floats CAUTION Setting both switches in a pair to ON also grounds the associated input but uses significant VATLAS current Do not use this setting Table 2 12 shows S9 switch functions For information about the effect of the PUMS inputs and operating modes see the MC13783 manual on the ADS CD Table 2 12 MC13783 Board SW9 MC13783 Power up Mode Select 59 1 59 2 59 3 59 4 S9 5 59 6 Function OFF OFF PUMS floats selects power up voltage levels ON OFF PUMS 1 grounded selects power up voltage levels OFF ON 1 pulled up selects power up voltage levels ON ON DO NOT USE OFF OFF PUMS2 floats selects power up voltage levels ON OFF PUMS2 grounded selects power up voltage levels OFF ON PUMS2 pulled up selects power up voltage levels ON ON DO NOT USE OFF OFF PUMSS floats selects power up sequence ON OFF PUMSS grounded selects power up sequence OFF ON PUMSS pulled up selects power up sequence ON ON DO NOT USE 2 4 2MC13783 Board Jumper Headers The MC 13783 board has seven jumper headers JMP1 JMP3 JMP9 JMP10 not implem

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