curryman DAC - Audiophonics
Contents
1. 5 5V Ground Ground Ground LRCK Please keep 12S signal lines as short as possible and provide a separate ground wire for each 12S signal line e g ribbon cable Analog Output Connectivity The unbalanced left and right analog outputs are provided via two screw terminals The output levels are 2Vrms at digital full scale OdB FS and the output impedance is lt 70 Ohms The following diagram shows the correct wiring of the analog outputs QND y oaa AO J Gerhar Right Signal Out Left Ground A 15V in 4 ghee y JSE Sp Left Signal Out NENE CTOUNG DIY use only c3 103 roe Curryman 2013 Features and Specifications are subject to change without prior notice 3 Application examples Combination with miniSTREAMER miniSTREAMER must be set to I2S Master The 12S input of the DAC can be connected to the buffered I2S output at the I2S Expansion connector please refer to miniSTREAMER datasheet using the following pin assignment curryman DAC miniSTREAMER SDI Pin Pin 6 SDOUT BCK Pin Pin 1 SCLKOUT LRCK Pin Pin 2 LRCLKOUT GND Pins Pin 7 GND se LS Example 1 Connection between miniSTREAMER and curryman DAC using ribbon cable Combination with miniSHARC The 12S input of the DAC can be connected to the I2S outputs of the miniSHARC via the 12S In amp Out Expansion port J2 please refer to miniSHARC datasheet user manual using the following pin assignment2. curryman DAC User manual V1 1 cr lt 4 Filter Buffer designed J Gerhar LE E i olf _ J52 wr ut ji 0 CELT ingol Ci a ae w I t cu wpe N 71 y i 7 i DAA j as ie 3 ot es s Tr C23 u L200 Pe Jay a T s i csli ES9023 12 DA VSO sprac by curryman a W SRA ics A ye m re s OROL KEI se y i a ORPO Ji MOLI UK SUI mi O The curryman DAC is a stereo digital to analog converter with 12S input featuring the ES9023 Sabre Premier Stereo DAC and an analog LCR output filter plus JFET buffer JG Filter Buffer developed by Joachim Gerhard for improved high frequency noise suppression and output drive capability Features e 12S Input e Stereo 2Vrms output unbalanced e Improved LCR output filter for reduced HF noise e JFET buffer line driver with low output impedance lt 70 Ohm e On board low jitter 5OMHz crystal oscillator XO e On board low noise LDO regulators for DAC 3 6V and XO 3 3V e Supported 12S input sample rates kHz 32 44 1 48 88 2 96 176 4 196 e Asynchronous mode operation using local XO as MCLK e Power Supply o 4 5V to 12V DC regulated or unregulated for DAC and XO o 10V to 18V DC regulated low noise for output buffer Curryman 2013 Features and Specifications are subject to change without prior notice 1 DC Connectivity The DAC board requires two power supplies e a regulate
3. curryman DAC miniSHARC SDI Pin Pin 16 for output channels 1 amp 2 12S DATA _OUT1 amp 2 Pin 17 for output channels 3 amp 4 12S DATA _OUT3 amp 4 Pin 18 for output channels 5 amp 6 12S DATA _OUT5 amp 6 Pin 19 for output channels 7 amp 8 I2S_DATA_OUT7 amp 8 BCK Pin Pin 15 I2S_IN_BCLK LRCK Pin Pin 14 12S_IN_LRCK GND Pins Pins 5 8 The combination of the miniSHARC with 3 curryman DACs 6ch Stereo 3way setup has been successfully tested without using an additional active buffer circuit 12S connections should be kept as short as possible Curryman 2013 Features and Specifications are subject to change without prior notice 4 Example 2 Connection between miniSHARC and 3 curryman DAC using ribbon cable Curryman 2013 Features and Specifications are subject to change without prior notice 5
4. d or unregulated DC power supply for the DAC and XO in the range from 4 5V to 12V max 65mA and e aregulated bipolar DC power supply between 10V and 18V max 35mA per rail Make sure to carefully follow the below wiring diagram to prevent any short circuits or damage to the board Ground 10V to 18V DC 10V to 18V DC vii R45 Filter Buffer Cs k red b 3 at 15V in T ftoaty cicah Ra R R42 L41 L51 R52 R i FO C Eek Cums BE C7 a use ore We Jal ls ae oe 7 EEn L31 ES9023 12S DAC OM i ot ia by curryman 2013 ZJE ice Oy me OOOO c30 fejejelelelelele ii Ea MCLK BCK LRCK SDI U Pi Ground 4 5V to 12V DC 12S Connectivity The ES9023 is configured to 12S slave mode and will work with I2S signals according to the following timing diagram standard 12S timing prere J LRCK Left Channel Right Channel 11 oon UU Un UU UU UU It will lock on to any of the following sample rates kHz 32 44 1 48 88 2 96 176 4 and 196 Curryman 2013 Features and Specifications are subject to change without prior notice 2 The DAC is configured to run in asynchronous mode and does not require external MCLK Thus only BCK bit clock LRCK left right clock or word clock and 12S data lines SDI have to be connected as per the following diagram a J He E D E oa C2 ve T apo a m ai ep a 2S DAC oy F 089 by curryman 2013 ui 0000 8 END
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