tut_quartus_intro_verilog_de1
Contents
1. Tasm w ide NMM 4 Figure 2 The main Quartus II display Quartus Il Ctrid M Ctrid o Ciri F4 New Project Wizard Open Project Chrl J Convert MAX PLUS II Project Save Project Close Project Save Ckri 5 Save As Save Current Report Section As File Properties Create Update Export Convert Programming Files KI Page Setup Print Preview E Print Ctrl F N ecent Files Recent Projects Exit Alt F4 Figure 3 An example of the File menu For some commands it is necessary to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 1 1 Quartus II Online Help Quartus II software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the Help menu To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu For in2. Default Parameters B Synthesis Netlist Optimizations Fitter Settings 00 Physical Synthesis Optimization Timing Analysis Settings H TimeQuest Timing Analyzer Classic Timing Analyzer Setting Classic Timing Analyzer Hc Assembler Descriptions i Design Assistant Specifies the type of simulation to perform for the current Simulation focus SignalT ap II Logic Analyzer Logic Analyzer Interface Fi Simulator Settings PowerPlay Power Analyzer Setting E Cancel Figure 35 Specifying the simulation mode Simulation Waveforms Simulation mode Functional 1 Painter B4 33 ns Interval 54 33 ns Start 40 0 ns 30 0 ns 120 0 ns Figure 36 The result of functional simulation 6 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select Assignments gt Settings gt Simulator Settings to get to the window in Figure 35 choose Timing as the simulation mode and click OK Run the simulator which should produce the waveforms in Figure 37 Observe that there is a delay of about 9 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device 22 Simulation Waveforms Simula
3. MIL For Help press F1 Figure 38 The Programmer window 23 Observe that the configuration file light sof is listed in the window in Figure 38 If the file is not already listed then click Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Note also that the device selected is EP2C20F484C7 which 1s the FPGA device used on the DEI board Click on the Program Configure check box as shown in Figure 40 Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware Available hardware items Hadwse Sever Pot Add Hardware LIS B Blaster Local LEM Figure 39 The Hardware Setup window W Quartus Il D introtutorial light light light cdf File Edit Processing Tools Window cay Hardware Setup USB Blaster USB 0 Mode JTAG Progress Enable real time ISP to allow background programming for MAX II devices msa e Dese oem moe E ven Beh mes S ee light sof EP2C20F 484 O01B0367 FFFFFFFF n Auto Detect X Delete Gab Add File p Chanae File For Help press F1 Figure 40 The updated Programmer window Now press Start in the window in Figure 40
4. An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that programming failed then check to ensure that the board is properly powered on 7 2 Active Serial Mode Programming In this case the configuration data has to be loaded into the configuration device on the DEI board which is iden tified by the name EPCS4 To specify the required configuration device select Assignments gt Device which leads to the window in Figure 41 Click on the Device and Pin Options button to reach the window in Figure 42 Now click on the Configuration tab to obtain the window in Figure 43 In the Configuration device box which may be set to Auto choose EPCS4 and click OK Upon returning to the window in Figure 41 click OK Recompile the designed circuit 24 Settings light Category General Files Libraries Select the family and device you want to target for compilation Device Operating Settings and Conditions Device family Show in Available devices list Compilation Process Settings Be Cyctore e EDA Tool Settings Family Cyclone Il v Package Any Analysis amp Synthesis Settings Oe y Fitter Settings evices z Timing Analysis Settings Speed grade Any x Assembler Target device Show advanced devices Design Assistant Auto device selected by the Fitter Sina ap Il Logic Analyzer Specific de
5. ef light v Figure 15 Text Editor window 3 1 1 Using Verilog Templates The syntax of Verilog code is sometimes difficult for a designer to remember To help with this issue the Text Editor provides a collection of Verilog templates The templates provide examples of various types of Verilog statements such as a module declaration an always block and assignment statements It is worthwhile to browse through the templates by selecting Edit gt Insert Template gt Verilog HDL to become familiar with this resource 3 2 Adding Design Files to a Project As we indicated when discussing Figure 6 you can tell Quartus II software which design files it should use as part of the current project To see the list of files already included in the light project select Assignments gt Settings which leads to the window in Figure 16 As indicated on the left side of the figure click on the item Files An alternative way of making this selection is to choose Project gt Add Remove Files in Project If you used the Quartus II Text Editor to create the file and checked the box labeled Add file to current project as described in Section 3 1 then the ight v file is already a part of the project and will be listed in the window in Figure 16 Otherwise the file must be added to the project So if you did not use the Quartus II Text Editor then place a copy of the file ight v which you created using some other text editor into the directory introtu
6. a name which is usually the same as the top level design entity that will be included in the project Choose light as the name for both the project and the top level entity as shown in Figure 4 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 5 asking if it should create the desired directory Click Yes which leads to the window in Figure 6 Quartus Il AN Directory D fintrotutorial does not exist Do vou want Ea create iE Yes Ma Figure 5 Quartus II software can create a new directory for the project Mew Project Wizard Add Files page 2 of 5 Select the design files you want ta include in the project Click Add All to add all design files in the project directory to the project Mate you can always add design files to the project later File name LL HDL version Add Al gt Specify the path names of any non default libraries User Libraries Next gt Finish Cancel Figure 6 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files if any should be included in the project Assuming that we do not have any existing files click Next which leads to the window in Figure 7 New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family r Show in Available device list 1 F
7. into the FPGA device you can now test the implemented circuit Flip the RUN PROG switch to RUN position Try all four valuations of the input variables x and x by setting the corresponding states of the switches SW and SW Verify that the circuit implements the truth table in Figure 11 If you want to make changes in the designed circuit first close the Programmer window Then make the desired changes in the Verilog design file compile the circuit and program the board as explained above Copyright 2009 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writ
8. one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the Verilog code In this case a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending statement in the Verilog code in the Text Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an error open the file ight v Remove the semicolon in the assign statement illustrating a typographical error that is easily made Compile the erroneous design file by clicking on the amp icon A pop up box will ask if the changes made to the light v file should be saved click Yes After trying to compile the circuit Quartus II software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report summary given in Figure 19 now confirms the failed result Expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 20 Double click on the first error message Quartus II software responds by opening the light v
9. 0 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 11 This should 20 produce the image in Figure 34 Observe that the output f is displayed as having an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file I light vwf Master Time Bar 1 Painter 166 25 ns Interval 166 25 ns Start 60 0 ns 30 0 ns 100 0 ns 120 0 ns 140 0 ns 180 0 ns 180 0 ns AK peu an ann a CUR O0 00 A E E A A A a6 00 00 A A a6 000 nS Figure 34 Setting of test values 6 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 6 1 1 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window On the left side of this window click on Simulator Settings to display the window in Figure 35 choose Functional as the s
10. Info Running Quartus II Analysis Synthesis Info Command quartus map read settings files on write settings files off light c light Error 10170 Verilog HDL syntax error at light v 5 near text endmodule expecting or Info Found 0 design units including 0 entities in source file light v Error Quartus II Analysis Synthesis was unsuccessful 1 error 0 warnings Extra Info Info 4 A Warning Critical Warning Error 2 A Flag Mesme0s12 Blin SSCS te Figure 20 Error messages 14 e light v Emodule light xl xz tf input xi ee output f assign f xl amp xz i xl amp xz Figure 21 Identifying the location of the error 5 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DEI board has hardwired connections between the FPGA pins and the other components on the board We will use two toggle switches labeled SW and S W1 to provide the external inputs x and xg to our example circuit These switches are connected to the FPGA pins L22 and L21 respectively We will connect the output f to the green light emitting diode labeled LE DGo which is hardwired to the FPGA pin U22 Quartus II D introtutorial light light Assignment Editor File Edit View Tools Window xi Category Pin Q l amp Timing 3 Logic Options H tk XV pde eso I O Ban
11. O Bank 1 Dedicated Clock CLK3 LVDSCLK1n Input I O Bank 1 Row I O LVDS15p DPCLK1 DQS1L CQ1Ls Figure 24 The available pins Quartus II D introtutorial light light Assignment Editor Figure 25 The complete assignment The DEI board has fixed pin assignments Having finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment Editor A simple file format that can be used for this purpose is the comma separated value CSV format which is a common text file format that contains comma delimited values This file format is often used in conjunction with the Microsoft Excel spreadsheet program but the file can also be created by hand using any plain ASCII text editor The format for the file for our simple project is To Location xl PIN L22 x2 PIN L21 f PIN U22 By adding lines to the file any number of pin assignments can be created Such csv files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 25 Now select Fil
12. Quartus II Introduction Using Verilog Design This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typi cal CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus II software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the Verilog design entry method in which the user specifies the desired circuit in the Verilog hardware description language Two other versions of this tutorial are also available one uses the VHDL hardware description language and the other is based on defining the desired circuit in the form of a schematic diagram The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DEI Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DEI board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 9 0
13. amily Cyclone I Package Any x Devices All Y Pin count Any v Target device Speed grade Any C Auto device selected by the Fitter MV Show advanced devices Specific device selected in Available devices list HardCopy compatible only Available devices EP2C204F 48418 239616 EP2C20F256C6 239616 EP2C20F256C 239616 EP2C20F256C8 239515 EP2C20F 25618 239515 EP2C20F484C6 239616 EP2C20F484C7 y EP2C20F484C8 239616 COV INC AOAIO ACIC Finish Cancel Figure 7 Choose the device family and a specific device 4 We have to specify the type of device in which the designed circuit will be implemented Choose Cyclone M II as the target device family We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the latter approach From the list of available devices choose the device called EP2C20F484C7 which is the FPGA used on Altera s DEI board Press Next which opens the window in Figure 8 Mew Project Wizard EDA Tool Settings page 4 of 5 Specify the other EDA tools in addition ta the Quartus software used with the project Design Entro Synthesis Tool name WNMMMN Format T Aun this tool automatically to synthesize the current design Simulation Tool name None gt Format E Run gateevel simulation automatically after compilation Timing Analysis Tool name Non
14. ditor window as shown in Figure 33 If you did not select the nodes in the same order as displayed in Figure 33 it is possible to rearrange them To move a waveform up or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor I light vw Master Time Bar 15 95 ns 4 Pointer 10 06 ns Interval 5 89 ns Start ps End 200 0 ns O ps 40 0 ns 80 0 ns 120 0 ns 160 0 ns 200 0 na Value at i i i i 15 95 ns 15 85 ns AO eee Bette See a EEE EEC E SS EEE EELS CECE UC 06 00 EEE EEE SE EEE EET eee RUE a Figure 33 The nodes needed for simulation 4 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing View gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon Is in
15. e gt Export which leads to the window in Figure 26 Here the file light csv is available for export Click on Export If you now look in the directory introtutorial you will see that the file light csv has been created 16 Save int 9 introtutorial ja E EJ o M My Recent Documents Desktop My Documents Mo Computer e My Network File name ligh Places Save as type Comma Separated Value File csv Cancel Figure 26 Exporting the pin assignment You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dia logue in Figure 27 to select the file to import Type the name of the file including the csv extension and the full path to the directory that holds the file in the File Name box and press OK Of course you can also browse to find the desired file Import Assignments Specify the source and categories of assignments to import File name E iw Copy existing assignments into light qsf bak before importing moron Cancel Figure 27 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE1 board are given in the file called DEI pin assignments csv in the directory DE1_tutorials design_files which is included on the CD ROM that accompanies the DEI board and can also be found on Altera s DEI web pages This file uses the names found in the DEI User Manual If we wanted to
16. e gt Format E T Aun this tool automatically after compilation Back Finish Cancel Figure 8 Other EDA tools can be specified 5 The user can specify any third party tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools where the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 9 Press Finish which returns to the main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 10 New Project Wizard Summary page 5 of 5 When you click Finish the project will be created with the following settings Project directory d introtutorial Project name Top level design entity Number of files added Number of user libraries added Device assignments Family name Cyclone Il Device EP2C20F 484C7 EDA tools Design entry synthesis None Simulation None Timing analysis None Operating conditions Core voltage 1 29 Junction temperature range 0 85 C Cancel Figure 9 Summary of the project settings Quartus II d introtutorial light light File Edit View Project Assign
17. ed at the insertion point which is indicated by a thin vertical line The insertion point can be moved either by using the keyboard arrow keys or by using the mouse Two features of the Text Editor are especially convenient for typing Verilog code First the editor can display different types of Verilog statements in different colors which is the default choice Second the editor can automatically indent the text on a new line so that it matches the previous line Such options can be controlled by the settings in Tools gt Options gt Text Editor SOFC Builder System Design Files AHDL File Black Diagram 5 chematic File EDIF File State Machine File SystemVerleg HDL File Tel Script File Verilog HDL File VHDL File Memory Files Hexadecimal Intel Format File Memory Initialization File V erificatian Debugging Files In System Sources and Probes File Logic Analyzer Interface File SignalT ap Il Logic Analyzer File Vector Waveform File Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File bul Cancel Figure 13 Choose to prepare a Verilog file 10 Save In i3 introtutorial E lab Muy Recent Documents 3 Desktop hy Documents hy Computer mm My Network File name fight Places Save as type Verilog HDL File v vlg verilog Cancel i Add file to current project Figure 14 Name the file
18. en Programmer Info Running Quartus II Classic Timing Analyzer Info Command quartus tan read settings files off write settings files off light c light timing analysis only Info Parallel compilation is enabled and will use 2 of the 2 processors detected Info Longest tpd from source pin Xl to destination pin f is 9 593 ns Info Quartus II Classic Timing Analyzer was successful 0 errors 0 warnings Info Quartus II Full Compilation was successful 0 errors 3 warnings System 2 A Processing 53 A Extra Info Info 50 Warning 3 Critical Warning Error Suppressed 6 Flag wu A c aeshan E Message 0 of 111 E For Help press F1 Figure 18 Display after a successful compilation When the compilation is finished a compilation report is produced A window showing this report is opened automatically as seen in Figure 18 The window can be resized maximized or closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sections listed on the left side of its window Figure 18 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed to implement this tiny circuit on the selected FPGA chip 13 4 1 Errors Quartus II software displays messages produced during compilation in the Messages window If the Verilog design file is correct
19. file and highlighting the statement which is affected by the error as shown in Figure 21 Correct the error and recompile the design Compilation Report Flow Summary 3 Compilation Report Flow Summary amp b B Legal Notice gE Flow summary VR SE Flow Settings Flow Status Flow Failed Wed Apr 29 15 07 07 2009 25 Flow Non Default Quartus II Version 3 0 Build 132 02 25 2003 SJ Full Version El Flow Elapsed Tim Revision Name light GES Flow OS Summar Top level Entity Name light amp b B Flow Log Family Cyclone II Lo Analysis amp Synthe Device EP2C20F484C7 Timing Models Final Met timing requirements N Total logic elements N amp until Partition Merge Total combinational functions NZ until Partition Merge Dedicated logic registers N until Partition Merge Total registers N until Partition Merge Total pins NZ until Partition Merge Total virtual pins N until Partition Merge Total memory bits N until Partition Merge Embedded Multiplier S bit elements N amp until Partition Merge Total PLLs N until Partition Merge LER Figure 19 Compilation report for the failed design Compilation Report Analysis amp Synthesis Messages Beles e Compilation Report Analysis amp Synthesis Messages 65 Flow summary GSES Flow Settings gg Flow Non Default Global Settir B Flow Elapsed Time 4B Flow Log BD Analysis amp Synthesis GSES summary eL Settings amp i Messages BE oss REICERISCUNUM te A
20. ically if a data error is encountered If this option is turned off you must externally direct the device to restart the configuration process if an error occurs Reset Figure 42 The Options window 29 Device and Pin Options Voltage Pin Placement Error Detection CRC Capacitive Loading Board Trace Model 1 0 Timing General Configuration Programming Files Unused Pins DuakPurpose Pins Specify the device configuration scheme and the configuration device Note For HardCopy designs these settings apply to the FPGA prototype device Configuration scheme Active Serial can use Configuration Device v Configuration mode Configuration device iw Use configuration device r V Generate compressed bitstreams Description Specifies the configuration device that you want to use as the means of configuring the target device Reset Figure 43 Specifying the configuration device The rest of the procedure is similar to the one described above for the JTAG mode Select Tools gt Program mer to reach the window in Figure 38 In the Mode box select Active Serial Programming If you are changing the mode from the previously used JTAG mode the pop up box in Figure 44 will appear asking if you want to clear all devices Click Yes Now the Programmer window shown in Figure 45 will appear Make sure that the Hardware Setup indicates the USB Blaster If the configuration file is not already listed
21. if other versions of the software are used some of the images may be slightly different Contents Typical CAD Flow Getting Started Starting a New Project Verilog Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a pro grammable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustrated in Figure 1 Design Entry Functional Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a schematic diagram or by using a hardware description language such as Verilog or VHDL e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues e Fitting the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between specific LEs e Timing Analysis propagatio
22. imulation mode and click OK The Quartus II simulator takes the inputs and generates the outputs defined in the light vwf file Before running the functional simulation it is necessary to create the required netlist which is done by selecting Processing gt Generate Functional Simulation Netlist A simulation run is started by Process ing gt Start Simulation or by using the icon F At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 36 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 11 21 Settings light Category Libraries Device Operating Settings and Conditions Select simulation options H Voltage Temperature j Compilation Process Settings Early Timing Estimate Simulation input ligbw 00 ES Add Multiple Files Ei Hn Incremental Compilation EDA Tool Settings i Simulation period al Design Entry Synthesis Simulation Simulation mode Sites m f Run simulation until all vector stimuli are used T Timing Analysis End simulation at i Formal Verification 3 Physical Synthesis Glitch Filtering options Auto Board Level BH Analysis amp Synthesis Settings More Settings H VHDL Input Verlag HOL Input
23. in the window press Add File The pop up box in Figure 46 will appear Select the file light pof in the directory introtutorial and click Open As a result the configuration file ight pof will be listed in the window This is a binary file produced by the Compiler s Assembler module which contains the data to be loaded into the EPCS4 configuration device The extension pof stands for Programmer Object File Upon returning to the Programmer window click on the Program Configure check box as shown in Figure 47 Quartus Il AN Some devices in current device list cannot be added to selected programming mode Active Serial Programming Do you want to clear all devices in Mo current device list and switch to selected mode Figure 44 Clear the previously selected devices 26 i light cdf DAOR s AJ A J n Hardware Setup USE Blaster 056 0 Mode Active Serial Programming Progress Dx Enable real time ISP to allow background programming For MAX II devices zu e e enm e TERT TES gli Stop 7X Delete 2b Add File Change File Li Save File LS Add Device Up Figure 45 The Programmer window with Active Serial Programming selected Select Programming File Look in B introtutorial amp ex a Cad incremental _db My Recent Documents 3 Desktop My Documents My Computer My Network File name light pot Y Places Files of type POF Files pof
24. indow is depicted in Figure 29 Save the file under the name ight vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 30 You may wish to resize the window to its maximum size SOPC Builder System Design Files AHDL File Block Diagram Schematic File EDIF File State Machine File System erilog HDL File Tcl Script File Verilog HDL File VHDL File Memory Files Hexadecimal Intel Format File Memory Initialization File Verification D ebugaing Files In System Sources and Probes File Logic Analyzer Interface File SignalT ap Il Logic Analyzer File Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File v Cancel Figure 28 Need to prepare a new file Ir light vwf Master Time Bar 15 35 ns 1 Painter 47 ns Interval 11 25 ns Start M Value at amg 15 95 ns Figure 29 The Waveform Editor window 18 I light vwf Master Time Bar 1595ns Pointer 968ne Intervali 6 27 ns Start ps End 200 0 ns j 120 0 ns 180 0 ns Hame Figure 30 The augmented Waveform Editor window 3 Next we want to include the input and output nodes of the circ
25. ing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 28
26. k I O Standard General Function Special Function lt lt new gt gt Figure 22 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Assignment Editor to reach the window in Figure 22 Under Category select Pin Double click on the entry lt lt new gt gt which is highlighted in blue in the column labeled To The drop down menu in Figure 23 will appear Click on x1 as the first pin to be assigned this will enter x1 in the displayed table Follow this by double clicking on the box to the right of this new x1 entry in the column labeled Location Now the drop down menu in Figure 24 appears Scroll down and select PIN L22 Instead of scrolling down the menu to find the desired pin you can just type the name of the pin L22 in the Location box Use the same procedure to assign input x2 to pin L21 and output f to pin U22 which results in the image in Figure 25 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments Figure 23 The drop down menu displays the input and output names 15 S savwm CLKO LYDSCLKOp Input CLK1 LYDSCLKOn Input I O Bank 5 Dedicated Clock CLK4 LVDSCLK2p Input I O Bank 1 Dedicated Clock CLK2 LVDSCLK1p Input I
27. ld the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the left button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Quartus Il Sele File Edit View Project Assignments Processing Tools Window Help 1 X cag jS 55 Jjlxx ewe og rx eojlrjejwwie Project Navigator Compilation Hierarchy ANTERA 7 3 QUARTUS II Compile Design ersion 9 0 Mo Analysis amp Synthesis b Fitter Place amp Route i M Assembler Generate programming files i pes p Timing Analy SIS H B EDA Netlist Writer p Program Device Open Programmer P Documentation ey v Locate OC
28. make the pin assignments for our example circuit by importing this file then we would have to use the same names in our Verilog design file namely SW 0 SW 1 and LEDG 0 for x x2 and f respectively Since these signals are specified in the DEI pin assignments csv file as elements of vectors SW and LEDG we must refer to them in the same way in the Verilog design file For example in the DEI pin assignments csv file the 10 toggle switches are called SW 9 to SW O In Verilog code they can also be referred to as a vector SW 9 0 6 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DEI board it is prudent to simulate it to ascertain its correctness Quartus II software includes a simulation tool that can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal 17 points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 28 Choose Vector Waveform File and click OK 2 The Waveform Editor w
29. ments Processing Tools Window Help OD ae ed a S amp Bgm oc E WK 204 Tr SH OO 4 Project Navigator diy Cyclone Il EP2C20F 48 3 light gj lt m MOARBPSMIMMERMEI E gt Compile Design Version 9 0 E P Analysis amp Synthesis H gt Fitter Place amp Route t M Assembler Generate programming files H gt Classic Timing Analysis Hj EDA Netlist Writer Lu i Program Device Open Programmer Message 35 Message El PE TAM rath eR E E Hr WAT Grisa ide NMM YZ Figure 10 The Quartus II display for the created project 3 Design Entry Using Verilog Code As a design example we will use the two way light controller circuit shown in Figure 11 The circuit can be used to control a single light from either of the two switches x and x5 where a closed switch corresponds to the logic value 1 The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will specify it using the gates shown X1 f 0 l l 0 o 5 O m i Figure 11 The light controller circuit The required circuit is described by the Verilog code in Figure 12 Note that the Verilog module is called light to match the name given in Figure 4 which was specified when the project was created This code can be typed into a file by using any text editor that stores ASCII files or by using
30. n delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by using the Verilog hardware description language It makes use of the graphical user interface to invoke the Quartus II commands Doing this tutorial the reader will learn about e Creating a project Design entry using Verilog code Synthesizing a circuit specified in Verilog code Fitting a synthesized circuit into an Altera FPGA Assigning the circuit inputs and outputs to specific pins on the FPGA Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DEI board Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all information for that project in a single directory folder in the file system To begin a new logic circuit design the first step is to create a directory to hold its files To ho
31. rned on The configuration information is lost when the power is turned off The second possibility is to use the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DEI board Then this data 1s loaded into the FPGA upon power up or reconfiguration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DEI board The RUN position selects the JTAG mode while the PROG position selects the AS mode 7 1 JTAG Programming The programming and configuration task 1s performed as follows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 38 Here it is necessary to specify the programming hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 39 W Quartus Il D introtutorial light light light cdf File Edit Processing Tools Window cs Hardware Setup USB Blaster USB 0 Enable real time ISP to allow background programming for MAX II devices pil Start n Auto Detect dete Gab Add File
32. sages given Quartus II D introtutorial light light Slee File Edit View Project Assignments Processing Tools Window Help WO eels Ae 1K GSS Ory SOR OB ae Project Navigator Its amp Compilation Report Flow Cyclone Il EP2C20F 484C7 5 c z ims bod p 7 ilati e Flow D abe light ag ompilation Report ummary Y Compilation Report Flow Summary E Legal Notice EE Flow Summary Em Flow Settings Flow Status Successful Wed Apr 29 15 01 30 2009 ES Flow Non Default Glob Quartus Il Version 3 0 Build 132 02 25 2008 SJ Full Version SEES Flow Elapsed Time Revision Name light BBS Flow OS Summary Top level Entity Name light EP B Flow Log Family Cyclone II ED Analysis amp Synthesis Device EP2C20F484C7 Eb Fitter dy Hierarchy B Files d Design Units E Timing Models Final ER Assembler Met timing requirements Yes EP Timing Analyzer Tasks Jic a iii Total logic elements 1 18 752 lt 1 Flow Compilation Total combinational functions 1 18 752 lt 1 De atad DUC levee ANE Compile Design 00 00 30 Total registers 0 P Analysis amp Synthesis 90 00 06 Total pins 3 315 lt 1 Fitter Place amp Route D0 00 11 Total virtual pins 0 Assembler Generate programming files 00 00 09 Total memory bits 0 233615 02 Classic Timing Analysis 00 00 04 Embedded Multiplier 9 bit elements 0 52 0 EDA Netlist Writer Total PLLs 0 4 02z b g amp B Program Device Op
33. stance selecting Help gt How to Use Help gives an indication of what type of help is provided The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which keywords can be entered Another method context sensitive help is provided for quickly finding documentation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 2 Starting a New Project To start working on a new design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard to reach the window in Figure 4 which asks for the name and directory of the project New Project Wizard Directory Name Top Level Entity page 1 of 5 E What is the working director for this project ID introtutorial ae What is the name of this project light ae What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design file light t Use Existing Project Settings Finish Cancel Figure 4 Creation of a new project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have
34. the Quartus II text editing facilities While the file can be given any name it is a common designers practice to use the same name as the name of the top level Verilog module The file name must include the extension v which indicates a Verilog file So we will use the name light v module light x1 x2 f input xl x2 output f assign f x1 amp x2 x1 amp x2 endmodule Figure 12 Verilog code for the circuit in Figure 11 3 1 Using the Quartus II Text Editor This section shows how to use the Quartus II Text Editor You can skip this section if you prefer to use some other text editor to create the Verilog source code file which we will name light v Select File gt New to get the window in Figure 13 choose Verilog HDL File and click OK This opens the Text Editor window The first step is to specify a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 14 In the box labeled Save as type choose Verilog HDL File In the box labeled File name type light Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Text Editor window shown in Figure 15 Maximize the Text Editor window and enter the Verilog code in Figure 12 into it Save the file by typing File gt Save or by typing the shortcut Ctrl s Most of the commands available in the Text Editor are self explanatory Text is enter
35. the toolbar or the Waveform Editing Tool which is activated by the icon e To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 11 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform name for the x node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for setting a selected signal to 0 1 unknown X high impedance Z don t care DC inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by right clicking on a waveform name Set x to 0 in the time interval O to 100 ns which is probably already set by default Next set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 5
36. tion mode Timing ls Master Time Bar D ps gt Pointer 85 34 ns Interval 85 34 ns Start End D ps 40 0 ns 80 0 ns 120 0 ns 160 0 ns 200 0 ns D ps Figure 37 The result of timing simulation 7 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required configura tion file is generated by the Quartus II Compiler s Assembler module Altera s DEI board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DEI Board for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains tu
37. torial To add this file to the project click on the File name button in Figure 16 to get the pop up window in Figure 17 Select the light v file and click Open The selected file is now indicated in the Files window of Figure 16 Click 11 OK to include the igt v file in the project We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in Verilog code even if the file has not been explicitly added to the project However for complex projects that involve many files it is a good design practice to specifically add the needed files to the project as described above Settings light Category General Libraries Select the design files you want to include in the project Click Add All to add all design files in the i Device project directory to the project j Operating Settings and Conditions gt Voltage File name 2s Temperature l Compilation Process Settings Filename Type Library Design enty s HDL version AddAl Ear Timing Estimate light v Verilog HDL None Incremental Compilation EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Formal Verification Physical Synthesis Board Level B Analysis amp Synthesis Settings H VHDL Input Verlag HOL Input Default Parameters En Synthesis Netlist Optimizations Fi
38. tter Settings 00 Physical Synthesis Optimization E Timing Analysis Settings H TimeQuest Timing Analyzer Classic Timing Analyzer Setting Classic Timing Analyzer Hc Assembler Design Assistant A E SignalT ap Il Logic Analyzer Logic Analyzer Interface F Saas Di oe ascbsne Dahuan Figure 16 Settings window Select File lens Se Bm E A dh My Recent Documents Desktop My Documents My Network File name flight T Places M Files of type Design Files tdf vhd hal v vlg verlog Cancel Figure 17 Select the file 12 4 Compiling the Designed Circuit The Verilog code in the file light v is processed by several Quartus II tools that analyze the code synthesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon amp that looks like a purple triangle As the compilation moves through various stages its progress is reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 18 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate mes
39. uit to be simulated Click Edit gt Insert gt Insert Node or Bus to open the window in Figure 31 It is possible to type the name of a signal pin into the Name box but it is easier to click on the button labeled Node Finder to open the window in Figure 32 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the input and output nodes as indicated on the left side of the figure Insert Node or Bus E Mame Type INPLIT Cancel Value type 9 Level E Node Finder Radix as Cll n Bus width Start index Display gray code count as binary count Figure 31 The Insert Node or Bus dialogue Node Finder Named fi Filter Pins all Customize List Q Look in flight pi IV Include subentities toy Cancel Nodes Found Selected Nodes PIN_U22 Output I lightlx1 PIN_L22 Input PIN_L22 Input ES llight 2 PIN L 21 Input PIN L21 Input T llightlf PIN U22 Output gt lt Figure 32 Selecting nodes to insert into the Waveform Editor 19 Click on the x signal in the Nodes Found box in Figure 32 and then click the gt sign to add it to the Selected Nodes box on the right side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 31 This leaves a fully displayed Waveform E
40. vice selected in Available devices list Logic amp nalyzer Interface Simulator Settings Other n a Device and Pin Options PowerPlay Power Analyzer Settings SSN Analyzer Available devices Name Coev LlEs Userl Memor Embed EP2C20F256C6 239616 EP2C20F256C7 239615 EP2C20F256C8 239615 EP2C20F256I8 239615 EP2C20F484C6 239616 EP2C20F484C7 a EP2C20F484C8 18752 315 lt CH Ec Ec Pin count Any Y HardCopy compatible only Migration compatibility Companion device Migration Devices HardCopy 0 migration devices selected v Limit DSP amp RAM to HardCopy device resources Figure 41 The Device Settings window Device and Pin Options Voltage Pin Placement Error Detection CRC Capacitive Loading Board Trace Model 170 Timing General Configuration Programming Files Unused Pins Dual Purpose Pins Specify general device options These options are not dependent on the configuration scheme Options Auto restart configuration after error Release clears before tri states Enable user supplied start up clock CLKUSR Enable device wide reset DEV CLRn Enable device wide output enable DEV OE Enable INIT DONE output Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF In system programming clamp state Delay entry to user mode Description Directs the device to restart the configuration process automat
41. z Figure 46 Choose the configuration file W Quartus II D introtutorial light light light cdf File Edit Processing Tools Window es Hardware Setup USB Blaster USB 0 Mode Active Serial Programming Progress Enable real time ISP to allow background programming for MAX II devices pose e ons sam NE E ESTEE IEEE L L all Stor light pof EPCS4 O5FIED3C 00000000 pb Auto Detect X Delete ab Add File amp Change File For Help press F1 Figure 47 The updated Programmer window 27 Flip the RUN PROG switch on the DEI board to the PROG position Press Start in the window in Figure 47 An LED on the board will light up when the configuration data has been downloaded successfully Also the Progress box in Figure 47 will indicate when the configuration and programming process is completed as shown in Figure 48 W Quartus II D introtutorial light light light cdf File Edit Processing Tools Window ess Hardware Setup USB Blaster USB 0 Mode Active Serial Programming Progress Enable real time ISP to allow background programming for MAX II devices ae ff onse oes Dome Sa ven Beh Tienen D ee Ls m E light pof EPCS4 O5FIED3C 00000000 X Delete eg Change File For Help press F1 Figure 48 The Programmer window upon completion of programming 8 Testing the Designed Circuit Having downloaded the configuration data
Download Pdf Manuals
Related Search