CS-E9302 User Manual
Contents
1. 200000 200000 200000000000000000 8 125 B 100000 no000 180000000000000000 0 000 o 10 10 34 Po od I LO IO od ON mM Qo a 9 r All measures are in mm CS E9302 is distributed with CD with Linux 2 4 NetBSD and Linux 2 6 sources and pre build images for Linux 2 4 Linux 2 6 and NetBSD The boards are pre loaded with Linux 2 6 in the internal flash The software for CS E9302 could be developed and debugged on desktop computer then cross compiled and loaded in the board Here below is example how to cross compile Hello world program In most of the cases you do not need JTAG as on the other embedded systems which do not have RTOS how often do you develop on your Pentium desktop computer with JTAG but for case where peoples want to blink LEDs without RTOS we have provided the JTAG connector as well Cross compiling a simple hello world example Extract one of the provided cross compilers on your host system and add it to the PATH variable Use the cross compiler to build the example then transfer it to the board by e g USB flash drive http download etc Example commands On the host system cd usr local arm tar xjf arm linux gcc 4 1 1 920t tar bz2 PATH PATH usr local arm 4 1 1 920t bin cat gt hello c include lt stdio h gt int main void unsigned int i printf r nProba proba for i70 i lt 10 i printf r n d i return 02. SCHEER te E H G 3 3 fa ven TON ET 8 57 een 0090 S z0ssn zn 8 H een Con B 0 een s zs 399 eros ps zda Tssa na ge ee S aH sus soon Suu wae MV gaan sva m 30 zoom L t Non 20487 om s9 ee 230 7 oon 3 zoon muaa Less 039 Toon weg too 700 eroa 2100 1700 om 650 800 200 Gel 90a spa 00 eva zaa 700 D swa aa z KS SS S ied zw Foo Sw at ee 8100 dy BTY ar r oa Erde a B0 Zi 800 sv EI ow aer aE s Su S 2 mo w m m toot SS mo W of ZS EL BY TN m BOARD LAYOUT rs232 USB Osis ethernet RS232_ 8 R45 Kerg t U W I 1 022 CH BF 3i D ks 672 NVATYL nN TLZZOST 6TLOSOCAVMSS ZOI 20E6d4 Sr paso E ke US Anton TTT lak SS o i 5 e a c4sW1 gt T 209 CR ior en a eB SI a 5 HUU OLIMEX COH DEV ape _ 602007 oe mn EXT POWER SUPPLY CIRCUIT CS E9302 power supply should be 5V regulated please do not use other than 5V power supply as the power line goes to the USB hosts and if you apply power supply above 5V this will destroy your USB devices The PWR_JACK inner pin is positive The board power consumption is about 400 450 mA with 200 MHz CPU clock and 100MHz system bus RESET CIRCUIT The EP9302 chip can be reset through t
3. AD arm linux gcc o hello hello c cp hello htdocs On the board wget http 192 168 0 xx hello chmod 777 hello hello Proba proba 0 1 ORDER CODE CS E9302 assembled and tested no kit no soldering required How to order You can order to us directly or by any of our distributors Check our web www olimex com dev for more info Pote Geen AU boards produced by Olimex are RoHS compliant Revision history REV A created July 2008 Disclaimer 2008 Olimex Ltd All rights reserved Olimex logo and combinations thereof are registered trademarks of Olimex Ltd Other terms and product names may be trademarks of others The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex products Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvements All particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fi
4. Reserved Reserved 0x8000 0000 0x800F FFFF AHB mapped registers AHB mapped registers 0x7000 0000 Ox7FFF_FFFF Async memory nCS7 Async memory nCS7 0x6000_0000 0x6100_0000 16MB on board NOR flash Async memory nCS6 Async memory nCS6 OxSFFF_FFFF Reserved Reserved Ox4FFF_FFFF Reserved Reserved Ox3FFF_FFFF Async memory nCS3 Async memory nCS3 Ox2FFF_FFFF Async memory nCS2 Async memory nCS2 Ox1FFF_FFFF Async memory nCS1 OXOFFF_FFFF Sync memory nSDCE3 Async memory nCS1 Async memory nCSO SCHEMATIC Dara corse OOK axe Lx3n 7 1X30 ess 1X30 2 SL EE vz s EM SE Ge ooz CEJ H 0059 770054 e vs ing aa Be Ta 07 S a No IN 13524 ole mm ES Se dE SERA Hr S i P ton 3 x Eed nee OZEJU Z Desive a zogen LZ oxy Tua XL eiar 95 vad AUSTESOKOI Dat d 0kST690 09 1 Dat 191090 08174 avg ET ere acd 28 Gi g A g 8 A dee der x st st nee OU STEEN 397 al Keck as T SE 4 ck Geer Die CR SE STZ 2057 as 08 FE j E E 1X3 BT TE 1X3 nee a ast D S T Sa Sea KE Gem ES Zem KC S
5. CS E9302 development board Users Manual Rev A July 2008 Copyright c 2008 OLIMEX Ltd All rights reserved INTRODUCTION CS E9302 is powerful development board for 200MHz Cirrus Logic EP9302 ARM920T microprocessors with two USB hosts two RS232 ports 100Mbit Ethernet SD MMC card 16MB NOR Flash 32MB SDRAM IrDA transciever JTAG UEXT EXT ADC connectors for additional peripherials BOARD FEATURES MCU EP9302 ARM920T 200Mhz 16 16KB instruction and data cache MMU SDRAM SRAM FLASH external bus controller 100Mhz bus 100Mbit Ethernet MAC two UARTS two USB 2 0 ports IrDA ADC SPI DS Audio AC97 DMA 12 ch RTC dual PLL WDT 2 16 bit 1 32 bit TIMERS boot ROM interrupt controller External SDRAM 32MB 16MB x16bit 7 5 ns 133MHz External Flash 16MB 8MB x16 bit 80 ns ETHERNET 10 100 PHY KS8721BL 2x RS232 drivers and connectors 2x USB host connectors SD MMC card IrDA transciever on board UEXT connector with I2C SPI RS232 and power supply for connecting add on modules like RF link MP3 etc available from Olimex JTAG interface ADC extension port Power supply plug in jack Linux 2 4 Linux 2 6 and NetBSD sources and pre build images ready to load with Redboot are available on the supplement CD Dimensions 110x90 mm 4 3 x 3 5 ELECTROSTATIC WARNING The CS E9302 development board is shipped in protective anti static packaging The board must not be subj
6. 0 This is the asynchronous serial data input RS232 for the shift register on the UARTO controller This pin is output for the RS232 and input for the LPC2478 TXD 1OutputTransmit Data 1 This is the asynchronous serial data output RS232 for the shift register on the UART1 controller This pin is input for the RS232 and input for the LPC2478 RXD lInput Receive Data 1 This is the asynchronous serial data input RS232 for the shift register on the UARTI controller This pin is output for the RS232 and input for the LPC2478 ETHERNET The CS E9302 is shipped with a complete physical and MAC subsystem The EP9302 supports 1 10 100 Mbps transfer rates The MAC subsystem is compliant with the ISO TEC 802 3 topology for a single shared medium with several stations Multiple MII compliant PHYs are supported The PHY layer is realized with MICREL PHY chip KS8721BL 12345678 RJ45 SIDE QOoOonw noha o e EES RE E o e o L im OOM Hal duplo TD OutputDifferential signal output This signal is output from the MCU TD OutputDifferential signal output This signal is output from the MCU RD Input Differential signal input This signal is input for the MCU RD Input Differential signal input This signal is input for the MCU UEXT spe Tie me r sa esse o sa o srrvn UEXT is a universal OLIMEX connector with 3 3V power supply and UART SPI interface MCU HGPIO 2 and HGPIO 3 port connected to UE
7. The corresponding jumpers are TO_H TO_L and T1_H T1_L When the TO_H TO_L jumper is closed to TO_H side TESTO pin is 1 When the TO_H TO_L jumper is closed to TO_L side TESTO pin is O When the T1_H T1_L jumper is closed to T1_H side TEST1 pin is 1 When the T1_H T1_L jumper is closed to T1_L side TEST 1 pin is 0 ASDO Select synchronous or asynchronous boot The corresponding 3 pin jumper is ASDO_H ASDO_L If the jumper is closed to ASDO_H side ASDO pin is log 1 The Other side is log O CSN 7 6 Select external boot width CSN6 and CSN7 are the jumpers which define logical level of these pins If the jumpers are closed the corresponding pin is O EECLK EEDAT TEST1 TESTO ASDO CSN 7 6 Boot Configuration External boot from Sync memory space selected by DevCfg3 through the SDRAM Controller The 00 media type must be either SROM or SyncFLASH 0 1 0 0 1 01 The selection of the SRAM width is determined by latched CSN 7 6 value 8 bit SFLASH 16 bit SROM External boot from Async memory space selected by nCSO through Synchronous Memory Controller The 0 1 0 0 0 00 selection of the SRAM width is determined by 01 latched CSN 7 6 value 8 bit SRAM 16 bit SRAM 1 1 0 1 x 01 16 bit SERIAL BOOT Boot from external NOR FLASH The selection of the bus width is determined by latched CSN 7 6 00 H J 0 0 J 01 value 8 bit 16 bit DEFAULT POSITION NORMAL B
8. DA module If RXD1 state is selected 1 2 shorted RXD1 pin is connected through RS232 driver U5 to RS232_1 connector Default position is 1 2 shorted IRDA TXD1 The IRDA TXD1 jumper defines TXDl pin 114 of e e e W connection When the jumper is installed in IRDA state 2 3 shorted then TXD1 function of MCU is 3 2 1 connected to IRDA module If TXD1 state is selected 1 2 shorted TXD1 pin is connected through RS232 driver U5 to RS232_1 connector Default position is 1 2 shorted IRDA_LS_E IRDA_LS_E jumper is used if Low Speed mode of an chip must be selected When the jumper is closed the user enables Low Speed mode Default position is open RST_E When the RST E jumper is closed pinl5 of JTAG o connect is tied to RSTN User Reset line or allows JTAG reseting Default position is closed UEXT RXD0 The UEXT RXDO jumper defines RXDO pin 109 of e i connection When the jumper is installed in UEXT state then the RXDO function of MCU is connected to 3 2 1 the UEXT connector If RXDO state is selected RXDO pin is connected through RS232 driver US to RS232_0 connector Default position is 1 2 shorted INPUT OUTPUT Two reset buttons with names RSTN and PRN connected to EP9302 chip pin 124 RSTON and pin 125 PRSTN One user button with name BUT connected to EP9301 pin 201 HGPIO 4 Two LEDs RED connected to EP9301 pin 98 RDLED and GREEN connected to EP9301 pin 97 GRLED Power supply r
9. E Sg E ES Se E Ee EES E GE ER ees Pr Km T 507 men Sr DEG eeng Sa RN Eer em ESCH Ko Gs Tess 36 Kc Se ES Sr 1 s S Z nee va FT TKU OFT em RH Siet E E 82 1X3 su 265 Dee Sen SEI an Sam EU E 8T CCRN LERSCH 26 571 0 GST Se EST St 1x3 er ES Set EE SE SE EST 1x3 r as sA m 1X3 arr REG Zar 1 aT 7 201803 EE VEH 1907 oe eg os eagO d 4401 ESCH E ax T ex 4107007077 3015 apru 5 sj 3 x aaron 1 8 a 5757 g lol zl al 213 JA S el F F EES 155 3 I WAFER REE UBAT S A7 zeza TORE 5 283 Gel R nee So S feb SBBORLRIKKAS SHRED ES ES odsatie 1v1 Z E zos 1931 0031 OSL K EEGEN Zog X314N0 2011 EGTSOG NOSEI NOXY koume Ka Oe Ko torao piid g beul xaa VOJAK zaoa ES Ee E Zaiten N3x4 08X4 Ke 0N9 904 SOND n 1 e H sara oy ere ae mes EE ams T Nvo ZZ Kmec Dreem eg 7 Se ES E 2s EI Taso Der Sek 41 6 64 T 6 G Ser amf 1 nz zuez E UI pesg Suen oe neer
10. Ke teziay e 72104 teziay eu 187104 Lu Gu 97104 Kaze IET 27104 ergy Kaze 6104 t8104 12104 13109 ie East ie 2104 TOY ite 402 azz ees 5 ES T et x Toor DARIA KIA KUA ZER Cem ut oat fur fuer wer wary ver fuer y 697 56 z Del TL ps ai nes o Sai zco rea ocoTesoTasa esoJosoT asd Xact urg S ON ozta Sma Ty D SCH Den e SS G T T ayo 0487690 09 ur oere CA boar peor pear ASIA vsdlesglzsg 193 osa lee esa zasl oa gas so lesa uber By NEJ 1 neve 1Ue1 N 9 4NGOT ae a oe eera NILE CH A olesalzs nol es sea s 37 i pe now ie Le aH SEL Lai tee T0 eg SS 877 ON Ted TULA TL voet 2893487 SES MEA peot WUEL NE SZENBBT ONS voey c eri Ha eee ted A do m Atuo 3ans neve 113 ONZBS1TI4 9021G i nm oer aa s 8 2 R ges EN ur inotvanotL uoat wens Agen co A feo eza Zeta EA M SCH vz H ana RW Ss T PSE IS GR z 7 TT Lt EZSKTO KA ZT TeL H OL neeO US Set Se poort sory Ser Si ET RW er eae 500 Eer zw 5 309 rer nwa Eug zs sz re on EB 11531 ap 407 zal lza lleza ueozlveor ENT 201 71N 3 ca Waa SEL on was aT 2344 44 nee
11. OOT Internal boot from on chip ROM The selection of the ROM width is determined by latched CSN 7 6 00 1 1 0 0 0 01 value 8 bit 16 bit Only two selections are functional for the user Normal Boot and Serial Boot The other modes are reserved for factory use only The BLUE table line is the default boot position Watchdog configuration jumpers CSNI CSN2 Disable Watchdog reset timer If the CSN1 jumper is closed the corresponding pin CSN1 is O otherwise 1 Disable Watchdog reset duration If the CSN2 jumper is closed the corresponding pin CSN2 is 0 otherwise 1 CSNI CSN2 Startup Option 0 Watchdog Disabled Reset Duration Disabled 1 Watchdog Disabled Reset Duration Active 0 Watchdog Active Reset Duration Disabled 1 Watchdog Active Reset Duration Active The BLUE table line is the default boot position WPD WPE The WPD WPE jumper defines Write protected state e R NOR FLASH U2 JS28F128J3C120 WPD state 1 2 shorted enables flash write WPE 1 2 3 state 2 3 shorted disables flash write Default position is 1 2 shorted EE WP When the EE WP jumper is it closed disables U7 AT25F 1024 EEPROM write Default position is open IRDA RXD1 The IRDA RXD1 jumper defines RXD1 pin 110 of MCU connection When the jumper is installed in IRDA 2 3 shorted then the RXD1 function of MCU is 3 2 1 connected to IR
12. XT pin 5 and pin 6 Other device or modules with these interfaces can connected with UEXT For example MOD NRF24L http www olimex com dev mod nrf24L htm1 MOD RFID125 http www olimex com dev mod rfid125 html MOD MP3 http www olimex com dev mod mp3 html ADC Signal Name Signal Name ADCO ADCI apc2 fe Lac ADC_VDDG3V s leo lu jon Vaie The ADC block consists of a 12 bit Analog To Digital converter with a analog input multiplexer The multiplexer can select to measure battery voltage and other miscellaneous voltages on the external measurement pins Signal should be in range O to 3 3 V ADC complete may issue interrupts SD MMC CARD INTERFACES nn Signal Name CS 1 s okove o okove 11 ut 94H 0S EXT 246 8 10 12 14 16 18 20 22 24 26 28 30 32 34 SAER RRRRERRE 1 3 5 T 9 11 13 15 17 19 21 23 25 27 29 31 33 1 eero 2 EGPIOIIS eno errors s Tecno e emm Jeng Jk Jee 100I o Tecno Ire 100000 On this connector are available all GPIOs of EP9302 which are not used for other purposes With them you can make add on modules to control with CS E9302 like GSM GPS input output add on boards TAG The JTAG connector allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Instructions may be inserted and executed by the core thus allowing MCU memory to be programmed with code and executed step by
13. ect to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board BOARD USE REQUIREMENTS Cables Two DB9 female female null modem type for connection with serial COM port of PC host Crossed LAN cable for connection with PC or straight LAN cable for connection with switch or router Hardware 5V 1A regulated power source ARM JTAG ARM USB OCD ARM USB TINY or other compatible tool only if you want to develop with JTAG usually with the pre loaded linux RTOS this is not necessary Software The boards are delivered pre loaded with Linux 2 6 PROCESSOR FEATURES The EP9302 system on chip processor has the following features 200 MHz ARM920T Processor 16 KByte data cache and 16 KByte instruction cache MMU enabling Linux and Windows CE 100 MHz system bus MaverickKey IDs for Digital Rights Management or Design IP Security 32 bit unique ID 128 bit random ID Integrated Peripheral Interfaces 1 10 100 Mbps Ethernet MAC Two port USB 2 0 Full Speed host OHCI Two UARTs 16550 Type IrDA interface slow and fast mode Analog to Digital Converter ADC Serial Peripheral Interface SPI port AC 97 interface BS interface up to 2 channels External Memory Options 16 bit SDRAM interface up to four banks 16 8 bit SRAM Flash ROM interface I F Serial EEPROM interface Inte
14. ed LED with name PWR indicates that power supply is present CONNECTOR DESCRIPTIONS USB1 USB2 Signal Name Signal Name USBMO and USBPO form the differential input output of the USB host 0 USBM1 and USBP1 form the differential input output of the USB host 1 The USB Open Host Controller Interface Open HCI provides full speed serial communications ports at baud rate of 12 Mbits sec Up to 127 USB devices printer mouse camera keyboard etc and USB hubs can be connected to the USB host in the USB tieredstart topology The USB port is compliance with the USB 2 0 specification and supports both low speed 1 5 Mbps and full speed 12 Mbps USB device connections RS232 0 RS232 1 a Aa UARTO supports modem bit rates up to 115 2 K 1 esa 16 byte FIFO for receive and a 16 byte FIFO for transmi z OS is available at the RS232 0 DB9 male connector The amp js 8 data bits no parity 1 stop bit no flow control UART1 contains an IrDA encoder operating at either the slow up to 115 Kbps medium 0 576 or 1 152 Mbps or fast 4 Mbps IR data rates It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit RS232_0 RS232_1 Signal Name Signal Name ni rn fe f TXD_O OutputTransmit Data 0 This is the asynchronous serial data output RS232 for the shift register on the UARTO controller This pin is input for the RS232 and input for the LPC2478 RXD Olnput Receive Data
15. he PRSTN pin power on reset or through the open drain common reset pin user reset RSTON pin PRSTN is a Power on Reset realized with MCP130T Reset circuit with typical 2 9V threshold On the board is present a PRN button which is used for manual Power on Reset The user reset RSTON is common for the CS9203 microcontroller PHY chip NOR flash JTAG and MCP130 Supervisory circuit It can be generated from JTAG pin 15 RSTN button CS9302 or MCP130T Reset circuit CLOCK CIRCUIT EP9302 generates its internal clock with PLL and uses single14 7456 MHz crystal connected to EP9302 pin 119 XTALO and pin 118 XTAL1 The Real Time Clock operates from a 32 768 KHz crystal JUMPER DESCRIPTION Boot configuration jumpers The Hardware Configuration controls are defined by a set of device pins that are latched into configuration control bits on the assertion of chip reset on the rising edge of the PRSTN or RSTON pin The different hardware configuration bits define watchdog behavior boot mode internal or external boot synchronicity and external boot width The latched pins are EECLK Select internal or external boot The corresponding jumper is EECLK_L When the jumper is closed EECLK pin is log 0 otherwise log 1 EEDAT Should be pulled up to 1 The corresponding jumper is EEDAT_L When the jumper is closed EEDAT pin is log 0 otherwise log 1 TEST 1 0 Select boot mode
16. rnal Peripherals Real Time clock with software trim 12 DMA channels for data transfer that maximizes system performance Boot ROM Dual PLLs control all clock domains Watchdog timer Two general purpose 16 bit timers General purpose 32 bit timer 40 bit debug timer General Purpose I Os 16 enhanced GPIOs including interrupt capability 31 additional optional GPIOs multiplexed on peripherals EP9302 BLOCK DIAGRAM Vectored Interrupt 17S IIS System Ctrl PLLs 2 UART1 wi HDLC UART2 w IrDA Controllers 2 SRA SDRAM M FLASH ROM 12 Channel DMA Engine 1 10 100 Ethernet MAC JTAG USB Host 2 Ports ARM920T Cache D Cache AMBA Peripheral Bus APB Enhanced GPIO EEPROM LED 2 Watchdog Timer RTC with Trim AMBA High Speed Bus AHB AHB APB Bridge MEMORY MAP Address Range 0xF000 0000 0xF200 0000 32MB Async Memory Boot ASDO Pin 0 Sync Memory Boot ASDO Pin 1 on board SDRAM Async memory nC SO Sync memory nSDCE3 0xE000 0000 OxEFFF_FFFF Sync memory nSDCE2 Sync memory nSDCE2 0xD000_0000 OxDFFF FFFF Sync memory nSDCE1 Sync memory nSDCE1 0xC000 0000 OxCFFF_FFFF Sync memory nSDCEO0 Sync memory nSDCE0 0x9000 0000 OxBFFF_FFFF Not Used Not Used 0x8080 0000 Ox8FFF_FFFF APB mapped registers APB mapped registers 0x8010_0000 0x807F_FFFF
17. s SES 159 163 mm 1283 if I 5 DEENEN 017 XAH1T0 2087 D LHOIBAdOJ FNIYU ZBECI1 SI DEI ES TON 14033 41933 DESCH 03139 EEN Cie Coen LOJOXETIU een GU Cu OJOX LIU ao suo BECH be Ech Sen erg aen 0104 304 Leen Lummen rezaasn ramasn Tms Thuas io Fxudss Ven We Weg neen Cat Come ont oe DIEN Een 1054 NASH Eech tg201daH Lion rezordoH Lien rezord94 2101494 TOId94 rezord93 TO1494 2101493 toen Geen 901493 9701493 Goen 801494 16701493 e ETHOI093 27101493 teri01d03 Geen 61101493 emie EEN Gem Ces oe NAHOS NSVO E Esc Wars Cam KE Le Ge LENSI CEA Ce Kr Win Wen Now tamwa feast Lea 27140 aaa oa 6X0 rea Lie 940 Ke Ge EWO ZWO CO rea 834007 0N9 2380970N9 9210370N9 Ser Ou ar Oe CC Ou Cer Oe T3402 oe 834097000 24097001 91037001 93037000 Ger 0 n Car o n 7241097000 Le o n BTONI TONY ZTONTE TONY STONRITONY STONRY TONY Cer Crew ge ZT NIH gu Leni gue BT NIHTONI peur gue BONISTOND venir TONA Senn gei Sun gue BMC EONTETONY Cour gu ce ronte aon Bee Sous g ronn OD Etant o n ZTONT TOO Loun 00N Gronn aon Senn O n Soup O n vente g n 9SNIETODN S NI O n ven OON Cour g Cour g n Lenin OD Der Kee Tax 0791X 14L LU OWL DESEN 0007304 rom Ke 121304 TDW Ke SHL 001 TOL OL NISL een EH LENNI Com Ka apen Nistid reen
18. step by the host software For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port 7 ms b lov 9 k In le FeKIGND 12 4 AND S 16 ap i8 op GND TDI Input Test Data In This is the serial data input for the shift register TDO OutputTest Data Out This is the serial data output for the shift register Data is shifted out of the device on the negative edge of the TCK signal TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine TCK Input Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edge triggered clock with the TMS and TCK signals that define the internal state of the device TRST Input Test Reset This signal resets the JTAG controller TCK OutputClock This is a synchronization signal which the JTAG connector uses to acknowledge it is ready to receive transmit RSTN Input Reset This signal resets the MCU This connector shares the ARM default JTAG layout PWR Pin Signal Name SVD ONLY Note Apply only 5V DC regulated voltage MECHANICAL DIMENSIONS 3 543 99 mm Ce e 3 415 E Oz O 5000001 ppppnp 885 O z ooo 5 Sal P REEL US gA D F09 900006 5000001 e SE a4 Se een a 2 u 4 0000 SE SR Beeepl CH o BB BH u Il E A FE D EE Bar a Oe 20000000000 10000000000 28 O a 205 0
19. tness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product
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