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DCAN Macro Version B2 Preliminary User`s Manual

1. 88 Chapter 16 Interrupt Information 000 eee eee 89 16 1 Interrupt Vectors 89 16 2 Transmit Interrupt 0 00 eee eee eens 89 16 3 Receive Interrupt 202s 89 16 4 Errorlnterr upl eae ee eee a eee AR PS 90 Chapter 17 Power Saving 91 17 1 oA REIR eM 91 17 2 CPU WATCH Mode eseseeee ern hn nn nn nhanh 91 17 3 CPU Stop Mode nth ee ne ua hoe u c E 91 17 4 DCANSIeep 91 17 5 DCAN Stop Mode rei eee bee Che al ee ake 93 Chapter 18 Functional Description by 95 18 1 Initialization oes et ree Re ee ee Se Be ay ee ees 95 18 2 Transmit 96 18 3 Abort Transmit clem RR x ee EX ee 97 18 4 Handling by the 98 18 5 Receive Event 99 18 6 Receive Task 100 8 Preliminary User s Manual U14668EE3VOUMOO Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2
2. 43 Chapter8 Transmit Buffer 44 Chapter9 Transmit Message Buffer 45 9 1 Transmit Message Definition 46 9 2 Transmit Identifier Definition 47 9 3 Transmit Data Definition 2 2 200 ee 48 Chapter 10 Receive Buffer 49 Chapter 11 Receive Message Buffer Format 50 11 1 Receive Control Bits Definition 51 11 2 Receive Status Bits Definition 52 11 3 Receive Identifier 54 11 4 Receive Message Data Part 55 Chapter 12 Mask Function 1 cs ur RI RRR 57 12 1 Identifier Compare with 58 12 2 Mask Identifier Control Register MCON 59 12 3 Mask Identifier Definition 60 Chapter 13 Operation of the Controller 61 13 1 Control Register 61 13 2 Control Register CANCn
3. rf RR I REG RERER eee 5 Chapter1 Outline Description llleeeeeen ii 13 Chapter2 CAN Protocol ciere tu RE Rr eta eed bee eee EE ES 15 2 4 Protocol Mode Function 000 e eee eee 15 2 2 Message Format ie hose dette ek ed eee RR ede EAE ER 16 2 3 Data Frame Remote 17 2 3 1 Description of each field cece tees 18 24 ErrorFrame pe ecco cee ceed RE Stee ERI eden ates 24 2 5 OverloadFrame 2 cnn ee hee eR een ee E ERE 25 Ghapter 3 Function auo neben cer EUR Mex a 27 34 Arbit ation ll ee gts ee ee ee a 27 3 2 Bit Stuffing isis oe eee I Eg au 28 33 Master fe eae RAI Mae ae ne oa eee 28 3 4 Mu lti CdSU ae ie eee Me A eee ee Bee ee E 28 3 5 Sleep Mode Stop Function 0 00 cece eee eee 28 3 6 Error Control Function oeil See Sa de RP EEE 29 3 7 Baud Rate Control Function 0000s 32 3 8 State Shift Chart on E ake 35 Chapter 4 Connection with Target 39 Chapter 5 DCAN Controller Configuration 40 Chapter 6 Special Function Register for DCAN module 41 Chapter 7 Message Buffer Configuration
4. 0 0 62 13 3 Error Status 67 Preliminary User s Manual U14668EE3VOUMOO 7 13 4 CAN Transmit Error 70 13 5 CAN Receive Error 70 13 6 Message Count 71 Chapter 14 Baud Rate 73 14 1 Bit Rate Prescaler 73 14 2 Synchronization Control Registers 0 and 1 75 Chapter 15 Function Control urs ERI Gente atthe EE ERR RE EET RE 79 15 1 Transmit ss 2 22 lle sce dele SE eee oliin Ron RI ie e afe 79 15 1 1 Transmit Control 79 15 2 Receive Control ocu is cede eee te Rie Si ee ae Se eed at 82 15 2 1 Receive Message 82 15 3 Mask Control 5 nue a dig dota ae ere ate 83 15 3 1 Mask Control 83 15 4 Special Functions whee epee mere Sa Hee a ae ee alee 86 15 4 1 Redefinition Control 86 15 5 Performance of the
5. Toggles with each start of frame on the CAN bus Clears SOFE bit when DCAN starts to store a message in receive buffer 4 SOFCn is located in the synchronisation register SYNC1n RESET and setting of the INIT bit of CANCn register clears the SOFOUT to 0 64 Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the DCAN Controller Figure 13 4 Time Stamp Function INT INT Object n Object n A 4 _ Other valid or 4 Valid message invalid message Valid message gt SOF SOF SOF A A gt Enable SOF Edge for capture Edge for capture Figure 13 5 SOFOUT Toggle Function Any valid or Any valid or Any valid or A invalid message invalid message invalid message SOF SOF SOF A gt Edge for Edge for Edge for capture capture capture Enable SOF Figure 13 6 Global Time System Function INT Object n Other valid or Valid sync 4 Other valid or A invalid message message buffer4 7 invalid message SOF SOF SOF A gt Edge for Edge for capture capture Enable Disable SOF SOF Preliminary User s Manual U14668EE3VOUMOO 65 Chapter 13 Operation of the Controller Figure 13 7 Transmission Reception Flag Transmission Flag 0 No transmission 1 Transmission active on CAN bus Note Note Transmission is active until intermission is completed Reception Fla
6. sse eene 23 Interframe Space Error Passive sssssssssssssesesee eene 23 Ero Erame ossium rm ten ipaa aur tuu arteriae eee 24 Overload Frame nis inopi anben E e deed gis REPE RU Lee 25 Nominal Bit Time 8 to 25 Time Quanta sse 32 Adjusting Synchronization of the Data Bit sssssssssssseeeeennen 33 Bit SyDnchronizationi eoe aider oe Re ex Teen en s dre Ein a drea 34 Transmission State Shift Chart sse 35 Reception State Shift ennt 36 Error State Shift PER eir ee edades de aoa 37 Connection to the CAN innen rens 39 Transmit Message Definition Register TCON 46 Transmit Identifier Register entren nnns 47 Trarismit Data oia ieri crie roc reda i ei a T a ERU eet 48 Receive Identifier Control Register IDCON 51 Receive Status Bits Register DSTAT 52 Receive Identifier Register nennen ennt nnne nnns 54 Receive Data eec ob db en de dii ede de dare ey 55 Identifier Compare with nennen nennen nennen 58 Mask Identifier Control Register MCON c
7. 1 Only receive operation CAN does not activate transmit line Differences to CAN protocol in the receive only mode The mode never sends an acknowledge error frames or transmit messages The error counters do not count The VALID bit in CANESn register reports if the DCAN interface receives any valid message SAMPn defines the number of sample points per bit as specified in the ISO 11898 Bit Sampling Sample receive data one time at receive point Sample receive data three times and take majority decision at sample point SOFC works in conjunction with the SOFE and SOFSEL bits in the CAN Control Register CANCn For detailed information please refer to the bit description of that SFR register and the time function mode SOFC Start of Frame Control SOFE bit is independent from CAN bus activities SOFE bit will be cleared when a message for receive message 4 is received and SOF mode is selected Caution CPU can read SYNCOn SYNC1n register at any time Writing to the SYNCOn SYNCin registers is only allowed during initialization mode Any write to this register when INITn is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus 78 Preliminary User s Manual U14668EE3VOUMOO Chapter 15 Function Control 15 1 Transmit Control 15 1 1 Transmit Control Register This register controls the transmission of the DCAN module The transmit control registe
8. Bit Number Definition Overload flag Sent 6 bits dominant level continuously Overload flag A node that receives an overload flag in the interframe space from any node Issues an overload flag Sends 8 bits recessive level continuously In case of monitoring dominant level at 8th bit an overload frame is transmitted after the next bit Overload delimiter Output following the end of frame error delimiter and overload Any frame delimiter Interframe space Interframe space or overload frame continues overload frame Note The DCAN never needs to send an overload frame Preliminary User s Manual U14668EE3VOUMOO 25 26 Preliminary User s Manual U14668EE3VOUMOO Chapter 3 Function 3 1 Arbitration If two or more nodes happen to start transmission in coincidence the access conflict is solved by a bit wise arbitration mechanism during transmission of the ARBITRATION FIELD 1 When a node starts transmission During bus idle the node having the output data can transmit When more than one node starts transmission The node with the lower identifier wins the arbitration Any transmitting node compares its output arbitration field and the data level on the bus tlooses arbitration when it sends recessive level and reads dominant from bus Table 3 1 Arbitration Level Detection Status of Arbitrating Node Conformity of Level Continuous Transmission
9. NEC Preliminary User s Manual DCAN Macro Version B2 Document No U14668EE3VOUMO00 Date Published May 2002 NEC Corporation 2002 Printed in Germany NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field wnen exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low
10. disaster systems anti crime systems safety equipment and medical equipment not specifi cally designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Notes 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M5 2000 03 Preliminary User s Manual U14668EE3VOUMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers pow
11. is set showing a successful transfer of the data l e the abort request was not issued In all cases the TXRQx bit and the TXAx bit x 0 1 bit will be cleared at the end of the abort opera tion when the transmit buffer is available again Cautions 1 The bits are cleared when the INIT bit in CANCn register is set 2 Writing a 0 to TXAx x 0 1 bit has no influence 3 Do not perform read modify write operations on TCRn The TXCx bit x 0 1 are updated at the end of every frame transmission or abort TXRQx Transmission Request Flag Write no influence Read transmit buffer is free Write request transmission for buffer n Read transmit buffer is occupied by former transmit request The transmit request bits are checked by the DCAN immediately before the frame is started The order in which the TXRQx bit x 0 1 will be set does not matter as long as the first requested frame is not started on the bus The TXRQXx bit x 0 1 have dual function 1 Request the transmission of a transmit buffer 2 Inform the CPU whether a buffer is available or if it is still occupied by a former transmit request Setting the transmission request bit requests the DCAN to sent the buffer contents onto the bus The DCAN clears the bit after completion of the transmission Completion is either a normal transfer without error or an abort request 80 Preliminary User s Manual U14668EE3VOUMOO Chapter 1
12. 0 Normal operation 1 Overrun occurred during access to RAM The overrun condition is set whenever the CAN can not perform all RAM accesses that are necessary for comparing and storing received data or fetching transmitted data Typically the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate An error interrupt is generated at the same time The DCAN interface will work properly i e no overrun condition will occur with the following settings The DCAN clock as defined with the PRM bits in the BRPRSn register is set to a minimum of 16 times of the CAN baudrate and the selected CPU clock defined in the PCC register is set to a minimum of 16 times of the baudrate Possible reasons for an overrun condition are Too many messages are defined DMA access to RAM area is too slow compared to the CAN Baudrate The possible reactions of the DCAN differ depending on the situation when the overrun occurs Table 13 1 Possible Reactions of the DCAN Overrun Situation When detected DCAN Behavior The frame itself conforms to the CAN specification but its content is faulty Corrupted data or ID in Next data byte request from proto the frame col Immediate during the frame TXRQx bit x 0 1 is not cleared DCAN will retransmit the correct frame after synchroniza tion to the bus Cannot get transmit data Data in RAM is inconsistent No receive flags DN
13. 1 These registers define the CAN bit timing They define the length of one data bit on the CAN bus the position of the sample point during the bit timing and the synchronization jump width The range of resynchronization can be adapted to different CAN bus speeds or network characteristics Additionally some modes related to the baud rate can be selected in SYNC1n register SYNCOn and SYNC1n can be read or written with an 8 bit memory manipulation instruction Figure 14 2 Synchronization Control Registers 0 and 1 SYNCOn SYNC1n 0 1 Symbol 7 6 5 4 3 2 1 0 After Reset R W swwco SPrz seri sero bar pers Symbol ya 6 5 4 3 2 1 0 After Reset R W SYNC11 TLMODE SOFC RXONLY 8 1 sawo SPTS AW The length of a data bit time is programmable via DBT 4 0 Data Bit Time Other than under Setting prohibited 1 8x TQ 9xTQ 10x TQ 11xTQ 12xTQ 13x TQ 14xTQ 15x TQ 16x TQ 17xTQ 18x TQ 19x TQ 20x TQ 21x TQ 22x TQ 23x TQ 24x TQ 0 25x TQ Other than above Setting prohibited of of of of olol Of o 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 01 o o O O OF oO Ola o oF of Of Of O Of of of of of of Preliminary User s M
14. 2 Transmit Buffers Figure 1 1 Structural Block Diagram CANL CANH CPU Access Bus Arbitration Logic N Receive Messages CPU Memory Buffer Memory RAM Access Engine Interface Management High Speed RAM includes global registers CAN Transmit Buffers Protocol Time Stamp Signal 1 55 External Timer DCAN Interface _q Transceiver This interface part handles all protocol activities by hardware in the CAN protocol part The memory access engine fetches information for the CAN protocol transmission from the dedicated RAM area to the CAN protocol part or compares and sorts incoming information and stores it into predefined RAM areas The DCAN interfaces directly to the RAM area that is accessible by the DCAN and by the CPU The DCAN part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical characteristics of the CAN bus itself Preliminary User s Manual U14668EE3VOUMOO 13 14 Preliminary User s Manual U14668EE3VOUMOO Chapter 2 CAN Protocol CAN is an abbreviation of Controller Area Network and is a class C high speed multiplexed communi cation protocol CAN is specified by Bosch in the CAN specification 2 0 from September 1991 and is standardized in ISO 11898 International Organization for Standardization and SAE So
15. 49 IDCON Chapter 11 Receive Message Buffer Format Address Bit3 Bit2 Bit 1 Bit 0 DSTAT RO IDRECO ID standard part IDREC1 ID standard part 0 0 0 RTRREC Note2 IDREC2 ID extended part IDREC3 ID extended part IDREC4 ID extended part 0 0 0 unused DATAO Message data byte 0 DATA1 Message data byte 1 DATA2 Message data byte 2 DATA3 Message data byte 3 DATA4 Message data byte 4 DATAS Message data byte 5 DATA6 Message data byte 6 DATA7 Message data byte 7 Notes 1 50 r 02 to 11 address index for the 16 Receive Buffers see Chapter 7 page 43 itis relative offset to the start address of the receive buffer RTRREC is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the bytes IDRECO and IDREC1 for standard frame format and IDRECO to IDRECA for extended frame format For the RTRREC bit exist two modes RTR bit in the MCON byte of the dedicated mask is set to 0 In this case RTRREC will always be written to 0 together with the update of the IDn bits in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer RTR bit in the MCON byte of the dedicated mask is set to 1 data and remote frames are accepted In this
16. Non conformity of el The data output is stopped from the next bit and reception operation starts Priority of data frame and remote frame When a data frame and remote frame with the same message identifier are on the bus the data frame has priority because its RTR bit carries Dominant level The data frame wins the arbitration Preliminary User s Manual U14668EE3VOUMOO 27 Chapter 3 Function 3 2 Bit Stuffing When the same level continues for more than 5 bits bit stuffing insert 1 bit with inverse level takes place Due to this a resynchronization of the bit timing can be done at least every 10 bits Nodes detecting an error condition send an error frame violating the bit stuff rule and indicating this message to be erroneous for all nodes Table 3 2 Bit Stuffing During the transmission of a data frame and a remote frame when the same level continues Transmission for 5 bits in the data between the start of frame and the ACK field 1 bit level with reverse level of data is inserted before the following bit During the reception of a data frame and a remote frame when the same level continues for Reception 5 bits in the data between the start of frame and the ACK field the reception is continued by deleting the next bit 3 3 Multi Master As the bus priority is determined by the identifier any node can be the bus master 3 4 Multi Cast Any message can be received by any node broadcast 3
17. Receive with Interrupt Software Flow ssssssseseseeeeenneren enne 99 Preliminary User s Manual U14668EE3VOUMOO 9 Figure 18 6 Figure 18 7 10 Receive Software PollinG e Receive Software Polling in case of Data New Flag Limitation Preliminary User s Manual U14668EE3VOUMOO Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 12 1 Table 13 1 Table 15 1 Table 16 1 List of Tables Bit Number of the Identifier piion ennt nnne 19 RIR Setting 2 2 eed acu ee A sd 19 Mode Setting RM 19 Data Length Code Setting 20 Operation in the Error State 23 Definition of each Field rece naren 24 Definition of each Frame nennen trn nnn nnns 25 AIDItEatiODr teme eee opes WL ae kei id le as 27 Bit tuff EE 28 Error E 29 Output Timing of the Error Frame cccececeeeeeeeeeeneeeeeeeeeeaaeeseneeesaeeeseaaeeeceeeeesaeenennees 29 Types ol Error eire ente ize eme La ple pb Ee oo os 30 Error Counter
18. User s Manual U14668EE3VOUMO00 93 94 Preliminary User s Manual U14668EE3VOUMOO Chapter 18 Functional Description by Flowcharts 18 1 Initialization Figure 18 1 Initialization Flow Chart RESET Software Init set INIT 1 in CANC H set BRPRS SYNCO 1 Initilialize message and mask data Write for BRPRS Clear INIT 0 in CANC SYNCO MONT MASKC is now disabled End Initialization Preliminary User s Manual U14668EE3VOUMOO 95 Chapter 18 Functional Description by Flowcharts 18 2 Transmit Preparation Figure 18 2 Transmit Preparation Transmit Wait or 1 Abort or Try other Buffer 0 Write data Select Priority TXP End Transmit 96 Preliminary User s Manual U14668EE3VOUMOO Chapter 18 Functional Description by Flowcharts 18 3 Abort Transmit Figure 18 3 Transmit Abort Transmission Abort Transmit Transmit was successful was aborted before ABORT End Transmission Abort Preliminary User s Manual U14668EE3VOUMOO 97 Chapter 18 Functional Description by Flowcharts 18 4 Handling by the DCAN 98 Figure 18 4 Handling of Semaphore Bits by DCAN Module Data Storage Warns that data will be changed Only for buffers that are declared for mask operation Identifier bytes Data is changed MUC 0 signals stable data End Data Storage Preliminary User s Manual U14668EE3VOUMOO Chapter 18 Functiona
19. address index for the 2 mask buffers see Chapter 7 page 43 MIDn Mask Identifier Bit n 0 28 0 Check IDn bit in IDRECO through IDREC4 of received message 1 Receive message independent from IDn bit 60 Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the Controller 13 1 Control Register DCANCn Depending on the integration of the DCAN into particular products there exists a DCAN Control regis ter DCANOCn that enables or disables channel DCANOn can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 13 1 DCAN Control Register DCANCn n 0 1 Symbol 7 6 5 4 3 2 1 0 After Reset R R R R R R R R W R R R R R R R R W DCANENn accessing data RAM operation 0 Disable accessing data RAM operation 1 Enable accessing data RAM operation Preliminary User s Manual U14668EE3VOUMOO 61 Chapter 13 Operation of the Controller 13 2 CAN Control Register CANCn The operational modes are controlled via the CAN control register CANCn CANOn can be set with a 1 bit or an 8 bit memory manipulation instruction For bit numbers in brackets a bit access is provided Figure 13 2 CAN Control Register CANCn 0 1 Symbol 7 lt 4 gt lt 2 gt lt 0 gt After Reset R W R W R W R W R W R W R W R W R W R W INIT Request status for operational modes 0 Normal operation Initialization mode Th
20. byte 5 Message data byte 6 Message data byte 7 Remark t 00 01 address index for the 2 transmit buffers Note This address is a relative offset to the starting address of the transmit buffer see Chapter 7 page 43 Preliminary User s Manual U14668EE3VOUMOO 45 Chapter 9 Transmit Message Buffer Format 9 1 Transmit Message Definition The memory location labelled TCON includes the information of the RTR bit and the bits of the control field of a data or remote frame TCON is set with a 1 bit or an 8 bit memory manipulation instruction Figure 9 1 Transmit Message Definition Register TCON Address offsetNote Note t 00 01 address index for the 2 transmit buffers see Chapter 7 page 43 Symbol 7 6 5 4 3 2 1 After Reset R W IDE Identifier Extension Select 0 Transmit standard frame message 11 bit identifier 1 Transmit extended frame message 29 bit identifier RTR Remote Transmission Select 0 Transmit data frames 1 Transmit remote frames Data Length Code Selection of Transmit MessageNote 0 data bytes 1 data bytes 2 data bytes 3 data bytes 4 data bytes 5 data bytes 6 data bytes 7 data bytes 0 8 data bytes Others than above Note Remark The control field describes the format of frame that is generated and its length The reserved bits of the CAN protocol are always sent in dominant state 0 Note The data length code selec
21. case the RTR bit in IDCON has no meaning The received mes sage type passed the mask is shown in RTRREC If a buffer is not assigned to a mask function mask 1 mask 2 or global mask the bytes IDRECO to IDREC4 are only read for comparing During initialization the RTRREC should be defined to O Preliminary User s Manual U14668EE3VOUMOO Chapter 11 Receive Message Buffer Format 11 1 Receive Control Bits Definition The memory location labelled IDCON defines the kind of frame data or remote frame with standard or extended format that is monitored for the associated buffer Notification by the receive interrupt upon successful reception can be selected for each receive buffer separately IDCON can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 11 1 Receive Identifier Control Register IDCON Address offsetNote After Reset R W Note 02 11 address index for the 16 Receive Buffers see Chapter 7 page 43 Symbol 7 6 5 4 3 2 1 EH Enable Interrupt on ReceiveNete No interrupt generated Generate receive interrupt after reception of valid message Eug Remote Transmission Select Receive data frames Receive remote frames IDE Identifier Extension Select Receive standard frame message 11 bit identifier Receive extended frame message 29 bit identifier The control bits define the type of message that is transferred in the associated buffer if this type of message appear
22. country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of 02 05 2002 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the fu
23. message buffer with an identifier mask combination fits to the received frame The memory access engine successfully stored data in the message buffer The message buffer is marked for interrupt generation with ENI bit set The receive interrupt can be generated as late as at the 7th bit of a directly following frame due to the store operation for the received message Preliminary User s Manual U14668EESVOUMOO 89 Chapter 16 Interrupt Information 16 4 Error Interrupt The error interrupt is generated when any of the following conditions are fulfilled Transmission error counter reaches or leaves bus off state i e BOFF bit of CANESn register changes its state Transmission error counter status TECS bit of CANESn register changes its state Reception error counter status RECS bit of CANESn register changes its state Overrun during RAM access OVER bit of CANESn register becomes active The wake up condition WAKE bit of CANESn register becomes active The wake up condition activates an internal signal to the interrupt controller In order to receive further error interrupts generated by other conditions the CPU needs to clear the WAKE bit in CANES register every time a wake up condition was recognized No further interrupt can be detected by the CPU as long as the WAKE bit is set 90 Preliminary User s Manual U14668EE3VOUMOO Chapter 17 Power Saving Modes 17 1 CPU Halt Mode The CPU halt mode is possible in conjunct
24. only Even when the slowest speed for the access is selected the DCAN operates correctly 88 Preliminary User s Manual U14668EE3VOUMOO Chapter 16 Interrupt Information 16 1 Interrupt Vectors Each instance of the DCAN macro supports four interrupt sources as shown in the following table Table 16 1 Interrupt Sources Function Source Error counter states Bus off RX and TX warning level Error Interrupt Overrun error Wake up Receive Interrupt Received frame is valid and has been stored Transmit Interrupt 0 TXRQO is clearedNote Transmit Interrupt 1 TXRQ1 is clearedNote Note Some products provide only one interrupt vector for both transmit interrupt sources 16 2 Transmit Interrupt The transmit interrupt is generated when all following conditions are fulfilled The transmit interrupt 0 is generated when TXRQO bit is cleared The transmit interrupt 1 is generated when TXRQ1 bit is cleared Clearing of these bits releases the buffer for writing a new message into it This event can occur due to a successful transmission or due to an abort of a transmission Only the DCAN can clear this bit The CPU can only request to clear the TXRQXx bit by setting the TXAx bit x 0 1 16 3 Receive Interrupt The receive interrupt is generated when all of the following conditions are fulfilled CAN protocol part marks received frame valid The received frame passes the acceptance filter In other words a
25. only difference is that the DCAN Stop mode prevents the wake up by CAN bus activity Caution The DCAN Sleep or DCAN Stop mode can not be requested as long as the WAKE bit in CANES is set The DCAN Sleep mode is cancelled under following conditions 8 CPU clears the SLEEP bit b Any transition while idle state on CAN bus STOP 0 C CPU sets SLEEP but CAN protocol is active due to bus activity The WAKE bit in CANESn is set under condition b and c SOFSEL Start of Frame Output Function Select 0 Last bit of EOF is used to generate the time stamp 1 SOF is used to generate the time stamp Start of Frame Enable 0 SOFOUT does not change 1 SOFOUT toggles depending on the selected mode Preliminary User s Manual U14668EESVOUMOO 63 Chapter 13 Operation of the Controller Figure 13 3 DCAN Time Stamp Support Data CRC EOF Q SOFOUT Capture Register pepee ong SOFSEL SOFE o3 n5 Clear SOFC DCAN 16 Bit Timer The generation of an SOFOUT signal can be used for time measurements and for global time base syn chronisation of different CAN nodes as a prerequisite for time triggered communication SOFSEL SOFOUT Function Time stamp function disabled Toggles with each EOF Toggles with each start of frame on the CAN Bus
26. wake up interrupt _5 enter CPU Stop mode NOP Note NOP NOP EI enable interrupts sri resume with application code Note The interrupt acknowledge needs some clock cycles depends on host core In order to prevent that the variable wakeup interrupt occurred is already read before DI becomes effective some NOP instruction have to be inserted As well the number of NOP instructions after the CPU Stop instruction is dependent on the host core The given example is tailored for 78KO 92 Preliminary User s Manual U14668EE3VOUMOO Chapter 17 Power Saving Modes 17 5 DCAN Stop Mode The CPU requests this mode from DCAN The procedure equals the request for DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the DCAN Stop mode due to ongoing bus activities After a successful switch to the DCAN Stop mode the CPU can safely go into halt watch or stop mode without any precautions The DCAN can only be woken up by the CPU Therefore the CPU needs to clear the SLEEP bit in the CANCn register This mode reduces the power consumption of the DCAN to a minimum Code example DCAN_Stop_Mode void CANES 0x02 clear Wake bit CANC 0x06 request DCAN Stop mode while CANES amp 0x02 check if DCAN Stop mode was accepted CANES 0x02 try again to get DCAN into stop mode CANC 0x06 Preliminary
27. 5 Function Control An error during the transmission does not influence the transmit request status The DCAN will auto matically retry the transfer Cautions 1 The bits are cleared when the INIT bit in CANCn is set A transmission already started will be finished but not retransmitted in case of an error Writing a 0 to TXRQO bit has no influence Do not use bit operations on this register Do not change data in transmit buffer when the corresponding TXRQ bit is set Preliminary User s Manual U14668EE3VOUMOO 81 Chapter 15 Function Control 15 2 Receive Control The receive message register mirrors the current status of the first 8 receive buffers Each buffer has one status bit in this register This bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer The CPU can easily find the last received message during receive interrupt handling The bits in this register always correspond to the DN bit in the data buffers They are cleared when the CPU clears the DNn bit in the data buffer The register itself is read only 15 2 1 Receive Message Register This register shows receptions of messages of the DCAN module More than one bit set is possible RMESn can be read with a 1 bit or an 8 bit memory manipulation instruction Figure 15 2 Receive Message Register RMESn n 0 1 Symbol 7 6 5 4 3 2 1 0 After Reset R R R R R R R R R R R R R R R R This register is read only a
28. 5 Sleep Mode Stop Function This is a function to put the CAN controller in waiting mode to achieve low power consumption The SLEEP mode of the DCAN complies to the method described in ISO 11898 Additional to this SLEEP mode which can be woken up by bus activities the STOP mode is fully con trolled by the CPU device 28 Preliminary User s Manual U14668EE3VOUMOO 3 6 Error Control Function 1 Error types Chapter 3 Function Table 3 3 Error Types Description of Error Detection State Detection Method Comparison of output level and level on the bus except stuff bit Bit error Detection Condition Disagreement of both levels Transmission Reception Transmission reception node Field Frame Bit that output data on the bus at the start of frame to the end of frame error frame and overload frame Check of the reception Stuff error Jata at the stuff bit 6 consecutive bits of the same output level Transmission reception node Start of frame to CRC sequence Comparison of the CRC generated from the reception data and the received CRC sequence CRC error Disagreement of CRC Reception node Start of frame to data field Field frame check of the fixed format Detection of the fixed for mat error Reception node CRC delimiter ACK field End of frame Error frame Overload frame Check of the ACK slot by ACK error the transmission node Detectio
29. 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 4 1 Figure 9 1 Figure 9 2 Figure 9 3 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 12 1 Figure 12 2 Figure 12 3 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 13 9 Figure 13 10 Figure 13 11 Figure 14 1 Figure 14 2 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 List of Figures Structural Block Diagram sss eene 13 Data Frame ai ie ea eee epa Cage un 17 Remote Frame eta RU TRE Be ir d Eee fetal 17 Data Frame i uui eU dde Hg es A re HD EHE BU ed dg lt e eR Le d 18 Arbitration Field Standard Format Mode cccccecceceeeeeeseeeesecaeeeseaeeeeeeeesaaeeeeeeeees 18 Arbitration Field Extended Format Mode see eene 19 Control Field Standard Format nens 20 Control Field Extended Format Mode 20 21 GRG Eield 2 tri Cuv ae 21 ACK Riella nate eligi etter 22 End of Frameyis ania nein A en in tea 22 Interframe Space Error Active
30. HT and AL are not available on older macro versions When not avail able these bits read 0 and writing to them has no effect Caution This register is readable at any time Writing to the MASKCn register is only allowed during initialization mode Any write to this register when INITn is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus MSKO Mask 0 Enable 0 Receive buffer 0 and 1 in normal operation 1 Receive buffer 0 is mask for buffer 1 MSK1 Mask 1 Enable 0 Receive buffer 2 and 3 in normal operation 1 F Receive buffer 2 is mask for buffer 3 GLOBAL Enable Global Mask Normal operation 0 1 Highest defined mask is active for all following buffers Preliminary User s Manual U14668EE3VOUMOO 83 Chapter 15 Function Control Function Single shot mode disabled Single shot mode enabled no re transmission when an error occurs Transmit message will not be queued for a second transmit request when the arbitration was lost Single shot mode enabled no re transmission when an error occurs Transmit message will be queued for a second transmit request when the arbitration was lost for TLMODE 0 See Setting of BRPRSx x 7 to 0 for TLMODE 1 on page 74 for TLMODE 1 The following table shows which compare takes place for the different receive buffers The ID in this table alway
31. Q per bit Therefore the overall prescaler value realized by BRPRSn is 2 or 1 respectively With TLMODE 0 the following register settings apply Register value Description Bit fields BRPRSn 00h Clock selector fx PRMn 00b BRPRSx 000000b SYNCOn A7h CAN Bit in TQ 2 8 DBTx 00111b 7 fx Baudrate bit rate prescaler 25 SYNC1n 0zzz0100b sample point 75 6 TQ SPTx 00101b SJW 25 2 2 TQ SJWy 01b 1 TQ equals 2 clocks amp BRPRS6 7 are disabled TLMODE 0 z depends on the setting of Number of sampling points Receive only function Use of time stamp or global time system Preliminary User s Manual U14668EE3VOUMOO 77 Chapter 14 Baud Rate Generation With TLMODE 1 the following register settings apply Register values Description Bit fields BRPRSn 00h Clock selector fx PRMn 00b MASKCn 00xx xxxxb BRPRSn 0000 00006 SYNCOn 6Fh CAN Bit in TQ 16 DBTn 01111b 7 fx Baudrate bit rate prescaler 25 SYNC1n 1zzz 11010 sample point 75 12 TQ SPTn 01011b SJW 2596 2 4 TQ SJWn 11b 1 TQ equals 1 clock BRPRS 6 7 are enabled TLMODE 1 z depends on the setting of Number of sampling points Receive only function Use of time stamp or global time system The receive only mode can be used for baud rate detection Different baud rate configurations can be tested without disturbing other CAN nodes on the bus RXONLY Receive Only Operation 0 Normal operation
32. Unused Unused Unused Unused Unused Unused Unused Unused Note m 2 4 address index for the 2 mask buffers see Chapter 7 page 43 Receive message buffer 0 and 2 can be switched for masked operation with the mask control register MASKCn In this case the message does not hold message identifier and data of the frame Instead it holds identifier and RTR mask information for compare operations for the next higher message buffer number In case the global mask is selected it keeps mask information for all higher message buffer numbers A mask does not store any information about identifier length The same mask can therefore be used for both types of frames standard and extended during global mask operation All unused bytes can be used by the CPU for application needs Preliminary User s Manual U14668EE3VOUMOO 57 Chapter 12 Mask Function 12 1 Identifier Compare with Mask The identifier compare with mask provides the possibility to exclude some bits from the comparison process That means each bit is ignored when the corresponding bit in the mask definition is set to one The setup of the mask control register MASKCn defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison The mask does not include any information about the identifier type to be masked This has to be defined within the dedicated receive buffer Therefore a global
33. ag Error flag Nodes receiving an error flag detect bit stuff errors and issue error superpositioning flags themselves Sends 8 bits recessive level continuously Error delimiter In case of monitoring dominant level at 8th bit an overload frame is transmitted after the next bit An error frame is transmitted continuously after the bit where the error Erroneous bit has occurred in case of a CRC error transmission continues after the ACK delimiter Interframe space Interframe space or overload frame continues overload frame 24 Preliminary User s Manual U14668EE3VOUMOO Chapter 2 Protocol 2 5 Overload Frame This frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception When a bit error is detected in the intermission also an overload frame is sent following the next bit after the bit error detection e Detecting a dominant bit during the 3 bit of intermission will be interpreted as START OF FRAME At most two OVERLOAD FRAMEs may be generated to delay the next DATA FRAME or REMOTE FRAMENete Figure 2 15 Overload Frame 41 Overload frame EN amp OD Interframe space or overload frame Overload delimiter Overload flag superpositioning Node n Overload flag Node m Each frame Table 2 7 Definition of each Frame
34. age Buffer Format 11 3 Receive Identifier Definition These memory locations define the receive identifier of the arbitration field of the CAN protocol IDRECO to IDREC4 can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 11 3 Receive Identifier Register Symbol 7 6 5 4 3 2 1 After Reset R W IDRECO 1 28 1027 1026 1025 1 24 1023 1 22 1 21 I2H undefined R W IDREC1 1 20 1 19 1 18 0 0 0 RTRaec 13H undefined R W IpREC2 1 17 1016 1015 ID14 ID13 1 12 IDt1 IDiO undefined R W ipREC4 Ibi o o o o undefined Rw Note 02 11 address index for the 16 Receive Buffers see Chapter 7 page 43 The identifier of the receive message has to be defined during the initialization of the DCAN The DCAN uses this data for the comparison with the identifiers received on the CAN bus For normal message buffers without mask function this data is only read by the DCAN for comparison In combina tion with a mask function this data is overwritten by the received ID that has passed the mask The identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the RDEF register because the change of the contents can happen at the same time when the DCAN uses the data for comparison This can cause inconsistent data stored in this buffer and a
35. and MUC bit may be set in message Data storage is ongoing during the Cannot store receive data six bit of the next frame ID compare is ongoing during six Message is not received and its bits of next frame data is lost Cannot get data for ID comparison Preliminary User s Manual U14668EE3VOUMOO 69 Chapter 13 Operation of the Controller 13 4 CAN Transmit Error Counter This register shows the transmit error counter TECn register can be read with an 8 bit memory manipulation instruction Figure 13 9 Transmit Error Counter Register TECn n 0 1 Symbol 7 6 3 2 1 0 After Reset 5 4 R R R R R R R R R R R R R R R R The transmit error counters reflects the status of the error counter for transmission errors as it is defined in the CAN protocol according ISO 11898 13 5 CAN Receive Error Counter This register shows the receive error counter RECn can be read with an 8 bit memory manipulation instruction Figure 13 10 Receive Error Counter Register RECn n 0 1 Symbol 7 6 5 3 2 1 0 After Reset 4 R R R R R R R R R R R R R R R R The receive error counters reflects the status of the error counter for reception errors as it is defined in ISO 11898 70 Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the Controller 13 6 Message Count Register With this register the number of receive message buffers is defined Automatically the RAM area of the receive mes
36. anual U14668EE3VOUMOO 75 Chapter 14 Baud Rate Generation The position of the sample point within the bit timing is defined by SPTOn through SPT4n ther than under Sample Point Position Setting prohibited 0 2xTQ 3xTQ 4xTQ 5xTQ 6x TQ 7xTQ 8x TQ 9x TQ 10x TQ 11x TQ 12x TQ 13x TQ 14x TQ 15x TQ o o ol ol ol 16 x TQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Ol o o o o ol ol o 0 Ol o O o OF o oj o ajloj OL O O OF O O 17 x TQ Other than above Setting prohibited For the DCAN version B2 the bit rate prescaler is improved compared to previous versions To be com patible with older DCAN versions an additional mode was implemented that can be selected with the TLMODE bit TLMODE Resolution of Bit Rate Prescaler 1 unit of BRPRS 5 0 in BRPRS register equals 2 DCAN clocks BRPRS 7 6 in MASKC register are disabled compatible to older macro versions 1 unit of BRPRS 7 0 in BRPRS and MASKC register equals 2 DCAN clocks BRPRS 7 6 in MASKC register are enabledNete Note The user needs to assure that phase segment 2 TSEG2 consists of at least 3 TQ when using this setting Phase segment 2 is given by the difference of DBT SPT each measured in units of TQ SJWO0 SJW1 d
37. anual U14668EE3VOUMOO 101 102 Preliminary User s Manual U14668EE3VOUMOO Although NEC has taken all possible steps SSag to ensure thatthe documentation supplied to our customers is complete bug free From and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may Name encounter problems inthe documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 465 250 3583 Fax 1 800 729 9288 1 408 588 6130 NOE tronics Hong Kong Ltd us iconductor Technical ectronics Hong Kong Ltd emiconductor Technical Hotline Europo GMBH Fax 81 44 435 9608 Market Communication Dept Fax 482 2 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 455 11 6462 6829 Fax 886 2 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excell
38. ata frame and remote frame are indicated Figure 2 3 Data Frame Interframe space Start of frame Arbitration field on bus idle i a R D 1 bit The start of frame SOF is denoted by the falling edge of the bus signal Reception continues when Dominant level is detected at the sample point The bus becomes idle state when Recessive level is detected at a sample point 2 Arbitration field Sets priority specifies data frame or remote frame and defines the protocol mode Figure 2 4 Arbitration Field Standard Format Mode a Arbitration field T Control field R Identifier 28 ID 41 bits 1 bit 1 bit 18 Preliminary User s Manual U14668EE3VOUMOO 2 Protocol Figure 2 5 Arbitration Field Extended Format Mode Arbitration field T Control field Identifier ID17 IDO i8bitsy Identifier 1028 1018 11 bits 1 bit 1 bit ID28 IDO is the identifier The identifier is transmitted with MSB at first position Substitute Remote Request SRR is only used in extended format mode and is always recessive Table 2 1 Bit Number of the Identifier Protocol Mode Identifier Standard format mode 11 bits Extended format mode 29 bits Table 2 2 RTR Setting Frame Type RTR Bit Data frame 0 Remote frame 1 Table 2 3 Mode Setting Protocol Mode IDE Bit Standard format mode 0 Extended format m
39. by using a pull up or pull down circuitry Each unused pin should be connected Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 2 Preliminary User s Manual U14668EE3VOUMOO MS DOS and MS Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT and PC DOS are trademarks of IBM Corp The related documents in this publication may include preliminary versions However preliminary versions are not marked as such The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by th customer The export or re export of this product from a
40. ccsceeeeeeeeeeeeeeeeeeceeeeeeaaeeeeeeeeesaeeneeees 59 Mask Identifier Register MREC sssssssssssseseeeenee eene nnne 60 Control Register DCANCn n 0 1 61 CAN Control Register n 0 1 62 Time Stamp 64 Time Stamp FUNCUON icp cet nido ote dance ete drop 65 SOFOUT Toggle Function 0 niekis ed ei in deeded et 65 Global Time System Function 65 Transmission Reception Flag sess nnns 66 Error Status Register CANESn n 0 1 67 Transmit Error Counter Register TECn n 0 1 70 Receive Error Counter Register RECn n 0 1 70 Message Count Register MCNTn n 0 1 71 Bit Rate Prescaler Register BRPRSn 0 1 73 Synchronization Control Registers 0 and 1 SYNCOn SYNC1n n20 1 75 Transmit Control Register TCRn n 0 1 79 Receive Message Register RMESn n 0 1 82 Mask Control Register MASKCn n 0 1 83 Redefinition Control Register REDEFn n 0 1 86 Initialization Flow Chart 95 Transmit 96 Transmit AVO ott ite eite cr Pese eet eit 97 Handling of Semaphore Bits by DCAN Module sse 98
41. ceive buffer 2 Mask 1 050H to 05FH Receive buffer 3 060H to O6FH Receive buffer 4 070H to 07FH Receive buffer 5 080H to 08FH Receive buffer 6 090H to O9FH Receive buffer 7 to OAFH Receive buffer 8 OBOH to OBFH Receive buffer 9 0 to OCFH Receive buffer 10 ODOH to ODFH Receive buffer 11 OEOH to OEFH Receive buffer 12 OFOH to OFFH Receive buffer 13 100H to 10FH Receive buffer 14 110H to 11FH Receive buffer 15 Address Offset Note 2 Register Name After Reset undefinedNotet Contents is undefined because data resides in normal RAM area 2 This address is an offset to the RAM area starting address which is fixed Depending on the Preliminary User s Manual U14668EE3VOUMOO product the offset address is selectable by the CADDx bits x 0 1 in the message count register s MCNTn or the offset is fixed by the design of the hardware and the setting of CADDx in MCNTn has no influence Some products feature 14 receive buffers only 43 Chapter 8 Transmit Buffer Structure Each DCAN channel has 2 independent transmit buffers The two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message The structure of the transmit buffer is similar to the structure of the receive buffers The CPU can use addresses that are specified as unused in the trans
42. ciety of Auto motive Engineers 2 1 Protocol Mode Function 1 Standard format mode This mode supports an 11 bit message identifier thus making it possible to differentiate between 2048 types of messages 2 Extended format mode n the extended format mode the identifier has 29 bits It is built by the standard identifier 11 bits and an extended identifier 18 bits When the IDE bits of the arbitration field is recessive the frame is sent in the extended format mode When a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted the node transmitting the message with the standard mode wins the arbitration 3 Bus values The bus can have one of two complementary logical values dominant or recessive During simultaneous transmission of dominant and recessive bits the resulting bus value will be dominant non destructive arbitration For example in case of a wired AND implementation of the bus the dominant level would be represented by a logical 0 and the recessive level by a logical 1 This specific representation is used in this manual Physical states e g electrical voltage light that represent the logical levels are not given in this document Preliminary User s Manual U14668EE3VOUMOO 15 2 2 Message Format Chapter 2 CAN Protocol The CAN protocol message supports different types of frames The types of frames are liste
43. d below 16 Data frame Remote frame Error frame Overload frame Carries the data from a transmitter to the receiver Transmission demand frame from the requesting node Frame sent on error detection Frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it The reception side did not finish its operations on the reception of the previously received frame yet Preliminary User s Manual U14668EE3VOUMOO Chapter 2 Protocol 2 3 Data Frame Remote Frame Figure 2 1 Data Frame Data frame 11 1 R p 29 3 6 0 64 16 2 7 3 D 0 Q9 O A A A A A Bus idle Interframe space End of frame ACK field CRC field Data field Control field Arbitration field Start of frame Figure 2 2 Remote Frame Remote frame R D A A A A Bus idle Interframe space End of frame ACK field CRC field Control field Arbitration field Start of frame Remark This frame is transmitted when the reception node requests transmission Data field is not transmitted even if the data length code 0 in the control field Preliminary User s Manual U14668EE3VOUMOO 17 2 Protocol 2 3 1 Description of each field 1 R indicates recessive level indicates dominant level Start of frame The start of d
44. e INIT is the request bit to control the DCAN INIT starts and stops the CAN protocol activities Due to bus activities disabling the DCAN is not allowed any time Therefore changing the INIT bit must not have an immediate effect to the CAN protocol activities Setting the INIT bit is a request only The INITSTAT bit in the CANESn register reflects if the request has been granted The registers MCNTn SYNCOn SYNC1n and MASKCn are write protected while INIT is cleared independently of INITSTAT Any write to these registers when INIT is set and the initialisation mode is not confirmed by the INITSTAT bit can have unexpected behaviour to the CAN bus STOP Stop Mode Selection Normal sleep operation Sleep mode is released when a tran sition on the CAN bus is detected Stop operation Sleep mode is cancelled only by CPU access No wake up from CAN bus Sleep Stop Request for CAN protocol Normal operation CAN protocol goes to sleep or stop mode depending on STOP bit Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the Controller The clock supply to the DCAN is switched off during initialisation DCAN Sleep and DCAN Stop mode All modes are only accepted while CAN protocol is in idle state whereby the CRXD pin must be reces sive high level A sleep or stop request out of idle state is rejected and the WAKE bit in CANES is set DCAN Sleep and DCAN Stop mode can be requested in the same manner The
45. e buffers depends on its type defined by the setup of the mask register in first place and its number in second place The rules for priority are All non masked receive buffers have a higher priority than the masked receive buffer Lower numbered receive buffers have higher priority Examples 1 All RX buffers are enabled to receive the same standard identifier OX7FFH Result the message with identifier OX7FFh is stored in RXO 2 In difference to the previous set up the mask option is set for RX2 Again the message Ox7FFH is stored in buffer in RXO 3 If additionally RXO is configured as a mask the message will be stored in RX4 Preliminary User s Manual U14668EE3VOUMOO 85 Chapter 15 Function Control 15 4 Special Functions 15 4 1 Redefinition Control Register This register controls the redefinition of an identifier of a received buffer REDEFn can be written with an 1 bit or an 8 bit memory manipulation instruction Figure 15 4 Redefinition Control Register REDEFn n 0 1 Symbol 7 2 1 0 After Reset R W R W R W R W R W Symbol 7 2 1 0 After Reset R W R W R W R W R W The redefinition register provides a way to change identifiers and other control information for one receive buffer without disturbing the operation of the other buffers DEF Redefine Permission Bit Normal operation Receive operation for selected message is disabled CPU can change definition data for this message This bit is cl
46. e is in error active state 8 Bit error detection during active error flag and overload flag when receiving node is in error active state No change 8 When the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the over load flag and every time eight subsequent dominant bits after that are detected Every time when the node detects eight continuous dominant bits after the passive error flag When the transmitting node has completed to sent without error 1 0 when error counter 0 No change When the reception node has completed to receive without error c Overload frame No change 1 1 REC lt 127 0 REC 0 119 127 REC 127 n case the recessive level of first intermission bit is driven to dominant level an overload frame occurs on the bus Upon detection of an overload frame any transmit request will be postponed until the bus becomes idle Preliminary User s Manual U14668EE3VOUMOO 31 Chapter 3 Function 3 7 Baud Rate Control Function 1 Nominal bit time 8 to 25 time quanta Definition of 1 data bit time is as follows Figure 3 1 Nominal Bit Time 8 to 25 Time Quanta Nominal bit time Sync Prop Phase segment segment segment 1 HEN bon Sample point 1 Minimum time for one time quantum TQ 1 fx Sync segment In this segment the bit synchronizati
47. ead this Manual Legend Preliminary User s Manual U14668EE3VOUMOO Introduction This manual has been prepared for engineers who want to understand the functions of the DCAN Macro and design and develop its application systems and programs This manual is intended for users to understand the functions described in the Organization below The DCAN Macro manual is separated into two parts an explanation of the CAN protocol and a detailed description of the DCAN macro Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers When you want to have an introduction to the CAN protocol and want to understand the function of the DCAN Read this manual in the order of the contents When you have a good command on the CAN protocol and want only to understand the DCAN function Start reading from Chapter 4 onwards Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXXX or Decimal XXxx Hexadecimal XXXxH or Ox Xxxx Prefixes representing pow
48. eared when INIT bit in CANC is set 86 Preliminary User s Manual U14668EE3VOUMOO Chapter 15 Function Control Buffer selection n 0 15 Buffer 0 is selected for redefinition Buffer 1 is selected for redefinition Buffer 2 is selected for redefinition Buffer 3 is selected for redefinition Buffer 4 is selected for redefinition Buffer 5 is selected for redefinition Buffer 6 is selected for redefinition Buffer 7 is selected for redefinition Buffer 8 is selected for redefinition Buffer 9 is selected for redefinition Buffer 10 is selected for redefinition Buffer 11 is selected for redefinition Buffer 12 is selected for redefinition Buffer 13 is selected for redefinition Buffer 14 is selected for redefinition Buffer 15 is selected for redefinition Other than above Setting prohibited Cautions 1 Keep special programming sequence Failing to do so can cause inconsistent data or loss of receive data 2 Do not change DEF bit and SELx bit x 3 to 0 at the same time Change SELx bit x 3 to 0 only when DEF bit is cleared 3 Write first SELxn x 3 to 0 with DEFn cleared Write than SELxn x 3 to 0 with DEF bit or use bit manipulation instruction Only clear DEF bit by keeping SELx bit x 3 to 0 or use bit manipulation instruction Setting the redefinition bit removes the selected receive buffer from the list of possible ID hits durin
49. efine the synchronization jump width as specified in ISO 11898 Synchronisation Jump Width 76 Preliminary User s Manual U14668EE3VOUMOO Chapter 14 Baud Rate Generation Limits on defining the bit timing The sample point position needs to be programmed between 3TQN 17TQ which equals a register value of 2 lt SPTxn lt 16 n 0 1 x 4 to 0 The number of TQ per bit is restricted to the range from 8TQ to 25TQ which equals a register value of 7 x DBTxn lt 24 0 1 x 4 to 0 The length of phase segment 2 TSEG2 in TQ is given by the difference of TQ per bit DBTxn and the sample point position SPTxn Converted to register values the following condition applies 2 lt DBTxn SPTxn lt 8 n 0 1 x A to 0 The number of TQ allocated for soft synchronization must not exceed the number of TQ for phase segment 2 but SJWyn may have as many TQ as phase segment 2 SJWyn x DBTxn SPTxn 1 n 0 1 x 4 to 0 y 0 1 Note Sample point positions of 3 TQ or 4 TQ are for test purposes only For the minimum number of TQ per bit time 8TQ the minimum sample point position is 5 TQ Example System clock fx 8 MHz CAN parameter Baud rate 500 kBaud Sample Point 75 SJW 2596 At first calculate the overall prescaler value fy 8 MHz Baudrate 500 KBaud 16 can be split as 1 x 16 or 2 x 8 Other factors can not be mapped to the registers Only 8 and 16 are valid values for T
50. egister Register Name DCAN control register MASKCO DCANC1 Bit Manipulation Units 1 Bit 8 Bit 16 Bit After Reset CAN control register CANC1 Transmit control register TCR1 Receive message register RMES1 Redefinition control register REDEF1 DCAN error status register CANES1 Transmit error counter TEC1 Receive error counter REC1 Message count register MCNT1 Bit rate prescaler BRPRS1 Synchronous control register 0 SYNCO 1 Synchronous control register 1 SYNC11 Mask control register The registers DCANCn are not available on every host CPU Preliminary User s Manual U14668EE3VOUMOO MASKC1 41 Chapter 6 Special Function Register for DCAN module The following SFR bits can be accessed with 1 bit instructions The other SFR registers have to be accessed with 8 bit instructions 42 DCANEN Description Enable Disable DCANn DCANCn 0 SOFE Start of frame enable CANCn 4 SLEEP Sleep mode CANCn 2 INIT Initialize CANCn 0 DEF Redefinition enable REDEFn 7 Preliminary User s Manual U14668EE3VOUMOO Notes 1 Chapter 7 Message Buffer Configuration 000H to OOFH Transmit buffer 0 010H to 01FH Transmit buffer 1 020H to 02FH Receive buffer 0 Mask 0 030H to Receive buffer 1 040H to 04FH Re
51. ei e tie qudd use tai doute 31 Segment Name and Segment Length ssssssssssseeeeeneenne 32 Mask Function Register 57 Possible Reactions of the 69 Mask Operation BUffers beet auct deep eid dose aratand aaria Enna 84 Interr pt SOUIC6S one on re nae p D quete esae ie Oe dn ede e 89 Preliminary User s Manual U14668EE3VOUMOO 11 12 Preliminary User s Manual U14668EE3VOUMOO Chapter 1 Outline Description Some host CPUs supports 2 instead of only 1 DCAN interface Both interfaces which have the same functionality are described at the same time in this manual The reference is given by the index n n 0 1 Where necessary the registers of both DCAN interfaces are shown Products that feature only one DCAN interface refer to the first index n 0 only For products with a single DCAN interface the index in the register names needs to be omitted The address information for special function registers SFR and memory base addresses needs to be picked up from the user manual of the particular product Remark The following indices were consequently used e nz0 1 for each of the 2 DCAN channels DCANO DCAN1 e m 2 4 address offset index for the 2 Mask Buffers r202to11 address offset index for the 16 Receive Buffers t 00 01 address offset index for the
52. ent Acceptable Clarity Technical Accuracy Organization CS 01 2
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54. ers of 2 address space memory capacity kilo 210 1024 M mega 220 10242 1 048 576 giga 239 1024 1 073 741 824 Chapter Organization Chapter Chapter 1 This manual divides the descriptions for the DCAN into different chapters as shown below Outline Description Chapter 2 CAN Protocol Chapter 3 Function Chapter 4 Connection with Target System Chapter 5 DCAN Controller Configuration Chapter 6 Special Function Register for DCAN module Chapter 7 Message Buffer Configuration Chapter 8 Transmit Buffer Structure Chapter 9 Transmit Message Buffer Format Chapter 10 Receive Buffer Structure Chapter 11 Receive Message Buffer Format Chapter 12 Mask Function Chapter 13 Operation of the DCAN Controller Chapter 14 Baud Rate Generation Chapter 15 Function Control Chapter 16 Interrupt Information Chapter 17 Power Saving Modes Chapter 18 Related Documents Functional Description by Flowcharts The content of this document issue April 2002 addresses the DCAN macro version B2 Differences to older versions are indicated but not described For particular information on memory or register addresses that are not men tioned in this document the respective user manual of the product needs to be checked Preliminary User s Manual U14668EE3VOUMOO Table of Contents Introduction
55. essful reception MUC Memory Update 0 CAN does not access data part 1 CAN is transferring new data to message buffer The DCAN module sets MUC when it starts transferring a message into the buffer and clears the MUC bit when the transfer is finished Reserved Bit 1 0 Reserved bit 1 of received message was 0 1 Reserved bit 1 of received message was 1 Ro Reserved Bit 0 0 Reserved bit 0 of received message was 0 1 Reserved bit 0 of received message was 1 52 Preliminary User s Manual U14668EE3VOUMOO Chapter 11 Receive Message Buffer Format Data Length Code Selection of Receive Message 0 0 0 0 0 data bytes 0 0 0 1 1 data bytes 0 0 1 0 2 data bytes 0 0 1 1 3 data bytes 0 1 0 0 4 data bytes 0 1 0 5 data bytes 0 1 1 0 6 data bytes 0 1 1 1 7 data bytes 1 0 0 0 8 data bytes Others than above Note DSTAT is written by the DCAN two times during message storage At the first access to this buffer DN 1 1 reserved bits and DLCx x 3 to 0 are written At the last access to this buffer DN 1 0 reserved bits and DLCx x 3 to 0 are written Note Valid entries for the data length code are 0 to 8 If a value higher than 8 is received 8 bytes are stored in the message buffer frame together with the data length code received in the DLC of the message Preliminary User s Manual U14668EE3VOUMOO 53 Chapter 11 Receive Mess
56. etects a start of frame in the bus idle state When the node detects a falling edge of a SOF the current time quanta becomes the synchronization segment The length of the following segments are defined by the values programmed into the SYNCO and SYNC1 registers Figure 3 2 Adjusting Synchronization of the Data Bit Bus idle Start of frame CAN bus N Sync Prop Phase Phase Preliminary User s Manual U14668EE3VOUMO00 33 Chapter 3 Function b Soft synchronization When a recessive to dominant level change on the bus is detected a soft synchronization is performed lf the phase error is larger than the programmed SJW value the node will adjust the timing by applying this SJW value Full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge s These errors that are equal or less of the programmed SJW are corrected instantly and full synchronization is achieved already for the next bit The TQ at which the edge occurs becomes sync segment forcibly if the phase error is less than or equal to SJW Figure 3 3 Bit Synchronization Phase Sync Prop segment segment segment Phase Sync Prop segment 2 segment segment 34 Preliminary User s Manual U14668EE3VOUMOO Chapter 3 Function 3 8 State Shift Chart Figure 3 4 Transmission State Shift Chart Reception Start of frame End Arbitration field Control field RTR 0 Data field End Bi
57. ffer Format 11 4 Receive Message Data Part These memory locations set the receive message data part of the CAN protocol DATAO to DATA7 can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 11 4 Receive Data Address offsetNote Symbol 7 6 5 4 3 2 1 DATA1 a i undefined undefined undefined undefined undefined undefined undefined undefined Note 02 11 address index for the 16 Receive Buffers see Chapter 7 page 43 R W R W R W R W R W R W R W R W R W The DCAN stores received data bytes in this memory area Only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area If the DLC is less than eight the DCAN will not write additional bytes exceeding the DLC value up to eight The DCAN stores a maximum of 8 bytes according to the CAN protocol rules even when the received DLC is greater than eight Preliminary User s Manual U14668EE3VOUMOO 55 56 Preliminary User s Manual U14668EE3VOUMOO Chapter 12 Mask Function Table 12 1 Mask Function Register Address Name Note Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 offset Unused ID standard part ID standard part 0 0 ID extended part ID extended part ID extended part 0 0 0 Unused
58. firmed by the INITSTATE bit of CANESn register can have unexpected behaviour to the CAN bus Input Clock Selector for DCAN Clock fy is input for DCAN fxx 2 is input for fxx 4 is input for DCAN fxx 8 is input for or CCLK pin of device is used as source Refer to the user manual of the product because this is device dependent Preliminary User s Manual U14668EE3VOUMOO 73 Chapter 14 Baud Rate Generation BRPRSn defines the number of DCAN clocks applied for one TQ For BRPRSn two modes are available depending on the TLMODE bit in the SYNC1n register Setting of BRPRSx x 5 to 0 for TLMODE 0 BRPRS5 BRPRS4 BRPRS3 BRPRS2 BRPRS1 BRPRSO Bit Rate PrescalerNote 2 x BRPRSn 5 0 2 118 120 122 124 126 128 Note The bit rate prescaler value represents the DCAN clocks per TQ Setting of BRPRSx x 7 to 0 for TLMODE 1 BRPRS7 BRPRS6 BRPRS5 BRPRS4 BRPRS3 BRPRS2 BRPRS1 BRPRSO Bit Rate Prescaler BRPRSn 7 0 1 123 124 125 126 127 128 Note The user needs to assure that phase segment 2 TSEG2 consists of at least 3 TQ when using this setting BRPRS7 BRPRS6 are located the MASKCn register s 74 Preliminary User s Manual U14668EE3VOUMOO Chapter 14 Baud Rate Generation 14 2 Synchronization Control Registers 0 and
59. g 0 No data on the CAN bus 1 Reception active on the CAN bus The TXF bit and RXF bit of CANCn register show the present status of the DCAN on the bus If both bits are cleared the bus is in idle state RXFn and TXFn are read only bits During initialisation mode both bits do not reflect the bus status 66 Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the DCAN Controller 13 3 DCAN Error Status Register This register shows the status of the DCAN CANESn has to be set with an 8 bit memory manipulation instruction Figure 13 8 DCAN Error Status Register CANESn 0 1 Symbol 7 After Reset 0 BOFF RECS TECS JER E VALID WAKE OVER QoHNete R W R W R W CANES1 BOFF RECS TECS SEA sin VALID WAKE OVER OOHNote R W R W R W Note RESET input sets CANCn to The RESET sets the INIT bit in CANCn register therefore CANESn will be read as 08h after RESET release Remark BOFF RECS TECS and INITSTATE are read only bits Caution Don tuse bit operations on this SFR The VALID WAKE and OVER bits have a special behavior during CPU write operations Writing a 0 to them do not change them Writing an 1 clears the associated bit This avoids any timing conflicts between CPU access and internal activities An internal set condition of a bit overrides a CPU clear request at the same time BOFF Bus Off Flag 0 Transmission error counter x 255 1 Trans
60. g identifier comparisons Setting the DEF bit will not have immediate effect if DCAN is preparing to store or is already in progress of storing a received message into the particular buffer In this case the redefinition request is ignored for the currently processed message The application should monitor the DN flag before requesting the redefinition state for a particular buffer A DN flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer The application should be prepared to receive a message immediately after redefinition state was set The user can identify this situation because the data new bit DN in the receive buffer will be set This is of special importance if it is used together with a mask function because in this case the DCAN also writes the identifier part of the message to the receive buffer Then the application needs to re write the configuration of the message buffer Preliminary User s Manual U14668EE3VOUMOO 87 Chapter 15 Function Control 15 5 Performance of the DCAN For the access to the DCAN SFRs some host CPU cores V850x provide a programmable waiting time After reset of the host CPU the access is typically configured to the slowest speed The user needs to assign the fastest speed i e no wait states in order to achieve a minimum run time for the routines serving the CAN communication Details on this subject are explained in the user manual of the device
61. intermission suspend transmission and bus idle Figure 2 13 Interframe Space Error Passive Each frame T Interframe space T Each frame R D Intermission Suspend Bus idle 3 bits transmission 0 to oo bits 8 bits Remark The nominal value of the intermission field is 3 bits However transmission nodes may start immediately a transmission already in the 3 bit of this field when a dominant level is detected Table 2 5 Operation in the Error State Error active Any node in this state is able to start a transmission whenever the bus is idle Any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission Error passive Preliminary User s Manual U14668EE3VOUMOO 23 2 Protocol 2 4 Error Frame This frame is sent from a node if an error is detected The type of an Error Frame is defined by its error flag ACTIVE ERROR FLAG or PASSIVE ERROR FLAG Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node Figure 2 14 Error Frame Error frame EN Interframe space or overload frame Error delimiter Error flag Error flag Error bit Table 2 6 Definition of each Field Bit Number Definition Error active node sends 6 bits dominant level continuously Error passive node sends 6 bits recessive level continuously Error fl
62. ion with DCAN Sleep mode 17 2 CPU WATCH Mode The CPU watch mode is possible in conjunction with DCAN Sleep mode Not all host CPU cores fea ture a watch mode 17 3 CPU Stop Mode The DCAN stops any activity when its clock supply stops due to a CPU Stop mode issued This may cause an erroneous behaviour on the CAN bus Entering the CPU Stop Mode is not allowed when the DCAN is in normal mode i e online to the CAN bus The DCAN will reach an overrun condition when it receives clock supply again CPU Stop mode is possible when the DCAN was set to initialization state sleep mode or stop mode beforehand Note that the CPU will not be started again if the DCAN Stop mode was entered previously The DCAN has to be set to initialization state or stop mode when the host CPU operates on subclock i e feature of some 78KO products 17 4 DCAN Sleep Mode The DCAN Sleep mode is intended to lower the power consumption during phases where no communi cation is required The CPU requests the DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities After a successful switch to the DCAN Sleep mode the CPU can safely go into halt watch or stop mode However the application needs to be prepared that the DCAN cancels the sleep mode any time due to bus activities If the wake up interrupt is serviced the CPU Stop mode has not to be issued Other
63. issue any dominant level on the CAN transmit pin The reception of messages is not affected by the bus off state Table 3 5 Types of Error Operation Value of Error Counter Output Error Flag Type Transmission Error active 0 to 127 Active error flag 6 bits of dominant level continue reception Error passive Transmission 128 to 255 Passive error flag 6 bits of recessive level con Reception 128 or more tinue Bus off 30 Transmission more than 255 Communication cannot be made Reception Does exist Preliminary User s Manual U14668EE3VOUMOO Chapter 3 Function b Error counter Error counter counts up when an error has occurred and counts down upon successful transmission and reception The error counters are updated during the first bit of an error flag Table 3 6 Error Counter Reception node detects an error except bit error in the active error flag or overload flag Transmission Error Counter TEC No change Reception Error Counter REC Reception node detects dominant level following the error flag of the own error frame No change Transmission node transmits an error flag Exception 1 ACK error is detected in the error passive state and domi nant level is not detected in the passive error flag sent 2 Stuff error generation in arbitration field No change Bit error detection during active error flag and overload flag when transmitting nod
64. l Description by Flowcharts 18 5 Receive Event Oriented Figure 18 5 Receive with Interrupt Software Flow Receive Interrupt scans RMES or DN bits to find message Uses CLR1 Command Data was changed by CAN during the processing Clear Interrupt End Receive interrupt Preliminary User s Manual U14668EE3VOUMOO 99 Chapter 18 Functional Description by Flowcharts 18 6 Receive Task Oriented 100 Figure 18 6 Receive Software Polling Receive Polled Uses CLR1 command Read or process data Data was changed by CAN during the processing Y es End Receive Polled Preliminary User s Manual U14668EE3VOUMOO Chapter 18 Functional Description by Flowcharts Figure 18 7 Receive Software Polling in case of Data New Flag Limitation Receive Polled Uses CLR1 command Data was changed by CAN during the processing End Receive Polled Some DCAN implementations for particular products have a limitation on the function of the DN flag The CPU may inadvertently reset the MUC bit when resetting the DN flag Clear DN bit For these products a particular waiting time Wait loop needs to be inserted before checking if consistent data was read beforehand The waiting time depends on macro frequency CPU frequency and the number of data bytes read Refer to the application report EACT BR 5001 1 0 for details on the exact waiting time Preliminary User s M
65. ll responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equip ment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti
66. lso the ID part can be falsified in case of using mask function Remarks 1 The unused parts of the identifier IDREC1 bit 4 0 always and IDREC4 bit 5 0 in case of extended frame reception may be written by the DCAN to 0 They are not released for other use by the CPU 2 RTRREC is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the bytes IDRECO and IDREC1 registers for standard frame format and IDRECO to IDREC4 registers for extended frame format For the RTRREC bit exists two modes bit in the MCON register of the dedicated mask is set to 0 In this case RTRREC bit will always be written to 0 together with the update of the IDx bits x 18 to 20 in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer RTR bit in the MCON byte of the dedicated mask is set to 1 data and remote frames are accepted In this case the RTR bit in IDCON register has no meaning The received message type passed the mask is shown in RTRREC bit If a buffer is not dedicated to a mask function mask 1 mask 2 or global mask the IDRECO to IDREC4 registers are only read for comparing All receive identifiers should be defined to 0 before the application sets up its specific values 54 Preliminary User s Manual U14668EE3VOUMOO Chapter 11 Receive Message Bu
67. mask can serve for standard receive buffers at the same time as for extended receive buffer Figure 12 1 Identifier Compare with Mask Received Identifier Compare Bit by Bit Store on equal Mask stored in Receive Buffer 0 or 2 Disable Compare for masked Bits Identifier stored in Receive Buffer This function implements the so called basic CAN behaviour In this case the type of identifier is fixed to standard or extended by the setup of the IDE bit in the receive buffer The comparison of the RTR bit can also be masked It is possible to receive data and remote frames on the same masked receive buffer 58 Preliminary User s Manual U14668EE3VOUMOO Chapter 12 Mask Function The following information is stored in the receive buffer Identifier 11 or 29 bit as defined by IDE bit Remote bit RTRREC if both frames types data or remote can be received by this buffer Reserved bits Data length code DLC Data bytes as defined by DLC Caution All writes into the DCAN memory are byte accesses Unused bits in the same byte will be written zero Unused bytes will not be written and are free for application use by the CPU 12 2 Mask Identifier Control Register MCON The memory location labelled MCON sets the mask identifier control bit of the CAN protocol MCON can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 12 2 Mask Identifier Control Regi
68. mission error counter 255 BOFFn is cleared after receiving 128 x 11 bits recessive state Bus idle or by issuing a hard DCAN reset with the TLRES bit in the MCNTn register Note An interrupt is generated when the BOFF bit changes its value RECS Reception error counter status 0 Reception error counter 96 1 Reception error counter gt 96 Warning level for error passive reached RECS is updated after each reception An interrupt is generated when RECS changes its value Note Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 Preliminary User s Manual U14668EE3VOUMOO 67 Chapter 13 Operation of the Controller TECS Transmission error counter status 0 Transmission error counter lt 96 1 Transmission error counter gt 96 Warning level for error passive reached TECS is updated after each reception An interrupt is generated when TECS changes its value INITSTATE Operational status of the DCAN 0 CAN is in normal operation 1 CAN is stopped and ready to accept new configuration data INITSTATEn changes with a delay to the INIT bit in CANCn register The delay depends on the current bus activity and the time to set all internal activities to inactive state This time can be several bit times long While BOFF bit is set a request to go into the initialisation mode by setting the INIT bit is ignored In this case the INITSTATE bit will not be set until the bus
69. mit buffer layout As well the CPU may use unused ID addresses unused data addressesN t and an unused transmit buffer of the for its own purposes The con trol bits the identification and the message data has to be stored in the message RAM area The transmission control is done by the TCRn register A transmission priority selection allows the cus tomer to realize an application specific priority selection After the priority selection the transmission can be started by setting the TXRQXx bit x 0 1 In the case that both transmit buffers are used the transmit priorities can be set For this purpose the DCAN has the TXP bit in the TCRn register n 0 1 The application software has to set this priority before the transmission is started The two transmit buffers of each DCAN channel DCANO DCAN1 supply two independent interrupt lines for an interrupt controller Note Message objects that need less than 8 data byte DLC 8 may use the remaining bytes 8 DLC for application purposes 44 Preliminary User s Manual U14668EE3VOUMOO Chapter 9 Transmit Message Buffer Format AddressNote Bit 7 Bit 5 DLC3 sed ID standard part ID standard part 0 0 ID extended part ID extended part ID extended part 0 0 Unused Message data byte 0 Message data byte 1 Message data byte 2 Message data byte 3 Message data byte 4 Message data
70. n of recessive level in ACK slot 2 Output timing of the error frame Transmission node ACK slot Table 3 4 Output Timing of the Error Frame Bit error stuff error form error ACK error Error frame is started at the next bit timing following the detected error Error passive 3 Measures when error occurs CRC error Error frame is started at the next bit timing following the ACK delimiter Transmission node re transmits the data frame or the remote frame after the error frame The CAN standard ISO 11898 allows a programmable suppression of this re transmission It is called single shot mode Preliminary User s Manual U14668EE3VOUMOO 29 Chapter 3 Function 4 Error state a Types of error state Three types of error state These are error active error passive and bus off The transmission error counter TEC and the reception error counter REC control the error state The error counters are incremented on each error occurrence refer to Table 3 6 If the value of error counter exceeds 96 warning level for error passive state is reached When only one node is active at start up it may not receive an acknowledgment on a transmitted message This will increment TEC until error passive state is reached The bus off state will not be reached because for this specific condition TEC will not increment any more if values greater than 127 are reached A node in bus off state will not
71. nd it is cleared when the INIT bit in CANCn register is set Data New Bit for Message n n 0 7 No message received on message n or CPU has cleared DN bit in the respective RX message buffer Data received in the respective RX message buffer DNO bit has no meaning when receive buffer 0 is configured for mask operation in the mask control register DN bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register 82 Preliminary User s Manual U14668EE3VOUMOO Chapter 15 Function Control 15 3 Mask Control The mask control register defines whether the DCAN compares all identifier bits or if some bits are not used for comparison This functionality is provided by the use of the mask information The mask infor mation defines for each bit of the identifier whether it is used for comparison or not The DCAN uses a receive buffer for this information when it is enabled by the mask control register In this case this buffer is not used for normal message storage Unused bytes can be used for application needs 15 3 1 Mask Control Register This register controls the mask function applied to any received message MASKOn can be written with an 8 bit memory manipulation instruction Symbol 7Note Figure 15 3 Mask Control Register MASKCn n 0 1 gNote 5Note 4Note 3 2 1 0 After Reset R W R W R W R W R R W R W R W R W R W R W R W R R W R W R W Note BRPRS7 BRPRS6 SS
72. nual U14668EE3VOUMOO 39 Chapter 5 DCAN Controller Configuration The DCAN module consists of the following hardware Item Configuration Message definition In RAM area 1 CTXD1n 1 CRXD1n DCAN input output DCAN control register DCANCn Nete CAN control register CANCn Transmit control register TCRn Receive message register RMESn Redefinition control register REDEFn DCAN error status register CANESn Control registers Transmit error counter TECn Receive error counter RECn Message count register MCNTn Bit rate prescaler BRPRSn Synchronous control register 0 SNYCOn Synchronous control register 1 SYNC1n Mask control register MASKCn Remark n 0 1 Note The register s DCANCn is are not available on all products 40 Preliminary User s Manual U14668EE3VOUMOO Remark Chapter6 Special Function Register for DCAN module Register Name DCAN control register DCANCO Bit Manipulation Units 1 Bit 8 Bit 16 Bit After Reset CAN control register CANCO Transmit control register TCRO Receive message register RMESO Redefinition control register REDEFO DCAN error status register CANESO Transmit error counter TECO Receive error counter RECO Message count register MONTO Bit rate prescaler BRPRSO Synchronous control register 0 SYNCOO Synchronous control register 1 SYNC10 Mask control r
73. ode 1 Preliminary User s Manual U14668EE3VOUMOO 19 2 Protocol 3 Control field The data byte number DLC in the data field specifies the number of databytes in the current frame DLC 0 to 8 Figure 2 6 Control Field Standard Format Mode Arbitration field E Control field Dm field OD Figure 2 7 Control Field Extended Format Mode Arbitration field at Control field field R D The bits rO and r1 are reserved bits for future use and are recommended to be recessive Table 2 4 Data Length Code Setting Data Length Code DLC2 DLC1 Number of Data Bytes 0 0 0 1 1 0 1 1 1 7 1 X X X 8 Remark n case of a remote frame the data field is not generated even if data length code O 20 Preliminary User s Manual U14668EE3VOUMOO Chapter 2 Protocol 4 Data field This field carries the data bytes to be sent The number of data bytes is defined by the DLC value Figure 2 8 Data Field Control field vue Data field mie field R D Data 8 bits Data 8 bits 5 CRC field This field consists of a 15 bit CRC sequence to check the transmission error and a CRC delimiter Figure 2 9 CRC Field Data field and control field T CRC field a ACK field R D CRC sequence CRC delimiter 15 bits 1 bit 15 bits CRC generation polynomial is expressed by SEXX OX Pax X Transmission node Transmit
74. off state is left Valid protocol activity detected No valid message detected by the CAN protocol Error free message reception from CAN bus This bit shows valid protocol activities independent from the message definitions and the RXONLY bit setting in SYNC1n register VALID is updated after each reception The VALID bit will be set at the end of the frame when a complete protocol without errors has been detected Cautions 1 The VALID bit is cleared if CPU writes an 1 to it or when the INIT bit in CANCn register is set 2 Writing a 0 to the valid bit has no influence Wake up Condition Normal operation Sleep mode has been cancelled or sleep stop mode request was not granted This bit is set and an error interrupt is generated under the following circumstances A CAN bus activity occurs during DCAN Sleep mode b Any attempt to set the SLEEP bit in the CAN control register during receive or transmit opera tion will immediately set the WAKE bit The CPU must clear this bit after recognition in order to receive further error interrupts because the error interrupt line is kept active as long as this bit is set Cautions 1 The WAKE bit is cleared to 0 if CPU writes an 1 to it or when the INIT bit in CANCn register is set 2 Writing a 0 to the WAKE bit has no influence 68 Preliminary User s Manual U14668EE3VOUMOO Chapter 13 Operation of the DCAN Controller OVER Overrun Condition
75. on is performed Prop segment This segment absorbs delays of the output buffer the CAN bus and the input buffer Prop segment time output buffer delay CAN bus delay input buffer delay Phase segment 1 2 These segments compensate the data bit time error The larger the size measured in TQ is the larger is the tolerable error The synchronization jump width SJW specifies the synchronization range The SJW is programmable SJW can have less or equal number of TQ as phase segment 2 Table 3 7 Segment Name and Segment Length Segment Length segment Name allowed Number of TQs Sync segment Synchronization segment Prop segment Propagation segment Programmable 1 to 8 Phase segment 1 Phase buffer segment 1 Kogrammaote T 5 8 Phase segment 2 Maximum of phase segment 1 Phase buffer segment 2 and the IPT Nete SJW Programmable 1 to 4 Note IPT Information Processing Time It needs to be less than or equal to 2 TQ 32 Preliminary User s Manual U14668EE3VOUMOO Chapter 3 Function 2 Adjusting synchronization of the data bit The transmission node transmits data synchronized to the transmission node bit timing The reception node adjusts synchronization at recessive to dominant edges on the bus Depending on the protocol this synchronization can be a hard or soft synchronization a Hard synchronization This type of synchronization is performed when the reception node d
76. r TCRn pro vides complete control over the two transmit buffers and their status It is possible to request and abort transmission of both buffers independently TCRn can be set with a an 8 bit memory manipulation instruction Caution Don t use bit operations on this register Also logical operations read modify write via software may lead to unexpected transmissions Initiating a transmit request for buffer 1 while TXRQO is already set is simply achieved by writing 02h or 82h The status of the bits for buffer 0 is not affected by this write operation Figure 15 1 Transmit Control Register TCRn n 0 1 Symbol 7 6 5 4 3 2 1 0 After Reset TCRO 1 TXCO TXA1 TXAO 1 TXRQO 00H R W R R R R W R W R W R W R R R W R R W R W R W R W Transmission Priority P 0 Buffer 0 has priority over buffer 1 1 Buffer 1 has priority over buffer 0 The user defines which buffer has to be send first in the case of both request bits are set If only one buffer is requested by the TXRQx bit x 0 1 bits TXP bit has no influence TXCx x 0 1 shows the status of the first transmission It is updated when TXRQx x 0 1 is cleared Transmission Abort Flag Write normal operation Read no abort pending Write aborts current transmission request for this buffer x Read abort is pending TXCn Transmission Complete Flag 0 Transmit was aborted no data sent 1 Transmit was comple
77. s on the bus This byte will never be written by the DCAN Only the host CPU can change this byte Note The user has to define with the ENI bit if he wants to set a receive interrupt request when new data is received in this buffer Preliminary User s Manual U14668EE3VOUMOO 51 Chapter 11 Receive Message Buffer Format 11 2 Receive Status Bits Definition The memory location labelled DSTAT sets the receive status bits of the arbitration field of the CAN protocol DSTAT can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 11 2 Receive Status Bits Register DSTAT Address offsetNote Note 02 11 address index for the 16 Receive Buffers see Chapter 7 on page 43 Symbol 7 6 5 4 3 2 1 After Reset R W The receive status reflects the current status of a message It signals whether new data is stored or if the DCAN currently transfers data into this buffer In addition the data length of the last transferred data and the reserved bits of the protocol are shown 0 No change in data 1 Data changed The DCAN module sets DNn twice At first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation The CPU needs to clear this bit to signal by itself that it has read the data During initialisation of the receive buffers the DNn bit should also be cleared Otherwise the CPU gets no information on an update of the buffer after a succ
78. s represents the ID stored in the mentioned receive buffer The table also shows which buffers are used to provide the mask information and therefore do not receive messages A global mask can be used for standard and extended frames at the same time The frame type is only controlled by the IDE bit of the receiving buffer Table 15 1 Mask Operation Buffers Receive Buffer GLOBAL 2 Operation Compare Compare Compare Compare Compare ID ID ID ID ID Compare Compare Compare Compare ID amp maskO ID ID ID Compare Compare Maskt Compare Compare ID ID ID amp mask1 ID Normal ID amp ID amp 1 ID awe Masks ID amp maskO ID amp ID amp maskO Global mask Compare Compare Compare Two normal ID ID Maski ID amp maski rest global mask Compare Maski Compare g maski One mask Masko ID amp maskO ID rest global mask 84 Preliminary User s Manual U14668EE3VOUMOO Chapter 15 Function Control Priority of receive buffers during compare It is possible that more than one receive buffer is configured to receive a particular message For this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective The priority of a receiv
79. s the CRC sequence calculated from the start of frame arbitration field control field and data field eliminating stuff bits Reception node The CRC received will be compared with the CRC calculated in the receiving node For this calculation the stuff bits of the received CRC are eliminated In case these do not match the node issues an error frame Preliminary User s Manual U14668EE3VOUMOO 21 2 Protocol 6 ACK field For check of normal reception Figure 2 10 ACK Field CRC field Kn ACK field E End of frame D ACK slot ACK delimiter 1 bit 1 bit Receive node sets the ACK slot to dominant level if no error was detected 7 End of frame Indicates the end of the transmission reception Figure 2 11 End of Frame ACK field T End of frame aW Interframe space of overload frame R D 7 bits 22 Preliminary User s Manual U14668EE3VOUMOO Chapter 2 Protocol 8 Interframe space This sequence is inserted after data frames remote frames error frames and overload frames in the serial bitstream on the bus to indicate start or end of a frame The length of the interframe space depends on the error state active or passive of the node a Error active Consists of 3 bits intermission and bus idle Figure 2 12 Interframe Space Error Active Any frame Interframe space frame R D Intermission Bus idle 3 bits 0 to bits b Error passive Consists of 3 bits
80. sage buffers which are handled by the DCAN module is allocated MONTn can be read with an 8 bit memory manipulation instruction Figure 13 11 Message Count Register MCNTn n 0 1 Symbol 7 After Reset R W R W R W R W R W R W R W R W Note The TLRES bit is not available on all DCAN implementations In that case the bit reads 0 and a write operation has no effect Receive Message Count Setting prohibited 1 receive buffer 2 receive buffer 3 receive buffer 4 receive buffer 5 receive buffer 6 receive buffer 7 receive buffer 8 receive buffer 9 receive buffer 10 receive buffer 11 receive buffer 12 receive buffer 13 receive buffer 14 receive buffer 15 receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 16 receive buffer Setting prohibited will be automatically changed to 16 Preliminary User s Manual U14668EE3VOUMOO 71 Note Chapter 13 Operation of the Controller TLRES Reset function for CAN Protocol MachineNete No Reset is issued Reset of CAN protocol machine is issued if DCAN is in bus off state DCAN will enter INIT state CANC 0 1 amp amp CANES 3 1 Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 DCAN Address definition 0 0 Setting prohibited 0 1 Setting prohibited 1 0 DCAN uses address range starting a
81. ster Address offsetNote Note m 2 4 address index for the 2 Mask Buffers see Chapter 7 page 43 Symbol T 6 5 4 3 2 1 After Reset R W RTR Remote Transmission Select 0 Check RTR bit of received message Note 1 1 Receive message independent from RTR bit Note 2 Notes 1 For RTR 0 the received frame type data or remote is defined by the RTR bit in IDCON of the dedicated buffer In this case RTRREC will always be written to 0 together with the update of the IDx bits x 18 to 20 in IDREC1 2 In case RTR in MCON is set to 1 RTR bit in IDCON of the dedicated receive buffer has no meaning The received message type passed the mask is shown in the RTRREC bit Preliminary User s Manual U14668EE3VOUMOO 59 Chapter 12 Mask Function 12 3 Mask Identifier Definition These memory locations set the mask identifier definition of the DCAN MRECO to MREC4 can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 12 3 Mask Identifier Register MREC Address Symbol 7 6 5 4 3 2 1 offsetNote After Reset R W MRECO MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 m2H undefined R W MREC1 MID20 MID19 MID18 0 0 0 0 0 m3H undefined R W MREC2 MID17 MID16 MID15 MID14 MID13 MID12 MID11 MID10 m4H undefined R W MREC3 MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 m5H undefined R W MREC4 MID1 MIDO 0 0 0 0 0 0 m6H undefined R W Note m 2 4
82. t error 1 Bit error Reception Bit error Bit error ACK error Bit error Error passive Error active Initialization setting 8 bits of 1 Start of frame transmission Start of frame reception Reception Preliminary User s Manual U14668EE3VOUMOO 35 Transmission Chapter 3 Function Figure 3 5 Reception State Shift Chart Transmission Start of frame End Stuff error Start of frame transmission n Arbitration field RTR 1 Stuff error Control field RTR 0 Stuff error Data field End CRC error stuff error ACK error bit error Transmission Start of frame reception Initialization setting Preliminary User s Manual U14668EE3VOUMOO Chapter 3 Function Figure 3 6 Error State Shift Chart a Transmission TEC 128 TEC 127 TEC 256 TEC Transmission error counter b Reception REC gt 128 Error passive REC 127 REC Reception error counter Preliminary User s Manual U14668EE3VOUMOO 37 38 Preliminary User s Manual U14668EE3VOUMOO Chapter 4 Connection with Target System The DCAN Macro has to be connected to the CAN bus with an external transceiver Figure 4 1 Connection to the CAN Bus Transceiver CANL DCAN Macro CANH Preliminary User s Ma
83. t the transmit message data of the data field in the CAN frame DATAO to DATA can be set with a 1 bit or an 8 bit memory manipulation instruction Figure 9 3 Transmit Data Address offsetNote T T T T 7 H undefied Note 00 01 address index for the 2 transmit buffers see Chapter 7 page 43 Symbol 7 6 5 4 3 2 1 After Reset R W R SS W R W R W R W R W R W R W R W Remark Unused data bytes that are not used by the definition in the DLC bits in the TCON byte are free for use by the CPU for application needs 48 Preliminary User s Manual U14668EE3VOUMOO Chapter 10 Receive Buffer Structure The DCAN has up to 16 receive buffers The number of used buffers is defined by the MCNTn register Unused receive buffers can be used as application RAM for the CPU The received data is stored directly in this RAM area The 16 buffers have a 16 byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message The structure of the receive buffer is similar to the structure of the transmit buffers The semaphore bits DN and MUC enable a secure reception detection and data handling For the first 8 receive message buffers the successful reception is mirrored by the DN flags in the RMESn register The receive interrupt request can be enabled or disabled for each used buffer separately Preliminary User s Manual U14668EE3VOUMOO
84. t user address 1Note 1 1 DCAN uses address range starting at user address 2Note Note Some products offer a selectable by software address location that even differs between Flash and Mask ROM devices Other products have a fixed address offset by hardware design In that case both CADDx bits read 1 and writing to them has no effect For 78K0 based DCAN implementations the user needs to set up memory configurations via the IXS register additionally The user address defines the lower starting address for the DCAN area The highest address the DCAN uses can be derived by the number of messages defined with MCNTn register 72 Preliminary User s Manual U14668EE3VOUMOO Chapter 14 Baud Rate Generation 14 1 Bit Rate Prescaler Register This register sets the clock for the DCAN internal DCAN clock and the number of clocks per time quantum TQ BRPRSn can be set with an 8 bit memory manipulation instruction Figure 14 1 Bit Hate Prescaler Register BRPHSn n 0 1 Symbol 7 6 5 4 3 2 1 0 After Reset R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W The PRMx x 0 1 bits define the clock source for the operation The PRM selector defines the input clock to the DCAN Macro and influences therefore all DCAN activities Writing to the BRPRSn register is only allowed during initialization mode Any write to this register when INIT bit is set in CANCn register and the initialization mode is not con
85. te abort had no effect The TXAx bits allow to free a transmit buffer with a pending transmit request Setting the TXAx bit x 0 1 by the CPU requests the DCAN to empty its buffer by clearing the respective TXRQx bit Preliminary User s Manual U14668EE3VOUMOO 79 Chapter 15 Function Control The TXAx bits x 2 0 1 have a dual function 1 The CPU can request an abort by writing a 1 into the bit 2 The DCAN signals whether such an request is still pending The bit is cleared at the same time when the TXRQx bit x 0 1 is cleared The abort process does not affect any rules of the CAN protocol A frame already started will continue to its end An abort operation can cause different results dependent on the time it is issued d When an abort request is recognized by the DCAN before the start of the arbitration for transmit the TXOx bit x 0 1 is reset showing that the buffer was not send to other nodes When the abort request is recognized during the arbitration and the arbitration is lost afterwards the TXOx bit x 0 1 is reset showing that the buffer was not send to other nodes f When the abort request is recognized during frame transmission and the transmission ends with an error afterwards the TXOx bit x 0 1 is reset showing that the buffer was not send to other nodes g When the abort request is recognized during the frame transmission and transmission ends with out error The TXCx bit x 0 1
86. ts the number of bytes which have to be transmitted Valid entries for the data length code DLC are 0 to 8 If a value greater than 8 is selected 8 bytes are transmitted in the data frame The Data Length Code is specified in DLC3 through DLCO 46 Preliminary User s Manual U14668EE3VOUMOO Chapter 9 Transmit Message Buffer Format 9 2 Transmit Identifier Definition These memory locations set the message identifier in the arbitration field of the CAN protocol IDTXO to IDTX4 register can be set with a 1 bit or an 8 bit memory manipulation instruction Symbol 7 IDTXO 1028 IDTX1 ID20 IDTX2 1017 IDTX3 ID9 IDTX4 ID1 Note 00 01 address index for the 2 transmit buffers see Chapter 7 page 43 6 ID27 ID19 ID16 1 8 IDO Figure 9 2 Transmit Identifier Register ID26 ID18 ID15 ID7 ID25 ID14 ID6 ID24 ID13 ID5 ID23 ID12 104 1022 1011 ID3 ID21 ID10 ID2 Address offsetNote t2H 13H t4H t5H teH After Reset R W undefined R W undefined R W undefined R W undefined R W undefined R W Remark f a standard frame is defined by the IDE bit in the TCON register then IDTXO and IDTX1 are used only IDTX2 to IDTX4 are free for use by the CPU for application needs then Preliminary User s Manual U14668EE3VOUMOO 47 Chapter 9 Transmit Message Buffer Format 9 3 Transmit Data Definition These memory locations se
87. wise the CPU will not be released from CPU Stop mode even when there is ongoing bus activity The wake up is independent from the clock The release time for the CPU Stop mode of the device is of no concern because the DCAN synchronizes again to the CAN bus after clock supply has started Preliminary User s Manual U14668EE3VOUMOO 91 Chapter 17 Power Saving Modes The following example sketches the general approach on how to enter the DCAN Sleep mode Note that the function may not return for infinite time when the CAN bus is busy The user may apply time out controls to avoid excessive run times Code example DCAN_Sleep_Mode void CANES 0x02 clear Wake bit CANC 0x04 request DCAN Sleep mode while CANES amp 0x02 check if DCAN Sleep mode was accepted CANES 0x02 try again to get DCAN asleep CANC 0x04 The following code example assures a safe transition into CPU Stop mode for all timing scenarios of a suddenly occurring bus activity The code prevents that the CPU gets stuck with its oscillator stopped despite CAN bus activity Code example any application code DCAN_Sleep_Mode request and enter DCAN sleep mode aise any application code DI disable interrupts NOP Nete NOP if wakeup interrupt occurred FALSE the variable wakeup interrupt occurred needs to be initialized at system reset and it needs to be set TRUE when servicing the

DCAN Macro Version B2 Preliminary User`s Manual

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