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405EXr - Octopart

1. Parameter Minimum Maximum Units Notes Unit Interval Ul 399 88 400 12 ps Differential p p Tx voltage swing 800 mV ppd Low power differential p p Tx voltage swing 400 mV ppd Tx de emphasis level ratio 3 0 4 0 dB Minimum Tx eye width 0 75 Ul Maximum time between the jitter median and maximum bing 0 125 UI deviation from the median Transmitter rise and fall time 0 125 2 Ul Maximum Tx PLL bandwidth 22 MHz Minimum Tx PLL BW for 3dB peaking 1 5 gt MHz Tx AC common mode voltage 20 mV Absolute Delta of DC Common Mode Voltage during LO and 0 100 mV Electrical Idle Absolute Delta of DC Common Mode Voltage between PCIENTx DricaTy 0 25 mV and PCIEnTx Electrical Idle Differential Peak Output Voltage 0 20 mV Lag amount of voltage change allowed during Receiver E 600 mV etection Transmitter DC common mode voltage 0 3 6 V Transmitter short circuit current limit 90 mA Minimum time spent in Electrical Idle 20 ns Maximum time to transition to a valid Electrical Idle after sending 8 5 ns an EIOS Maximum transition time to valid differential signaling after 8 y i ns leaving Electrical Idle Differential return loss 10 dB Common mode return loss 6 dB DC differential Tx impedance 80 120 Q AMCC Proprietary 71 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Initialization The
2. Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name JO1 PCIEORx Ko1 AGND LO1 PCIEOCIKC Mot AVpp J02 PCIEORx K02 PCIEOTx L02 PCIEOCIKT M02 PCIEORExtG J03 AVpp K03 PCIEOTx L03 PCIEOATB M03 PCIEORExt J04 GND K04 AVpp L04 AGND M04 AHVpp J05 No ball KO5 No ball L05 No ball M05 No ball JO6 No ball K06 No ball LO6 No ball M06 No ball JO7 No ball KO7 No ball L07 No ball M07 No ball J08 No ball K08 No ball L08 No ball M08 No ball JO9 No ball K09 No ball L09 No ball Mog No ball J10 No ball K10 No ball L10 No ball M10 No ball J11 No ball K11 No ball L11 GND M11 OVpp J12 No ball K12 No ball L12 OVpp M12 GND J13 No ball K13 No ball L13 GND M13 GND J14 No ball K14 No ball L14 Vop M14 GND J15 No ball K15 No ball L15 OVpp M15 GND J16 No ball K16 No ball L16 GND M16 OVpp J17 No ball K17 No ball L17 No ball M17 No ball J18 No ball K18 No ball L18 No ball M18 No ball J19 No ball K19 No ball L19 No ball M19 No ball J20 No ball K20 No ball L20 No ball M20 No ball J21 No ball K21 No ball L21 No ball M21 No ball J22 No ball K22 No ball L22 No ball M22 No ball J23 GND K23 Vop L23 Svrer2B M23 Vop J24 PerAddr10 K24 GND L24 TrcCik M24 MemData00 J25 PerAddr08 K25 PerAddr06 L25 MemData04 M25 DMO J26 PerAddr07 K26 GPIO26 L26 MemData05 M26 DQSO 34 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table
3. 36 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 4 Signals Listed by Ball Assignment Sheet 6 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name AAO1 IICOSData AB01 GND ACO1 GMCTxD5 ADO1 GMCTxD2 AA02 IIC1SCIk AB02 GMCTxD7 AC02 GMCTxD4 AD02 GMCTxD1 AA03 SCPDI AB03 GMCTxD6 AC03 GMCTxD3 AD03 GND AA04 IIC1SData AB04 EOVpp AC04 GND AD04 GMCCD AA05 No ball ABO5 No ball ACO5 EOVpp AD05 GMCTxEn AA06 No ball AB06 No ball AC06 GMCTxCIk ADO6 SysErr AA07 No ball ABO7 No ball AC07 EOVpp AD07 GMCRefCIk AA08 No ball AB08 No ball AC08 EOVpp AD08 SysReset AA09 No ball AB09 No ball ACO9 GND AD09 GMCRxCIk AA10 No ball AB10 No ball AC10 Vpp AD10 GMCRxD2 AA11 No ball AB11 No ball AC11 GMCRXDO AD11 MemData27 AA12 No ball AB12 No ball AC12 Vpp AD12 Reserved AA13 No ball AB13 No ball AC13 GND AD13 DM3 AA14 No ball AB14 No ball AC14 Syref1A AD14 SVpp AA15 No ball AB15 No ball AC15 Vpp AD15 MemData23 AA16 No ball AB16 No ball AC16 Sypep2A AD16 DM2 AA17 No ball AB17 No ball AC17 Vpp AD17 MemData21 AA18 No ball AB18 No ball AC18 GND AD18 MemODTO AA19 No ball AB19 No ball AC19 SVpp AD19 RAS AA20 No ball AB20 No ba
4. Note This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data It is not a recommended physical circuit design for this interface An actual interface design depends on many factors including the type of memory used and the board layout DDR2 SDRAM On Die Termination Impedance Setting For all DDR2 applications the On Die Termination ODT impedance value must be set to 75 ohms in the DIMM Extended Mode Register EMR in order to optimize the data transmission during memory write operations 62 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 22 DDR SDRAM Output Driver Specifications Output Current mA Signal Path 1 O H maximum I O L maximum Write Data MemData00 31 10 1 ECC0 7 10 19 DM0 4 10 A MemClkOutO 10 A MemAddr00 14 10 19 BA0 2 10 10 BankSel0 1 10 MemCIkEn 10 10 DQS0 4 10 to MemODT0 1 10 1 DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DOS signal on writes as indicated in Figure 9 DQS rising and falling edges are centered on valid data for writes The data in Table 23 is generated by means of simulation and includes logic driver package RLG and lengths Values are calculated over best case and worst case processes with speed junction temperature and vo
5. 50 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 10 Recommended DC Operating Conditions Sheet 2 of 2 Device operation beyond the conditions specified is not recommended Extended operation beyond the recommended conditions can affect device reliability Parameter Symbol Minimum Typical Maximum Unit Notes I O Maximum Allowable Overshoot 3 3V LVTTL and 2 5V 3 3 tolerant CMOS Vmao 39 ba aie I O Maximum Allowable Undershoot V 0 6 v 3 4 3 3V LVTTL and 2 5V 3 3 tolerant CMOS MAU Case Temperature Te 40 85 C 5 Notes 1 2 3 4 5 LPDL is least positive down level MPUL is most positive up level Can be extended to 1 1V min 1 2V typ 1 3V max with an estimated power increase of 130mW at 1 2V nom Maximum duration is 10 of the bus clock period Bus clock is as follows EBC PerClk Ethernet RxClk USB USB2CIk Duration of the overshoot is time above Vjy max Duration of the undershoot is time below Vj min A 533 MHz part running at 400 MHz or less can operate up to a case temperature of 95 Power Supply Sequence All the PPC405EXr I O designs are power supply sequence independent There is no requirement that the power supplies power up in any particular order The following items are power sequence considerations If the logic power Vpp is applied before the I O supply voltages t
6. KW which equals 4KB AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet PowerPC 405 Processor The PPC405 processor is a fixed point 32 bit RISC unit Features include e Five stage pipeline with single cycle execution of most instructions including loads and stores e Separate configurable 16 KB D and I caches both two way set associative e Thirty two 32 bit general purpose registers GPRs Unaligned load store support e Hardware multiply divide e Parity detection and reporting for the instruction cache data cache and translation look aside buffer TLB e Double word instruction fetch from cache Translation of the four GB logical address space into physical addresses Built in timer and debug support e Power management e DCR interface is 32 bits wide Selectable processor vs bus clock ratios N 1 ratio only where N 1 2 3 or 4 Internal Buses The PPC405EXr contains four internal buses the processor local bus PLB the Advanced High Performance Bus AHB the on chip peripheral bus OPB and the device control register DCR bus High performance devices such as the processor the DDR SDRAM memory controller PCI Express the Ethernet MAL and DMA utilize the PLB Lower bandwidth I O interfaces such as communications and timer interfaces utilize the OPB The daisy chained DCR bus provides a lower bandwidth path for passing status and control
7. PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Revision Log Date Version Contents of Modification 06 07 2007 1 00 Initial creation of document 06 28 2007 1 01 Updates and corrections Correct AMCC phone numbers Change PerErr to always pull down Add revised I O timing figures from 405EX DS Implement doc issues 374 and 382 Major updates to DDR SDRAM section and other parts of the DS Doc issue 392 Add PCI E I O specifications I O timing values updates Change boot from EBC support Doc Issue 383 10 25 2007 1 02 Six voltage pins originally labeled SVpp changed to EOVpp 11 21 2007 1 03 S2Vpp changed to SVpp Add TrcClk to Table 20 Implemented document Issues 412 436 and 440 01 04 2008 TO Note Automatic change bars now appear on all updates Implemented doc issue 447 ahs 01 15 2008 1 05 hid Re acapella ur range with increased power consumption Change DDR SDRAM and PCI E specs 01 16 2008 1 06 Correct voltage changes Change frequency spec on Analog supply voltage 02 13 2008 197 Update POIENCI signal desertion Increase PCI E differential signal amplitude to 1600mV doc issue 468 02 15 2008 1 08 Change power consumption numbers from estimated to measured Change number of RGMII interfaces from two to one Doc Issue 476 Misc updates Doc Issue 482 05 02 2008 1 09 Remove GMCMDIO timing numbers Doc Issue 495 Add power se
8. USB2CIk DO7 OVpp A08 GND Bos GPIO13 C08 PerData28 Dog OVpp A09 PSROUser B09 GPIOO5 Cog GPIO02 Dog GND A10 GPIO14 B10 GPIO15 C10 SysCik D10 Vpp A11 SAGND B11 PerReady C11 GPIO12 D11 GPI007 A12 SAVpp B12 GPIOO1 C12 GPIO06 D12 EOVpp A13 GND B13 PerData15 C13 GPIO04 D13 OVpp A14 PerData13 B14 PerData12 C14 PerData14 D14 GND A15 PerData11 B15 PerData09 C15 PerData10 D15 Vop A16 GPIO00 B16 PerData07 C16 PerData06 D16 PerData04 A17 PerData08 B17 PerData05 C17 PerData02 D17 Vop A18 PerData03 B18 PerData01 C18 PerData00 D18 GND A19 GND B19 ExtReset C19 PerErr D19 OVpp A20 PerCik B20 GPIO10 C20 GPIO08 D20 OVpp A21 PerCs2 B21 PerCS0 C21 PerWBE1 D21 PerBLast A22 PerWBE3 B22 PerWBE2 C22 PerAddr31 D22 OVpp A23 PerWBEO B23 PerRW C23 PerAddr30 D23 GND A24 PerOE B24 PerAddr29 C24 GND D24 PerAddr26 A25 PerAddr28 B25 GND C25 PerAddr25 D25 PerAddr22 A26 GND B26 PerAddr27 C26 PerAddr21 D26 PerAddr19 32 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 4 Signals Listed by Ball Assignment Sheet 2 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name E01 GND F01 GPIO21 G01 GPIO19 HO1 GND E02 UARTSerClk F02 G
9. ge vad bd AA not SVop EOVop oa Total Unit Notes 1 2V 1 3V with DDR1 AHVpp SAVpp EAVpp 333 1 89 na na 0 65 0 15 2 69 Ww 1 2 400 2 07 na na 0 72 0 15 2 94 W 1 3 533 na 2 90 na 0 72 0 17 3 79 W 1 4 Notes 1 Maximum power is measured on a best case process worst case power part at a case temperature of 85 C at the specified voltages while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB and Security 2 DDR1 running at 333MHz PLB running at 166MHz DDR1 running at 400MHz PLB running at 200MHz 4 DDR1 running at 355MHz PLB running at 177MHz oo 52 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 14 Typical DC Power Supply Requirements with DDR2 SDRAM Abra en ee ey SVostEOVopt ove Total Unit Notes HASV 1 25V AHVpp SAVpp EAVpp 333 0 97 na 0 21 0 18 0 11 1 47 w 1 2 400 1 09 na 0 26 0 18 0 11 1 64 w 1 3 533 na 1 46 0 21 0 19 0 11 1 97 W 1 4 Notes 1 Typical power is measured on a typical process part at a case temperature of 85 C at the specified voltages while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB and Security 2 3 4 DDR2 running at 333MHz PLB running at 166MHz DDR2 running at 400
10. 4 Signals Listed by Ball Assignment Sheet 4 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name NO1 Reserved P01 AVpp R01 AGND T01 AVpp N02 Reserved P02 Reserved R02 Reserved T02 Reserved N03 AVpp P03 Reserved R03 Reserved T03 Reserved N04 AVpp P04 AGND R04 AHVpp T04 Reserved NO5 No ball P05 No ball R05 No ball T05 No ball N06 No ball P06 No ball R06 No ball TO6 No ball NO7 No ball P07 No ball R07 No ball T07 No ball NO8 No ball P08 No ball R08 No ball T08 No ball Nog No ball P09 No ball R09 No ball T09 No ball N10 No ball P10 No ball R10 No ball T10 No ball N11 Vop P11 GND R11 OVpp T11 GND N12 GND P12 GND R12 GND T12 EOVpp N13 GND P13 GND R13 GND T13 Vop N14 GND P14 GND R14 GND T14 GND N15 GND P15 GND R15 GND T15 SVpp N16 GND P16 Vop R16 SVop T16 GND N17 No ball P17 No ball R17 No ball T17 No ball N18 No ball P18 No ball R18 No ball T18 No ball N19 No ball P19 No ball R19 No ball T19 No ball N20 No ball P20 No ball R20 No ball T20 No ball N21 No ball P21 No ball R21 No ball T21 No ball N22 No ball P22 No ball R22 No ball T22 No ball N23 SVpp P23 GND R23 Vpp T23 Surer 1B N24 MemData01 P24 MemData03 R24 MemData08 T24 MemData09 N25 MemData06 P25 MemData02 R25 MemData12 T25 DQS1 N26 GND P26 MemData07 R26 MemData13 T26 DM1 AMCC Proprietary 35 PPC405EXr PowerPC 405EXr Embedded Process
11. 43 TmrCik D06 TMS Vo1 JTAG 42 TrcCik L24 Trace 43 TRST Yo01 JTAG 42 TS0 PerAddr08 DMAReg3 J25 TS1 PerAddr07 DMAAckO J26 Trace 43 TS2 PerAddro6 DMAReq0 K25 TS3 PerAddr05 GPIO26 DMAEOTO K26 AMCC Proprietary 29 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 13 of 14 Signal Name Ball Interface Group Page TSOE PerAddr10 J24 TSOO PerAddr12 H24 Trace 43 TS1E PerAddr09 H25 TS10 PerAddr11 G26 UARTOCTSJGPIO18 G02 UARTODCD UART1CTS GPIO16 F04 UARTODSR UART1RTS GPIO17 F02 UARTODTR UART1Tx GPIO20 F03 za UART Peripheral 46 UARTORI UART1Rx GP1021 F01 UARTORTSJGPIO19 G01 UARTORx G03 UARTOTx H02 UART1CTS UARTODCD GPIO16 F04 UART1RTS UARTODSR GPIO17 F02 UART Peripheral 46 UART1Rx UARTORI GPIO21 F01 UART1Tx UARTODTR GPIO20 F03 UARTSerClk E02 UART Peripheral 46 USB2CIk C07 USB 2 0 46 USB2Data0 PerData16 GPIO12 C11 USB2Data1 PerData17 GPIO13 B08 USB2Data2 PerData18 GPIO14 A10 USB2Data3 PerData19 GPIO15 B10 USB 2 0 46 USB2Data4 PerData20 GPIO04 C13 USB2Data5 PerData21 GPIO05 Bog USB2Data6 PerData22 GPI006 C12 USB2Data7 PerData23 GPIO07 D11 USB2Dir PerData24 A07 USB2Next PerData26 B06 USB 2 0 46 USB2Stop PerData25 B07 30 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedd
12. 6 dB Receiver DC common mode impedance 40 60 Q DC differential inpedance 80 120 Q Rx AC common mode voltage 150 mV DC Input CM input impedance during reset or power down 200 kQ Electrical idle detect threshold 65 125 ns Table 29 PCI E Reference Clock I O Specifications Parameter Minimum Maximum Units Notes PCI E reference clock frequency PCIENCIKC and PCIENCIKT 100 100 MHz 1 Accuracy 300 300 ppm Duty cycle 45 55 Peak to peak jitter for 1E 6 BER 1 x 10 bit error rate 86 ps 3 Spread Spectrum Clock SSC frequency 30 33 kHz 2 Common mode voltage 0 1600 mV Differential signal amplitude 200 1600 mV Notes 1 The PCI E reference clock frequency specification does not include 300ppm accuracy specification 2 The data rate can be modulated from 0 5 to 0 5 of the nominal data rate frequency at a modulation rate in the range not exceeding 30kHz 33kHZz The 600ppm requirement remains which requires the two communcicating ports to be modulated so that they never exceed a total of 600 ppm difference For most implementations this requires that both ports have the same bit rate clock source when the data is modulated with an SSC 3 1E 6 is the probability that the jitter is greater than 86ps peak to peak 70 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 30 PCI E Transmitter I O Specifications
13. Inbound Memory Regions 4 Memory 1 I O 1 Expansion ROM e INTx Interrupts support PCI legacy Up to four INTx Termination for Root Ports A B C D interrupts are wired to the UIC A B C D INTx types Generation for Endpoints e MSI Message Signaled Interrupts MSI Generation for End Point MSI Termination for Root Ports MSI_X Termination for Root Ports Security Function The built in security function is a cryptographic engine attached to the 128 bit PLB with built in DMA and interrupt controllers Features include e Federal Information Processing Standard FIPS 140 2 design e Support for an unlimited number of Security Associations SA e Different SA formats for each supported protocol IPsec SSL TLS DTLS MACSec SGT L2 L3 and sRTP e Internet Protocol Security IPSec features Full packet transforms ESP 8 AH Complete header and trailer processing IPv4 and IPv6 Multi mode automatic padding Mutable bit handler for AH including IPv4 option and IPv6 extension headers e Secure Socket Layer SSL Transport Layer Security TLS and Datagram Transport Layer Security DTLS Packet transforms One pass hash then encrypt or decrypt then hash for SSL TLS and DTLS packet transforms using ARC4 Stream Cipher 12 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet e Secure Real Time Protocol sRTP features Packet
14. USB 2 0 On the Go OTG controller that can be configured as either a Host or Device port Features include e Low Host only Full and High Speed support e Internal DMA to optimize performance and offload the CPU Up to two IN OUT Endpoints in Device mode one can be isochronous e Supports maximum packet size of 1024 B isochronous and 512B bulk Support for isochronous traffic Three packets per microframe 24 MB s throughput Eight KB buffer e ULPI SDR interface DDR1 2 SDRAM Controller The Double Data Rate 1 2 DDR1 2 SDRAM memory controller supports industry standard discrete devices that are compatible with both the DDR1 or DDR2 specifications The correct I O supply voltage must be provided for the two types of DDR devices DDR1 devices require 2 5V and DDR2 devices require 1 8V Global memory timings address and bank sizes and memory addressing modes are programmable Features include 16 or 32 bit memory interface e Optional 8 bit error checking and correcting ECC e 1 6 GB s peak data rate Two memory banks of up to 1 GB each e Maximum capacity of 2GB Support for one memory bank of 2GB with CAS latencies of 2 2 5 or 3 e Clock frequencies from 133 MHz 266 Mbps to 200 MHz 400 Mbps supported Faster parts may be used but must be clocked no faster than 200 MHz Page mode accesses up to 16 open pages with configurable paging policy Programmable address mapping and timing Software initiated self
15. Voltage AVpp 0 to 41 6 V 1 PCI Express SerDes PLL Analog Supply Voltage AHVpp 0 to 42 6 V 1 O Supply Voltage OVpp 0 to 43 6 V SDRAM DDR1 2 Supply Voltage SVpp 0 to 42 6 1 9 V Ethernet I O Supply Voltage EOVpp 0 to 2 6 V System PLL Analog Supply Voltage SAVpp 0 to 2 6 V 1 Ethernet PLL Analog Supply Voltage EAVpp 0 to 2 6 V 1 Input Voltage 3 3V LVTTL receivers Vin 0 to 3 6 V Storage Temperature Range TsTG 55 to 150 C Case Temperature Range under bias To 40 to 120 C Junction Temperature Range TJMax 40 to 125 C 2 Notes 1 The analog voltages can be derived from the 1 2V and 2 5V supplies but must be filtered as shown below before entering the PPC405EXr Use a separate filter for each voltage This circuit can be used for AVpp AHVpp SAVpp and EAVpp VDD o L 00007 O AVpp L1 Murata BLM18AG121SN1D AS Gi C1 0 1 pF ceramic 2 The device meets all electrical specifications at a junction temperature under bias of 125 C but part lifetime and reliability is reduced lt is recommended that prudent thermal management techniques be used to maximize device lifetime 48 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 9 Package Thermal Specifications The PPC405EXr is designed to operate within a case temperature range Te defined in Recommended DC Operating Conditions on page 50 The
16. chip are not functional However most of the reserved balls cannot be left unconnected Connect the balls shown in the following table as indicated Table 6 Non Functional Ball Connections Ball Connection NO1 GND N02 GND P02 Open P03 Open R02 GND R03 GND T02 GND TO3 GND T04 GND AD12 Open 40 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Signal Functional Descriptions The following table provides a description of the I O signals on the PPC405EXr Table 7 Signal Functional Description Sheet 1 of 7 Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description I O Type Notes Ethernet Interface a 3 3V tolerant GMCCD GMII MII Collision detect 2 5V CMOS 1 5 3 3V tolerant GMCCrS GMII MII Carrier sense 1 0 2 5V CMOS 1 GMCGTxCIk GMII MII Transmit clock for GMII 1000 Mbps O 3 3V tolerant GMCOTxCIk RGMII 0 Transmit clock 2 5V CMOS 3 3 V tolerant GMCMDCIk Management
17. data clock O 2 5V CMOS 3 3V tolerant GMCMDIO Management data I O 1 0 2 5V CMOS 3 3 V tolerant GMCRefCIk GMII MII RGMII Required 125 MHz reference clock 2 5V CMOS 1 5 receiver GMCRxClk GMII MII Receive clock 3 3V tolerant 1 5 GMCORxClk RGMII 0 Receive clock 2 5V CMOS i GMCRxDO 3 GMII MII Receive data 3 3 V tolerant 1 GMCORxDO 3 RGMII 0 Receive data 2 5V CMOS S F 3 3V tolerant GMCRxD4 7 GMII MII Receive data 2 5V CMOS 1 GMCRxDV GMII MII Receive data valid 3 3V tolerant 1 GMCORxCtl RGMII 0 Receive control 2 5V CMOS y 3 3V tolerant GMCRxEr GMII MII Receive error 2 5V CMOS 1 GMCTXCIk GMII MII Transmit clock for 10 100 Mbps SOV to erant 1 5 pS 2 5V CMOS GMCTxDO 3 GMII MII Transmit data O 3 3V tolerant GMCOTxD0 3 RGMII 0 Transmit data 2 5V CMOS l 3 3V tolerant GMCTxD4 7 GMII MII Transmit data O 2 5V CMOS GMCTxEn GMII MII Transmit enable o 3 3V tolerant GMCOTxCtl RGMII 0 Transmit control 2 5V CMOS 3 3V tolerant GMCTxEr GMII MII Transmit error O 2 5V CMOS IIC Interface IICOSCIk IIC Serial Clock 1 0 3 3V LVTTL 1 2 IICOSData IIC Serial Data 1 0 3 3V LVTTL 2 IIC1SCIk IIC Serial Clock 1 0 3 3V LVTTL 1 IIC1SData IIC Serial Data 1 0 3 3V LVTTL 1 AMCC Proprietary 41 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 2 of 7 Notes 1 Receiver input has hysteresis 2 Must pull
18. following describes the method by which initial chip settings are established when a system reset occurs Strapping When the SysReset input is driven low system reset the state of certain I O pins is read in order to enable default initial conditions before PPC405EXr start up The actual instant of capture is the nearest system clock edge before the deassertion of reset These pins must be strapped using external pull up logical 1 or pull down logical 0 resistors to select the desired default conditions The recommended pull up is 3kQ to 3 3V or 10kQ to 5V The recommended pull down is 1kQ to GND These pins are only used for strap functions during reset They are used for other signals during normal operation The following table lists the strapping pins along with their functions and strapping options The signal names assigned to the pins for normal operation appear below the pin number Table 31 Strapping Pin Assignments Pin Strapping Initialization Source Option U oe U rn U ROCES EBC 8 bit wide ROM A 0 0 0 EBC 16 bit wide ROM B 0 0 1 EBC 16 bit wide ROM C 0 1 0 EBC 8 bit wide NAND Flash D 0 1 1 EBC 8 bit wide NAND Flash E 1 0 0 IIC ROM at address 0xA8 G 1 0 1 EBC 8 bit wide ROM F 1 1 0 IIC ROM at address 0xA4 H 1 1 1 Note See the PPC405EXr Embedded Processor User s Manual tor option descriptions and other details regarding the boot process 72 AMCC Proprietary PPC405EXr
19. function The flexibility of sharing allows a single chip to offer a richer pin selection than would otherwise be possible Initialization Strapping One group of pins is used as strapped inputs during system reset These pins function as strapped inputs only during reset and are used for other functions during normal operation see Initialization on page 72 Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable Pull Up and Pull Down Resistors Pull up and pull down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state The recommended pull up value of 3kQ to 3 3V and pull down value of 1kQ to GND applies only to individually terminated signals To prevent possible damage to the device I Os capable of becoming outputs must never be tied together and terminated through a common resistor If your system level test methodology permits input only signals can be connected together and terminated through either a common resistor or directly to 3 3V or GND When a resistor is used its value must ensure that the grouped l Os reach a valid logical zero or logical one state when accounting for the total input current into the PPC405EXr AMCC Proprietary 39 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Reserved Balls The balls marked Reserved on this
20. information between the processor and the other on chip peripheral functions PLB The Processor Local Bus PLB is a high performance on chip bus used to connect PLB equipped master and slave devices to the PPC405 CPU It provides a 128 bit data path with 64 bit addressing and operates up to 200MHZ There are bridges between the PLB and the OPB Features include e Separate and simultaneous 6 4GB s read and write data paths e Decoupled address and data buses Address pipelining Late master request abort capability Hidden overlapped bus request grant protocol e Bus arbitration locking mechanism e Byte enable capability allows for unaligned half word transfers and 3 B transfers Support for 32 and 64 B burst transfers Read word address capability e Sequential burst protocol e Guarded and unguarded memory transfers e Simultaneous control address and data phases e DMA buffered flyby peripheral to memory memory to peripheral and DMA memory to memory operations AHB The Advanced High Performance Bus AHB is dedicated to the USB OTG 2 0 Features include 32 bit data path 32 bit address e Synchronous to the PLB From 60MHz to 100MHz AMCC Proprietary 9 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet OPB The OPB provides 32 bit address and data interfaces and operates up to 100MHz There are bridges between the OPB and the PLB Features include
21. is edge aligned with DQS To capture the incoming data on the rising and falling edges DQS is delayed by the DDR controller in order to center a DQS edge on valid data Programmable registers control the delay DDR SDRAM MemCIkOut0 and Read Clock Delay In order to accommodate timing variations introduced by memory layout and process a three stage data path is used to eliminate metastability and allow data sampling to be adjusted for minimum latency Figure 10 shows the data read path of a single data bit Data entering on the left is captured in the Stage 1 Flip Flops Four Flip Flops are needed to capture an entire four beat burst on the DDR interface The DDR controller only supports burst of four Data captured on the rising edge of DQS is stored in the even numbered Flip Flops Like wise data captured on the falling edge of DQS is stored in the odd numbered Flips Flops To latch the data in Stage 1 a delayed version of DQS is used Initialization software is responsible for tuning the DQS delay timing so that DQS is centered on valid data Since there is process variation between parts and possible voltage variations on boards read tuning is required Fixed DQS delay values should not be used on production systems The Feedback Data Capture Window selects which Flip Flop is used to store the data sampled by DQS Each output of this block generates a pulse to an input multiplexer The series of four pulses selecting the input multiplexer is
22. storing the data in Stage 1 68 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Figure 12 DDR SDRAM Read Cycle Timing Example Oversampling Guard Band DDR 1X Clock DDR 2X Clock MemClkOut0 Diff f A f DQS at Pin Ley I 1 kue EU A ae ee ps Da Y os X ve Y or Y os Y bs Y Store 1st Data ABREGO Ti T2 T3 T4 Data at Pin y DO or A D2 MemFBR at Pin NG gt DDR 1X Clock cycle Delayed DQS Data Out Stage 1 0 Data Out Stage 1 1 Data out Stage 1 2 Valid High I DO Y D2 Data Out Stage 2 Low D1 D3 AMCC Proprietary 69 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet PCI Express PCI E I O Specifications The following tables provide the required I O timing information regarding the use of the PCI Express interface on this chip Table 28 PCI E Receiver I O Specifications Parameter Minimum Maximum Units Notes Unit Interval Ul 399 88 400 12 ps Differential Rx peak peak voltage 175 1200 mV Receiver eye time opening 0 4 Ul Maximum time delta between median and deviation from median 0 3 Ul Rx differential return loss 10 dB Common mode Rx return loss
23. up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description 1 0 Type Notes PCI Express Interface PCIEOATB Analog Test Bus for manufacturing test na Analog PCIEOCIKC ws PCIEOCIKT Differential input for external reference clock CML 5 PCIEORExt External reference resistor Attach a 1 37 kQ 1 resistor between PCIENREXIG RExt and RExtG to provide the reference for both the bias currents na Analog and the impedance calibration circuitry PCIEORx Differential receiver for received serial data LVDS PCIEORx Note Input must be DC coupled and biased to OV common mode REM PCIEOTx Differential driver for transmitted serial data O LVDS driver PCIEOTx Note Output must be AC coupled ba Interrupts Interface IRQ0 2 External interrupt requests 3 3V LVTTL IRQ3 5 External interrupt requests 3 3V LVTTL 1 IRQ6 External interrupt requests 3 3V LVTTL IRQ7 9 External interrupt requests 3 3V LVTTL 1 JTAG Interface TCK Test clock 3 3V LVTTL 1 3 3V LVTTL TDI Test data in l w pull up 1 4 TDO Test data out O 3 3V LVTTL 3 3V LVTTL TMS Test mode select w oull up 1 TRST Test r
24. 08 Preliminary Data Sheet Figure 10 DDR SDRAM Read Data Path for a Single Data Bit FF Flip FI DDR 1X Clock PEER Ext FeedBack Signals MemFBD Driver Coarse Delay ae CAS Lat Delay _ Read Start DDR 1X Clock Read Latency adjust circuit Rec J E wv th gt Fine Delay Stage 2 Store Oversampling WA MemFBR DOS aligned Cycles IL 1 Fine Delay an feedback signal Delay Guard Band Data Capture l TI T2 1314 TUT On time sample clock F kaaa A 7 t 0 P Oversampling 2 I Clock 3 Q2 Ovs Package A O pins FF Ta FF Qe Compare Qs FF gt PLB bus D x64 ECC Read FIFO gt 0 63 oe Mux Upper U DQS Rising MemData gt Edge Sync Stage 1 Stage 2 Stage 3 x32 bits y 2 LONG x8 bits ECC FF 7 FF Q3 pg gt a2 x64 ECC cr PLB bus 4 127 Mux 6 C 7 Mux Programmed O DOS Read DAS a ae x4 x1 Delay ECC bits DDR 1X Clock PLB 1X Clock ECC detection and correction if enabled occurs after Stage 3 before completing the read on the PLB DDR SDRAM Read Cycle Timing The following diag
25. 1 5 1 11 08 7 37 PerCik ExtReq 2 1 5 3 na na PerClk NFALE 5 3 1 11 08 7 37 PerClk NFCE0 3 5 3 1 11 08 7 37 PerCik NFCLE 5 3 1 11 08 7 37 PerCik NFData0 15 2 3 1 5 3 1 11 08 7 37 PerCik NFRdyBusy 1 7 1 na na PerClk NFREn 5 3 1 11 08 7 37 PerClk NFWEn 5 3 1 11 08 7 37 PerCik AMCC Proprietary 61 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet DDR 2 1 SDRAM I O Specifications The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from the PLB clock The PLB clock is an internal signal that cannot be directly observed However MemClkOut is the same frequency as the PLB clock signal and is in phase with the PLB clock signal Note MemClkOut can be advanced with respect to the PLB clock by means of the SDRAMO_CLKTR programming register In a typical system users advance MemClkOut by 90 This depends on the specific application and requires a thorough understanding of the memory system in general refer to the DDR SDRAM Controller chapter in the PPC405EXr Embedded Processor User s Manual The signals are terminated as indicated in Figure 8 for the DDR timing data and output currents in the following sections Figure 8 DDR SDRAM Simulation Signal Termination Model MemCIkOut0 o o AR 10pF no ib 1200 10pF MemCIkOut0 o o Ver SOVpp 2 PPC405EXr 500 Addr Ctrl DDR2 Addr Ctrl Data DQS DM DDR1 30pF
26. 2Data6 C12 PerData23 GPIO07 USB2Data7 D11 PerData24 USB2Dir A07 PerData25 USB2Stop B07 PerData26 USB2Next B06 PerData27 NFREn A05 PerData28 NFWEn C08 PerData29 NFCLE A06 PerData30 NFALE C06 PerData31 NFRdyBusy A04 PerDataPar0 GPIO00 A16 PerDataPar1 GPIO01 B12 a External Peripheral 44 PerDataPar2 GPIO02 C09 PerDataPar3 GPIO03 B04 PerErr C19 PerOE A24 External Peripheral 44 PerReady B11 PerRW B23 PerWBEO A23 PerWBE1 C21 External Peripheral 44 PerWBE2 B22 PerWBE3 A22 PSROUser A09 System 43 RAS AD19 DDR 2 1 SDRAM 45 28 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 12 of 14 Signal Name Ball Interface Group Page Reserved NO1 Reserved No2 Reserved P02 Reserved P03 Reserved R02 Other 47 Reserved R03 Reserved T02 Reserved T03 Reserved T04 Reserved AD12 SAGND A11 SAVpp A12 Power 47 SCPCIkOut IIC1SCIk AA02 SCPDI AA03 Serial Communication Port 46 SCPDO IIC1SData AA04 SVpp N23 SVpp R16 SVpp T15 SVop W23 SVpp Power 47 SVpp AB23 SVop AC19 SVpp AC20 SVpp AC22 SVpp AD14 Syref1A AC14 Svaer1P i DDR2 1 SDRAM 45 Syrer2A AC16 Svrer2B L23 SysClk C10 SysErr AD06 System 43 SysReset ADOS TCK V02 TDI Wo2 JTAG 42 TDO W03 TestEn Y02 System
27. 2kB 64B device page sizes supported e ECC generation hamming code single bit correction double bit detection SEC DED Eight bit command write address write and data read write Interrupt on device ready after long page write or block erase operations Boot from NAND Executes up to 4KB of boot code out of first block Automatic page read accesses performed based on device configuration and read address DMA Controller The Direct Memory Access DMA controller is a Processor Local Bus PLB master that enables faster data transfer between memory and peripherals than is possible under program control The 4 channel DMA controller handles data transfers between memory and peripherals and from memory to memory Each channel has an 10 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet independent set of registers needed for data transfer a control register a source address register a destination address register and a transfer count register Features include e Memory to memory transfers Buffered memory to peripheral transfers e Buffered peripheral to memory transfers Four independent DMA channels e Scatter gather capability for dynamically programming multiple DMA transfers e Programmable address increment or decrement Internal data buffering e Can transfer data to from any PLB slave including the external bus USB 2 0 OTG Interface One
28. 3 3V LVTTL SCPDO Data output O 3 3V LVTTL UART Peripheral Interface The UART interface can be configured as follows 1 One 8 pin 2 Two 4 pin 3 Two 2 pin pull up DCD DSR CTS and RTS 4 One 4 pin and one 2 pin 3 3V LVTTL UARTSerClk Serial clock input receiver 4 w pull up UARTnCTS Clear to send l 3 3V LVTTL 1 6 UARTnDCD Data carrier detect l 3 3V LVTTL 1 6 UARTNDSR Data set ready l 3 3V LVTTL 1 6 UARTNDTR Data terminal ready O 3 3V LVTTL 1 UARTnRI Ring indicator I 3 3V LVTTL 1 UARTNATS Request to send O 3 3V LVTTL 1 UARTnRx Receive data 3 3V LVTTL UARTnTx Transmit data O 3 3V LVTTL USB 2 0 Interface USB2CIk USB clock pl eee 5 USB2Data0 7 Parallel data bus 1 0 3 3V LVTTL USB2Dir Data bus direction control I 3 3V LVTTL Next data byte control When data is being transferred to the PHY USB2Next the next byte should be sent When data is being received from the 3 3V LVTTL PHY the next byte is available USB2Stop Stop output control O 3 3V LVTTL 46 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 7 of 7 Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommend
29. B peripherals It is an easily programmable general purpose 32 bit RISC controller that offers an upgrade path for applications One one lane PCI Express interfaces operating up to 2 5 Gbps One Gigabit Ethernet interfaces half and full duplex to external PHY GMII MI RGMII e USB 2 0 OTG port configurable as either Host or Device e Programmable universal interrupt controller UIC General Purpose Timer GPT Up to two serial ports 16750 compatible UART Two IIC interfaces operating up to 400kHz and supporting all standard IIC EEPROMs e One SCP SPI synchronous full duplex channel operating up to 25 MHz e General purpose I Os GPIOs each with programmable interrupts and outputs Supports JTAG for board level testing e System power management low power dissipation and small form factor Available in a ROHS compliant lead free package in need of performance and connectivity improvements Technology Cu 08 CMOS 90nm Package 388 ball 27mm x 27mm enhanced plastic ball grid array EPBGA 1mm ball pitch Power consumption typically less than 2W at all speeds Voltages required 3 3V 2 5V 1 8V DDR2 SDRAM only and 1 2V AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table of Contents Features aid iS kN eee as 1 Description dcir A dr Lea bh AA AAA AAA ES 1 Table of Gontents iaai Man 38 oe ee died A Da BR AN
30. BA1 AE25 GND AF25 MemFBR AE26 MemAddr08 AF26 GND 38 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Pin Group List The following table provides a summary of the number of package pins balls associated with each functional interface group Table 5 Pin Groups Group No of Pins Total Signal Pins 237 Vop 17 OVpp 20 EOVpp 6 sm 149 GND 71 AVpp 7 AHVop 2 SAVpp 1 SAGND 1 EAVpp 1 EAGND 1 AGND 4 Total Power Pins 141 Reserved 10 Total Pins 388 In the table Signal Functional Description on page 41 each external signal is listed along with a short description of the signal function Active low signals for example Halt are marked with an overline See the preceding table Signals Listed Alphabetically on page 18 for the pin ball number to which each signal is assigned Shared Pins Some signals are shared on the same package pin so that the pin can be used for different functions In most cases the signal names shown in this table are not accompanied by signal names that might share the same pin If you need to know what if any signals are shared with a particular signal look up the name in Signals Listed Alphabetically on page 18 It is expected that in any single application a particular pin will always be programmed to serve the same
31. CC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 8 of 14 Signal Name Ball Interface Group Page MemData00 M24 MemData01 N24 MemData02 P25 MemData03 P24 MemData04 L25 MemData05 L26 MemData06 N25 MemData07 P26 MemData08 R24 MemData09 T24 MemData10 V26 MemData11 U24 MemData12 R25 MemData13 R26 MemData14 U26 MemData15 U25 MemData16 AE17 DDR2 1 SDRAM 45 MemData17 AF17 MemData18 AE15 MemData19 AF15 MemData20 AF18 MemData21 AD17 MemData22 AF16 MemData23 AD15 MemData24 AE13 MemData25 AF12 MemData26 AF10 MemData27 AD11 MemData28 AE14 MemData29 AF13 MemData30 AF11 MemData31 AE11 MemFBD AD23 MemFBR AF25 MemODTO AD18 DDR2 1 SDRAM 45 MemODT1 AE18 AMCC Proprietary 25 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 9 of 14 Signal Name Ball Interface Group Page NFALE PerData30 C06 NFCEO PerCso B21 NFCE1 PerCS1 GPIOO8 IRQ7 C20 NFCE2 PerCS2 GPI009 IR 8 A21 NFCE3 PerCS3 GPIO10 IRQ9 B20 NFCLE PerData29 A06 NFDa
32. DDR SDRAM Tos Notes 1 All of the DQS signals are referenced to MemCIkOut0 with the DQS delay line programmed to 1 cycle 2 Clock speed is 200MHz E Tos ns Signal Name Pi Minimum Maximum DQSO 4 6 DQS1 4 6 DQS2 4 6 DQS3 4 6 DQS4 4 6 64 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 25 VO Timing DDR SDRAM Tgp and Tha Signal Name Tsa ns Minimum Tua ns Minimum MemAddr00 14 1 08 1 12 BAO 2 1 12 1 15 BankSel0 1 1 09 1 13 MemCIkEn 1 10 1 16 CAS 1 10 1 13 RAS 1 09 1 12 WE 1 08 1 16 Table 26 I O Timing DDR SDRAM Write Timing Tsp and Typ Notes 1 Tsp and Typ are measured under worst case conditions 2 Clock speed for the values in the table is 200 MHz 3 The time values in the table include 1 4 of a cycle at 200 MHz 5ns x 0 25 1 25 ns 4 To obtain adjusted Tsp and Typ values for lower clock frequencies subtract 1 25 ns from the values in the table and add 1 4 of the cycle time for the lower clock frequency for example Tsp 1 25 0 25Teyg Signal Names Reference Signal Tsp ns Tup ns MemData00 07 DMO DQSO 1 067 0 973 MemData08 15 DM1 DQS1 1 074 0 973 MemData16 23 DM2 DQS2 1 082 0 973 MemData24 31 DM3 DQS3 1 088 0 973 ECCO 7 DM4 DQS4 1 012 0 973 DDR SDRAM Read Operation Data on a read
33. DRAM 45 DMO M25 DM1 T26 DM2 AD16 DDR 2 1 SDRAM 45 DM3 AD13 DM4 Y26 DMAAck0 PerAddr07 TS1 J26 DMAAck1 GPI031 IRQ0 D01 DMA 44 DMAAck2 HoldReq GP1022 B05 DMAAck3 ExtAck GPIO25 IRQ3 C04 DMAEOTO PerAddr05 GPIO26 TS3 K26 DMAEOT1 GPIO29 IRQ2 D03 DMA 44 DMAEOT2J ExtReq GPIO24 IRQ4 A03 DMAEOT3 BusReq GPI027 IRQ5 B03 DMAReqo PerAddrO6 TS2 K25 DMAReq1 GPIO30 IRQ1 D02 BMA j DMAReq2 HoldAck GPI023 C05 DMAReg3 PerAddr08 TS0 J25 18 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 2 of 14 Signal Name Ball Interface Group Page DQSO M26 DQS1 T25 DQS2 AE16 DDR 2 1 SDRAM 45 DQS3 AE12 DQS4 Y25 EAGND AE07 Power 47 EAVpp AE08 ECCO V24 ECC1 W24 ECC2 AB26 ECC3 AB25 DDR 2 1 SDRAM 45 ECC4 V25 ECC5 W25 ECC6 AA26 ECC7 AA25 EOVpp D12 EOVpp T12 EOVpp ACO5 Power 47 EOVpp AB04 EOVpp ACO7 EOVpp AC08 EXtAck GPI025 DMAAck3 IRQ3 C04 ExtReq GPIO24 DMAEOT2 IRQ4 A03 External Bus Master 44 ExtReset B19 AMCC Proprietary 19 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 3 of 14 Signal
34. Device operation beyond the conditions specified is not recommended Extended operation beyond the recommended conditions can affect device reliability Parameter Symbol Minimum Typical Maximum Unit Notes Logic Supply Voltage 333 MHz 8 400MHz Vpp 1 1 1 15 1 2 V 2 Logic Supply Voltage 533 MHz Vop 1 2 1 25 1 3 V I O Supply Voltage OVpp 3 15 3 3 3 45 V SDRAM DDR1 2 Supply Voltage SVpp 2 4 41 7 2 5 1 8 2 6 1 9 V Ethernet I O Supply Voltage EOVpp 2 4 2 5 2 6 V AHVpp PLL Analog Supply Voltage SAVpp 2 4 2 5 2 6 V EAVpp Analog Supply Voltage 333 MHz amp 400 MHz AVpp 1 1 1 15 1 2 V 2 Analog Supply Voltage 533 MHz AVpp 1 2 1 25 1 3 V I O Input Low 3 3V LVTTL Vi 0 0 8 V I O Input High 3 3V LVTTL Vin 2 0 3 6 V I O Output Low 3 3V LVTTL VoL 0 0 4 V I O Output High 3 3V LVTTL VoH 2 4 3 6 v 1 0 Input Low 3 3V tol 2 5V CMOS Vi 0 0 7 V I O Input High 3 3V tol 2 5V CMOS ViH 1 7 3 6 v I O Output Low 3 3V tol 2 5V CMOS VoL 0 0 4 V I O Output High 3 3V tol 2 5V CMOS Vou 2 0 2 7 V I O Input Low DDR1 2 SSTL2 Vi 0 3 PE er V VO Input High DDR1 2 SSTL2 Vi a SVop 0 3 v I O Output Low DDR1 2 SSTL2 VoL See JESD8 9 JESD8 15A standard V I O Output High DDR1 2 SSTL2 Vou See JESD8 9 JESD8 15A standard V a to o 1 ua fh mera pulkdown IE 0 LPDL 200 MPUL pA 1 A na 1SO POL owpuy ma
35. Figure 3 Clocking Waveform 2 0V 1 5V 0 8V AMCC Proprietary 55 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Spread Spectrum Clocking Care must be taken if using a spread spectrum clock generator SSCG with the PPC405EXr This controller uses a PLL for clock generation inside the chip The accuracy with which the PLL follows the SSCG is called tracking skew The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the PLL for a given frequency deviation and modulation frequency If using an SSCG with the PPC405EXr the following conditions must be met The frequency deviation must not violate the minimum clock cycle time Therefore when operating the PPC405EXr with one or more internal clocks at their maximum supported frequency the SSCG can only lower the frequency The maximum frequency deviation must not exceed 3 and the modulation frequency must not exceed 40kHz In some cases on board PPC405EXr peripherals impose more stringent requirements see Note 1 Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the modulation Notes 1 The serial port baud rates are synchronous to the modulated clock The serial port has a tolerance of approximately 1 5 on baud rate before framing errors begin to occur assuming that the connected device is running at
36. G ABA LAAL 2 EIStORFIGUIES ak eyes cael A ed es al dd ay 3 LISTO TDI airada dirt RAE A A A AAA 4 Ordering PVR and JTAG Information rn nrk rn nr rn nrk rn rakne 5 Address Maps ii jaje re A RA Se ge 7 PowerPC 405 Processor n aaa aa haha dee anar a a a a a Gaal r e 9 Internal BUSES sat Arad lad E ed ters sea AN A 9 External Bus Controller 2 2 20 arv tte eee 10 NAND Flash Controller a mata paaa peaks tats eddie dele radaren ba edd deed ede spa Reeds 10 DMA Gontr ller va22le ante Sad ektet er ae ese ee ae a dee a IA ae Naan 10 USB 20 OTG Interface russer eee en te ok a Genre ee ee keen 11 DDRI 2 SDRAM Controllers coronan da a nate de ET FR ET nde EA 11 PGLEXPpr s s ard Ais 2 Stoll oe SA dyed Gb sone PAL hete 12 Security FUNCTION vi weer gar SPES A ee A RA A RR Er eS a 12 UART west nine el tha alee d Path de Pa lana hone glee des ANA ees a eaten Deka 13 NG Bus terrace TANGA eaten Ghee NAG tue A LG A eae eae ned tena 14 Serial Communication Port Interface SCP SPI ee 14 General Purpose I O GPIO Controller ooooococccococooo tte tenes 15 Universal Interrupt Controller UIC 2 2 6 tenets 15 Ethernet Controller uggs daa rer a a el ee LANA BANG Se ee ee a 15 TAG paka ad ae Goad e Heen beg AA Me Aetat serende 16 Signal lists arsen riste erte sed ee eee breve ee an 18 Signal Functional Descriptions navna r raneren teeta 41 Ratings and Specifications bicicletas da velandes a 48 Sp
37. MHz PLB running at 200MHz DDR2 running at 355MHz PLB running at 177MHz Table 15 Maximum DC Power Supply Requirements with DDR2 SDRAM dera E a P de SVog EOVgpt os Total Unit Notes 1 2V 1 3V AHVpp SAVpp EAVpp 333 1 89 na 0 21 0 26 0 15 2 51 Ww 1 2 400 2 07 na 0 22 0 26 0 15 2 70 Ww 1 3 533 na 2 90 0 29 0 26 0 17 3 62 Ww 1 4 Notes 1 Maximum power is measured on a best case process worst case power part at a case temperature of 85 C at the specified voltages while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB wm and Security DDR2 running at 333MHz PLB running at 166MHz DDR2 running at 400MHz PLB running at 200MHz DDR2 running at 355MHz PLB running at 177MHz AMCC Proprietary 53 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 16 DC Power Supply Loads with DDR1 SDRAM Parameter Symbol Typical Maximum Unit Notes Vpp 1 2V active operating current loo 1192 2220 mA 1 AVpp 1 2V active operating current lapp 4 10 mA 1 AHVpp 2 5V active operating current lAHDD 1 2 mA 1 OVpp 3 3V active operating current lopp 35 50 mA 1 SVpp EOVpp 2 5V active operating current leospD 196 235 mA 1 SAVpp 2 5V active operating current Isapp 1 2 mA 1 EAVpp 2 5V active ope
38. MMC APPLIED MICRO CIRCUITS CORPORATION Part Number 405EXr Revision 1 10 July 10 2008 405EXr Preliminary Data Sheet PowerPC 405EXr Embedded Processor Features AMCC PowerPC 405 32 bit RISC processor core operating from 333MHz to 533MHz including 16KB I and D caches with parity checking e On chip 128 bit processor local bus PLB operating up to 200MHz e On chip 32 bit peripheral bus OPB operating up to 100 MHz External 8 16 or 32 bit peripheral bus EBC operating up to 100MHz External bus master EBM operating up to 100MHz e On chip Security feature with True Random Number generation e Eight and 16 bit NAND Flash interface Inter chip connectivity SCP and IIC Boot from NOR Flash on the external peripheral bus or NAND Flash on the NAND Flash interface DMA 4 channel support for all on chip slaves and external bus UARTs and devices on the EBC e DDR1 2 SDRAM interface operating up to 400 Mbps Description With speeds up to 533 MHz a flexible off chip memory architecture and a diverse communications package that includes PCI Express USB 2 0 OTG and 10 100 1000 Ethernet the PowerPC 405EXr embedded processor provides a low power and small footprint system on a chip SOC solution for a wide range of high performance cost constrained embedded applications This includes wireless LAN applications security appliances internet appliances line cards and intelligent US
39. Name Ball Interface Group Page GMCCD AD04 GMCCrS AF04 GMCGTxClk GMCOTxClk AE04 GMCMDCIk AE03 GMCMDIO AF02 GMCRefClk ADO7 GMCRxClk GMCORXCIkK AD09 GMCRxDO GMCORxDO AC11 GMCRxD1 GMCORxD1 AE10 GMCRxD2 GMCORxD2 AD10 GMCRxD3 GMCORxD3 AFO9 GMCRxD4 AE09 GMCRxD5 AF07 GMCRxD6 AF06 Ethernet 41 GMCRxD7 AE06 GMCRxDV GMCORXxC tl AE05 GMCRxEr AF05 GMCTxClk AC06 GMCTxDO GMCOTxDO AEO1 GMCTxD1 GMCOTxD1 AD02 GMCTxD2 GMCOTxD2 ADO1 GMCTxD3 GMCOTxD3 AC03 GMCTxD4 AC02 GMCTxD5 ACO1 GMCTxD6 AB03 GMCTxD7 AB02 GMCTxEn GMCOTXxC tl AD05 GMCTxEr AF03 20 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 4 of 14 Signal Name Ball Interface Group Page GND A01 GND A08 GND A13 GND A19 GND A26 GND B01 GND B02 GND B25 GND C01 GND C02 GND C03 GND C24 GND D04 GND D09 GND D14 GND D18 GND D23 GND E01 GND E03 GND HO1 GND H26 GND J04 Power 47 GND J23 GND K24 GND L11 GND L13 GND L16 GND M12 GND M13 GND M14 GND M15 GND N12 GND N13 GND N14 GND N15 GND N16 GND N26 GND P11 GND P12 GND P13 GND P14 GND P15 GND P23 AMCC Proprietary 21 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Al
40. OM 0 FFEO 0000 0 FFFF FFFF 2MB Notes 1 If peripheral bus boot is selected peripheral bank 0 is automatically configured at reset to the address range listed above 2 After the boot process software may reassign the boot memory regions for other uses 3 PCI Express can use PLB address range 0x1 0000 0000 to OxF FFFF FFFF even though the CPU can not access it AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 2 DCR Address Map Function Start Address Hex End Address Hex Size Total DCR Address Space 0x000 0x3FF 1KW 4KB Reserved 000 00B CPR Clocking Power on Reset 00C 00D 2W System DCRs 00E 00F 2W DDR 2 1 SDRAM Controller 010 011 2W External Bus Controller EBC 012 013 2W External Bus Master EBM 014 015 2W Reserved 016 01F PLB4XAHB Bridge 020 02F 16W Reserved 030 03F PCI Express O 040 05F 32W Reserved 060 07F PLB4 Arbiter 080 08F 16W PLB to OPB Bridge 090 09F 16W OPB to PLB Bridge OAO 0A7 8W Reserved 0A8 OAF Power Management OBO 0B2 3W Reserved 0B3 OBF UIC 0 oco OCF 16W UIC 1 0DO ODF 16W UIC 2 0E0 OEF 16W Reserved OFO OFF DMA 100 13F 64W Reserved 140 17F Ethernet MAL 180 1FF 128W Reserved 200 3FF Notes 1 A DCR address is 10 bits 1024 or 1K unique addresses Each unique address represents a single 32 bit word register or one kiloword
41. PIO17 G02 GPIO18 H02 UARTOTx E03 GND F03 GPIO20 G03 UARTORx HO3 GPIO11 E04 OVpp F04 GPIO16 G04 OVpp HO4 Voo E05 No ball F05 No ball G05 No ball HO5 No ball E06 No ball F06 No ball G06 No ball HO6 No ball E07 No ball FO7 No ball G07 No ball HO7 No ball E08 No ball F08 No ball G08 No ball HO8 No ball E09 No ball F09 No ball G09 No ball H09 No ball E10 No ball F10 No ball G10 No ball H10 No ball E11 No ball F11 No ball G11 No ball H11 No ball E12 No ball F12 No ball G12 No ball H12 No ball E13 No ball F13 No ball G13 No ball H13 No ball E14 No ball F14 No ball G14 No ball H14 No ball E15 No ball F15 No ball G15 No ball H15 No ball E16 No ball F16 No ball G16 No ball H16 No ball E17 No ball F17 No ball G17 No ball H17 No ball E18 No ball F18 No ball G18 No ball H18 No ball E19 No ball F19 No ball G19 No ball H19 No ball E20 No ball F20 No ball G20 No ball H20 No ball E21 No ball F21 No ball G21 No ball H21 No ball E22 No ball F22 No ball G22 No ball H22 No ball E23 OVpp F23 PerAddr23 G23 OVpp H23 OVpp E24 PerAddr24 F24 PerAddr20 G24 PerAddr17 H24 PerAddr12 E25 PerAddr18 F25 PerAddr16 G25 PerAddr13 H25 PerAddr09 E26 PerAddr15 F26 PerAddr14 G26 PerAddr11 H26 GND AMCC Proprietary 33 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 4 Signals Listed by Ball Assignment Sheet 3 of 7
42. Package available in leaded or lead free versions 01 03 05 07 09 11 13 15 17 19 21 23 25 02 04 06 08 10 12 14 16 18 20 22 24 26 0 60 0 1 SOLDERBALL x 388 AMCC Proprietary 17 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Signal Lists The following table lists all the external signals in alphabetical order and shows the ball pin number on which the signal appears Shared signals are shown with the default signal following reset notin brackets and the alternate signal in brackets Signals that have different functions for different modes with the same function are separated by commas Shared signals appear alphabetically multiple times in the list once for each signal name on the ball The Page column indicates the page within the table Signal Functional Description on page 41 on which the signals in the indicated interface group begin Table 3 Signals Listed Alphabetically Sheet 1 of 14 Signal Name Ball Interface Group Page AGND KO1 AGND L04 Power 47 AGND P04 AGND RO1 AHVpp ba Power 47 AHVpp R04 AVpp J03 AVpp K04 AVpp MO1 AVpp NO3 Power 47 AVpp N04 AVDD Pot AVpp T01 BAO AD22 BAI AF24 DDR 2 1 SDRAM 45 BA2 AE24 Bankoalu pra DDR 2 1 SDRAM 45 BankSel1 AE20 BusReq GPIO27 DMAEOT3 IRQ5 B03 External Bus Master 44 CAS AF20 DDR 2 1 S
43. V active operating current lopp 35 50 mA 1 SVop 1 8V active operating current Ispp 145 155 mA 1 EOVpp 2 5V active operating current IEODD 76 80 mA 1 SAVpp 2 5V active operating current Isapp 1 2 mA 1 EAVpp 2 5V active operating current lEADD 1 2 mA 1 Notes 1 The maximum current values listed above are not guaranteed to be the highest obtainable These values are dependent on many factors including the type of applications running clock rates use of internal functional capabilities external interface usage case temperature and the power supply voltages Your specific application can produce significantly different results Vpp logic current and power are primarily dependent on the applications running and the use of internal chip functions DMA PCI Express Ethernet and so on OVpp I O current and power are primarily dependent on the capacitive loading frequency and utilization of the external buses The information in this table provides details about the conditions under which the listed values were obtained Maximum power is measured on a best case process worst case power part running at 533MHz with a case temperature of 85 C and with voltages of Vpp 1 30V OVpp 3 45V SVpp 2 6V and EOVpp 2 6V while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB Security 54 AMCC Proprietary PPC405EXr Po
44. cor renner renner nar ee 55 Table 20 Peripheral Interface I O Clock Timings not SDRAM or PCI E 2 57 Table 21 VO Specifications o o o o ooooo verner rn rn rn rar rn rn rn eens 60 Table 22 DDR SDRAM Output Driver Specifications cette 63 Table 23 DDR SDRAM Write Operation Conditions renere rank 63 Table 24 VO Timing DDR SDRAM Tps 2 ro vara va varar rn rar knarr knarr rn nr ran 64 Table 25 VO Timing DDR SDRAM Tga and Tha 22 varar eee 65 Table 26 VO Timing DDR SDRAM Write Timing Tsp and Typ 6 eee eee 65 Table 27 VO Timing DDR SDRAM Read Timing Tsp and Typ rava rav varar ete 68 Table 28 PCI E Receiver I O Specifications 0 00 0 cette 70 Table 29 PCI E Reference Clock I O Specifications nrk 70 Table 30 PCI E Transmitter I O Specifications A AA 71 Table 31 Strapping Pin Assignments 00 rv rn rn nrk n eee nas 72 4 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Ordering PVR and JTAG Information This section provides the part number nomenclature For availability contact your local AMCC sales office Order Part Number Rev Product Name see Notes Package Level PVR Value JTAG ID PPC405EXr PPC405EXr SpCfffT 27mm 388 ball EPBGA C 0x1291147B 0x1405B1E1 PPC405EXr PPC405EXr NpCfffT 27mm 388 ball EPBGA C 0x12911479 0
45. cted to the external pin depends 1 0 3 3V LVTTL i on the setting of bits in the GPIO registers General purpose I O Most of the GPIO signals are multiplexed with 3 3V tolerant GPIO28 other signals Which signal is connected to the external pin depends 1 0 2 5V CMOS on the setting of bits in the GPIO registers i Performance screen ring output Use for module characterization and PSROUSSr screening only A 2 Trace Interface TrcCik Trace interface clock Operates at half the CPU core frequency O 3 3V LVTTL Da Even trace execution status 1 0 3 3V LVTTL 1800 Odd trace execution status 1 0 3 3V LVTTL TS10 TS0 3 Trace status 1 0 3 3V LVTTL AMCC Proprietary 43 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 4 of 7 Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description 1 0 Type Notes External Peripheral Interface PerAddr05 31 Address bus 5 31 1 0 3 3V LVTTL PerCik Clock output O 3 3V LVTTL P
46. d asynchronous communication bits such as start stop and parity to from serial data Even odd or no parity bit generation and detection Stop bit generation of 1 1 5 or 2 bits e Variable baud rate Internal diagnostic capability e Loopback controls for isolating communications link faults Break parity overrun framing error simulation e OPB interface with optional DMA support IIC Bus Interface The Inter Integrated Circuit IIC interface provides a Philips 200 compatible interface operating up to 400kHz either as a master a slave or both with a bootstrap controller BSC included During chip reset the bootstrap controller can read configuration data from an IIC compatible memory device e g EEPROM This data can be used to replace the default configuration settings provided by the chip Features include Two IIC channels e Compliant with Philips Semiconductors FC Specification dated 1995 e Operation at 100kHz or 400kHz Byte 8 bit data Addresses are 10 or 7 bits e Slave Transmit and Receive e Master Transmit and Receive e Multiple bus masters supported e Programmable as master slave or master slave Boot parameters read from IIC attached memory Port 0 with IIC bootstrap controller e OPB slave interface is 32 bits wide Serial Communication Port Interface SCP SPI The Serial Communication Port SCP also known as the Serial Peripheral Interface or SPI is a full duplex synchronous character ori
47. dr17 G24 PerAddr18 E25 External Peripheral 44 PerAddr19 D26 PerAddr20 F24 PerAddr21 C26 PerAddr22 D25 PerAddr23 F23 PerAddr24 E24 PerAddr25 C25 PerAddr26 D24 PerAddr27 B26 PerAddr28 A25 PerAddr29 B24 PerAddr30 C23 PerAddr31 C22 PerBLast External Peripheral 44 PerClk A20 PerCSO NFCEO B21 PerCS1 NFCE1 GPIO08 IRQ7 C20 External Peripheral pa PerCS2 NFCE2 GPIO09 IRQ8 A21 PerCS3 NFCE3 GPIO10 IRQ9 B20 AMCC Proprietary 27 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 11 of 14 Signal Name Ball Interface Group Page PerData00 NFData00 C18 PerData01 NFData01 B18 PerData02 NFData02 C17 PerData03 NFData03 A18 PerData04 NFData04 D16 PerData05 NFData05 B17 PerData06 NFData06 C16 PerData07 NFData07 B16 PerData08 NFData08 A17 PerData09 NFData09 B15 PerData10 NFData10 C15 PerData11 NFData11 A15 PerData12 NFData12 B14 PerData13 NFData13 A14 PerData14 NFData14 C14 PerData15 NFData15 B13 i External Peripheral 44 PerData16 GPI012 USB2Data0 C11 PerData17 GPIO13 USB2Data1 Bos PerData18 GPIO14 USB2Data2 A10 PerData19 GPIO15 USB2Data3 B10 PerData20 GPIO04 USB2Data4 C13 PerData21 GPIOO5 USB2Data5 Bog PerData22 GPIO06 USB
48. e Pipelined read support e Dynamic bus sizing e Single cycle data transfer between masters and slaves DCR Bus The daisy chained DCR bus provides a path for passing status and control information between the processor core and the other on chip cores All DCRs are 32 bits in width with 10 bit addressing External Bus Controller The external bus controller EBC and EBM transfers data between the PLB and external memory or peripheral devices attached to the external peripheral bus The EBC provides direct attachment of memory devices such as ROM and SRAM DMA device paced memory devices and DMA peripheral devices Features include Up to 33MHz to 100 MHz speed Data bus is 8 16 or 32 bits with a 27 bit address bus Up to four chip selects e Arbitration and multi master supported e Flash ROM interface Boot from 8 or 16 bit NOR flash support e Direct support for 8 16 or 32 bit SRAM and external peripherals External bus master support NAND Flash Controller The NAND Flash controller NDFC provides a simple interface between the External Bus Controller EBC and a variety of NAND Flash based storage devices Features include Attachment as internal EBC slave device e Eight and 16 bit NAND Flash interface Up to four banks of NAND Flash supported Device sizes 4MB and larger supported for read write access 4MB to 256MB supported for boot from NAND flash size supported depends on addressing mode e 512B 16B or
49. ed Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 14 of 14 Signal Name Ball Interface Group Page Vop D10 Vpop D15 Vop D17 Vpp HO4 Vpp K23 Vpop L14 VDD M23 Vop N11 Vop P16 Power 47 Vpp R23 VDD T13 Vop U04 Vop U23 Vpp AC10 VDD AC12 Vop AC15 VDD AC17 WE AE19 DDR2 1 SDRAM 45 AMCC Proprietary 31 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet In the following table only the default signal name is shown for each ball Shared balls are marked with an asterisk To determine what signals or functions are shared on those balls look up the default signal name in Signals Listed Alphabetically on page 18 The following table lists the signals by ball assignment Table 4 Signals Listed by Ball Assignment Sheet 1 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A01 GND B01 GND C01 GND DO1 GPIO31 A02 Halt B02 GND co2 GND D02 GPIO30 A03 GPIO24 Bo3 GPI027 C03 GND D03 GPIO29 A04 PerData31 B04 GPI003 C04 GPIO25 D04 GND A05 PerData27 BOS GPIO22 C05 GPIO23 D05 OVpp A06 PerData29 B06 PerData26 C06 PerData30 D06 TmrCik A07 PerData24 B07 PerData25 C07
50. ed termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description 1 0 Type Notes Power Vop Logic Supply 1 2V na na na OVpp I O Supply 3 3V na na na SVop DDR1 2 SDRAM Supply 2 5 V or 1 8V na na na EOVop Ethernet I O Supply 2 5V na na na GND Ground na na na SAVpp System PLL Analog Supply 2 5V na na na SAGND System PLL Analog Ground na na na EAVop Ethernet PLL Analog Supply 2 5V na na na EAGND Ethernet PLL Analog Ground na na na AVpp PCI Express SerDes Analog Supply 1 2V na na na AHVpp PCI Express SerDes PLL Analog Supply 42 5 V na na na AGND PCI Express Analog Ground for AHVpp and AV pp na na na Other Reserved MN Jie ra AMCC Proprietary 47 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Ratings and Specifications Table 8 Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only Operation at or beyond these maximum ratings can cause permanent damage to the device None of the performance specification contained in this document are guaranteed when operating at these maximum ratings Characteristic Symbol Value Unit Notes Logic Supply Voltage internal logic Vop 0 to 1 6 V PCI Express SerDes Analog Supply
51. ented byte port that allows the exchange of data with other serial devices The SCP is a master on the serial port supporting a three wire interface receive transmit and clock and is a slave on the OPB Features include One SCP channel full duplex synchronous e SCP master e Up to 25MHz Programmable internal loopback capabilities e Multi master protocol supported Independent masking of all interrupts master collision transmit FIFO overflow transmit FIFO empty receive FIFO full receive FIFO underflow receive FIFO overflow Dynamic control of serial bit rate of data transfer serial master mode only Data Item size for each data transfer under programmer control 4 to 16 bits e OPB slave interface is 32 bits wide 14 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet General Purpose I O GPIO Controller The GPIO controller enables multiplexing of module l O pins with multiple functions within the chip That is a single package pin can be assigned to multiple I O functions Which function the pin is assigned to is determined by register bit settings controlled by software This significantly reduces the number of package pins needed to support multiple I O groups Features include Up to 32 GPIOs available GPIOs are multiplexed with alternate functions If not in use for dedicated functions I Os are available as GPIOs Direct contr
52. eq DMAAck2 B05 GPIO23 HoldAck DMAReq2 C05 GP1024 ExtReq DMAEOT2 IRQ4 A03 GPIO25 ExtAck DMAAck3 IRQ3 C04 GPI026 PerAddr05 DMAEOTO0 TS3 K26 GPIO27 BusReq DMAEOT3 IRQ5 B03 GPIO28 U03 GPIO29 IRQ2 DMAEOT 1 D03 GPIO30 IRQ1 DMAReq1 D02 GPI031 IRQ0 DMAAck1 D01 Halt A02 System 43 HoldAck GPIO23 DMAReq2 C05 External Bus Master 44 HoldReg GPIO22 DMAAck2 B05 IICOSData AA01 IICOSCIK Y03 IIC 41 IIC1SData SCPDO AA04 IC1SCIK SCPCIKOut AA02 AMCC Proprietary 23 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 7 of 14 Signal Name Ball Interface Group Page IRQ0 GPIO31 DMAAck1 DO1 IRQ1 GPIO30 DMAReq1 D02 IRQ2 GPIO29 DMAEOT1 D03 IRQ3 ExtAck GPIO25 DMAAck3 C04 IRQ4 ExtReq GPI1024 DMAEOT2 A03 Interrupts 42 IRQ5 BusReq GPI027 DMAEOT3 B03 IRQ6 GPIO11 H03 IRQ7 PerCS1 NFCE1 GPI008 C20 IRQ8 PerCS2 NFCE2 GPIO09 A21 IRQ9 PerCS3 NFCE3 GPIO10 B20 MemAddr00 AE21 MemAddr01 AD20 MemAddr02 AF22 MemAddr03 AE22 MemAddr04 AF23 MemAddr05 AD21 MemAddr06 AC21 MemAddr07 AE23 DDR2 1 SDRAM 45 MemAddr08 AE26 MemAddr09 AD25 MemaAddr10 AD26 MemAddr11 AC24 MemAddr12 AB24 MemAddr13 AC25 MemAddr14 AC26 MemCIkEn Y24 MemCIkOut0 AA23 DDR2 1 SDRAM 45 MemCIkOut0 AA24 24 AM
53. erCSO Chip selects 0 O 3 3V LVTTL 2 PerCS1 3 Chip selects 1 3 I O 3 3V LVTTL 1 2 PerData00 31 Data bus 0 31 1 0 3 3V LVTTL PerDataPar0 3 Data bus parity 0 3 1 0 3 3V LVTTL PerOE Output enable O 3 3V LVTTL 2 PerReady Slave is ready to transfer data l lg PerBLast Last transfer of burst access VO 3 3V LVTTL 1 4 PerErr External bus error 1 0 3 3V LVTTL 1 3 PerRW Read Write 1 0 3 3V LVTTL 1 2 PerWBE0 3 Write Byte enable 0 3 I O 3 3V LVTTL 1 2 ExtReset External reset O 3 3V LVTTL External Bus Master Interface BusReq External bus request O 3 3V LVTTL 1 ExtAck External data transfer complete O 3 3V LVTTL 1 ExtReq External data transfer request l 3 3V LVTTL 1 HoldReq External request for bus access l 3 3V LVTTL 1 HoldAck External request acknowledge O 3 3V LVTTL 1 DMA Interface DMAAcko0 1 External peripheral DMA acknowledge O 3 3V LVTTL DMAAck2 3 External peripheral DMA acknowledge O 3 3V LVTTL 1 DMAReq0 1 External peripheral DMA request 3 3V LVTTL DMAReq2 External peripheral DMA request 3 3V LVTTL 1 DMAReg3 External peripheral DMA request 3 3V LVTTL DMAEOTO 1 External DMA peripheral end of transmission 1 0 3 3V LVTTL DMAEOT2 3 External DMA peripheral end of transmission 1 0 3 3V LVTTL 1 44 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 5 of 7 Notes 1 Receiver input has hysteresis 2 Mu
54. eset Must be low during power on reset to initialize the JTAG 3 3V LVTTL 1 5 controller and for normal operation of the chip w pull up 42 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 3 of 7 Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description 1 0 Type Notes System Interface 3 3V tolerant SysClk System input clock 2 5V CMOS 1 receiver i 3 3V tolerant SysErr Machine check exception has occurred O 2 5V CMOS Gps Main system reset This signal may be driven by the PPC405EXr to 3 3V tolerant SysReset cause a board level reset to occur VO 2 5v CMOS e 3 3V LVTTL TestEn Test enable Reserved for manufacturing LSSD test receiver 3 w pull down Ls 3 3V LVTTL Halt External request to stop the processor revr w pull up 3 3V LVTTL TmrClk Processor timer external input receiver w pull up GP1000 27 General purpose I O Most of the GPIO signals are multiplexed with GPI029 31 other signals Which signal is conne
55. he I Os include internal supply sequencing circuitry that ensures the output of the receiver connected to internal chip logic is O until the I O power is applied When the logic power supply is on and the I O power supplies are off the I O logic connected to the associated ball neither sinks or sources significant current unless influenced by an internal pull up or pull down resistor While the I O supply is ramping the state of the I O balls are not predictable This power sequence is not destructive to the I Os or internal logic and does not cause any functional problems If the I O power is applied before the logic power is applied the output driver output stage connected to the balls will come up in an unknown state driving 1 driving 0 or tri state until the internal logic voltage is stable within normal operating range This power sequence is not destructive to the I Os or internal logic and does not cause any functional problems External voltage should not be applied to the chip I O balls before the associated I O power supply voltage is applied to the chip A chip power down cycle must complete all I O supply voltages and Vpp are below 0 4V before a new power up cycle is started During a 405EX power up cycle the system reset and test reset inputs should be asserted low System reset and test reset should remain asserted until the system clock is stable and then at least 32 system clock times after all power supplies are stable wit
56. hin normal operating range Failure to follow this reset sequence during the power up cycle might result in unpredictable operation AMCC Proprietary 51 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 11 I O Input Capacitance Parameter Symbol Maximum Unit Notes 3 3V LVTTL Cima 2 3 pF 2 5V CMOS Cine 2 1 pF 2 5 1 8V SSTL2 Cins 3 2 pF PCI Express differential data receiver Cina 1 59 pF PCI Express differential data transmitter Cins 1 16 pF PCI Express differential clock receiver Cine 0 188 pF Table 12 Typical DC Power Supply Requirements with DDR1 SDRAM CHEE ka not pe SVos EOVop Over Total Unit Notes 1 15V 1 25V with DDR1 AHVpp SAVpp EAVpp 333 0 97 na na 0 49 0 11 1 57 Ww 1 2 400 1 09 na na 0 55 0 11 1 75 Ww 1 3 533 na 1 46 na 0 55 0 11 2 12 Ww 1 4 Notes 1 Typical power is measured on a typical process part at a case temperature of 85 C at the specified voltages while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB and Security 2 DDR1 running at 333MHz PLB running at 166MHz 3 DDR1 running at 400MHz PLB running at 200MHz 4 DDR1 running at 355MHz PLB running at 177MHz Table 13 Maximum DC Power Supply Requirements with DDR1 SDRAM
57. initiated by a feedback signal pulse on the input of the Feedback Data Capture Window The DDR controller calculates when to assert the feedback signal based on when the data should be present after a read command The width of the feedback pulse is the same as DDR 1X clock The internal DDR 1X clock is the same frequency as MemClkOut0 MemClkOut0 is slightly delayed relative to DDR 1X clock due to the insertion delay of the drivers AMCC Proprietary 65 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet The feedback signal to the Feedback Data Capture Window is adjusted for propagation delay by the fine coarse delays and is automatically adjusted for variations in the DDR I O due to supply voltage and temperature Compensation for driver receiver variations is accomplished by driving and receiving the feedback signal on the external MemFBD and MemFBR pins Tuning the fine coarse delays adjust for propagation delay When properly tuned the feedback pulse is aligned to the first DQS in a four beat burst such that the rising edge of DQS is nominally centered on the feedback pulse Software must adjust the pulse using the fine coarse delays when tuning read DQS delay Note Using minimum trace length connect MemFBD directly to MemFBR The data captured in Stage 1 is relative to the DQS timing domain and is held for four DDR 1X cycles Stage 2 samples the data in Stage 1 attempting to capture
58. license under its patent rights nor the rights of others AMCC reserves the right to ship devices of higher grade in place of those of lower grade AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS AMCC is a registered Trademark of Applied Micro Circuits Corporation Copyright 2008 Applied Micro Circuits Corporation 74 AMCC Proprietary
59. ll AC20 SVpp AD20 MemAddr01 AA21 No ball AB21 No ball AC21 MemAddr06 AD21 MemAddr05 AA22 No ball AB22 No ball AC22 SVpp AD22 BAO AA23 MemCIkOut0 AB23 SVpp AC23 GND AD23 MemFBD AA24 MemCikOut0 AB24 MemAdari2 AC24 MemAddr11 AD24 GND AA25 ECC7 AB25 ECC3 AC25 MemAddr13 AD25 MemAddr09 AA26 ECC6 AB26 ECC2 AC26 MemAddr14 AD26 MemAddr10 AMCC Proprietary 37 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 4 Signals Listed by Ball Assignment Sheet 7 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name AEO1 GMCTxDO AFO1 GND AE02 GND AF02 GMCMDIO AE03 GMCMDCIk AF03 GMCTxEr AE04 GMCGTxCIk AF04 GMCCrs AE05 GMCRxDV AFO5 GMCRxEr AE06 GMCRxD7 AF06 GMCRxD6 AE07 EAGND AF07 GMCRxD5 AE08 EAVpp AF08 GND AE09 GMCRxD4 AF09 GMCRxD3 AE10 GMCRxD1 AF10 MemData26 AE11 MemData31 AF11 MemData30 AE12 DQS3 AF12 MemData25 AE13 MemData24 AF13 MemData29 AE14 MemData28 AF14 GND AE15 MemData18 AF15 MemData19 AE16 DQS2 AF16 MemData22 AE17 MemData16 AF17 MemData17 AE18 MemODT1 AF18 MemData20 AE19 WE AF19 GND AE20 BankSel1 AF20 CAS AE21 MemAddr00 AF21 BankSel0 AE22 MemAddr03 AF22 MemAddr02 AE23 MemAddr07 AF23 MemAddr04 AE24 BA2 AF24
60. ltage as follows Table 23 DDR SDRAM Write Operation Conditions Case Process Speed Junction Temperature C Voltage V Best Fast 40 1 3 Worst Slow 125 1 1 Note In the following tables and timing diagrams minimum values are measured under best case conditions and maximum values are measured under worst case conditions The timing numbers in the following sections are obtained using a simulation that assumes a model as shown in Figure 8 AMCC Proprietary 63 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet The following diagram illustrates the relationship among the signals involved with a DDR write operation Figure 9 DDR SDRAM Write Cycle Timing ox AY Nf AY MemCIikOut0 Addr Cmd X DQS MemData gt Tsa M Tha 4 Tos 3 4 Tos a E gt lETsD gt THp Tsa Setup time for address and command signals to MemCIkOut0 Tha Hold time for address and command signals from MemCIkOut0 Tsp Setup time for data signals minimum time data is valid before rising falling edge of DSQ Thp Hold time for data signals minimum time data is valid after rising falling edge of DSQ Tps Delay from rising falling edge of clock to the rising falling edge of DQS Note The timing data in the following tables is based on simulation runs using Einstimer Table 24 I O Timing
61. minary Data Sheet List of Tables Table 1 System Memory Address Map 4GB System Memory ooooccocccoc nn eee 7 Table 2 DGR Address Map cisterna apadrinar ara BELLA awed PAG ha NG ted 8 Table 3 Signals Listed Alphabetically rann eet narr n een 18 Table 4 Signals Listed by Ball Assignment rv renner narr knr nen 32 Table 5 Pin Groups vat tota de d de kreert read re AA AAA DRA 39 Table 6 Non Functional Ball Connections rn ner n annen 40 Table 7 Signal Functional Description rann rn n annen 41 Table 8 Absolute Maximum Ratings nr ne eee eae 48 Table 9 Package Thermal Specifications ooocoocoocococ arrene tte eens 49 Table 10 Recommended DC Operating Conditions arv raner tte eee 50 Table 14 O lnput Gapacitance aaret seres tea AAA BERA READ ren hetse 52 Table 12 Typical DC Power Supply Requirements with DDR1 SDRAM 2 22 2220 52 Table 13 Maximum DC Power Supply Requirements with DDR1 SDRAM 22202 00 52 Table 14 Typical DC Power Supply Requirements with DDR2 SDRAM 2 22 2200 53 Table 15 Maximum DC Power Supply Requirements with DDR2 SDRAM 2 22 2022 53 Table 16 DC Power Supply Loads with DDR1 SDRAM rv vr cece annan 54 Table 17 DC Power Supply Loads with DDR2 SDRAM 00 0 ccc ete 54 Table 18 Power Contribution of Functional Units arv ete 55 Table 19 System Clocking Specifications oooocoococ
62. mt Timers MMU Power PC 405 Processor UART lICx2 x2 BSC NAND SCP Flash SPI GPIO Controller EBC EBM Arbiter JTAG 16KB D Cache A y DDR1 2 SDRAM Controller On chip Peripheral Bus OPB OPB PLB Bridges Processor Local Bus PLB4 128 bits PKA TRNG EIP 94 we Security ang Feature HSS DMA Controller 4 Channel A MAL w AHB PLB Interrupt Coalescing Bridge Ethernet USB 2 0 MAC 1Gbit OTG Controller jue The PPC405EXr is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an ASIC application specific integrated circuit product This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Address Maps The PPC405EXr incorporates two address maps The first address map defines the possible use of addressable memory regions that the processor can access The second address map defines Device Configuration Register DCR addresses numbers The DCRs are accessed by software running on the PPC405EX
63. o MemFBD SSTL2 Dr Rev f Er 2 5V 1 8V MemODTO 1 On die termination O SSTL2 Dr Rev DMO 4 Write data byte lane mask DM4 is the byte lane mask for the ECC o 2 5V 1 8V byte lane SSTL2 Dr Rev i 2 5V 1 8V DQS0 4 Byte lane strobe DQS4 is the strobe for the ECC lane 1 0 SSTL2 Dr Rev a 2 5V 1 8V BAO 2 Bank address for up to eight banks O SSTL2 Dr Rev 2 5V 1 8V BankSel0 1 Bank select for up to two SDRAM memory banks O SSTL2 Dr Rev 2 5V 1 8V ECCO 7 ECC check bit byte 1 0 SSTL2 Dr Rev WE Write enable O RS AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 7 Signal Functional Description Sheet 6 of 7 Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required Signal Name Description I O Type Notes DDR 1 DDR2 Reference voltage 1 and 2 inputs Syref1A B Minimum 1 15 0 825 V 1 25V 0 9V Svrer2A B Nominal 1 25 0 9 V Volt ref receiver Maximum 1 35 0 975 V Serial Communication Port SCP Interface SCPCIKOut Output clock 1 0 3 3V LVTTL SCPDI Data input l
64. o of the frequency of the PLB clock The maximum OPB clock frequency is 100MHz 2 TrcCik is 1 2 CPU Clk The maximum CPU Clk supported for instruction trace is 400 MHz AMCC Proprietary 57 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Figure 4 Input Setup and Hold Timing Waveform System Clock 1 5V_ 4 Inputs 1 5V Outputs MAX Outputs 58 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Figure 6 Input Setup and Hold Timing Waveform for RGMII Signals GMCnRxClk 1 25V RGMII 1000 Mbps timing is with reference to the raising and falling edge of GMCnRxClk RGMII 10 100 Mbps timing is with reference only to the raising edge of GMCnRxClk Figure 7 Output Delay and Hold Timing Waveform for RGMII Signals GMCnTxCIk LAA AAA Tov MAX High Drive oa Outputs Float High Z PANA 3 PAD Low Drive NP WMV ALMA fs AYALA RGMII 1000 Mbps timing is with reference to the raising and falling edge of GMCnTxCIk RGMII 10 100 Mbps timing is with reference only to the raising edge of GMCnTxClk AMCC Proprietary 59 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 21 VO Specifi Notes cations 1 Ethernet interface meets timing req
65. ol of all functions from registers programmed by means of OPB bus master accesses Time multiplexing of controller outputs to module outputs Programmable conversion of module outputs to open drain outputs enables sharing of active low outputs externally Time multiplexing of module inputs to controller inputs Universal Interrupt Controller UIC The Universal Interrupt Controller UIC provides the control status and communications necessary between the various sources of interrupts and the PPC405 processor Features include Ten external interrupt sources supported e Generate interrupt on level high or low or edge rising or falling Programmable as synchronous edge capture or level sensitive or asynchronous edge or level sensitive triggering Each interrupt source bit programmable as critical or non critical e DCR bus interface is 32 bits wide e Optional interrupt handler vector generation Programmable vector base address Programmable vector offset size Programmable interrupt priority ordering e Programmable polarity for all interrupt types Interrupts of the same type do not need to be in contiguous bit positions e Status registers provide current state of all interrupts current state of enabled interrupts Ethernet Controller The Ethernet support provides one 10 100 1000 Mbps interfaces GMI MI RGMII Features include e ANSI EEE Std 802 3 and IEEE 802 3u supplement compliant e Half duplex and full d
66. or Revision 1 10 July 10 2008 Preliminary Data Sheet Table 4 Signals Listed by Ball Assignment Sheet 5 of 7 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name U01 GND V01 TMS WO1 GND Y01 TRST U02 GND V02 TCK W02 TDI Y02 TestEn U03 GPIO28 V03 OVpp W03 TDO Y03 IICOSCIK U04 Vop V04 GND W04 OVpp Y04 OVop U05 No ball V05 No ball W05 No ball Y05 No ball U06 No ball V06 No ball W06 No ball Y06 No ball U07 No ball V07 No ball W07 No ball Y07 No ball U08 No ball V08 No ball W08 No ball Y08 No ball U09 No ball VO9 No ball WO9 No ball Y09 No ball U10 No ball V10 No ball W10 No ball Y10 No ball Ut1 No ball V11 No ball W11 No ball Y11 No ball U12 No ball V12 No ball W12 No ball Y12 No ball U13 No ball V13 No ball W13 No ball Y13 No ball U14 No ball V14 No ball W14 No ball Y14 No ball U15 No ball V15 No ball W15 No ball Y15 No ball U16 No ball V16 No ball W16 No ball Y16 No ball U17 No ball V17 No ball W17 No ball Y17 No ball U18 No ball V18 No ball W18 No ball Y18 No ball U19 No ball V19 No ball W19 No ball Y19 No ball U20 No ball V20 No ball W20 No ball Y20 No ball U21 No ball V21 No ball W21 No ball Y21 No ball U22 No ball V22 No ball W22 No ball Y22 No ball U23 Vop V23 GND W23 SVpp Y23 SVop U24 MemData11 V24 ECCO W24 ECC1 Y24 MemCIkEn U25 MemData15 V25 ECC4 W25 ECC5 Y25 DOS4 U26 MemData14 V26 MemData10 W26 GND Y26 DM4
67. phabetically Sheet 5 of 14 Signal Name Ball Interface Group Page GND R12 GND R13 GND R14 GND R15 GND T11 GND T14 GND T16 GND U01 GND U02 GND V04 GND V23 GND Wo1 GND W26 GND ABO1 GND ACOA Power 47 GND ACO9 GND AC13 GND AC18 GND AC23 GND AD03 GND AD24 GND AE02 GND AE25 GND AF01 GND AF08 GND AF14 GND AF19 GND AF26 22 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 6 of 14 Signal Name Ball Interface Group Page GPIO00 PerDataPar0 A16 GPIO01 PerDataPar1 B12 GPIO02 PerDataPar2 C09 GPIO03 PerDataPar3 B04 GPIO04 PerData20 USB2Data4 C13 GPIOO5 PerData21 USB2Data5 Bog GPIO06 PerData22 USB2Data6 C12 GPIO07 PerData23 USB2Data7 D11 GPIO08 PerCS1 NFCE1 IRQ7 C20 GPI009 PerCS2 NFCE2 IRQ8 A21 GPIO10 PerCS3 NFCE3 IRQ9 B20 GPIO11 IRQ6 HO3 GPIO12 PerData16 USB2Data0 C11 GPIO13 PerData17 USB2Data1 B08 GPIO14 PerData18 USB2Data2 A10 GPIO15 PerData19 USB2Data3 B10 System 43 GPIO16 UARTODCD UART1CTS F04 GPIO17 UARTODSR UART1RTS F02 GPIO18 UARTOCTS G02 GPIO19 UARTORTS G01 GPIO20 UARTODTR UART1Tx F03 GPI021 UARTORI UART1Rx F01 GPI022 HoldR
68. precise baud rates If an external serial clock is used baud rate is unaffected by the modulation 2 Ethernet operation is unaffected 3 IIC operation is unaffected 4 For PCI E see the PCI Express I O Specifications Caution The system designer must ensure that any SSCG used with the PPC405EXr meets these requirements and does not adversely affect other aspects of the system 56 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 20 Peripheral Interface I O Clock Timings not SDRAM or PCI E Clock Min Max Units Notes GMCTxCIk frequency 125 125 MHz GMCTxCIk high time 45 of nominal ns GMCTxCIk low time 55 of nominal ns GMCRxClk frequency 125 125 MHz GMCRxClk high time 45 of nominal ns GMCRxClk low time 55 of nominal ns GMCGTxCIk 125 125 MHz GMCMDCIk 2 5 25 MHz GMCRefCIk 125 125 MHz GMCRefCIk edge stability phase jitter cycle to cycle na 0 1 ns GMCRefClk rise time na 1 ns GMCRefClk high time 40 of nominal ns GMCRefClk low time 60 of nominal ns GMC1RxClk 125 125 MHz GMC1TxCIk 125 125 MHz UARTSerClk 1000 2Topg1 2ns MHz 1 TmrClk na 100 MHz PerClk 33 100 MHz TCK na 20 MHz USB2CIk 60MHz 0 05 57 97 60 03 MHz TreClk 66 300 MHz 2 Notes 1 Topg is the period in ns of the OPB clock The internal OPB clock runs at an integral divisor rati
69. quence information Doc Issue 509 Change GMCRefCIk signal description Doc Issue 523 Remove pull up requirement on UARTnDSR Doc Issue 537 Updated part numbers revision level and PVR 07 10 2008 1 10 Added extended temperature operation of 533MHz part at 400 MHZ or less Added maximum power for each speed Added some functional unit power consumption figures AMCC Proprietary 73 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet AMEC APPLIED MICRO CIRCUITS CORPORATION Applied Micro Circuits Corporation 215 Moffett Park Drive Sunnyvale CA 94089 Phone 408 542 8600 800 840 6055 Fax 408 542 8601 http www amcc com AMCC reserves the right to make changes to its products its datasheets or related documentation without notice and war rants its products solely pursuant to its terms and conditions of sale only to substantially comply with the latest available datasheet Please consult AMCC s Term and Conditions of Sale for its warranties and other terms conditions and limitations AMCC may discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information is current AMCC does not assume any lia bility arising out of the application or use of any product or circuit described herein neither does it convey any
70. r processor through the use of mtder and mfder instructions Table 1 System Memory Address Map 4GB System Memory Function Subfunction Start Address Hex End Address Hex Size Local Memory DDR 2 1 SDRAM 0 0000 0000 0 7FFF FFFF 2GB EBC 0 8000 0000 0 8FFF FFFF 256MB PCI Express 0 9000 0000 0 EF5F FFFF 1 5GB GPT 0 EF60 0000 0 EF60 01FF 512B UART 0 0 EF60 0200 0 EF60 0207 8B Reserved 0 EF60 0208 0 EF60 02FF 248B UART 1 0 EF60 0300 0 EF60 0307 8B Reserved 0 EF60 0308 0 EF60 03FF 248B IIC 0 0 EF60 0400 0 EF60 041F 32B Reserved 0 EF60 0420 0 EF60 04FF 224B IIC 1 0 EF60 0500 0 EF60 051F 32B Reserved 0 EF60 0520 0 EF60 05FF 224B OPB Peripherals SCP 0 EF60 0600 0 EF60 0605 6B Reserved 0 EF60 0606 0 EF60 06FF 250B OPB Arbiter 0 EF60 0700 0 EF60 073F 64B Reserved 0 EF60 0740 0 EF60 07FF 192B GPIO 0 EF60 0800 0 EF60 087F 128B Reserved 0 EF60 0880 0 EF60 08FF 128B Ethernet 0 0 EF60 0900 0 EF60 09FF 256B Reserved 0 EF60 OA00 0 EF60 OAFF 256B RGMII Bridge 0 EF60 0B00 0 EF60 0C03 260B Reserved 0 EF60 0C04 0 EF60 FFFF 62KB PKA TRNG 0 EF61 0000 0 EF61 FFFF 64KB PCI Express Interrupt Handler 0 EF62 0000 0 EF62 00FF 256B PLB AHB Peripherals Reserved 0 EF62 0100 0 EF6B FFFF 640KB USB OTG 0 EF6C 0000 0 EF6F FFFF 256KB Security 0 EF70 0000 0 EF77 FFFF 512KB Reserved 0 EF78 0000 0 EFFF FFFF 8 9MB FAC EBC Memory 0 F000 0000 0 FFDF FFFF 254MB EBC Memory Boot R
71. ram illustrates the relationship of the signals involved with a DDR read operation AMCC Proprietary 67 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Figure 11 DDR SDRAM Memory Data and DOS g DQS MemData Tsp gt Mt Tho gt Table 27 I O Timing DDR SDRAM Read Timing Tsp and Typ 1 Tsp and Typ are measured under worst case conditions 2 Clock speed for the values in the table is 200 MHz 3 The time values in the table include 1 4 of a cycle at 200 MHz 5ns x 0 25 1 25 ns 4 To obtain adjusted Tsp and Typ values for lower clock frequencies subtract 0 75 ns from the values in the table and add 1 4 of the cycle time for the lower clock frequency e g Tsp 1 25 0 25Tcyc Signal Names Reference Signal Read DEE vs DQS Set up Read Data vs DQS Hold sp ns Thp ns MemData00 07 DQSO 0 27 0 45 MemData08 15 DQS1 0 27 0 45 MemData16 23 DQS2 0 27 0 45 MemData24 31 DQS3 0 27 0 45 ECCO 7 DQS4 0 27 0 45 In the following example the data strobes DQS and the data are shown to be coincident There is actually a slight skew as specified by the SDRAM specifications and there can be additional skew due to loading and signal routing lt is recommended that the signal length for all of the DQS signals be matched The following example shows the timing relationship between SDRAM DDR Data at the input pin and
72. rating current leaDD 1 2 mA 1 Notes 1 The maximum current values listed above are not guaranteed to be the highest obtainable These values are dependent on many factors including the type of applications running clock rates use of internal functional capabilities external interface usage case temperature and the power supply voltages Your specific application can produce significantly different results Vpp logic current and power are primarily dependent on the applications running and the use of internal chip functions DMA PCI Express Ethernet and so on OVpp I O current and power are primarily dependent on the capacitive loading frequency and utilization of the external buses The information in this table provides details about the conditions under which the listed values were obtained Maximum power is measured on a best case process worst case power part running at 533MHz with a case temperature of 85 C and with voltages of Vpp 1 30V OVpp 3 45V SVpp 2 6V and EOVpp 2 6V while running Linux and test applications that exercise each function with representative traffic PCI Express Gigabit Ethernet USB Security Table 17 DC Power Supply Loads with DDR2 SDRAM Parameter Symbol Typical Maximum Unit Notes Vpp 1 2V active operating current IDD 1165 2220 mA 1 AVpp 1 2V active operating current lapp 4 10 mA 1 AHVpp 2 5V active operating current lAHDD 1 2 mA 1 OVpp 3 3
73. read Spectrum Clocking narrer rn rann knr teas 56 DDR 2 1 SDRAM I O Specifications rar varenr teens 62 PCI Express PCI E I O Specifications 0 0 0 ccc tte eee 70 Intalz ton 44 Rhee dates karene A A A d r armada aa edie Waban la ada 72 2 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet List of Figures Figure 1 PPC405EXr Embedded Controller Functional Block Diagram erre 6 Figure 2 Package 27mm 388 Ball EPBGA 2 2 2 2 nere eee 17 Figure 3 Clocking Waveform 1 0 0 2 00 ranerne eens 55 Figure 4 Input Setup and Hold Timing Waveform 2 00 cece tte eee 58 Figure 5 Output Delay and Float Timing Waveform 00000 eee teeta 58 Figure 6 Input Setup and Hold Timing Waveform for RGMII Signals 0 00000 eee eee eee 59 Figure 7 Output Delay and Hold Timing Waveform for RGMII Signals 00 cece eee 59 Figure 8 DDR SDRAM Simulation Signal Termination Model 000 0c eee eee ee 62 Figure 9 DDR SDRAM Write Cycle Timing 22 2 teen e eee 64 Figure 10 DDR SDRAM Read Data Path for a Single Data Bit 0 67 Figure 11 DDR SDRAM Memory Data and DQS 0 0 ccc tees 68 Figure 12 DDR SDRAM Read Cycle Timing Example 0 000 cece ete 69 AMCC Proprietary 3 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preli
74. refresh e Power management self refresh suspend Two regions two chip selects one clock driver AMCC Proprietary 11 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet PCI Express The PCI Express single lane interface include the following features Features include e Compliant with PCI Express base specification 1 1 e Port can be End Point or Root Complex Upstream amp Downstream e PCI Express to PCI Express opaque Non Transparent bridge Power Management e Supports one virtual channel VCO with no Traffic Class TC filtering e Maximum Payload block size 256B e Supports up to 512B maximum Read request size e Requests supported Up to two posted outbound Write requests memory and messages Up to two posted inbound Write requests Up to two outbound Read requests outstanding on PCI Express Up to two inbound Read requests outstanding on PCI Express Outbound I O request as a PCI Express Root Port Inbound I O request as a PCI Express End Point e Buffering in PCI Express Port for the following transaction types 1KB Replay buffer up to eight in flight transactions 512B for Outbound posted Writes 512B for Outbound Reads completion 512B for Inbound posted Writes 512B for Inbound Reads completion e Parity checking on each buffer e POM Programmable Outbound Memory Regions 3 Memory 1 I O 1 Message 1 config 1 Internal Regs e PIM Programmable
75. rface IRQ0 9 15 75 10 46 JTAG Interface TDI na na TDO 15 75 10 46 TMS na na TRST na na 60 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 21 VO Specifications Notes 1 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time loH lov Clock Notes Tis min Ti min Tov max Tox min min min System Interface GPIO00 10 na na na na 11 08 7 37 GPIO11 15 na na na na 5 51 7 23 GPIO16 27 na na na na 11 08 7 37 GPIO28 na na na na 15 75 10 46 GPIO29 31 na na na na 11 08 7 37 Halt na na na na na na SysErr na na na na 5 51 7 23 SysReset na na na na 5 51 7 23 External Peripheral Interface PerAddr05 31 1 8 1 5 3 1 11 08 7 37 PerCik PerCS0 3 5 2 1 11 08 7 37 PerCik PerData00 31 2 7 1 5 3 1 11 08 7 37 PerCik PerDataPar0 3 1 9 1 5 3 1 11 08 7 37 PerCik PerOE 5 2 1 11 08 7 37 PerCik PerReady 2 1 na na PerCik PerRW 1 8 1 5 3 1 11 08 7 37 PerCik PerWBE0 3 1 7 1 5 1 1 11 08 7 37 PerCik PerBLast 2 1 5 1 11 08 7 37 PerCik PerErr 1 9 1 5 3 1 11 08 7 37 PerCik ExtReset 5 3 1 11 08 7 37 PerCik BusReq 2 3 1 5 1 1 11 08 7 37 PerCik HoldReq 2 1 5 2 1 na na PerClk HoldAck 5 2 1 11 08 7 37 PerClk ExtAck 2 3
76. rmal resistance values for the EPBGA packages in a convection environment are as follows Airflow Parameter Symbol ft min m sec Unit 0 0 100 0 51 200 1 02 300 1 52 400 2 02 500 2 53 600 3 03 Junction to ambient thermal resistance Oja 18 9 16 6 15 8 15 4 15 0 14 7 14 4 C W without heat sink Junction to ambient thermal resistance Oya 15 5 12 5 11 4 10 9 10 7 10 5 10 3 C W with heat sink Resistance Value Junction to case thermal resistance Oyo 8 96 C W Junction to board thermal resistance 948 ot ev Notes 1 Values in the table are achieved with the following JEDEC standard board 114 5mm x 101 6mm x 1 6mm 4 layers 2 For a chip mounted on a card with at least one signal and two power planes the following relationships exist a Case temperature Tc is measured at top center of case surface with device soldered to circuit board b Ta To Px05a where Ta is ambient temperature and P is power consumption c Tomax Tymax 7 PX0yc where Tymax is maximum junction temperature and P is power consumption Thermal Management The following heat sink was used in the above thermal analysis 26 92mm x 27mm x 11 43mm The heat sink is manufactured by Aavid Thermalloy P N 62925 AMCC Proprietary 49 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 10 Recommended DC Operating Conditions Sheet 1 of 2
77. st pull up See Pull Up and Pull Down Resistors on page 39 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 39 for recommended termination values 4 If not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required SSTL2 Dr Rev Signal Name Description 1 0 Type Notes NAND Flash Interface NFALE Address latch enable O 3 3V LVTTL NFCEO Chip select 0 O 3 3V LVTTL NFCE1 3 Chip selects 1 3 O 3 3V LVTTL 1 NFCLE Command latch enable O 3 3V LVTTL NFData00 15 Data Bus 1 0 3 3V LVTTL IED Read Busy If low indicates that Read Erase command is in process NFRdyBusy If high indicates that the command is complete S 3VENTIL NFRE Read enable O 3 3V LVTTL NFWE Write enable O 3 3V LVTTL DDR1 2 SDRAM Interface 2 5V 1 8V MemData00 31 Memory data 1 0 SSTL2 Dr Rev 2 5V 1 8V MemAddr00 14 Memory address O SSTL2 Dr Rev one 2 5V 1 8V RAS Row address strobe O SSTL2 Dr Rev KG 2 5V 1 8V CAS Column address strobe O SSTL2 Dr Rev 2 5V 1 8V MemCIkEn Clock enable O SSTL2 Dr Rev MemCIkOut0 2 5V 1 8V MemClkOuto Differential DDR SDRAM clock output O SSTL2 Dr Rev Feedback driver Connect directly to MemFBR with the minimum 2 5V 1 8V MEmEBD trace length O SSTL2 Dr Rev F 2 5V 1 8V MemFBR Feedback receiver Connect externally t
78. ta00 PerData00 C18 NFData01 PerData01 B18 NFData02 PerData02 C17 NFData03 PerData03 A18 NFData04 PerData04 D16 NFData05 PerData05 B17 NFData06 PerData06 C16 NAND Flash 45 NFData07 PerData07 B16 NFData08 PerData08 A17 NFData09 PerData09 B15 NFData10 PerData10 C15 NFData11 PerData1 1 A15 NFData12 PerData12 B14 NFData13 PerData13 A14 NFData14 PerData14 C14 NFData15 PerData15 B13 NFRdyBusy PerData31 A04 NFREn PerData27 A05 NFWEn PerData28 C08 OVpp DO5 OVpp DO7 OVpp D08 OVpp D13 OVpp D19 OVpp D20 OVpp D22 OVpp E04 OVpp E23 OVop gya Power 47 OVpp G23 OVpp H23 OVpp L12 OVpp L15 OVpp M11 OVpp M16 OVpp R11 OVpp V03 OVpp W04 OVpp Y04 26 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Table 3 Signals Listed Alphabetically Sheet 10 of 14 Signal Name Ball Interface Group Page PCIEOATB L03 PCIEOCIKC LO1 PCIEOCIKT L02 PCIEORExt M03 PCIEORExtG M02 PCI Express 42 PCIEORx Jot PCIEORx J02 PCIEOTx Ko2 PCIEOTx K03 PerAddr05 GPIO26 TS3 DMAEOTO0 K26 PerAddr06 TS2 DMAReq0 K25 PerAddr07 TS1 DMAACKO J26 PerAddr08 TS0 DMAReg3 J25 PerAddr09 TS1E H25 PerAddr10 TS0E J24 PerAddr11 TS10 G26 PerAddr12 TS00 H24 PerAddr13 G25 PerAddr14 F26 PerAddr15 E26 PerAddr16 F25 PerAd
79. ter UART interface provides four configurations e One 8 signal port e Two 4 signal ports e Two 2 signal ports e One 4 signal port and one 2 signal port The UART performs serial to parallel conversion on data received from a peripheral device or a modem and parallel to serial conversion on data received from the processor Features include e Compatible with the16750 All six software modem control functions CTS RTS DSR DTR RI DCD on UARTO e Programmable auto flow data flow controlled by RTS and CTS signals e Characters can be 5 6 7 or 8 bits e Programmable start stop parity bit insertion e Sixty four byte FIFOs for buffering Tx and Rx data LIN sub bus specification compliant line break generation detection and false start bit detection e Programmable internal external loopback capabilities Low Power and Sleep mode e Register conformance after reset to configuration of the NS16450 register set AMCC Proprietary 13 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Hold and shift registers eliminate need for precise synchronization between processor and serial data in character mode e Complete status reporting e Full prioritized interrupt system controls e Independently controlled transmit receive line status and data set interrupts Programmable baud generator divides serial clock input and generates 16x clock e Ability to add delete standar
80. the data in the DDR 1X domain The on time sample clock from the Stage 2 Store block samples the Stage 1 data at sample cycle T1 T2 T3 or T4 The sample cycle is either selected by initialization software or can be automatically selected and adjusted by the DDR controller The Stage 1 data is sampled a second time by the over sample clock at a delayed sample point The delay between the on time sample and over sample clocks is the Over Sampling Guard Band The feedback pulse is sampled with the data captured by the first DQS in the four beat burst A match of one or both of the sample clocks with the feedback pulse is a hit The DDR controller based on hits or misses by the on time sample and over sample clocks adjust the sample cycle in order to track variations in DQS Burst data from a sample hit is passed to Stage 3 In Stage 3 the data is synchronized to the PLB clock domain and eventually driven onto the PLB bus The data captured on the rising and falling DQS edges is unpacked into the correct bit locations on the upper 0 63 and lower 64 127 PLB bus When ECC is enable ECC checking and corrections is done after Stage 3 Figure 12 illustrates how the three Stage read logic captures the data in the DQS timing domain and synchronizes it to the PLB clock domain The first DQS of four beat burst is roughly centered on feedback signal pulse 66 AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 20
81. transforms ROC removal and TAG insertion Variable bypass offset of header length per packet e Media Access Control Security MACSec features Cipher suite GCM AES 128 Header insertion and removal Integrity and confidentiality with MSDU e SGT L2 supported features GCM AES with 128 bit key Integrity only and with confidentiality of MSDU e ICV generation and validation SGT L3 supported features AES GCM AES GMAC with 128 192 and 256 bit key e IPsec SSL security acceleration engine e DES 3DES AES ARC 4 AES GCM and GMAC AES encryption decryption e MD 5 SHA 1 and SHA 256 hashing e Public key acceleration for RSA DSA and Diffie Hellman e Combined encryption hash and hash decryption with the AES CCM algorithm True or pseudo random number generators Non deterministic true random numbers Pseudo random numbers with lengths of 8B or 16B ANSI X9 17 Annex C compliant using a DES algorithm e Interrupt controller Fifteen programmable maskable interrupts Initiate commands via an input interrupt Sixteen programmable interrupts indicating completion of certain operations All interrupts mapped to one level or edge sensitive programmable interrupt output DMA controller Autonomous 4 channel 1024 words 32 bits word per DMA transfer Scatter gather capability with byte aligned addressing Byte reverse capability on SA and descriptors UART The Universal Asynchronous Receiver Transmit
82. uirements as defined by IEEE 802 3 standard Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time loH lot Clock Notes Tis min Ti min Tov max To min min min Ethernet GMII Interface GMCMDIO na na na na 5 51 7 23 Async 1 GMCCD 2 0 na na Async 1 GMCCrS 2 0 na na Async 1 GMCRxDO 7 1 85 0 na na GMCRxCIk 1 GMCRxDV 1 95 0 na na GMCRxCIk 1 GMCRxEr 1 95 0 na na GMCRxClk 1 GMCTxD0 7 2 3 2 0 5 51 7 23 GMCGTxClk 1 GMCTxEr 2 4 2 0 5 51 7 23 GMCGTxClk 1 GMCTxEn 2 4 2 0 5 51 7 23 GMCGTxClk 1 Ethernet RGMII Interface n 0 or 1 GMCnRxD0 3 0 7 1 na na GMCnRxClk 1 GMCnRxCtl 0 8 1 na na GMCnRxClk 1 GMCnTxDO 3 0 5 2 7 5 51 7 23 GMCnTxCIk 1 GMCnTxCtl 0 5 2 7 5 51 7 23 GMCnTxClk 1 Internal Peripheral Interfaces not SDRAM or PCI E IICnSData na 10 46 UARTNOTS na na 15 75 10 46 UARTnRTS na na 15 75 10 46 UARTNDSR na na 15 75 10 46 UARTnDCD na na 15 75 10 46 UARTNDTR na na 15 75 10 46 UARTNAI na na 15 75 10 46 UARTnRx na na na na UARTnTx na na 15 75 10 46 SCPDI na na SCPDO na 10 46 USB2Data0 7 3 9 0 6 3 2 15 75 10 46 USB2CIk USB2Dir 3 7 6 4 2 na na USB2CIk USB2Next 3 5 0 na na USB2CIk USB2Stop 6 4 2 15 75 10 46 USB2CIk DMA Interface DMAAck0 3 5 2 1 0 15 75 10 46 PerClk DMAReq0 3 2 4 1 na na PerCik DMAEOT0 3 2 1 5 3 1 0 15 75 10 46 PerClk Interrupts Inte
83. uplex support for the following One Gigabit Media Independant Interface GMII One Media Independant Interface MII One Reduced GMII interfaces RGMII e Receive and transmit FIFOs are 16K bytes with programmable thresholds e FCS control for transmit receive packets e Multiple packet handling in transmit and receive FIFOs e Unicast multicast broadcast and promiscuous address filtering Two 256 bit hash filters for unicast and multicast frames Automatic retransmission of collided frames Runt frame rejection e Programmable inter frame gap AMCC Proprietary 15 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet IEEE 802 3x compliant for frame based flow control mechanism including self assembled control frame transmitting Wake on LAN and Power over Internet supported Programmable internal external loopback capabilities OPB slave MAC and PLB master MAL interfaces for control and configuration are 32 bits wide MAL has 128 bit PLB master interface for data path Extensive error status vector generation for each processed packet VLAN tag ID supported according to IEEE Draft 802 3ac D1 0 standard Programmable automatic source address inclusion replacement for transmit packets Programmable automatic Pad FCS stripping for receive packets Programmable VLAN Tag inclusion replacement for transmit packets Half or full duplex GMII RGMII Jumbo frames support Memor
84. werPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Power Contro This chip has power management control to put the following functional units to sleep if not needed The typical and maximum power consumption for the each of these units is Table 18 Power Contribution of Functional Units Functional Unit Typical Maximum Units Notes EBM OPB 0 006 0 012 WwW Security 0 117 0 230 WwW Nand Flash 0 127 0 246 Ww USB 0 005 0 008 W EMAC 0 118 0 133 WwW Test Conditions Clock timing and switching characteristics are specified in accordance with minimum Output o operating conditions shown in the table Recommended DC Operating Conditions on Pin page 50 For all signals AC specifications are characterized at To 85 C with the test ADR load shown in the figure to the right Table 19 System Clocking Specifications Symbol Parameter Min Max Units CPU PFc Processor clock frequency must be gt SCF 333 33 533 33 MHz SysClk Input SCF Frequency 33 33 100 MHz SCTcs Edge stability phase jitter cycle to cycle na 0 1 ns SCTcH High time of nominal period 40 60 SCToL Low time of nominal period 40 60 SCrr Rise time na 1 ns Note Input slew rate 1V ns Other Clocks VCOF VCO frequency 600 1600 MHz PLBFG PLB frequency 133 200 MHz OPBFc OPB frequency 66 100 MHz
85. x1405B1E1 Notes 1 S security feature present N security feature not present 2 p Package S lead free RoHS compliant P leaded 3 C Chip revision level C 4 fff Processor frequency 333 333 MHz 400 400 MHz 533 533MHz 5 T Case temperature range 40 C to 85 C see footnote 5 on page 51 The part number contains a part modifier Included in the modifier is a revision code This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only The PVR Processor Version Register and the JTAG ID register are software accessible read only and contain information that uniquely identifies the part See the PPC405EXr Embedded Processor User s Manual for details about accessing these registers Order Part Number Key PPC405EXr SSB533T ta AMCC Part Number Case Temperature Range Security Processor Speed MHz Chip Package Revision Level Note The example P N above has the security feature is lead free capable of running at 533MHz and is shipped in a tray tape and reel packaging is not available AMCC Proprietary 5 PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Block Diagram Figure 1 PPC405EXr Embedded Controller Functional Block Diagram Universal Interrupt Controller x3 Clock Control Reset Power Mg
86. y Access Layer MAL provides DMA capability to Ethernet channel Interrupt coalescence support for two transmit and two receive channels General Purpose Timer GPT The GPT provides a time base counter and system timers in addition to those defined in the processor Features include e 32 bit time base counter driven by the OPB clock e Seven 32 bit compare timers JTAG Features include IEEE 1149 1 test access port e JTAG Boundary Scan Description Language BSDL Refer to http www amcc com Embedded Partners for a list of AMCC partners supplying probes for use with the JTAG interface AMCC Proprietary PPC405EXr PowerPC 405EXr Embedded Processor Revision 1 10 July 10 2008 Preliminary Data Sheet Figure 2 Package 27mm 388 Ball EPBGA Gold Gate Release Corresponds to A01 Ball Location Top View Logo View gt AMCC Power Part Number PPC405EXr Lot Number rd 1YWWBZZZZZ Epoxy Mold Side View Compound gt 2 65 max PCB Substrate gt y 0 3 min 27 0 gt Bottom View lt 25 0 4 E e AF ag 8893883389388338338233338 y 1 0 Basic AD 00000000000000000000000000 4 AC 00000000000000000000000000 AB 0000 AA 0000 Y 0000 W 0000 V 0000 U T 0000 000000 R 000000 27 0 P 0000 000000 N 000 000 M 0000 000000 L 0000 000000 K 0000 J 0000 H 0000 G 0000 F 0000 E 0000 D G ooo A Notes 1 All dimensions are in mm 4 Be 2 Package conforms to JEDEC MS 034C A 3

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