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SH7760 Group USB Host Module Application Note

1. Done queue Dword 0 Dword 1 TD Queue Tail Pointer TailP Dword 2 TD Queue Head Pointer HeadP Dword 3 i i Notes 1 Fields are not accessed or modified by the HC and are available for use by the HC for any purpose 2 Fields 0 must be processed by the HC after clearing the HCD to O Figure 2 5 Endpoint Descriptor Table2 1 Field Definitions for Endpoint Descriptor Name HC Access Description FA R FunctionAddress Address of a USB function device EN R EndpointNumber Number of the corresponding endpoint D R Direction This field indicates the direction of data flow IN or OUT The direction may also be determined by using the PID field of the TD Get direction from TD OUT IN Get direction from TD S R Speed Indicates the speed of the endpoint full speed S 0 or low speed S 1 K R sKip When this bit is set HC continues on to the next ED without attempting communication for this endpoint F R Format This bit indicates the format of the TDs linked to this ED If this is a control bulk or interrupt endpoint then F 0 indicating that the General TD format is used If this is an isochronous endpoint then F 1 indicating that the Isochronous TD format is used Rev 1 00 10 03 page 8 of 90 RENESAS Name HC Access Description MPS R MaximumPacketSize This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single USB packet
2. eese nennen 53 3 1 Hardware Environment eeo eae etr ente i e re e pe eee nene eres aeneis 54 3 2 Software Enviro metit eerte tee ee t d bt tex UE espe 56 322 1 Sample Program een ec e at de e e Ce epa 56 3 2 2 Compiling and Linking eii ete RR e Rd enti sr tus 56 3 2 3 RequestGenerator ne deerit reip ista 57 3 3 Loading and Executing the Program sese eem ener 58 3 3 4 1 Loading the Program eco rete ti 59 3 4 Exec cio 60 Section 4 Overview of the Sample Program lt w wwwmmmaemanemanmawaro 69 4 State Transition Diagram zer id fi rd Eee 70 42 Types DUA eren ner Eee pie ee e 72 4 3 CPUC SHUI cei ceret e ite A 73 4 4 Purposes of FUNCIONS nr e OR TO HI eo terns 75 Section 5 Operation of Sample Program esee 83 5 Reset State ced ead e e debe ge e e a Erbe p rede ee cises 83 5 2 Main Loop Connection Wait and Steady States sse 84 5 3 Root Hub Processing State eee eim er ER HR eno eh es rao Ro Eden 85 5 4 Connection Processing Staters iii e on eene nennen nene een rennen 86 5 5 Serial Input State RequestGeneratorDriver Processing State eese 87 5 6 Transfer Request Generation State essere nene eene 88 5 7 DoneQueue Processing EH T eren 89 5 8 Transfer Result Processing State AA 90 Rev 1 00 10 03 page iv of vi RENESAS Section 1 Overview This applicatio
3. DeviceDriver list called by EnumerationDriver Usbh Dr ReqGenDr h Various declarations of ReqGenDr Usbh App Link h Various declarations required for USB host module and UART conjunction processing Usbh Common h Common declaration of whole USB host Rev 1 00 10 03 page 73 of 90 3 NE SAS USB host UART conjunction processing part Usbh_App_xxx c Driver layer Enumeration RequestGenerator Driver Driver UART firmware Usbh Dr xxx c USB Drive USBD layer Usbh_Usbd_xxx c Host Controller Driver HCD layer Usbh_Hcd_xxx c Software Hardware UART Host Controller HC USB host module Figure 4 3 Layer Structure of Firmware Rev 1 00 10 03 page 74 of 90 ENESAS 4 4 Purposes of Functions Table 4 2 to 4 10 shows functions contained in each file and their purposes Table 4 2 StartUp c File in Which Stored Function Name Purpose StartUp c CallReseException Operates for reset exception and calls function to be executed CallGeneralException Calls function corresponding to general exception other than TLB miss occurrence CallTLBMissException Calls function corresponding to TLB miss occurrence Callinterrupt Calls function corresponding to interrupt request SetPowerOnSection Module and memory initialization and shift to main loop _INITSCT Copies variables that have initial settings to the RAM work area InitMemory Clears RAM area us
4. DoSetConfiguration Request SetConfiguration ReceiveSetConfigurationResult Receive the result of SetConfiguration request DolntTransfer Request interrupt transfer ReceivelntTransferResult Receive the result of interrupt transfer request DoSetEnvironment Set DeviceSpeed information and information of MaxPacketSize of EpO DoGetEnvironment Request obtaining DeviceSpeed information and information of MaxPacketSize of EpO ReceiveGetEnvironmentResult Receive DeviceSpeed information and information of MaxPacketSize of EpO DoControlTransfer Request any control transfer ReceiveControlTransferResult Receive result of control transfer request DoBulkTransfer Request bulk transfer ReceiveBulkTransferResult Receive result of bulk transfer request DoMemoryRead Data is read from specified address mystrtoul Rev 1 00 10 03 page 80 of 90 RENESAS Convert character string to hexadecimal File in Which Stored Function Name Purpose Usbh Dr ReqGenDr c DisplayTitle Output title of RequestGenerator DisplayHelp Indicate Help information Usbh Dr ReqGenDr c receives a transfer request from the USB packet generation tool RequestGenerator on the PC and returns the result Table 4 10 Usbh App Link c File in Which Stored Function Name Purpose Usbh App Link c App SerialL n Serialln processing App SerialOut Serial out processing Usbh App Link c perfor
5. TailP R TDQueueTailPointer The address of the last TD linked with this ED is stored If TailP and HeadP are the same this ED contains no TD that the HC can process If TailP and HeadP are different this ED contains a TD to be processed by the HC H R W Halted This bit is set by the HC to halt the processing of ED This bit is set usually due to an error in processing a TD C R W ToggleCarry Whenever a TD is retired this bit is written to contain the last data toggle value LSb of DataToggle field from the retired TD This field is not used for Isochronous Endpoints HeadP R W TDQueueHeadPointer The first TD linked with this ED Whenever the processing of TD indicated by this field has been completed the value set to the address of next TD linked with this TD is incremented NextED R NextED Address of the ED linked with this ED If no ED to link clear this bit to O The HCD sets the sKip bit to stop processing of an ED When a sKip bit is set to 1 the HC skips processing of that ED and begins processing the ED indicated by NextED If an error occurs during the processing of a TD the Halt bit is set the TD that caused the error is moved to the Done Queue and the HeadP bit is updated by the HC After the source of the error has been eliminated the HCD clears the Halt bit and processing of the ED recommences 2 3 3 Transfer Descriptor TD A TD is a data structure placed in memory by the HC to define t
6. such as SetAddress and SetConfiguration as Out Notes The SetAddress command cannot be executed through this function Execute this command by clicking the SetAddress button Erroneous settings may lead to incorrect operation e Interrupt Click the Interrupt button to execute an interrupt transfer Specify the endpoint number for the transfer the direction of transfer MaxPacketSize PollingRate amount of data to be transferred the data to be transferred setting data is unnecessary for In transfers and the number of interrupt packets to be generated on the parameter input screen e Bulk Click the Bulk button to execute a bulk transfer Specify the endpoint number for the transfer the direction of transfer MaxPacketSize PollingRate amount of data to be transferred and the data to be transferred setting data is unnecessary for In transfers on the parameter input screen e MemoryRead Data can be read from a specified address of the SH7760SE by clicking the MemoryRead button Specify the address amount of data to be read and access width byte word or longword on the parameter input screen e Scenario Rev 1 00 10 03 page 63 of 90 RENESAS Clicking the Scenario button allows you to set up a text file containing a list of processes for execution Any button function other than Start Finish and Scenario can be included in the text file The command names that correspond to the respective buttons along w
7. RO O Figure 2 24 HcBulkCurrentED Register Table 2 18 HcBulkCurrentED Register Read Write Key Reset HCD HC Description BCED Oh R W R W BulkCurrentED This field indicates a pointer of the current ED This is advanced to the next ED after the HC has served the present one When it reaches the end of the Bulk list HC checks the BulkListFilled of HcControl If set it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit If it is not set it does nothing HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared When set the HCD only reads the instantaneous value of this register HcDoneHead Register The HcDoneHead register indicates the physical address of the last completed TD that was added to the Done queue As the value of this register is gained from the HCCA usually this register is not accessed by HCD 3 0 0 0 1 4 3 0 A 0 i Figure 2 25 HcDoneHead Register Table 2 19 HcDoneHead Register Read Write Key Reset HCD HC Description DH Oh R R W DoneHead When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD HC then overwrites the content of HcDoneHead with the address of this TD This is set to zero whenever HC writes the content of this register to HCCA It also sets the WritebackDoneHead of HclnterruptStatus Rev 1 00 10 03 page 38 of 90 RENESAS 2 6 3 Frame Counter Partition HcFmlnterval Register The HcFmlnterv
8. The program returns to this state when a device is disconnected from the Root Hub while the program is in the steady state In this state the program waits for a RootHubStatusChange interrupt When this interrupt is generated by the connection of a device to the Root Hub processing for connection is carried out and the steady state is then entered e Steady State The program enters this state after a device has been connected to the Root Hub while the program was in the connection wait state In this state EDs and TDs are generated and transfer requests are generated for the HC Processing for the requested transfer is then completed The program also controls the SCIF module to perform serial output e Root Hub Processing The program enters this state in response to a RootHubStatusChange interrupt that occurs while the program is in the connection wait or steady state Since this interrupt occurs when the root hub condition changes the program decides the interrupt source and handles the following connection processing when the root hub condition changes from the disconnection state to connection state disconnection processing when the root hub condition changes from the connection state to the disconnection state and overcurrent clearing processing when the overcurrent state is entered e Done Queue Processing The program enters this state in response to a WriteBackDoneHead interrupt that occurs while the program is in the steady state
9. 00 10 03 page 90 of 90 RENESAS SH7760 Group USB Host Module Application Note Publication Date Rev 1 00 October 20 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Technical Documentation amp Information Department Renesas Kodaira Semiconductor Co Ltd Edited by 02003 Renesas Technology Corp All rights reserved Printed in Japan Renesas Tech nology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan RENESAS SALES OFFICES 241 NC SAS http www renesas com Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel lt 1 gt 408 382 7500 Fax lt 1 gt 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH United Kingdom Tel lt 44 gt 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Europe GmbH Dornacher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax lt 49 gt 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688 Fax 852 2375 6836 Renesas Technology Taiwan Co Ltd FL Tel 10 99 Fu Hsing N Rd Taipei Taiwan 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd 26 F Ruijin Building No 205 Maoming Road S Shangha
10. Delaylnterrupt As the field of GTD indicates how long the interrupt generation is delayed when ITD is completed FC R FrameCount Indicates the number of data packet transferred the number of frame to be transferred from ITD FrameCount 0 One data packet FrameCount 7 Eight data packets CC R W ConditionCode Stores the condition code when the Isochronous TD is moved to the Done Gueue BPO R BufferPageO Indicates the first address of the data buffer NextTD R W NextTD Indicates the address of the next IsochronousTD BE R BufferEnd Indicates the last address of a buffer Rev 1 00 10 03 page 13 of 90 RENESAS Name HC Access Description OffsetN R Offset Indicates the head address of Isochronous Data Packets 5 3 2 0 Name HC R W Offset Offset 13 bits Set the lower 12 bit of transfer start address by lower 12 bit of Offset The way of obtaining the value of upper 20 bit is selected by the 12th bit When the value is 0 the value of the upper 20 bit of BufferPage0 is used When the value is 1 the value of the upper 20 bit of BufferEnd is used PSWN W PacketStatusWord Stores the condition code when Isochronous Data Packets are transferred completely HC R W Description Size of Packet 11 bits Indicates the size of reception on an IN transfer This bit is 0 on an OUT transfer Condition Code When this field indicates NotAccessed format of OffsetN PSWN is Offset When this field i
11. The HcFmRemaining register is a 14 bit down counter which shows the bit time remaining in the current frame Rev 1 00 10 03 page 39 of 90 RENESAS 0 0 oe AN Figure2 27 HcFmRemaining Register Table2 21 HcFmRemaining Register Read Write Key Reset HCD HC Description FR Oh R R W FrameRemaining Indicates bit time When it reaches zero it is reset by loading the Framelnterval value specified in HcFmlnterval at the next bit time boundary When entering the USBOPERATIONAL state HC re loads the content with the Framelnterval of HcFminterval and uses the updated value from the next SOF FRT 0b R R W FrameRemainingToggle This bit is loaded from the FramelntervalToggle field of HcFmlnterval whenever FrameRemaining reaches 0 This bit is used by HCD for the synchronization between Framelnterval and FrameRemaining HcFmNumber Register The HcFmNumber register is a 16 bit counter which indicates the current frame number The HCD can generate a 32 bit frame number by using the FrameNumberOverrun interrupt 3 1 1 0 1 6 5 0 Figure2 28 HcFmNumber Register Table2 22 HcFmNumber Register Read Write Key Reset HCD HC Description FN Oh R R W FrameNumber This is incremented when HcFmRemaining is re loaded It will be rolled over to H O after H FFFF When entering the USBOPERATIONAL State this will be incremented automatically The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundar
12. after a hardware or software reset HcHCCA Register The HcHCCA register contains the physical address of the Host Controller Communications Area HCCA The HCCA should be aligned to a 256 byte boundary Therefore the lower 8 bit of this register is always read as 0 3 1 0 YA oo 0 8 Ll ica S 0 Figure 2 19 HcHCCA Register Rev 1 00 10 03 page 35 of 90 RENESAS Table 2 13 HcHCCA Register Read Write Key Reset HCD HC Description HCCA Oh R W R Indicates the base address of the Host Controller Communications Area HcPeriodCurrentED Register The HcPeriodCurrentED register indicates the physical address of the current Isochronous ED or Interrupt ED 3 0 0 0 1 4 3 0 PCED o Figure 2 20 HcPeriodCurrentED Register Table 2 14 HcPeriodCurrentED Register Read Write Key Reset HCD HC Description PCED Oh R R W PeriodCurrentED This is used by HC to point to the head of one of the Periodic lists which will be processed in the current Frame The content of this register is updated by HC after a periodic ED has been processed HCD may read the content in determining which ED is currently being processed at the time of reading HcControlHeadED Register The HcControlHeadED register indicates the physical address of the first ED of the Control list 3 0 0 0 1 413 CHED po Figure 2 21 HcControlHeadED Register Table 2 15 HcControlHeadED Register Read Write Key Reset HCD HC Description CHED Oh R W R C
13. enabled or disabled The Root Hub may clear this bit when an overcurrent condition disconnect event switched off power or operational bus error such as babble is detected This change also causes PortEnabledStatusChange to be set HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable This bit cannot be set when CurrentConnectStatus is cleared This bit is also set if not already at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set 0 Port is disabled 1 Port is enabled write SetPortEnable The HCD sets PortEnableStatus by writing a 1 Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortEnableStatus but instead sets ConnectStatusChange This informs the driver that it attempted to enable a disconnected port PSS Ob R W R W read PortSuspendStatus This bit indicates the port is suspended or in the resume sequence It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval This bit cannot be set if CurrentConnectStatus is cleared This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBRESUME state If an upstream resume is in progress it should propagate to the HC 0 Port is not suspended 1 Port is suspended write SetPortSuspend The HCD sets the Por
14. gt o Isochronous endpoint descriptor Da Oo o o o Interrupt head pointers W Y wn OAN WA ATE V N NY V y NW YZ IA WW U N 200 Endpoint polling interval ms Figure 2 4 Example of Periodic ED List 2 3 2 Endpoint Descriptors EDs The HCD prepares an Endpoint Descriptor ED for each endpoint of communications and gathers the information necessary to communicate with the endpoints An ED consists of 16 bytes and must be aligned with a 16 byte boundary Figure 2 5 shows the format of an ED and table 2 1 lists the details of the individual fields As was explained in section 2 3 1 all EDs for a given transfer type are linked to form a list by placing the address of the next ED in the NextED field of each ED A zero in this field indicates that the ED is not linked with any other ED After confirming that neither the sKip nor the Halted bit is set to 1 the HC compares TailP to HeadP If they are the same the HC recognizes that no TD is queued for processing and starts processing the next ED If TailP and HeadP have different values the TD indicated by HeadP will Rev 1 00 10 03 page 7 of 90 RENESAS be processed Data is transmitted from the buffer area of the TD packet by packet or a received packet is written to the buffer area After processing of a TD has been completed the value in the NextTD field of this TD is copied to the HeadP field of ED and the processed TD is moved to the
15. interrupt generated Obtain DoneQueue Take the TD from Done Queue ProcessDoneQueue Delete all TDs and EDs linked to that USBDRequest that corresponds to the D for which the transfer error occurred Clear the TD ShortPacket OK amp Data Unknown Error Control transfer USBDRequest completed Bulk transfer or Interrupt transfer Make the status of USBD_ReceiveUSBDRequest USBDReguestng emor To figure 5 8 Transfer Result Processing Y To main loop Figure 5 7 DoneQueue Processing Rev 1 00 10 03 page 89 of 90 RENESAS 5 8 Transfer Result Processing State The program enters this state from a DoneQueue processing state which has been executed by the WriteBackDoneHead interrupt A completed TD is received as a USBDRequest from the DoneQueue processing function the result of the transfer is checked and the result is returned to the Driver that requested the transfer Details of the transfer result processing state are given in figure 5 8 Done Queue processing USBDRequest structure Drive layer Search for DriverRequest USBD_Receive USBDRequest structure variable corresponding Write back the information of RequestNumber to RequestNumber the USBDRequest variable to allocated to a DriverRequest variable DriverRequest structure variable Clear the USBD variable Check the result of transfer To main loop Figure 5 8 Transfer Result Processing Rev 1
16. provided to be used as a reference when the user creates USB Host Module firmware This application note and the described software are application examples of the USB Host Module and their contents and operation are not guaranteed In addition to this application note the manuals listed below are also available for reference when developing applications Related manuals e Universal Serial Bus Specification Revision 1 1 e Open Host Controller Interface Specification for USB Revision 1 0a e SH7760 Hardware Manual e SH7760 Solution Engine MS7760CP01 Instruction Manual e SH7760 E10A Emulator User s Manual Caution Trademark The sample programs described in this application note do not include firmware related to isochronous transfer of USB transfer types When using this transfer type the user needs to create the program for it Also the hardware specifications of the SH7760 and SH7760 Solution Engine which will be necessary when developing the system described above are described in this application note but more detailed information is available in the SH7760 Hardware Manual and the SH7760 Solution Engine Instruction Manual Microsoft Windows 95 Microsoft Windows 98 Microsoft Windows Me Microsoft Windows 2000 and Microsoft Windows XP are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries Rev 1 00 10 03 page iv of vi RENESAS Content
17. the Done Queue Sequence errors occur when the amount of data received from an endpoint does not match the expected amount The categories of sequence error are STALL DATAOVERRUN and DATAUNDERRUN Once such errors have occurred the corresponding TDs are moved to the Done Queue A system error is the occurrence of trouble to do with the system environment of the HC The categories of system error are BUFFEROVERRUN and BUFFERUNDERRUN Such errors only occur in the processing of Isochronous TDs Those do not occur in the processing of General TDs Time errors also only occur in the processing of Isochronous TDs The categories of time error are skipped packets and late retirement Since each data packet of an Isochronous TD has to be transferred in a specific frame the situation can arise where it is impossible to transfer an isochronous data packet in the corresponding frame If it s not possible to send a data packet in the frame in which it should have been sent that transfer is skipped and the condition code for the data packet is set to NOTACCESSED The packet is skipped and the next one is processed When a packet has been skipped but processing of the last data packet is completed the ConditionCode in DwordO is set to NOERROR and the TD is retired However if the last data packet is skipped the ConditionCode DATAOVERRUN is placed in Dword0 and the TD is retired In this case processing of the ED is not halted and processing of the next Is
18. to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortResetStatus but instead sets ConnectStatusChange This informs the driver that it attempted to reset a disconnected port RENESAS Read Write Key Reset HCD HC Description PPS Ob R W R W read PortPowerStatus This bit reflects the port s power status regardless of the type of power switching implemented This bit is cleared if an overcurrent condition is detected HCD sets this bit by writing SetPortPower or SetGlobalPower HCD clears this bit by writing ClearPortPower or ClearGlobalPower Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask NDP In global switching mode PowerSwitchingMode 0 only Set ClearGlobalPower controls this bit In per port power switching PowerSwitchingMode 1 if the PortPowerControlMask NDP bit for the port is set only Set ClearPortPower commands are enabled If the mask is not set only Set ClearGlobalPower commands are enabled When port power is disabled CurrentConnectStatus PortEnableStatus PortSuspendStatus and PortResetStatus should be reset 0 port power is off 1 port power is on write SetPortPower The HCD writes a 1 to set the PortPowerStatus bit Writing a 0 has no effect Note This bit is always reads 1b if power switching is not supported LSDA Xb R W R W read LowSpeedDeviceAttached This bit ind
19. transfer 0 endpoint 2 MaxPacketSize 0x40 bytes Write the command from the first column of each line Characters after are ignored treated as comments Tab codes are ignored The line feed must be included A command that does not end with a line feed is not processed SetAddress is not executable by the CNT command Set Address must be executed by using the SA command Other functions and points to note are explained below e Descriptor display function Select the Show Descriptor tab Click the Descriptor button to view Descriptor information that has been obtained by clicking the GetDesc button Rev 1 00 10 03 page 65 of 90 RENESAS im RequestGenerator Main Show Descriptor Jee Info Descriptor Device bLength Config 1 bDescriptorType Interface 0 0 bEndpointAddress Endpoint 81 bmAttributes vMaxPacketSize bInterval Endpoint 02 Figure 3 12 RequestGenerator Descriptor Display A Descriptor s information can only be displayed when the Descriptor has been obtained through the GetDesc button Information on Descriptors that is gained by the Control button or Scenario button cannot be displayed e Register browsing function Select the HC Info tab The latest values of the USB host module registers are displayed whenever the HC_Regs item is clicked Double click on HC_Regs to view the values in the fields of HcControlHeadED HcControlCurrentED HcBulkHeadED an
20. 0 RENESAS 2 6 Register Specifications The HC contains registers as shown in table 2 6 Every register is accessed as a 32 bit unit by the HCD The registers of the HC are divided into four partitions specifically for Control and Status Memory Pointer Frame Counter and Root Hub Table 2 6 Offset 54 4 NDP Legend Host Controlled Operational Registers HcRevision HcControl HcCommandasStatus HclnterruptStatus HcinterruptEnable HcinterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmlnterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus 1 HcRhPortStatus NDP NDP Number Downstream Ports NDP 1 for the SH7760 Group Rev 1 00 10 03 page 26 of 90 RENESAS 2 6 1 Control and Status Partition HcRevision Register 3 o o 1 87 0 REV Figure 2 13 HcRevision Register Table2 7 HcRevision Register Read Write Key Reset HCD HC Description REV 10h R R Revision This read only field contains the BCD representation of the version of the HCI specification that is implemented by this HC For example a value of H 11 corresponds to version 1 1 All of the HC implementations that are compliant with this specification will have a value of H 10 HcControl Register This
21. 15 HcCommandStatus Register Table 2 9 HcCommandStatus Register Read Write Key Reset HCD HC Description HCR Ob R W R W HostControllerReset This bit is set by HCD to initiate a software reset of HC Regardless of the functional state of HC it moves to the UsBSUSPEND state in which most of the operational registers are reset except those stated otherwise e g the InterruptRouting field of HcControl and no Host bus accesses are allowed This bit is cleared by HC upon the completion of the reset operation The reset operation must be completed within 10 us This bit when set should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports CLF Ob R W R W ControlListFilled This bit is used to indicate whether there are any TDs on the Control list It is set by HCD whenever it adds a TD to an ED in the Control list When HC begins to process the head of the Control list it checks CLF As long as ControlListFilled is 0 HC will not start processing the Control list If CF is 1 HC will start processing the Control list and will set ControlListFilled to 0 If HC finds a TD on the list then HC will set ControlListFilled to 1 causing the Control list processing to continue If no TD is found on the Control list and if the HCD does not set ControlListFilled then ControlListFilled will still be O when HC completes processing the Control list and Control list processing will stop
22. 3 page 64 of 90 RENESAS Table 3 3 Examples of Writing SA 2 line feed Examples of Scenario File Entries Transfer Issues the SetAddress command for address 2 SC 1 line feed Issues the SetConfig command for configuration 1 GDD 12 line feed Issues the GetDescriptor Device command for transfer size 0x12 GDC 400 line feed Issues the GetDescriptor Config command for transfer size 0x400 CNT 0009010000000000 0 1 line feed Issues the SetConfig command for configuration 1 CNT 8006000100001200 12 2 line feed Issues the GetDescriptor Device command for transfer size 0x12 CNT 8006000200000004 0400 2 line feed Issues the GetDescriptor Config command for transfer size 0x400 INT 1 41020 4 20 line feed Interrupt transfer is carried out with the following settings Endpoint 1 amount for transfer 0x4 bytes polling rate 10 msec direction of transfer 2 IN data for transfer 0 MaxPacketSize 0x4 bytes transfer count 0x20 times BLK 40 1 transfer data 1 40 line feed Bulk transfer is carried out with the following settings Amount for transfer 0x40 bytes direction of transfer 1 OUT data for transfer omitted endpoint 1 MaxPacketSize 0x40 bytes BLK 40 2 0 2 40 line feed Notes Bulk transfer is carried out on following settings Amount for transfer 0x40 bytes direction of transfer 2 IN data for
23. 4 shows the connection processing for a connected device As was explained in section 5 3 connection of a device to the Root Hub generates a RootHubStatusChange interrupt and the USBD layer is informed of the connection The function USBD ReportConnection is called from the HCD ControlRootHub function USBD ReportConnection initializes the USBD layer and calls the EnumerationDriver The EnumerationDriver carries out the SetAddress processing to allocate the DeviceAddress and through GetDescriptor processing obtains the Descriptor information on the device that has been connected Of this information the Class information on the connected device is used to select the most appropriate driver Note Inthis sample program the connected device is controlled from the RequestGenerator a tool which runs on the PC Therefore drivers are not called From Root Hub processing state USBD ReportConnetion HCD_ControlRootHub Initialization of USBD layer Call EnumerationDriver Usb_Dr_EnuDr c Initialization of EnumerationDriver Execute SetAddress Execute GetDescriptor Use the obtained Descriptor information to distinguish the connected device type Define which driver to call and then call a driver To main loop Figure 5 4 Connection Processing Rev 1 00 10 03 page 86 of 90 RENESAS 5 5 Serial Input State ReguestGeneratorDriver Processing State The flow chart for serial input processing is given in figure 5 5 Clicki
24. C R W ConditionCode Indicates the status of the last transfer generated by GTD CBP R W CurrentBufferPointer Indicates the buffer area for transfer to from the endpoint The address of buffer to be accessed next is always indicated When CurrentBufferPointer is 0 data of size 0 will be transferred or the transfer has been completed NextTD R W NextTD Points the next TD BE R BufferEnd Indicates the last address of the buffer area Rev 1 00 10 03 page 11 of 90 RENESAS The CurrentBufferPointer of the GTD indicates the address of the data buffer and is referred to when the HC generates a data packet for the endpoint indicated by the ED with which the GTD is linked On completion of the transfer of each packet generated from the GTD the result of the transfer is written to the ConditionCode field When the transfer has been completed without error the value of the CurrentBufferPointer is updated by the amount transferred The MSb of the DataToggle field indicates the source of the data PID value of the first data packet generated from this TD When MSb 0 the source is the toggleCarry bit of the ED and is not LSb of DataToggle field of the GTD When MSb is 0 the source is the LSb of DataToggle field Bulk and interrupt transfers usually start with the DataToggle field set to 00b When a TD is retired and processing switches to the next TD the toggle information is carried over the LSb of the DataToggle field is copied to the t
25. CCA Communications are performed via registers in the HC or via the HCCA in memory EDs and TDs are transferred between the HCD and HC The HCD creates an ED for a transfer and the TDs for the data to be transferred links them in a list and then sends the list to the HC The HC generates USB packets from the received ED and TDs and transfers the packets to the endpoint indicated by the ED The HC places the transfer completed TDs in the Done Queue and sends the head pointer to the Done Queue of completed TDs back to the HCD at specified intervals Four items of information are transferred between the HCD and HC the control list and bulk list for nonperiodic transfer the list for periodic transfer and the Done Queue Communication between the HCD and HC is through the transfer of pointers to the respective head addresses The two head pointers for nonperiodic transfer are transferred via registers while the head pointers for periodic transfer and the Done Queue are transferred via the HCCA in other words the latter two lists are transferred via memory This is shown in figure 2 11 Rev 1 00 10 03 page 21 of 90 RENESAS Device enumeration OpenHCI Operational Host Controller registers Communications Area eeu lI Device registers in USB host module Figure 2 11 Communication Channels Rev 1 00 10 03 page 22 of 90 RENESAS 24 Responsibilities of Host Controller Drive 2 4 1 Management of Host Controller The HCD mai
26. D InitializeEndpoint Generate Endpoint variable and make ED variable HCD GetRootDeviceSpeed Obtain information of device speed connected to RootHub HCD ScanEndpoint Access to array for Endpoint control HCD_StoreEndpoint Access to array for Endpoint control HCD_Request Generate Endpoint variable ED variable and TD variable from received USBDRequest HCD CheckDiffEPs Confirm whether setting of Endpoint has changed HCD CheckRemainedTDs Check the number of remaining TD variable HCD CheckRemainedEDs Check the number of remaining ED variable HCD CheckRemainedEPs Check the number of remaining Endpoint HCD PauseEndpoint Pause ED processing HCD_RemoveEndpoint Delete Endpoint variable and ED variable HCD_CancelRequest Delete transfer requested USBDRequest HCD_FreeEndpoint Clear Endpoint variable FreeEndpointDescriptor Clear ED variable HCD_ClearDeviceData Clear DeviceData variable HCD_ClearList Initialize array for Endpoint ED and TD variables HCD_ClearHCCA Initialize HCCA area HCD_WaitConnection Complete Connect device to RootHub HCD_WaitRoutine Wait routine In Usbh_Hcd_Others c contains common functions called from the HCD layer function and functions called from the USBD layer Rev 1 00 10 03 page 77 of 90 RENESAS Table 4 6 File in Which Stored Usbh Usbd Common c Usb h Usbd Common c F
27. ESAS Read Write Key Reset HCD HC Description CCIC Ob RW RW OverCurrentindicatorChange This bit is set by the HC when a change has occurred to the OCI field of this register The HCD clears this bit by writing a T Writing a 0 has no effect CRWE Ww R write ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable Writing a has no effect HcRhPortStatus 1 and NDP Registers The HcRhPortStatus register is used to control and report port events on a per port basis The lower word is used to set the port status Whereas the upper word monitors the status change of ports reserved 2 1 DU O O Ulw o Qo TIPO muj o oojoo o O o o o 1 1 0 0 5 0 7 5 I Figure 2 34 HcRhPortStatus Register Table 2 28 HcRhPortStatus Register Read Write Key Reset HCD HC CCS Ob RW RW Rev 1 00 10 03 page 46 of 90 Description read CurrentConnectStatus This bit reflects the current state of the downstream port 0 No device connected 1 Device connected write ClearPortEnable The HCD writes a 1 to this bit to clear the PortEnableStatus bit Writing a 0 has no effect The CurrentConnectStatus is not affected by any write Note This bit is always read 1b when the attached device is nonremovable DeviceRemoveable NDP RENESAS Read Write Key Reset HCD HC Description PES Ob R W R W read PortEnableStatus This bit indicates whether the port is
28. Emulator manufactured by Renesas Technology Corp PC Windows 95 98 equipped with a PCMCIA slot Control PC Windows 98 Windows 2000 Serial cable cross cable supplied together with the MS7760CP01 USB cable Debugging Interface hereafter called HDI manufactured by Renesas Technology Corp High performance Embedded Workshop hereafter called HEW manufactured by Renesas Technology Corp USB function device any device Rev 1 00 10 03 page 53 of 90 RENESAS 3 1 Hardware Environment Figure 3 1 shows the device connections Control PC Windows 98 Windows 2000 E10A PC Windows 95 Windows 98 User firmware can be developed by using HDI HEW As a PC for serial connection requests generation of USB packet from RequestGenerator USB cable Any USB function device Transfer USB function device Figure 3 1 Device Connections Rev 1 00 10 03 page 54 of 90 RENESAS 1 SH7760SE The DIP switch and jumper settings on the SH7760SE board must be changed from those at shipment Before turning on the power ensure that the switch and jumper are set as shown in table 3 1 There is no need to change any other DIP switches or jumpers Table 3 1 Switch and Jumper Settings At Time of Switch and Jumper Shipment After Change Function CPU board SW5 8 OFF ON Selects endian mode big endian Debug board J1 1 2 Closed Open Specifies CSO area sections flash memory area placed at the top 2 Control PC A
29. HC enters UsBSUSPEND after a software reset whereas it enters USBRESET after a hardware reset The latter also resets the Root Hub IR Ob R W R InterruptRouting This bit determines the routing of interrupts generated by events registered in HclnterruptStatus If clear all interrupts are routed to the normal host bus interrupt mechanism If set interrupts are routed to the System Management Interrupt HCD uses this bit as a tag to indicate the ownership of HC RWC Ob R W R W RemoteWakeupConnected This bit indicates whether HC supports remote wakeup signaling If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST HC clears the bit upon a hardware reset but does not alter it upon a software reset RWE Ob R W R RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling When this bit is set and the ResumeDetected bit in HcinterruptStatus is set a remote wakeup is signaled to the host system Rev 1 00 10 03 page 29 of 90 RENESAS HcCommandStatus Register The HCD requests the list processing HC reset and honor ship change to the HC by using this register The number of frames with which the HC has detected the scheduling overrun error is counted by this register 3 1 1 1 1 0 0 0070 1 8 7 6 5 4 3 2 1 0 S O B C H reserved O reserved C L L C C RIFIFIR Figure 2
30. Line in the View menu to open a window figure 3 8 click the BatchFile button on the upper left and specify the 7760e10a hdc file in the SH7760 folder As a result the BSC is set and access to the SDRAM is enabled e Select LoadProgram from the File menu in the Load Program dialog box specify debugger ABS in the SH7760 folder e Select Go from the Run menu bar to execute the program Through the above procedure the sample program can be loaded into the RAM of the SH7760SE Figure 3 7 Reset Request Dialog Rev 1 00 10 03 page 59 of 90 RENESAS El Command Lineno batch fileno log 1 O O x Batch file Figure 3 8 Command Line Input 3 4 Execution Activation of RequestGenerator 1 Execute the sample program according to the procedure of section 3 3 1 After successful launching of the sample program OK AA is displayed on the SH7760SE s 8 bit LEDs 2 Copy the ocx file from the ReqGen folder to the Windows System32 folder Windows 98 or WinNT System32 Windows 2000 3 Execute ReqGen exe which is in the ReqGen folder This opens the COMI port Rev 1 00 10 03 page 60 of 90 RENESAS Show Descriptor HC Info Start MemoryRead Set ddress Finish Scenario SetConfig GetDesc Interrupt Control Bulk Status PortStatus Opened RequestGenerator I Disable DeviceSpeed I TE EndPoint laa MaxPacketSize 8 Figure 3 9 Initial Screen of the RequestGenerator 4 Click St
31. PC with Windows 98 Windows 2000 installed and with a serial interface is used as a PC for USB packet generation tool RequestGenerator 3 PC equipped with a PCMCIA slot E10A PC The E10A should be inserted into a PC card slot and connected to the SH7760SE via an interface cable After connection start the HDI and perform emulation Rev 1 00 10 03 page 55 of 90 RENESAS 3 2 Software Environment A sample program as well as the compiler and linker used are explained 3 2 1 Sample Program Files required for the sample program are all stored in the SH7760 folder When this entire folder with its contents is moved to a PC on which HEW and HDI have been installed the sample program can be used immediately Files included in the folder are shown in figure 3 2 StartUp c AsmFunction src Sct src SH7760 h st16c_uart h USBHost folder Usbh_dr_EnuDrDefs h Usbh_ Dr_DrList h Usbh_Usbd_Defs h Usbh Hcd TypeDef h Usbh_Hcd_ProType h Usbh Hcd Defs h Usbh Usbd Common c Usbh Hcd Tasks c Usbh Hcd Main c Usbh Hcd Main c Usbh Dr StorageDr c debugger ABS debugger MAP debugger MOT log txt dwfinf folder BuildOfHew bat InkSet1 sub Figure 3 2 Files Included in SH7760 Folder 3 2 2 Compiling and Linking The sample program is compiled and linked using the following software High performance Embedded Workshop Version 1 0 release 9 hereafter called HEW When HEW is installed in C Hew the procedure for compiling and linking the progra
32. Rev 1 00 10 03 page 30 of 90 RENESAS Key BLF Reset Ob Read Write HCD R W HC R W Description BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list It is set by HCD whenever it adds a TD to an ED in the Bulk list When HC begins to process the head of the Bulk list it checks BF As long as BulkListFilled is 0 HC will not start processing the Bulk list If BulkListFilled is 1 HC will start processing the Bulk list and will set BF to O If HC finds a TD on the list then HC will set BulkListFilled to 1 causing the Bulk list processing to continue If no TD is found on the Bulk list and if HCD does not set BulkListFilled then BulkListFilled will still be O when HC completes processing the Bulk list and Bulk list processing will stop OCR Ob R W R W OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC When set HC will set the OwnershipChange field in HclnterruptStatus After the changeover this bit is cleared and remains so until the next request from OS HCD SOC 00b R W SchedulingOverrunCount These bits are incremented on each scheduling overrun error It is initialized to B OO0b and wraps around at B 11 This will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HclnterruptStatus has already been set This is used by HCD to monitor any persistent scheduling problems HcInter
33. RhDescriptorA register is the first register of two describing the characteristics of the Root Hub 3 2 2 1 4 14 1 0 0 1 413 3 2 1 0 7 0 POTPGT reserved N O D N P NDP T P S SIM Figure 2 31 HcRhDescriptorA Regis Table 2 25 HcRhDescriptorA Regis Read Write Key Reset HCD HC NDP IS R R Description NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub The minimum number of ports is 1 The maximum number of ports supported by OpenHCl is 15 NPS IS RW R NoPowerSwitching These bits are used to specify whether power switching is supported or ports are always powered When this bit is cleared in other words power switching is enabled the PowerSwitchingMode specifies global or per port switching 0 Ports are power switched 1 Ports are always powered on when the HC is powered on PSM IS RW R Rev 1 00 10 03 page 42 of 90 PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled This field is only valid if the NoPowerSwitching field is cleared 0 All ports are powered at the same time 1 Each port is powered individually This mode allows port power to be controlled by either the global switch or per port switching If the PortPowerControlMask bit is set the port responds only to port power commands Set ClearPortPower If the port mask is cleared then the port is controlled only by the global po
34. S Table 2 2 Field Definitions for General TD Name HC Access Description R R bufferRounding If the last packet generated by GTD is short packet a DataUnderrun error is generated When this field is set to 1 a DataUnderrun error is neglected DP R Direction PID Direction of transfer and PID are set PID Type Data Direction SETUP to endpoint OUT to endpoint IN from endpoint Reserved DI R Delaylnterrupt The timing of an interrupt WriteBackDoneHead generation which is generated after the TD has been completed is defined The HC waits for frames set by this field before generating an interrupt If setting value is 0 an interrupt is generated immediately If the setting value is 1 an interrupt is generated after waiting for one frame If setting value is 111b no interrupt is generated T R W DataToggle Sets the PID DATAO DATA1 of data packet by LSb It is updated after each successful transmission reception of a data packet The MSb of this bit is 0 when the data toggle value is acquired from the toggleCarry field in the ED The MSb of this bit is 1 when the data toggle value is acquired from this field EC R W ErrorCount For each transmission error this value is incremented If ErrorCount is 2 and another transfer error occurs the error type is recorded in the ConditionCode field and placed on the Done Queue When a transaction completes without error ErrorCount is reset to 0 C
35. SetFramelnterval Arrange value of frame interval Get32BitFrameNumber Generate 32 bit frame number from 16 bit length HccaFrameNumber Functions of Usbh Hcd Tasks c are all based on the sample codes in section 5 of the OpenHCI specification The function carries out generation and deletion of EDs and TDs Table 4 5 Usbh Hcd Others c File in Which Stored Usbh Hcd Others c Function Name HCD CreateDeviceData Purpose Initialize DeviceData structure variable HCD CreateEndPoint Initialize Endpoint structure variable HCD SetupEndpoint Setup Endpoint structure variable AllocateEndpointDescriptor Reserve ED variable PhysicalAddressOf Obtain address IsListEmply Define whether List Entry variable is null or not AllocateTransferDescriptor Reserve TD variable InsertHeadList Insert List Entry variable in start of List InsertTailList Insert List Entry variable in end of List Containing Record Find ED and TD which meet condition InitializeListHead Rev 1 00 10 03 page 76 of 90 Initialize List Entry variable RENESAS File in Which Stored Function Name Usbh Hcd Others c Purpose min Define minimum value CompleteUsbdReguest Send completed USBDReguest variable to USBD layer FreeTransferDescriptor Delete TD variable RemoveListHead Delete LIST_ENTRY variable RemoveListEntry Delete LIST_ENTRY VirtualAddressOf Obtain address HC
36. The Done Queue which is the list of completed TDs is received in this state e Serial Communications State The program enters this state in response to a UART receive interrupt that occurs while the program is in the steady state Communications with the RequestGenerator which is a tool running on the PC take place in this state Rev 1 00 10 03 page 70 of 90 3 NE S AS Reset state Initial setting completed Connection wait sate RootHubStatusChange Root Hub intgerrupt generated processing state T Connection Connection processing state Disconnection RootHubStatusChange Disconnection interrupt generated processing state Steady state p ds OverCurrent processing state Transfer result processing state WriteBackDoneHead interrupt generated Serial output state Done Queue processing state Serial communications state Serial input state Transfer request generation state Figure 4 1 State Transition Diagram Rev 1 00 10 03 page 71 of 90 l ENESAS 4 2 Types of Interrupts As was explained at the beginning of section 4 the USB host module interrupts are used in this sample program The three interrupt sources in use are indicated by the HcInterruptStatus register When an interrupt occurs the flag bit for the corresponding interrupt source is set to 1 and an interrupt request is sent to the CPU The sample program includes appropriate interrupt handling Figure 4 2 shows the types of inte
37. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inguiry 24 N S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise
38. W PortSuspendStatusChange This bit is set when the full resume seguence has been completed This seguence includes the 20 msec resume pulse LS EOP and 3 mssec resychronization delay The HCD writes a 1 to clear this bit Writing a 0 has no effect This bit is also cleared when ResetStatusChange is set 0 Resume is not completed 1 Resume completed OCIC Ob R W RW PortOverCurrentIndicatorChange Rev 1 00 10 03 page 50 of 90 This bit is valid only if overcurrent conditions are reported on a per port basis This bit is set when Root Hub changes the PortOverCurrentIndicator bit The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 no change in PortOverCurrentIndicator 1 PortOverCurrentIndicator has changed RENESAS Read Write Key Reset HCD HC Description PRSC Ob R W R W PortResetStatusChange This bitis set at the end of the 10 ms port reset signal The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 port reset is not complete 1 port reset is complete Rev 1 00 10 03 page 51 of 90 RENESAS Rev 1 00 10 03 page 52 of 90 RENESAS Section 3 Development Environment This section describes the development environment used to develop this system The devices tools listed below were used when developing the system SH7760 Solution Engine type number MS7760CP01 hereafter referred to as SH7760SE manufactured by Hitachi ULSI Systems Co Ltd SH7760 E10A
39. _Request f ZO ZO a QueueGeneralRequest f Ly ZWA LLL lh LEE HCD CreateEndpoint f PETET OpenPipe InsertEDForEndpoint j Figure 4 4 Interrelationship between Functions Rev 1 00 10 03 page 82 of 90 RENESAS Section 5 Operation of Sample Program The operation of the sample program is explained in this section 5 1 Reset State The internal state of the CPU and the registers of the on chip peripheral modules are initialized while the microcomputer is in the reset state Next the reset interrupt function CallResetException is called reset exception processing is handled and the SetPowerOnSection function is called Figure 5 1 is a flow chart of operation from occurrence of the reset interrupt occurs to entry to the steady state main loop Microcomputer reset CallResetException Set ports H2 H1 and HO as USB pins BSC initial settings Reserve the HCCA area and Set the data alignment mode set address in HcHCCA in the DMA USB control registers SetPowerOnSection Microcomputer initial settings Set HcPeriodicStart Initialize variables USB host initial settings HCD Setup Set DeviceData structure variable Set HcFminterval Clear RAM to 0 Build the List of periodic EDs Initialize UART Set the port s power mode to Per Port Power and Clear the USB interrupt mask disable overcurrent in the interrupt mask clear register Change the HC s state from Reset to Operational Set the USB inter
40. age 43 of 90 RENESAS Table 2 26 HcRhDescriptor Register Read Write Key Reset HCD HC Description DR IS R W R DeviceRemovable Each bit is dedicated to a port of the Root Hub When cleared the attached device is removable When set the attached device is not removable bit 0 Reserved bit 1 Device attached to Port 1 bit 2 Device attached to Port 2 bit15 Device attached to Port 15 PPCM IS R W R PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set When set the port s power state is only affected by per port power control Set ClearPortPower When cleared the port is controlled by the global power switch Set ClearGlobalPower If the device is configured to global switching mode PowerSwitchingMode 0 this field is not valid bit 0 Reserved bit 1 Ganged power mask on Port 1 bit 2 Ganged power mask on Port 2 bit15 Ganged power mask on Port 15 HcRhStatus Register The HcRhStatus register specifies the status of the Root Hub 1 8 4 2 reserved reserved O C I Figure 2 33 HcRhStatus Register Rev 1 00 10 03 page 44 of 90 RENESAS Table 2 27 HcRhStatus Register Read Write Key Reset HCD HC Description LPS Ob R W R read LocalPowerStatus The Root Hub does not support the local power status feature thus this bit is always read as 0 write ClearGlobalPower In global power mode PowerSwitchingMode 0 th
41. al register contains a 14 bit value which indicates the bit time interval in a frame between two consecutive SOFs and a 15 bit value indicating the maximum packet size that the HC can transfer without causing scheduling overrun The HCD can carry out minor adjustment on the frame interval This register provides the programmability necessary for the HC to synchronize with an external clock source and to adjust any unknown local clock 3 1 F 1 11 1 0 6 54 3 0 FSMPS reserved FI T Figure 2 26 HcFmInterval Register Table 2 20 HcFmlnterval Register Read Write Key Reset HCD HC Description Fl 2bEDFh R W R Framelnterval This specifies the interval between two consecutive SOFs in bit times The nominal value is set to be 11 999 HCD should store the current value of this field before resetting HC By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value FSMPS TBD R W R FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun The field value is calculated by the HCD FIT 0b R W R FramelntervalToggle HCD toggles this bit whenever it loads a new value to Framelnterval HcFmRemaining Register
42. art Main snow Descriptor HC Info MemoryRead Setaddress XE a Request Generator For 5H77275E Ver0 0 Finish Scenario setcon ig C Copyright 2002 Hitachi Ltd All rights reserved GetDesc Interrupt Control Bulk Status PortStatus Opened RequestGenerator I Enable DeviceSpeed i EndPoint MaxPacketSize 8 Figure 3 10 Screen when the RequestGenerator is Active Rev 1 00 10 03 page 61 of 90 RENESAS 5 Connect the USB function device to the USB A connector of the SH7760 SE When the connection is detected the GetDescriptor Device command is executed and the MaxPacketSize information on endpointO is obtained Information on the speed of the connected device can also be obtained Note To use the RequestGenerator click Start before connecting the device im RequestGenerator Main snow Descriptor HC Info MemoryRead seradaress P Request Generator For SH7727SE Ver0 0 Finish Scenario setcon ig Copyright 2002 Hitachi Ltd All rights reserved GetDesc Interrupt EPOMPS Complete GetEnvironnent Control Bulk Status PortStatus Opened RequestGenerator Enable DeviceSpeed I 0 EndPoint0 as aa MaxPacketsize 8 Figure 3 11 RequestGenerator Screen when a Device is Connected Perform the desired operation Pull the plug for the USB function device from the SH7760SE s USB A socket Click the Finish button Various USB function de
43. ated from the TD indicated by the HeadP of ED4 and processed Figure 2 8 List Processing 2 3 6 Done Queue The HC links TDs for which transfer has been completed in another list This is called the Done Queue An example of a Done Queue is shown in figure 2 9 Consider the situation where the list indicated by List as the one to be processed by the HC initial condition and transfer for TD1 1 TD2 1 TD3 1 and TD4 1 in the list is completed during Frame R processing Each time the transfer for a TD is completed that TD is linked to the Done Queue As is shown in figure 2 11 the latest transfer completed TD for which processing has most recently been completed is always linked to the head of the Done Queue The oldest transfer completed TD is always at the end of the queue Rev 1 00 10 03 page 18 of 90 RENESAS Done Queue after transfer for TD4 1 Done Queue after transfer for TD1 1 Head Head Done Queue Frame R 1 Frame R Frame R 1 TD1 1 TD2 1 TD3 1 TD4 1 Completion Completion Completion Completion of processing of processing of processing of processing List List initial condition List after transfer for TD4 1 Pointer Figure 2 9 The Done Queue Figure 2 10 shows the flow for the linking of TDs to the Done Queue on completion of the corresponding transfers On completion of the transfer for TD1 in figure 2 10 processing by the HC is as listed below 1 The value of the NextTD of t
44. be used to evaluate the USB host module of the SH7760 quickly 2 The sample program supports control bulk and interrupt transfers 3 Additional programs can be created to support isochronous transfer Note Isochronous transfer program is not provided and will need to be created by the user Rev 1 00 10 03 page 2 of 90 RENESAS Section 2 Overview of the Open Host Controller Interface OpenHCI Specification The USB host module incorporated in the SH7760 supports to the Open Host Controller Interface hereafter referred to as OpenHCI specification The OpenHCI specification is explained in this section Refer to this section when developing a USB host system For details of the OpenHCI specification see Revision 1 0a of the Open Host Controller Interface Specification for USB 2 1 OpenHCI Standard The hierarchical structure of a USB host system consists of the USB device host controller HC host controller driver HCD USB driver USBD and client software levels The OpenHCI specification prescribes the functions of the HCD and HC and the interface between them that is the interface between the software and hardware Client Software Software USB Driver Host Controller Driver Scope of OpenHCI Host Controller Hardware USB Device Figure 2 1 USB Focus Areas Rev 1 00 10 03 page 3 of 90 RENESAS 2 2 Data Transfer Types The four data transfer types defined for the USB are listed below Interr
45. d DriverRequest function to USB layer and request transfer DriverCommon Endian Endian conversion Usbh Dr EmuDr c carries out the processing for EnumerationDriver The function carries SetAddress for the connected device distinguishes DeviceClass and defines which Driver to call Table4 8 Usbh App Log c File in Which Stored Function Name Usbh App Log c App LogOut Char Purpose Function to output character string App LogOut Data Function to output character string App ExOutPut Function to output 1 byte string variable Rev 1 00 10 03 page 79 of 90 RENESAS Usbh App Log c serially outputs information of debugging Table 4 9 File in Which Stored Usbh Dr RegGenDr c Usbh Dr RegGenDr c Function Name App_ReceiveCommand Purpose Receive command data from RequestGenerator App_CheckReceiveCommand Define received command data DisableRequestGenerator Carry out RequestGenerator end processing DoRequestGenerator Initialize RequestGeneratorDriver DoSetAddress Request SetAddress ReceiveSetAddressResult Receive result of SetAddress request DoGetDescriptorDevice Request GetDescriptor Device request ReceiveGetDescriptorDevice Result Receive result of GetDescriptor Device request DoGetDescriptorConfig Request GetDescriptor Config request ReceiveGetDescriptorConfig Result Receive the result of GetDescriptor Config request
46. d HcBulkCurrentED Rev 1 00 10 03 page 66 of 90 RENESAS Main Show Descriptor HC Info Figure 3 13 HcHcca HccalInterruptLlist HcPeriodCurrentED cControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED Figure 3 14 HcRevision HcControl HcConmandStatus HcInterrupt3tatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodicCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHeadED HcFmInterval HcFrameRemaining HcFmNunber HcPeriodicStart HcLSThreshold HcRhDescriptora HcRhDescriptorB HcRhStatus HcRhPort tatusl HeRhPortstatus2 00000010 000000bc 00000000 00000004 80000062 80000062 ad700000 00000000 ad500620 00000000 00000000 00000000 00000000 27782edf 00000b0d 0000e0lb 00002a2f 00000628 02000902 00060000 00000000 00000008 00000103 RequestGenerator Register Display HcControlHeadED Dwordo 00080002 HcControlHeadED Dwordl ad500cb0 HcControlHeadED Dword2 ad500cb0 HcControlHeadED Dword3 ad5005f0 HcControlHeadED MPS HcControlHeadED F HcControlHeadED K HcControlHeadED 5 HcControlHeadED D HcControlHeadED EN HcControlHeadED F HcControlHeadED HcControlHeadED HcControlHeadED HcControlHeadED HcControlHeadED RENESAS 0 0 ADSOOSFO RequestGenerator Register Display Rev 1 00 10 03 page 67 of 90 Rev 1 00 10 03 page 68 of 90 RENESAS Section 4 Overview of the Sample Program The features and structure of the sample pr
47. e RegGenDr data area 1028byte Notes The memory map differs according to the compiler version compiling conditions firmware upgrade etc Placed in the P3 cache write through space Consequently the address bits A31 to A29 are 110 Figure 3 6 Memory Map As shown in figure 3 6 this sample program allocates areas of P C D R and B to the SDRAM In order to use the E10A for break and other functions the program must be placed in RAM in this way These memory allocations are specified by the InkSet1 sub file in the SH7760 folder When incorporating the program in ROM by writing it to flash memory or some other media this file must be modified Rev 1 00 10 03 page 58 of 90 RENESAS 3 3 1 Loading the Program In order to load the sample program into the SDRAM of the SH7760SE the following procedure is used e Insert the EIOA in which the HDI has been installed into the E10A PC connect the E10A to the SH7760SE via a user cable and connect the COMI port of serially connected PC to the SH7760SE via a serial cable e Turn on the power to the E10A PC and serially connected PC for start up e Initiate the HDI e Turn on the power to the SH7760SE connect the AC adapter and press SW1 on the CPU board for about 10 seconds e A dialog figure 3 7 is displayed on the PC screen turn the SH7760SE reset switch SW2 on the CPU board on and after resetting the CPU click the OK button or press the Enter key e Select Command
48. e HccalnterruptTable is used to store these pointers The HC accesses the HccalnterruptTable once per frame and obtains the corresponding pointer The HccaFrameNumber field is updated by the HC on every frame The HC updates HcFrameNumber before issuing the start of frame packet SOF After that the HC updates the HecaFrameNumber and then reads the ED to be processed first in that frame The value of HcDoneHead is written to the HccaDoneHead field After a TD has been processed and the number of frame periods indicated by the DelayInterrupt field has passed processing of the next frame starts and the value in HcDoneHead is written to the HccaDoneHead Rev 1 00 10 03 page 17 of 90 RENESAS 2 3 5 List Processing Figure 2 8 shows a situation where there are four EDs ED1 ED2 ED3 and ED4 with one or more TDs linked to each ED The HC neither processes a single ED until all TDs linked to that ED have been retired nor processes a single TD until the TD has been retired The HC repeatedly generates single data packets for transfer from the first TD of each ED so that processing is shared among the EDs a TD1 1 TD2 1 Y TD1 3 Flow of processing One USB packet is generated from the TD indicated by the HeadP of ED1 and processed One USB packet is generated from the TD indicated by the HeadP of ED2 and processed One USB packet is generated from the TD indicated by the HeadP of ED3 and processed One USB packet is gener
49. ed in bulk transfer InitSystem Pull up control of the USB bus Scilnit UART initialization When a power on reset or manual reset is carried out SetPowerOnSection in StartUp c is called At this point the SH7760 initial settings are carried out After that the RAM area used for the transfers is cleared Table 4 3 Usbh Hcd Main c Purpose File in Which Stored Function Name Usbh Hcd Main c HCD Setup Initializes the HCD HCD_IntRoutine Interrupt processing routine HCD_MainRoutine HCD layer main routine HCD_ControlRootHub Control RootHub In Usbh Hcd Main c the HCD is initialized and various interrupts are processed when they are occurred Also when the RootHubStatusChange interrupt is occurred Root Hub is controlled Rev 1 00 10 03 page 75 of 90 RENESAS Table 4 4 File in Which Stored Usbh Hcd Tasks c Usb Hcd Tasks c Function Name InsertEDForEndpoint Purpose Generate ED and add it to list QueueGeneralRequest Generate TD and link it to ED ProcessDoneQueue DoneQueue processing InitializelnterruptLists Build Interrupt list OpenPipe Generate periodic ED and add it to list CheckBandwidth Check bandwidth PauseED Pause ED ProcessPausedED Pause ED RemoveED Delete existing ED CancelRequest Cancel processing of existing USBDRequest Delete generated TD UnschedulelsochronousOr InterruptEndpoint Delete periodic ED
50. et and the MasterInterruptEnable bit is set a hardware interrupt is generated Writing a 1 to a bit in this register sets the corresponding bit Writing a 0 to a bit in this register leaves the corresponding bit unchanged To clear the corresponding bit write 1 to a bit in the HcInterruptDisable register 2 0 0 9 7 3 Figure 2 17 HcInterruptEnable Register Rev 1 00 10 03 page 33 of 90 RENESAS Table 2 11 HclnterruptEnable Register Read Write Key Reset HCD HC Description SO Ob RW R 0 Ignored 1 Enables interrupt generation due to Scheduling Overrun WDH Ob R W R 0 Ignored 1 Enables interrupt generation due to HcDoneHead Writeback SF Ob R W R 0 Ignored 1 Enables interrupt generation due to Start of Frame RD Ob R W R 0 Ignored 1 Enables interrupt generation due to Resume Detect UE Ob R W R 0 Ignored 1 Enables interrupt generation due to Unrecoverable Error FNO Ob R W R 0 Ignored 1 Enables interrupt generation due to Frame Number Overflow RHSC Ob R W R 0 Ignored 1 Enables interrupt generation due to Root Hub Status Change OC Ob RW R 0 Ignored 1 Enables interrupt generation due to Ownership Change MIE Ob R W R 0 Ignored 1 Enables interrupt generation due to other bits of this register This is used by HCD as a Master Interrupt Enable HcInterruptDisable Register Each bit in the HcInterruptDisable register corresponds to each bit in the HcInterruptStatus register The HcInterr
51. et4 PSW4 Dword 7 Offset7 PSW7 Offset6 PSW6 Figure 2 7 Isochronous TD Format The data packets generated from an Isochronous TD have to be transferred within specific frames From 1 to 8 consecutive frames of data to be transferred are set in an Isochronous TD FrameCount 1 frames of data are consecutively transferred with the first packet placed in the Rev 1 00 10 03 page 12 of 90 RENESAS frame specified by StartingFrame When the difference between the HcFmNumber register and the StartingFrame is R data packets are isochronously transferred until R has been incremented from 0 to the number in FrameCount Offset R determines the first buffer address of each frame The lower 12 bits are always specified by Offset R The upper 20 bits are given by BufferPageO when the 12th bit of Offset R is O and by the 20 higher order bits of BufferEnd when the 12th bit of Offset R is 1 The last address in the buffer for each frame from R 0 to FrameCount 1 is defined by Offset R 1 1 and the same 20 higher order bits as are defined for the first address The last address of the last data packet R FrameCount is BufferEnd On completion of the transfer of each frame the Offset PSWN fields of the frame become PSWN fields the ConditionCode and SizeOfPacket data are written to these fields Table 2 3 Field Definitions for Isochronous TD Name HC Access Description SF R StartingFrame Indicates the transfer start frame of data packet DI R
52. he packets of data that are transmitted to received from an endpoint TDs are categorized into General Transfer Descriptors GTDs and Isochronous Transfer Descriptors ITDs The GTD is used in control transfer bulk transfer and interrupt transfer while the ITD is used in isochronous transfer Both the GTD and ITD specify a buffer with a length of 0 to 8192 bytes A TD is linked to the ED which corresponds to the endpoint for the transfer The HCD generates TDs and links TDs to EDs The HC processes each TD and after the processing has been completed the TD is moved from the ED to the Done Queue Rev 1 00 10 03 page 9 of 90 RENESAS The details of the GTD and ITD are explained below General Transfer Descriptor GTD The Transfer Descriptors TDs that are used in control bulk and interrupt transfer all have the same format and are called General TDs GTDs The format and individual fields of the GDT are shown in figure 2 6 and table 2 2 respectively The GTD is 16 bytes long and should be aligned with a 16 byte boundary 3 22 22 2 2 1 1 0 0 1 7 6 543 0 9 8 3 0 2 2 8 1 Dword 0 CC EC T DI DP R Dword 1 Current Buffer Pointer CBP Dword 2 Next TD NextTD 0 Dword 3 Buffer End BE Notes 1 The all fields should not be modified while a TD is accessed by the HC 2 Fields are not written to nor changed the values by the HC Figure 2 6 General Transfer Descriptor Rev 1 00 10 03 page 10 of 90 RENESA
53. he transfer completed TD TD1 is written to the HeadP field of ED ED1 2 The value of the HcDoneHead register is written to the NextTD field of TD1 3 The first address of the TDI is written to the HcDoneHead register TD1 is thus linked to the Done Queue on completion of the corresponding transfer On completion of transfer for TD2 processes 1 to 3 are applied to link TD2 to the Done Queue The HC links the transfer completed TD to the Done Queue When a WriteBackDoneHead interrupt is generated the value of HcDoneHead is written to the HccaDoneHead field by the HC The HCD is able to recognize the TDs in the Done Queue by reading the HccaDoneHead field after having detected the WriteBackDoneHead interrupt Rev 1 00 10 03 page 19 of 90 RENESAS HeadP HcDoneHead 0 HccaDoneHead 0 TD1 head address NextTD TD2 head address NextTD 0 Processing for TD1 is completed HeadP HcDoneHead HccaDoneHead 0 TD2 head address DoneGusue TD1 head address NextTD 0 NextTD 0 Processing for TD2 is completed HeadP 0 HeadP HccaDoneHead 0 TD2 head address NextTD s TD1 head address NextTD 0 WriteBackDoneHead interrupt generated HccaDoneHead HcDoneHead 0 TD2 head address NextTD TD1 head address NextTD 0 Figure 2 10 Operation of The Done Queue Rev 1 00 10 03 page 20 of 90 RENESAS 2 3 7 Communication Channels There are two channels for communication between the HC and the H
54. her rights belonging to Renesas Technology Corp or a third party Renesas Technology Corp assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corp without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before maki
55. i 200020 China Tel Re 86 21 6472 1001 Fax 86 21 6415 2952 nesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 406 10 Keppel Bay Tower Singapore 098632 Te 65 6213 0200 Fax 65 6278 8001 Colophon 1 0 SH7760 Group USB Host Module Application Note 2 NE SAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJO6B0215 0100Z
56. icates the speed of the device attached to this port When set a Low Speed device is attached to this port When clear a Full Speed device is attached to this port This field is valid only when the CurrentConnectStatus is set 0 Full speed device attached 1 Low speed device attached write ClearPortPower The HCD clears the PortPowerStatus bit by writing a 1 to this bit Writing a 0 has no effect Rev 1 00 10 03 page 49 of 90 RENESAS Read Write Key Reset HCD HC Description CSC Ob RW RW ConnectStatusChange This bit is set whenever a connect or disconnect event occurs The HCD writes a 1 to clear this bit Writing a 0 has no effect If CurrentConnectStatus is cleared when a SetPortReset SetPortEnable or SetPortSuspend write occurs this bit is set to force the driver to re evaluate the connection status since these writes should not occur if the port is disconnected 0 No change in CurrentConnectStatus 1 Change in CurrentConnectStatus Note If the DeviceRemovable NDP bit is set this bit is set only after a Root Hub reset to inform the system that the device is attached PESC Ob R W R W PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared Changes from HCD writes do not set this bit The HCD writes a 1 to clear this bit Writing a 0 has no effect 0 No change in PortEnableStatus 1 Change in PortEnableStatus PSSC Ob RW R
57. is bit is written to 1 to turn off power to all ports clear PortPowerStatus In per port power mode it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set Writing a 0 has no effect OCI Ob R R W OverCurrentindicator This bit reports overcurrent conditions when the global reporting is implemented When set an overcurrent condition exists When cleared all power operations are normal If per port overcurrent protection is implemented this bit is always O DRWE 0b R W R read DeviceRemoteWakeupEnable This bit enables or disables remote wakeup This bit enables a ConnectStatusChange bit as a resume event causing a UsBSUSPEND to USBRESUNE state transition and setting the ResumeDetected interrupt 0 ConnectStatusChange is not a remote wakeup event 1 ConnectStatusChange is a remote wakeup event write SetRemoteWakeupEnable Writing a 1 sets DeviceRemoveWakeupEnable Writing a 0 has no effect LPSC Ob R W R read LocalPowerStatusChange The Root Hub does not support the local power status feature thus this bit is always read as 0 write SetGlobalPower In global power mode PowerSwitchingMode 0 this bit is written to 1 to turn on power to all ports clear PortPowerStatus In per port power mode it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set Writing a 0 has no effect Rev 1 00 10 03 page 45 of 90 REN
58. is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this docu
59. isochronous EDs and begins processing the Bulk Control lists CLE Ob RW R Rev 1 00 10 03 page 28 of 90 ControlListEnable This bit is set to enable the processing of the Control list in the next Frame If cleared by HCD processing of the Control list does not occur after the next SOF HC must check this bit whenever it determines to process the list When disabled HCD may modify the list If HcControlCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcControlCurrentED before re enabling processing of the list RENESAS Read Write Key Reset HCD HC Description BLE Ob RW R BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame If cleared by HCD processing of the Bulk list does not occur after the next SOF HC checks this bit whenever it determines to process the list If HcBulkCurrentED is pointing to an ED to be removed HCD must advance the pointer by updating HcBulkCurrentED before re enabling processing of the list HCFS 00b R W R W HostControllerFunctionalState Defines the state of the HC 00b UsBRESET 01b USBRESUME 10b UsBOPERATIONAL 11b USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later This field may be changed by HC only when in the UsBSUSPEND state HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port
60. it to the requesting driver Rev 1 00 10 03 page 78 of 90 RENESAS Table 4 7 Usbh Dr EnuDr c File in Which Stored Function Name Usbh_Dr_EnuDr c EnumeDriver Start Purpose Initialize EnumerationDr and ready to start transfer EnumeDriver Result Receive the result of transfer reguest to USBD layer and request next transfer EnumeDriver Request Transfer request to USBD layer EnumebDriver GetlnfoFrom Descriptor Selects necessary information among obtained Descriptor information EnumeDriver_GetDevice Descriptor Selects necessary information from obtained DeviceDescriptor EnumeDriver_GetConfig Descriptor Selects necessary information from obtained ConfigDescriptor EnumebDriver Getlnterface Descriptor Selects necessary information from obtained InterfaceDescriptor EnumeDriver_GetEndpoint Descriptor Selects necessary information from obtained EndpointDescriptor EnumebDriver Initialize Initialize EnumerationDriver EnumebDriver Clear Clear internal flag of EnumerationDriver EnumebDriver EnableDriver Define class of connected device and call most appropriate Driver function EnumebDriver Enable Enable EnumerationDriver EnumebDriver Disable Disable EnumerationDriver DummyDriver Start Dummy Dreiver execution function DriverCommon SetupDriver Request Gather transfer request to DriverRequest DriverCommon DobDrivr Request Sen
61. ith their parameters are listed in table 3 2 Spaces must be included between the command name and parameters and between the individual parameters and the line must end with a line feed For example to include SetConfig for execution enter SC 1 then begin a new line Table 3 3 gives some examples and descriptions Parameters should be written in the order shown in figure 3 2 The listed parameters are the same as are specified by clicking the individual buttons on the parameter input screen The order of parameters is also the same as on the parameter input screen Table3 2 Commands in the Scenario Function Button Command Parameter D decimal H hexadecimal SetAddress SA USB device address D 2 or greater SetConfig SC Configuration value D GetDesc DeviceDescriptor GDD Amount to be transferred H ConfigDescriptor GDC Interrupt INT Endpoint number D amount to be transferred H polling rate D direction of transfer D 1 OUT 2 IN data for transfer H MaxPacketSize H transfer count H Control CNT DeviceRequest H amount to be transferred H direction of transfer D 1 OUT 2 IN data for transfer H Bulk BLK Amount to be transferred H direction of transfer D 1 OUT 2 IN data for transfer H Endpoint number D MaxPacketSize H MemoryRead MR Address to be accessed H amount of data D access unit D 1 byte 2 word 3 longword Rev 1 00 10 0
62. lag which indicates that a USB host Clear the IntFlag and interrupt has been generated enable USB host interrupts WBDH WriteBackDoneHead interrupt RHSC RootHubStatusChange interrupt FNO FrameNumberOverrun interrupt Figure 5 2 Main Loop Rev 1 00 10 03 page 84 of 90 RENESAS 5 3 Root Hub Processing State The flow chart for Root Hub processing is given in figure 5 3 This state is entered when the RootHubStatusChange interrupt occurs while the program is in the connection wait state and steady state 1 e in the main loop This interrupt occurs when the state of the Root Hub has been changed Processing is carried out as shown in the following figure in response to the detection of any of three states connection of a device to the Root Hub disconnection of a device from the Root Hub or when a port of Root Hub is overcurrented LA RootHubStatusChange HCD_ControlRootHub interrupt generated Disconnected Stop HC processing of the list Inform the USBD layer of device disconnection Disconnection processing state Connected Start HC processing of the list Enable WriteBackDoneHead interrupt Inform USBD layer of device connection Y Connection processing state Overcurrent Disable overcurrent detection Port1 PowerOn Enable overcurrent detection Y To main loop Figure 5 3 Root Hub Processing Rev 1 00 10 03 page 85 of 90 RENESAS 5 4 Connection Processing State Figure 5
63. m among these rates Since the isochronous transfer ED has to be accessed at 1 ms intervals it is linked to the interrupt transfer ED which has a polling rate of 1 ms As is shown in figure 2 3 each interrupt transfer ED which is polled every 32 ms is linked to a head pointer Each of the interrupt transfer EDs with a 16 ms polling rate is obtained by linking it to two 32 ms head Rev 1 00 10 03 page 5 of 90 RENESAS pointers These EDs are thus accessed twice in every 32 ms interval i e once in every 16 ms interval The interrupt EDs with polling rates of 8 4 and 2 ms are accessed from four eight and 16 head pointers respectively The interrupt transfer ED polled every 1 ms is accessed from all of the head pointers The isochronous ED is linked with the tree after the interrupt ED that is polled every 1 ms The periodic transfer EDs are thus organized into a tree structure Interrupt endpoint descriptor placeholder Ji BA LI AE V V 3 E um Interrupt head pointers V m V m V za She L a Endpoint polling interval ms Figure2 3 Interrupt List Structure An example of a list for periodic transfer is shown in figure 2 4 This sample consists of a single interrupt transfer ED polled every 4 ms two EDs each for polling every 32 16 8 2 and 1 ms and the single isochronous ED Rev 1 00 10 03 page 6 of 90 RENESAS E ozo Interrupt endpoint descriptor N A Damn Nomno
64. m is as follows Firstly a folder named Tmp should be created below the CAHew folder for use in compiling figure 3 3 Figure 3 3 Creating a Working Folder Rev 1 00 10 03 page 56 of 90 RENESAS Next the folder in which the sample program is stored SH7760 should be copied to any drive In addition to the sample program this folder contains a batch file named BuildOfHew bat This batch file sets the path specifies compile options specifies a log file indicating the compile and linking results and performs other operations When BuildOfHew bat is executed compiling and linking are performed As a result a file named debugger ABS which is an executable file is created within the folder At the same time a map file named debugger MAP and a log file named log txt are created The map file indicates the program size and variable addresses The compile results whether there are any errors etc are recorded in the log file figure 3 4 Note If HEW is installed to a folder other than C Hew the compiler path setting and settings for environment variables used by the compiler in BuildOfHew bat as well as the library settings in InkSet1 sub must be changed Here the compiler path setting should be changed to the path of shc exe and the setting for the environment variable shc lib used by the compiler should be set to the folder of shc exe the shc inc setting should be changed to the folder of machine h and the setting of shc t
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67. mp should specify the working folder for the compiler The path of shcpic lib should be specified for the library SH7760 Batch file Execution result BuildOfHew bat op debugger ABS Execution debugger MOT debugger MAP log txt Figure 3 4 Compile Results 3 2 3 RequestGenerator Files required for the USB packet generation tool RequestGenerator are all stored in the RegGen folder ReqGen exe MSCOMM32 0CX TABCTL32 0CX mscomctl ocx comdlg32 ocx SampleScenario Control txt SampleScenario Control2 txt SampleScenario Interrupt txt SampleScenario_Bulk txt Figure 3 5 Files Included in ReqGen Folder Rev 1 00 10 03 page 57 of 90 RENESAS 3 3 Loading and Ezecuting the Program Figure 3 6 shows the memory map for the sample program SH7760CP ACOO 0000 ACOO 00FB ACOO 0100 ACOO 017B ACOO 0400 ACOO 048F ACOO 0600 ACOO 067F PResetException area 252byte PGeneralExceptions area 124byte PTLBMissException area 144byte PInterrupt area 84byte ACOO 1000 128byte ACOO 1083 PNonCash area y CC01 0000 PC D 16byt CC01 C6E3 C D areas 50916byte AC20 0000 AC20 517B R B areas 20860byte AFFO 2000 AFFO 0000 FE34 1000 FE34 10FB FE34 1100 FE34 207F FE34 2080 FE34 22BF USBD layer area 576byte Stack area 8Kbyte HCCA area 252byte HCD layer data area 3956byte FE34 22C0 FE34 24C3 FE34 24D0 FE34 28D3 EnuDr data area 516byt
68. ms communication between RequestGeneratotrDriver and RequestGenerator on the PC by controlling the UART Figure 4 4 shows the interrelations between the functions explained in table 4 2 to 4 10 The upper side functions call the lower side functions Also multiple functions may call the same function In the steady state CallResetException calls other functions and in the case of a transition to the USB communication state which occurs on an interrupt CallInterrupt which is an interrupt function calls HCD IntRoutine function In the UART interrupt IRL CallInterrupt calls AppsSerialIn Figure 4 4 shows the hierarchical relation of functions there is no order for function calling For information on the order in which functions are called refer to the flowcharts in section 6 Rev 1 00 10 03 page 81 of 90 3 NE SAS ZG ny a CallResetException Callinterrupt f j LA SsjFowerOnSeclion xum App Serialln f ny i ey E AA gt __ 4 Ses _INTSCT InitMemory f InitSystem EA LU a ee uml j USBD ReceiveUSBDRequest L L6 l USBD_FreeRequest DriverReguest gt Function Zo USBD_ReportDisConnection f o a Zo USBD_RemoveUSBDRequest j USBD RemoveDevice USBD_RemoveDevice LZ USBD_ReportConnection f Ene ll o l Zo eae USBD_GetDeviceAddress j EnumeDriver Start AAA AA AAA 74 USBD_ReceiverDriverRequest f ZANA ZG USBD_CreateRequest USBD SetupDriverRequestToUSBDRequest f HCD
69. n note describes how to use the USB host module that is incorporated in the SH7760 and explanation of sample programs The features of the USB host module incorporated in the SH7760 are listed below e Conforming to the Open Host Controller Interface OHCI 1 0 register set e Conforming to USB1 1 e Root hub function e Low speed 1 5 Mbps and full speed 12 Mbps transfer supported e Detection of overcurrent supported e On chip 8 kbyte SRAM can be used to store transfer data and descriptors Note Some register functions do not conform to the interface specifications For details see section 21 3 Register Descriptions and section 21 6 Restrictions on HcRhDescriptorA in the SH7760 Hardware Manual Figure 1 1 shows an example of a system configuration for executing a sample program Control PC Windows 98 Windows 2000 SH7760 Solution Engine Any USB function device Figure 1 1 System Configuration Example Rev 1 00 10 03 page 1 of 90 RENESAS This system is configured with the SH7760 Solution Engine made by Hitachi ULSI Systems Co Ltd hereafter referred to as the SH7760SE and a PC running on Windows 98 Windows 2000 In this system the host PC and the SH7760SE are connected through serial cable USB packets can be generated to the USB function devices connected to the SH7760SE by the USB packet generation tool RequestGenerator This system offers the following features 1 The sample program can
70. ndicates other than NotAccessed format of OffsetN PSWN is PacketStatusWord Condition Code The values that can be set in ConditionCode fields of TDs are listed in table 2 4 The ConditionCode for a General TD is set when the TD is moved to the Done Queue Condition codes appear in two places within an Isochronous TD in the ConditionCode field of Dword0 and the Offset PacketStatusWord fields After each data packet has been transferred the condition code is placed in the corresponding Offset PacketStatusWord When the TD is moved to the Done Queue condition codes are placed in the ConditionCode field of DwordO Rev 1 00 10 03 page 14 of 90 RENESAS Table 2 4 Condition Code Code Meaning Description 0000 NOERROR Data packet processing completed with no detected errors 0001 CRC Last data packet from endpoint contained a CRC error 0010 BITSTUFFING Last data packet from endpoint contained a bit stuffing violation 0011 DATATOGGLEMISMATCH Last packet from endpoint had data toggle PID that did not match the expected value 0100 STALL TD was moved to the Done Queue because the endpoint returned a STALL PID 0101 DEVICENOTRESPONDING Device did not respond to token IN or did not provide a handshake OUT 0110 PIDCHECKFAILURE DataPID IN and Handshake OUT are error PID 0111 UNEXPECTEDPID Receive PID was not valid 1000 DATAOVERRUN The amount of data packet more than MaxPacke
71. nditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics produc
72. ng a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corp or an authorized Renesas Technology Corp product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corp is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corp for further details on these materials or the products contained therein Rev 1 00 10 03 page iii of vi 13 N SAS Preface This application note describes the firmware that uses the USB Host Module in the SH7760 This is
73. ng the RequestGenerator s Start button sends the command RG which enables the USB packet function In response to this command the RequestGeneratorDriver is read and the EnumerationDriver is disabled on the SH7760SE side Thus when a USB function device is connected to the USB A connector the EnumerationDriver is not read this allows USB control by the RequestGeneratorDriver 1 e RequestGenerator After that the RequestGeneratorDriver decodes and executes requests for transfers from the RequestGenerator and returns the results to the RequestGenerator Generation of a serial in interrupt App_Serialln Serial data received Yes App ReceiveCommand App CheckReceiveCommand ReguestGenerator A activation command Disable EnumerationDriver Initialize RequestGeneratorDriver Processing command Transfer request received generation state Y To main loop Figure 5 5 Serial Receive State RequestGeneratorDriver Processing State Rev 1 00 10 03 page 87 of 90 RENESAS 5 6 Transfer Reguest Generation State The program enters this state on completion of connection processing after a device has been connected to the Root Hub and generation of the corresponding RootHubStatusChange interrupt In this state reguests for transfers are received from the Driver layer by the HCD via the USBD layer and the list in which EDs and TDs are linked is generated and sent to the HC The flow chart for transfer reguests i
74. ntains and controls the HC The HCD controls the HC by directly accessing the registers of the HC and registering the head pointers in the interrupt Endpoint Descriptor list of the HCCA The HCD thus maintains the state of the HC head pointers to each list enabling and disabling of list processing and enabling and disabling of interrupts 2 4 2 Bandwidth Allocation In the USB a frame is generated every 1 0 ms As is shown in figure 2 12 in the OpenHCL a frame is internally divided into three parts with periods for the processing of nonperiodic and periodic lists On completion of SOF packet generation nonperiodic transfers are carried out until the value of the Frame Remaining field in HcFmRemaining reaches that of the Frame Interval field in HcFmInterval Periodic transfer begins when the value in the Frame Remaining field has exceeded the value in the Interval field After all of the periodic transfers have been completed nonperiodic transfers are again carried out The HCD determines whether or not to accept requests for periodic transfer by judging whether or not there is sufficient bandwidth for the transfers 1 0ms NP Non Periodic Figure 2 12 Frame Bandwidth Allocation 2 4 3 List Management The USB data packets are generated from the TDs which are linked to the EDs The HCD creates the structures of linked EDs and TDs i e lists A new ED can easily be added to the end of a list without halting list processing by
75. ochronous TD soon starts Rev 1 00 10 03 page 16 of 90 RENESAS 2 3 4 Host Controller Communications Area HCCA The Host Controller Communications Area HCCA is used to transfer various information between the HCD and HC The format of the HCCA is shown in table 2 5 The HCCA consists of 256 bytes and should be located on a 256 byte boundary The HCD is able to get information from the HCCA through memory access alone 1 e without directly accessing the HC Table 2 5 Host Controller Communications Area Size Offset bytes Name R W Description 0 128 HccalnterruptTable R 32 pointers to Interrupt ED 0x80 2 HccaFrameNumber W Current frame number This field is updated by the HC before it begins processing EDs of each frame 0x82 2 HccaPad1 Ww When the HC updates HccaFrameNumber it sets this word to 0 0x84 4 HccaDoneHead WwW When the HC reaches the end of a frame and WriteBackDoneHead interrupt is enabled the HC writes the value of HcDoneHead in this field Once the HC writes in this field the HC never write in this field until software clears the WD bit in the HclnterruptStatus When LSb of this field is set to1 indicates that interrupts other than WriteBackDoneHead are generated when this field is written by the HC 0x88 116 reserved R W Reserved Pointers to the 32 Interrupt EDs are placed in the HccalnterruptTable As was explained in section 2 3 1 the list for periodic transfer has 32 head pointers Th
76. oggleCarry bit and then to the LSb of the DataToggle field in the next TD Toggle information is thus carried over and the DataPID is toggled when processing moves from one TD to the next For a control transfer the DataPacketPID is Data0 in the Setup stage Datal in the first packet of the Data stage and Datal in the status stage Therefore the more significant bit of DataToggle is set to 1 in the TD of each stage so that information is obtained from the less significant bit of the DataToggle field rather than from the previous TD via the ED Processing of the TD is completed in either of two ways all data between the CurrentBufferPointer and BufferEnd specifications of the TD has been transferred or a data packet from the endpoint was smaller than MaxPacketSize In the former case the TD is moved from the ED to the Done Queue In the latter case if BufferRounding is set normal transfer completion processing is performed If BufferRounding is not set a DataUnderrun error occurs and the Halt field in the ED is set Isochronous Transfer Descriptor ITD The Isochronous TD replaces the General TD in transfer to from the isochronous endpoints The format of the ITD and details of its fields are shown in figure 2 7 and table 2 3 respectively Dword 0 Dword 1 Buffer Page 0 BPO Dword 2 Next TD Dword 3 Buffer End BE Dword 4 Offset1 PSW1 Offset0 PSWO Dword 5 Offset3 PSW3 Offset2 PSW2 Dword 6 Offset5 PSW5 Offs
77. ogram are explained in this section The sample program runs on the SH7760SE and handles USB host processing in response to interrupts from the USB host module and branches from the main routine The UART ST16C2550 manufactured by EXAR Corporation on the board handles communication with the RequestGenerator which is the USB packet generation tool Of the interrupts from modules in the SH7760 the sample program uses three that concern the USB host module that is RootHubStatusChange WritebackDoneHead and FrameNumberOverflow An IRL interrupt is used for the UART Features of this sample program are as follows Control transfer can be performed Bulk transfer can be used Interrupt transfer can be performed Transfer requests can be generated by using the RequestGenerator packet generation tool on the PC which is connected to the SH7760SE with serial cable Notes Isochronous transfer is not supported The Suspend and Resume states are not supported Rev 1 00 10 03 page 69 of 90 3 NE SAS 4 1 State Transition Diagram Figure 4 1 shows a state transition diagram for this sample program In this sample program as shown in figure 4 1 there are transitions between six states e Reset State Upon power on reset and manual reset this state is entered In this reset state the SH7760 mainly performs initial settings e Connection Wait State This state is entered after initial settings have been completed in the reset state
78. ontrolHeadED HC traverses the Control list starting with the HcControlHeadED pointer Rev 1 00 10 03 page 36 of 90 RENESAS HcControlCurrentED Register The HcControlCurrentED register indicates the physical address of the current Control ED 3 0 0 0 E 413 0 po CED Figure 2 22 HcControlCurrentED Register Table 2 16 HcControlCurrentED Register Read Write Key Reset HCD HC Description CCED Oh R W R W ControlCurrentED This field indicates a pointer of the current ED This pointer is advanced to the next ED after serving the present one When it reaches the end of the Control list HC checks the ControlListFilled of in HcCommandaStatus If set it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit If not set it does nothing HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared When set HCD only reads the instantaneous value of this register HcBulkHeadED Register The HcBulkHeadED register indicates the physical address of the first ED of the Bulk list 3 0 0 0 1 413 0 AA O Figure 2 23 HcBulkHeadED Register Table 2 17 HcBulkHeadED Register Read Write Key Reset HCD HC Description BHED Oh RW R BulkHeadED HC traverses the Bulk list starting with the HcBulkHeadED pointer HcBulkCurrentED Register The HcBulkCurrentED register indicates the physical address of the current Bulk ED Rev 1 00 10 03 page 37 of 90 RENESAS 3 0 0 0 5 4 3 0
79. register defines the operating modes for the HC NO oo o0 oo reserved Figure 2 14 HcControl Register EmzEx e oz ajos EY ie Boro mro so m jee mr oleo DODO Rev 1 00 10 03 page 27 of 90 RENESAS Table 2 8 HcControl Register Read Write Key Reset HCD HC CBSR 00b RW R Description ControlBulkServiceRatio This specifies the ratio between Control ED and Bulk EDs During processing the nonperiodic lists HC processes one to four Control EDs according to the ratio specified for this field before processing a Bulk ED During processing the nonperiodic lists this process is repeated After a Control ED has been processed according to the ratio for this field HC decides whether to continue serving another Control ED or switching to Bulk EDs 1 1 2 1 3 1 PLE Ob R W R PeriodicListEnable This bitis set to enable the processing of the periodic list in the next frame If cleared by HCD processing of the periodic list does not occur after the next SOF HC must check this bit before it starts processing the list IE Ob R W R IsochronousEnable This bit is used by HCD to enable disable processing of isochronous EDs While processing the periodic list in a Frame HC checks the status of this bit when it finds an Isochronous ED F 1 If set enabled HC continues processing the EDs If cleared disabled HC halts processing of the periodic list which now contains only
80. rrupts HcelnterruptStatus Bit 7 6 5 4 3 2 1 0 ZA y RootHubStatusChange FrameNumberOverrun WriteBackDoneHead Figure 4 2 Types of Interrupts Rev 1 00 10 03 page 72 of 90 RENESAS 4 3 File Structure This sample program consists of nine source files and eleven header files The overall file structure is shown in table 4 1 The relationships among files are shown as layered configuration in figure 4 3 Table4 1 File Structure File Name StartUp c Principle Role Microcomputer initial setttings Usbh Hcd Tasks c OpenHCl specification functions Usbh Hcd Others c HCD layer common function Usbh Hcd Main c Main routine of HCD layer interrupt functions etc Usbh Usbd Common c USBD layer common function Usbh Dr EnuDr c Driver layer function for Enumeration processing Usbh Dr ReqGenDr c Driver layer function for RequestGenerator Usbh App Log c Serial output function Usbh App Link c Function for USB host module and UART conjunction processing SH7760 h SH7760 register definition st16c_uart h UART register definition Usbh_Hcd_TypeDef h HCD layer structure declaration Usbh Hcd ProType h Prototype declaration of HCD layer Usbh Hcd Defs h Various declarations of HCD layer Usbh Usbd Defs h Various declarations of USBD layer Usbh Dr EmuDrDefs h Various declarations of EnumerationDriver Usbh Dr DrList h
81. rupt level to 15 in interrupt priority setting register 08 Set port 1 power ON and enable overcurrent Enable the RootHubStatusChange and FrameNumberOverrun interrupts Figure 5 1 Processing in the Reset State Rev 1 00 10 03 page 83 of 90 RENESAS Set items such as pins and interrupt levels that are related to operation of the USB host so that the host is in a usable state before it is initialized When the USB host is initialized it enters the connection wait state 5 2 Main Loop Connection Wait and Steady States This loop is entered after initial settings have been completed in the reset state In the main loop the program waits for USB host interrupts Figure 5 2 is the flowchart of the main loop HCD IntRoutine is called in response to a USB host interrupt This function sets the flag IntFlag which indicates generation of the USB host interrupt disables the interrupt and ends immediately after that The actual processing in response to the interrupts is carried out in the main routine The main routine constantly checks for the occurrence of USB host interrupts This is done by checking whether or not IntFlag is set to 1 When IntFlag 1s set to 1 processing that corresponds to the generated interrupt is carried out and interrupts are enabled again HCD MainRoutine WBDH DoneQueue processing interrupt RHSC RootHub processing interrupt FNO interrupt FrameNumber processing IntFrag The f
82. ruptStatus Register This register provides status on various events that cause hardware interrupts When an event occurs corresponding bit is set When a bit is set if the event is enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set a hardware interrupt is generated To clear specific bits in this register write a 1 to the bit by the HCD The HCD can clear but not set any of these bits While the HC can set but not clear the bit Ss eds 211 A SSS O or EIE RIS WIS reserved HINJE F p O S O C Figure 2 16 HcInterruptStatus Register Rev 1 00 10 03 page 31 of 90 RENESAS Table 2 10 HclnterruptStatus Register Read Write Key Reset HCD HC Description SO Ob RW RW SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented WDH Ob R W R W WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead Further updates of the HccaDoneHead will not occur until this bit has been cleared HCD should only clear this bit after it has saved the content of HccaDoneHead SF Ob R W R W StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber HC also generates a SOF token at the same time RD Ob R W R W ResumeDetected This bit is set when HC de
83. s Section OVerVIe WA Es 1 Section 2 Overview of the Open Host Controller Interface OpenHCI A A KA Deae 3 2 4 OpenHCLEStandard iege eee it 3 2 2 Data Transter Types ee pem e eee o ee dede E ENDE eren exa 4 2 3 Host Controller Interf ce o d mte mete E RE Eds 4 DoS Ae eJLAISIS Gimeno rine ERR D LER OU E Ee d bea ete 4 2 3 2 Endpoint Descriptors EDS nsc eee erret inte 7 2 3 3 Transfer Descriptor TD iiis tenete ee ete pde decades 9 2 3 4 Host Controller Communications Area HCCA sese 17 2 3 List Processing n tenente E IR RA 18 2 3 6 Done Queue eher ertet le e t e eet te edges 18 2 3 Communication Channels seen een rennen 21 2 4 Responsibilities of Host Controller Drive 23 2 4 Management of Host Controller eese rennen 23 24 2 Bandwidth Allocation retenti 23 2413 Vist Management cia di ii 23 DAA Root H b ze iaa 24 2 5 Responsibilities of Host Controller essere 24 AOAC USB Staten ee ine tee ies 24 2 5 2 Frame Management es dde eed ie Pr edi legs 24 2 3 3 List Process cR edad dde et e m diia 24 2 6 Register Specifications is it 26 2 6 1 Control and Status Partition essere 27 2 6 Memory Pointer Partition eese nennen eene rennen 35 2 6 3 Frame Counter Pa eadera ibt e teat 39 2 6 4 Root HUD Partition e rete ee rti RE in 42 Section 3 Development Environment
84. s given in figure 5 6 In this sample software transfer reguests from the ReguestGenerator on the PC are received by the ReguestGeneratorDriver by the serial receive interrupt and transfer reguests for the HCD are carried In response to these transfer reguests the HCD generates and sends EDs and TDs to the HC From Serial Input decia YES Transfer request generated Corresponding ED has been generated2 Link the transfer request InsertEDForEndpoint to the DriverRequest USBDRequest OpenPipe structure variable structure Generate ED DriverRequest structure Link the generated ED to list USBD Receive DriverRequest Allocate Request Number QueueGeneralRequest to the DriverRequest structure variable Generate the TDs Convert DriverRequest structure variable to USBDRequest structure variable Link the TDs to the ED Y To main loop HC processing Figure 5 6 Transfer Request Processing Rev 1 00 10 03 page 88 of 90 RENESAS 5 7 DoneQueue Processing State The DoneOueue processing state is entered when a WriteBackDoneHead interrupt is generated while the program is in the steady state In response to transfer reguests the HC generates data packets from received EDs and TDs and carries out USB communication in the way shown in figure 5 6 When processing of a set of received TDs has been completed a WriteBackDoneHead interrupt is generated The flow chart is given in figure 5 7 WriteBackDoneHead
85. state 2 5 2 Frame Management At the beginning of the processing of each frame an SOF packet is generated and the frame counter in memory is incremented 2 5 3 List Processing The HC implements transfer defined by the EDs and TDs generated by the HCD During the periodic transfer period of each frame the HC reads one of the 32 interrupt list head pointers from the HCCA and processes the interrupt list and isochronous list A USB packet is generated from the head TD linked to each ED of the lists The lists for control and bulk transfer are processed during the nonperiodic transfer period These lists are processed in succession The timing of the changeover is set by the HCD The HC continues to process the control and bulk lists throughout the nonperiodic transfer period transferring n control packets to 1 bulk packet followed by n control packets and so on the value of n is set by the HCD A TD for which processing has been completed is moved from its ED to the Done Queue whether or not the transfer was successful A completed TD is linked to the Done Queue with the most recently completed TD at the head of the queue The HC sets the NextTD field of a transfer completed TD to the head TD of the Done Queue thus placing the most recently completed TD in Rev 1 00 10 03 page 24 of 90 RENESAS the Done Queue Information on the Done Queue is periodically sent from the HC to the HCD via the HCCA Rev 1 00 10 03 page 25 of 9
86. sts to the HC The head address of a list is transmitted or received via an internal register of the HC or the Host Controller Communications Area HCCA which is set up in the memory The HC passes each TD for which transfer has been completed to the HCD by placing it at the head address of the Done Queue in the HCCA Details of the processing of lists EDs TDs the HCCA and the interface between the HCD and HC are given below 2 3 1 Lists A maximum of 127 USB function devices can be connected in a single USB system and each USB function device has a maximum of 15 endpoints As more than one endpoint can be specified one ED is prepared to gather the information for each endpoint The OpenHCI specification provides for groups of EDs which include all EDs for a given transfer type A group thus linked is called a list Each TD has to have a target endpoint and so is placed in the queue of the ED that corresponds to this endpoint In other words one or more TDs are linked in a FIFO Rev 1 00 10 03 page 4 of 90 RENESAS gueue to each ED The EDs and TDs for each transfer type are aggregated in lists of the type shown in figure 2 2 The HCD controls the address of the head ED ofa list as a pointer to the list the head pointer of figure 2 2 Passing the head pointer of a list to the HC writing the information to a register of the HC allows the HC to access that list Head pointer eo ev eo 60 Figure 2 2 Typical List Struc
87. tSize of endpoint has been received or the amount of total receive size is more than that was expected 1001 DATAUNDERRUN The amount of data less than MaxPacketSize has been received or the amount of total transfer size is less than that was expected 1010 Reserved 1011 Reserved 1100 BUFFEROVERRUN During an IN transfer received data from endpoint faster than it could be written to system memory Only for the isochronous TD 1101 BUFFERUNDERRUN During an OUT transfer read access to the system memory can not be executed fast enough to keep up with USB transfer rate 111x NOTACCESSED This code is set by software before TD is generated and listed If the value of the ConditionCode is not changed processing have not be done by the HC When an error occurs the corresponding Condition Code is set in the ConditionCode field of the TD and the Halt bit of the ED is set Rev 1 00 10 03 page 15 of 90 RENESAS Errors are categorized into the four types shown below e Transmission Errors e Sequence Errors e System Errors e Time Errors Transmission errors are errors that occur in communicating information over the USB wires and manifest themselves as CRC errors BITSTUFFING errors DEVICENOTRESPONDING errors When this error occurs the TD is not immediately moved to the Done Queue and a transaction is retried If however this error occurs three times in a row or another error occurs after two transmission errors the TD is moved to
88. tSuspendStatus bit by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortSuspendStatus instead it sets ConnectStatusChange This informs the driver that it attempted to suspend a disconnected port Rev 1 00 10 03 page 47 of 90 RENESAS Read Write Key Reset HCD HC POCI Ob RW RW Description read PortOverCurrentindicator This bitis only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per port basis If per port overcurrent reporting is not supported this bit is set to O If cleared all power operations are normal for this port If set an overcurrent condition exists on this port This bit always reflects the overcurrent input signal 0 No overcurrent condition 1 Overcurrent condition detected write ClearSuspendStatus The HCD writes a 1 to initiate a resume Writing a 0 has no effect A resume is initiated only if PortSuspendStatus is set PRS Ob RW RW Rev 1 00 10 03 page 48 of 90 read PortResetStatus When this bitis set by a write to SetPortReset port reset signaling is asserted When reset is completed this bit is cleared when PortResetStatusChange is set This bit cannot be set if CurrentConnectStatus is cleared 0 Port reset signal is not active 1 Port reset signal is active write SetPortReset The HCD sets the port reset signaling by writing a 1
89. tects that a device on the USB bus is asserting resume signaling This bit is not set when HCD sets HC in USBResume state by modifying the HostControllerFunctionalState field in the HcControl register UE Ob R W R W UnrecoverableError This bit is set when HC detects a system error not related to USB HC should not proceed with any processing nor signaling before the system error has been corrected HCD clears this bit after HC has been reset FNO Ob R W R W FrameNumberOverflow This bit is set when the MSb of HcFmNumber bit 15 changes value from 0 to 1 or from 1 to 0 and after HccaFrameNumber has been updated RHSC Ob R W R W RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus NumberofDownstreamPort has changed OC Ob R W RW OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandaStatus This event when unmasked will always generate a System Management Interrupt SMI immediately This bit is tied to Ob when the SMI pin is not implemented Rev 1 00 10 03 page 32 of 90 RENESAS HcInterruptEnable Register Each bit in the HcInterruptEnable register corresponds to each bit in the HcInterruptStatus register The HcInterruptEnable register is used to control which events generate a hardware interrupt When a bit is set in the HcInterruptStatus register and the corresponding bit in the HcInterruptEnable register is s
90. the HC On the other hand deleting an existing ED requires a halt to list processing by the HC the ED is then deleted after which list processing is enabled again List processing is enabled and disabled by the ControlListEnable BulkListEnable PeriodicListEnable and IsochronousListEnable bits in the HcControl register List processing stops after all of these bits have been cleared to 0 and the next SOF has been transferred TDs are added and deleted in the same way as EDs Rev 1 00 10 03 page 23 of 90 RENESAS 2 4 4 Root Hub The HC includes the registers for the Root Hub The HCD needs to control both the HC and the Root Hub 2 5 Responsibilities of Host Controller 2 5 1 USB State Four USB states are defined in the OpenHCI specification Operational Reset Suspend and Resume The HC places the USB bus in the proper state Operational State SOF Tokens can be generated and processing of the respective lists proceeds Reset State This state follows a hardware reset The USB bus is in the reset state No SOF Token generation list processing or frame number incrementation is carried out Suspend State No SOF Token generation list processing or frame number incrementation is carried out The HC s remote wakeup circuit waits to be activated by the wakeup signal Resume State This state is only entered from the Suspend state Register access by the HCD or acceptance of a remote wakeup signal makes the system enter this
91. ts or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics gt O S9 CD Er Oo mD Z Oo rt 9 ENESAS SH7760 Group USB Host Module Application Note Renesas 32 bit RISC Microcomputer SuperH RISC engine Family SH7760 Series e ecw Onis Rev 1 00 2003 10 Rev 1 00 10 03 page ii of vi 13 N SAS Cautions Keep safety first in your circuit designs 1 Renesas Technology Corp puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap Notes regarding these materials 1 These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp product best suited to the customer s application they do not convey any license under any intellectual property rights or any ot
92. ture Lists for Non Periodic Transfer Figure 2 2 shows the structure of the lists for bulk transfer and control transfer which are categorized as non periodic Each list has one head pointer and these head pointers are stored in the registers of the HC HcControlHeadED and HcBulkHeadED Although bulk transfer and control transfer are non periodic i e they occur asynchronously the HC still executes these forms of transfer by reading their head pointers Lists for Periodic Transfer Interrupt transfer and isochronous transfer are categorized as periodic forms of transfer and their lists are treated as a single unit The first ED of the isochronous transfer list is linked to the last ED of the interrupt transfer list The Open HCI specification thus has three lists the non periodic control transfer and bulk transfer lists and the single periodic transfer list The periodic transfer list is as shown in figure 2 3 This list differs from those for non periodic transfer in the number of head pointers There are 32 head pointers and each is referred to at a 32 ms interval i e 32 frame interval Since the EDs for periodic transfer have to be referred to at specific intervals the list for periodic transfer is organized into the tree structure shown in figure 2 3 The OpenHCI specification provides fixed polling rates of 32 ms 16 ms 8 ms 4 ms 2 ms and 1 ms for interrupt transfer The polling rate for each interrupt transfer ED is chosen fro
93. unction Name USBD_SetupDriverRequest Purpose Make USBDRequest structure variable ToUSBDRequestndpoint from DriverRequest structure variable USBD ReceiveDriver Receive DriverRequest structure variable Request from Dr layer USBD ReceiveUSBDR Request Receive completed USBDRequest structure variable from HCD layer USBD CreateRequest Reserve USBDRequest structure variable and initialize USBD FreeRequest Initialize USBDRequest structure variable USBD_GetDeviceAddress Obtain value of usable DeviceAddress USBD_ReportConnection Called when a device is connected to RootHub and initialize USBD layer USBD_ReportDisConnection Called when a device is disconnected from RootHub and processing of disconnection is carried USBD_RemoveUSBDRequest Delete processing requested USBDRequest to HCD USBD_RemoveDevice Delete endpoint structure variable in specified DeviceAddress USBD_RemoveEndpoint Delete specified Endpoint structure variable USBD_ReadDAArray Access to array for DeviceAddress control USBD_WriteDAArray Access to array for DeviceAddress control USBD RootDeviceSpeedlnfo Obtain information of device speed connected to RootHub Usbh Usbd Common c is the function group in the USBD layer which receives transfer request from the Driver layer and transfers the request to the HCD layer Then the group receives the transfer result from the HCD layer and informs
94. upt Transfer Small amounts of data are transferred periodically The transfer interval can be optimized to suit the requirements of the device Isochronous Transfer Transfer is performed periodically with a constant data rate Control Transfer Configuration command and status information of the device is transferred nonperiodically Bulk Transfer Large amounts of data are transferred nonperiodically In the OpenHCI specification the four data transfer types are classified into two categories periodic and non periodic Interrupt and isochronous transfers are classified as periodic since they are scheduled to run at periodic intervals Control and bulk transfer are classified as non periodic since they are not scheduled to run at periodic intervals 2 3 Host Controller Interface Communication between the HCD and HC is through the transmission reception of Endpoint Descriptors EDs and Transfer Descriptors TDs An ED contains the information on an endpoint the device address speed and mazimum packet size of the device to which the corresponding endpoint belongs and the endpoint number The TD contains the information on the data packets to be transferred to an endpoint PID data toggle information address of transmitted received data in memory and status information after the transfer has been completed The HCD gathers the descriptors and places them in lists according to the transfer type then sends the head addresses of the li
95. uptDisable register is coupled with the HcInterruptEnable register Writing a 1 to a bit in the HcInterruptDisable register clears the corresponding bit in the HcInterruptEnable register Writing a 0 to a bit in the HcInterruptDisable register leaves the corresponding bit in the HcInterruptEnable register unchanged On read the current value of the HcInterruptEnable register is returned ak Sa 211 A A S U mo alejo SETTE reserved HINJE F p O Sjo C Figure 2 18 HclnterruptDisable Register Rev 1 00 10 03 page 34 of 90 RENESAS Table 2 12 HcInterruptDisable Register Read Write Key Reset HCD HC Description SO Ob RW R 0 Ignored 1 Disables interrupt generation due to Scheduling Overrun WDH Ob R W R 0 Ignored 1 Disables interrupt generation due to HcDoneHead Writeback SF Ob R W R 0 Ignored 1 Disables interrupt generation due to Start of Frame RD Ob R W R 0 Ignored 1 Disables interrupt generation due to Resume Detect UE Ob R W R 0 Ignored 1 Disables interrupt generation due to Unrecoverable Error FNO Ob R W R 0 Ignored 1 Disables interrupt generation due to Frame Number Overflow RHSC Ob R W R 0 Ignored 1 Disables interrupt generation due to Root Hub Status Change OC Ob RW R 0 Ignored 1 Disables interrupt generation due to Ownership Change MIE Ob R W R 0 Ignored 1 Disables interrupt generation due to other bits of this 2 6 2 Memory Pointer Partition register This field is set
96. vices can be placed under the control of the RequestGenerator by repeating steps 4 to 8 ME pU oe OY The functions of the RequestGenerator s buttons are explained below e Start Activate the RequestGenerator by clicking the Start button When the RequestGenerator is activated the status display against RequestGenerator changes from Disable to Enable e Finish Click the Finish button to close the RequestGenerator When the RequestGenerator is closed the status display against RequestGenerator changes from Enable to Disable Rev 1 00 10 03 page 62 of 90 RENESAS e SetAddress Click the SetAddress button to issue a SetAddress command Input a USB device address 2 or greater for allocation on the parameter input screen e SetConfig Click the SetConfig button to issue a SetConfig command Input the value for the required configuration on the parameter input screen e GetDesc Click the GetDesc button to issue a GetDescriptor command Input the descriptor type only the Device and Configuration are supported and size on the parameter input screen e Control Any control transfer can be executed by clicking the Control button Specify an 8 byte DeviceRequest value the transfer direction for the data stage and data and amount of data to be transferred in the data stage this setting is prohibited with In transfers on the parameter input screen Set the direction of data stage transfer for commands that have no DataStage
97. wer switch Set ClearGlobalPower RENESAS Read Write Key Reset HCD HC Description DT 0b R R DeviceType This bit specifies that the Root Hub is not a compound device The Root Hub is not permitted to be a compound device This field should always read write O OCPM IS R W R OverCurrentProtectionMode This bit describes how the overcurrent status for the Root Hub ports are reported At reset this fields should reflect the same mode as PowerSwitchingMode This field is valid only if the NoOverCurrentProtection field is cleared 0 Over current status is reported collectively for all downstream ports 1 Over current status is reported on a per port basis NOCP IS R W R NoOverCurrentProtection This bit describes how the overcurrent status for the Root Hub ports are reported When this bit is cleared the OverCurrentProtectionMode field specifies global or per port reporting 0 Over current status is reported collectively for all downstream ports 1 No overcurrent protection supported POTPGT IS R W R PowerOnToPowerGoodTime This byte specifies the duration HCD has to wait before accessing a powered on port of the Root Hub The unit of time is 2 ms The duration is calculated as POTPGT x 2 ms HcRhDescriptorB Register The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub 3 ili 0 1 6 5 0 5PEM RT Figure 2 32 HcRhDescriptor Register Rev 1 00 10 03 p
98. y and sent a SOF but before HC reads the first ED in that Frame After writing to HCCA HC will set the StartofFrame in HcInterruptStatus Rev 1 00 10 03 page 40 of 90 RENESAS HcPeriodicStart Register The HcPeriodicStart register determines when is the earliest time HC should start processing the periodic list 3 111 0 1 413 0 Figure 2 29 HcPeriodicStart Register Table 2 23 HcPeriodicStart Register Read Write Key Reset HCD HC Description PS Oh R W R PeriodicStart After a hardware reset this field is cleared The value is calculated roughly as 10 off from HcFminterval A typical value will be H 3E67 When HcFmRemaining reaches the value specified HC will start processing the Periodic list after having completed the current Control or Bulk transaction HcLSThreshold Register The HcLSThreshold register referred when the HC to decide whether to transfer a maximum of 8 byte LS packet before EOF 3 1 1 1 2 1 LST Figure 2 30 HcRhDescriptorA Regis Table 2 24 HcLSThreshold Regis Read Write Key Reset HCD HC Description LST 0628h RW R LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction The transaction is started only if FrameRemaining gt this field The value is calculated by HCD with the consideration of transmission and setup overhead Rev 1 00 10 03 page 41 of 90 RENESAS 2 64 Root Hub Partition HcRhDescriptorA Register The Hc

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