`FleaFPGA Uno` Starter Board - User Manual rev. 0.27
Contents
1. T Z 3 i 5 5 7 a USER GPIO SRAM UART_TX TK SYS_RESET d GPIO 11 a 8 GEO ei SRAM AD AMO 8 a JA o 1138 SRAM AL AL gt o 5 j 4 le SRAM A2 2 A2 ol JME oe TES 4 SRAM_AZ A3 al 3d 9 6 RAMA Ad 2 TU TR 6 RANAS 16 As i e S Da gt H 17 t jo SRAM_A6 A6 SRAM_D6 lt OIAOINOVOCDAIAVOVIAIVAODOXAVAOXDAX lt A lt X lt OVO DIA RY 9 18 SSG dd OZ GE ESS GO GG OO E EOS ZZ GORE EO OO OO GPIO_8 g RAM_A A7 SRAM_D 7 EE Sigrid eie giei eizi diNNOSgNNNANZS NO AMMMMMM rx 10 SRAM ABIL9 ag ee poo eho abbi bibi Gabbhoa boebabbae Re d 1 O__ RAM_AQ SA A9 4x10K SRAM A10 29 ALO R30 SRAM ATI A11 vee 4x10K RAM AT 2 A8 A12 29 M3 PR2A 4x10K RR SO Ar PR28 GPOIBR 3 GPIO_6R AMAS 381 415 PRSA R10 GLIO IR 4x10K E 39 AL PR3B GPIO_8R EAEE ZA ALS PRAC LA ves Ger GPIO_2IN Ei RANCALO 3 A19 A20 42_ SRAM_A20 d 37_HS SRAM_TSP2 d Ger x n PR7A GPIO_25N 2 2 PR7B GE S S PRIA si d PROB 3 LATTICE_MACHX02_7000 ui 1 EE U1 PR12A 1 GPIO_23 PR12B GPIO 24 WIFI GND GPIO_25 EE EE SE PRISB 8 Mde PR16A ge j emi mM m PR16B g TTT PRITA ao 99 se ZEEN LEI PR178 ya ya gle Gur 0 LuF EO 0 A RESET SYS RESET ae v GND LL Sid pp GPIO18R PRZIA Sri A V OUT R23 PR22. sl Stereo Audio out Page 6 Section 4 FleaFPGA Uno hardware overview Following table describes the function of each of the FleaFPGA Uno peripherals in further detail Please refer to the FleaFPGA Uno schematics in Appendix B for information on electrical connection details Peripheral Hardware details User Digital GPIO Normally used for providing digital signal lines to Arduino R3 compatible shields Provides up to 22 programmable user digital bidirectional lines depending on how the FPGA is configured In addition all digital only pins feature programmable pull up resistors Please read the following warning note and then proceed on to Appendix B for further details WARNING ALL GPIO on the FleaFPGA Uno is 3 3V capable only DO NOT INSTALL any Arduino compatible shields that can only drive GPIO pins at 5V levels Doing so may cause permanent damage to your FleaFPGA Uno and void your warranty Normally if an intended shield has the ability to sense the IOREF and AREF ie to detect if 3 3V I O must be used instead of 5V pins then chances are it can operate correctly with FleaFPGA Uno If you have any doubts about shield compatibility please contact us Thankyou Sigma Delta ADC inputs Normally configured for approximately 1980 counts full scale ie almost 11bits resolution 90Ksamples second for use in Arduino oriented projects AREF is to 3 3V For all non arduino applications faster sample rates at lower data r
3. File Edit View Project Design Pr BB Ra ra E bai E Save blinky vnd File List EEN 4 IS blinky Please Note Any obvious errors in the source file will be reported by Lattice Diamond in the error messaging console frames 4 amp 5 Please refer to the Lattice Diamond User Manual for a detailed explanation of the topics covered in this section Next we will compile the project and then upload the resultant bit file to FleaFPGA Uno FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 19 Section 7 Using Lattice Diamond Continued Section 7 4 Compiling a HDL project I Select the Process tab located at the bottom of source tree frame 1 Hierarchy C lscc diamond 2 2 x64 examples k ii You will then see new information appear in Frame 1 Process Tree Information Please tick the option boxes as they appear in the following figure synthesize Design zz Synplify Pro Translate Design Map Design Map Trace Veniog Simulation File VHDL Simulation File Place amp Route Design v Place amp Route Trace e VO Timing Analysis Export Files IBIS Model Verilog Simulation File VHDL Simulation File JEDEC File Bitstream File ti ti Th TA TA Please Note While Place amp Route Trace option may not be needed for this project it is critical this report be generated because it will be needed for more complex projects ili Double click on the Export Fil
4. 16MByte SPI ROM Used for storing user programs and or data Based on Winbond W25Q128FV Flash ROM Refer to the schematics on Appendix B for pin out details or the manufacturer s datasheet for detailed device info TX RX or USR 1 2 LEDs Normally function as USB UART communication activity indicators but can be re assigned for other uses as well Connected to FPGA pins 1 and 2 respectively Each LED can be turned on by driving the related FPGA I O pin high NOTE When the ESP8266 WiFi option is installed LED2 is hardwired as a module enable signal by default See Appendix B RESET USR 1 Button Normally functions as a system reset button but can be re configured for other uses as well Connected directly to FPGA pin 11 When the button is pressed a logic low signal is passed on to the FPGA Optional ESP8266 Serial to WiFi adapter on PCB underside Module TX_out RX_in reset boot_mode and module_enable signals connected to FPGA pins 109 12 142 75 and 2 respectively Please note in order to enable the WiFi module pullup resistor tied to Digital 0 PORTD_0 must be enabled and LED2 must be on Users are also encouraged to refer to the ESP8266 datasheet as well as the F32c based serial console example sketch FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 8 Section 5 Software Installation This section covers the basic steps needed to setup your Windows based PC for use with
5. As Default Close FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 24 Section 7 Using Lattice Diamond Continued x You should now see the FleaFPGA JTAG utility console appear and begin to load FleaFPGA Uno with the blinky LED example xi Once the programming cycle has completed and FleaFPGA JTAG has reported no errors you should now see a slow blinking TX LED on the FleaFPGA Uno board of around once per second If you got to this point without any problems your Lattice Diamond software is now ready to create digital designs with FleaFPGA Uno Please Note To initiate successive programming cycles to FleaFPGA Uno via Lattice Diamond simply double click on blinky xcf or myproject xcf etc in the source tree to trigger a custom firmware file upload to FleaFPGA Uno FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 25 Section 8 Where to from here Once you ve followed the previous sections of this guide i e installing software tools loading firmware via JTAG using lattice Diamond etc you may want to do more with your FleaFPGA Uno than blink an LED Exploring further HDL examples Further HDL project examples are available for FleaFPGA Uno These can be found on Nttp www fleasystems com fleaFPGA Uno html Example projects include e F32c based System on Chip https github com f32c f32c e Sweet32 based System on Chip h
6. Example VHDL projects gt Examplel Blinky LED HDL files DEZA Search HDL files Ca d I Organize New folder dE y n h Isc env Name Date modified Type Size Iscc Z blinky 15 12 2013 4 01 PM VHD File MSOCache FleaFPGA Uno top 15 12 2013 3 19 PM LPF File FleaFPGA Uno top 16 12 2013 12 51 VHD File nasm PerfLogs Program Files Program Files x86 Recovery SysGCC System Volume Information tcc temp k h k h h ProgramData a A h b h temp_sw si EN File name FleaFPGA Uno top blinky FleaFPGA Uno top v AI Files _ FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 16 Section 7 Using Lattice Diamond Continued v Next you will be asked to enter in the actual Lattice FPGA you will be using in this project As FleaFPGA uses the Lattice MachXO2 7000HC 4 FPGA part in the TQFP 144 IC package style please select the options as shown in the figure below and then click Next Device Selector Select Device Family LatticeEC d LatticeECP LatticeECP LatticeXP LatticexP2 e MachXO MachX02 re Sb 4 JU Performance grade _ l Operating conditions Commercial Part Names LEMX02 7000HC 4TG144C Select ASC Device Part Names LASC10 156481 Online Data Sheet for Device bi Device LOMXO2 2000UHC LCMX02 2000UHE LCMXO2 2000ZE LC
7. FPGA exactly how to behave when power is applied to it Examples that are provided for use on FleaFPGA Uno are written in VHDL Please Note Following is NOT a substitute for Lattice s own Diamond User Guide This guide only provides the reader with an insight into the steps involved in building a HDL project using Lattice software tools Interested readers are also encouraged to read through the Lattice Diamond User Guide as suggested in Section 8 By the end of this section you will hopefully gain some idea around how to create a new VHDL project within Lattice Diamond and then synthesizing i e compiling the project source into a suitable binary file to be loaded into the FPGA Programming the FPGA from within Lattice Diamond is also covered Section 7 1 Download example project source files I Download the blinky example project Uno_blinky zip from the FleaFPGA Uno project page of www fleasystems com Contained in the zip will be the following files FleaFPGA Uno top vhd Contains FleaFPGA Uno specific interface code FleaFPGA Uno top lpf Contains FleaFPGA Uno specific FPGA pinout info Blinky vhd Contains user level VHDL project source Attention When creating your own projects you must always include the first two files as they are needed to help tell Lattice Diamond what physical hardware is connected to the FPGA on FleaFPGA Uno Section 7 2 Create a new HDL project I Start Lattice Diamond and create
8. are created using FPGA development tools i e Lattice Diamond Please Note This document is NOT a how to guide on VHDL programming nor is it an introduction to electronics engineering It is essential that the reader already has a good understanding of basic electronics particularly of digital electronics and logic theory Many tutorials exist in print form and online for VHDL basic electrical electronic and digital logic theory Should you have any questions or feedback about this guide you may either register on our support forums http www fleasystems com forums or drop us an email from the contacts section on our site Thanks again and happy experimenting Sincerely Valentin Angelovski www fleasystems com FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 4 Section 3 FleaFPGA Uno connectivity block diagram SYSTEM CONNECTIVITY OPTIONS SPI Expansion mm se oe Shares pins Optional ESP 8266 i with PORT B e Stereo Audio out WiFi module and PORT C e Composite Video out PCB underside Mixed signal port can be configured for either e 3 3V GPIO PORT C 0 5 or e 11 bit ADC Six channels 90 000 samples second or at much higher sample rates with lower resolution Please refer to Section 4 RESET SPI ms com 3 3v GPIO PORT D 0 7 nm Tiny wee C22 JIUIAIDIIIZIU D JOU Ga AAA SAAM SAS Zega y www fleasyste EE ABR
9. be referring to the numbered frames shown above to help emphasize which frame within Lattice Diamond that we re covering FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 18 Section 7 Using Lattice Diamond Continued Section 7 3 Editing HDL source files within Lattice Diamond i From the source tree Frame 1 double click on a source file of interest i e blinky vhd You should see the source contained within that file appear in the source editor Frame 2 as shown Y blinky vhd a alx wwkwkwkwkwkwwwk Pleatiny FPGA Blinky LED example module bbk bbk db bbk zr Very simple example of how to create a custom logic module using HDL Following VHDL code describes an up counter with a count range of 25 millio Counter value is incremented by the external system clock which is 50MHz o zr LEDI on FleaFPGA will be toggled every time the counter value reaches 25 m and reset back to zero Creation Date 15th December 2013 Author Valentin Angelovski 111 library IEEE use IEEE STD LOGIC 1164 ALL use IEEE numeric std ALL entity blinky is port clk in STD LOGIC blink LED BUFFER STD LOGIC END blinky OARCHITECTURE behavior OF blinky IS OBEGIN li Once you ve modified the source file in the source editor frame Save your work as shown in the following figure Lattice Diamond Source Editor EA
10. not specifically include the following official project HDL source files FleaFPGA_Uno_Top vhd and FleaFPGA Uno Top lpf as downloaded from the www fleasystems com FleaFPGA_Uno support page It is the responsibility of the user to ensure their custom HDL applications include these two critical source files Through the purchase of FleaFPGA Uno Starter Board you agree to indemnify and hold harmless Fleasystems from any consequential damages or claims arising from or associated with use of FleaFPGA Uno Starter Board If you do not agree to any of the abovementioned terms please return your FleaFPGA Uno Starter Board within 90 days of purchase to obtain a full refund Legal Notice FleaFPGA Uno Starter board is intended to be treated as an electronic module for evaluation purposes only For commercial products intended for sale that include FleaFPGA Uno it is the responsibility of the user to ensure their final system meets overall regulatory and compliance requirements The FleaFPGA Uno is NOT to be used as a solution for applications deemed to be Safety critical or life support related The user shall assume all responsibility for any consequences arising from such use While every effort is made to ensure the information presented is accurate Fleasystems make no such guarantee Fleasystems reserve the right to update this document without prior notice FleaFPGA Uno PCB layout logo and related documentation are the copyright of V
11. option and Click Ok FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 21 Section 7 Using Lattice Diamond Continued iv Now in the source editor frame you will see some FPGA programming related information see below Please scroll across until you see a column marked Operation Double click on the cell immediately below it as shown mm et XE Start Page bd Programmer blinky xcf 1 5 dk in i EB Device Operation Cable Settings eek degi casi DetectCable Cable USB2 Port FTUSB 0 Custom Port HEX i VO Settings a Use Default 1 0 Settings a Use Custom I O Settings 2 n ININ Fin Con nected E mM a DONE F nnecte 2 Mm d TRST Fil t et TRST High tTRS AMN Fin Connect ispEN Pir nected et ispEN High Please Note Following page covers the two main programming modes for FleaFPGA Uno 1 Loading user firmware into the FPGA configuration SRAM User firmware can be updated an infinite number of times with a very quick upload time of 3 seconds However user firmware uploaded in this mode is NOT permanenily stored and will be lost upon power off 2 Loading user firmware into the FPGA configuration Flash ROM User firmware may be permanently committed to the FPGA using this mode However programming time is considerably longer i e 20 seconds to over 2 minutes depending w
12. pre built FPGA configuration files i e files specifically compiled for FleaFPGA Uno use using the VME file format or for end user FPGA development Software drivers Install Essentially this includes all the software drivers and utilities needed to allow the user to upload FPGA files i e VME bit files which must be specific to FleaFPGA Uno that may be downloaded from our fleasystems com website to be programmed into their FleaFPGA Uno platform 1 Installation of the FTDI D2XX driver as needed by the PC to recognize FleaFPGA Uno s on board JTAG interface FT230x interface chip 2 Installation of the FleaFPGA JTAG utility allowing suitable bit files to be uploaded to FleaFPGA Uno FPGA development tools Install Essentially this includes all the elements of the basic installation as well as the ability for users to create their own custom logic designs i e user custom VME bit file on FleaFPGA Uno This is accomplished by installing Lattice Diamond Development and configuring it for use with the FleaFPGA Uno platform Please Note All examples contained in this guide are screenshots from a Windows7 based installation Windows 8 installation processes should be almost identical however Before you begin You will need the following e Modern PC with windows7 Ideally 64 bit version but not essential or newer installed and also web enabled Must have at least 4GBytes RAM as well as 30GBytes of free Hard Disk space mini
13. with 8mA current source sink capability Please refer to the Lattice MachXO2 datasheet for more detailed information Maximum current draw from FleaFPGA Uno s USB host port is 150mA Maximum recommended current draw from FleaFPGA Uno s Shield header is 250mA FleaFPGA Uno s Input polyfuse rated for a maximum continuous current of 750mA Mechanical PCB Dimensions 69 x 63 5mm Overall dimensions 74 x 63 5 x 15mm Typically with WiFi option installed Four 3 1mm diameter mounting holes arranged in Arduino compatible pattern System rated for 0 50deg c temperature ambient FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 31 Appendix B FleaFPGA Uno Board Schematics
14. 1B R6 GP015 L0 of ag PR23A ya Il E d PR23B 3 n 3 A eg EEA manamana eeen PR2LA veli ESS HMMOOLHD OMMDODO ARA HIOMUNNDO PR24B LA d d MO OO MAHA GO ed HHA ed GA ei DO edi D ON ON OI AN KO KO KO OO KO Uu KI KI KO KO KI Gu GA GO GO GO GO GO ZO GO GO ZZ GO GO GO OO Ou GO ZZ GO GO GO OO GO GO GO GO GO GO ZZ GO Ou GO GO GO GO GO OO 12nF gt 0000000000000 gt 0o0000000000000 gt 00000 gt Y EO EI pese x l ON BOARD 1 0 e PS2 USB HOST O des ILD Lo PM ZO JO D1 GREEN LED Saia 12nF Ad EER CIO id 1 USER EDZ OO CLOCK Fe l lE GES Gk C46 PTC 200mA x R3 gt mM E USER EDI Li D2 GREEN LED gt SYSCLK Ouh 1uF Jh C47 St SWITCH MOMENTARY 2SMD 2 i da a 1 3 E pt 5 AZ SWITCH 1 de CRYSTALSMD_5X3 V RT R19 bu vsus USB SHIELD g c51 i gl GPIO_22R 4 GND Y ede GPIO_23R an SPIO USER ed aD i A eu d SYS_RESET y b SPI ROM SYS RESET b ERATZE Piga GATZEZ Pe i qs D C48 U2 aa POWER SUPPLY HI pm geed lecs Howpysioz 2 SPIT_MISO 2_lso siot sckt SP TIK VIDEO OUT cas c16 cis c20 c22 cae c25 c26 c27 c28 c29 c30 e 5 HDV CONN J3 i EIOZ SI S100 SPI1 MOSI OtuF 0 tuF O 1uF 0 1uF 0 1uF 0 tuF OAuF 0 1uF 0 1uF O 1uF O LuF 0 4uF EE dE T T T T dl T T ae sE ia oar esa dr TEN cs lo tur pura gt ZE ZA O 1uF IG Datel Data2_SHD Car dar sui Datat_SHD gt USB SERIAL JTAG GGE ITZ aa Data0_SHD A c17 Ira cz1 c23 c44 cas USER POWER ZO c10 TI Seta Clock SAD 42 a ede 0 1uF fica Odur l otu
15. Diamond uses the jed extension bd MachX02 LEMXO2 OOOHE Device Properties Device Operation Access Mode Flash Programming Mode Operation FLASH Program Programming Options Programming File diamond 2_x64 examples blinky blinky_blinky jed E Device Options _ Reinitialize part on program error FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 23 Section 7 Using Lattice Diamond Continued vii Save the current JTAG configuration by clicking on the related icon in the top menu as shown Lattice Diamond Programmer blini File Edit View Project Design P Mann nas mos Save bl inky xcf ES ed ale List vili Now we will go back to our Source tree Frame 1 and enable use of the FleaFPGA JTAG utility for use within Lattice Diamond With the mouse cursor over the file blinky xcf in the source tree hit right click and then select Open With from the right click menu as shown below E blinky FleaFPGA 2v4 top Ipf Ji Debug Files Ji Script Files Ji Analysis Files 4 Programming Files i I e vi Open Open With Open Containing Folder IX Select the FleaFPGA JTAG utility from the following list as shown Click Set as Default and then Click Ok Open With Choose the program you want to use to open this file BIOK Programs ea Adda he FleaFPGA JTAG Default dd Programmer Edit Remove Set
16. FleaFPGA Uno Starter Board Quick Startup Guide Revision 0 27 Preliminary jjwww erta Come rte pe 19 eu JIO O on IE ne SADE NT HU IO SPI EA AV OUT ELF me omni URD fea RX at E a Fl el Uno PCB Rev El LE E EE e E e e Tr esta 4 e esi E Ee e e ei erra i www fleasystems com Contents SECTION 1 WARRANTY AND LEGAL INFORMATION serrererre re rea resin resin ee nen ee nen AA nen ee nen ie nen ie ne nea ne nee ne Gee 3 SECHON 2 INTRODUCTION c aaa rata 4 SECTION 3 FLEAFPGA UNO CONNECTIVITY BLOCK DIAGRAM ese see se see se see see ese ee ieri nie ne nie nin iene nie ne nea ne Ge Ge ee 5 SECTION 4 FLEAFPGA UNO HARDWARE OVERVIEW e sesse sesse see ee see ee since sen sede ees dese nen ee nen ie nen Ge Ge Ge Gee 7 SECHION 5 SOFTWARE INSTALLATION 9 SECTION 6 LOADING BIT FILES INTO FLEAFPGA UNO esse ese see sesse see se see ee ren ee ee ee nen AREA nen ie nin ie AG Ge ne see ne zione 14 SECTION 7 USING LATTICE DIAMOND artze zetaz parearen eer ea akeen Eee Ea EEEa Eee 15 SECTION amp WHERE TO FROM HERE iese SE dee ke EA ee oe Ge aeta re du Ge ee ee 26 SECTION badue ALEAN 28 APPENDIX A FLEAFPGA UNO REV E1 SPECIFICATIONS icscsssscssccsssncsccoacasnansanecassanassanswansaesanonnaaaccaasecsscesassaans 31 APPENDIX B FLEAFPGA UNO BOARD SCHEMATICS es ssssse soes es sees kke skeie skede eee 32 FleaFPGA Uno Ouick St
17. I AGE 3 3v GPIO PORT B 0 5 Gerke Shield power reset and reference pins eza C29 ee O 33v GPIO PORT E 0 1 bed d EA E E aig En rd i CMI NNO Taa F NA vit wa dd OP AA t Ole dY GOAN Sar e PS 2 Keyboard port e 5V Power Digital Video Out USB 1 1 host port Up to 800x600 e Serial UART FPGA config dependent USB 24 bit color e FPGA JTAG interface under development supported FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 5 Section 3 FleaFPGA Uno connectivity block diagram Remote PC USB Host Sensor Display Communication and or Motor driver shields etc NOTE USERS MUST ENSURE THAT ANY INSTALLED USER SHIELDS ARE 3 3V VO COMPATIBLE Continued REVISION E1 PCB SYSTEM BLOCK DIAGRAM 5V POWER UART DIGITAL PORT VIDEO OUT USB Slave 24bit color JTAG PORT 512KBx8 SRAM Optional Expandable to ESP8266 2MB onboard serial WiFi 16MB SPI Flash FPGA Arduino R3 Compatible Lattice PS 2 or USB 1 1 shield header MachX02 7000 Host Interface 22 GPIO including 6 ADC inputs 4 bit video DAC 2 x user LED PWM Low pass Filters FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary VGA or TV display with DVI D or hdmi input PS 2 Keyboard Mouse or USB slave device Note USB portion is currently under development NTSC Color Display
18. MX02 4000HC LCMXO2 4000HE LCMX02 4000ZE LCMX02 000HC ICMYA2TANNUE DT 4 TT p Tn Package type TOFP144 y Numbers 0 Fir Device Information Voltage LUT Registers EBR Bits EBR Blocks Dist RAM DSP PLL DLL PCS APIO PIO Cells PIO Pins Max Programmable lOs VMON Pins IMON Pins TMON Pins Trim Mar Pins HVOUT Pins GPIO Cancel 2 54 3 3V 6864 6864 239 6K 26 24012 eS GO Sid Em Help vi You will now be asked to select a synthesis tool Select Synplify Pro and then click Next vii Diamond will now provide you with a summary of the settings you ve made for your new project Make sure the summary matches this guide and then click Finish Congratulations You have just created your first Lattice Diamond project FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 17 Section 7 Using Lattice Diamond Continued If your new project was created successfully you should now see the following source tree appear in your Lattice Diamond project Lattice Diamond Reports e File Edit View Project Design Process Tools Window Help A v BH dB aw Af OA ES EA ZG SA ZG E ZE d SZ KO E SZ BZ SA E E SZ GA GI Sz KO B d B GOZ BRE File List BK start Page 4 IE blinky blinky ia LCMX02 7000HE 4TG144C lo _ aD Strategies Design Summary ES Area 4 MA Project ES 1 0 Assistant P
19. PS 2 or firmware pending USB 1 1 Host Provides user input from keyboard or mouse devices with a PS 2 interface USB 1 1 Host firmware currently under development Maximum current drawn from this port should not exceed 150mA Data signals are connected to FPGA pins 120 and 119 FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 7 Section 4 FleaFPGA Uno hardware overview continued Peripheral Hardware details USB Slave port Enables either of the following functions to be performed 1 Programming of the on board FPGA via JTAG 2 Virtual COM port Where TX_out and RX_in pins connected to FPGA pins 141 and 140 respectively In addition to the above USB slave port also serves as the main power supply feed for FleaFPGA Uno Current consumption by FleaFPGA Uno with all peripherals connected should not exceed 750mA continuous current Attention Due to the shared nature of the USB slave design users must NOT have the COM port open while performing JTAG operations on FleaFPGA Uno Please close any open terminal programs to FleaFPGA s slave COM port before connecting to FleaFPGA Uno using the JTAG loader utility and vice versa 512KByte 10 nanosecond SRAM Organised as 512K x 8bit data width based on either ALLIANCE AS7C34096A or NETSOL S6R4008W1A SRAM Refer to the schematics on Appendix B for pin out details or the manufacturer s datasheet for detailed device info FleaFPGA
20. a new project file as shown in the figure below Wa Lattice Diamond Start Page Fite Edit View Project Design Process Tools Window Help New 14 File Ctrl N el m Een B Project Ctri Shift N G E Implementat N Close Ctrl F4 Strategy E i Close All 7 7 Project Close Project Open BE kiria il You should see a new project child window appear Click Next FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 15 Section 7 Using Lattice Diamond Continued ili Diamond will now ask for a project name Please enter the name Blinky in the text box as shown in the figure below and then click Next EE EE EE EE New Project Project Name e Enter a name for your project and specify a directory where the project dd data files will be stored Project Name blinky Location C flsco diamond 2 2_x64 examples F Browse iv Next you will be asked to add any VHDL source files to the project Please tick the copy source to implementation directory box Next Click Add source and then a file import window will appear Select All files in the file extension selection and then select all the files contained within the example blinky zip file Once all the files are selected as shown below click Open Import File E eTa ib a gO i Local Disk C gt temp
21. alentin Angelovski All trademarked product names listed herein belong to their respective trademark owners Copyright 2015 Valentin Angelovski FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 3 Section 2 Introduction Dear Experimenter Thank you for purchasing the FleaFPGA Uno Starter board As its name suggests FleaFPGA Uno is built around the relatively new and exciting world of FPGA Field Programmable Gate Array Technology Unlike traditional microprocessor or microcontroller based boards FleaFPGA Uno uses hardware oriented languages like VHDL or Verilog to describe custom digital hardware that the user may potentially wish to create inside the FPGA Through the power of FPGA a wide variety of digital circuit functions may be realized i e from Counters and simple controllers through to Microprocessors Digital radio modulators Video etc Within the physical limits of the on board FPGA FleaFPGA Uno is built around Lattice s MachXO2 7000 product Refer to the Lattice MachXO2 Datasheet for further information The aims of this startup guide are three fold 1 To provide a useful reference for the FleaFPGA Uno platform hardware Appendices A and B cover the overall specifications and circuit schematics respectively 2 Provide the steps needed to load firmware files into FleaFPGA Uno via the on board USB JTAG interface 3 Provide insight into how new firmware files
22. art Guide Date 7 11 2015 Revision 0 27 Preliminary Page 2 Section 1 Warranty and legal information Product Warranty and Liability FleaFPGA Uno Starter Board is warranted against defects in materials and workmanship for a period of 90 days from the date of purchase At its discretion Fleasystems will repair or replace a FleaFPGA Uno Starter Board where it has found defective due to quality control or manufacturing error In the case of a valid warranty claim Fleasystems will cover the repair cost of a defective FleaFPGA Uno Starter board and only pay for return shipping via standard mail In all other instances the user shall pay all shipping and repair costs This warranty does not cover product damage or destruction due to improper use i e operating FleaFPGA Uno beyond stated electrical and thermal limits or through physical abuse This includes instances where a shield board that only supports 5Volt signalling is installed into FleaFPGA Uno which only supports 3 3V logic signals and can NOT TOLERATE 5V logic levels resulting in probable permanent damage to installed shield s and FleaFPGA Uno The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies Supplier from all claims arising from the handling or use of the goods This warranty also does not cover instances where the user has JTAG programmed a firmware application into their FleaFPGA Uno Starter Board that does
23. chXO2 7000HC FPGA 512KByte 512Kx8 bit 10nsec Parallel SRAM expandable to 2MBytes on board 16MByte 128Mx1 bit SPI user Flash ROM Digital Video output interface 640x480 and 800x600 24bit color supported Combo USB type A port enabling the following options dependent on FPGA config 1 PS 2 Keyboard or Mouse port but not both 2 To be implemented USB 1 1 host port 3 5mm stereo audio via 1bit PWM NTSC composite video out via 4bit DAC Separate USB slave serial port via FTDI interface Also serves as a JTAG interface for easy programming of the FPGA 22 X 3 3V level GPIO lines via Arduino compatible shield header including six capable of Analog to Digital conversion ADC ADC resolution is 1900 counts Full scale On FleaFPGA Uno IOREF and AREF are both tied to 3 3V See Appendix B WARNING DO NOT install a user shield that requires 5V VO to operate doing so may risk damaging both FleaFPGA Uno and or the installed user shield and voiding the warranty One push button Marked as RESET on the board Two user LEDs Marked as TX and RX on the board 25MHz onboard oscillator Optional ESP8266 WiFi to serial interface module Electrical Ratings Typical current draw Depending on the uploaded FPGA user configuration as well as active peripherals if any Generally around 50mA 250mA range This estimate does not include power drawn from the USB host port or GPIO header GPIO Header pins 3 3V CMOS compatible
24. es option as highlighted in the above figure This will commence the HDL compilation process FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 20 Section 7 Using Lattice Diamond Continued iv Lattice Diamond will now compile the project Depending on the complexity of the HDL source as well as available PC resources this may take from 20 seconds or so to well over a few minutes in very complex projects If the project completed with no errors you should see the following in the process status console Frame 3 Output UFM Summary UFM Size 2046 Pages 128 2046 Bits UFM Utllization General Purpose Flash Memory Available General Purpose Flash Memory 2046 Pages Page 0 to Page 2045 Initialized UFM Pages 0 Page Done completed successfully Paadu Section 7 5 Setting up Diamond programmer for use with FleaFPGA Uno Please Note This section only needs to be completed once at project creation time i Make Sure your FleaFPGA Uno s USB slave port is connected to the PC ideally via a hub but not essential ii From the small icons list in the top menu Click on the programmer icon as shown sign Process Tools Window Help BERK SA i BG uWORSBE BEE Programmer ZE Stat Page EJ ere Blinky Design Summary ili You now see a child window titled Programmer Getting Started appear Select the Create a New Blank Project
25. esolution are possible This is due to the fact that nearly all of the FleaFPGA Uno s ADC circuits are integrated into the MachXO2 FPGA itself Each analog input in the FleaFPGA Uno can be thought of as a 1 bit ADC designed for 200 Million samples second operation This output is then accumulated and filtered to provide the desired sample rate and resolution More information on the Sigma Delta ADC method can be found in Lattice Semiconductor s Application Note RD1066 as well as on David Kessner s technical blog site Also refer to Appendix B of this document as well as the default Simple ADC vhd module as found in either the F32c or Sweet32 SoC examples to see how it is implemented WARNING I O pins operate at 3 3V levels only and are not 5V tolerant Digital Video Out Provides a 24bit color RGB digital video signal out including horizontal and vertical timing information as per digital standards like DVI D and or HDMI Supported resolutions up to and including 800x600 Stereo audio NTSC video out Left and Right audio outputs are connected to FPGA pins 97 and 96 respectively via a low pass filter Each audio channel is designed to be driven by a PWM Pulse Width Modulated waveform from within the FPGA NTSC video out is implemented using a resistive 4bit DAC that provides 0 gt 1 2V output range as required by the NTSC standard for color video generation Up to 32 colors are possible Refer to Appendix B further details Combined
26. hether a USB hub is used or not In addition programming cycles are limited to 100 000 times or so before the Flash ROM begins to wear out FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 22 Section 7 Using Lattice Diamond Continued v FPGA SRAM programming mode In the following child window please select the Correct Access Mode Operation and Programming File options as shown below Note that for SRAM programming Lattice Diamond uses the bit extension Warning Before you can successfully access the fast SRAM programming mode you MUST first program the FleaFPGA Uno with a valid bit file to Flash ROM Any attempt to program FleaFPGA Uno s configuration SRAM will simply not work otherwise If you have not yet programmed your FleaFPGA Uno s Flash ROM please skip this step and only come back when you can confirm that you have successfully load a bit file into Flash ROM De MachXO2 LCOMX02 000HE Device Properties Device Operation Access Mode Static RAM Cell Mode Operation SRAM Fast Program Programming Options Programming File diamond 2_x64 examples blinky blinky_blinky bit Lal Device Options Reinitialize part on program error vi FPGA Flash ROM programming mode In the following child window please select the Correct Access Mode Operation and Programming File options as shown below Note that for Flash ROM programming Lattice
27. ing utility In the shipping confirmation email of your FleaFPGA order you will have received the following attachment FleaFPGA JTAG Setup 7z You will see several files contained within the 7z file where one of these is named FleaFPGA Uno test vme This file is basically a pre built test firmware image to be uploaded to FleaFPGA Uno please save the file in a temporary directory i e c temp Unzip and run FleaFPGA JTAG Setup exe installation wizard Follow the installation steps as per the wizard recommended or default settings until you arrive at the following window Ge Setup FleaFPGA JTAG Utility BE Completing the FleaFPGA JTAG Utility Setup Wizard Setup has finished installing FleaFPGA JTAG Utility on your computer The application may be launched by selecting the installed icons Click Finish to exit Setup V Launch FleaFPGA JTAG Utility e EE Make sure the Launch FleaFPGA JTAG Utility option is ticked and then click finish FleaFPGA utility will now run and request the path of ddtemd exe This file can typically be found in the following path assuming you ve installed the 64 bit version of lattice Diamond here C lscc diamond 3 3_x64 bin nt64 Please Note You only need to select the relevant file and then click Open if you have Diamond installed and plan on using it to create your own custom FPGA based logic designs If you only wish to play with pre built FPGA firmware exam
28. ith or over 2 minutes without a USB hub has completed successfully you should now see TX LED blink roughly once per second on your FleaFPGA Uno board If a HDMI DVI D TV or monitor is plugged into the video output port at this point you should also see a nice color test pattern If you got this far then all JTAG support and if Section 5 2 was not skipped suitable development software for FleaFPGA should be now installed and ready for use FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 13 Section 6 Loading bit files into FleaFPGA Uno Currently two methods are available to program FleaFPGA Uno from MS Windows 1 Using the FleaFPGA JTAG utility to load suitable firmware files VME extension 2 Loading custom firmware files using Lattice Diamond which then calls our FleaFPGA JTAG utility to program the FPGA Only method 1 will be discussed in this section For users interested in custom FPGA experiments please refer to Section 7 and up Pre built vme example files can be found on the FleaFPGA projects page of our site Please Note Ensure that a suitable USB cable is plugged into your FleaFPGA Uno s slave USB port from the host PC Also recommended but not essential is that connection be made via a USB hub as it cuts the Flash ROM programming time from 2 minutes to 20 seconds or so i With FleaFPGA JTAG installed on your system firmware image may be loaded by 1 Doub
29. le clicking on a desired vme file to load from Windows Explorer 2 Starting FleaFPGA JTAG utility and then selecting a desired vme file to load Either method will work though method 1 is quicker ii FleaFPGAUTAG will now proceed to program the on board FPGA with your selected prebuilt_xyz vme bit file Program upload status screen should appear as per the following ees eg E FleaFPGA JTAG We m N leal beize Requesting file to process Searching for FleaFPGA found FT230X Basic UART IJTAG method bit bang write CBUS read RTS TDI TX TMS CTS TCK CB1 TDO Processing UME file Ci temp FleaFPGA_test ume JTAG bits clocked out in 287744 1852 time 0 26 0 bps 13325 ili Once the FPGA flash program cycle is complete and a successful status message appear in the JTAG console window you should see your FleaFPGA Uno board running the desired firmware Nothing to it really FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 14 Section 7 Using Lattice Diamond In this section you will be introduced to Lattice semiconductor s Diamond FPGA Development Environment for use with FleaFPGA Uno Diamond allows the user to configure FleaFPGA Uno with custom logic functions All FPGA based logic designs are created by using a Hardware Description Language HDL of which two VHDL and Verilog are most relevant and popular Programs written using this language tell the
30. mum and one free USB port e FleaFPGA Uno Starter board e USB Type A to Micro B Male adapter cable e USB Hub is recommended but not essential Allows for JTAG Flash ROM programming time to be reduced from 150 seconds to 20 Reason it is not essential however is that JTAG programming of FPGA configuration SRAM is extremely quick 3 seconds in either case FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 9 Section 5 Software installation Continued Section 5 1 PC Installation of the FTDI D2XX driver i Download the driver file that matches your Windows OS version from the following link Note If the link is broken please navigate from www ftdichip com to find the relevant support page http www ftdichip com Drivers D2XX htm li Once it has downloaded unzip and run the executable installer Follow the prompts as given by the installer application FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 10 Section 5 Software installation Continued Section 5 2 Installation of Lattice Diamond FPGA Development software Please Note Users who only wish to load pre built FleaFPGA Uno firmware files and not create their own custom digital logic designs may skip this process and proceed on to Section 5 5 Additional Note Following requires the user to register on the Lattice Semiconductor website in order to be able to download the Lattice Diamond tools as well a
31. ples and do NOT have Lattice Diamond installed just click Cancel FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 12 Section 5 Software installation Continued v FleaFPGA JTAG utility will then ask for a programming file VME file to be uploaded to the FleaFPGA board Please locate the previously saved FleaFPGA Uno testvme select it and then click Open Ga ww ra FleaFPGA JTAG Requesting file to process A Select FleaFPGA JTAG file for processing gt Computer gt Local Disk C temp Organize v New folder a MSOCache h nasm PerfLogs Program Files Program Files x86 ProgramData g Recovery Jj SysGCC g System Volume Information bh tec temp temp sw Im File name FleaFPGA test he FleaFPGA_Uno_test e tuzte Y vi FleaFPGA JTAG will now proceed to program the on board FPGA with the ready made FleaFPGA Uno test vme bit file Program upload screen should appear as follows g ke FleaFPGA JTAG Processing UME file C temp FleaFPGA_Uno_test ume Requesting file to process Searching for FleaFPGA found FT230X Basic UART IJTAG method bit bang write CBUS read RTS TDI TX TMS CTS TCK CB1 TDO JTAG bits clocked out in 287744 1852 time 0 26 0 bps 13325 m ME i vii Once the FleaFPGA Uno flash program cycle approximately 20 seconds w
32. r otr O4ur otur Our EE dE Y EE a z SCL SHD1 E TXD cBus3 I it E SDA SHD2 RTSH causo 45 bei GEA d vecio cpus D y CTRL_GND SHD3 RO US ono 13 5V_50mA feed 1 GND vee O Y R16 HOT_PLUG_DET Vv SYS_RESET JTAG_IDI a KO RESET di 1 EI XH ERIS 3V30UT f C27 JTAG_TDO IAZ TEK Side aanle R17 c 2015 Valentin Angelovski Ee hi ENE AE File Fleatiny color sch u Sheet Y USB MINIB 5PIN Title FleaFPGA Uno Rev E Size A3 Date 3 jul 2015 Rev E KiCad E D A eeschema 2012 01 19 BZR 3256 stable Id 1 1 T 2 3 4 5 6 7 Page 32 iminary 0 27 Prel ISION 7 11 2015 Rev Date FleaFPGA Uno Quick Start Guide
33. roject Summary Modute Name Synthesis ynplify ES Quick 4 M Process Reports Implementation Name blinky Strategy Name E Timing D Map Last process Strategyl D Place amp Route Target Device LCMXO2 TOOOBE 4 FB blinky gt Signal Pad 4TG144C a ed pata vice i aas ee nput Files E ade conditions Ma blinky FleaFPGA_2v4_top vhd work D Map Trace EE Ee Je Synthesis Constraint Files DD Place amp Route Tr Logic preference file 1 2v4 top lpf i gt ni Physical Preference blinky blinky blinky prf i 4 E A EE er versions azo za versions J Debug Files D VO SSO Analysis Script Files 2 Hierarchy Parsin A Implementation C lscc diamond 2 2 x64 examples blinky di Analysis Files Run BKM Check L Programming Files di Papa z blinky project summary Frame 2 Source Editor and reports browser File List Process Hierarchy Output Warning C 1scc diamond 2 2 x64 examples blinky FleaFPGA 2v4 top vhd 18 8 18 20 INFO all VHDL 1012 analyzing entity fleafpga 2v4 C 1scc diamond 2 2 x64 examples blinky FleaFPGA 2v4 top vhd 94 14 94 18 INFO VHDL 1010 analyzing architecture arch C lscc 18 20 INFO e iscerd Frame 3 Process status ks I I vanL 10d i Benton del console Frames 4 amp 5 Warning amp Error messaging tut AE C Iscc diamond 2 2 x64 examples blinkfuck Idf Mem Usage 124 656 K For the remainder of this section we will
34. s obtain a related freeware license keyfile LICENSE DAT file via email It is recommended that you do this before installing Lattice Diamond Attention It is strongly advised to download and install the 64 bit version of this software due to the fact that all FleaFPGA Uno example projects were built in a 64 bit operating environment hence all relevant file paths will have a x64 string added to them i Once you ve received an email from Lattice containing a freeware LICENSE DAT file You may now proceed to download the installer that matches your Windows OS version from the following link If the link is broken please navigate from www latticesemi com to find the relevant support page http www latticesemi com Products DesignSoftwareAndlP FPGAandLDS LatticeDiamond aspx ii Run the Lattice Diamond installation wizard Follow the installation steps as per the wizard recommended or default settings ili Once the installation process is complete copy the LICENSE DAT file you received from Lattice Semiconductor and save it in the following directory on your computer C lscc diamond 3 3_x64 License Your Lattice Diamond software is now installed and ready to use All that remains now is installation of the FleaFPGA JTAG programming utility FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 11 Section 5 Software installation Continued Section 5 3 Installation of the FleaFPGA JTAG programm
35. ttps github com Basman74 Sweet32 CPU e Apple 2 Home computer Nttp www cs columbia edu sedwards apple2fpga e More to follow Developing your own HDL projects from scratch For those who are interested in developing their own HDL projects using FleaFPGA Uno you will require the following minimum 1 Some background in digital electronics i e Boolean Algebra state machines understanding timing diagrams as well as a good understanding of logic elements i e gates flip flops tri state buffers etc are required 2 If you are not familiar with VHDL or Verilog then you will need to learn it Several reference guides are included for further study i http www ashenden com au vhdl book SG2E html li http www doulos com content products golden reference guides php Anchor Th 61209 3 It is essential that your custom HDL project knows what external hardware is connected to the FPGA Therefore your project must include both FleaFPGA Uno Toplevel vhd and FleaFPGA Uno Toplevel lpf files These can be found on www fleasystems com in the FleaFPGA projects page 4 Better understanding of the Lattice MachXO2 FPGA and Diamond tools including the in built HDL simulator i e where you can test out your project before programming the FPGA It is recommended the reader read the Lattice Diamond and MachXO2 User Guides available from www latticesemi com Attention Though you re free to view modify and upload these files to
36. your FleaFPGA Uno you need to make sure that you understand the underlying theory as outlined above It is recommended that interested readers download unzip and then copy each of the above examples into the following path on your local machine i e C lscc diamond 3 3_x64 examples Once you ve copied the project files start Lattice Diamond Open the desired project by selecting open gt project from the file menu from the abovementioned path Lattice project files use the ldf extension FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 26 Section 8 Where to from here Continued What if get stuck Users with any questions relating to FleaFPGA Uno may 1 Read the FAQ on the FleaFPGA Uno http www fleasystems com fleaFPGA Uno html 2 Register on our forum http www fleasystems com forums and ask a question there 3 Send an email using the address provided in the contacts section of our site FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 27 Section 9 Notes FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 28 Section 10 Notes FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 29 Section 11 Notes FleaFPGA Uno Quick Start Guide Date 7 11 2015 Revision 0 27 Preliminary Page 30 Appendix A FleaFPGA Uno Rev E1 Specifications Peripheral set Lattice Ma
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