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USPIIi-3v User`s Manual

1. Figure 5 12 Base Board P1 P2 Connector Orientation Table 5 13 Base Board P1 Connector Pinout Signal Name Pin 6 GND VME lt D05 gt VME BGIN L lt 1 gt VME lt D13 gt NC 12 GND VME DS L lt 1 gt VME BR L lt 0 gt VME SYSRESET L NC Themis Computer 5 15 USPIli 3v User s Manual Table 5 13 Base Board P1 Connector Pinout Signal Name Pin 20 GND IACK L GND 22 GND VME IACKOUT L NC VME A lt 16 gt NC 23 NC VME AM lt 04 gt GND 29 NC VME A lt 02 gt VME IRG L lt 2 gt VME A lt 09 gt NC Table 5 14 Base Board P2 Connector Pinout Signal Name Pin 3 NC SCSI TRMPWR SCSI TRMPWR A 4 GND SCSI ATN B A24 5 NC SCSI BSY B A25 6 GND SCSI ACK B A26 SCSI ACK A NC 7 NC SCSI RESET B A27 8 GND SCSI MSG B A28 9 NC SCSI SEL B A29 10 GND SCSI CD B A30 11 NC SCSI REG B A31 12 GND SCSI IO B GND 13 NC SCSI DATO B 5V 5 16 Themis Computer 5 Connector Pinouts Table 5 14 Base Board P2 Connector Pinout Signal Name Pin 559 5 EEE SOSLORT 18 GND SCSI DAT5 B D20 SCSI DAT5 A NC 19 NC SCSI DAT6 B D21 SCSI DAT6 A NC 20 GND SCSI DAT7 B D22 SCSI DAT7 A 21 NC SCSI PARO B D23 SCSI PARO A 22 GND SCSI DAT8 B GND SCSI DAT8 A 23 NC SCSI DAT9 B D24 SCSI DAT9 A 24 GND SCSI DAT10 B D25 SCSI DAT10 A 25 NC SCSI DA
2. E EE LN LET LOST MN 93 C INNEREN SCSI A ACK L SCSI A DAT lt 10 gt SCSI A DAT lt 11 gt Themis Computer 5 5 USPIli 3v User s Manual Table 5 5 Front Panel SCSI B Connector Pinout 5 6 Themis Computer me 7 GND SCSI B DAT 1 m Ls peso s w mo a m 14 GND 48 SCSI PAR lt 0 gt 16 GND 50 GND e K 22 22 GND 56 GND 27 GND SCSI B SEL L s oe 5 2 4 5 Connector Pinouts Ethernet A and Ethernet B Connector Type RJ 45 TPE Part Number STEWART 55 64885 Front View of PCB Figure 5 5 Front Panel Ethernet A and Ethernet B Connector Orientation Table 5 6 Baseboard RJ45 Ethernet A amp B Pinouts Signal Name RJ TXD CONN RJ TXD CONN BERESI LT RJ RXD CONN ER RENI RJ RXD CONN RJ 4T D4P CONN RJ 4T CONN RJ 4T D3P CONN Themis Computer 5 7 USPIli 3v User s Manual 5 3 P2 Paddle Board Themis Computer uo 14041 5 di PMC I O E gt PARALLEL O8 OTIO 5 a m lt S lt o o 3 4 a O o ol o DIMENSION 2 38 x 4 5 Figure 5 6 P2 Paddle Bo
3. 5 11 Serial Port C PS 2 Keyboard Connector 5 12 Serial Port D PS 2 Mouse Connector Pinout 5 12 P2 Paddle Board PMC Connector 5 13 Base Board P1 Connector i ai i etn va ise 5 15 Base Board P2 Conmieector 5 16 Middle Board P2 Connector 5 18 Carrier Board P1 Connector klai ia a 5 19 PMC Carrier Board I O P2 Connector Pinout essere 5 20 Base Board JTAG Connector PLHBOULE ui o itti usi oia etae i ecu ai Declan a E 5 22 Base Board ROMBO Connector Pinout sess 5 23 Themis Computer v USPIli 3v User s Manual Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 Table 6 13 Table 6 14 Table 7 1 Table 8 1 Table 9 1 Table 9 2 Table 9 3 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 11 5 Table 11 6 Table 11 7 Table 11 8 Table 11 9 Table 11 10 Table 11 11 Table 11 12 Table 11 13 Table 11 14 Table 11 15 Table 11 16 Table 11 17 vi Universe II Miscellaneous Control Register MISC CTL esses 6 4 Universe II Power Up pu Ons de Re RECS 6 5 PCI Configuration Base Address 0 Register
4. Transmit Clock B Data Terminal Ready Port B N GND Not Used EE s Bas Terie __ al Receive Data Port B Transmit Clock Port B pos P Transmit Data Port B Data Carrier Detect Port B N EC SENS e BE ESSE Clear to Send Port B Request To Send Port B Not Used Transmit Data Port B 7 Receive Data Port B N N N P P 74 oeacwerose ens Themis Computer 5 3 USPIli 3v User s Manual 5 2 2 Keyboard Mouse Connector Type Circular DIN 8 Part Number AMP 749179 1 TH102113 Front View Figure 5 3 Front Panel Keyboard Mouse Connector Orientation Table 5 3 Front Panel Keyboard Mouse Connector Pinout m 3 w s suem ee s ee 3 seme 5 2 3 SCSI A and SCSI B Connector Type Honda Dual SCSI 3 40 MB sec Connector 68 Pin 0 8 mm Pitch Part Number Honda HDRA E68WILfdT SL TH106874 Front View of PCB Figure 5 4 Front Panel SCSI A and SCSI B Connector Orientation 5 4 Themis Computer 5 Connector Pinouts Table 5 4 Front Panel SCSI A Connector Pinout SCSI DAT lt 15 gt SCSI A DAT lt 3 gt SCSI A DAT lt 4 gt SCSI A DAT lt 5 gt SCSI A DAT lt 6 gt De ee 02100280888 EN e EEE TT NE MI EEE RR HI ME oa EN KES DA
5. eh Ae Duden i 3 4 3 2 1 Processor Module amp Memory Subsystems eese 3 4 222 Subsystem ts erat 3 5 2 23 Auxiliary FUNCIONS Liu iiit Ee a 3 5 3 9 Environmental SpeciHealiOn x aa 3 6 Hardware DEO dM 4 1 4 1 Major DES T r at NT Re 4 1 4 1 1 Ultras PARC IIr CPU Module iioc ia a ten pi pedi Diese 4 1 4 1 2 SME Advanced PCI Bridge APB eese enne 4 2 4 1 3 SME Reset Interrupt and Clock 4 2 Themis Computer i USPIli 3v User s Manual 4 1 4 T ndra Unmverse od 4 1 5 SME PCI I O Controller nenn i giiia i 4 1 6 SYMDIOS IG catu iE 4 1 7 EC A ia aaa 4 1 8 National Super as a vet ae ioe 4 1 9 Seimens SAB 825923 konnte s RI REESE TR I edi rna 4 1 10 Boot FLASH PROM and Non volatile Storage SETI TOD and NA RA Nedas a a ia ucla qu tel a 4 2 Memory SUbSytem uae a ii a i i i i a caus a i k 4 2 1 Data Path and Interface to 45 4 2 2 Memory Addressing sc tese oeste nde Mee Ra 4 2 3 PMC Carrier Subsystem Beo coc OR o i 4 2 4 Creator Graphics EEB zs dete cie S Peu 4 3 Open Boot s
6. Themis Computer 8 1 8 1 8 3 8 3 9 1 9 1 9 1 9 2 9 2 9 2 iii USPIli 3v User s Manual 10 11 9 5 Reset LOS IE S ota eus S E 9 3 9 5 1 Reset Control Register RCR ias ia Ia ia aa 9 3 9 5 2 Reset Status Register RSR ios ice eee uti ede emu Aceites dns 9 3 9 6 Voltage and Temperature Monitoring and 9 4 9 7 WOLEAEOUTIdS 9 4 Temperature Sensing and Monitoring 10 1 10 1 obere E atte EET 10 1 10 1 1 Temperature Sensing and Monitoring Hardware 10 1 10 1 2 Temperature Sensing and Monitoring in the 10 1 Jumpers and Solder 11 11 1111 eeeeeeeee eene nnne nnn 11 1 LLA OVERVIEW Li iii da k i i i i a e i i A i i i ii k 11 1 11 2 WRITS CUS a i I ii ro 11 1 1121 SCSI Termination ier ii 11 3 11 22 VME SYSCLK Sources itte n de Dues e a 11 3 11 22 Elashr Write RUPEE TRE 11 3 11 2 4 Flash 1 and Flash 2 Write Enable inen oie Peces ser bem ee ed 11 4 LES Keyboard 11 4 T1260 Mouse berum qct torus en 11 4 11 2 7 Serial Port B Transceiver Modes 11 5 11 2 8 Seri
7. 2 resulted from Universe soft reset XIR resulted from Universe soft reset VME Reset resulted from Universe soft reset Themis Computer 9 FPGA The main function of the Reset Logics is to prevent the latch up situation what the system prone to owing to the closed reset loop between the CPU and the VME According to the default behavior after the boot of the USPIIj 3v the reset from the CPU PCI Reset propagates to the VME backplane and the VME reset from the backplane forces the CPU to reset The Reset Logics prevents closing the loop and the latch up 9 3 USPIli sv Software Manual 9 6 9 7 Voltage and Temperature Monitoring and Shutdown During the 5V power up the system is not protected Monitoring starts when the 5V reaches the working range From the start of the monitoring within 500 ms all voltages 5V 3 3V 2 6V must be above the minimum allowable value otherwise the monitor shuts down the 3 3V and 2 6V DC DC converters after 500 ms If the system comes up normally and later one of the 3 3V and 2 6V voltages drops below the minimum value the monitor shuts down both DC DC converters within 100 ms The monitor also shuts down the DC DC converters if the temperature around the CPU exceeds the failure level and the jumper enables the temperature shut down If a shut down happens for any reason the system remains in this state until a power cycle is executed to avoid oscillation
8. JO POUPA HALON 70501 NAI 3481998 PS AINA 94331 posn jou PINOYS PSIA 124 19521042 9U AINA 2sroAtu OL FALON P523 TINA 24 po usrug ISDA MN ap 142 243 4 T 154545 AINA 24 0 0 ISDA MN ayy ur 511005 PUL TALON jndjno 00 ZX VIN 9 4195944 euis 4 34 OLIY NLI 510 saporp 70 60 TALON 7 3 17154194 SLISNHMd B RSTL ISUSASUA 005 lt ASYHAAINI T 154 AINA 10d 0OWd auvog OL auvog TALON WAANS Be gt 5102 AHd AHd MO UAMOd gt 22A UAMOd 154 SAS o E B m e B RSTL A RST L o z lt o V TAIX AINA E 21807 ISUSASXA Ud 100 8 MIXX PSA xe _ _ SOTHdVaD TS T HVAOV AINA i SAUL 8dV Taw ga a ISA X Sopyoye a T 1544 ndO LSW 8 1049 154 SAS amp epqsu 154 LSUSASXA 1SUSASXA T HSVTA E E wasn DOA WAM Od LHSVIA wasn 71644 Md AINA CALON 154945 8 AWA 1 ii T TLSUSAS AINA 17188546 AINA D N02 MO Wd MOd NO C eg TALON ASF 3 gt MO UAMOd AC E NT gt 1 22A WA OX IS
9. 11 3 Flash 1 and Flash 2 Write Enable Jumper 11 4 Keyboard TTYC Jumper Settings ses e ecd eta ero Use aer 11 4 Mouse i 11 4 Serial Port B Transceiver Mode Jumper Settings eene 11 5 Serial Port B Loop Back Mode Jumper 11 5 ROMBO PROM Boot Source Jumper Settings sene 11 5 Temperature Shut Down Jumper quet ode opened 11 6 Temperature Fail Interrupt Jumper Settings 11 6 Temperature Warning Interrupt Jumper Settings sese 11 6 USPIE 3y Solder Beads eii dee 11 7 FPGA Bypass for SYS RST System Reset Solder Bead Settings 11 9 FPGA Bypass for PB RST Push Button POR Reset Solder Bead Settings 11 9 FPGA Bypass for X RST Push Button XIR Reset Solder Bead Settings 11 9 Themis Computer Table 11 18 Table 11 19 Table 11 20 Table 11 21 Table 11 22 Table 11 23 Table 11 24 Table 11 25 Table 11 26 Table 11 27 Table 11 28 List of Tables Reset from VME to CPU Solder Bead 2 11 10 Reset from CPU to VME Solder Bead Settings cee aaa aaa aaa aaa 11 10 Primary PCI Processor Bus Speed Solder Bead 11 10 Serial Port C Solder Bead ai ese tied a ia
10. 12 Reset Generation s anise ans Ii as a a a 7 2 1 a e a L 7 2 1 1 Push button POR 7 2122 Push b ttom XIR qeu ai 7 2 1 3 Scan Power On Rest i S 7 2 1 4 Scan A LR dE 7 202 Reset related functions in the 4 2224 2 21 7 2 2 1 Watchdog timer level 3 40422242 2 722222 Watchdog timer level 2 interrupt sees 1223 FPGA Reset Logics 7 2 2 4 Reset Turnaround 190165 ots ipta up tesi satin dra 7 2 2 5 VDD CORE Voltage Protection esses 7 2 2 6 VME Reset Resolution 1 22 22 021 Intefrupls G t tikiu si ste o ec cap i an RAUS eV b Prove i i ae ER i a 8 1 l tertupt Syste Hi oio obice dese Gears dlc ars dore daraus ce Aa 8 1 1 Interrupt DesCnptlOob sias iai ii sia nts ade i ei a Y SERE PRU 8 1 2 RIC ImpleietitatloDsc neces uir oc a i ta dts gem EE HERR ERU air ERGA e 9 1 si asas i ii ka i i i i a identi 9 2 ROMBO and Flash Selection 1 9 3 User BUD e ai i a a a a e i a a a a aa ge Maulana 9 4 Watchdog Tittietg cet si i e i i M i i 9 4 1 Watchdog Rel SET S Lasa ri a i cde
11. slots The USPIIi 3v is a SPARC V9 0 compliant computer with a VMEbus interface and an UItraSPARC IIi processor Before you begin carefully read each of the procedures in this manual and the associated CPU manual Improper handling of the equipment can cause serious damage We value our customer s comments and concerns Our Marketing department is eager to know what you think of our products A Reader Comment Card is located at the end of this manual for your use Please take the time fill it out and return it to Themis Computer Intended Audience This manual is written for system integrators and programmers The USPIIi 3v is targeted at a technically sophisticated customer who will integrate the product as part of an overall system solution This manual contains all necessary information for installation and configuration of the USPIIi 3v The OpenBoot PROM code is installed in the system flash The system must run all sun4u application binaries unmodified It must also boot a Solaris CDROM and run an unmodified sun4u kernel Additional device drivers such as a VME nexus driver are required to use all the features of the board but no part of the standard Solaris OS can be modified Themis supplied software for the USPIIi 3v is installed on top of a standard Solaris installation and will minimize the potential for any conflict with Solaris patches which may be released by SunSoft The reader should have a worki
12. The 360 MHz UItraSPARC IIi module consists of one UItraSPARC IIi CPU microprocessor one 64K x 18 cache tag SRAM four 256K x 18 cache data SRAMS and circuitry for generating the processor SRAM and UPAOAS interfaces PCI clocks are generated externally The module runs at 360 MHz internal processor frequency The clock synthesizer sets the frequency and division circuitry operates the UPA frequency at one third of the internal processor frequency The module interface uses two high speed impedance controlled connectors The E Cache also referred to as Level 2 Cache is a unified write back allocating on misses direct mapped cache The E Cache is physically indexed and physically tagged PIPT and has no virtual or context information Except for stable storage and error management the operating system requires no knowledge of the E Cache after initialization The E Cache always includes the content of the Instruction Cache I Cache and the Data Cache D Cache The E cache uses a fast Register Latch access mode In the Register Latched mode also referred to as 2 2 the E Cache Static RAMs have a cycle time equal to half of the processor cycle time Depending on the grade of UItraSPARC IIi processor ordered the SRAM cycle time will either be 1 51 nano seconds for the 330 MHz processor or 1 66 nano seconds for the 300 MHz processor In the Register Latched mode two processor clocks are used to send the address and two pr
13. The function of solder bead SB2501 is to select between normal mode or shut down mode for the Serial Port C Drivers Receivers Table 11 21 Serial Port C Solder Bead Settings Open Serial Port C Drivers Receivers Pin 1 is not used Serial Port C Drivers Receivers are in shutdown mode are in normal mode Factory Default 11 3 8 Serial Port D The function of solder bead SB2502 is to select between normal mode or shut down mode for the Serial Port D Drivers Receivers Table 11 22 Serial Port D Solder Bead Settings Positions 2 3 Closed Pin 1 is not used Serial Port D Drivers Receivers are in normal mode Serial Port D Drivers Receivers are in shutdown mode 11 3 9 Watchdog Control Mask The function of solder bead SB2902 is to enable or disable the Watchdog Control Mask Table 11 23 Watchdog Control Mask Solder Bead Settings TT TS Watchdog Control Mask enabled Watchdog Control Mask disabled 11 12 Themis Computer 11 Jumpers and Solder Beads 11 3 10 Watchdog Control Mode The function of solder bead SB2903 is to select normal mode or test mode for the Watchdog Control Mode Table 11 24 Watchdog Control Mode Solder Bead Settings _ Factory Default 11 3 11 Watchdog Control Request The function of solder bead SB0803 is to select whether the Request Feedback signal is connected or disconnected Table 11 25
14. North America South America and Pacific Rim Telephone 510 252 0870 Fax 510 490 5529 E mail support themis com WebSite http Awww themis com USPIIi 3v User s Manual September 2000 Part Number 105622 Version Revision History Version 1 0 November 1998 Version 2 0 September 1999 Version 2 1 September 2000 Table of Contents Getting Started e 1 1 1 1 How to Use This Manual vetito o ki o o ants as a Sia in K ii fn 1 1 1 2 Intended uie Debes anne 1 1 1 2 1 Product Warranty and 1 2 1 3 Unpacking 1 2 1 4 HOW to Start QUICK Atha ere thea AR cela teh GO BGs ae cud 1 3 1 5 Rel ucd Relerengeso ue tetigi utu m dus uua 1 3 Hirn 2 1 2 1 OpenBOOT PROM Configuration eese 2 1 2 2 Configuring 2 1 2 3 Installing The Paddle Board eere 2 2 2 4 Attaching the to a 2444 2 2 2 5 Attaching a Keyboard and Mouse 2 3 2 6 FT Y a S ue e ee de ANIMS 2 3 SBeCIIICal OTI ui ania ii ii a ainiai ki i ss i a i o 3 1 3 1 a DN Lu C Cae ad 3 1 3 1 1 Block VA St AI ais iii asai 3 2 3 2 System Specification coude qudd veta
15. Reset Workarounds According to Sun experience the CPU not always comes out from the reset state when the reset inputs are deactivated If it happens the CPU needs an additional reset at the input The Reset Workaround monitors the input reset to the CPU and the Read signal from the CPU If the read signal does not appear within 100 ms after the reset input has been deactivated the Workaround circuit repeats the reset to the CPU input Themis Computer 10 1 10 1 1 10 1 2 10 Temperature Sensing and Monitoring Introduction The CPU Module contains a thermistor placed on the opposite side of the PCB relative to the processor to monitor the temperature A series of measurements showed that the temperature difference between the thermistor and the processor heat sink is about 5 10 Celsius degree depending on the airflow intensity The purpose of these measurements were to find a relation between the processor heat sink ultimately the junction and the thermistor temperature The result allows only estimation as you see above Using a conservative estimation the Warning temperature is set to 70 Celsius degree and the Critical or Fail temperature is set to 75 Celsius degree Temperature Sensing and Monitoring Hardware A resistance to voltage converter amplifier generates a voltage level proportional to the temperature at the thermistor Two EEPROM based digital potentiometer are used to set the Warning and Fail levels These levels are co
16. Watchdog Control Request Solder Bead Settings EE m L Reguest Feed Back Reguest Feed Back is disconnected is connected 11 3 12 JTAG This information is provided for reference only These solder bead settings are only for Themis Engineering staff use Table 11 26 JTAG Solder Bead Settings Solder Bead Function Positions 1 2 Closed Positions 2 3 Closed Included in JTAG Chain Not Included in JTAG Chain SOTO a SB0401 Creator Graphics B0601 PCI Bridge SB0801 Cheerio A PCIO SB1001 Ethernet PHY A Dual SCSI Controller SB1501 Universe PCI VME Bridge SB1801 Cheerio B PCIO SB2001 Ethernet PHY B SB0804 PLD 0 00 o 2 No a WhentheCarrierBoardisnotconnectedthefollowingtemporaryconnectionmustbemade SB0804pin2 3 toSB0401 pin3 2 Themis Computer 11 13 USPIIi 3v User Manual 11 3 13 VDD Core Voltage The function of solder beads SB3101 and SB3102 is to select the VDD Core Voltage setting Proper selection of the VDD Core Voltage setting requires that SB3101 and SB3102 be set in conjunction with one another Table 11 27 VDD Core Voltage Solder Bead Settings 11 3 14 Carrier Board There are 19 signals on the P2 connector of the Carrier Board which can be configured to one of two sources sending Ethernet B signals or sending the PMC1 I O signal These solder points and jumpers are configured at the factory For more information please contact customer
17. or a Software Initiated Reset SIR These resets originate within the UltraSPARC IIi core and are only observed by the processor core Depending on the conditions and type of the reset the processor may propagate the reset throughout the system in the case of a POR or reset part of the system i e the processor core itself Note that unlike other UltraSPARC based systems the UltraSPARC IIi does not support a wake up reset for power management ResetGeneration The block diagram of the reset system for the Ultra IIi 3V can be seen in Figure 7 1 USPIIi 3v Reset Block Diagram on page 7 3 Themis Computer 7 1 USPIli 3v User s Manual 7 2 1 7 2 1 1 7 2 1 2 7 2 1 3 7 2 1 4 7 2 2 7 2 Resets The RIC chip detects 5 different resets POWER OK from power supply voltage monitoring system Push button POR Power On Reset Push button XIR eXternally Initiated Reset ScanPOR and ScanXIR The RIC chip combines the 5 reset conditions into 3 signals to the UltraSPARC IIi A table describing the effects of resets is provided in Table 7 1 Effects of Resets on page 7 5 Push button POR Push button POR reset is equivalent to the POWER OK except some minor effects Both reset force the CPU to generate RESET L signal which is the general reset signal used by the system components Push button XIR Push button XIR allows a user reset of the processor without resetting the entire system It is a non maskable interrupt Scan
18. the host bus being the root The device tree includes several device nodes PCI bus is a device node DMA Accesses by a master on the secondary bus to a target on the primary bus DMA is equivalent to Upstream Firmware This is software which stays with the hardware usually in a PROM or similar device Referred to as in IEEE 1275 standards In the implementation release version 3 10 x and later are supported This version comes with the motherboard The user may upgrade the OBP to a newer version if needed Hardware On the USPIIi 3v CPU module cables peripheral devices are typical examples of hardware Themis Computer A 1 USPIli 3v User s Manual may A keyword indicating flexibility of choice with no impied preference MMU Memory Management Unit NVRAMRC Acronym for Non Volatile Random Access Memory Run Command This refers to the executable OBP script that is written in the NV RAM Other text information or binary data may exist in the NVRAM but is not referred as NVRAMRC OBP Acronym for Open Boot Program This refers to a memory device which consists of executable code by the UItraSPARCIIi CPU The Code is responsible for initialization of the hardware and booting the system to bring up the Solaris operating system PCI Peripheral Component Interconnect bus A high performance 32 or 64 bit bus with multiplexed address and data lines as specified in the PCI Local Bus Specification Revisio
19. 0 00 0 0 0 0 5 508 8525222592525525 0 0 05245 0 052 525252595255 66555255 2255252525 6555524 5955070000090 6555524 625552525252504 vavo 2 555 24 325255252525 Yororvterererevere 4 85555555050525255550092 622259595252525250552524 6222595950525 4595254 852225550552 6052525 65252525252 va 5 SS SIM i ess Hale 33 Ee SOS NIAT Beet E Wi o 656 At 322202524545 III III III a a a a a a o 29191 910252525 2529292929254 22 2 E 2509090909 0007 255555555 9 Tete eto Reader Comment Card We welcome your comments and suggestions to help improve the USPIIi 3v User s Manual Please take time to let us know what you think about these manuals The information provided in the manuals was complete Agree Disagree Not Applicable The information was well documented and easy to follow Agree Disagree Not Applicable___ Theinformation waseasily accessible Agree Disagree Not Applicable___ manuals were useful Agree Disagree Not Applicable Please write down any additional comments you may have about these manuals Name Title Company Address
20. 2000 90000 25255 60600 x 000060 1 60000 gi BOTTOM VIEW Figure 11 2 USPIl 3v Baseboard with Solder Bead Locations Themis Computer 11 9 USPIIi 3v User Manual 11 3 1 11 3 2 11 3 3 11 10 FPGA Bypass for SYS RST System Reset The function of solder bead SB0102 is to select whether a System Reset to the CPU is passed through the FPGA or comes directly from the RIC For diagnostic purposes the FPGA should be bypassed Table 11 15 FPGA Bypass for SYS RST System Reset Solder Bead Settings Reserved Reset to the CPU module from the Reset to the CPU module comes RIC is passed through the FPGA directly from the RIC Factory Default FPGA Bypass for PB RST Push Button POR Reset The function of solder bead SB0103 is to select whether a Push Button POR Reset to the CPU is passed through the FPGA or comes directly from the RIC For diagnostic purposes the FPGA should be bypassed Table 11 16 FPGA Bypass for PB RST Push Button POR Reset Solder Bead Settings Positions 1 2 Closed Positions 2 3 Closed Reset to the CPU module from the Reset to the CPU module comes RIC is passed through the FPGA directly from the RIC FPGA Bypass for X RST Push Button XIR Reset Open Reserved The function of solder bead SB0104 is to select whether a Push Button XIR Reset to the CPU is passed through the FPGA or comes directly from the RIC For diagnostic purposes the FPGA should be
21. A or PMC Slot 1 P14 50 COLL A or PMC Slot 1 14 49 14 RXDO A or PMC Slot 1 P14 52 RX DV A or PMC Slot 1 P14 51 15 GND GND 16 RXD2 A or PMC Slot 1 P14 54 6 RXD1 A or PMC Slot 1 P14 53 17 TXD3 A or PMC Slot 1 P14 56 RXD3 A or PMC Slot 1 14 55 18 GND GND 19 TXD1 A or PMC Slot 1 14 58 69 TXD2 A or PMC Slot 1 P14 57 20 TXEN A or PMC Slot 1 14 60 TXDO A or PMC Slot 1 P14 59 21 GND GND 22 TX ER A or PMC Slot 1 P14 62 MDC A or PMC Slot 1 P14 61 23 PWR A or PMC Slot 1 P14 64 MDIO A or PMC Slot 1 P14 63 24 GND GND Themis Computer 5 13 USPIli 3v User s Manual 5 14 Table 5 12 P2 Paddle Board PMC I O Connector Pinout 27 GND GND 28 PMC Slot 0 P14 38 78 PMC Slot 0 P14 37 29 PMC Slot 0 P14 40 79 PMC Slot 0 P14 39 30 GND 80 GND 33 GND 8 GND 35 PMC Slot 0 P14 48 85 PMC Slot 40 P14 47 36 GND 86 GND 39 GND 8 GND 42 GND 92 GND 45 GND GND 48 GND 98 GND 49 GND 99 GND 50 GND GND Themis Computer 5 Connector Pinouts 5 4 P1 P2 Connectors 5 4 1 Base Board P1 P2 Connectors Connector Type Part Number ROBINSON NUGENT P08 100SL B TG Top View O0000000000000000000000000000000
22. Board SCSI A and SCSI B Connector Orientation 5 10 Themis Computer 5 Connector Pinouts Table 5 9 P2 Paddle Board SCSI A and SCSI B Connector Pinout 4 GND SCSI DAT15 5 GND SCSI PARH L 11 GND SCSI DAT5 12 GND SCSI DAT6 15 GND GND 16 GND GND 17 SCSI TERMPWR SCSI TERMPWR SCSI TERMPWR SCSI TERMPWR 19 FRONT SCSI L C 20 GND GND 22 GND GND 24 GND SCSI ACK L 25 GND SCSI RESET L Themis Computer 5 11 USPIli 3v User s Manual 5 3 4 Serial C and Serial D Ports Connector Type 20 Pin SUB D Connector Part Number AMP 786554 1 Figure 5 10 P2 Paddle Board Serial C and Serial D Connector Orientation Table 5 10 Serial Port C PS 2 Keyboard Connector Pinout Pin Signal Name Pin Signal Name C 5V Fused GND Signal Name DTR D D Lo EN IL 45 0 0 EON NN ET EA 5 12 Themis Computer 5 3 5 PMC I O Connector Type 100 Pin Connector Part Number AMP 749070 9 5 Connector Pinouts Table 5 12 P2 Paddle Board PMC I O Connector Pinout Pin Signal Name Signal Name 1 PMC Slot 1 P14 34 PMC Slot 1 P14 33 2 GND GND 5 GND 5 GND 8 GND GND 10 TXCLK A or PMC Slot 1 14 46 60 PMCSlot 1 P1445 11 CRS A or PMC Slot 1 P14 48 RXCLK A or PMC Slot 1 14 47 12 GND GND 13 RX ER
23. Computer 5 Connector Pinouts 5 4 3 PMC Carrier Board Connectors Connector Type Part Number FUJITSU FCN234J096 G V Top View Row A Row B Row C O0000000000000000000000000000000 1 32 Figure 5 14 Carrier Board P1 and P2 Connector Orientation Table 5 16 PMC Carrier Board P1 Connector Pinout Signal Name NC NC NC GND C Themis Computer 5 19 USPIli 3v User s Manual Table 5 16 PMC Carrier Board P1 Connector Pinout 5 20 Signal Name Pin L5 27 NC NC NC 28 NC NC NC 32 VCC VCC Table 5 17 PMC Carrier Board I O P2 Connector Pinout Signal Name Pin 2 PMC Slot 1 P14 36 GND 4 PMC Slot 1 14 40 A24 5 PMC Slot 1 P14 42 A25 6 PMC Slot 1 P14 44 A26 7 TXCLK A or PMC Slot 1 P14 46 27 8 CRS A or PMC Slot 1 P14 48 A28 RXCLK A or PMC Slot 1 P14 47 9 RX ER A or PMC Slot 1 P14 50 29 or PMC Slot 1 P14 49 10 RXDO A or PMC Slot 1 14 52 A30 RX DV A or PMC Slot 1 P14 51 11 RXD2 A or PMC Slot 1 14 54 A3
24. Slots in a single VME slot Creator Graphics FFB a Mll2and19oftheupper32bits ofthe l O from PMC 1 areaccessible only onthe P2 Paddle Board The defaultselectionis 2 Auxiliary Functions SCSI Port A Front Panel Paddle Board Single Ended Ultra Wide SCSI SCSI Port B Front Panel Paddle Board Paddle Board On Carrier Board On Base Board Table 3 4 Auxiliary Functions Specifications on page 3 5 summarizes the functional specifications of the auxiliary functions Table 3 4 Auxiliary Functions Specifications Feature Function Boot Flash User Flash NVRAM TOD Description 2 MB 2Mx8 One 29F016 Device 4 MB 2x2Mx8 Two 29F016 Devices 8 KB 8Kx8 Battery Backed M48T59 Themis Computer 3 5 USPIli 3v User s Manual Table 3 4 Auxiliary Functions Specifications System Status LEDs Ten different colored LED s Located on Front Panel User LEDs 2 Red and 2 Green LED s Located on Front Panel Reset Switches Reset Abort Momentary Push button Located on Front Panel recessed Watchdog Timers Three Level Watchdog Level One Interrupt Level Two XIR Level Three POR Reset Level Three Solder Bead disabled enabled Voltage Sensors Monitors 5 3 3V and 2 6VSupply Reset if out of range DC DC converters are shut down if out of range Temperature Sensors Two Level Level One warning Interrupt Level Two Fail Interrupt Jumper enabled disabled a FailshutsdownDC D
25. and retains your settings in NVRAM Warning Unless you are familiar with the Forth Monitor and are experienced in interacting with your system PROM restrict yourself to the most basic Forth Monitor operations That is to synching your disks ejecting floppies from the diskette drive booting your system and configuring the VME interface More advanced commands can do damage to your system s operation Installing The USPIli 3v Paddle Board The paddle board also referred to as a transition board delivered with the USPIIi 3v attaches to the rear of the P2 backplane and provides connectors for Serial Port C amp D PS 2 KB amp MS MII 1 MII 2 or PMC slot 1 SCSI A amp B Parallel port Attaching the USPIli 3v to a Network The USPIIi 3v features two RJ 45 for 10 100 Base T ethernet interface connections ethernet 1 amp 2 interface are provided on the paddle board The interface has auto detection capabilities and no configuration is necessary Themis Computer 2 5 2 6 2 Installation If only the baseboard is present there is only a single network connection Ethernet A available either through the RJ45 connector or If the I O Board is present a second ethernet Ethernet B is available Both Ethernets A and B may be active After attaching the USPIIi 3v to a network you can verify proper physical connection by executing the FORTH network selftest test net This test will indicate external loopba
26. and Clock RIC The SME Reset Interrupt and Clock SME STP2210QFP ASIC provides a variety of functions on the USPII 3v The RIC manages system resets system interrupts system scans and system clock control functions These functions are divided into independent functional blocks on the RIC Themis Computer 4 Hardware Overview The interrupt controller on the RIC accepts all interrupts from the USPIIi 3v sub systems up to 41 interrupts and delivers encoded interrupts on the six 6 interrupt lines going into the UItraSPARC II microprocessor Interrupts are accepted by the RIC in a round robin priority scheme The interrupts received by the RIC are not passed to the UItraSPARC IIi in the order they are received Instead a priority level is assigned Eight 8 interrupt levels are implemented For more information concerning the SME RIC ASIC refer to Chapter 8 Resets Tundra Universe II The Tundra Universe II Tundra CA91C142 ASIC interfaces the local 32 bit PCI bus to the VMEbus The Universe II includes a 33 MHz 32 bit PCI bus interface a fully compliant high performance 64 bit VMEbus interface as well as a broad range of VMEbus address and data transfer modes of e A32 A24 A16 master and slave transfer except for A64 and A40 e D64 D32 D16 D08 master and slave transfer except for MD32 MBLT BLT ADOH RMW LOCK and location monitors The Universe II also includes support for full VMEbus System Controller nine user
27. bypassed Table 11 17 FPGA Bypass for X RST Push Button XIR Reset Solder Bead Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved Reset to the module from the Reset to the module comes RIC is passed through the FPGA directly from the RIC Themis Computer 11 Jumpers and Solder Beads 11 3 4 Reset from VME to CPU The function of solder bead SB1601 is to select whether the reset line from the VME to the CPU is continuous or broken Table 11 18 Reset from VME to CPU Solder Bead Settings _ Reset line from VME to CPU is Reset line from VME to CPU is broken continuous Factory Default 11 3 5 Reset from CPU to VME The function of solder bead SB1602 is to select whether the reset line from the CPU to the VME is continuous or broken Table 11 19 Reset from CPU to VME Solder Bead Settings Open Closed Reset line from CPU to VME is Reset line from CPU to VME is broken continuous 11 3 6 Primary PCI Processor Bus Speed The function of solder beads SB0602 and SB0603 is to select the Primary PCI Processor Bus Speed of 66MHz or 33MHz Proper selection of the Primary PCI Processor Bus Speed reguires that SB0602 and SB0603 have identical settings Table 11 20 Primary PCI Processor Bus Speed Solder Bead Settings Reserved PPCI Bus Speed is 66MHz PPCI Bus Speed is 33MHz Themis Computer 11 11 USPIIi 3v User Manual 11 3 7 Serial Port C
28. configurations used on the USPIIi 3v Jumpers are considered user configurable and may be altered by a user on site Solder beads are considered factory settings and may not be altered by the user If solder beads require a configuration other than the default settings please contact the Customer Service department Warning Attempting to alter solder bead configurations could seriously damage the DO ALTER SOLDER BEAD CONFIGURATIONS CONTACT CUSTOMER SERVICE 11 2 Jumpers The USPII 3v has fourteen user configurable jumper settings Location of the jumpers is shown below in Figure 11 1 USPIIi 3v Baseboard with Jumper Locations These jumpers provide the following functionality Table 11 1 USPIIz3v Jumpers ermination P120 P120 d VME SYSCLK Source 1 2 Closed Flash 0 Write Enable 1 2 Closed Flash 1 and Flash 2 Write Enable 1 2 Closed Keyboard TTYC 2 3 Closed Mouse TTYD 2 3 Closed Serial Port B Transciever Mode Serial Port B Loop Back Mode ROMBO PROM Boot Source Temperature Shut Down Themis Computer 11 USPIIi 3v User Manual Table 11 1 Jumpers Temperature Fail ail Interrupt Temperature Warning Interrupt 1 2 Closed 11 2 Themis Computer 11 Jumpers and Solder Beads sm 0 REV P Jj JP2201 29595 0 000060000000000004000604000066060000 O
29. contains a completed transaction ifthere isa coupled cycle request The DMA Channel requests the VMEbus Master Interface when the DMAFIFO has 64 bytes available when reading from the VMEbus the DMAFIFO has 64 bytes in its FIFO when writing to the VMEbus the DMA block is complete Bi Directional DMA FIFO VMEbus PCI Master E PCI Bus Slave Channel Be posted writes with FIFO coupled read logic Ej ci Ne Channel Interrupts a Handler Interrupts nterrupter EU Bi Directional DMA FIFO Figure 6 1 Universe II Architectural Diagram Master zm The Universe 8 VMEbus Master Interface supports all of the addressing and data transfer modes as specified by the VME64 specification The Universe II does not support the A64 mode and modes intended to augment the applications i e A40 and MD32 The Universe II is compatible with all the VMEbus modules that conform to pre VME64 specification The Universe II as the VMEbus Master supports RMW and ADOH The Universe II accepts BERR and DTACK as cycle terminations from the VMEbus The Themis Computer 6 3 USPIli 3v User s Manual Universe II does not accept the RETRY as a termination from the VMEbus Slave DTACK indicates the successful completion of a transaction The Universe II utilizes the ADOH cycle to implement the VMEbus Lock command allowing a PCI bus master to lock the VMEbus resources 6 3 2 VMEbu
30. cycle VCT in Separately sets each region as pro gram or data Table 6 13 Control Fields for Special PCI Bus Target Image posted write PWEN in posted write enable bit Themis Computer 6 11 USPIli 3v User s Manual The special PCI target image register is described below Table 6 14 Special PCI Target Image Register Offset 188 Bits 31 EN R W Image Enable 0 Disable 1 Enable 30 PWEN R W Posted Write Enable 0 Disable 1 Enable 29 24 Reserved 23 20 VDW 3 0 RAN VMEbus Maximum Datawidth Each of the four bits specifies a data width for the corresponding 16 MB regions The lower order bits correspond to the lower order address regions 0 16 bit 1 32 bit 19 16 Reserved 15 12 PGM 3 0 RAN Program Data AM Code Each of the four bits specifies Program Data AM code for the cor responding 16 mB region The lower order bits correspond to the lower order address regions 0 Data 1 Program 11 8 SUPER 3 0 R W Supervisor User AM Code Each of the four bits specifies Supervisor User AM code for the corresponding 16 MB region Lower order bits correspond to the lower address regions 0 Non Privileged 1 Supervisor 07 02 BS 5 0 RAN Base Address Specifies a 64 MB aligned base address for this 64 MB image 01 Reserved 00 LAS R W PCI Bus Address Space 0 PCI Bus Memory Space 1 PCI Bus I O Space 6 12 Themis Computer BASE 0x400 0000 64 MB T 6 5 6 5 1 6 Universe ll BASE 0x3F
31. in Figure 11 2 USPIIi 3v Baseboard with Solder Bead Locations These solder beads provide the following functionality Table 11 14 0 Solder Beads Function Reference Reset Related Solder Beads FPGA Bypass for SYS RST System Reset SB0102 1 2 Closed FPGA Bypass for PB RST Push Button POR Reset SB0103 1 2 Closed FPGA Bypass for X RST Push Button XIR Reset SB0104 1 2 Closed Reset from VME to CPU SB1601 Closed Reset from CPU to VME SB1602 Closed Primary PCI Processor Bus Speed Solder Beads JTAG Solder Beads See Table 11 26 Power Board Solder Beads VDD Core Voltage SB3101 SB3102 Primary PCI Processor Bus Speed SB0602 SB0603 1 2 Closed Serial Port C and Serial Port D Solder Beads Watchdog Control Solder Beads Watchdog Control Mask Watchdog Control Mode 5829003 Opn Watchdog Control Request KZT Carrier Board Solder Beads See Table 11 28 Themis Computer 11 Jumpers and Solder Beads O aw ety 90 22 of 9020 os E p Ye 8 oe e gt ooooo dio 69000 82222 S o 60000 580607 00000 exo 852950 2 62 5899 E 00006 x d 60000 999 Bz 99000 00000 d 9o 2 60000 985 60000 exo pd 60000 5554 900 59690 6 9 9960 00006 ree 00000 204 coco 600000 lt 0 600000 5255 60600 20000 5 608606 e 95050 600000 00009
32. more information Registered Access at the power up Register access at the power up is used in a system where either the Universe II is independent of the local CPU or there a CPU 15 not present Since the Universe II and the UltraSPARC IIi are present on the USPIli 3v registered access at power up is not supported Universe II s hardware Power Up Options The Universe II power up options are determined right after the PWRRST based on the level of VMEbus Address VA 31 1 and VMEbus Data VD 31 27 Refer to Table F 2 for the Universe II s power up options on the USPIIi 3v The Universe II is automatically configured at power up to operate in the default configuration It should be noted that all power up options are latched only at the positive edge of PWRRST they are loaded when SYSRST PWRRST and RST are negated Table 6 2 Universe II Power Up Options LES BS VMEbus Register VRAI CTL Access Slave Image VMEbus CR CSR VCSR VA 20 Themis Computer 6 5 USPIli 3v User s Manual Table 6 2 Universe II Power Up Options VINT STAT SW INT VINT MAP1 SW INT BI Mod MISC CTL AUTO SYSCON MISC SYSCON Detect Auto ID MISC STAT DY4AUTO Disabled VD 30 MISC CTL V64AUTO Disabled VD 29 Disabled VD 28 Enabled SYSFAIL Asser VCSR_SET SYSFAIL Hon VCSR CLR SYSFAIL PCI Target 1510 EN LAS 0 VAS me fs Asserted Disabled VA 13 1510
33. package should include An assembled USPIIi 3v system consisting of Front Panel Base Board CPU Module Memory Boards OpenBoot PROM installed in the system flash P2 Paddle Board for I O Setof cables for the Front Panel Serial Ports USPII 3v User s Manual if ordered Report any discrepancies to the Themis Computer Customer Support department immediately 1 2 Themis Computer 1 Getting Started 1 4 How to Start Quickly To start quickly with the USPIIji 3v Themis Computer recommends that you read the following sections e Appendix A contains vital information on configuring the USPIIi 3v and the design and setup of VMEbus based systems Consult Chapter 11 Jumpers and Solder Beads This chapter contains a complete listing of all user configurable jumpers and the default settings Verify that the jumpers on your board are set to meet your application requirements 1 5 Related References The following is a list of related references PCI Local Bus Specification Revision 2 1 PCI Special Interest Group Portland American National Standard for VM E64 ANSI VITA 1994 IEEE Standard 1275 1994 Standard For Boot Initialization Configuration Firmware Core Practices and Requirements IEEE Standard 1275 1 1994 Standard For Boot Initialization Configuration Firmware ISA Supplement for IEEE P1754 SPARC IEEE Standard P1275 6 D4 Standard For Boot Initialization Configuration Fir
34. programmable slave images and seven interrupt lines For more information on the Universe II refer to Chapter 8 Resets and the Tundra Universe II User Manual published by Tundra Tundra Document Number 8091142 MD300 01 SME PCI I O Controller The SME PCI I O Controller SME STP2003QFP is a 5 Volt ASIC that provides a Master Slave interface bus compliant with PCI Local Bus Specification Revision 2 1 The PCI I O is connected to the SME APB via the local PCI bus MII support for 10base T 802 3 and 100base T 802 30 Ethernet is provided by PCI I O as well as an IEEE 1149 1 JTAG compliant architecture a 40 MHz SCSI clock oscillator a 10MHz real time clock and an expansion bus interface EBus2 Support for the National PC87303 Super I O the Siemens SAB82532 Dual 16C550 Synchronous Asynchronous Serial Port controllers the NVRAM Time of Day and a boot PROM control port is provided via the EBus2 The boot PROM control port interfaces directly to the FPGA Symbios SCSI Controller The Symbios SCSI Controller SYM53C876 provides two 2 UltraWide SCSI interfaces 40 MB sec In order to maximize speed it is attached directly to the SME APB through local 33 MHz PCI Bus A A maximum burst rate of up to 132 MB sec is supported FPGA The FPGA device on the USPIIi 3v is the Altera EPF8820 It resides on the Ebus of the PCI I O ASICs The FPGA implements a voltage monitor boot address decoder a three level watchdog timer the Us
35. reguired Table 7 1 Effects of Resets Effect on Memory Reset PCI Reset UliraSPARC lli Refresh Devices UPA64S CPU PCI Reset Sources POWER_OK a NC No Change b causes jumpto XIRtrap vector Note The system can behave as either Master or slave in the VME environment From a reset point of view the USPIIi 3v system can initiate a VME reset and as a slave has to accept a VME reset The default setup programmed in the FPGA for power on By this setup the system sends out a VME reset as long as the processor outputs the reset plus the time by the reset is extended in the Universe II chip The FPGA blocks the incoming reset from the VME to avoid the latch up condition On the other hand the USPIIi 3v system has to accept VME reset as a slave if it was generated by some other device on the VMEbus As a result the slave has to pull down the reset until the slave becomes ready This behavior is also default to the USPII 3v system The default behavior of the USPIIi 3v system obeys VME specification however it can result in a serious problem if more than one USPIIi 3v is connected to the same VMEbus During the power up sequence the two systems can reset each other continuously thereby blocking the boot up of the USPIIi 3v systems At the present time we have not found a solution to this problem which also satisfies the VME specification For applications which use multiple USPIIi 3v
36. the shared P2 backplane pins The default setting is the MII 2 signals Creator Graphics FFB The Fast Frame Buffer FFB is a high performance UPA based 24 bit frame buffer with an integer rendering pipeline for use in demanding graphic applications It is a UPA slave only non cached PIO graphics output device Open Boot Program The Open Boot Program OBP can be accessed through the EBus2 OBP code is contained in Flash Memory and provides the following functionality Runs start up diagnostic tests Initializes the host machine Themis Computer 4 5 USPIli 3v User s Manual Reads non volatile RAM and executes the boot sequence The Diagnostic Executive or standalone programs can also be executed Includes the abbreviated system monitor Entry into the system monitor is signified by the gt prompt If a boot attempt fails the OBP tries to start the abbreviated system monitor Supplies program code for the FORTH Toolkit the on board diagnostics contain the FORTH Toolkit and the FORTH language interpreter Entry into the FORTH Toolkit is signified by the ok prompt For more information on the OBP please refer to the OpenBoot Command Reference from Sun Microsystems 4 6 Themis Computer 5 ConnectorPinouts 5 1 Introduction This chapter details the connector pinouts for the user interfaces on the USPIIi 3v The Front Panel Paddle Board P1 P2 Connectors and On Board Baseboard connect
37. to Motherboard The memory data path contains a 144 bit data bus 128 data bit and 16 ECC bits The data bus interfaces with the Bus Exchanger Devices on the motherboard Texas Instruments 74LVT 162244 which combine the 144 bits of memory data to 72 bits for the UItraSPARC IIi s memory data bus Memory Addressing The total address limitation of the memory controller is one 1 GByte The 16 128 256MB memory is addressed using 13 bits of ROW address and 10 bits of column address The memory board uses the 4Mx16 memory devices and uses 12 bits for row addressing and 10 bits for column addressing The write and read control signals are controlled by the ROW address 13 The 512MB memory is addressed using 13 bits of ROW address and 11 bits of column address Note The 10 and 11 bit column address memory modules can not be mixed within one USPIIi 3v system The OBP probes the memory boards for column addressing and automatically sets the proper addressing mode PMC Carrier Subsystem The PMC Carrier Board subsystem supports up to three 3 standard PMC boards located in the third VME slot slots 0 and 1 have the J4 I O connectors installed and the upper 32 pins 33 64 of these connectors are routed to the P2 backplane connector and are available on the P2 Paddle Board The I O lines 46 63 of PMC slot 1 share pins on the P2 backplane connector with the MII 2 signals A set of 19 solder beads on the Carrier Board selects the source of
38. 1 RXD1 A or PMC Slot 1 P14 53 12 TXD3 A or PMC Slot 1 14 56 GND RXD3 A or PMC Slot 1 14 55 13 TXD1 A or PMC Slot 1 P14 58 5V TXD2 A or PMC Slot 1 P14 57 14 TXEN A or PMC Slot 1 P14 60 TXDO A or PMC Slot 1 P14 59 15 TX ER A or PMC Slot 1 P14 62 MII MDC A or PMC Slot 1 P14 61 16 PWR A or PMC Slot 1 P14 64 MDIO A or PMC Slot 1 P14 63 18 PMC Slot 0 P14 36 D20 Themis Computer 5 Connector Pinouts Table 5 17 PMC Carrier Board I O P2 Connector Pinout Signal Name Pin 20 PMC Slot 0 14 40 022 21 PMC Slot 0 14 42 023 22 PMC Slot 0 14 44 GND 23 PMC Slot 0 P14 46 D24 PMC Slot 0 P14 45 25 PMC Slot 0 P14 50 D26 26 PMC Slot 0 P14 52 D27 27 PMC Slot 0 P14 54 D28 28 PMC Slot 0 14 56 D29 29 PMC Slot 0 P14 58 D30 30 PMC Slot 0 14 60 D31 PMC Slot 0 P14 59 32 PMC Slot 0 P14 64 5V Themis Computer 5 21 USPIli 3v User s Manual 5 5 Base Board Connectors 5 5 1 JTAG Connector Connector Type Dual Row 0 1 Socket Part Number BERG 92084 308 1 7 Figure 5 15 Base Board JTAG Connector Orientation Table 5 18 Base Board JTAG Connector Pinout JTAG TDO JTAG TCLK JTAG RESET L si EH ERN II S DS NND pru S 5 22 Themis Computer ROMBO Connector Connector Type Two Straight Line 18 Pin Connectors Part Number BERG 92084 318 2 36 1 5 Figure 5 16 Base Board ROMBO Connector Orientat
39. A32 A24 or A16 space on the VMEbus If the Location Monitor is enabled an access to a Location Monitor would cause the PCI Master Interface to issue an interrupt The Universe II supports the VMEbus lock commands as they are described in the VME64 Specification The cycles are used to execute the lock command with a special AM code A locked resource can not be accessed by any other resource as long as the VMEbus master has the bus ownership It Target Abort or Master Abort occurs during a locked transaction on the PCI bus the Universe II will reliquaries its lock on the bus in accordance with the PCI Specification Themis Computer 6 3 1 PCI Bus 6 Universe Il Universe II as the VMEbus Master The Universe II becomes the VMEbus master when the VMEbus Master Interface is internally reguested by the Interrupt Channel the PCI Bus Target Channel or the DMA channels The Interrupt Channel always has the highest priority over the other two channels and will reguest the VMEbus Master Interface when it receives an enabled VMEbus interrupt reguest The PCI Bus Target Channel and the DMA Channel compete for the VMEbus Master Interface and are awarded it in a fair manner There are several methods available for user to configure the relative priority that the DMA channel and the PCI Bus Target Channel have over the ownership of the VMEbus Master Interface The PCI Target Channel reguests the VMEbus Master Interface when the TXFIFO
40. B3_IRQ4 SB3 SB3 IRQ2 Serial C Sun Keyboard 1 2 B3 B1 B AD13 PMC3 C B3 B1 B AD13 SB3_IRQ1 SB2 IRQ7 SB2 IRQ6 SB2 IRQ5 SB2 IRQ4 SB2 IRQ3 SB2 IRQ2 SB2_IRQ1 SB1_IRQ7 SCSI_B A_AD12 PMC3_D B3 B1 B_AD13 Ethernet_A A0 A1 P A AD13 PMC2 B B2 B3 B AD15 PMC2 C B2 B3 B AD15 PMC2 D B2 B3 B AD15 29 24 Di E Themis Computer 8 1 USPIli 3v User s Manual 8 2 Table 8 1 Interrupt inputs to RIC RIC PCI ID RIC pin name Pin Source at Ultra Sabre Panther PCI slot Select warns T SB1_IRQ4 PMC1_B B1 B2 B AD14 ewe 5 0 IRQ6 PMCO A BO A3 AD16 SBO IRG5 SBO 4 PMCO B AD16 PMCO C AD16 SBO mum E 14 s 5 4 48 eoon PARALLEL INT Temperature Warning Power Fail POWER FAIL INT SKEY INT L a Sabre refersto Sabre PRM Additionstothe US II SUN Microelectronics Rev 1 1 8Jan 1997 as sourceforPClslotdefinition SMOU INT L Panther referstotheSunPantherschematicassourceforPCIslotdefinition b Theslot pairclosedinto meansthatthesourceisactuallyisnota slot typedevicebutusesoneinterruptinputfromth atparticular group c IntheSunPantherdesignA AD15isusedforlIDselect USPIIj 3vusesonlyB AD signalsonthe PMCcarrierboard Themis Computer 8 Interrupts Interrupt Description The interrupt controller is the RIC ASIC The RI
41. BD PCI Bus Size MISC STAT LCLSIZE PCI CSR Image PCI CSR BM Space PCI Register PCI BSO SPACE Access PCI BS1 PCI Bus Size MISC STAT LCLSIZE PCI CSR Image PCI CSR BM Size 0 VA 5 2 32 bit REQ64 Disabled VA 14 Refer to table F 3 VA 1 and table F 4 HES disabled VA 14 TheLASfieldwillenablethe PCI CSRregistersIOSorMSfieldifthe ENFIELDoftheLSIO CTLregisterisset b AsperPCI2 1Specification the PCIBusSizeisloadedonany RST event c FollowingthePCl2 1Specification the PCIBusSizeisloadedonany RST event The PCI Configuration Base Address 0 and Base Address 1 Registers offsets are 0x010 and 0x014 respectively The registers specify the 4KB aligned base address of the 4 KB Universe II register space on PCI The power up options determine if the registers are mapped into Memory or I O space Table 6 3 PCI Configuration Base Address 0 Register PCI BSO Blts Description Reset State 31 12 BS Base Address 00 SPACE PCI Bus Address Space 0 Memory 1 I O Power up Options 6 6 Themis Computer 6 4 6 4 1 6 4 1 1 6 Universe Il a AllotherbitsareReadO Table 6 4 PCI Configuration Base Address 1 Register PCI BS1 Blts Description Reset State 31 12 BS Base Address Address Base Address sR 00 PCI Bus Address Space 0 Memory 1 I O Power up Options a AllotherbitsareReadO Slave Image Programming The Universe II recognizes two types of acce
42. C accepts all interrupts from the It delivers encoded interrupts on the six 6 interrupt lines INT NUM lt 5 0 gt presented to the UItraSPARC IIi microprocessor The interrupts are sampled on the rising edge of the PCI CLK The Mondo Interface which is integrated in the UItraSPARC IIi CPU implements 8 interrupt priority levels The Mondo Interface does not pass interrupts to the CPU core in the same order as received The interrupt priorities assigned to at the Mondo Interface are described in the Interrupt Mapping Section For more information on the priority scheme of the Mondo Interface see Chapter 8 of the Sabre PRM All interrupts except X RESET L input are maskable X RESET L resets only the CPU core and does not effect the rest of the system RIC Implementation The RIC component a round robin priority binary encoder accepts up to 41 interrupts and delivers encoded interrupts to the 6 interrupt lines of the UItraSPARC IIi CPU Themis Computer 8 3 USPIli 3v User s Manual 8 4 Themis Computer 9 1 9 2 FPGA Introduction The FPGA device on the USPIIi 3v is the Altera EP8820ATC144 4 and resides on the Ebus2 of the PCI I O ASIC Cheerio B The FPGA implements a voltage and temperature monitor controller boot address decoder three level watchdog timer user LEDs control register reset logics Ebus2 interface internal clock generators internal and CPU reset workaround logics At boot up the FPGA se
43. Cconvertersifjumpersareenabled 3 3 EnvironmentalSpecification When measuring the operating environment air temperature for the USPIIi 3v measure the air temperature as close to the air intake port on the enclosure as possible Although the thermal characteristics of the USPIIi 3v are quite good the maximum air flow should be across the USPIIi 3v board processor section Table 3 5 3 Operating Environmental Specifications Humidity Range relative 596 95 non condensing at 104 F 40 Altitude Range 9 843 feet 3 000meters Air Flow 300 Ifm airflow at 50 C Table 3 6 USPIli 3v Non operating Environmental Specifications Humidity Range relative non con 596 95 densing at 104 F 40 Altitude Range 0 feet 0 meters 38 370 feet 12000 meters 3 6 Themis Computer 4 1 4 Hardware Overview Major Components UltraSPARC Ili CPU Module The UItraSPARC IIi CPU Modules SME5421MCZ 300 333 360 consist of the following components UItraSPARC IliProcessor 2MB E cache 333MHJz and 360M Hz 5MB E cache 300MHz Clock generator External PCI JTAG temperature sense interface connector External Memory UPA64S connector The UItraSPARC IIi CPU Modules are high performance SPARC V9 compliant small form factor processor modules based on the UItraSPARC IIi single chip solution They interface to the UltraSPARC Port Architecture UPA64S interconnect bus main memory and the prima
44. DO000000000000000000000000000000 00000 O06000060000600000C060000606004006000 N0O0060060000000000000060600000660000G6 090000000000000000009000000000000 099000000000000000000900900000000 09600000000000600000000000000 o o o o o JP1202 Ll o o00000000000000000000000000000 11 3 Themis Computer BOTTOM VIEW USPIli 3v Baseboard with Jumper Locations Figure 11 1 USPIIi 3v User Manual 11 2 1 11 2 2 11 2 3 11 4 SCSI Termination SCSI termination is controlled by jumpers JP1202 SCSI Channel A and JP1203 SCSI Channel B as described below The settings for jumpers JP1202 and JP1203 are identical Table 11 2 SCSI Termination Jumper Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved On board SCSI termination Autosensing logic automatically is disabled disables on board SCSI termination when a SCSI device is attached via the front panel con nectors or the P2 Paddle Board VME SYSCLK Source The current VME PCI bridge does not deliver SYSCLK during reset The function of jumper JP1701 is to provide a continuous VME SYSCLK source from the clock divider Table 11 3 VME SYSCLK Source Jumper Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved Clock signal comes from clock Clock signal comes from the Uni divider 16MHz for the SYSCLK verse Il Not valid
45. F FFFF 16 MB BASE 0x300 0000 BASE 0x2FF 0000 BASE 0x200 0000 BASE 0x1FF 0000 BASE 0x 100 0000 BASE 0x0FF 0000 BASE 0x000 0000 Figure 6 4 Memory Mapping in the Special PCI Target Image Universe Il s Interrupt and Interrupt Handler VME and PCI Interrupters For the VMEbus the interrupt source can be mapped to any of the VMEbus interrupt output pins such as VIRQ 7 0 If a hardware and software source are assigned to the same VMEbus VIRQn pin the software source always has higher priority Interrupt sources mapped to the PCI bus interrupts are generated via the PCI Interrupt pin INT 0 For the VMEbus interrupt outputs the Universe II interrupter provides an 8 bit STATUS ID to a VMEbus interrupt handler Optionally the Universe II generates an internal interrupt to signal that the interrupt vector has been provided Themis Computer 6 13 USPIli 3v User s Manual 6 5 2 6 5 3 6 5 4 6 5 5 6 14 Interrupts mapped to the PCI bus interrupt output pin INTO are serviced by the PCI Interrupt Controller The UItraSPARC IIi determines which interrupt sources are active by reading the interrupt status register in the Universe II The interrupt is negated after being serviced by the UItraSPARC IBD VMEbus Interrupt Handling A VMEbus interrupt causes the Universe II to issue a normal VMEbus IACK cycle and to generate the specified interrupt output When the IACK cycle is completed the Universe II
46. PCI 50 2 2 2 6 6 PCI Configuration Base Address 1 Register PCI 51 4 2222 6 7 VMEbus Fields for VMEbus Slave Image 6 8 PCI Bus Fields for VMEbus Slave Image eene eee ene eene 618 0008 6 8 Control Fields for VMEbus Slave Image 6 9 PCI Bus Fields for PCI Bus Target Drag 6 9 PCI Bus Fields for PCI Bus Target Image 6 10 Control Fields for PCI Bus Target Image eee eee nein 6 10 PCI Bus Fields for Special PCI Bus Target 6 11 PCI Bus Fields for Special PCI Bus Target 6 11 Control Fields for Special PCI Bus Target Image eee 6 11 Special PCI Target Image Register Offset 188 sese 6 12 Effects Resets ai od a a 7 5 inp ts notat 8 1 Watchdog o eus co eese US 9 2 R set Control MAS II aao Mei dein ii 9 3 Reset status Register RORY 5 a mea tac quindi e eram 9 3 DSP Times accetti dope ideo gato a qum eei Lus esu coUe 11 1 SCSI Termination Jumper a i i a desee o aa ine db dede ae ded 11 3 VME SYSCEK Source Jumper Settings deo Pose s sie ali 11 3 Flash 0 Write Enable Jumper 5
47. Power On Reset Scan POR generated in the RIC has the same effect as Push button POR Scan XIR Scan XIR generated in the RIC has the same effect as Push button XIR There is an additional source of reset at the Ultra 3 SYSRST L signal Correct handling of this reset source is extremely important because this signal 1s also a target during power up sequence To break a possible latching loop extra logics are inserted between the VME reset signal and the CPU reset inputs This logics blocks the VME reset signal from the CPU reset inputs during POR or SYS reset whenever RESET L signal is generated by the CPU The multiple reset capability of the Universe II PCI VME bridge gives more complications to the correct realization of the USPIE 3v reset system To facilitate the correct handling of the 3 level reset system of the CPU a FPGA is used to implement the necessary logics jumper set is added to select between the RIC and the FPGA outputs During diagnostic period using directly the RIC outputs can be convenient The notes in the reset block diagram are very important to consider Reset related functions in the FPGA Here only those functions are listed which are in relation with the reset procedure Themis Computer 7 Resets oj soouepodur ur oq 0 pasoddns 114 UAM uonezgep mir pue 24 3521 ur 106592014 ay daay pue 1 D IP 112Au02
48. Separate TSBs reside both in the MMU and the IOM Virtual Address An address produced by a processor that maps all system wide program visible memory Virtual addresses usually are translated by a combination of hardware and software to physical addresses which can be used to access physical memory WriteCycle A VMEbus cycle used to transfer 1 2 3 4 or 8 bytes from a Master to a Slave Themis Computer Computer Themis 3185 Laurel View Court t CA 94538 Publ Fremon Attn ications Department III SISU III ASS ILO II III S pH HIGH Ed 153525252122252525151511421211212415151512421242525151515141421212124251510101441052525 d Pao eo 1000000910004 0 00 00 0 92 00 0 0 0 0 M B 043 posco Mp Med S 315999090293 07 1399 000000 07 ASIS E poo oon 490808 84 30949 60555 252525252425 3 52525252525554 208080 coveve 004 Ela toed did Eo E d 2505 NNI 3233322352234 949810 090949 52525252555555555521227 050 0 45505 05 01 52525552525252 0 0 0 0 040 0 0 0464 5 95 95 91 5552525555555055555555 05555556555 85552555952555 6 525255552 55292444445 SOS ORES 85552255952555 25245552 555255525555 SOS SE Wie fete 555595595555 5 555525252525 5555565 1550909092542 is 955553 525559525252 8525252595525 55255595952524505525556 5 6 225952525252555052525250 52525600 154509000525 0 0 0 0 0 0 5
49. T11 B D26 SCSI DAT11 A NC 26 GND SCSI DAT12 B D27 SCSI DAT12 A NC 27 NC SCSI DAT13 B D28 SCSI DAT13 A 28 GND SCSI DAT14 B D29 SCSI DAT14 A 29 NC SCSI DAT15 B D30 SCSI DAT15 A 30 GND SCSI PAR1 B D31 SCSI PAR1 A 31 NC SCSI REAR B GND SCSI REAR A 5 4 2 Middle Board P2 Connector Connector Type Part Number FUJITSU FCN234J096 G V Row B Row C Top View O0O000000000000000000000000000000 Figure 5 13 Middle Board 2 Connector Orientation Themis Computer 5 17 USPIIi 3v User s Manual Table 5 15 Middle Board P2 Connector Pinout Signal Name Pin 3 TXD C RETRY L TXD D 4 RTS C A24 RTS D 5 DTR C A25 DTR D 6 RXD C A26 RXD D 7 DSR C A27 DSR D 8 DCD C A28 DCD D 9 CTS C A29 CTS D 10 RI C A30 RI D 11 MOUSE PS2 CLK A31 KEYB PS2 CLK 12 MOUSE PS2 DATA GND KEYB PS2 DATA 13 GND 45V TXCLK B 14 PP STROBE RXCLK B 15 PP DATAO CRS B 16 PP MII COLL B 17 PP DATA2 RX ER B 18 PP DATA3 D20 RX DV B 19 PP DATA4 D21 RXDO B 20 PP DATA5 D22 21 DATA6 D23 22 PP DATA7 GND 23 PP ACK D24 TXD3 B 24 PP BUSY D25 MII TXD2 B 25 PP PAPER EMPTY D26 26 PP SELECT D27 MII TXDO B 27 PP AUTOFEED D28 TXEN B 28 PP ERROR D29 29 PP INIT D30 TX ER B 30 PP SELECTIN D31 5 18 Themis
50. USPIli 3v User s Manual Version 2 1 September 2000 Themis Computer Americas and Pacific Rim Themis Computer Rest of World 3185 Laurelview Court 1 Rue Des Essarts Fremont CA 94538 Z A De Mayencin Phone 510 252 0870 38610 Gieres France Fax 510 490 5529 Phone 33 76 59 60 61 World Wide Webhttp www themis com Fax 33 76 63 00 30 Copyright 1999 2000 Themis Computer Inc ALL RIGHTS RESERVED No part of this publication may be reproduced in any form by photocopy microfilm retrieval system or by any other means now known or hereafter invented without the prior written permission of Themis Computer The information in this publication has been carefully checked and is believed to be accurate However Themis Computer assumes no responsibility for inaccuracies Themis Computer retains the right to make changes to this publication at any time without prior notice Themis Computer does not assume any liability arising from the application or use of this publication or the product s described herein RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252 227 7013 1 1 and FAR 52 227 19 TRADEMARKS SOLARIS isa registered trademark of Sun Microsystems SPARC is a registered trademark of SPARC International All other trademarks used in this publication are the property of their respective owners Themis Customer Support
51. UX AS 31302 WAMOd 51807 ISUSASXA VSIA 104293054 IFEMA OD WAM Od T 154 AINA 124 AAOO AGA T LSA SAS AINA 5218071 Taoa away PSIA T ISUSAS 8 AWA UA4AINA OW LSUX UAMOd AINA 154 AINA TISHIO LES AquQ oc oc Tort LSA 44 aod UAMOd ISA SAS USPIl 3v Reset Block Diagram Figure 7 1 Themis Computer USPIli 3v User s Manual 7 2 2 1 7 2 2 2 7 2 2 3 7 2 2 4 7 2 2 5 7 2 2 6 Watchdog timer level 3 interrupt When the level 3 Watchdog expires both level 2 and level 1 Watchdog have previously expired If the jumper between XRST RO OUT L Output and XRST_RQ_IN_L input is connected the Watchdog timer level 3 interrupt generates a reset being equivalent to the POR push button reset The only difference between these two resets is that the level 3 watchdog expired bit in the timer status register is set if the reset was initiated by the watchdog timer This bit must be cleared during the initialization after a reset recovery Watchdog timer level 2 interrupt Watchdog timer level 2 interrupt has the same effect as Push button XIR The only difference between these two resets is that the level 2 watchdog expired bit in the timer status register is set if the reset was initiated by the watchdog This bit must be cleared d
52. VMEbus 2 2 0 6 3 1 Universe II as the VMEbus aaa kasa saaa eksas 6 3 2 VMEbus First Slot Detector eese enne 6 3 2 1 Automatic Slot Identification esses 6 3 2 2 Registered Access at the power up Themis Computer 4 3 4 3 4 3 4 4 4 4 Table of Contents 6 3 3 Universe II s hardware Power Up Options 6 4 Slave Image o ead orestis itt etu Ue con a i ero 6 4 1 MME Slave Images a a S 6 4 1 1 VMIEbus Fields ces 6 4 1 2 FOI BUS Eie s ans Doa 6 4 1 3 Oo 51106 LAS OS aa is ia por Dept iuit onde d cse 6 4 2 PCI Bus Target 6 4 2 1 PET Bus Pic ls s ae trim tiet te Mese aaa 6 4 2 2 VMEbus Fields asa a De bd eode don e aee 6 4 2 3 Control 6 4 2 4 Special PCI Target Image L A eue 6 5 Universe II s Interrupt and Interrupt Handler eene 6 5 1 PCI Int rPUptets d iso 6 5 2 VMEbus Interrupt Handling lt 6 5 3 Universe Il s Mailbox am pda em eas 6 5 4 Universe IPs Semaphotr 8 casse a et eere a is 6 5 5 Programmable slave images on the VMEbus and PCI bus Di m M 7 1
53. VMEbus master access address interrupts and slave base address of the USPIIi 3v All other VMEbus interface related options are configured using extensions to the Sun OpenBoot PROM monitor program OBP stores system configuration parameters in non volatile storage NVRAM using a setenv mechanism familiar to UNIX shell users The OBP command setenv must be used to set the values of the environment variables The printenv command will list all supported environment variables and can be used to verify proper setting You must be at the OpenBoot command prompt to enter and execute OpenBoot commands Themis Computer 2 1 USPIli 3v User s Manual 2 3 2 4 If autoboot is enabled interrupt the boot sequence by pressing L1 A 5 on a serial terminal press BREAK If BOOTMON compatibility mode is enabled you will initially see the BOOTMON prompt Enter n tostart OpenBoot Type b boot c continue or n new command mode gt n ok gt At the ok gt prompt you are now able to enter OBP commands Use setenv to modify the environment variables necessary to configure the USPIIi 3v for your VMEbus configurations or execute the appropriate commands listed above The following example moves the slave window for A32 accesses to 0x80000000 and enables slave accesses ok setenv vme32 slave base 0x8000 0000 The automatically programs the Universe II VMEbus interface chip with the correct register values
54. a 11 11 Serial Port Solder Bead sc ve petet stripes ide n lta wena aus 11 11 Watchdog Control Mask Solder Bead 11 11 Watchdog Control Mode Solder Bead 11 12 Watchdog Control Request Solder Bead 11 12 JTAG Solder Bead ania 11 12 VDD Core Voltage Solder Bead Settings eese 11 13 Carrier Board a ais S 11 13 Themis Computer vii USPIli 3v User s Manual viii Themis Computer Figure 3 1 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 7 1 Figure 11 1 Figure 11 2 Listof Figures USPIU 5y BIOGK a 3 2 Front Panel Layout io a i 5 2 Front Panel Serial A and Serial B Connector Orientation esses 5 3 Front Panel Keyboard Mouse Connector Orientation esee 5 4 Front Panel SCSI A and SCSI B Connector Orientation eee 5 4 Front Panel Ethernet A and Ethernet Connector Orientation 5 7 P2 Paddle Boatd inae d e aa a i 5 8 P2 Paddle Board Parallel Port Connector Orient
55. ages 1 to 3 and 6 to 8 have a 64 KB resolution The maximum image size of 4 GB Table 6 5 VMEbus Fields for VMEbus Slave Image bound BD 31 12 or BD 31 16 in VSIx BD BB address space A16 A24 A32 User 1 User 2 Warning The address space of a VMEbus slave image must not overlap with the address space for the Universe II s control and status registers 6 4 1 2 PCI Bus Fields The PCI bus fields specifies the mapping of a VMEbus transaction to the appropriate PCI bus transaction and allows users to translate a VMEbus address to a different address on the PCI bus the translation of VMEbus transactions beyond 4 GB results in a wrap around to the low portion of the address range Table 6 6 PCI Bus Fields for VMEbus Slave Image VSIx TO selected PCI address Address space LAS in VSIx CTL Memory I O Configuration A32 Image Offset 31 12 VME 31 12 VME 11 0 PCI 31 12 PCI 11 0 Figure 6 2 Address Translation for VMEbus to PCI Bus Transfers 6 8 Themis Computer 6 4 1 3 6 4 2 6 4 2 1 AN 6 Universe Il Control Fields A VMEbus slave image is enabled using the EN bit of the control field The control field also specifies how reads and writes are processed either as a coupled transfer or a posted write At power up all images are disabled and configured for coupled reads and writes Table 6 7 Control Fields for VMEbus Slave Image posted write PWEN in VSIx CTL posted writed e
56. al Port B Loop Back 11 5 11 29 ROMBO PROM Boot Source 4 aaa aaa aaa 11 5 11 2 10 Temperature Shut DOW 1 ara aa dto a a 11 6 11 2 11 Temperature Fail ais i a e aaa 11 6 11 2 12 Temperature Warning Interrupt e a 11 6 11 3 Solder B GALI oe Sica iii a a i i a a d a E S 11 7 11 3 4 FPGA Bypass for SYS RST System 11 9 11 3 2 FPGA Bypass for PB RST Push Button POR 11 9 11 3 3 FPGA Bypass for X RST Push Button XIR 11 9 1134 Reset from V ME to GPL Sas eite optet dg Ia viene i qoo uten Ted 11 10 11 3 5 Reset from CPU to 11 10 11 3 6 Primary PCI Processor Bus 11 10 Hage Sena OUT on descen Tode le nts Sort brum e E 11 11 Port tef auod a dei ee 11 11 T123 9 Watchdog Control Mask usce e oa 11 11 11 3 10 Watchdog Control Mode reme a Us ia sa ia sa 11 12 11 3 11 Watchdog Control piece tins 11 12 11 312 JTAG A i E S 11 12 1122213 VDD Core VoOlldBe 4 a a Ro mu ME 11 13 EUS Ib Carrier Board s iecore a aa INI Lice uite 11 13 GIOSSAFY Ia iai ede ii i ne Cut cv beo TA A 1 A l a iai a a C 1 Themi
57. ard Drivers Figure 3 1 USPIli 3v Block Diagram 3 2 Themis Computer Ebus Address Latch EB LADR lt 23 8 gt Primary Boot Flash PROM 2 MB PCIB 33 MHz ROMBO Connector P2 EPLD Altera EPF8820ATC144 4 Dual Serial Interface A amp B SAB 82532 PCIA 33 MHz Cheerio A Front Panel RJ45 Ethernet2 10 100 Mbit Ethernet 2xABT827 10 100 Mbit Front Panel Ethernet RJ45 Ethernet 1 B Front Panel Secondary User Flash PROM 2x2 MB PC87307 Sun Keyboard Mouse Data Clock Lines 3xACA5020 Eilters Parallel Port 2xIPEC 1284 P2 or Serial Port CandD Figure B 1 Block Diagram Themis Computer USPIli 3v User s Manual 3 2 SystemSpecification 3 2 1 Processor Module amp Memory Subsystems Table 3 1 ProcessorSpecifications on page 3 4 and Table 3 2 Memory Specification on page 3 4 summarize the processor and memory subsystems Table 3 1 Processor Specifications Feature Function Specifications Processor UltraSPARC Ili Processor Speed Grade 1 300 MHz Grade 2 333 MHz Grade 3 360 MHz Performance 12 1 SPECint95 0 300 MHz w 256KB cache estimate 12 9 SPECfp95 9 300 MHz w 256KB cache estimate External Cache 2 MB SRAM fast Register Latch access mode for the 333 MHz and 360MHz Table 3 2 Memory Specification Feature Function Specifications Main Memory Proprietary Coplanar Modules O
58. ard AMP AMP AMP CONNECTORS AMP AMP 749070 9 745967 7 173279 2 786554 1 749070 7 5 3 1 5 Connector Pinouts Parallel Port Connector Type DB25 Female Connector Part Number AMP 745967 7 13 1 O O 25 14 Figure 5 7 2 Paddle Board Parallel Port Connector Orientation Table 5 7 P2 Paddle Board Parallel Connector Pinout Seat Nae Sia Nae Pa PRA LG TO PP DAT 1 16 PP INIT Pow Pom x E REOR LT Er EL EN eae Ec EE BERE LUN prd nn Themis Computer 5 9 USPIli 3v User s Manual 5 3 2 Ethernet MII A and Ethernet MII B Ports Connector Type 40 Pin Mini D Connector Part Number AMP 173279 2 19 1 O O 40 20 Figure 5 8 P2 Paddle Board Ethernet A and Ethernet B Connector Orientation Table 5 8 P2 Paddle Board Ethernet MII A and Ethernet B Connector Pinout Signal Name Pins Signal Name MDIO SGND RXD 3 SGND RXD 1 SGND RX DV SGND TX ER TX CLK TX EN PWR 5V C 5 3 3 SCSI A and SCSI B Ports Connector Type 68 Pin Female Shielded Subminiature D Connector Part Number AMP 749070 7 26 27 37 uu a XT a En E EE SN RE ND UE UI DEC Zi y Figure 5 9 P2 Paddle
59. ation eene 5 9 P2 Paddle Board Ethernet A and Ethernet B Connector Orientation 5 10 P2 Paddle Board SCSI and SCSI B Connector Orientation 5 10 P2 Paddle Board Serial C and Serial D Connector Orientation 5 12 P2 Paddle Board PMC I O Connector 5 13 Base Board and P2 Connector Orientation 5 15 Middle Board P2 Connector 5 17 PMC Carrier Board and P2 Connector Orientation eee 5 19 Base Board JTAG Connector Orientation 5 22 Base Board ROMBO Connector 5 23 Universe TL Architectural uoo 6 3 Address Translation for VMEbus to PCI Bus Transfers eee 6 8 Address Translation for PCI Bus to VMEbus Transfers 6 10 Memory Mapping in the Special PCI Target Image eee 6 13 USPII 3v Reset Block Diagrams oen dore aa kiai 7 3 USPIIi 3v Baseboard with Jumper Locations 11 2 USPIIi 3v Baseboard with Solder Bead 11 8 Themis Computer ix List of Figures Themis Computer X 1 1 1 2 1 Getting Started How to Use This Manual Thank you for purchasing the Themis USPIIi 3v computer The USPIi 3v system is composed of two 6U VME boards and requires 3
60. ck failure on each of the network interfaces when there is not a proper physical connection As only one interface can be active the inactive network interface will always return an external loopback error Ok test net for Ethernet 1 Test net 2 for Ethernet 2 Using MII Ethernet Interfac Lance Register test succeeded Internal loopback test succeeded External loopback test Lost Carrier transceiver cable problem send failed Using TP Ethernet Interfac Lance Register test succeeded Internal loopback test succeeded External loopback test succeeded send ok net selftest succeeded Attaching a Keyboard and Mouse A standard Sun Keyboard Mouse combination can be attached to the front panel KB M connector Attaching a TTY Terminal A TTY display terminal can be attached to the Serial A port on the front panel Use the serial cable from the accessories delivered with the USPIIi 3v Themis Computer 2 3 USPIli 3v User s Manual 2 4 Themis Computer 3 1 3 Specification System The system is an UltraSPARC IIi based design supporting PMC PCI mezzanine cards Sun FFB and VME64 modules The USPIIj 3v system consists of two 6U VME boards and occupies 3 VME slots The design is largely based on the Panther Board design from Sun Microelectronics and the Nordica Board design from Themis Computer It has been optimized for embedded systems industries The mem
61. dress space for the Universe II s control and status registers Themis Computer 6 9 USPIli 3v User s Manual 6 4 2 2 6 4 2 3 6 10 VMEbus Fields The VMEbus fields cause the Universe II to generate the appropriate VMEbus address AM code and cycle type allowing PCI transactions to be mapped to a VMEbus transaction It is possible to use invalid combinations such as block transfers in A16 space This may cause illegal transactions on the VMEbus All accesses beyond the 4 GB limit will wrap around to the low address range A32 Image Offset 31 12 VME 31 12 11 0 PCI 31 12 PCI 11 0 Figure 6 3 Address Translation for PCI Bus to VMEbus Transfers Table 6 9 PCI Bus Fields for PCI Bus Target Image base BS 31 12 or BS 31 16 in LSIx BS Translates PCI Bus Address to VMEbus Address bound BD 31 12 or BD 31 16 in LSIx BD 8 16 32 or 64 bits mode Supervisor or non privileged Control Fields Through the control fields the user specify how writes are processes and enable a PCI target image The PCI target image 1s enabled by setting the EN bit Posted Writes are performed when the PWEN bit is set and the particular PCI target image is accessed Posted writes are only decoded within PCI Memory space Access from other memory spaces are performed with coupled cycles regardless of the setting of the PWEN bit Table 6 10 Control Fields for PCI Bus Target Image EN in LSIx enable bit po
62. during reset Flash 0 Write Enable The function of jumper JP2201 is to enable or disable the write function to the Flash 0 device Table 11 4 Flash 0 Write Enable Jumper Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved Write to Flash 0 is disabled Write to Flash 0 is enabled Themis Computer 11 Jumpers and Solder Beads 11 2 4 11 2 5 11 2 6 Flash 1 and Flash 2 Write Enable The function of jumper JP2301 is to enable or disable the write function to the Flash 1 and Flash 2 devices Table 11 5 Flash 1 and Flash 2 Write Enable Jumper Settings Open Reserved Write to User s Flash 1 Write to User s Flash 1 and Flash 2 is disabled and Flash 2 is enabled Factory Default Keyboard TTYC The function of jumper JP2401 is to select between serial input from the keyboard connector located on the front panel or from TTYC located on the P2 Paddle Board Table 11 6 Keyboard TTYC Jumper Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved Serial input source is TTYC on the Serial input source is the P2 Paddle Board keyboard connector on the front panel Mouse TTYD The function of jumper JP2402 is to select between serial input from the mouse connector located on the front panel or from TTYD located on the P2 Paddle Board Table 11 7 Mouse TTYD Jumper Settings Open Positions 1 2 Closed Positions 2 3 Closed Reserved Serial input source is TTYD on
63. e and before the first read from the FLASH This delay normally is guaranteed because the reset to the CPU is delayed by the RIC by several ms relative to the POWER OK signal TOD and NVRAM The Non Volatile Memory NVRAM and a Time of Day TOD clock are both contained in the NVRAM memory SGS Thompson M48T59Y 70MH1 The has its own lithium battery to operate the clock and maintain the contents of the NVRAM during power off situations The battery device is an SGS Thomson Microelectronics BT1402 This single lithium battery provides backup for approximately 10 years and the real time clock circuitry provides accuracy of one 1 second per day NVRAM and TOD are programmed using the FORTH toolkit in Open Boot Program OBP Memory Subsytem The supports up to two 2 coplanar memory modules of either 64 128MB 256MB or 512MB each Each module of 64 128 128MB consists of 1 2 or 4 banks of 64MB organized as nine 9 4AMx16 EDO DRAMs NEC UP4265165 These modules provide 64MB 128MB 256MB of system memory Additionally there is a 512MB memory module consisting of 36 16Mx8 EDO DRAM chips The memory design includes Error Correction Code ECC A single bit error in a 64 bit word is corrected without loss of a cycle CAS before RAS refresh is used and CAS RAS and WE are buffered on the memory module Themis Computer 4 2 1 4 2 2 4 2 3 4 2 4 4 3 4 Hardware Overview Data Path and Interface
64. e opens a window to the resources on the PCI bus and through the specific attributes the VMEbus slave images allow the user to control the type of access to the PCI resources The VMEbus slave images are divided into VMEbus PCI bus and Control fields For the PCI Slave Images the Universe II accepts accesses from the PCI bus with the specific programmed PCI target images Each one of the PCI bus slave image opens a window to the resources on the VMEbus and it allows the user to control the type of access to the VMEbus resources The PCI bus slave images are divided into VMEbus PCI bus and control fields There is one special PCI target image which is separate from the VMEbus PCI bus and the control fields DMA Controller The Universe II utilizes an internal DMA controller for high performance data transfer between the VMEbus and the PCI bus Universe 5 parameters for the DMA transfer are software configurable DMA operations between the source and destination bus are decoupled via the use of a single bidirectional FIFO DMAFIFO Themis Computer 6 Universe Il There are two modes of operation for the DMA Linked List Mode and Direct Mode In Linked List Mode the Universe II loads the DMA registers from PCI memory and executes the transfers described by these registers In the direct mode the PCI master directly programs the DMA registers The DMA controller also utilizes the command packet A command packet is a block of DMA register
65. egisters Support for four location monitors Support for eight semaphores Support for RMW cycles and lock cycles This chapter is intended to outline the VMEbus to PCI Bus interface on the USPIIi 3v If more detailed information is need please refer to the Tundra Universe II User s Manual Note All registers on the Universe II are little endian Themis Computer 6 1 USPIli 3v User s Manual 6 2 6 3 6 2 VMEbus Configuration The following lists the initial configuration of the VMEbus system VMEbus First Slot Detector Two methods of Auto Slot ID Register Access at the power up Universe as the VMEbus Slave The Universe Is VMEbus Slave Channel supports all of the addressing and data transfer modes which are documented the VME64 specification The Universe II does not support the A64 mode and the ones that are intended to augment the 3U applications i e A40 and MD32 The Universe II becomes a slave when one of its eight programmed slave images or register images are accessed by a VMEbus master not that the Universe II cannot reflect a cycle on the VMEbus and access itself Depending on the programmed values of the VMEbus slave images or the incoming write transaction from the VMEbus may be treated as either posted or coupled If the post write operation is selected then the data is written to a Posted Write Receive FIFO RXFIFO and then the VMEbus master receives the data acknowledgment from the Univ
66. er LED register reset logic and Ebus control logic At power on the FPGA self loads from a serial EPROM Altera EPC1213PC8 to program itself for these features For more information on the FPGA refer to Chapter 9 FPGA Themis Computer 4 3 USPIli 3v User s Manual 4 1 10 4 1 11 4 2 4 4 National Super I O The National Super I O PC87307 ICE is an industry standard single chip solution that provides support for Sun KB MS two 2 fast full function asynchronous serial ports Serial Ports C and D and an IEEE 1284 bi directional parallel port Each component is individually configured to maximize the performance of the Seimens 82532 The Seimens 82532 Enhanced Serial Communication Controller provides support for Serial Ports A and B and used for TTYA and TTYB Serial Ports A and B are supported entirely independent of one another Boot FLASH PROM and Non volatile Storage The Boot FLASH PROM is the AMD 29F016 This is a 2MBit x 8 Flash Prom memory device The access time of this device shall be at least 90 nanoseconds The User FLASH shall consist of two 2 erasable 16MBit AMD 29F016 devices organized in 2Mbit x 8 configurations The device uses a 5V power supply and a 90 nanosecond access time The total user FLASH in the Ultralli 3V design is 4 MBytes Using the RP signal of the FLASH for protection during power up and reset requires several microsecond delay after the RP goes inactiv
67. erse IL The Universe II transfers the write data from the RXFIFO without the involvement of the initiating VMEbus master refer to Posted Writes on page 2 15 of the Universe II manual for a complete explanation of this operation If the coupled cycle operation is selected the transaction is completed on the PCI bus first and then the data acknowledgment is sent to the VMEbus master With the coupled cycle the VMEbus is not available to other masters while the PCI bus is executing the transaction Read transactions may either be pre fetched or coupled A pre fetched read is initiated when it is enabled by the user and when a VMEbus master requests for a block read transaction BLT or MBLT When the Universe II receives a request for the block transfer using burst transactions from the PCI bus resource it begins to fill its Read Data FIFO RDFIFO The initiating VMEbus master then obtains its block read data from the RDFIFO of the Universe II rather than the PCI resources directly A RMW cycle allows a VMEbus master to read from a VMEbus slave and then write to the same resource without releasing the bus between the two operations Each one of the Universe II slave images can be programmed to map RMW cycles to the PCI Locked cycles RWM cycles are not supported with the unaligned or D24 Cycles In order to support the VMEbus broadcast capability Universe II has four Location Monitors The location monitor s image consist of a 4Kbyte image in
68. initiates a Watchdog Interrupt and starts Level2 Watchdog Wgd2 if it is enabled When Wdg2 expires it generates an XIR interrupt and initiates Level3 Watchdog Wdg3 if it is enabled When Wdg3 expires it generates a POR interrupt if the SD0803 solder bead is shorted 9 4 1 Watchdog Registers There is a common register for the three watchdogs 0x30 Interrupt Mask Register The access to this register is controlled by SB2902 solder bead 0 1 disable enable Wdgl Bitl 0 1 disable enable Wdg2 Bit2 0 1 disable enable Wdg3 Table 9 1 Watchdog Registers Address Register Name and Function Register Length Toe wer wa Um esa oe Wdg3 Down Counter Big endian Wag3 Limit register Big endian 0x28 Wdg3 Status Register 2 bits NL MM 9 2 Themis Computer 9 5 9 5 1 9 5 2 Reset Logics After boot different reset behavior can be programmed using the reset registers Reset Control Register RCR Address 0x44 Table 9 2 Reset Control Register Value 5 Reset VME through the bridge on POR T an TI TEST ATA E 5 s mme Reset Status Register RSR Address 0x48 Table 9 3 Reset Status Register RSR 5 POR resulted from VME Reset XIR resulted from VME Reset Too long VME Reset is present VME Reset stucked
69. ion Table 5 19 Base Board ROMBO Connector Pinout 5 Connector Pinouts B EB LADR12 B EB ADR7 B EB ADR6 12 WR L EST L I sw 7 CR EE ae 0 ES ae EAE poo NL MIL as per gt E RCM uw p qe NEA EEK EE ND ET B EB LADR14 B EB LADR13 EB LADRO8 Themis Computer 5 23 USPIli 3v User s Manual 5 24 Themis Computer 6 Universe lIl 6 1 Features Tundra s Universe II CA91C142 interfaces the local 32 bit PCI bus to the VMEbus The following lists some of the Universe II s features on the USPIIi 3v board 33 MHz 32 bit PCI bus interface Fully compliant high performance 64 bit VMEbus interface Integral FIFOs buffer with multiple transactions from the PCI bus to the VMEbus and from the VMEbus to the PCI both directions Programmable DMA controller with linked list support A broad range of VMEbus address and data transfer modes of A32 A24 A16 master and slave transfer except for A64 and A40 D64 D32 D16 D08 master and slave transfer except for MD32 MBLT BLT ADOH RMW LOCK and location monitors Support for full VMEbus System Controller Nine user programmable slave images on the VMEbus and the PCI bus ports Seven interrupt lines Auto initialization for the slave only applications Programmable registers from both the VMEbus and the PCI bus Support for four mailbox r
70. lf loads from a serial EPROM Altera EPC1213PC8 to program itself for the features above The FPGA base address is 1FF F120 0000 the Audio CS from the Cheerio B In the rest of the chapter the addresses are given as an offset in hex format relative to the base address ROMBO andFlash Selection Signals The ROMBO connector on the USPIIi 3v 72201 and J2202 adjacent connectors together allows the system to boot from external boot source Additional boot sources are the System Flash PROM and the two User Flash PROMs The 2MB initial boot space starts at 1FF F000 000 Depending on the JP2902 and JP2901 jumpers the initial boot space address selects the ROMBO 11 FlashO 00 Flash1 01 and Flash2 10 sources for boot Independently from the jumper settings the following mapping is valid Flash0 can be accessed at 1FF F020 0000 2MB long e Flashl can be accessed at 1FF F040 0000 2MB long e Flash2 be accessed at 1FF F060 0000 2MB long Themis Computer 9 1 USPIli sv Software Manual 9 3 User LEDs The lower four bits of the Register Ox4C control the User LEDs Bit 0 corresponds to USER 1 LED 9 4 Watchdog Timers Note At the time of this writing there is no supporting software for the three Watchdog Timers The use of these timers is up to user discretion The watchdog counters are 10 bit wide and the clock is 10 Hz The longest time for one watchdog is 102 4 second When the Levell Watchdog Wdg1 expires it
71. mpared to the amplifier output level by two comparators The output of the Warning level comparator goes to the JP3203 jumper If the jumper is in position 1 2 the low level of the comparator generates the Temperature Warning interrupt The output of the Fail level comparator goes to the JP3202 and JP3201 jumpers If the JP3202 jumper is in 1 2 position the low level of the Fail comparator generates the Temperature Fail interrupt If the JP3201 jumper is in 1 2 position the low comparator output shuts down the 3 3V and 2 6V DC DC converters Note Before using the temperature interrupts consult with Themis Computer Temperature Sensing and Monitoring in the OBP There are two environmental variables in the OBP to set the Warning and Fail temperatures in Celsius degree temp warning and temp critical After the boot the following OBP command reads back the two values from the digital potentiometer read ds1867 setting Themis Computer 10 1 USPIli sv Software Manual Even if the digital potentiometers save the settings at power down the OBP rewrites the potentiometers at each boot At power up the potentiometers must have good values not to shut down the system immediately if the JP3201 jumper is in position 1 2 The shut down state is visible by the red SHUTDOWN LED on the front panel 10 2 Themis Computer 11 Jumpers and Solder Beads 11 1 Overview This chapter provides a listing of the jumper settings and solder bead
72. mware 64 Bit Extensions PCI Bus Binding to IEEE 1275 1994 Standard for Boot Initialization Configuration Firmware Revision 1 0 14 April 1994 Prepared by the Open Firmware Task Force of the PCI Alliance The SPARC Architecture Manual Version 9 David L Weaver and Tom Germond editors PTR Prentice Hall Themis Computer 1 3 USPIli 3v User s Manual 1 4 Themis Computer 2 1 2 2 2 Installation OpenBOOT PROM OBP Configuration The OpenBOOT PROM OBP code is used to boot the operating system run diagnostics modify system start up parameters and to load and execute programs The version of OBP code used on the USPIIi 3v 15 OBP Release 3 10 13 and later At power up the processor fetches instructions starting at physical address ADDRESS from the FLASH device where the OBP code is stored to execute an appropriate start up sequence Themis Computer provides an OBP Configuration pre programmed in the FLASH However this configuration may be modified to fit an individual user s needs modifications are made using the FORTH Monitor Configuring The VME Interface Themis has implemented a variable and flexible VMEbus interface using both on board jumpers OpenBoot PROM OBP commands and environment variables specific to the USPIIi 3v board The is typically re configured when VMEbus boards are added removed or changed in the chassis Board configuration normally involves allocation of
73. n 2 1 June 1 1995 PhysicalAddress An address that maps to real physical memory or I O device space PIO Accesses by a Master on the primary bus to a Slave on the secondary bus PIO is equivalent to Downstream Probing A process implemented in the firmware and software to identify onboard hardware devices and add on cards on the PCI bus The probing process creates the device tree RO An abbreviation used to indicate Read Zero When software attempts to read an RO area zero will be returned Writes to RO are not permitted Read Cycle A VMEbus cycle used to transfer 1 2 3 4 or 8 bytes from a Slave to a master Read Modify Write Cycle A VMEbus cycle used to read from and then write to a Slave location without permitting any other Master to access that location during that cycle RED state The Reset Error and Debug state of the UItraSPARC IIi processor The UltraSPARC IIi enter the RED_ state when PSTATE RED 1 Software A collection of machine readable information instructions data and procedures that enable the computer to perform specific functions Typically stored on removable media Solaris The best known operating system from Sun TLB Translation Lookaside Buffer A hardware cache that contains copies of recently used translations Separate TLBs reside both in the MMU and the IOM TSB Translation Storage Buffer A one level software data structure that maintains address translation information
74. nable bit Note For a VMEbus slave image to respond to an incoming cycle the PCI Master Interface must be enabled bit BM in the PCI CSR register PCI Bus Target Images The Universe II accepts accesses from the PCI bus with specific programmed PCI target images that open windows to the VMEbus and control to the type of access to the VMEbus There are eight 0 7 standard PCI target images and one special PCI target image The special PCI target image may be used for A16 and A24 transaction freeing the other 8 images for standard A32 transactions PCI Bus Fields Decoding for VMEbus accesses is based on the address and command information produced by a PCI bus master The PCI Target Interface claims a cycle if there is an address match and if the command matches certain criteria The PCI target images are A32 capable only For accesses other than A32 the Special PCI Target Image may be used refer to Section 6 4 2 4 Special PCI Target Image on page 6 11 Of the eight standard PCI target images the first and fifth PCI target images 0 and 4 have a 4 KB resolution PCI target images 1 to 3 and 5 to 8 have a 64 KB resolution Table 6 8 PCI Bus Fields for PCI Bus Target Image BS 31 12 or BS 31 16 in LSIx BS Multiples of 4 or 64 KBytes base to BD 31 12 or BD 31 16 in LSIx BD Bound maximun ot LAS in LSIx CTL Memory or I O Warning The address space of a VMEbus slave image must not overlap with the ad
75. ne 1 to two 2 Modules Memory Bus Interface 72 bit Data Path from CPU including 8 bit ECC 2 to 1 Interleave to DRAM 13 bit Address Bus 3 3V Level Interface Memory Modules Four Module Types 64 MB using 9 4Mx16 EDO DRAMs 128 MB using 18 AMx16 EDO DRAMs 256 MB using 36 4Mx16 EDO DRAMs 512 MB using 36 16Mx8 EDO DRAMs Memory Configurations 64 MB One 1 64 MB Module 128 MB One 1 128 MB Module 256 MB One 1 256 MB Module 512 MB Two 2 256 MB Modules One 1 512 MB Module 1 GByte Two 2 512 MB Modules 3 4 Themis Computer 3 Specification 3 2 2 3 2 3 I O Subsystem Table 3 3 I O Sub system Specification on page 3 5 summarizes the I O subsystem functionality Table 3 3 Sub system Specification Function Sun Keyboard Mouse Port PS 2 Compatible KB Mouse Port Location Front Panel Paddle Board Serial Port A RS 232 Serial Port B RS 232 422 Serial Port C RS 232 If Sun KB MS is not in use Serial Port D RS232 If Sun KB MS is not in use Parallel Port Bi Directional IEEE1284 Front Panel sync asynch Front Panel sync asynch Paddle Board asynch Paddle Board asynch Paddle Board Ethernet Port 1 Ethernet Port 2 RJ45 Front Panel 10 100BaseT MII 1 Interface Paddle Board RJ45 Front Panel 10 100BaseT MII 2 Interface Paddle Board Single Ended Ultra Wide SCSI PMC 0 and PMC 1 I O upper 32 bits PMC Expansion Three PMC
76. ng knowledge of the VMEbus specifications SPARC processor architecture Ethernet and SCSI ANSI X3 131 1986 Themis Computer 1 1 USPIli 3v User s Manual 1 2 1 Product Warranty and Registration Please review the Themis Computer warranty and complete the product registration card delivered with your USPIIi 3v system Return of the registration card is not required to activate your product warranty but by registering your USPIIi 3v Themis Computer will be able to better provide you with timely updated information and product enhancement notifications Our Customer Support department is committed to providing the best product support in the industry Customer Support is available 8am 5pm PST Monday through Friday via telephone fax e mail or our World Wide Web site Themis Customer Support Telephone 510 252 0870 Fax 510 490 5529 E mail support themis com Web Site http www themis com 1 3 Unpacking Caution 5 contains static sensitive components Industry standard anti static measures must be observed when removing the USPII 3v from its shipping container and during any subsequent handling A wrist strap or grounding strap provides grounding for static electricity between your body and the chassis of the system unit Electric current and voltage do not pass through the wrist strap Remove the USPIIj 3v and accessories from the shipping container and check the contents against the packing list The
77. nostics the signal is always disconnected Table 11 11 Temperature Shut Down Jumper Settings Reserved Temperature Shut Down signal is Temperature Shut Down signal is connected disconnected Factory Default Temperature Fail Interrupt The function of jumper JP3202 is to connect disconnect the Temperature Fail Interrupt Reguest signal during normal system operation During initial power up and system diagnostics the signal is always disconnected Table 11 12 Temperature Fail Interrupt Jumper Settings Positions 1 2 Closed Positions 2 3 Closed Temperature Fail Interrupt Temperature Fail Interrupt Reguest signal is connected Request signal is disconnected Open Reserved Temperature Warning Interrupt The function of jumper JP3203 is to connect disconnect the Temperature Warning Interrupt Request signal during normal system operation During initial power up and system diagnostics the signal is always disconnected Table 11 13 Temperature Warning Interrupt Jumper Settings Reserved EE Warning Interrupt LAM Warning Interrupt Request signal is connected Request signal is disconnected Themis Computer 11 7 USPIIi 3v User Manual 11 3 11 8 Solder Beads The USPIIi 3v has fourteen factory configurable solder bead settings The Customer Service department should be contacted 1f something other than default functionality is desired Location of the solder beads is shown below
78. ocessor clocks are used to return the E Cache data giving a 4 cycle pin to pin latency As a result of the tight control over the SRAM turn on and turn off times no dead cycles are necessary when alternating between reads and writes Memory accesses to the E Cache must be cacheable Consequently no E Cache enable bit is present in the LSU Control Register Refer to Table 5 4 LSU Control Register Instruction fetches are directed to non cacheable PCI or UPA64S space when any of the following conditions are true The I MMU is disabled The UItraSPARC II is in RED state The access is mapped by the I MMU as physically non cacheable Data accesses to non cacheable PCI or UPA64S space occur when either The D MMU enable bit DM in the LSU Control Register is clear or The access is mapped by the D MMU as non physical cacheable unless ASI PHYS USE EC is used Note When non cacheable accesses are used the associated addresses must be legal according to the UltraSPARC II physical address map SME Advanced PCI Bridge APB The SME Advanced PCI Bridge SME SME2411 interfaces directly with the UltraSPARC IIi microprocessor and concentrates two 2 5V 33MHz PCI buses into one 3 3V 66 MHz PCI bus that interface directly with the UItraSPARC II The 66 MHz PCI to CPU can achieve a peak bandwidth of 2 GBits sec Within the USPIIi 3v the two 2 33 MHz PCI busses are referred to as PCIA and PCIB SME Reset Interrupt
79. or pinouts are presented as individual sections Themis Computer 5 1 USPIIi 3v User s Manual 5 2 Front Panel SYSTEM SHUTDOWN VME ACTIVE VME SYSCON SYSFAIL IN SYSFAILOUT ETHERNET 1 ETHERNET2 SCSIB SCSIA USER 1 USER 2 USER 3 USER 4 OO 5 2 Themis Computer Status LED s There are 14 LED s with the following functions LED Color 1 SYSTEM Green 2 SHUTDOWN Red 3 VME ACTIVE Orange 4 VME SYSCON Green 5 VME SYSFAIL IN Red 6 VME SYSFAIL OUT Red 7 ETHERNET 1 Orange 8 ETHERNET 2 Orange 9 SCSI B Orange 10 SCSI A Orange 11 USER 1 Red 12 USER 42 Red 13 USER 3 Green 14 USER 4 Green Figure 5 1 Front Panel Layout 5 2 1 5 Connector Pinouts Serial A and Serial B Connector Type Part Number ITT CANNON MDSM 30PE Z10 VR22 A8 Al 000000 Serial A A15 A9 B8 Bl o o Serial 15 B9 Figure 5 2 Front Panel Serial A and Serial B Connector Orientation Table 5 1 Front Panel Serial A Connector Pinout Pin Signal Name Pin Signal Name Receive Clock Port B N Receive Clock Port A Clear To Send Port B N Transmit Clock Port A N Clear To Send Port A 26 Transmit Data Port A am Request To Send Port A Receive Data Port A Not Used Table 5 2 Front Panel Serial B Connector Pinout Signal Name Signal Name E
80. ory sub system utilizes a family of proprietary co planar stackable DRAM memory modules of either 64 MB 128MB 256MB or 512MB per module Memory configurations of 64 MB 128 MB 256 MB 512 MB and 1GB are supported The local I O subsystem is PCI based with separate PCI channels provided for I O functions and external VMEbus backplane access The front panel of the USPIIi 3v system provides two SCSI ports two Ethernet ports two serial ports and Sun Keyboard Mouse connections The back panel VMEbus interface provides signals via the P2 Paddle Board delivered with the USPIIi 3v for Serial Port C amp D P S2 Kb amp MS MII 1 MII 2 or PMC slot 1 amp 2 SCSI A amp B Parallel port A triple PMC Carrier Board is available for vendor specific PMC board expansions Themis Computer 3 1 USPIli 3v User s Manual 3 1 1 Block Diagram Driver LVC16374 Drivers ni 3xLPT16244 DS Address Address 8 E CNTL CNTL Sila 2 UltraSPARC Ili EDO Processor Module DRAM g Data 72 D Proc SME1040 266 300 333 O Cache 512K 644 8P amp T 14 2 P or2M Data 144 128 16 66 MHz PCI Interface 1 GByte SME2411 6xSN74ALVC162268 PCIA 3 33 MHZ A 32 32 Dual Wide PCIMezzanine Board Ultra SCSI Interface A amp B and On Board PMCI 2 Termination PCIMezzanineBoard 10 SYM53C876 Tundra 2xUCC3912 Universe II 6xUC5606PLUS A B PMC2 64 VME Front PCIMezzanineBo
81. relinguishes the VMEbus The interrupt vector is read by the PCI resource servicing the interrupt output Hardware and internal interrupts are RORA Software interrupts are ROAK Universe II s Mailbox Registers Universe II contains four 32 bit mailbox registers that provide an additional communication path between the PCI bus and the VMEbus The mailboxes support read and write accesses from either bus The mailboxes may be enabled to generate interrupts on either bus whenever written to The mailboxes are accessed from the same address spaces and in the same method as other Universe II registers Universe II s Semaphores The Universe II contains two general purpose semaphore registers such as SEMAO and SEMA each register contains four semaphores To obtain the ownership of a semaphore a processor writes a logic one to the semaphore bit and an unique pattern to the associated tag field if a subsequent read of the tag field returns the same pattern then the processor has gained the ownership of the semaphore In order to release the semaphore the processor writes a value of O to it Programmable slave images on the VMEbus and PCI bus There are two types of accesses that the Universe II recognizes on its bus interfaces accesses for its own register space and accesses destined for elsewhere For the VME Slave Images the Universe II accepts accesses from the VMEbus within specific programmed slave images Each one of the VMEbus slave imag
82. ry PCI bus UltraSPARC modules include fully integrated external cache The UltraSPARC IIi microprocessor incorporates a CPU PCI bus interface and memory controller The UItraSPARC IIi modules are available in three configurations 300MHz with 5MB E cache clocked at 150 MHz 333MHz with 2 MB E cache clocked at 167 MHz and 360MHz with 2MB E cache clocked at half CPU frequency 300 MHz UItraSPARC IIi module consists of one UItraSPARC IIi CPU microprocessor one 64K x 18 tag SRAM four 64K x 18 data SRAMS and circuitry for generating the processor and UPA64S clocks PCI clocks are generated externally The module runs at 300 MHz internal processor frequency Clock synthesizer and division circuitry on the module set the UPA frequency to one third of the internal processor frequency The module interface is implemented using two high speed impedance controlled connectors The 333 MHz UItraSPARC IIi module consists of one UItraSPARC IIi CPU microprocessor one 64K x 18 cache tag SRAM four 256K x 18 cache data SRAMS and circuitry for generating the processor SRAM and UPA64S interfaces PCI clocks are generated externally The module runs at 333 MHz internal processor frequency The clock synthesizer sets the frequency and division circuitry operates the UPA frequency at one third of the internal processor frequency The module interface uses two high speed impedance controlled connectors Themis Computer 4 1 USPIli 3v User s Manual
83. s Computer Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 5 12 Table 5 13 Table 5 14 Table 5 15 Table 5 16 Table 5 17 Table 5 18 Table 5 19 Listof Tables Processor Specifications asies ais tb p ra is a ao a ad 3 4 Memory Specification sis vascos ise eb onm ERR XXE EEE 3 4 I O Sub system Specification io eh eite tend ee aeq RES ii i k SERE 3 5 Auxiliary Functions SpecttiCatlotis asa eic eoe ore a aa see o RR ai 3 5 USPIIi 3v Operating Environmental 3 6 USPIIj 3v Non operating Environmental Specifications 3 6 Front Panel Serial A Connector 0 5 3 Front Panel Serial B Connector Pino t 2 iei teda sesta da deseada 5 3 Front Panel Keyboard Mouse Connector 5 4 Front Panel SCSI A Connector Pinout sess 5 5 Front Panel SCSI B Connector 0 5 6 Baseboard RJ45 Ethernet amp B Pinout 5 7 P2 Paddle Board Parallel Connector Pinout eese 5 9 P2 Paddle Board Ethernet MII A and Ethernet MII B Connector Pinout 5 10 P2 Paddle Board SCSI and SCSI B Connector
84. s stored in PCI memory A command packet may be linked to another command packet so that when the DMA has finished the operations described by one command packet the DMA controller can automatically move on to the next command packet in the linked list of command packets Themis Computer 6 15 USPIli 3v User s Manual 6 16 Themis Computer 7 1 7 2 7 Resets Overview This chapter presents a brief discussion of the reset structure of the USPIIi 3v The various types of resets some possible reset sources and reset effects are explained Resets are used to force all or part of the system into a known state A Reset is defined as any action or signal that places the UltraSPARC IIi in Reset Error and Debug State RED State This state will be entered under any of the following conditions Trap is taken when Trap Level Max Trap Level 1 One of the Reset request signals POR XIR WDR becomes active e A reset request SIR is issued when the Trap Level lt Max Trap Level If Trap Level Max Trap Level the UltraSPARC IIi enters and error state Internal processor error exception or catastrophic errorexception occurs The setting of PSTATE RED by system software The RED state is indicated by the PSTATE RED bit being set For more information on the RED state consult Section 17 3 RED state of the UItraSPARC II User s Manual The system or part of the system may also be reset by a Watchdog Reset WDR
85. sFirst Slot Detector As defined by the VME64 specification the Universe II samples the BG3IN right after the reset to determine if the USPII 3v resides in slot 1 If the BG3IN is sampled low right after the reset then the USPIIi 3v board becomes the SYSCON otherwise the SYSCON Module of the Universe IIis disabled The software can set or clear the SYSCON bit the MISC CTL register of the Universe II The offset of this register is Ox404 Table 6 1 Universe Il Miscellaneous Control Register MISC CTL ge ESA AI 31 28 VBTO VMEbus Time out 0000 Disable 0001 16 us 0010 32 us 0011 64 5 0100 128 us 0101 256 us 0110 512 us 0111 1024 us Others RESERVED 26 VARB VMEbus Arbitration Mode 0 Round Robin 1 Priority 25 24 VARBTO VMEbus Arbitration Time out 00 Disable Timer 01 16 us minimum value of 8 us due to the 8 us clock granularity 10 256 us others RESERVED 23 SW LST PCI Reset 0 no effect 1 initiate PCI bus LRST 22 W SYSRST Software VMEbus SYSRESET 0 no effect 1 Initiate VMEbus SYSRST 20 BI Mode 0 Universe II is in Bl mode 1 Universe II is not in BI mode 19 ENGBI Enable Global Bl mode Initiator 0 Assertion of VIRQ1 ignored 1 Assertion of VIRQ1 puts the Universe Il in Bl mode 18 17 SYSCON SYSCON Power up 0 Universe II is not a VMEbus System Controller Option 1 Universe II is a VMEbus System Contoller 16 V64AUTO VME64 Auto ID Power up Wri
86. service se Table 11 28 Carrier Board Jumper Settings Function References Ethernet MII B Default R0201 R0203 R0204 R0207 R0208 R0211 R0212 R0214 R0216 R0218 R0221 R0222 R0225 R0226 R0228 R0230 R0232 R0235 R0236 R0202 R0205 R0206 R0209 R0210 R0213 R0215 R0217 R0219 R0220 R0223 R0224 R0227 R0229 R0231 R0233 R0234 R0237 R0238 11 14 Themis Computer A 1 A Glossary Terminology The terminology used in this manual generally follows industry conventions The following list defines the specific meanings of words and terms as used in this section A16 Addressing on address line A 15 1 as specified in ANSI VME64 Specification A24 Addressing on address line A 24 1 as specified in ANSI VME64 Specification A32 Addressing on address line A 32 1 as specified in ANSI VME64 Specification A40 Addressing on address line A 40 1 as specified in ANSI VME64 Specification A64 Addressing on address line A 64 1 as specified in ANSI VME64 Specification Arbitration The process of assigning the data transfer bus to a Master or Slave ASI An abbreviation for Address Space Identifier Boot The process of initializing the hardware to execute and run an operating System such as Solaris 2 6 CPI Cycles per Instruction The number of clock cycles required to execute one instruction Devicetree The OBP probing process constructs a hierarchal representation of the hardware devices that are found on the bus
87. ss ope Dod ade t etapas Sede Connector PIN OUTS occisa ish Dr De ta ra rx CER a ai Qe Car i i RE Sa Oe 5 1 corre COEUR REDE 5 2 co eot Dr M a dae M 5 2 1 Seral aid Serial B uec rite equiti edu desees 2222 Keyboard MOUSE isd sasas ass L o a a Ui qo i 5 2 3 SCSIA amb se is i 5 2 4 Ethernet and Ethernet 2 202222020 1 21 0000000000000000 5 5 3 P2 Paddle Board ni si saaa ais 5 3 1 Parallel ii a a a a e Ia ia a aaa ai a 5 3 2 Ethernet MII A and Ethernet B 5 3 3 SCSI B Parts ene 5 3 4 Serial and Serial D Ports kaka 5 3 5 5 4 PLAP 5 4 1 Base Board P2 Connectors 22 0 0 00 5 4 2 Middle Board P2 Connector 5 4 3 PMC Carrier Board 1 02002224 0 000000000000 545 Base Board aaa aaa 5 5 1 ere Ya ee Rr SE 5 52 ROMBO Connector iais aestate eat rette eei ME eia Iain eL 6 1 TG AUTOS eth erem a fiit het e Ieri PEU ais 6 2 VMEDUS Configuratore ree erige teer igo se rod oai si Ev 6 3 Universe II as the
88. sses on its bus interfaces accesses destined for the other bus and accesses decoded for its own register space VME Slave Images A VMEbus slave image is used to access the resources of the PCI bus when the Universe II is not the VMEbus master The user may control the type of accesses by programming specific attributes of the VMEbus slave image The Universe II will only accept accesses to the VMEbus from with the programmed limits of the VMEbus slave image Note The Bus Master Enable BM bit of the PCI CS register must be set in order for the image to accept posted writes from an external VMEbus master If this bit is cleared while there is data in the VMEbus Slave Posted Write FIFO the data will be written to the PCI bus No further data is accepted into this FIFO until the bit is set VMEbus Fields Before the Universe II responds to a VMEbus Master other than itself the address must lie between the base and bound addresses and the address modify must match modifier specified by the address space access mode and type fields A description of the VMEbus fields for VMEbus Slave Images in presented in Table 6 5 VMEbus Fields for VMEbus Slave Image on page 6 8 Themis Computer 6 7 USPIli 3v User s Manual The Universe II eight VMEbus slave images 0 7 are bounded by A32 space Slave images 0 and 5 have a4 KB resolution Typically these images would be used as an A16 image since they provided the finest granularity Slave im
89. sted write PWEN in LSIx CTL posted write enable bit Themis Computer 6 4 2 4 6 Universe Il Note For a VMEbus slave image to respond to an incoming cycle the PCI Master Interface must be enabled bit BM in the PCI register Special PCI Target Image A special PCI target image is provided to expedite A16 and A24 transaction The other eight standard PCI target images are typically programmed to access A32 space The special PCI target image is a 64 MB space located either within memory or I O space that is decoded using PCI address lines 31 26 Its base address is aligned on 64 MB boundaries and no offsets are provided Therefore PCI address information is mapped directly to the VMEbus The special PCI target image has a lower priority than any other PCI target image The 64 MB space is divided into four 4 16 MB spaces that are selected using AD 25 16 For each region the upper 64 KB map to VMEbus A16 space while the remaining portion map to VMEbus A24 space The addressing of this slave image is depicted in Figure 6 2 Address Translation for VMEbus to PCI Bus Transfers on page 6 8 Table 6 11 PCI Bus Fields for Special PCI Bus Target Image BS 05 in 64 MB aligned base address for the image Table 6 12 PCI Bus Fields for Special PCI Bus Target Image maximum data width VDW in separately set each region for 16 or 32 bits mode SUPER in separately set each region for supervisor or non privileged
90. systems in a single enclosure the FPGA can be modified to avoid this continuous reset situation The FPGA can be modified though the NVRAM which takes effect during boot up The continuous reset problem is the result of an extra reset from the CPU which appears between the POST and the OBP The POST executes at slightly different speeds on different systems and therefore the reset appears at different times on the different systems The quickest system will reset the reset of the systems and then the next quickest will reset the reset of the systems and so on The reset related part of the FPGA will be described in more detail in Chapter 9 FPGA Themis Computer 7 5 USPIli 3v User s Manual 7 6 Themis Computer 8 1 Interrupt System 8 Interrupts There are two main sources for the interrupts in the Ultra system The standard peripheral devices which have inputs in the RIC already assigned by Sun The new interrupt lines of the additional standard devices have to be assigned to the available inputs of the RIC The slot type PCI devices PMCs which may have maximum 4 interrupts per slot Sun produced an assignment rule for these interrupt lines using the Sbus interrupt inputs of the RIC Table 8 1 Interrupt inputs to RIC shows this assignment together with the selections for the Ultra IIi 3V additional interrupt lines Table 8 1 Interrupt inputs to RIC SB3 IRQ6 PMC3 A B3 B1 B AD13 SB3 IRQ5 S
91. te 0 no effect 1 Initiate sequence Option This bit initiates the Universe II VME64 Auto ID Slave par ticipation a Allunspecifiedbitsinthistableare RESERVED forthe Universe ll andshouldnotbe accessedbytheuser When the Universe II is configured as the System Controller it provides the following functions on the VMEbus A 16MHz Clock Driver An Arbitration Module 6 4 Themis Computer 6 3 2 1 6 3 2 2 6 3 3 6 Universe Il Abus timer An IACK Daisy Chain Driver DCD The USPIli 3v supports Round Robin arbitration The VMEbus arbitrator time out is also controlled by the MISC CNT register described above The timer may be set to either 16 us 256 us or disabled The default setting is 16 us The arbitration timer has a granularity of 8 us setting the timer to 16 us means the timer may expire in as little as 8 us or as much as 24 us It should also be noted that disabling the arbitration timer means that the Universe II will not recover from an access error Disabling the arbitration timer is not recommended Automatic Slot Identification The Universe II supports two types of Auto ID functionality Auto Slot ID as described by VME64 specification Proprietary Method which is developed by Tundra Refer to the following sections for a detailed description of Auto Slot ID VME64 Specified on page 2 24 and Auto ID A Proprietary Tundra Method on page 2 25 of the Universe II Manual for
92. the Serial input source is the P2 Paddle Board mouse connector on the front panel Themis Computer 11 5 USPIIi 3v User Manual 11 2 7 11 2 8 11 2 9 Serial Port B Transceiver Mode The function of jumper JP2601 is to select the transceiver mode for Serial Port B Table 11 8 Serial Port B Transceiver Mode Jumper Settings Reserved RS232 Mode RS422 Mode Factory Default Serial Port B Loop Back Mode The function of jumper JP2602 is to select the loop back mode for Serial Port B Table 11 9 Serial Port B Loop Back Mode Jumper Settings Reserved Loop Back Mode Normal Mode PROM Boot Source The function of jumpers JP2901 and JP2902 is to select the boot source selection of the boot source reguires that JP2901 and JP2902 be set in conjunction with one another Table 11 10 ROMBO PROM Boot Source Jumper Settings Positions 1 2 Closed amp Positions 2 3 Closed amp Positions L cluspd Positions Positions 2 3 Closed Positions 1 2 Closed ROMBO is Boot Source Flash 0 is Boot Source Flash 1 is Boot Source Flash 2 is Boot Source via connector pair J2201 and J2202 Themis Computer 11 Jumpers and Solder Beads 11 2 10 11 2 11 11 2 12 Temperature Shut Down The function of jumper JP3201 is to connect disconnect the Temperature Shut Down signal during normal system operation During initial power up and system diag
93. uring the initialization after a XIR reset recovery Note When the level 2 Watchdog Timer expires both the corresponding internal bit of the USPIIi 3v and the status bit of the Watchdog are set When the level 2 Watchdog expires the level 1 Watchdog should have previously expired FPGA Reset Logics For each level of reset the FPGA contains logics to combine all the reset sources into three possible groups Additionally to the actual signal sources there are programmable register bits as inputs outputs to the reset logics Detailed description can be found in Chapter 9 FPGA Reset Turnaround Logics This is a patch to assure the start of the system when the processor can not come out from the reset procedure In this case this logics re resets the processor VDD CORE Voltage Protection As part of the reset power management this logics shuts off the DC DC converters for the VDD and CORE whenever any of the voltages VCC VDD or fails VME Reset Resolution Logics The complexity of the reset of the UNIVERSE PCI VME bridge requires special handling of its reset inputs outputs to be able to integrate the bidirectional VME reset smoothly into the USPII 3v reset system When the UItraSPARC Ili asserts its reset output the reset is propagated to the whole board Themis Computer 7 Resets After a reset all the components are in a known state Note that for many of these components the presence of one or multiple clocks is

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