OKI Semiconductor ML86V7655/56 Preliminary
Contents
1. Table 7 Vidieo Output Pins Output format Pin name Composite CVBS S Video YS CS xo EBORE Y G Cb B Cr R interlaced progressive 18 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 INTERNAL REGISTERS Use the I2C interface to change the internal register values For details on register functions refer to the User s Manual Table 8 Register Map Sub address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 EXTSEL MSSEL Reserved MLTDAT IMODSEL 2 0 01 Reserved IN2S 1411 SPL411 NPSEL 1444SEL IRGBSEL IPRGSEL 02 SONSEL LDSEL PISEL OFINV OHCSEL CSSEL ORGBSEL OPRGSEL 03 CBON BBON MCON SBON RGBLEV SETUP OUTLEV 1 0 04 Reserved DMASK1 Reserved DMASK2 05 Reserved 06 CNTCTL TFON Reserved FRUN BLKADJ 3 0 07 Reserved SYNCLEV 1 CVBS 2 0 Reserved SYNCLEV2 COMP 2 0 08 NOSIG Reserved LUMLEV 3 0 09 GGAIN 7 0 0A BGAIN 7 0 0B RGAIN 7 0 0C DACOFFSET 1 0 DACOFF 5 0 oD Reserved Reserved FFM OE Reserved OF Reserved 10 CCEN 1 0 Reserved CCLN 4 0 11 CCODO 7 0 12 CCOD 1 7 0 13 CCEDO 7 0 14 CCED1 7 0 15 Reserved CCSTAT 1 0 16 CGMSEN Reserved WD01 5 0 17 WD02 7 0 18 CRCON Reserved CRCDATA 5 0 19 GP12 7 0 1A WSSEN Reserved GP34 5 0 1B to Reserved 3F Reserved Reserved for the system Do not use these registers 192. OKT Oki Network Solutions for a Global Society PEDL7655 56 000 MLS6V7655 56 Preliminary NTSC PAL Compatible 6ch DAC Equipped Digital Video Encoder with Format Conversion Function GENERAL DESCRIPTION The ML86V7655 is an NTSC PAL compatible digital video encode It encodes digital image data such as ITU R BT 656 and ITU R BT 601 to analog video signals As digital input RGB 4 4 4 YCbCr 4 4 4 and progressive scan signals are supported besides generic ITU R BT 601 and ITU R BT 656 As analog video output RGB and component signals can be output in interlace or progressive format in addition to NTSC PAL S Video and composite outputs DAC simultaneous 6 channel output or independent output for each channel can be selected With the I P and P I conversion function interlaced digital signals can be output as progressive signals or progressive digital signals can be output as interlaced signals The ML86V7656 supports Macrovision copy protection compliant with version 7 1 L1 for interlace and version 1 2 for progressive FEATURES Supported video type NTSC PAL Scanning method Interlace Progressive Single field signals Input data format ITU R BT 656 4 type Y CbCr 4 2 2 10 bit multiplexing synchronization signal information added ITU R BT 601 Y CbCr 4 2 2 20 bit non multiplexing Y CbCr 4 1 1 20 bit non multiplexing Y CbCr 4 2 2 10 bit multiplexing without synchronization signal YCbCr 4 2 2 20 bit non multiplexing progr
3. QN5v so QdAv ON SA QN5v ON ON TANDO 75 DGND1 74 STANDBY 73 OLC 72 OLR 71 OLG 70 OLB 69 OCSYNC OHSYNC 68 OVSYNC 67 DGND2 66 DVDD2 65 BDO 64 BD1 63 BD2 62 BD3 61 BD4 60 BD5 59 BD6 58 BD7 57 BD8 56 BD9 55 TEST5 54 CDO 53 CD1 52 cp2 51 DVDD2 pz LL 9L 64 08 18 c8 E8 vs G8 98 L8 88 68 bs O O OS 6v 8v LV 9v Sv v ev lv Or 6 8 LE 9E IGE tE EE ce TE DE 6c 8z O LZ 9c NC DVDD1 2 SDA 3 SCL 4 SLA 5 MS DGND2 7 DVDD2 8 IMODO 9 IMOD1 10 IMOD2 11 IPAL 12 IRGB 13 IPRG 14 1444 15 ORGB 16 OPRG 17 RESET L 118 TESTO 19 TESTI 20 TEST2 21 TEST3 22 TEST4 23 CLKX2 24 DGND2 25 ZANDA Ed va Sd2 9d2 Lq2 sao 602 TANDA 0dA IdA Zd
4. 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 PACKAGE DIMENSIONS Unit mm TQFP100 P 1414 0 50 K 016 0 0 2 014 0 0 1 e 0 22 095 BIG 1065 INDEX MARK 9 Mirror finish y TYP 2MAX 0 17 0 05 TOO OH ST 1270 10 ae NG PLANE Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating gt 5um Package weight g 0 55 TYP Rev No Last Revised 4 Oct 28 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times 20 22 OKI Semiconductor PEDL7655 56 000 ML86V7655 56 REVISION HISTORY Page ary Date Previous Current Description Edition Edition PEDL7655 000 Sep 14 2004 Preliminary edition 1 21 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 NOTICE The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being
5. 3 V I O supplyy 2 5 V core supply SCL and SDA pins only 5 V tolerant e Package 100 pin plastic TQFP TQFP100 P 1414 0 5 K ML86V7655TB ML86V 7656TB 2 22 TTIE 0000 CGMS WSS CC ROJO Contoller L 11bitDAC Y G 0 i Progressive i Interlace n YCbCr RGB YCbCr RGB ME 11bit DAC Cb B YD 9 0 Q Progressive o 9 Input Data E S 3 Progressive o CD 9 0 3 Decoder 9 gol 3 Interlace 2 YCbCr RGB zi BD 9 0 4 8 oe gt lt YCbCr RGB g t1bitDAC Cr R 8 25 ZB YObCr S p Go 3 Y 2 Y a La a Y 11bit DAC YS Progressive YCbCr y TE to 11bit DAC gt wince gt tee YUV ES F i as gt gt FOUT V IPAL OCSYNC OHSYNC LPF IPRG sync generator 2OVSYNC 12C Interface 2 11bit DAC 9 CVBS oaa Timing controller gt OCLKX1 PRG gt VSYNC L Color Burst Subcarrier 9 Z FIS YNGE Generator Generator CLKX2 3 9 CSYNC L nn RESET_L gt BLANK_L g Q 5 NVADVIA MOTA JOJONPUOSIUIIS TYO 9S SS9LA98 TN 000 9S SS9L 11 Hd PEDL7655 56 000 ML86V7655 56 OKI Semiconductor PIN CONFIGURATION TOP VIEW TAAA 1N04 ON QN5v O A QdAv g q5 aNDV Y O QdAv QN5v J3uAX Sd dNOD QdAv SAD
6. COMP O Internal reference voltage output pin 90 AVDD Analog power supply 91 CVBS O Composite signal output pin 92 AGND Analog GND 93 CS O Separate C signal output pin 94 AVDD Analog power supply 95 NC No connection 96 YS O Separate Y signal output pin 97 AGND Analog GND 98 NC No connection 99 NC No connection 100 DGND1 1 0 GND 7 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power supply voltage I O VDD1 Ta 25 C 0 3 V to 4 6 V V Power supply voltage Core VDD2 Ta 25 C 0 3 V to 43 6 V V Power supply voltage Analog AVDD Ta 25 C 0 3 V to 4 6 V V Input voltage Vi Ta 25 C 0 3 V to 6 0 V V Output short circuit current los 50 mA Power dissipation Pp Ta 25 C 1 Ww Storage temperature Tstg 55 to 150 C Caution Product quality may suffer if any of the absolute maximum ratings above is exceeded even for an instant That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage Therefore the product must be used under conditions that ensure that no absolute maximum rating will ever be exceeded RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power supply voltage I O VDD1 3 0 3 3 3 6 V Power supply voltage Core VDD2 2 25 2 5 2 75 V Power supply voltage
7. Format Write data to the specified subaddress register If multiple data items are written in succession the subaddress is incremented automatically for each data item Read format gill Save al Subaddrass A ar SO We LAC RI GR oes Data Aml P address address 0 n Figure 4 Read Format Read data of the register at the specified subaddress If multiple data items are written in succession the subaddress is incremented automatically for each data item Table 1 Symbols Used in the Input Formats Symbol Meaning S Start condition Sr Restart condition Slave address 100 010X Specify X from the SLA pin 1 or 0 Slave address Ww Write R Read A Acknowledge slave Am Acknowledge master Sub address Subaddress Data n Write and read data at subaddress P Stop condition 12 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 INPUT OUTPUT TIMING 1 Input timing VIH CLKX2 VIL tsi tu VIH Input signal VIL Input signal VSYNC_L HSYNC_L BLANK_L IMODO to 3 IPAL IRGB IPRG 1444 ORGB OPRG MS YD CD BD OLC OLR OLG OLB 2 Output timing VIH CLKX2 VIL Top VIH Output signal VIL Output signal VSYNC_L HSYNC_L BLANK L OVSYNC OCSYNC OHSYNC FOUT OCLKXI VSYNC_L HSYNC_L and BLANK_L are configured as output pins in master mode 13 22 PEDL76
8. R BT601 Wide 18 0 36 2 Input data formats for interlaced and progressive scanning Table 3 shows the scanning method interlaced progressive and data type Table 3 Types of Input Data Formats Input data format Scanning method Data type Sampling rategi color ad IR difference Interlaced YCbCr 4 2 2 or 4 1 1 1 YD CD or YD 2 Interlaced YCbCr 4 4 4 YD CD BD Interlaced RGB 4 4 4 YD CD BD Progressive YCbCr 4 2 2 YD CD Progressive YCbCr 4 4 4 YD CD BD Progressive RGB 4 4 4 YD CD BD Change internal register value to select 4 2 2 or 4 1 1 2 Use only the YD pin for video data synchronized information multiplexing input e g ITU R BT 656 Table 4 shows the available scanning methods for NTSC and PAL Table 4 Scanning Methods Scanning method No of lines Frequency NTSC interlaced 262 5 60 Hz NTSC progressive 525 60 Hz PAL interlaced 312 5 50 Hz PAL progressive 625 50 Hz 16 22 OKI Semiconductor 3 Video data synchronization information multiplexing input format types PEDL7655 56 000 ML86V7655 56 The ML86V7655 56 support the video data synchronization information multiplexing input interfaces and data multiplexing no multiplexing for sync signals input interfaces shown in Table 5 Table 5 Types of Multiplexed Input Interfaces Input CLKX2 f Input interface frequency MHz Data in
9. input pin color difference Cb B signal bit 2 64 BD1 lO Video signal input pin color difference Cb B signal bit 1 65 BDO lO Video signal input pin color difference Cb B signal bit 0 66 DVDD2 Core digital power supply 2 5 V 67 DGND2 Core digital GND 68 OVSYNC O Component vertical sync signal output OCSYNC Composite synchronization signal output Component horizontal 69 OHSYNC O synchronization signal output Select either output with the internal register OCHSEL 70 OLB l Overlay text color blue input pin 71 OLG l Overlay text color green input pin 72 OLR l Overlay text color red input pin 73 OLG Transparency control When set to 1 an overlay signal is displayed Connect this pin to GND if it is not used 74 STANDBY Standby enable input pin 1 Standby 0 Normal operation 6 22 OKI Semiconductor PIN FUNCTION continued PEDL7655 56 000 ML86V7655 56 Pin Symbol Type Description 75 DGND1 1 0 GND 76 DVDD1 I O power supply 3 3 V 77 FOUT O Field information signal output pin 78 NC No connection 79 AGND Analog GND 80 Y G O Y G output pin 81 AVDD Analog power supply 82 Cb B O Cb B output pin 83 AGND Analog GND 84 Cr R O Cr B output pin 85 AVDD Analog power supply 86 AGND Analog GND 87 XVREF l O Reference voltage input pin 88 FS l Video output full scale adjustment pin 89
10. l Test mode control 2 Tie this pin to GND 22 TEST3 l Test mode control 3 Tie this pin to GND 23 TEST4 l Test mode control 4 Tie this pin to GND 24 CLKX2 l System clock input pin 25 DGND2 Core digital GND 26 DVDD2 Core digital power supply 2 5 V CLKX1 output pin a Paga 9 Outputs 1 2 divided frequency of CLKX2 Vertical sync signal input output pin fe vere e When in master mode output when in slave mode input Horizontal sync signal input output pin di HEXNE E ue When in master mode output when in slave mode input BLANK signal input output pin m BENE v When in master mode output when in slave mode input 31 YD9 Video signal input pin Brightness Y G signal bit 9 32 YD8 Video signal input pin Brightness Y G signal bit 8 33 YD7 Video signal input pin Brightness Y G signal bit 7 5 22 OKI Semiconductor PIN FUNCTION continued PEDL7655 56 000 ML86V7655 56 Pin Symbol Type Description 34 DVDD1 I O power supply 3 3 V 35 YD6 l Video signal input pin brightness Y G signal bit 6 36 YD5 l Video signal input pin brightness Y G signal bit 5 37 YD4 l Video signal input pin brightness Y G signal bit 4 38 YD3 l Video signal input pin brightness Y G signal bit 3 39 YD2 l Video signal input pin brightness Y G signal bit 2 40 YD1 l Video signal input pin brightness Y
11. 55 56 000 OKI Semiconductor ML86V7655 56 DESCRIPTION OF FUNCTIONAL BLOCKS This section describes the functions of the blocks shown in the Block Diagram For a detailed explanation of all the functions refer to the User s Manual 1 2 3 4 5 6 7 8 9 10 Input Data Decoder Converts the video data format based on the format of the digitally input video data ITU BT 656 20 bit 4 2 2 YCbCr and 10 bit 4 2 2 YCbCr input data are converted to 4 4 4 YCbCr data When ITU BT 656 is input the synchronization information is separated from the SAV and EAV information to generate a synchronization signal RGB input data is output to the next block The input video signal limiter function clips the input video signal at the quantization level 64 940 specified by ITU R BT601 In the extended luminance range mode the limiter function clips the input video signal at the quantization level 4 1016 Overlay amp Color Bar Controller A 3 bit title graphic and color bar are generated The 3 bit title graphic becomes effective when the OLC pin is set to H The RGB graphic data input from the OLR OLG and OLB pins can be replaced with input video data in pixel units The input video data supports YCbCr input RGB input interlaced input and progressive input With this function letters can be displayed on the screen as with the OSD function The built in color bar becomes effective by setting the interna
12. A dA vaa SaA 9dA Taqad LAA 8dA 60A 1 VNT18 1 9NASH T 9NASA TXy190 zaa d 100 Pin Plastic TQFP 4 22 OKI Semiconductor PEDL7655 56 000 ML86V7655 56 PIN FUNCTION Pin Symbol Type Description 1 NC No connection 2 DVDD1 I O power supply 3 3 V 3 SDA 1 0 Data pin for I C bus 5 V tolerant pin 4 SCL l Data pin for I C bus 5 V tolerant pin 5 SLA C bus slave address least significant bit specification pin 6 MS Master slave select pin 1 Master mode 0 Slave mode T DGND2 Core digital power supply 2 5 V 8 DVDD2 Core digital power supply 2 5 V 9 IMODO Input mode 0 control pin 10 IMOD1 Input mode 1 control pin 11 IMOD2 Input mode 2 control pin PAL NTSC mode select pin ie eg 1 PAL 0 NTSC RGB YCbCr input select pin i RE 1 RGB input 0 YcbCr input 14 IPRG Progressive interlaced input select pin 1 Progressive input 0 Interlaced input 4 2 2 4 4 4 select pin is Ad 1 4 4 4 input 0 4 2 2 input RGB YCbCr output select pin 16 oH 1 RGB output 0 YcbCr output 17 OPRG Progressive outhuvinteraced output select pin 1 Progressive output 0 Interlaced output 18 RESET_L l System reset pin Reset at a L level 19 TESTO l Test mode control 0 Tie this pin to GND 20 TEST1 l Test mode control 1 Tie this pin to GND 21 TEST2
13. Analog AVDD 3 0 3 3 3 6 V Operating temperature Ta 40 85 C External reference voltage Vretex 1 23 V D A output setting resistance Riadj 500 1000 1330 D A output load resistance Ri 300 Q 8 22 OKI Semiconductor ELECTRICAL CHARACTERISTICS DC Characteristics 1 PEDL7655 56 000 ML86V7655 56 Ta 40 to 85 C DVDD1 3 3 V 0 3 V VDD2 2 5 0 25 V AVDD 3 3 V 0 3 V DGND1 DGND2 AGND 0 V Parameter Symbol Condition Min Typ Max Unit ae VDD1 H level input voltage 1 Vin 2 2 0 3V V H level input voltage 2 Vino 2 2 5 5 V L level input voltage Vi 0 3 0 8 V Voltage at Schmitt trigger threshold value vr d Y Voltage at Schmitt trigger threshold value bia OF X Voltage at Schmitt trigger Vu 0 4 hysteresis value H level output voltage Vou lous 4 mA 2 4 V L level output voltage Vor lo 4mA 0 4 V Input leakage current lu Vin VDD1 or GND1 10 10 uA H level input current pull down lia Vin VDD1 20 250 uA resistance Output leakage current llo Vour VDD1 or GND1 10 10 uA Power supply current during i CLKX2 36 MHz 160 mA operation D RL 3000 Power supply current when loosi CLKX2 0 MHz Viv Vi a 45 mA stopped 1 Power supply current when CLKX2 0 MHz Vn ViL Y 5 SUA stopped 2 DDS STANDBY Vin 1 V
14. G signal bit 1 41 YDO l Video signal input pin brightness Y G signal bit 0 42 DGND1 1 0 GND 43 CD9 l Video signal input pin color difference C Cr R signal bit 9 44 CD8 l Video signal input pin color difference C Cr R signal bit 8 45 CD7 l Video signal input pin color difference C Cr R signal bit 7 46 CD6 l Video signal input pin color difference C Cr R signal bit 6 47 CD5 l Video signal input pin color difference C Cr R signal bit 5 48 CD4 l Video signal input pin color difference C Cr R signal bit 4 49 CD3 l Video signal input pin color difference C Cr R signal bit 3 50 DGND2 Core digital GND 51 DVDD2 Core digital power supply 2 5 V 52 CD2 l Video signal input pin color difference C Cr R signal bit 2 53 CD1 l Video signal input pin color difference C Cr R signal bit 1 54 CDO l Video signal input pin color difference C Cr R signal bit 0 55 TEST5 I O Test pin Tie this pin to GND 56 BD9 lO Video signal input pin color difference Cb B signal bit 9 57 BD8 lO Video signal input pin color difference Cb B signal bit 8 58 BD7 lO Video signal input pin color difference Cb B signal bit 7 59 BD6 lO Video signal input pin color difference Cb B signal bit 6 60 BD5 lO Video signal input pin color difference Cb B signal bit 5 61 BD4 lO Video signal input pin color difference Cb B signal bit 4 62 BD3 lO Video signal input pin color difference Cb B signal bit 3 63 BD2 lO Video signal
15. IH2 is applied to the SDA and SCL pins only Note The power supply current does not include the current consumption of the output buffer no load DC Characteristics 2 Ta 40 to 85 C DVDD1 3 3 V 0 3 V VDD2 2 5 0 25 V AVDD 3 3 V 0 3 V DGND1 DGND2 AGND 0 V Parameter Symbol Condition Min Typ Max Unit DAC internal reference voltage Vrerin mE 1 187 1 23 1 313 V DAC integral linearity SINL 4 LSB DAC differential linearity SDNL 2 LSB 9 22 OKI Semiconductor AC Characteristics PEDL7655 56 000 ML86V7655 56 Ta 40 to 85 C DVDD1 3 3 V 0 3 V VDD2 2 5 0 25 V AVDD 3 3 V 0 3 V DGND1 DGND2 AGND 0 V Parameter Symbol Condition Min Typ Max Unit Clock frequency NTSC square pixel 24 545454 MHz CLKX2 frequency PAL square pixel 29 5 MHz E NTSC 4Fsc 28 636364 MHz NTSC PAL ITU R BT601 27 MHz NTSC PAL ITU R BT601 36 E MHz wide Clock duty ratio dtcik 45 55 96 Input data setup time tsi 6 ns Input data hold time tui 5 ns Output delay time top C 20 pF 18 ns Reset pulse time tRsTP 100 ns 12C clock cycle time teczce Rpull up 4 7 KQ 10 us IC clock H level time tHizc Rpull up 4 7 KQ 4 us FC clock L level time tuzc Rpull up 4 7 KQ 4 7 us C dat
16. OKI Semiconductor ML86V7655 56 VIDEO DATA OUTPUT CONTROL Video signals composite signals separate video signals and component YCbCr RGB signals can be simultaneously output from the 6 channel D A converter Composite signals are output from the CVBS pin and separate video signals are output from the YA and CS pins YCbCr or RGB signals are exclusively output from the Y G Cb B and Cr R pins For each input data scanning method conversion from interlaced to progressive and from progressive to interlaced is possible Color space conversion such as YCbCr gt RGB and RGB YcbCr is also possible Table 6 shows the available output formats for each input format For example 4 2 2 YCbCr progressive video data can be simultaneously output in three different video formats composite S Video and YCbCr interlaced Table 6 Correspondence of Input Formats and Output Formats Output format Input format YCbCr YCbCr RGB RGB Composite S Video interlaced progressive interlaced progressive 4 2 2 4 1 1 YCbOr 4 4 4 YCbCr interlaced 4 2 2 YCbCr progressive 4 4 4 YCbCr progressive RGB interlaced O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O RGB progressive O Output enabled Table 7 shows the output pins from which video data is output Change the internal register values to enable disable D A converter output for each channel
17. a setup time tosizc Rpull up 4 7 KQ 250 ns C data hold time tonic Rpull up 4 7 KQ 0 3 45 us 10 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 POWER ON SEQUENCE Turn on the power supplies in the following order DVDD1 gt AVDD gt DVDD2 Turn them off in the reverse order After every power supply reaches its specified voltage and the clock CLKX2 is stabilized input the reset signal RESET INPUT TIMING Input the reset signal for the reset pulse time tgsrp RESET_L tRSTP R Figure 1 Reset Signal Input Timing 11 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 PC INTERFACE TIMING Use the I C interface to set the internal register values The I C interface is compliant with the 100 kHz SCL frequency standard mode Figure 2 shows the basic timing Make sure that the SDA value does not change while SCL is at a H level For information on timing parameter values refer to the AC characteristics soL A MAA rl StatCondton Y LY W L1 d Ly IDSI2C onec coic 1120 120 Figure 2 I C Interface Basic Timing dog m SDA MSB 1 EA PA pla f 9 poke 2 Pol P ack Stop Condition Figures 3 and 4 show the I C interface input format Write format S alaye W A Subaddress A Datao A na Datan A P address Figure 3 Write
18. essive YCbCr 4 4 4 30 bit 24 bit non multiplexing interlaced progressive RGB 4 4 4 30 bit 24 bit non multiplexing interlaced progressive Input pixel frequency Input double speed clock frequency 12 272727 MHz 24 545454 MHz NTSC Square Pixel 13 5 MHz 27 MHz NTSC PAL ITU R BT 601 14 318182 MHz 28 636364 MHz NTSC 4fsc 14 75 MHz 29 5 MHz PAL Square Pixel 18 MHz 36 MHz NTSC PAL ITU R BT 601 wide e Output format Composite CVBS S Video Y C separate signals RGB Interlace Progressive YCbCr component Interlace Progressive Scan type conversion function Color space conversion function Interlace to Progressive Progressive to Interlace YCbCr to RGB RGB to YCbCr Built in 6ch 11 bit DAC Capable of simultaneous output of composite S video YCbCr or RGB e Output load resistance 300Q A video amp is required when a TV monitor is connected e Master Slave operation Slave only for ITU R BT 656 mode e Color bar output e 3 bit title graphic input interface Luminance adjustment RGB gain adjustment e Expanded luminance range mode Synchronization signal level adjustment e CGMS WSS information adding function Closed caption information adding function 1 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 e Supports Macrovision copyguard function only available in the ML86V7656 Conforms to version 7 1 L1 for interlace Conforms to version 1 2 for progressive 2C bus type serial interface Supply voltage 3
19. l register value The color bar is a color bar with a luminance order 25 50 75 and 100 It supports NTSC PAL and YCbCr RGB CVBS S Video interlaced and progressive Progressive to Interlace Converts progressive video data YCbCr RGB to interlaced video data Progressive video data to be input supports YCbCr 4 2 2 and 4 4 4 and RGB Interlace to Progressive Converts interlaced video data YCbCr RGB to progressive video data RGB to YCbCr YCbCr to RGB Converts RGB YCbCr data to YCbCr RGB data Y RGB Level Adjustment This block adjusts the levels of the luminance signal Y RGB data The luminance signal level can be adjusted in 16 steps 78 125 to 125 in increments of 3 125 by setting the internal register value RGB data gain can be set from 0 0 to 2 0 times by setting the internal register value A different setting can be made for each channel of R G and B YCbCr to YUV Converts YCbCr data to YUV data Sync Controller This block adds a synchronization signal to the video signal adds VBI data and adjusts the synchronization signal level and offset of the signal CGMS WSS CC Controller This block generates data of CGMS A Copy Generation Management System Analog WSS Wide Screen Signaling and CC Closed Caption LPF Removes high frequency components from video data 14 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 11 Color Burst amp Subcarrier Generator These blocks generate the ampli
20. put pin NTSC ITU R BT656 style 1 27 YD PAL ITU R BT656 style 1 27 YD NTSC 4 2 2 10 bit multiplexing no multiplexing for sync 27 YD signals 2 NTSC Square F xel 4 2 2 10 bit multiplexing no multiplexing 24 545454 YD for sync signals 2 NTSC ASG 4 2 2 10 bit multiplexing no multiplexing for sync 28 63634 YD signals 2 PAL 4 2 2 10 bit multiplexing no multiplexing for sync E 27 YD signals 2 PAL Square Pixel 4 2 2 10 bit multiplexing no multiplexing 29 5 YD for sync signals 2 NTSC Square Pixel ITU R BT656 style 3 24 545454 YD PAL Square Pixel ITU R BT656 style 3 28 63634 YD NTSC 4FSC ITU R BT656 style 3 29 5 YD ITU R BT656 style input interface For details refer to Video Interface Timing in the User s Manual 2 4 2 2 10 bit multiplexing no multiplexing for sync signals interface This interface multiplexes YCbCr and inputs the data from the YD pin Input the synchronization signal from the VSYNC L HSYNC_L and BLANK L pins For details refer to the Input Data Format and Video Interface Timing sections in the User s Manual 3 ITU R BT656 style input interface for SquarePixel and 4FSC This interface multiplexes video data and synchronization information and inputs the data from the YD pin Synchronization information is multiplexed as SAV and EAV For details refer to the Video Interface Timing section in the User s Manual 17 22 PEDL7655 56 000
21. quipment measurement equipment consumer electronics etc These products are not unless specifically authorized by Oki authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2004 Oki Electric Industry Co Ltd 22 22
22. referred to is up to date The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication e
23. tude of the U and V components of a burst signal and generate an color subcarrier 12 11 bit DAC Converts digital video signals with 11 bit resolution to analog video signals and outputs them The DAC output is of the current drive type Connect an external load resistor 300Q to the analog output pin Connect a video amplifier to the output stage of the encoder to drive a 75 Q load 13 Sync Generator amp Timing Controller This block generates video synchronization signals and controls the timing of internal operations A slave mode and a master mode are available In the slave mode operation is based on synchronization signals input from outside In the master mode operation is based on synchronization signals generated within the LSI 14 I2C Interface I C bus serial interface Used to set operation modes and internal register values 15 22 PEDL7655 56 000 OKI Semiconductor ML86V7655 56 VIDEO DATA INPUT CONTROL 1 Types of input video pixel frequencies The ML86V7655 56 support the pixel frequencies for input video shown in Table 2 Every pixel frequency can be selected Note The input clock frequency should be double the pixel frequency Table 2 Types of Input Pixel Frequencies Pixel frequency MHz iS NTSC ITU R BT601 13 5 27 PAL ITU R BT601 13 5 27 NTSC Square Pixel 12 272727 24 545454 NTSC 4Fsc 14 318182 28 63634 PAL Square Pixel 14 75 29 5 NTSC ITU R BT601 Wide 18 0 36 PAL ITU
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