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20EM09-00 E4 User Manual - Diamond Point International

1. 33 Pin assignment of 9 pin D Sub COM1 LAN3 plug connector EM9 34 Pin assignment of onboard I O connector J3 EM9A 35 Signal mnemonics of onboard I O connector J3 EM9A 35 Pin assignment of I O connector J2 general pinout 37 Signal mnemonics of I O connector J2 general pinout 38 Pin assignment of I O connector J2 factory standard FPGA COMMPUTAU ON serron ies ee 0 59 93S EIN DESI xu geet I Charitas 39 Signal mnemonics of I O connector J2 factory standard FPGA COMMPUTAUON sesoonse wes Sao reta dip Sessa idus 40 Pinassionment ot PCI JL sede absentee a o iod nama 43 FPGA Factory standard configuration table for ESM 45 MENMON Program update files and locations 51 MENMON Diagnostic tests Ethernet 54 MENMON Diagnostic tests SDRAM and FRAM 35 MENMON Diagnostic tests FPGA ee 56 MENMON Diagnostic tests EEPROM 000 5 56 MENMON Diagnostic tests IDE NAND Flash I MENMON Diagnostic tests COMI COM2 57 MENMON Diagnostic tests touch eese 58 MENMON Diagnostic tests RTC 2 ee eee 58 MENMON System parameters for console selection and configuratlol i vens ar enaar redes det Cae PRSE ER 59 MENMON Address map full featured mode 61 MENMON Boot Flash memory map 000005 61 MENMON Controller Logical Units CLUNSs nanana
2. con3 00 none none e e Read write ecl CLUN of attached network inter face hex CLUN 0x00 none CLUN O0xFF first available Ether net OxFF Read write gcon CLUN of graphics device to display boot logo CLUN 0x00 disable CLUN 0xFF Autoselect first avail able graphics console OxFF AUTO Read write hdp HTTP server TCP port decimal 0 don t start telnet server 1 use default port 23 else TCP port for telnet server 1 Read write tdp Telnet server TCP port decimal 0 don t start HTTP server 1 use default port 80 else TCP port for HTTP server 1 Read write 4 7 2 Video Modes None of the included drivers allows to change the video mode MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 MENMON 4 7 3 Abort Pin Since the ESM has no real abort button it is simulated by connecting pin 1 to pin 2 on the debug connector TDI pin of debugger with GND If the abort pin is detected asserted the secondary MENMON is not invoked the fallback FPGA image is loaded MENMON uses default parameters such as baud rate console port deactivates the FPGA watchdog and enters the command line interface This is useful if a secondary MENMON has been programmed that does not work or if you have misconfigured a system parameter Note that when a JTAG debugger is connected the abort pin is always read as active Figure 6 M
3. 3 ole Ss 8 LAN2RX 4 LAN2_RX 9 LANi RX 5 LAN1 RX MEN Mikro Elektronik GmbH 30 20EMO9 00 E4 2010 02 01 Functional Description EMS 5 Pin assignment of 9 pin D Sub Ethernet plug connector LAN3 COM1 EM9 LAN3 TX LAN3 TX 0000 00000 1 2 3 4 LAN3 RX 5 6 7 5 8 9 LAN3 RX Connection via J3 Onboard I O Connector EM9A See Chapter 2 10 I O Connector J3 EM9A on page 35 2 8 2 General Ethernet is a local area network LAN protocol that uses a bus or star topology and supports data transfer rates of 100 Mbits s and more The Ethernet specification served as the basis for the IEEE 802 3 standard which specifies the physical and lower software layers Ethernet is one of the most widely implemented LAN standards Ethernet networks provide high speed data exchange in areas that require economical connection to a local communication medium carrying bursty traffic at high peak data rates A classic Ethernet system consists of a backbone cable and connecting hardware e g transceivers which links the controllers of the individual stations via transceiver transmitter receiver cables to this backbone cable and thus permits communication between the stations 2 8 3 10Base T 10Base T is one of several adaptations of the Ethernet IEEE 802 3 standard for Local Area Networks LANs The 10Base T standard also called Twisted Pair Ethernet uses a twisted
4. FP1 EMO09 001ICO05B1 FP1 FPGA1 FPGA1 code backup FP2 EMO09 001C005A1 FP2 FPGA2 FPGA2 code 66 MHz PCI clock FP3 EMO09 00ICO05A1 FP3 FPGA3 FPGAS code backup Bxx DSKIMG BOO DISK Starting at sector xx in second disk Cxx DSKIMG C00 DISK Starting at sector xx in first disk NAND Flash Dxx MYFILE DOO Starting at 0x200000 xx in SDRAM Exx MYFILE E00 Starting at byte xx in EEPROM Fxxx MYFILE FOOO Starting at sector xxx in boot Flash Flash has 128 sectors with 0x20000 bytes each 4 5 2 Update from Network using NDL You can use the network download command NDL to download the update files from a TFTP server in network The file name extensions locations and passwords are the same as for the SERDL command MEN Mikro Elektronik GmbH 51 20EMO9 00 E4 2010 02 01 MENMON 4 5 3 Update via Program Update Menu The following Program Update Menu is implemented in the ESM MENMON Program Update Menu gt Copy external CF gt internal CF 1 1 Copy external CF IMAGE COO gt internal CF Copy external CF IMAGE FPO gt boot flash FPGA code Copy external CF IMAGE FP1 gt boot flash fallback FPGA code Copy external CF IMAGE SMM gt boot flash sec MENMON Copy ime rnall Cr exuermel Clr ils il internal CF stands for the onboard NAND Flash external CF stands for the first external IDE storage device 4 5 4 Automatic Update Check MENMON s automatic update check l
5. page 22 Table 9 Pin assignment of onboard I O connector J3 EM9A A B C D 16 GND GND GND GND 17 COM1 TXD COM1 RTS COM2 TXD COM2_RTS 18 COM1_RXD COM1_CTS COM2_RXD COM2_CTS 19 GND GND GND GND 20 21 SHIELD SHIELD SHIELD SHIELD 22 L3_MD O L3_MD 2 L3_MD 1 L3_MD 3 23 L3_MD 0 L3_MD 2 L3 MD 1 L3 MD S 24 SHIELD SHIELD SHIELD SHIELD 25 L1 MD O L1 MD 1 L2 MD O L2 MD 1 26 L1 MD O L1 MD 1 L2 MD O L2 MD 1 27 SHIELD SHIELD SHIELD SHIELD 28 L1 MD 2 L1 MD 3 L2 MD 2 L2 MD 3 29 L1 MD 2 L1 MD 3 L2 MD 2 L2 MD 3 30 SHIELD SHIELD SHIELD SHIELD Table 10 Signal mnemonics of onboard I O connector J3 EM9A Signal Direction Function Power GND Digital ground UARTS COMx CTS in COM 1 2 clear to send COM1 COM2 COMx RTS out COM1 2 request to send COMx_RXD in COM1 2 receive data COMx_TXD out COM1 2 transmit data Ethernet Lx_MDJ 3 0 in out Differential pairs of data lines for LAN1 2 3 LAN1 LAN3 MEN Mikro Elektronik GmbH 35 20EMO9 00 E4 2010 02 01 Functional Description 2 11 l O Connector J2 The board features a second 120 pin PCI 104 standard connector that implements additional I O The type of I O depends on the FPGA configuration of the ESM which is very flexible and can contain a number of FPGA IP cores For more information please refer to Chapter 3 FPGA on page 44 To illustrate the possibilities this manual shows the standard factory FPGA configuration t
6. 29 5V SDA PC29 GND 30 SCL 3 3V_STBY PC30 PD30 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Functional Description Table 12 Signal mnemonics of I O connector J2 general pinout Signal Direction Function Power 3 3V 3 3V power supply 3 3V_STBY in Power supply for real time clock 5V 5V power supply GND Digital ground FPGA I O PAxx PDxx in out FPGA general purpose I O lines PC SCL out l2C bus EEPROM spa in out l C bus MEN Mikro Elektronik GmbH 38 20EMO9 00 E4 2010 02 01 Functional Description Table 13 Pin assignment of I O connector J2 factory standard FPGA configuration A B C D 1 IDE_RST SCLK 5V BLUE 2 2 GND SDI RXD10 45V 3 IDE D7 GND RTS10 BLUE 3 4 IDE D6 IDE D8 GND BLUE 4 5 3 3V IDE D9 CTS104 GND 6 IDE D5 43 3V TXD12 BLUE 5 7 IDE_D4 IDE_D10 43 3V GREEN O 8 GND IDE D11 RXD12 43 3V 9 IDE D3 GND RTS124 GREEN 1 10 IDE D2 IDE D12 GND GREEN 2 11 45V IDE D13 CTS12 GND 12 BEEN 45V TXD11 GREEN 3 13 IDE DO IDE D14 45V GREEN 4 14 GND IDE D15 RXD11 45V 15 IDE DRQ GND GPIO 0 3 GREEN 5 16 IDE WR SDO GND RED O 17 43 3V SCS GPIO_0 4 GND 18 IDE RD amp 33V GPIO 05 RED 1 19 IDE RDY IDE EN amp 43 3V RED 2 20 GND PENIRQ COM10_SW 43 3V 21 IDE DAK amp GND IDE R W amp RED 3 22 IDE IRQ GPIO 0 0 GND RED 4 23 45V PWR FAIL PBRST GND 24 IDE A1 45V GPIO 0 6 RED 5 25 IDE
7. 3 000m Shock 15g 11ms Bump 10g 16ms Vibration sinusoidal 1g 10 150Hz Conformal coating on request MTBF 245 671h 40 C according to IEC TR 62380 RDF 2000 Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manu facturers EMC Tested according to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst BIOS MENMON Software Support Linux VxWorks QNX on request INTEGRITY OG Green Hills Software on request OS 9 on request F e For more information on supported operating system versions and drivers see online data sheet MEN Mikro Elektronik GmbH 8 NE ee NE Block Diagram Block Diagram EM9 System a SDRAM DDR2 ee gt Front panel connector Supervisor B Onboard connector PowerPC Opti 10 MPC8548 or Ethemet NEU MRCS349 10 100 1000Base T Ethemet 10 100 1000Base T 1 i A Only with EH i Ethernet bana F gt MPC8548 Hor oo 1000Base Tj S versions 1 P 4 MOLIL COM2 1 T w Watchdog Additional SDRAM DDR2 Carrier Board PCI 104 J1 E V0 J2 MEN Mikro Elektronik GmbH 9 20EM09 00 E4 2010 02 01 Block Diagram PowerPC BE MPC8548 or MPC8543 Ethemet 10 100 1000Base T Ethemet 10 100 1000Base T RS232 COM2 Additional SDRAM DDR2 Td Carrier Board PCI 104 J1 E vo J2 MEN Mikro Elektronik GmbH
8. LANI 0x 00 CO 3A 62 xx xx LAN2 0x 00 CO 3A 63 xx xx LAN3 0x 00 CO 3A 64 xx xx where 00 CO 3A is the MEN vendor code 62 63 and 64 are the MEN channel related codes and xx xx is the hexadecimal serial number of the product which depends on your board e g 00 2A for serial number 000042 EM9A LANI 0x 00 CO 3A 9E 1x xx LAN2 0x 00 CO 3A 9E 2x xx LAN3 0x 00 CO 3A 9E 3x xx where 00 CO 3A is the MEN vendor code and 9E 1 9E 2 and 9E 3 are the MEN channel related codes and x xx is the hexadecimal serial number of the product which depends on your board e g 0 2A for serial number 000042 See also Chapter 6 2 Finding out the Board s Article Number Revision and Serial Number on page 75 2 8 1 Connection On EMO three standard RJA5 connectors or two D Sub connectors are available at the front panel for connection to network environments Two status LEDs for each connector are accommodated on the bottom side of the PCB right next to the connectors so as to be visible at the front EM9A has no front connectors The Ethernet signals are available on the J3 I O connector The pin assignments correspond to the Ethernet specification IEEE802 3 Table 2 Signal mnemonics of Ethernet interface Signal Direction Function BI_Dx in out Differential pairs of data lines for 1000Base T RX in Differential pair of receive data lines for 10 100Base T TX
9. Set to name of first Yes Read only selected console cpu CPU type as ASCII string e g Yes Read only MPC8548E cpuclkhz CPU core clock frequency decimal Hz Yes Read only dlun MENMON device unit number that Yes Read only MENMON used as the boot device hexadecimal flashO Flash size decimal kilobytes Yes Read only framo FRAM size decimal kilobytes Yes Read only immr Physical address of CCSR register Yes Read only block memo RAM size decimal kilobytes Yes Read only mem1 Size of SRAM decimal kilobytes Yes Read only MEN Mikro ElektronikGmbH 2822 UT s 63 20EMO9 00 E4 2010 02 01 MENMON Parameter T Parameter User alias Description Standard Default String Access memclkhz Memory clock frequency decimal Hz Yes Read only mm Info whether primary or secondary Yes Read only MENMON has been used for booting either smm or pmm mmst Status of diagnostic tests as a string Yes Read only nmac0 1 2 MAC address of Ethernet interface x Yes Read only 0 n Format e g 00112233445566 Set automatically according to serial number of the board pciclkhz PCI bus clock frequency system input Yes Read only clock decimal Hz rststat Reset status code as a string see Yes Read only Chapter 4 7 6 4 Reset Cause Param eter rststat on page 68 If implemented Table 32 MENMON ESM system parameters Production data Parameter eg Paramete
10. 2 9 9 _1OBASET oes se RSS AR RR ER Ads 31 284A MOOR ASG T oic cabs 191515 009 1409 hn ins Uii dtd al 2 8 59 1000BaseT ans aaa er saneren Cad Sees os 32 229 UART MENCE S earma rE dabo thode Ae nantes 33 2 10 VO Connector J3 EM9A soan Rr rhe 35 20b VO Connector 2 ries verroeste se RUNS 36 2 12 POI T04 Interface detoneren then ebde 42 3 BGA Cc 44 Sob Genital Said eire ette oren enten hea NAS 44 3 2 Standard Factory FPGA Configuration ven enen 45 3 2 IP COMES ase CERIS Ime ab nas 9o Spit or dens kee 45 3 2 2 FPGA Configuration Table nnn ome boten ent bed 45 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Contents 4 MENMON sauer RO 5 oseee 6 eueenneeusceye ened eR EROR ent ERES 46 AT General 2m mns ORE RO HR CDM de 46 4 0 State Diadora s ueni qol e hod art Ag d d ics 47 4 2 Interacting with MENMON 4 5 52 sen aaa ond peds 49 4 2 1 Entering the Setup Menu Command Line 49 4 3 Configuring MENMON for Automatic Boot 50 44 Calibrating the Touch Screen sorore vereen CREE 50 4 5 Updating Boot Flash NAND Flash SDRAM and EEPROM 51 4 5 1 Update via the Serial Console using SERDL 51 4 5 2 Update from Network using NDL 51 4 5 3 Update via Program Update Menu llus 52 4 5 4 Automatic Update Check ee 52 4 5 5 Updating MENMON Code 53 4 6 Diagnostic TESS sessi mb eere dore er eder Rd ss 54 Tl
11. Bermnetonsozatvhsu ona vp oad os REDE RCC A I E aed 54 402 SDRAM and PRAM aanmanen ee diets 55 405 FPGA 51 xwbev tuis SPP ease se wise D p 56 4 04 EEPROM e RR Re RR re REIR RES 56 465 TDBE INAND EIBS ins v 9 DbRECHEDE I DEB bs a7 460 COMVCOM2 iau drei og dto dre ode ain athena 57 qo NOUCK b20 042 d902342bendetyooodalernendlereonhas 58 460 RLC EET 58 4 7 MENMON Configuration and Organization 59 Gil CONSOLE esting PP 59 4 1 2 Video MOd6S s eek RR REOR eR IRR RETE 59 dA ADO BIOS SS des Lb ert RUE Eee odd ees 60 4 7 4 MENMON Memory Map iseseeeeee cece enen 61 4 7 5 MENMON BIOS Logical Units 62 4 720 System Parameters eten va rer Hebr per RE ES 63 4 8 MENMON Commands 0 0 00 cee ees 69 5 Organization of the Board snersersmervsre ren 71 2 4 Memory MappIDES 4a 5i cres deed EROS URS REG ERA TERCER RACER 71 5 2 Interrupt Handling 22s ose Ree RR dda e 72 3 9 OMB DEVICES elen zebra prPieerqenmuvta teli Idee ee oe bus 73 4 PCI Devicesion BUSO 4 uet qoe t mene Ia ep mars 73 6 Appendix i s a p rh pr PERPE ERE ET ET 74 6 1 Literature and Web Resources oa sn ise pre PUE ES Res 74 6 ll PowerPC anna esmee sine eae oaths n SR SUR ERE 74 OAD IBCDIOR arretieren 74 0 13 CBiherneboezo duoc scar n edo utu odo en deep eng a 74 E DET ET 74 MEN Mikro Elektronik GmbH 18 20EMO9 00 E4 2010 02 01 Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 MEN Mikro Elek
12. Connection between touch controller and touch panel 4 6 8 RTC Table 25 MENMON Diagnostic tests RTC Test Name Description Availability RTC Quick presence test of RTC Always Groups POST AUTO RTC X Extended test of RTC Always Groups NONAUTO ENDLESS 4 6 8 1 RTC Test This is a quick presence test of the real time clock RTC and is executed on POST Checks Presence of RTC I2C access Does not check If RTC is running RTC backup voltage 4 6 8 2 Extended RTC Test Checks Presence e g PC access RTC is running Does not check RTC backup voltage MEN Mikro Elektronik GmbH 58 20EMO9 00 E4 2010 02 01 4 7 4 7 1 Consoles MENMON Configuration and Organization MENMON You can select the active consoles by means of system parameters con0 con3 and configure the console through parameters ecl gcon hdp and tdp MENMON commands CONS xxx also give access to the console settings see Chapter 4 8 MENMON Commands page 69 Table 26 MENMON System parameters for console selection and configuration Parameter alias Description Default User Access cbr baud Baud rate of all UART consoles decimal default 9600 baud 8n1 9600 Read write cono con3 CLUN of console 0 3 CLUN 0x00 disable CLUN 0xFF autoselect next avail able console con0 is implicitly the debug console cond 08 COM1 cont 0A Touch con2 00
13. and the system library which are also IP cores Figure 3 FPGA Block diagram exemplary PCI bus Config i EE Table 4 i Table A configuration table provides the information which modules are implemented in the current configuration Furthermore the revision the instance number one module can be instantiated more than one time the interrupt routing and the base address of the module are stored At initialization time the CPU has to read the configuration table to get the information of the base addresses of the included modules Note that with regard to the FPGA resources such as available logic elements or pins it is not possible to grant all possible combinations of the FPGA IP cores The following chapter describes one possible configuration of the FPGA Please ask our sales staff for other configurations TA You can find an overview and descriptions of all available FPGA IP cores on MEN s website MEN Mikro Elektronik GmbH 44 20EM09 00 E4 2010 02 01 FPGA 3 2 Standard Factory FPGA Configuration 3 2 1 IP Cores The factory FPGA configuration for standard boards comprises the following FPGA IP cores Main bus interface e 16Z024 01_Chameleon Chameleon V2 table 1672069 RST Reset controller 1672052 GIRQ Interrupt controller 162070 IDEDISK IDE controller for NAND Flash 162043 SDRAM Additional SDRAM controller 32 MB DDR2 8 MB used as NAND Flash main memory 8 MB used
14. depending on the ESM functionality and carrier board The standard carrier board tests are TOUCH IDE COM_CB 4 6 1 Ethernet Table 18 MENMON Diagnostic tests Ethernet Test Name Description Availability ETHERO Ethernet 0 1 2 LAN1 2 3 internal Always ETHER1 loopback test except ETHER with an ETHER2 Groups POST AUTO MPC8543 processor ETHERO X Ethernet 0 1 2 LAN1 2 3 external Always ETHER1 X oopback test except ETHER with an ETHER2 X Groups NONAUTO ENDLESS MPC8543 processor 4 6 1 1 Ethernet Internal Loopback Test The test configures the network interface for loopback mode on PHY verifies that the interface s ROM has a good checksum verifies that the MAC address is valid not OXFFFFFF sends 10 frames with 0x400 bytes payload each verifies that frames are correctly received on the same interface If the network interface to test is the currently activated interface for the MENMON network stack the interface is detached from the network stack during test and reactivated after test Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Does not check Connection between PHY and physical connector nterrupt line e All LAN speeds MEN Mikro Elektronik GmbH 54 20EMO9 00 E4 2010 02 01 MENMON 4 6 1 2 Ethernet External Loopback Test This test is the same as the Ethernet Internal Loopback Test but requires
15. device unit number deci 0 No Read write mal MEN Mikro Elektronik GmbH 67 20EMO9 00 E4 2010 02 01 MENMON 4 7 6 4 Reset Cause Parameter rststat The following rststat values are possible When MENMON starts up it determines the reset cause and sets system parameter rststat accordingly Table 35 MENMON Reset causes through system parameter rststat rststat Value Description hrst Board was reset due to activation of HRESET line pwon Power On pdrop Power error swrst Board was reset by software by means of the board s reset con troller wdog Board was reset by FPGA watchdog time out reset controller rbut Board was reset by an external reset pin e g reset button MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 MENMON 4 8 MENMON Commands The following table gives all MENMON commands that can be entered on the ESM MENMON prompt You can fork up this list also using the H command A green background marks commands different to the global specification Table 36 MENMON Command reference Command Description lt reg gt lt val gt Display modify registers in debugger model ACT lt addr gt lt size gt Execute a HWACT script ARP Dump network stack ARP table B DC lt no gt lt addr gt Set display clear breakpoints BIOS_DBG masks net cons Set MEN
16. firmware BIOS can be used for bootstrapping operating systems from disk Flash or network for hardware testing or for debugging applications without running any operating system The EMO EMOA is a communication engine ideal for use in embedded applications for instance as an embedded Linux server but also for high end automation and robot control under a real time operating system For a first evaluation of the functions of the EM9 EM9A we strongly recommend to use the EK9 ESM starter kit The kit consists of the standard EM9 module an FPGA loaded with additional I O functions the carrier card with I O connectors an external PSU cables and an adapter for mounting a PCI 104 module ESM modules consist of the hardware CPU chip set memory I O which is not fixed to any application specific function and an FPGA programmed in VHDL code which provides I O that is also still independent of a specific application ESM modules are based on PCI They have two or three system connectors J1 has a fixed signal assignment while J2 is variable depending on the final application specific configuration of the ESM and the carrier board J2 also feeds the I O signals of the functions programmed in the FPGA to the carrier card Some ESM modules have an additional J3 connector that is used to replace the front I O connectors to route the signals to the carrier board or to the backplane of a CPCI or VME system MEN Mikro Elektronik Gm
17. here Otherwise you may make your board inoperable In any case read the following instructions carefully Please be aware that you do MENMON updates at your own risk After an incorrect update your CPU board may not be able to boot WARNING After a MENMON update the hardware revision displayed by MENMON will most probably be different from the actual hardware revision of your CPU board because MENMON follows MEN s hardware revision updates Do the following to update MENMON Ml Unzip the downloaded file e g 4EM09 00 01 02 zip into a temporary direc tory M Connect a terminal emulation program with the COM 1 port of your ESM and set the terminal emulation program to 9600 baud 8 data bits 1 stop bit no par ity no handshaking if you haven t changed the target baud rate on your own M Power on your ESM and press ESC immediately Ml In your terminal emulation program you should see the MenMon gt prompt M Enter SERDL MENMON to update the secondary MENMON You should now see a C character appear every 3 seconds M In your terminal emulation program start a YModem download of file 14EM09 00 01 02 smm for example with Windows Hyperterm select Trans fer gt Send File with protocol YModem M When the download is completed reset the ESM MEN Mikro Elektronik GmbH 53 20EMO9 00 E4 2010 02 01 MENMON 4 6 Diagnostic Tests Note MENMON may include further tests for COM or other interfaces
18. service marks or product names as designated by the companies who market those products The trademarks and registered trademarks are held by the companies producing them Inquiries concerning such trademarks should be made directly to those companies All other brand or product names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or design MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document Copyright 2010 MEN Mikro Elektronik GmbH All rights reserved D Please recycle Germany France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder Stra e 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Ch telaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 E mail info men de www men de Phone 33 0 450 955 312 Fax 33 0 450 955 211 E mail info men france fr www men france fr Fax 215 542 9577 E mail sales menmicro com www menmicro c
19. working Parse SO DIMM SPD Init DRAM Check for d pressed Quick DRAM test e DRAM ok C Relocating MainState M 7 Full Mode v FullStartup UN Init heap in DRAM StartupPrologue 2 i d MainState p MEN Mikro Elektronik GmbH 47 20EM09 00 E4 2010 02 01 Figure 5 MENMON State diagram main state MENMON Main State i s Init ES Init on chip MMBIOS devs PCI autoconfig RTC init FPGA load Init further MMBIOS devs gt for user abort No user intervention Y Selftest SETUP Screen Menu B e start network servers S iented Mai creen oriented Main menu 3 i a s pressed C gt l Perform self tests oo Check for user abort Touch pressed outside setup b TouchCalib Y e touch calibration No user intervention E Auto Update Check Es do check for update media Execute Auto update dialog when suitable medium found Leave dialog after 5 seconds aw Booting ES User abort or degraded mode User abort or Self test error and stignfault false jJ Execute mmstartup string mmstartup empty Jump to bootstrapper A No user intervention User abort or Boot failure a vv MenmonCli entry start network servers do process command line MEN Mikro Elektronik G
20. wr U EO ee Usermodule 90 of 0 6 of of of 8000 1000 Usermodule 1 9000 of 0 7 of o of 9000 1000 All values in the tables are given in hexadecimal notation MEN Mikro Elektronik GmbH 45 20EMO9 00 E4 2010 02 01 MENMON 4 MENMON 4 1 General MENMON is the CPU board firmware that is invoked when the system is powered on The basic tasks of MENMON are Initialize the CPU and its peripherals Load the FPGA code PCI auto configuration Perform self test Provide debug diagnostic features on MENMON command line Interaction with the user via touch panel TFT display Boot operating system Update firmware or operating system The following description only includes board specific features For a general T description and in depth details on MENMON please refer to the MENMON 2nd Edition User Manual MEN Mikro Elektronik GmbH 46 20EM09 00 E4 2010 02 01 MENMON 4 1 1 State Diagram Figure 4 MENMON State diagram Degraded Mode Full Mode a Degraded Mode 3 a Earlylnit TN do CPU early init Check if secondary MENMON Secondary MENMON vali valid Ts E J Secondary E MENMON Secondary MENMON not valid or abort pin set Y K DegradedStartup Bs StartupPrologue DR Determine clocks I2C controller init SYSPARAM init Init early MMBIOS dev PN D d pressed Check for D pressed DRAM not
21. 1 AD15 3 3V 9 SERR GND SBO PAR 10 GND PERR 3 3V SDONE 11 STOP 3 3V LOCK GND 12 3 3V TRDY GND DEVSEL 13 FRAME GND IRDY 3 3V 14 GND AD16 3 3V C BE2 15 AD18 3 3V AD17 GND 16 AD21 AD20 GND AD19 17 3 3V AD23 AD22 3 3V 18 IDSELO GND IDSEL1 IDSEL2 19 AD24 C BE3 VI O 3 3V IDSEL3 20 GND AD26 AD25 GND 21 AD29 5V AD28 AD27 22 5V AD30 GND AD31 23 REQO GND REQ1 VI O 3 3V 24 GND REQ2 5V GNTO 25 GNT1 VI O 3 3V GNT2 GND 26 5V CLKO GND CLK1 27 CLK2 5V CLK3 GND 28 GND INTD 5V RST 29 Reserved INTA INTB INTC 30 Reserved REQ3 GNT3 GND For a description of signals please refer to the PCI 104 specification see Chapter 6 1 Literature and Web Resources on page 74 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 FPGA 3 FPGA 3 1 General The FPGA as a part of the ESM represents an interface between a user selectable configuration of I O modules IP cores and the PCI bus The PCI core included in the FPGA can be a PCI target or master It can be accessed via memory single burst read write cycles The Wishbone bus is the uniform interface to the PCI bus However the FPGA may have multiple internal buses so that IP cores can be connected to one of several internal buses e g Wishbone or Avalon This guarantees the highest possible flexibility for different configurations of the FPGA Typically each implementation contains basic system functions such as reset and interrupt control etc
22. 10 20EMO9 00 E4 2010 02 01 Configuration Options Configuration Options CPU Several PowerQUICC III types with different clock frequencies MPC8548 or MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 1 5 GHz MPC8543 or MPC8543E 800 MHz or 1 GHz Memory System RAM 512 MB 1 GB or 2 GB NAND Flash OMB up to maximum available FRAM OKBor 128 KB Boot Flash 8 MB or 16 MB VO EM9 Front Connections D Sub connectors for Ethernet and COM LANI and LAN2 via one 9 pin D Sub connector with 10 100Base T support LAN3 and COMI via one 9 pin D Sub connector LAN3 with 10 100Base T Ethernet Only two channels instead of three with MPC8543 COM2 Additional COM2 RS232 interface COMI and COM2 sharing front connector Both COMs without handshake lines VO EM9A Ethernet Only two channels instead of three with MPC8543 FPGA Type Altera Cyclone II EP2C20 instead of EP2C35 18 752 logic elements 239 616 total RAM bits Thermal Characteristics EM9A The ESM module s heat sink is always tailor made to the customer s thermal requirements MEN Mikro Elektronik GmbH ll 20EMO9 00 E4 2010 02 01 Configuration Options Power Supply Single 5V power supply instead of 5V and 3 3V Mechanical EM9 PCI and I O connectors can also be placed for face to face assembly ESM Type N EM9A PCI and I O connectors can also be placed for face up assembly ESM Type S P
23. 2 1672016 IDE IDE controller PIO mode 0 and UDMA mode 5 162044 DISP Display controller 800 x 600 60Hz 75Hz 6 bit RGB 162031 SPI SPI touch panel controller 167125 UART UART controller controls COM10 COM12 162034 GPIO GPIO controller 8 I O lines system control signals The FPGA offers the possibility to add customized I O functionality See FPGA PCI Interface 32 bit 33 66 MHz PCI interface at PCI 104 connectors J1 and J2 Compliant with PCI Specification 2 2 e Support of four external masters Miscellaneous Real time clock Temperature sensor power supervision and watchdog Electrical Specifications Supply voltage power consumption 5V 2 5 2A typ 3 3V 2 5 0 5A typ Mechanical Specifications Dimensions conforming to ESM specification PCB 149mm x 71mm Type II N except height approx 1mm higher than standard Heat sink is always tailor made to the customer s needs no heat sink included in standard version Weight 90g w o heat sink MEN Mikro Elektronik GmbH 7 20EMO9 00 E4 2010 02 01 20EMO9 00 E4 2010 02 01 Technical Data Environmental Specifications Temperature range operation 40 85 C screened with appropriate heat sink Airflow min 10m h Temperature range storage 40 85 C Relative humidity operation max 95 non condensing Relative humidity storage max 95 non condensing Altitude 300m to
24. 20EMO 9 00 E4 2010 02 01 EM9 EM9A Embedded System Modules with MPC8548 EM9 Configuration example shown without heat sink EM9A Configuration example shown without heat sink User Manual man mikro elektronik gmbh n rnberg EM9 EM9A Embedded System Modules with MPC8548 EM9 EM9A Embedded System Modules with MPC8548 The EM9 EM9A is a complete embedded SBC for use on any carrier board in different industrial environments The final application consists of a stand alone EM9 EM9A an EM9 EM9A with an application specific carrier card and or with additional PCI 104 modules EM9 The EM9 EMOA is controlled by an integrated PowerPC MPC8548 or MPC8543 processor optionally with encryption unit running at clock frequencies between 800 MHz and 1 5 GHz The EM9 EM9A is equipped with soldered DDR2 SDRAM for data and with NAND Flash for program storage The EMO provides front panel access for three Gigabit Ethernet channels and one COM port via four RJ45 connectors while the EM9A provides access for three Gigabit Ethernet channels and two COM ports via its I O connector J3 Additional functionality such as graphics touch CAN bus protocol converters etc can be realized in an FPGA for the needs of the individual application The corresponding connectors are available on a carrier board Application software dynamically loads the functions of the FPGA The EM9 EM9A comes with MENMON support This
25. AO 33 MHz Ox DE 0000 0x FFDE 0000 128 KB System parameter section in boot Flash if useflpar system parameter is set to 1 Ox EO 0000 0x FFEO 0000 1 MB Secondary MENMON Ox FO 0000 0x FFFO 0000 1 MB Primary MENMON MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 MENMON 4 7 5 MENMON BIOS Logical Units The following table shows fixed assigned CLUNs All other CLUNs are used dynamically Table 29 MENMON Controller Logical Units CLUNs CLUN Bos b a Description 0x00 IDEO NAND Flash IDE primary IDE 0x01 IDE1 IDE devices controlled by onboard FPGA 0x02 ETHERO Ethernet 0 LAN 1 0x03 ETHER1 Ethernet 1 LAN 2 0x04 ETHER2 Ethernet 2 LAN 3 0x08 COM1 MPC854X UART channel 0 0x09 COM2 MPC854X UART channel 1 optional on EM9 0x0A TOUCH Touch console if 162031 SPI found in onboard FPGA and can communicate with touch controller 0x0B COM10 UART 0 of onboard FPGA UART 0x0C COM11 UART 1 of onboard FPGA UART 0x0D COM12 UART 2 of onboard FPGA UART 0x20 All other devices dynamically detected on PCI or FPGA devices 0x40 Telnet console 0x41 HTTP monitor console Table 30 MENMON Device Logical Units DLUNs CLUN DLUN MENMON BIOS Name Description 0x00 0x00 NAND Int CF Internal NAND Flash 0x01 0x00 IDE1 M Ext CF External IDE Master 0x01 0x01 IDE1 S External IDE Slave MEN Mikro Elektronik Gmb
26. AO TXD10 45V DOTCLK 26 GND IDE A2 GPIO 0 1 45V 27 IDE CS1 GND GPIO_0 2 DTMG 28 GPIO 07 IDE_CS3 GND HSYNC 29 45V SDA BLUE 0 GND 30 SCL 43 3V_STBY BLUE 1 VSYNC MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Functional Description Table 14 Signal mnemonics of I O connector J2 factory standard FPGA configuration Signal Direction Function Power 3 3V 3 3V power supply 3 3V_STBY in Power supply for real time clock 5V 5V power supply GND Digital ground of respective interface lC SCL out C bus EEPROM SDA in out I C bus IDE SRAM IDE_A 2 0 out IDE SRAM address 2 0 IDE_CS1 out IDE chip select 1 IDE_CS3 out IDE chip select 3 IDE D 15 0 in out IDE SRAM data 15 0 IDE_DAK out IDE DMA acknowledge IDE_DRQ in IDE DMA request IDE_EN out IDE SRAM enable 0 IDE 1 SRAM IDE_IRQ in IDE interrupt request IDE_RD out IDE SRAM read strobe IDE_RDY in IDE ready IDE_RST out IDE reset IDE_R W out SRAM address latch enable IDE_WR out IDE SRAM write strobe UARTs COM10_SW out COM10 mode 0 COM10 operates in RS422 485 mode 1 COM10 operates in RS232 mode CTS10 in COM10 clear to send RTS10 out COM10 request to send RXD10 in COM10 receive data TXD10 out COM10 transmit data RXD11 in COM11 receive data TXD11 out COM11 transmit data CTS12 in COM12 clear to send RTS12 out COM12
27. D Flash memory controlled by the FPGA The data bus is 8 bits wide MEN s NAND ATA controller provides wear leveling without user interaction Using the NAND ATA controller the NAND Flash is seen as an ATA disk NAND Flash provides 100 000 erase cycles minimum and 10 years data retention See also Chapter 4 5 Updating Boot Flash NAND Flash SDRAM and EEPROM on page 51 2 7 4 FRAM The board has 128 KB non volatile FRAM memory connected to the local bus of the CPU The FRAM does not need a back up voltage for data retention 2 7 5 Additional SDRAM The board can be supplied with up to 32 MB additional DDR2 SDRAM It is controlled by the FPGA and a part of it is used for the NAND Flash firmware It can also be used for graphics for instance 2 7 6 EEPROM The board has a 4 kbit serial EEPROM for factory data MENMON parameters and for the VxWorks bootline MEN Mikro Elektronik GmbH 28 20EMO9 00 E4 2010 02 01 Functional Description 2 8 Ethernet Interfaces The ESM has three Ethernet interfaces All the channels are controlled by the CPU LANI to LAN3 They support up to 1000 Mbits s and full duplex operation Board versions with the MPC8543 E processor only have two Ethernet channels The unique MAC address is set at the factory and should not be changed Any A attempt to change this address may create node or bus contention and thereby render the board inoperable The MAC addresses on the ESMs are as follows EM9
28. ENMON Position of abort pins on debug connector Heat Sink Debug conn PowerQUICC III MEN Mikro Elektronik GmbH 60 20EMO9 00 E4 2010 02 01 MENMON 4 7 4 MENMON Memory Map 4 7 4 1 MENMON Memory Address Mapping Table 27 MENMON Address map full featured mode Address Space Size Description 0x 0000 0000 0000 1400 5KB Exception vectors Ox 0000 3000 0000 3FFF 4KB MENMON parameter string Ox 0000 4200 0000 42FF 256 bytes VxWorks bootline Ox 0000 4300 OOFF FFFF Nearly Free 16 MB Ox 01D0 0000 O1DF FFFF 2 MB Heap2 Ox O1E0 0000 OIEF FFFF 1 MB Text Reloc Ox O1FO 0000 O1F1 FFFF 128 KB Stack Ox O1F2 0000 O1F4 FFFF 128KB Stack for user programs and operating system boot Ox O1F5 0000 O1FE FFFF 640 KB Heap Ox OIFF 0000 OIFF FFFF 64KB Not touched for OS post mor tem buffer i e VxWorks WindView or MDIS debugs requires ECC to be turned off 0x 0200 0000 End of RAM Free or download area 4 7 4 2 Boot Flash Memory Map Table 28 MENMON Boot Flash memory map Flash Offset CPU Address Size Description Ox 00 0000 0x FF00 0000 10 MB Available to user Ox AO 0000 0x FFAO 0000 1 MB Fallback FPGA code FPGA1 66 MHz Ox BO 0000 0x FFBO 0000 1 MB Initial FPGA code FPGAO 66 MHz Ox CO 0000 0x FFCO 0000 1MB _ Fallback FPGA code FPGA1 33 MHz Ox DO 0000 0x FFDO 0000 896 KB Initial FPGA code FPG
29. ESM runs at 66 MHz PCI 266 MHz SDRAM memory and 1 33 GHz core 2 4 Real Time Clock The board includes an RA8581 real time clock Interrupt generation of the RTC is not supported For data retention during power off the RTC must be supplied with 3 3V from an external battery via J2 pin 3 3V_STBY B30 A control flag indicates a back up power fail condition In this case the contents of the RTC cannot be expected to be valid A message will be displayed on the MENMON console in this case MEN Mikro Elektronik GmbH 25 20EMO9 00 E4 2010 02 01 Functional Description 2 5 PowerPC CPU The board is equipped with the MPC8548 or MPC8543 processor which includes a 32 bit PowerPC e500 core the integrated host to PCI bridge Ethernet controllers and UARTs 2 5 1 The MPC8548 3 family of processors integrates an e500v2 processor core built on Power Architecture technology with system logic required for networking telecommunications and wireless infrastructure applications The MPC8548 3 is a member of the PowerQUICC III family of devices that combine system level support for industry standard interfaces with processors that implement the embedded category of the Power Architecture technology General The MPC8548 3 offers a double precision floating point auxiliary processing unit APU up to 512 KB of level 2 cache up to four integrated 10 100 1Gbits s enhanced three speed Ethernet controllers with TCP IP acceleration and
30. H 62 20EMO9 00 E4 2010 02 01 MENMON 4 7 6 System Parameters System parameters are parameters stored in EEPROM Some parameters are automatically detected by MENMON such as CPU type and frequency The parameters can be modified through the EE xxx command via the command line 4 7 6 4 Physical Storage of Parameters Most parameters are stored in the 512 byte serial EEPROM on the ESM Carrier board specific parameters are stored in the serial EEPROM on the carrier board If required you can configure MENMON to store some strings in boot Flash rather than in EEPROM 4 7 6 2 Start up with Faulty EEPROM If a faulty EEPROM is detected i e the checksum of the EEPROM section is wrong the system parameters will use defaults The behavior is the same if the EEPROM is blank The default baud rate is 9600 4 7 6 3 ESM System Parameters Note Parameters marked by Yes in section Parameter String are part of the MENMON parameter string Note Parameters for production data of carrier boards will use prefixed parameter names e g c brd Table 31 MENMON ESM system parameters Autodetected parameters Parameter Dn Parameter User alias Description Standard Default String Recess ccbclkhz CCB clock frequency decimal Hz Yes Read only clun MENMON controller unit number that Yes Read only MENMON used as the boot device hexadecimal cons Selected console
31. MON BIOS or network debug level lt clun gt set debug console BO lt addr gt lt opts gt Call OS bootstrapper BOOTP lt opts gt Obtain IP config via BOOTP C BWLLNAX lt addr gt lt val gt Change memory CHAM LOAD lt addr gt Load FPGA CHAM lt clun gt Dump FPGA Chameleon table CONS Show active consoles CONS ACT lt clun1 gt lt clun2 gt Test console configuration CONS GX lt clun gt Test graphics console D lt addr gt lt ent gt Dump memory DBOOT lt clun gt lt dlun gt lt opts gt Boot from disk DCACHE ON OFF Enable disable L1 data cache DIAG lt which gt VTF Run diagnostic tests DSKRD lt args gt Read blocks from RAW disk DSKWR args Write blocks to RAW disk EER xxx lt arg gt Raw serial EEPROM commands EE xxx lt arg gt Persistent system parameter commands ERASE lt D gt lt O gt lt S gt Erase Flash sectors ESMCB xxx ESM carrier commands FI lt from gt lt to gt lt val gt Fill memory byte GO lt addr gt Jump to user program H Print help list commands HELP lt D gt List board information ICACHE ON OFF Enable disable L1 instruction cache IOI Scan for BIOS devices LM81 Show monitor values MEN Mikro Elektronik GmbH 69 20EM09 00 E4 2010 02 01 MENMON Command Description LOGO Display MENMON start up text screen LS lt clun gt lt dlun gt lt opts gt List files partitions on devic
32. No Read write startup 144 chars max if useflpar 0 512 chars max if useflpar 1 nobanner Disable ASCII banner on start up 0 No Read write noecc Do not use ECC even if board supports 0 No Read write it Dool nspeed0 1 2 Speed setting for Ethernet interface AUTO Yes Read write 0 2 Possible values AUTO 10HD 10FD 100HD 100FD 1000 stdis Disable POST bool 0 No Read write stdis XXX Disable POST test with name XXX 0 No Read write bool stdis ether Internal ETHERO 1 2 loopback stdis nand NAND Flash test stdis fpga FPGA test stdis fram FRAM test stdis_sram SRAM test stdis touch Touch controller test stignfault Ignore POST failure continue boot 1 No Read write bool MEN Mikro Elektronik GmbH 0000000000000 Md 65 20EMO9 00 E4 2010 02 01 MENMON Parameter ae Parameter User alias Description Standard Default String Access stwait Time in 1 10 seconds to stay at least in 30 No Read write SELFTEST state decimal 0 Continue as soon as POST has fin ished tdp Telnet server TCP port decimal 1 No Read write tries Number of network tries 20 No Read write tto Minimum timeout between network 0 No Read write retries decimal in seconds u00 u15 User parameters hex 16 bits 0x0000 No Read write updcdis Disable auto update check bool 0 No Read write useflpar Store kerpar and mmstartup parame 0 No Read write ters in boot Flash rather than in EEPROM bool vmode Ves
33. Test IDEO NAND amp OK Test TOUCH ONS NOW AUTOEXECUTING BO No default start address configured Stop Setup network interface CLUN 0x02 00 c0 3a 62 00 18 AUTO Searching for server BOOTP in background Telnet daemon started on port 23 HTTP daemon started on port 80 MenMon gt MEN Mikro Elektronik GmbH 23 20EMO9 00 E4 2010 02 01 Getting Started Mi Now you can use the MENMON BIOS firmware see detailed description in Chapter 4 MENMON on page 46 MI Observe the installation instructions for the respective software 1 3 Installing Operating System Software The board supports Linux VxWorks QNX and INTEGRITY By standard no operating system is installed on the board Please refer to the operating system installation documentation on how to install the software You can find any software available on MEN s website EM9 EM9A 1 4 Installing Driver Software For a detailed description on how to install driver software please refer to the respective documentation You can find any driver software available on MEN s website EM9 EM9A MEN Mikro Elektronik GmbH 24 20EMO9 00 E4 2010 02 01 Functional Description 2 Functional Description The following describes the individual functions of the board and their configuration on the board There is no detailed description of the individual controller chips and the CPU They can be obtained from the data sheets or data books of the semicondu
34. a Video Mode for graphics console 0x0101 No Read write hex see Chapter 4 7 2 Video Modes on page 59 wat Time after which watchdog timer shall O disabled No Read write reset the system after MENMON has passed control to operating system decimal in 1 10 s If 0 MENMON disables the watchdog timer before starting the operating sys tem 1 If SRAM is implemented MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Table 34 MENMON ESM system parameters VxWorks bootline parameters MENMON Parameter E Parameter User alias Description Standard Default String Access bf bootfile Boot file name 127 chars max Empty string No Read write bootdev VxWorks boot device name Empty string No Read write e netip IP address subnet mask e g Empty string No Read write 192 1 1 28 ffffff00 g netgw IP address of default gateway Empty string No Read write h nethost Host IP address used when booting Empty string No Read write over NBOOT TFTP hostname VxWorks name of boot host Empty string No Read write netaddr Access the IP address part of netip No Read write parameter netsm Access the subnet mask part of netip No Read write parameter procnum VxWorks processor number decimal O No Read write S VxWorks start up script Empty string No Read write tn netname Host name of this machine Empty string No Read write unitnum VxWorks boot
35. aaa 62 MENMON Device Logical Units DLUNS annanananaaena 62 MENMON ESM system parameters Autodetected parameters 63 MENMON ESM system parameters Production data 64 MENMON ESM system parameters MENMON persistent parameters oan deese d pe REB en En SUPR P RE THER OEE 65 MENMON ESM system parameters VxWorks bootline parameters 2g Rcs Sh CREE p RS STEEP RS 67 20 Table 35 MENMON Reset causes through system parameter rststat 68 Table 36 MENMON Command reference 0 000000 es 69 Table 37 Memory map processor VIEW annen ehm ne qe taiea 71 Table 38 Address mapping tor PCI 222b reetem remm 71 Table 39 Dedicated interrupt line assignment eneen 12 Table 40 Interrupt numbering assigned by MENMON 12 Table 41 SMB deMIOES sernon sars deter verbete tende ae 73 Table 42 PCI devices on DUSO zon a varen tha dora Ete arten Ade 73 MEN Mikro Elektronik GmbH 21 20EMO9 00 E4 2010 02 01 Getting Started 1 Getting Started This chapter will give an overview of the board and some hints for first installation in a system as a check list 1 1 Map of the Board Figure 1 Map of the board EM9 top view Heat Sink PowerQUICC III Connector LAN3 is only assembled on board versions with MPC 8548 E COM2 is available as an option Figure 2 Map of the board EM9A top view Heat Sink PowerQUICC III LAN3 is only available on board versio
36. alk existing applications Network Operating Systems network management platforms and applications MEN Mikro Elektronik GmbH 32 20EMO9 00 E4 2010 02 01 Functional Description 2 9 UART Interfaces COM1 COM2 are standard RS232 interfaces On EM9A they are both led to the J3 onboard I O connector On EMO by standard only COMI is available via an RJ45 or D Sub connector at the front panel As an option the CTS RTS handshaking signals can be replaced by the RXD TXD signals of COM2 COMI is controlled by the MPC854X UART 0 COM2 is controlled by the MPC854X UART 1 Table 6 Signal mnemonics of UART interfaces Signal Direction Function CTS in Clear to send GND Ground RTS out Request to send RXD in Receive data TXD out Transmit data Connection via RJ45 Connector EM9 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 7 Pin assignment of RJ45 UAHT connector EM9 Standard version COM1 Option with COM2 1 7 z 2 3 z j 4 GND GND 5 RXD1 RXD1 1 G TXD1 TXD1 7 CTS1 RXD2 8 RTS1 TXD2 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Functional Description Connection via 9 pin D Sub Connector EM9 A D Sub connector can be implemented as an option This connector replaces not only the COMI RJ45 but also the LAN3 RJ45 connector These two interface
37. an external loopback connector Before sending frames the link state is monitored If it is not ok within 2 seconds the test fails Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Connection between PHY and physical connector Does not check nterrupt line e All LAN speeds 4 6 2 SDRAM and FRAM Table 19 MENMON Diagnostic tests SDRAM and FRAM Test Name Description Availability SDRAM Quick SDRAM connection test Always Groups POST AUTO SDRAM X Full SDRAM test Always Groups NONAUTO ENDLESS FRAM Quick FRAM test ESM is known to have Groups POST AUTO FRAM FRAM X Full FRAM test Tests available as of EM9 i hardware revision 01 xx Groups NONAUTO ENDLESS 4 6 2 1 Quick RAM Test This quick test checks most of the connections to the RAM chips but does not test all RAM cells It executes very quickly within milliseconds This test is non destructive saves restores original RAM content Checks All address lines All data lines Byte enable signals ndirectly checks clock and other control signals Does not check SDRAM cells Burst mode MEN Mikro Elektronik GmbH 55 20EMO9 00 E4 2010 02 01 MENMON 4 6 2 2 Extended RAM Test This full featured memory test allows to test all RAM cells Depending on the size of the SDRAM this test can take up to one minute It tests 8 16 or 32 bit access each with ran
38. anel Six onboard LEDs to signal LAN Link and Activity One RS232 UART COMI One RJ45 connector at front panel Data rates up to 115 2kbits s 16 byte transmit receive buffer Handshake lines CTS RTS or COMO without any COM handshake lines Further I O depending on FPGA configuration Front Connections Three Ethernet RJ45 e One RS232 UART COMI RJ45 FPGA e Standard factory FPGA configuration Main bus interface Interrupt controller reset controller 162070 IDEDISK IDE controller for NAND Flash 1672043 SDRAM Additional SDRAM controller 32MB DDR2 167016 IDE IDE controller PIO mode 0 and UDMA mode 5 162044 DISP Display controller 800 x 600 60Hz 75Hz 6 bit RGB 162031 SPI SPI touch panel controller 167125 UART UART controller controls COM10 COM12 162034 GPIO GPIO controller 8 I O lines system control signals The FPGA offers the possibility to add customized I O functionality See FPGA PCI Interface 32 bit 33 66 MHz PCI interface at PCI 104 connectors J1 and J2 Compliant with PCI Specification 2 2 e Support of four external masters Miscellaneous Real time clock Temperature sensor power supervision and watchdog Electrical Specifications Supply voltage power consumption 5V 2 5 2A typ 3 3V 2 5 0 5A typ MEN Mikro Elektronik GmbH 4 20EMO9 00 E4 2010 02 01 Technical Data Mechanical Specifications Dimensions confo
39. as graphics RAM 16 MB unused 167016 IDE IDE controller PIO mode 0 and UDMA mode 5 UDMA100 1672044 DISP Display controller 800 x 600 60Hz 75Hz 6 bit RGB 1672031 SPI SPI touch panel controller 167125 UART UART controller controls COM10 COM12 162034 GPIO GPIO controller 2 cores 8 general I O lines PWR FAIL LEDs and other system control signals 3 2 2 FPGA Configuration Table The resulting configuration table of the standard FPGA is as follows Note 162070 IDEDISK consists of three cores 162053 IDEATA 162068 IDETGT 162063 NANDRAW Table 16 FPGA Factory standard configuration table for ESM IP Core Device Variant Revision interrupt Group Instance BAR Offset Size Chameleon Table 24 1 5 3 0 o op of 200 162069 RST 69 0 2 3 0 of of 200 2100 162052 GIRQ PAP 0 2 3 0 of of 300 100 162016 IDE 116 0 1 1 0 of of 400 100 162031 SPI 3m gb pe gn of 809 100 162044 DISP 44 o 1 3E 1 of of 600 100 162034 GPIO 34 0 3 2 0 of of 700 100 162034 GPIO PAP 0 3 2 0 1 of 800 100 162125 UART 125 0 7 3 0o o op 900 J0 162125 UART es gp or Tp of oof 10 162125 UAHT 125 0 7 3 0 2 of 920 10 162068 NANDRAW 63 Of H sH 2f 0 of 4600 100 162068 IDETGT 608 O0 r s ff 6000 9800 162053 IDEATA e o F5 e off 000 400 162043 SDRAM o o 1 3 1 0 af TE 06 162043 SDRAM L A9p w
40. bH 2 20EMO9 00 E4 2010 02 01 Technical Data Technical Data EM9 CPU PowerPC PowerQUICC III MPC8548 MPC8548E MPC8543 or MPC8543E 800MHz up to 1 5GHz T For more information on available standard versions see online data sheet See also Configuration Options e500 PowerPC core with MMU and double precision embedded scalar and vector floating point APU Integrated Northbridge and Southbridge Memory e 2x32KB L1 data and instruction cache 512KB 256KB L2 cache integrated in MPC8548 MPC8543 Up to 2GB SDRAM system memory Soldered DDR2 Up to 300 MHz memory bus frequency depending on CPU e Up to 1GB soldered NAND Flash and more FPGA controlled 32MB additional DDR2 SDRAM FPGA controlled e g for video data and NAND Flash firmware 16MB boot Flash 128KB non volatile FRAM Serial EEPROM 4kbits for factory settings Mass Storage Parallel IDE PATA One port for hard disk drives Available via I O connector FPGA controlled PIO mode 0 and UDMA mode 5 UDMA100 support Up to 1GB soldered ATA NAND Flash and more FPGA controlled Graphics Available via I O connector FPGA controlled e 800 x 600 60Hz 75Hz 6 bit RGB MEN Mikro Elektronik GmbH 3 20EMO9 00 E4 2010 02 01 Technical Data vo Three Ethernet channels Three 10 100 1000Base T Ethernet channels with MPC8548 E Two 10 100 1000Base T Ethernet channels with MPC8543 E Three RJ45 connectors at front p
41. board and other components against damage from static electricity you should follow some precautions whenever you work on your computer Power down and unplug your computer system when working on the inside Hold components by the edges and try not to touch the IC chips leads or cir cuitry Use a grounded wrist strap before handling computer components Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system Store the board only in its original ESD protected packaging Retain the original packaging in case you need to return the board to MEN for repair MEN Mikro Elektronik GmbH 14 20EMO9 00 E4 2010 02 01 About this Document About this Document This user manual describes the hardware functions of the board connection of peripheral devices and integration into a system It also provides additional information for special applications and configurations of the board The manual does not include detailed information on individual components data sheets etc A list of literature is given in the appendix Unless otherwise stated all information in this manual is valid for the EM9 and EMOA For reasons of simplicity we generally refer to ESM in the text History Issue Comments Date E1 First edition 2007 09 10 E2 Chapters on MENMON and board organization 2007 10 29 added E3 UDMA support added addition t
42. classification capabilities a DDR DDR2 SDRAM memory controller a programmable interrupt controller two PC controllers a four channel DMA controller a general purpose I O port and dual universal asynchronous receiver transmitters DUART The MPC8548 3 is available with MPC8548 3E or without an integrated security engine with XOR acceleration Table 1 Processor core options on EM9 EM9A Processor Type Core Frequency L2 Cache Encryption Unit Ethernet Ports MPC8548 1 GHz 1 2 GHz 1 33 GHz or 512 KB No 3 1 5 GHz MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 512 KB Yes 3 1 5 GHz MPC8543 800 MHz or 1 GHz 256 KB No 2 MPC8543E 800 MHz or 1 GHz 256 KB Yes 2 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 2 5 2 The CPU generates around 8 W of power dissipation when operated at 1 33 GHz Thermal Considerations To meet thermal requirements a suitable heat sink must be attached to the CPU and sufficient airflow must be provided MEN provides suitable heat sinks to meet thermal requirements for different board versions and ESM carrier cards Please note that if you use any other heat sink than that supplied by MEN or no heat sink at all warranty on functionality and reliability of the ESM may cease If you have any questions or problems regarding thermal behavior please contact MEN Functional Description 2 6 Bus Structure 2 6 1 Host to PCI Bridge The integrated host to PCI bridge i
43. ctor manufacturer concerned Chapter 6 1 Literature and Web Resources on page 74 2 1 Power Supply The board is supplied with 5V and 3 3V via PCI 104 connectors J1 J2 The onboard power supply generates the 1 1V core voltage for the CPU 1 8V for memory 2 5V for Ethernet and the 1 2V core voltage for the FPGA 2 2 Board Supervision The board features a temperature sensor and voltage monitor The temperature sensor and voltage monitor cause a reset when the temperature reaches a critical point or the voltages are not in the specified range A voltage monitor supervises 5V 3 3V 2 5V 1 8V 1 2V and 1 1V and holds the CPU in reset condition until all supply voltages are within their nominal values In addition this device contains a watchdog that must be triggered The watchdog timeout switches automatically from 56 s after reset to 1 6 s after the first trigger pulse This allows a longer watchdog timeout period during the start up phase After power up the CPU loads the FPGA The configuration file depends on the application After configuration the FPGA serves the external hardware watchdog without further action by the CPU If there is any problem loading the FPGA the external watchdog causes a reset An additional watchdog is implemented in the FPGA 2 3 Clock Supply The CPU is supplied with one copy of the onboard PCI clocks This is internally multiplied to generate the core clock and the memory clock By default the
44. dom pattern and single and burst access On each pass this test first fills the entire memory starting with the lowest address with the selected pattern using the selected access mode and then verifies the entire block This test is destructive Checks All address lines All data lines All control signals All SDRAM cells 4 6 3 FPGA Table 20 MENMON Diagnostic tests FPGA Test Name Description Availability FPGA FPGA presence test Always Groups POST AUTO 4 6 4 EEPROM Table 21 MENMON Diagnostic tests EEPROM Test Name Description Availability EEPROM I C access Magic nibble check Always Groups POST AUTO ENDLESS This test reads the first EEPROM cell over SMB and checks if bits 3 0 of this cell contain the magic nibble OxE MEN Mikro Elektronik GmbH 56 20EMO9 00 E4 2010 02 01 MENMON 4 6 5 IDE NAND Flash Table 22 MENMON Diagnostic tests IDE NAND Flash Test Name Description Availability IDE External IDE master access sector MENMON BIOS device 1 0 0 access present and carrier board is known to have external IDE G NONAUTO ENDLESS ERE e g hard disk or Compact Flash IDEO NAND Check if IDE NAND Flash device If SDRAM and IDE NAND disk is present devices are present in Groups POST FPGA The test first performs an ATA register test then reads sector 0 from the Flash disk without verifying the content o
45. e MC addr1 lt addr2 gt cnt Compare memory MII lt clun gt lt reg gt val Ethernet MII register command MO from to cnt Move copy memory MS from to val Search pattern in memory MT lt opts gt start end Memory test lt runs gt NBOOT lt opts gt Boot from Network NDL lt opts gt Update Flash from network NETSTAT Show current state of networking parameters PCI VPD lt devNo gt lt busNo gt PCI Vital Product Data dump lt capld gt PCIC dev lt addr gt lt bus gt PCI config register change lt func gt PCID dev lt bus gt lt func gt PCI config register dump PCI PCI probe PCIR List PCI resources PCI VPD lt devNo gt lt busNo gt PCI Vital Product Data dump lt capld gt PFLASH lt D gt lt O gt lt S gt lt A gt Program Flash PGM XXX lt args gt Media copy tool PING lt host gt lt opts gt Network connectivity test RELOC Relocate MM to RAM RST Cause an instant system reset RTC xxx lt arg gt Real time clock commands S lt addr gt Single step user program SERDL passwd Update Flash using YModem protocol SETUP Open interactive Setup menu MEN Mikro Elektronik GmbH 70 20EMO9 00 E4 2010 02 01 Organization of the Board 5 Organization of the Board To install software on the board or to develop low level software it is essential to be familiar with the b
46. f the sector Checks Most ATA control lines Basic ATA transfer Does not check ATA signals IRQ DAK DRQ Partition table or file system on disk 4 6 6 COM1 COM2 Table 23 MENMON Diagnostic tests COM1 COM2 Test Name Description Availability COM1 External loopback test RxD TxD Always RTS CTS Groups NONAUTO ENDLESS Note Test will be skipped when COM1 is currently used as a con sole COM2 External loopback test RxD TxD Only if implemented Groups NONAUTO ENDLESS COMx External loopback test RxD TxD Depending on FPGA pro handshake lines grammed UARTs Groups NONAUTO ENDLESS This test requires an external test adapter connecting TXD and RXD To test TXD RXD a test string is sent through the UART RTS and CTS To test TXD RXD a test string is sent through the UART To test handshake lines the lines are toggled and it is checked whether input lines follow MEN Mikro Elektronik GmbH 57 20EMO9 00 E4 2010 02 01 MENMON 4 6 7 Touch Table 24 MENMON Diagnostic tests touch Test Name Description Availability TOUCH Touch controller communication test Carrier board is known to Groups POST AUTO ENDLESS Mave a touch controller This test tries to communicate over the SPI bus with the touch controller on the carrier board by sending an Identify command to the controller Checks e SPI connection to touch controller Does not check
47. hat is used on models 15EM09 00 and 15EM09A00 It provides the following interfaces via J2 See Chapter 3 2 Standard Factory FPGA Configuration on page 45 DE SRAM Serial interfaces COMIO 12 Display SPI touch panel GPIO 8 lines Miscellaneous functions The following tables give the pinouts of the raw J2 connector FPGA independent and of its signals in conjunction with the above mentioned FPGA configuration Connector types 4 row 120 pin PCI 104 receptacle connector 2mm pitch Mating connector 4 row 120 pin PCI 104 plug connector 2mm pitch For the position of connector J2 on the board see Chapter 1 1 Map of the Board on page 22 MEN Mikro Elektronik GmbH 36 20EMO9 00 E4 2010 02 01 Functional Description Table 11 Pin assignment of I O connector J2 general pinout A B C D 1 PA1 PB1 5V PD1 2 GND PB2 PC2 5V 3 PA3 GND PC3 PD3 4 PA4 PB4 GND PD4 5 3 3V PB5 PC5 GND 6 PA6 3 3V PC6 PD6 7 PA7 PB7 3 3V PD7 8 GND PB8 PC8 3 3V 9 PA9 GND PC9 PD9 10 PA10 PB10 GND PD10 11 45V PB11 PC11 GND 12 PA12 5V PC12 PD12 13 PA13 PB13 5V PD13 14 GND PB14 PC14 5V 15 PA15 GND PC15 PD15 16 PA16 PB16 GND PD16 17 3 3V PB17 PC17 GND 18 PA18 3 3V PC18 PD18 19 PA19 PB19 3 3V PD19 20 GND PB20 PC20 3 3V 21 PA21 GND PC21 PD21 22 PA22 PB22 GND PD22 23 5V PB23 PC23 GND 24 PA24 5V PC24 PD24 25 PA25 PB25 5V PD25 26 GND PB26 PC26 5V 27 PA27 GND PC27 PD27 28 PA28 PB28 GND PD28
48. heet with up to date information and documentation www men de products 15em09a html 6 1 1 PowerPC MPC8548 MPC8548E PowerQUICC III Integrated Processor Family Reference Manual MPC8548ERM 2007 Freescale Semiconductor Inc www freescale com 6 1 2 PCI 104 PCI 104 PCI 104 Specification PC 104 Embedded Consortium www pc104 org 6 1 3 Ethernet Ethernet in general The Ethernet A Local Area Network Data Link Layer and Physical Layer Specifications Version 2 0 1982 Digital Equipment Corpora tion Intel Corp Xerox Corp ANSI IEEE 802 3 1996 Information Technology Telecommunications and Information Exchange between Systems Local and Metropolitan Area Networks Specific Requirements Part 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Phys ical Layer Specifications 1996 IEEE www ieee org www ethermanage com ethernet links to documents describing Ethernet components media the Auto Negotia tion system multi segment configuration guidelines and information on the Ethernet Configuration Guidelines book www iol unh edu training ethernet html collection of links to Ethernet information including tutorials FAQs and guides ckp made it com ieee8023 html Connectivity Knowledge Platform at Made IT technology information service with lots of general information on Ethernet 6 1 4 EIDE EIDE Information Technology AT Attachment 3 Interface ATA 3 Revi
49. igned by MENMON on page 72 each FPGA unit interrupt is routed to a dedicated interrupt line The mapping is as follows Table 39 Dedicated interrupt line assignment MPC854X External Interrupt Line FPGA Function IRQ 1 IDE UDMA capable IRQ 2 GPIOs IRQ 3 UARTS IRQ 4 SPI Touch controller IRQ 5 NAND Flash IDE IRQ 6 User module 1 IRQ 7 User module 2 Table 40 Interrupt numbering assigned by MENMON MPC854X IRQ Input PCI Interrupt Line ae ee IRQS INTA 0x8 IRQS INTB 0x9 IRQ10 INTC OxA IRQ11 INTD 0x8 MEN Mikro Elektronik GmbH 72 20EMO9 00 E4 2010 02 01 Organization of the Board 5 3 SMB Devices Table 41 SMB devices Address Function Ox5E LM81 hardware monitor OxA0 Reserved OxA2 Real time clock 0xA8 CPU EEPROM 512 bytes OxAC Carrier board EEPROM if present and supported 5 4 PCI Devices on Bus 0 Table 42 PCI devices on bus 0 NES r Vendor ID Device ID Function Interrupt 0x00 0x1057 0x0012 PCI host bridge in MPC854X 0x13 0x1A88 0x4D45 FPGA 0x14 PCI 104 slot 1 INTA 0x15 PCI 104 slot 2 INTB 0x16 PCI 104 slot 3 INTC 0x17 PCI 104 slot 4 INTD MEN Mikro Elektronik GmbH 73 20EMO9 00 E4 2010 02 01 Appendix 6 Appendix gt 6 1 Literature and Web Resources EMO data sheet with up to date information and documentation www men de products 15em09 html e EMOA data s
50. lease note that some of these options may only be available for large volumes Please ask our sales staff for more information For available standard configurations see online data sheets EM9 e EM9A MEN Mikro Elektronik GmbH 2 2 3 RW i i i i i ia i i it S 12 20EMO9 00 E4 2010 02 01 FPGA Flexible Configuration This MEN board offers the possibility to add customized I O functionality in FPGA t depends on the board type pin counts and number of logic elements which IP cores make sense and or can be implemented Please contact MEN for informa tion on feasibility e You can find more information on our web page User I O in FPGA FPGA Capabilities e FPGA Altera Cyclone II EP2C35 33 216 logic elements 483 840 total RAM bits Connection Total available pin count 81 pins Functions available via I O connector J2 x MEN offers a starter kit for a computer on module of the same product family version with front I O The kit includes a suitable carrier board with different I O connectors for FPGA signals An FPGA development package for this hard ware kit is also available for download MEN Mikro Elektronik GmbH 13 20EMO9 00 E4 2010 02 01 Product Safety Product Safety AN Electrostatic Discharge ESD Computer boards and components contain electrostatic sensitive devices Electrostatic discharge ESD can damage components To protect the
51. mbH 20EMO9 00 E4 2010 02 01 MENMON 4 2 Interacting with MENMON To interact with MENMON you can use the following consoles UARTs COMI 2 RS232 UARTs COMIO 12 FPGA Touch panel TFT interface if present Telnet via network connection HTTP monpage via network connection The default setting of the COM ports is 9600 baud 8 data bits no parity and one stop bit 4 2 1 Entering the Setup Menu Command Line During normal boot you can abort the booting process in different ways during the self test depending on your console With a touch panel press the Setup button to enter the Setup Menu With a text console press the s key to enter the Setup Menu With a text console press ESC to enter the command line By default the self test is not left until 3 seconds have elapsed measured from the beginning of the self test even if the actual test has finished earlier to give the user a chance to abort booting and enter the Setup Menu You can modify the self test wait time through MENMON system parameter stwait see page 66 MEN Mikro Elektronik GmbH 49 20EMO9 00 E4 2010 02 01 MENMON 4 3 Configuring MENMON for Automatic Boot You can configure how MENMON boots the operating system either through the Setup Menu or through the command line In the Basic Setup Menu you can select the boot sequence for the bootable devices on the ESM The selected sequence is stored in system parameter mms
52. ns with MPC8548 E MEN Mikro Elektronik GmbH 22 20EMO9 00 E4 2010 02 01 Getting Started 1 2 Integrating the Board into a System You can use the following check list when installing the board in a system for the first time and with minimum configuration A The board is completely trimmed on delivery M Power down the system Install the ESM on your carrier card Ml Insert the assembly into your system M Connect a terminal to the standard RS232 interface COMI M Set your terminal to the following protocol 9600 baud data transmission rate 8 data bits 1 stop bit No parity MI Power up the system MI The terminal displays a message similar to the following Secondary MENMON for MEN EM9 Family 0 21 c 2007 2007 MEN Mikro Elektronik GmbH Nuremberg MENMON 2nd Edition Created Oct 12 2007 11338801 CPU Board EMO9 00 Serial Number 24 CPU MPC8548E CPU MEM Clk 1386 198 MHz HW Revision 00 02 01 CCB LISXC CII amp s 396 50 MHz DDR2 SDRAM 512 MB ECC off 3 0 3 8 FRAM 0 kB FLASH 16 MB Reset Cause Power On Produced l PCs 32 Blut 39 MAZ Last repair l Carrier Board ECO1 11 Rev 01 02 00 Serial 736 Setting speed of NETIF 0 to AUTO Setting speed of NETIF 1 to AUTO Setting speed of NETIF 2 to AUTO press ESC for MENMON s for setup Test SDRAM 8 OK Test FPGA OK Test ETHERO MON ES RR ORK Test ETHERZ g OK Test EEPROM amp OK Test RTC amp OK
53. o MENMON 2008 03 20 E4 Description of EM9A added minor errors corrected 2010 02 01 Conventions This sign marks important notes or warnings concerning proper functionality of the product described in this document You should read them in any case italics Folder file and function names are printed in italics bold Bold type is used for emphasis monospace A monospaced font type is used for hexadecimal numbers listings C function descriptions or wherever appropriate Hexadecimal numbers are preceded by Ox hyperlink Hyperlinks are printed in blue color m C The globe will show you where hyperlinks lead directly to the Internet so you can look for the latest information online IRQ Signal names followed by or preceded by a slash indicate that this signal is IRQ either active low or that it becomes active at a falling edge in out Signal directions in signal mnemonics tables generally refer to the corresponding board or component in meaning to the board or component out meaning coming from it Vertical lines on the outer margin signal technical changes to the previous issue of the document MEN Mikro Elektronik GmbH 15 20EMO9 00 E4 2010 02 01 About this Document Legal Information MEN Mikro Elektronik reserves the right to make changes without further notice to any products herein MEN makes no warranty representation or guarantee regarding the suitability of its products for any partic
54. oard s address and interrupt organization 5 1 Memory Mappings Table 37 Memory map processor view CPU Address Range Size Description 0x 0000 0000 End of RAM 512 1024 SDRAM 2048 MB 0x 8000 0000 EFFF FFFF 1792 MB PCI Memory Space Ox F000 0000 F00F 0000 64 MB CCSR Ox F200 0000 F200 3FFF Config PLD Ox F300 0000 F301 FFFF FRAM opt Ox FBOO 0000 FBFF FFFF 16 MB PCI I O ISA Space Ox FF00 0000 FFFF FFFF 16 MB Boot Flash Table 38 Address mapping for PCI CPU Address Range Mapped to PCI Space Description Ox 8000 0000 83FF FFFF 0x 8000 0000 83FF FFFF Prefetchable MEM BARs of onboard FPGA Ox 8400 0000 8FFF FFFF Ox 8400 0000 8FFF FFFF Prefetchable MEM BARs of all other PCI devices Ox 9000 0000 EFFF FFFF Ox 9000 0000 EFFF FFFF Non prefetch MEM able BARs Ox FBOO 0000 FBFE FFFF 0x 0000 0000 00FE FFFF PCI ISA mem MEM ory Ox FBFF 0000 FBFF OFFF 0x 0000 0FFF I O PCI I O space of onboard FPGA Ox FBFF 1000 FBFF FFFF Ox 1000 FFFF I O PCI I O space of all other PCI devices MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Organization of the Board 5 2 Interrupt Handling Interrupt handling between the FPGA and the CPU is done via the 12 external interrupt lines of the CPU IRQ 0 11 While the IRQ lines 8 to 11 are used as the four PCI interrupt lines see Table 40 Interrupt numbering ass
55. om MEN Mikro Elektronik GmbH 16 20EMO9 00 E4 2010 02 01 Contents Contents L Getting Started o ode p hom m RUSO EROR nn bede AED BEN 22 LI Map Or the Boards samsara uid Qoid pd eua 22 1 2 Integrating the Board into a System nennen 23 1 3 Installing Operating System Software aan 24 1 4 Installing Driver Software ae en 24 2 Functional Description esee e rr ween nennen 25 2 Power Supplyuravan verevenen deekie 25 2 2 Board Supervision iu 22 pue dr treten dermee nlet 25 2 3 Clock SUPP ypes siider paaie petite 9 lei aq e ER 25 234 Real Time ClOCK nas saneren Rm RESET RS baie Ris 25 2 POWerPC CR noten pirsa viii ketonen at a 26 254 Mental sand eden 26 2 52 Thermal Considerations as neatetinss hetnet 26 2 6 BUS SUUCUITG s s tamin avatar bad Abi dad babba rb qu ad 27 2 61 Host to PCI Bridge aaa oua van m est 27 262 Focal PCIE BUS esci beta ERR EER VE REI 27 2 MGM0fysicccaceacdsa shed RA UR E dikte Rer IR ke BES 28 2 11 DRAM System Memoty 5 sse emere Rd EE 28 Ze NBOOLPIASI 23 iuro pud Sad easin qe abs hades 28 2 129 JINAND EISSh sons re eed etende 28 2A ERAM ed gea OPE opea debeo tp ENS 28 2 7 5 Additional SDRAM nennen eee 28 20 0 MEBPROM co30 pa taane peiahes SENE RA E gua 28 2 8 Ethernet Intemacesins ouai ea IN E PREDREGG GRE RE RU GRECE RES 29 2 5 Conneclon sm ded CERE E TE retenus 29 Qo General soir tages Uode d etg ode ui qoo aur eto dos 31
56. ooks for some special files on an external IDE device if present on carrier card The files that are searched for are Name stored in system parameter bf or bootfile or if this is empty BOOTFILE e IMAGE CO00 see also Table 17 MENMON Program update files and loca tions on page 51 To allow MENMON to locate these files they must be in the root directory of a DOS FS This works on unpartitioned media or on drives with one partition MENMON does not automatically start the copying process Depending on the type of file found it presents different menus to the user In case BOOTFILE was found Detected an update capable external Disk gt Ignore continue boot Boot from this medium In case IMAGE C00 was found Detected an update capable external Disk gt Ignore continue boot Copy external CF IMAGE COO gt internal CF The copying process is then performed in the same way as a standard sector by sector media copy program update see MENMON 2nd Edition User Manual If there is no user input for 5 seconds after the menu appears booting continues 1 MENMON versions lt 3 4 only search for bootfile MEN Mikro Elektronik GmbH 52 20EMO9 00 E4 2010 02 01 MENMON 4 5 5 Updating MENMON Code Updates of MENMON are available for download from MEN s website MENMON s integrated Flash update functions allow you to do updates yourself However you need to take care and follow the instructions given
57. out Differential pair of transmit data lines for 10 100Base T MEN Mikro Elektronik GmbH 29 20EMO9 00 E4 2010 02 01 Functional Description Connection via RJ45 Connectors EM9 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 3 Pin assignment and status LEDs of RJ45 Ethernet connectors LAN1 3 EM9 1000Base T 10 100Base T 1 BI_DA TX Lights up whenever there is A 2 BI_DA TX receive activity 3 BI DB RX 4 BI_DC i 5 BI DC Lights up as soon as a L 6 BI DB RX 1000 Gbit link is established 7 BI DD 8 BI DD Connection via 9 pin D Sub Connectors EM9 D Sub connectors can be implemented as an option In this case only 10Base T and 100Base TX are supported no Gigabit Ethernet connection In addition the D Sub connector for LAN3 replaces not only the LAN3 RJ45 but also the COMI RJ45 connector These two interfaces are routed to one D Sub connector Connector types 9 pin D Sub plug according to DIN41652 MIL C 24308 with thread bolt UNC 4 40 Mating connector 9 pin D Sub receptacle according to DIN41652 MIL C 24308 available for rib bon cable insulation piercing connection hand soldering connection or crimp connection Table 4 Pin assignment of 9 pin D Sub Ethernet plug connector LAN1 2 EM9 1 LAN1_TX 6 o2 6 LAN1_TX 2 LAN2 TX So 7 LAN2 TX
58. pair cable with maximum lengths of 100 meters The cable is thinner and more flexible than the coaxial cable used for the 10Base 2 or 10Base 5 standards Since it is also cheaper it is the preferable solution for cost sensitive applications Cables in the 10Base T system connect with RJ45 connectors A star topology is common with 12 or more computers connected directly to a hub or concentrator The 10Base T system operates at 10 Mbits s and uses baseband transmission methods 2 8 4 100Base T The 100Base T networking standard supports data transfer rates up to 100 Mbits s 100Base T is actually based on the older Ethernet standard Because it is 10 times faster than Ethernet it is often referred to as Fast Ethernet Officially the 100Base T standard is IEEE 802 3u There are several different cabling schemes that can be used with 100Base T e g 100Base TX with two pairs of high quality twisted pair wires MEN Mikro Elektronik GmbH 31 20EMO9 00 E4 2010 02 01 Functional Description 2 8 5 1000Base T 1000Base T is a specification for Gigabit Ethernet over copper wire IEEE 802 3ab The standard defines 1 Gbit s data transfer over distances of up to 100 meters using four pairs of CAT 5 balanced copper cabling and a 5 level coding scheme Because many companies already use CAT 5 cabling 1000Base T can be easily implemented Other 1000Base T benefits include compatibility with existing network protocols i e IP IPX AppleT
59. r User alias Description Standard Default String A cess brd Board name Yes Read only brdmod Board model mm Yes Read only brdrev Board revision xx yy zz Yes Read only prodat Board production date MM DD Y Y YY Yes Read only repdat Board last repair date MM DD Y Y YY Yes Read only sernbr Board serial number Yes Read only MEN Mikro ElektronikGmbH 4 64 20EMO9 00 E4 2010 02 01 Table 33 MENMON ESM system parameters MENMON persistent parameters MENMON Parameter oer Parameter User alias Description Standard Default String Access bsadr bs Bootstrapper address Used when BO l0 No Read write command was called without argu ments hexadecimal 32 bits cbr baud Baudrate of all UART consoles dec 9600 Yes Read write con0 con3 CLUN of console 0 3 hex see Chap OxFF auto No Read write ter 4 7 1 Consoles on page 59 eccsth ECC single bit error threshold 32 No Read write ecl CLUN of attached network interface OxFF No Read write hex gcon CLUN of graphics screen hex see OxFF auto No Read write Chapter 4 7 1 Consoles on page 59 hdp HTTP server TCP port decimal 1 No Read write kerpar Linux Kernel Parameters 399 chars Empty string No Read write max Part of VxWorks bootline if usefl par 0 400 chars max if useflpar 1 Idlogodis Disable load of boot logo bool 0 No Read write mmstartup Start up string Empty string
60. r for application in medical appliances used for therapeutical purposes Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product ESM ESMini MDIS MDIS4 MENMON M Module M Modules SA Adapter SA Adapters UBox USM and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH PC MIP is a registered trademark of MEN Micro Inc and SBS Technologies Inc MEN Mikro Elektronik ESMexpress MIPIOS and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH Altera amp Arria Avalon Cyclone Nios and Quartus are registered trademarks of Altera Corp Freescale and PowerQUICC are trademarks of Freescale Semiconductor Inc PowerPC is a registered trademark of IBM Corp Green Hills and INTEGRITY are registered trademarks of Green Hills Software Inc OS 9 OS 9000 and SoftStax are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak and Hawk are trademarks of RadiSys Microware Communications Software Division Inc RadiSys is a registered trademark of RadiSys Corporation QNX is a registered trademark of QNX Ltd Tornado and VxWorks are registered trademarks of Wind River Systems Inc All other products or services mentioned in this publication are identified by the trademarks
61. request to send RXD12 in COM12 receive data TXD12 out COM12 transmit data MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Functional Description Signal Direction Function Display DOTCLK out Dot clock DTMG out Display data valid invalid HSYNC out Horizontal synchronization RED 5 0 out Monitor interface red green blue GREEN 5 0 BLUE 5 0 VSYNC out Vertical synchronization Other GPIO x in out GPIO lines LED 4 1 out LEDs controlled through GPIO PBRST in Push button reset controlled through GPIO PWR_FAIL in Power supply fail controlled through GPIO MEN Mikro Elektronik GmbH 4 20EM09 00 E4 2010 02 01 Functional Description 2 12 PCI 104 Interface J1 The ESM provides a 32 bit PCI interface at the PCI 104 connector J1 The ESM is always the system controller of the PCI 104 bus and supports four external masters Connector types 4 row 120 pin PCI 104 receptacle connector 2mm pitch e g Samtec ESQT 130 02 G Q 368 Mating connector 4 row 120 pin PCI 104 plug connector 2mm pitch MEN Mikro Elektronik GmbH 42 20EMO9 00 E4 2010 02 01 Table 15 Pin assignment of PCI J1 Functional Description A B C D 1 GND Reserved 45V ADOO 2 VIO 3 3V ADO2 ADO1 5V 3 ADO5 GND AD04 ADO3 4 C BEO ADO7 GND ADO6 5 GND ADO9 ADO8 GND 6 AD11 VI O 3 3V AD10 M66EN 7 AD14 AD13 GND AD12 8 3 3V C BE
62. rming to ESM specification PCB 149mm x 71mm Type I S except height approx 1mm higher than standard Weight 108g w o heat sink standard heat sink 142g Environmental Specifications Temperature range operation 40 4 85 C screened Airflow min 10m3 h e Temperature range storage 40 85 C Relative humidity operation max 95 non condensing Relative humidity storage max 95 non condensing Altitude 300m to 3 000m Shock 15g 11ms Bump 10g 16ms Vibration sinusoidal 1g 10 150Hz Conformal coating on request MTBF 245 671h 40 C according to IEC TR 62380 RDF 2000 Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manu facturers EMC Tested according to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst BIOS MENMONTM Software Support Linux VxWorks QNX INTEGRITY 9 Green Hills Software OS 9 on request For more information on supported operating system versions and drivers see online data sheet MEN Mikro Elektronik GmbH 5 20EMO9 00 E4 2010 02 01 Technical Data CPU PowerPC PowerQUICC III MPC8548 MPC8548E MPC8543 or MPC8543E 800MHz up to 1 5GHz T For more information on available standard versions see online data sheet See also Configuration Options e500 PowerPC core with MMU and double precision embedded scalar and vector floating point APU Integrated Nor
63. s are routed to one D Sub connector Connector types 9 pin D Sub plug according to DIN41652 MIL C 24308 with thread bolt UNC 4 40 Mating connector 9 pin D Sub receptacle according to DIN41652 MIL C 24308 available for rib bon cable insulation piercing connection hand soldering connection or crimp connection Table 8 Pin assignment of 9 pin D Sub COMT LANG plug connector EM9 Standard version COM1 Option with COM2 1 o9 1 6 2 COMI RXD 6 2 COM1_RXD So 7 COM1_RTS 3 COM1_TXD 7 COM2 TXD 3 COM1_TXD le S 8 com1_cTs 4 X 8 COM2 RXD 4 9 5 GND 9 5 GND Connection via J3 Onboard I O Connector EM9A See Chapter 2 10 I O Connector J3 EM9A on page 35 MEN Mikro Elektronik GmbH 34 20EMO9 00 E4 2010 02 01 Functional Description 2 10 O Connector J3 EM9A EM2A has no front connectors Instead the serial interfaces COM1 COM2 and the physical Ethernet lines for LAN1 to LAN3 are led to onboard connector J3 J3 is a board to board connector that directly leads the interfaces to the carrier board Its pin assignment complies with the ESM Embedded System Module Specification Connector types 4 row 60 pin PCI 104 receptacle connector 2mm pitch e g Samtec SQT 115 01 F Q Mating connector 4 row 60 pin PCI 104 plug connector 2mm pitch For the position of connector J3 on the board see Chapter 1 1 Map of the Board on
64. s used as host bridge and memory controller for the PowerPC processor All transactions of the PowerPC to the PCI bus are controlled by the host bridge The FRAM and boot Flash are connected to the local memory bus of the integrated host to PCI bridge The PCI interface is PCI bus Rev 2 2 compliant and supports all bus commands and transactions Master and target operations are possible Only big endian operation is supported 2 6 2 Local PCI Bus The local PCI bus is controlled by the integrated host to PCI bridge It runs at 66 33 MHz The I O voltage is fixed to 3 3V The data width is 32 bits The FPGA is connected to the local PCI bus MEN Mikro Elektronik GmbH 27 20EMO9 00 E4 2010 02 01 Functional Description 2 7 Memory 2 7 1 DRAM System Memory The board provides up to 2 GB onboard soldered DDR2 double data rate SDRAM on eight memory components The memory bus is 8 bits wide and operates at up to 300 MHz physical depending on the processor type 2 7 2 Boot Flash The board has 16 MB of onboard Flash It is controlled by the CPU Flash memory contains the boot software for the MENMON operating system bootstrapper and application software The MENMON sectors are software protected against illegal write transactions through a password in the serial download function of MENMON cf Chapter 4 5 1 Update via the Serial Console using SERDL on page 51 2 7 3 NAND Flash The board includes up to 1 GB soldered NAN
65. sion 6 working draft 1995 Accredited Standards Committee X3T10 MEN Mikro Elektronik GmbH 74 20EMO9 00 E4 2010 02 01 Appendix 6 2 Finding out the Board s Article Number Revision and Serial Number MEN user documentation may describe several different models and or hardware revisions of the ESM You can find information on the article number the board revision and the serial number on two labels attached to the board Article number Gives the board s family and model This is also MEN s order ing number To be complete it must have 9 characters Revision number Gives the hardware revision of the board Serial number Unique identification assigned during production If you need support you should communicate these numbers to MEN Figure 7 Labels giving the board s article number revision and serial number Complete article number 15EMO9 00 O 00 00 00 ts 8641517 Revision number Serial number MEN Mikro Elektronik GmbH 75 20EMO9 00 E4 2010 02 01
66. tartup as a string of MENMON commands For example if the user selects Int CF NAND Ether None the mmstartup string will be set to DBOOT 0 NBOOT TFTP You can view and modify this string directly using the Expert Setup Menu option Startup string or through the command line command EE MMSTARTUP T See also MENMON 2nd Edition User Manual for further details 4 4 Calibrating the Touch Screen You can enter the touch panel calibration function through the Setup Main Menu This function is also entered automatically during the self test if you hit the touch screen at any position outside the Setup button You may have missed the Setup button because the touch panel was incorrectly calibrated Follow the instructions on the screen to complete calibration F See also MENMON 2nd Edition User Manual for further details MEN Mikro Elektronik GmbH 50 20EMO9 00 E4 2010 02 01 MENMON 4 5 Updating Boot Flash NAND Flash SDRAM and EEPROM Primary MENMON is hardware protected 4 5 1 Update via the Serial Console using SERDL You can use command SERDL to update program data using the serial console The following table shows the ESM locations Table 17 MENMON Program update files and locations File Name F Password for Extension Typical File Name SERDL Location SMM MENMON EMO09 SMM MENMON Secondary MENMON FPO EMO09 001CO05B1 FPO FPGAO FPGAO code 33 MHz PCI clock
67. thbridge and Southbridge Memory e 2x32KB L1 data and instruction cache 512KB 256KB L2 cache integrated in MPC8548 MPC8543 Up to 2GB SDRAM system memory Soldered DDR2 Up to 300 MHz memory bus frequency depending on CPU Upto IGB soldered NAND Flash FPGA controlled 32MB additional DDR2 SDRAM FPGA controlled e g for video data and NAND Flash firmware 16MB boot Flash 128KB non volatile FRAM Serial EEPROM 4kbits for factory settings Mass Storage Parallel IDE PATA One port for hard disk drives Available via I O connector J2 FPGA controlled PIO mode 0 and UDMA mode 5 UDMA100 support Upto IGB soldered ATA NAND Flash FPGA controlled Graphics Available via I O connector J2 FPGA controlled e 800 x 600 60Hz 75Hz 6 bit RGB Vo Three Ethernet channels Three 10 100 1000Base T Ethernet channels with MPC8548 E Two 10 100 1000Base T Ethernet channels with MPC8543 E On board to board connector J3 MEN Mikro Elektronik GmbH 6 20EMO9 00 E4 2010 02 01 Technical Data Two RS232 UARTs COMI COM2 On board to board connector J3 Data rates up to 115 2kbits s 16 byte transmit receive buffer Handshake lines CTS RTS Further I O depending on FPGA configuration FPGA e Standard factory FPGA configuration Main bus interface Interrupt controller reset controller 162070 IDEDISK IDE controller for NAND Flash 1672043 SDRAM Additional SDRAM controller 32MB DDR
68. tronik GmbH 20EMO9 00 E4 2010 02 01 Map of the board EM9 top view nanne 22 Map of the board EM9A top view 00 ee eee ee eee 22 FPGA Block diagram exemplary 0 000002 ee eee 44 MENMON State diagram Degraded Mode Full Mode 47 MENMON State diagram main state llle eese 48 MENMON Position of abort pins on debug connector 60 Labels giving the board s article number revision and serial number 75 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 MEN Mikro Elektronik GmbH 20EMO9 00 E4 2010 02 01 Processor core options on EM9 EM9A nn 26 Signal mnemonics of Ethernet interface 29 Pin assignment and status LEDs of RJ45 Ethernet connectors LAN1 3 EMO e aren tien setted n Rep ehals ROS Eger EEE hams ieee ex 30 Pin assignment of 9 pin D Sub Ethernet plug connector LANI 2 EMO c ussemati dueni ave ka entree hp eR Ran eap aue mte Rs 30 Pin assignment of 9 pin D Sub Ethernet plug connector LAN3 COM1 EMO EET EE 31 Signal mnemonics of UART interfaces en 33 Pin assignment of RJ45 UART connector EM9
69. ular purpose nor does MEN assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts MEN does not convey any license under its patent rights nor the rights of others Unless agreed otherwise MEN products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur Should Buyer purchase or use MEN products for any such unintended or unauthorized application Buyer shall indemnify and hold MEN and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that MEN was negligent regarding the design or manufacture of the part Unless agreed otherwise the products of MEN Mikro Elektronik are not suited for use in nuclear reactors o

20EM09-00 E4 User Manual - Diamond Point International

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