dg24 manual - RTD Embedded Technologies, Inc.
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1. ma mu wa we me 1s es 44 When bit 7 of this word is set to 0 a write can be used to individually program the Port lines Set Reset Bit Set Reset Function Bit Bit Select 0 set bit to 0 0 active 000 PCO 1 set bit to 1 001 PC1 010 PC2 011 100 PC4 101 5 110 PC6 111 PC7 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 0 X X X 0 0 0 1 Sets PCO to 1 written to BA 3 X don t care Set Reset Set PCO Function Bit Bit Select 000 PCO Programming the DG24 This section gives you some general information about programming and the DG24 board and then walks you through the major DG24 programming functions These descriptions will help you as you use the example programs included with the board All of the program descriptions in this section use decimal values unless otherwise speci fied DG24 is programmed by writing to and reading from the correct 1 O port locations on the board These ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports2. A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of PCg input Operations STB Strobe Input A low on this input loads data into the input latch Input Bufter Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with Controlled by bit set reset of PC4 3 136 intel 82 55 PL DDD ef 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 PERIPHERAL Bus 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF MASK STB RD e MASK ACK WR Veo eat re 3 137 intel 82C55A MODE 2 AND MODE O INPUT MODE 2 AND MODE 0 OUTPUT CONTROL WORD CONTROL WORD D 0 D D D D D D 0 D 0 0 0 D 0 Ll bel fro 11969 Jo fro 1 INPUT 1 INPUT MODE 2 AND MODE 1
3. DG24 User s Manual 1509001 and 9100 Certified Real Time Devices Inc Accessing the Analog World DG24 User s Manual REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 Copyright O 1992 by Real Time Devices Inc All rights reserved Printed in U S A Rev 9234 Table of Contents A N ee 1 3 What Comes With Your Board i 3 Board ACCES es acid 1 3 Using This Me ha IT TA i 3 When You Need i 4 CHAPTER 1 BOARD SETTINGS cccsscsssescscssssscssscsscsossvsscessssssessecessessessesessesevsessesenscececseceesereee 1 1 Factory Configured Switch and Jumper Settings 1 3 P2 Base Address Factory Setting 300 hex 768 decimal 1 4 Interrupt Source and Channel Select Factory Setting Disabled 20 1 4 Digital I O Direction Model DG24 B Only Factory Setting 1 5 P5 Pull up Pull down Select Factory Setting 5 Pull up 1 5 51 52 53 Buffer Bypass Switches DG24 B Only Factory Setting OPEN Not Bypassed 1 6 Pull up Puli down Resistors on Digital Input Lines RN1 RN4 1 8 Pull down Resistors on Buffered
4. Voc to Note 1 lOFL Output Float Leakage Current 10 pA Vin Voc to OV Note 2 Darlington Drive Current Note 4 Ports A Rext 5000 Vext 1 7V IPHL Port Hold Low Leakage Current 50 300 pA Vout 1 0V Port A only Port Hold High Leakage Current Vout 3 0V Ports A Port Hold Low Overdrive Current 5 pa Vout 0 8V LM Port Hold High Overdrive Current Vout 30 NOTES 1 Pins Ay Ao CS WR RD Reset 2 Data Rus Ports 5 3 Outputs open 4 Limit output current to 4 0 mA 5 5V Vin or GND Port Conditions Open High Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High Voc Supply Current Standby 3 141 OS intel 82C55A CAPACITANCE 25 C GND OV Symbo Parameter Min units Conditions en 9 Unmeasured pins fo 1 2 5 NOTE 5 Sampled not 100 tested A C CHARACTERISTICS 0 to 70 C Vcc 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE Conditions tan Address Stable Before ADJ ee taa RDPusewian wo tor 75 m tay Recovery Time between RD WA zo ns WRITE CYCLE
5. LOWER 1 INPUT 0 OUTPUT PORT B 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE O MODE 1 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout contro signal definition vs PC layout and complete functional flexibility to support almost any device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appii cations When Port C is being used as status control for Port Aor B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 contro signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C GIT SELECT 612131416
6. PBo 7 20 22 VO PORT PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer WR WRITE CONTROL This input is low during CPU write operations No 0 8 9 Ao RD WR CS input Operation Read 13 Lo Senror Word Data us po fs pt to f fo DaaBus Ponc 1110111 0 _ Tb LX x Databus 3 Ste 4 bit port contains 4 bit latch and it can be used for the control signal outputs and status signal inputs conjunction with ports 20 _ SYSTEMPOWER 6v PowerSuppy _ xal Lind EIE iid System data bus buffer and an 8 bit data input latch TR 23 34 3 125 Ve 9 intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82 55 is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose 1 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buf
7. The 8255 programmable peripheral interface PPI can be easily configured to solve a wide range of digital real world problems This high performance TTL CMOS compatible chip has 24 parallel programmable digital lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines The PPI has three modes of operation Mode 0 Basic input output Provides simple input and output operations for each port Data is written to or read from a specified port Mode 1 Strobed input output Provides a means for transferring I O data to or from Port A or Port B in conjunction with strobes or handshaking signals Mode 2 Strobed bidirectional input output Provides a bidirectional means of communicating with another device on a single eight bit bus Handshaking signals are similar to mode 1 This mode applies to Port A only In Mode 0 all four ports B C lower and C upper are available as I O lines Sixteen configurations are possible in this mode and any port can be configured as an input or an output The outputs are latched but the inputs are not latched In Mode 1 the four ports are grouped into two groups Each group contains one eight bit data port Port A or Port B and one four bit control data port Port C lower or Port C upper which is used for control and status of the eight bit port The eight bit data port in each group can be con
8. The table below shows you how to read from and write to I O ports using some popular programming languages we Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the I O ports on the DG24 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB a b c a b c MOD DIV AND OR a b MOD c a xbDIVc b AND c a bORc BASIC MOD backslash AND a bMODc a b c a bANDc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the DG24 4 6 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators U
9. 145 intel 82 55 WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8255 DATA FROM DATA FROM PERIPHERAL TO 8255 8256 TO PERIPHERAL DATA FROM 8285 TO 6080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD permissible INTR IBF MASK e STB RD MASK e ACK WR WRITE TIMING READ TIMING DATA BUS 231256 28 231256 27 A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 20 20 gt gt pots lt lt 180 pF as 231256 29 231256 30 Testing inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic 0 Timing Measurements Are Made 2 0V For Vexr Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For Logic 0 The Specification Includes Jig Capacitance 0 45 3 146 APPENDIX D WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid
10. C are not affected by Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and 5TB lines with the Set Reset Port C Bit command will affect the Group A and Group interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION D De Ds Ds D3 D2 Di Do In Mode 0 Port C transfers data to or from the pe t TR ripheral device When the 82 55 is programmed to DEA INTES Era INTRO function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de REN vice Reading the contents of Port C allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D Dg Ds D4 D3 D2 D Do ripheral device and change the program flow ac OB INTEA 1 0 1 O INTRA INTEs INTRa cordingly GROUP A GROUP B There is no special instruction to read the status in formation from Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function Ds Ds 0 D3 02 D Do SAA I I E GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figur
11. Digital Output Lines RNS RN8 1 9 CHAPTER 2 BOARD INSTALLATION 0 4 22 ses sesesesessesssessesse 2 1 Board O 2 3 Extemal VO Connectisssss 2 3 Connecting the Digital IO 2 4 Connecting the External Interrupt 2 4 Connecting the Reset Pin A das 2 4 CHAPTER 3 HARDWARE DESCRIPTION cscccsccosscoecssssecsseesussenecsssssessessessessessssssnssesenscseceeeee 2 1 Digital 8255 Programmable Peripheral Interface 3 3 LIS ns 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING 4 1 Defining the DO Mad 4 3 BA 0 PPI Port A Digital Read Vrite 4 3 1 PPI Port Digital YO Read Write 8 8 4 3 BA 2 PPI C Digital Read Vrite 4 3 3 8255 PPI Control Word Write Only 4 4 Programming the 2024 4 6 Clearing and Setting Bits in Port 4 7 lia dd EA A O 4 8 Digital DO Operations tai 4 8 IntetvuptS iioi diia O 4 8 What TS an i iT 4 8 Interrupt Request Lines 4 8 8259 Programmable Interrupt Controller 4 9 Interrupt Mask Register IMR 4 9 End of Interrupt EOI Command 4 9 What Exactly Happens When an Interrupt Occurs 4 9 Using Interrupts in Your Programs 4 9 Writing Interrupt Service Routine 1 4 9 Saving the Startup Interrupt M
12. OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD I CONTROL WORD D 0 0 D Dy 0 D Op 5 0 0 0 0 0 D 0 DD 231256 21 Figure 16 MODE Y Combinations 3 138 82 55 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used tor control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and line states flag status will appear on the data bus in the PC2 PC4 and 6 bit positions as illustrated by Figure 18 Through a Write Port command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port command nor can the interrupt enable fiags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port Bit command must be used With a Set Reset Port Bit command any Port line programmed as an output including INTR IBF and can be written or an interrupt enable can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port
13. connected to the appropriate signal pin on the I O connector and the low side is connected to a DIGITAL GND P6 pins 1 4 10 and 40 Connecting the External Interrupt The DG24 can receive an externally generated interrupt signal EXTINT through I O connector P6 pin 11 and route it to an IRQ channel through on board header connector P3 Interrupt generation is enabled through hardware When interrupts are enabled a rising edge on the EXTINT line will cause the selected IRQ line to go high and the IRQ status bit will change from 0 to 1 You must take the EXTINT line high until the interrupt routine is serviced Connecting the Reset Drv Pin The RESET DRV pin P6 38 can be used to connect the RESET signal generated by the PC to external circuitry The RESET is an active high signal i e the line goes high during a RESET condition 2 4 CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the major features of the DG24 s 8255 based digital I O This chapter also describes the hardware select able interrupts 3 1 The DG24 provides 24 digital 1 O lines with buffered lines available on the DG24 B model as shown Figure 3 1 This chapter describes the hardware which makes up the digital 1 O circuitry and hardware selectable interrupts a 2 9 9 Fig 3 1 DG24 Block Diagram Digital VO 8255 Programmable Peripheral Interface
14. the written data from Port C through P6 to an external device BA 3 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the configuration Note that the D2 and D6 Mode Select bits should be set for 0 Mode 0 operation in the fully buffered B board The table below shows the control words for the 16 possible Mode 0 Port I O combinations 1 X X X X X X X ed Flag AMA C Lower z Output Mode Select 1 Iu 00 mode 0 mode 1 Port B 1x mode 2 0 output 1 input Port A Ox output Mode Select 1 input 0 mode 0 1 mode 1 Port Upper L _ MB Group A 1 input Sa Port Flow Direction and Control Words Mode 0 Contro Word wesen Upper Port B Lower Binary Decimal A Oups Output Oupa 10000010 10 Output 1000001 es 10001000 we moa 10001001 ser 3100010 m ma mon oma 9910005 wa 9 mp pa 31901000 or 10010019 we w mu owa oma 1001199
15. your board after installation Before using the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your DG24 board Digital VO DIGITAL Simple program the shows how to read and write the digital I O lines BASIC Programs These programs are source code files so that you can easily develop your own custom software for your DG24 board Digital VO DIGITAL Simple program the shows how to read and write the digital lines 4 12 APPENDIX A DG24 SPECIFICATIONS A 1 DG24 Characteristics Typical 25 Interface Jumper selectable base address O mapped Jumper selectable interrupts Digital VO CMOS 82C55 1 6 2 ad dio 24 Logic compatibility 5 Configurable with optional pull up pull down resistors High level output voltage 4 2V min Low level output voltage 0 45V max High level input voltage 2 2 min 5 5V max Low level input voltage 2 0 3V min 0 8V max High level output current Isource Unbuffered 100 uA max B TTL buffer 15 mA max Low level output current 15 Unbuffered
16. 1 3a shows PC3 connected to IRQ3 and Figure 1 3b shows EXTINT connected to IRQ4 It is important to note that the DG24 interrupt sources are not open collector Therefore do not attempt to connect one of these interrupts to any other interrupt output 1 4 E H z z z z a a ul A A Fig 1 3a PC3 Fig 1 3b EXTINT Connected to IRQ3 Connected to IRQ4 wv 1 gt 53938856 582885 gc dc dc c c rc dc gc rc c Fig 1 3 Interrupt Source and Channel Select Jumper P3 P4 Digital VO Direction Model DG24 B Only Factory Setting IN This header connector shown in Figure 1 4 sets the direction input or output of the buffered digital I O lines on the DG24 B board This header is not used if the B option is not installed One jumper is installed for each group of lines Port A Port B Port C lower and Port C upper Installing a jumper vertically across the IN pins configures a group as inputs OUT configures them as outputs One jumper must be installed for each buffered port for proper operation If a particular port is shunted by using the port s DIP switch and removing the corresponding buffer then the jumper on P4 for that port has no effect on operation A CL CH B P4 OUT Fig 1 4 Digital Direction Jumpers P4 P5 Pull up Pull down Select Factory Setting Disabled No Jumpers Installed The DG24 board provides four locations to add res
17. 1 7 mA TTL buffer 24 mA max Darlington drive 1 min 5 mA max Available on any 8 pins on Ports amp A AA Unbuffered 10 yA TTL buffer 20 200 uA esaca eeeeee a 10pF Input capacitance oA naL 10 pF Output capacitance ipio po mlt A E 20 pF Miscellaneous l Os 12V 45V Digital GND PC bus sourced EXTINT RESET DRV Current Requirements 12 mA 5 volts unbuffered 125 mA 5 volts B buffers installed Connectors P6 40 pin right angle shrouded header with ejector tabs Size Short slot 3 875 H x 5 25 W 99mm x 134mm APPENDIX B P6 CONNECTOR PIN ASSIGNMENTS DIGITAL GND 1 2 5 VOLTS 5 VOLTS 3 4 DIGITAL GND DIGITAL GND 5 6 DIGITAL GND DIGITAL GND 7 8 DIGITAL GND DIGITAL GND 99419 DIGITAL GND EXTINT 1 2 DIGITAL GND 9 2 1969 Pas 1709 Paz Par 4969 Pao 2 Pcs Pcs 6363 rca 25966 2 Pci 2268 Pco PB7 2969 PBs PBS 61 62 PB4 6364 2 1 65969 12 VOLTS 6768 RESET DAV 12 VOLTS DIGITAL GND DG24 P6 Connector Mating Connector Manufacturer DG24P6Connector P6 Mating Connector Fujitsu FCN 705Q040 AU M
18. 5 is initialized you can use the digital I O lines to control or monitor external devices Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is retumed to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DG24 board can interrupt the processor when any of the three interrupt sources is enabled jumpers installed on P3 By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition f
19. 67 This function allows the Programmer to disallow ES allow a specific I O device to interrupt the CPU with out affecting any other device in the interrupt struc ture SIT SET RESET FLAG Oe ACTIVE INTE flip flop definition BIT SET INTE is SET Interrupt enable 5 INTE is RESET Interrupt disable Figure 7 Set Reset Format EIS ES Note Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82 55 Operating Modes Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports e Any port can be input or output Mode 0 Basic input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking e Outputs are latched is required data is simply written to or read from a e inputs are not latched specified port e 16 different Input Output configurations are pos sible in this Mode MODE 0 BASIC INPUT 0 A tao 231256 8 MODE 0 BASIC OUTPUT 231256 9 3 130 82C55A MODE 0 Port Definition MODE 0 Configurations CONTROL WORD 60 2 0 D 0 D 0 CONTROL WORD 01 D 0 0 0 0 D D GRoupA corra Th dowen 0 o output output ouTPUT fo 1 our
20. C Buffer Circuitry Pull up Pull down Resistors on Digital Input Lines RN1 RN4 The 8255 programmable peripheral interface provides 24 parallel TTL CMOS compatible digital I O lines which can be interfaced with external devices The lines are divided into four groups eight Port A lines eight Port B lines four Port C Lower lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines when they are configured as input ports To use the pull up pull down feature you must first install 10 kilohm resistor packs recommended value in any or all of the four locations RN1 through RN4 as shown in the table below Note that these resistor networks are independent of the pull down resistor networks 5 through RN8 used on buffered output lines as described in the following section Input Port SIP Pack Resistor Network After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs This is done by placing the corresponding jumper on 5 for each port s resistor network across the 5V pins pull up or across the GND pins pull down 1 8 Pull down Resistors on Buffered Digital Output Lines RN5 RN8 When you configure a port to provide buffered outputs you may want to install a pull down resistor network in the appropriate location on the board as shown in the table below to keep the buffered output lines low d
21. CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the inte
22. Continued CONTROL WORD 612 D D D D D D CONTROL WORD 13 D 0 0 0 D D D Operating Modes MODE 1 Strobed input Output This functional configuration provides a means for transferring 1 data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals tra Tan gom an e CONTROL WORD 0 04 D 0 0 D Do CONTROL WORD 615 D 0 D 0 0 0 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group Each group contains 8 bit data port and one 4 bit control data port 8 bit data port can be either input or output Both inputs and outputs are latched e The 4 bit port is used for control and status of the 8 bit data port 3 133 intel 82 55 Input Control Signal Definition MODE 1 PORT A STB Strobe input A low on this input loads data into the input latch CONTROL WORD D 0 D D 0 0 D Oy IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service D D D
23. FCN 707B040 AU B 3M 3417 7040 Robinson Nugent IDS C40PK C SR TG MIL C 83503 M83503 7 09 B 3 APPENDIX C COMPONENT DATA SHEETS 1 Intel 82 55 Programmable Peripheral Interface Data Sheet Reprint intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Control Word Read Back Capability Other Microprocessors m Direct Bit Set Reset Capability High Speed Zero Wait State Operation with 8 MHz 8086 88 and Eo nenn Available in 40 Pin DIP and 44 Pin PLCC 24 Programmable 1 Pins as va m Low Power CHMOS Standard Temperature Range Completely Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 MODE 0 each group of 12 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt contro signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s adv
24. Test CA gt on twa Address Hold Time After WA 1 Ports amp Fm E ETT tow Data Setup Time Before WRT 10 LE Data Hold Time AfterWAT 30 PorsA amp B 30 n Poc 3 142 intel 82 55 OTHER TIMINGS 82 55 2 Parameter ETARE Test WR 1tooup Peripheral Data Betore RD Peripheral Data After 0 ACKPuseWidh 20 tsr STBPusewitn 100 20 Per Data Before STB High Per Data After STBHigh top ACK 0to0BF 1 STB 0t0IBF 1 AD ttowr 0 STB 1to0IwTR 1 wr ACK ttoinTR 1 wo m S wr zo 6 Reset Pulse Width 590 ns seenotez NOTE 1 INTA T may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum N 3 143 inte 82 55 WAVEFORMS MODE 0 BASIC INPUT C A1 Hl 1 LL O O ore 231256 22 MODE 0 BASIC OUTPUT 3 144 82 55 WAVEFORMS Continued MODE 1 STROBED INPUT Ro INPUT FROM PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT 231256 25 3
25. USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE DG24 Board User Selected Settings Base I O Address hex decimal Interrupt Channel Selection 8255 PC3 IRQ Channel 8255 PCO 1 Channel EXTINT IRQ Channel
26. anced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82 55 is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are tor pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82 55 Table 1 Pin Description Pin Number Symbol Dip PLCC Type Name and Function PA3 0 PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to respond to RD and WA signals RD and WR are ignored otherwise ADDRESS These input signals in conjunction RD and WA contro the selection of one of the three ports or the contro 7 4 10 13 11 13 15 PORT PINS 4 7 Upper nibble an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port and 14 17 16 19 PORTC PINS 0 3 Lower nibble of Port RESET RESET A high on this input clears the control register and all ports are set to the input mode word registers can be divided into two 4 bit ports under the mode control Each
27. ar a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 25 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits O to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the DG24 board functions Initializing the 8255 PPI Before you can operate the DG24 the 8255 must be initialized This step must be executed every time you start Up reset or reboot your computer The 8255 is initialized by writing the appropriate control word to I O port BA 3 The contents of your control word will vary depending on how you want to configure your I O lines Use the control word description in the previous I O map section to help you program the right value Remember that certain modes are not supported when the digital I O lines are buffered B board In the example below a decimal value of 128 sets up the 8255 so that all I O lines are Mode 0 outputs 1 0 0 0 0 0 0 0 or os os 02 Digital VO Operations Once the 825
28. ask Register IMR and Interrupt 1 4 11 Restoring the Startup IMR and Interrupt Vector 4 11 Common Interrupt Mistakes 4 11 Example Programi mec 4 12 Cand Pascal PIOD SHIS see Nee ohne 4 12 BASIE Programs MPH 4 12 APPENDIX A DG24 SPECIFICATIONS cccscscssssesscssscesssesssssssesesssesessesesscvsnsesssnensnsecererecececees A 1 APPENDIX B P6 CONNECTOR PIN ASSIGNMENTS scccsccssssssscssessecesececesesesasesesesesesecereceeee Bo APPENDIX C COMPONENT DATA SHEETS ccccsscsssssecsssssscsssesscesosesesesesesesesesersencececececererese C 1 APPENDIX D WARRANTY PRA D 1 LIST OF ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 1 3 1 Board Layout Showing Factory Configured Settings 1 3 BASE Address Jumper Pi ale 1 4 Interrupt Source and Channel Select Jumper PR 1 5 Digital I O Direction Jumpers P4 1 5 Pull up Pull down Select Jumpers P5 1 5 Port A tds 1 7 Fort B Buffer CA 1 7 Port C Buffer isa 1 8 P6 I O Connector Pin Assignments 2 3 DG24 Block Diagramm un ca A eL 3 3 INTRODUCTION The DG24 is a general purpose digital I O board for use in the PC XT AT or compatible computer Installed within a single short or full size expansion slot in the computer the DG24 featu
29. b 0 5 D 0 INTR is set by the STB is a one IBF is a TAT 7 and INTE is a It is reset by the falling edge of LRD RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of Figure 8 MODE 1 input PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input 3 134 intel 82 55 Output Signal Definition MODE 1YIPORT A Output Buffer Full F F OBF output will go low to indicate that the CPU has written data CONTROL WORD out to the specified port The F F will be set Dy D D 0 D D the rising edge of the WA input and reset by Te To Input being low INPUT ACK Acknowledge input A low on this input informs the 82C55A that the data from Port A or Port has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU MODE 1 PORT 8 INTR Interrupt Request A high this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU a M INTR is set when ACK is a one OBF is a one a a and INTE is a one It is reset by the falling edge of WR INTE Controlled by
30. bit set reset of PCs INTE B Controlled by bit set reset of 2 231256 16 Figure 11 MODE 1 Strobed Output 3 135 intel Combinations of MODE 1 82 55 Port A and Port can be individually defined as input or output Mode 1 to support a wide variety of strobed applications CONTROL WORD D 0 D 0 0 0 0 Leii beii D 12 INPUT PORT STROBED INPUT PORT STROBED OUTPUT CONTROL WORD D D Ds D Dz 0 D Do Ces 1 INPUT 0 OUTPUT RD PORT A STROBED OUTPUT PORT STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus fiow discipline in a similar manner to MODE 1 interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions e Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched e The 5 bit control port Port is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus 1 0 Control Signal Definition INTR interrupt Request
31. d C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one B bit input latch buffer Both pull up and puli down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82C55A BIDIRECTIONAL DATA Gus NOTE NM 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration 3 127 4 en IA nn 82 55 82 55 OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi direc
32. e 17b MODE 2 Status Word Format Alternate Port C Pin Signal Mode Output Mode 1 or STBg Input Mode 1 STB Input Mode 1 or Mode 2 Output Mode 1 or Mode 2 Figure 18 Enable Flags in Modes 1 and 2 interrupt Enable Flag Position INTE INTE A2 INTE 1 3 140 82 55 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 C to 150 C functional operation of the device at these or any other conditions above those indicated in the opera Supply Voltage cnp e EUN tional sections of this specification is not implied Ex Operating Voltage 4 7V posure to absolute maximum rating conditions for Voltage on any input GND 2V to 6 5V extended periods may affect device reliability Voltage any Output GND 0 5V to Voc 0 5V Power Dissipation 1 Watt 2 CHARACTERISTICS 0 C to 70 C 5V 110 GND OV 40 C to 85 for Extended Temperture o a la Vu input Low vottage os os v mae VoL Output Low Voltage Mt a Output High Voltage 3 0 2 5 mA Voc 0 4 100 pA Input Leakage Current Vin
33. e interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 The most common mistake when writing an ISR is forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR 4 11 Example Programs Included with the DG24 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal and BASIC Also included is an easy to use menu driven diagnostics program DG24DIAG which is especially heipful when you are first checking out
34. ed while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This
35. ette with BASIC Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your DG24 package Real Time Devices offers a full line of accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Accessories for the DG24 include the TB40 terminal board and XB40 prototype terminal board for prototype development and easy signal access and the XP40 flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Suppor
36. f these signals in both directions both to and from Port C Buffers may still be used for Ports A and B input or output As with Mode 0 operation buffers cannot be used for Port A or Port if the Mode 1 direction is changed dynamically under software control In this case the appropriate DIP switches must be closed for these ports and the corresponding buffers and P4 jumpers removed Mode 2 Operation When operating the 8255 in Mode 2 the lines of Port A must be bidirectional and the lines of Port C function as control lines some as outputs and some as inputs When using Mode 2 both the Port A and Port C buffers must be removed and bypassed Buffers may still be used for Port B Installing and Removing Buffers Whenever you install a buffer for an 8255 port be sure to OPEN its corresponding DIP switches and set its direction on P4 When removing a buffer CLOSE the corresponding DIP switches and remove the jumper from P4 Figure 1 6 shows the Port A buffer circuitry Figure 1 7 shows the Port B buffer circuitry and Figure 1 8 shows the Port C buffer circuitry CAUTION Remember whenever you close the switches 1 2 or 3 be sure to remove the correspond ing buffers from the board Failure to do so may damage the board DG24 vo SONNESTOR 6 Fig 1 6 Port A Buffer Circuitry DG24 110 6 Fig 1 7 Port B Buffer Circuitry DG24 CONNECTOR PS Fig 1 8 Port
37. fer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The contro word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A em A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the contro word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B an
38. figured as an input or an output Both inputs and outputs are latched Because Port C is used bidirectionally in this mode Port C buffers must be removed from the B board and bypassed for Mode 1 see Chapter 1 3 3 In Mode 2 Port A is an eight bit bidirectional bus and Port C is a five bit control port Port B cannot be used in this mode but is available for use in Mode 0 or Mode 1 while Port is in Mode 2 Both inputs and outputs are latched On the B board Port A and Port C buffers must be removed and bypassed when using Mode 2 see Chapter 1 The PPI is configured by writing a control word to the appropriate I O address location as described Chap ter 4 The control word can also be used to individually set or reset the Port C bits This feature allows any bit of Port C to be set or reset without affecting the other port C bits The PPI can also be used to generate interrupts in Mode 1 or Mode 2 operation In these modes the interrupt enable INTE mask is used to enable the INTRA and INTRB interrupt signals To enhance its capabilities the PPI can be ordered with the B TTL buffer option The buffer circuitry allows the PPI to drive long cables with output signals and provides noise immunity for input signals However as noted above buffers cannot be used for some ports when operating in Modes 1 2 or when dynamically changing the port direction through software control On board DIP switc
39. hat its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot 6 After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer 7 After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External I O Connections Figure 2 1 shows the DG24 s P6 I O connector pinout Refer to this diagram as you make your I O connections DIGITAL GND 1 2 5 VOLTS 5 VOLTS 3 4 DIGITAL GND DIGITAL GND 5 6 DIGITAL GND DIGITAL GND 7 8 DIGITAL DIGITAL GND DIGITAL GND EXTINT DIGITAL GND PAT PAG PAS PAS PA1 PC6 PCS PC4 PC3 PC2 PCI PCO PB7 PB6 PBS PB4 PB3 PB2 PB1 PBO 12 VOLTS RESET DRV 12 VOLTS 6909 DIGITAL GND Fig 2 1 P6 VO Connector Pin Assignments 2 3 Connecting the Digital VO For all digital I O connections the high side of an external signal source or destination device is
40. he DG24 has a header connector P2 which lets you select any one of eight starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address These addresses are from left to right on P2 Hexadecimal me m 9 To change the base address setting remove the jumper from the fifth from right pair of pins 300 hex and using Figure 1 2 as a guide install it in the desired location Record the new base address setting on the table inside the back cover of this manual 3C0 8388988828 P2 Fig 1 2 Base Address Jumper P2 P3 Interrupt Source and Channel Select Factory Setting Disabled This header connector shown in Figure 1 3 lets you connect one of three interrupt sources to an interrupt channel for interrupt generation These sources are PCO which is the INTRB signal from the 8255 PPI PC3 which is the INTRA signal from the 8255 PPI and EXTINT an external interrupt you can route onto the board through the P6 I O connector Each source has two IRQ channels available to avoid contention When selecting the interrupt and channel you desire be sure that the IRQ channel is not used by other devices your computer system Note that it is possible to use more than one interrupt source on the DG24 To connect an interrupt source place the jumper across the desired set of pins Figure
41. hes are included to bypass the buffers When these DIP switches are closed and their corresponding buffers are removed then the I O lines controlled by them are shunted Each of the four ports A B CL or CH is controlled by one DIP switch and buffer Chapter 1 describes how to set the switches and remove buffers Interrupts The DG24 can use any one of three signal sources to generate interrupts These sources which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI and EXTINT an external interrupt you can route onto the board through the P6 I O connector Chapter 1 tells you how to set the jumpers on interrupt header connector P3 and Chapter 4 provides some programming information 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your DG24 board It provides a complete description of the map and a detailed description of programming operations to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming 4 1 Defining the VO Map The I O map for the DG24 is shown in Table 4 1 below As shown the board occupies four consecutive I O port locations The base address designated as BA can be selected using header connecto
42. istor networks to control the state of the Port A Port B Port C lower and Port C upper lines upon reset The PS header connector is used in conjunction with these optional resistor networks to configure them to function as pull ups or pull downs Until a jumper is installed on this header the corresponding resistor network is disabled For each group of signals to be pulled up install a jumper vertically between the 5V pin and the corresponding port pin To pull a group of signals down install the jumper between GND and the corresponding port pin Note that only one jumper can be installed for each group of lines Figure 1 5 shows all ports pulled up resistor networks must be installed at RN1 through RN4 for the pull ups to be active There are no jumpers installed on this header connector when you receive the board a a 2 o 45V N 45V N 45V N 45V PS A CL CH B Fig 1 5 Pull up Pull down Select Jumpers P5 81 82 83 Buffer Bypass Switches DG24 B Only Factory Setting OPEN Bypassed The 8255 be operated in Mode O when buffers installed on the I O lines Mode 1 and Mode 2 operation require some of these buffers to be removed Additionally buffers must be removed from any group of lines when you wish to be able to change direction dynamically through software Table 1 2 shows the ports of the 8255 and their associated buffers and shunt switches Table 1 2 8255 Butters and Shun
43. lain how to change the factory settings Pay special attention to the setting of P2 the base address jumper to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Sets resistor networks RN1 RN4 for Ports A CL amp CH as pull ups 5V or pull downs GND active only when optional resistor packs are installed Digital VO Control Board Ps u von 0555555050 0550650 005550 0555555555 cs 00000000 00000000 a 00000000 5 E SWITCH SWITCH Dooooooo nooooooo 9 DO000000 8 82 0000000000 0000000 0000000 0000000000 7415245 7415243 7415245 4000000000 noooooo w 1000000000 15559655550 055550 055550 5000000050 00000000000000000000 29000000000000000600 00000609 m 20000000 00000000 a w CDE cio cry Real Time Devices inc State College PA 16804 USA An Fig 1 1 Board Layout Showing Factory Configured Settings 1 3 P2 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the DG24 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem t
44. often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259 4 10 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library
45. r P2 as described in Chapter 1 Board Settings The following sections describe the register contents of each address used in the I O map Table 4 1 0624 Map Register Description Read Function Write Function Decimal 8255 PPI Port A 8255 PPI Port Read Port B digital input lines Program Por B digital output BA 8255 PPI Port Read Port C digital input lines Program Port digital ouput ines 8255 PPI Control Word Program PPI configuration BA 3 BA Base Address 0 PPI Port A Digital UO Read Write Transfers the 8 bit Port A digital input and digital Output data between the board and an external device A read transfers data from the external device through P6 and into PPI Port A a write transfers the written data from Port A through P6 to an extemal device BA 1 PPI Port B Digital VO Read Write Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P6 and into PPI Port B a write transfers the written data from Port through P6 to an external device BA 2 PPI Port Digital UO Read Write Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port Lower between the board and an external device A read transfers data from the external device through P6 and into PPI Port C a write transfers
46. res 24 TTL CMOS 8255 based programmable digital I O lines Optional TTL buffered outputs for high driving capability B model Optional pull up pull down resistors e Simple or strobed operation Hardware enabled interrupts IRQ2 IRQ7 BASIC Turbo Pascal and Turbo source code The following paragraphs briefly describe the major function of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Digital VO DG24 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip The unbuffered 8255 can be operated in any one of the 825575 three modes If you have purchased the DG24 B with TTL buffers for high driving capacity the 8255 can be operated in Mode O when the buffers are installed CMOS buffers are available on request Pads for installing and activating pull up or pull down resistors are included on the board Installation proce dures are given at the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your DG24 package DG24 or DG24 B with TTL buffers interface board Software disk
47. rom low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be 4 8 acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by COM2 IRQ4 by COM1 and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the DG24 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for and so on If a bit is set equal to 1
48. routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the DG24 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at 1 O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit O is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled nterrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on If you need to program the source of your interrupts do that next For example if you are using the program mabl
49. rrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being call
50. set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning range of bits is a mixture of setting and clearing operations You can set clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as 4 7 inportb port_address amp 199 40 outportb port address A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to cle
51. sing AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 23 and then write the resulting value to the port In Pascal this is programmed as Vo Port PortAddress OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 29 and then write the resulting value to the port In C this is programmed as v inportb port address v 6 171 outportb port address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be
52. t Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem 1 4 CHAPTER 1 BOARD SETTINGS The DG24 board has jumper settings you can change if neces sary for your application The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Note that DIP switches S1 S2 and S3 has been provided to bypass the 8255 buffers if you have the DG24 B buffered model Also note that by installing resistor packs at RN1 RN4 and setting the jumpers on 5 you can configure your digital input lines to be pulled up or pulled down This procedure is explained near the end of this chapter RNS through RN8 are provided to install resistor packs for ports configured as buffered outputs These pull down resistor packs are described at the end of this chapter 1 1 1 2 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumper and switches on the DG24 board Figure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs exp
53. then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H mos mos maa mas mor imao For all bits 0 IRQ unmasked enabled 1 masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to port 20H What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DG24 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at
54. tional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis CONTROL BUS DATA BUS 8 A Uo vo CONTRO CONT mes ORO BI DIRECTIONAL PATAS CONTROL 231256 5 Figure 5 Basic Mode Definitions and Bus interface CONTROL WORD PORT C
55. to REAL TIME DEVICES replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO
56. ts Buffer Buffer Location Type Al EN Mode 0 Operation If the direction of a port configured for Mode 0 operation is changed dynamically through software all of the switches on the corresponding DIP switch must be set to the CLOSED position and the buffer must be removed for that port This is required because the buffers are hardware configured for a particular direction using the jumper at P4 Therefore their direction cannot be changed through software When removing the buffer also remove the corresponding jumper on P4 After closing the DIP switches carefully remove the corresponding buffer from the printed circuit board Locate the port that requires a DIP switch shunt in Table 1 2 then note the component labels of both the buffer and the associated DIP switch to verify that all settings are as desired In the event that shunts are required for only one half of Port C the switches on DIP switch S3 can be closed in groups of four Determine their positions from Table 1 2 then close the appropriate group of switches Only the buffer corresponding to the half of Port C that requires shunts must be removed refer to the table for its location Mode 1 Operation When operating a group of lines in Mode 1 some of the Port C bits are used as hand shaking signals Therefore the buffers that are installed at locations U6 and U7 must be removed and DIP switch S3 must have all switches closed to allow for the transmission o
57. ur output 1 fo 1 2 input fo ourur ourrur Pur o 1 pur 4 ourrur o 1 1 ourur 5 output o 1 ourrur 6 INPUT OUTPUT o 1 1 1 ouput wer v 1 0 output output a o 1 meur ourur e output ieu 3 o pur oureuT 3 o meur ourur wur 1 weur 12 output L3 1 1 meur 13 L3 1 imeut 14 weur output 3 1 1 meur meur 15 GROUP B CONTROL WORD 62 D 0 0 0 Do CONTROL WORD D 0 0 D D D D 231256 10 3 131 MODE 0 Configurations Continued CONTROL WORD 64 D D 0 D 0 O D D CONTROL WORD 06 0 0 0 0 0 0 0 D CONTROL WORD 66 D 0 D 0 0 D D CONTROL WORD D D 0 0 D D 82 55 3 132 CONTROL WORD 68 D D 0 D D D 0 0 CONTROL WORD 6 D 0 D 0 0 0 Do CONTROL WORD 10 0 De D 0 D D D 0 CONTROL WORD 611 D 0 0 0 0 D D D 231256 11 intel 82 55 MODE 0 Configurations
58. uring the time between system power up or reset and initialization of the A recommended value of resistance for these pull downs is 10 kilohms Buttered Output SIP Pack Resistor Network 1 9 CHAPTER 2 BOARD INSTALLATION The DG24 is easy to install in your IBM PC XT AT It can be placed in any slot short or full size This chapter tells you step by step how to install and connect the board Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 Turn OFF the power to your computer 2 Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this 3 Select any unused short or full size expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag 5 Holding the board by its edges orient it so t
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