Home

HY16F19 Series User manual

1. 171 21 3 uere etse Fete ae 171 22 XA24 BIT A D CONVERTER 178 22 1 description osisssa naaa 178 22 2 Registef address m 188 223 R gister TUNC ioni f Pct t Fete e ER tu teda 188 224 Model program tb Race Rae ea 193 22 5 Modell program f rictiOni 1 i Pt Ent YR au dee Eg ERR 195 REBWVEUDCVYN UTT X 197 231 Overall description ecce Eee te tener De stake ea tedden neu e 197 23 2 eenchabcIid 202 23 3 Register function oe eee reenter ne reer e nennen enr nenne 203 29 4 Model program flow rct ee aM ME eu d 206 23 5 Model program furictiOri iiie recited enin eu Red 207 www hycontek com page6 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 23 6 Model program description 207 23 7 OPAMP application circuit 208 23 8 OPAMP application circuit system ll 208 23 9 OPAMP ap
2. ER ER EE Rd 111 13 6 Model program description 112 IE XEOJUBMVAULWEVYOIDUI V 113 14 1 Overall description oet e a aed ome uh 113 14 2 Register address edet SE eR RARE E 114 14 3 RegiterTunctlon ui Reti e HR RR EE Pa ace 116 15 GPIO PT3 MANAGEMENT E 119 15 1 entere 119 15 2 Register address uon neret Bx PX x donem 120 15 3 Register 120 16 GPIO PTG MANAGEMENT iiid cris ossa succ nra DER 123 16 1 Qverall descriptiOn orent eee tone Eee e 123 16 2 Register address rer tee Ded nace te eee eae cae ei eee 125 16 3 Register function ce nr nr ee ee nnns ndn nene eren nennen 125 17 7 DA Re OU da DV DERE 133 TEA Overall description e er Ret RR RR EFE RN ERE E EE 133 17 2 Register address 1 nn ne nenne eren nennen 135 16
3. The program starts Initialization settings Timer C settings Wait for interrupt Interrupt the subprogram Clear the interrupt flag Reverse the Return to the main program 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page104 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 12 5 Model program function Use the Timer C interrupt Each the Timer C interrupt will reverse the IO Ex it is 0x5 before the interrupt it is OxA after the interrupt 12 6 Model program description 00 01 Zinclude HY16F19X h 02 03 junsigned int i 04 05 int main void 06 07 0 05 08 DrvGPIO Open E PT2 0x0FE IO OUTPUT 2 0 3 Set Output 09 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 10 11 DrvTMBC CIk Source 0 0 Prescaler 1 12 CK clock source 13 110 clock divider 1 14 15 DrvTMB Open E TMB MODEO E TMB NORMAL OxFFFF Timer B overflow OxFFFF 16 17 DrvCapture1 Open 2 14 1 TimerCO use as Capture 1 18 llinput source selection 19 1218 CK 20 14 16384 1 Positive edge trigger 21 22 DrvCapture2 Open 1 1 1 use
4. Bit Name Description PT10 3 Output Enable Bit 19 PT103OE 0 Disable 1 Enable PT10 3 Input Enable Bit 18 PT103IE 0 Disable 1 Enable PT10 3 Output Data Bit 17 103000 Output Low 1 Output High PT10 3 Input Data Bit 16 PT103DI 0 Input Low 1 Input High PT10 2 Output Enable PT1020E 0 Disable 1 Enable PT10 2 Input Enable Bit 2 PT102IE 0 Disable 1 Enable PT10 2 Output Data 102000 Output Low 1 Output High PT10 2 Input Data Bit O PT102DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page167 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash neste When LCD Mode GPIO Base Address 0x94 0x40894 SEGO SEG1 PT10 Control Register 1 31 24 23 22 21 20 19 18 16 SEG1 Data Bit 1508 7 6 59 B m 0 Nam MASK O Bit Name Description LCD Segment 1 Data support 1 3 or 1 4 or 1 5 duty mode Segment Data LCD Segment 0 Data support 1 3 or 1 4 duty mode Segment Data Bit 20 16 SEG 1 Data Bit 3 0 SEG 0 Data 0 16 198 01 2014 HYCON Technology Corp page168 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash
5. 275 30 1 275 30 2 Register address ec 278 30 3 Register TUNCHON cu dat esaet ee tb e uat 279 30 4 Model program cer aec e ch e eee de eO Reed C eL ERE de 291 30 5 Model program UNCON 291 30 6 Model program descriptlOn rtt oe ttn a 291 31 POWER SAVING MODE INTRODUCTION 293 31 1 293 31 2 Interrupt point 2 293 31 3 Register TUDClOn 294 32 LCD DRIVER m M RSS 296 32 1 296 32 2 LCD initialization configuration 297 32 3 Register address cesi ner eee ail diel iat 297 32 4 Rogister function eii de een e i dr 298 33 MODIFICATION 301 www hycontek com page9 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHN
6. The tens place of the month BCD code format Bit 4 10MO 0 0 1 1 Bit 3 0 1MO The one s place of the month BCD code format 0000 0 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page284 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid gt 30 3 6 Hardware RTC register RTCDWC Base Address 0 14 0x41A14 RTCDWC Date and week Control Register For calendar 31 24 21 20 Name MASK ROW 0 o it 15 08 ame MASK ROW 0 8 Bit Name Description The tens place of the date BCD code format 00 0 Bit 21 20 10DAT 01 1 10 2 11 3 Bit 19 16 1DAT The one s place of the month BCD code format 0000 0 0001 1 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page285 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid Bit 2 0 000 Sunday 001 Monday 010 Tuesday WDA 011 Wednesday 100 Thursday 101 Friday 110 Saturday
7. CMPO CPDA 3 0 CPDN 3 0 CMPO CPDA 3 0 CPDN 3 0 Output Hysteresis Output Hysteresis status switch period status switch period 0 uuuu 0 Ouuu 0000 1000 1 uuuu 1 1uuu 0001 0 uuuO 1001 0 OuuO 1 uuu 1 1uu1 0010 0 uuOu 1010 0 OuOu 1 uu1u 1 1u1u 0011 0 uu00 1011 0 0u00 1 uu11 1 1u11 0 uOuu 0 0100 1100 1 1 1 11uu 0 uOuO 0 00u0 0101 1101 1 u1u1 1 11u1 0 uOOu 0 000u 0110 1110 1 u11u 1 111u 0114 0 4000 1111 0 0000 1 u111 1 1111 Table 25 1 Hysteresis control CPDM 3 0 configuration and values 25 1 3 Comparator output The output of the comparator is digital output and it will reach the IO pin PT1 7 therefore the output of the comparator should set the IO to serve as the output mode The output of the comparator can be set to pass through the 2us low pass filter to eliminate the peak pulse interference If the control bit CPDF is set as 1 the output of the comparator will pass through the 2us low pass filter if the control bit CPDF is set as 0 it will not pass through the filter polarity of the comparator can be set by the control bit 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page218 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash Ifthe is set as lt 1 gt the output the comparator will be opposite in phase if the
8. program starts Initialization setting Detect PT1 1 Is the value higher than OXF 13 5 Model program function Press the PT1 1 for one time will add the LED by 1 If the LED is added OxF it will be reset to 0 Then Press the PT1 1 for one time will add the LED by 1 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com 111 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash 13 6 Model program description HYG N HYCON TECHNOLOGY 01 include HY16F19X h 03 Delay unsigned int num 05 int main void 06 07 unsigned int 0 0 08 DrvGPIO Open E 1 0 02 IO INPUT Set PT1 1 INPUT 09 DrvGPIO Open E 1 0 02 IO PullHigh Enable PT1 1 pull hi R 11 DrvGPIO Open E PT2 0x0FE IO OUTPUT Set 2 0 3 OUTPUT 13 while 1 15 i DrvGPIO GetBit E PT1 1 Read PT1 1 high or low 16 if i 0 PT1 1 is low 18 DrvGPIO_SetPortBits E_PT2 j 11 J gt OxF J 0 19 if j gt OxOF j 0x00 22 Delay 0x8000 23 25 Delay unsigned int num 27 int a for a 0 a lt num at Delay loop 28 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page112 16 19 series user manual HYGON 21 bit ENOB ZAADC gt
9. 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 Input High PT9 0 Output Enable Bit 3 PT900E 0 Disable 1 Enable PT9 0 Input Enable Bit 2 PT9OIE 0 Disable 1 Enable PT9 0 Output Data PT90DO 0 Output Low 1 Output High PT9 0 Input Data Bit 0 PT90DI 0 Input Low 1 Input High When LCD Mode GPIO Base Address 0x80 0x40880 Symbol SEG26 SEG27 PT9 Control Register 0 31 24 23 22 21 20 19 18 16 Name E SEG27 Data RW 1 WD LE IE T ea SEG26 Data Bit Name Description LCD Segment 27 Data Segment Data LCD Segment 26 Data Segment Data Bit 21 16 SEG 27 Data Bit 5 0 SEG 26 Data 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page156 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 19 3 2 9 2 9 3 register When GPIO Mode GPIO Base Address 0x84 0 40884 Name MASK 9 9 93 Bt 501 7 68 0 Bit Name Description PT9 3 Output Enable Bit19 0 Disable 1 Enable PT9 3 Input Enable Bit 18 PT93IE 0 Disable 1 Enable PT9 3 Output Data PT93DO 0 Output Low
10. VDD3V VLCD VDDA UR Reinir HSXT Enable ENOHS 2 6 2 8 3 0 3 3 CKHS 2 20M HSXT E 4 Hz 2 20 HSXT HS CK EN VEDI VODA 41457 SEL VDDA 10 2 4 27 3 0 3 3 EN gt 0 HAO 1 0 2 410 6 HSRC EE HAOTR 7 0 MHz EN VCM ADC common 1 voltage MT REFO 1 INH 3 0 0000 0001 0010 0011 0100 0101 Aloo 1 AlIO2 4 3 1 VDDA 1001 04 05 06 7 R gt 00 PGAGN 2 0 R INL 3 0 AIO1 AIO2 VI SHORT AIO0 PGA off x8 x16 x32 p r ENADC ADCCLK 0 L ADFDR ADGN 1 0 gt AAD SEx1 Xx2 XR x4 AIO3 1 02 5 0 5 1 4 5 AIO6 7 R INL SI m VR x1 x VRSHR lt vppa 001 Alo2 01 AlO4 10 REFO 11 VSSA 00 AIO3 01 AIO6 10 REFO 1112 VDDA quio ENACD ADCD 0 CFRST OSR 3 0 3201 A CO 31 0 ADCIF Interrupt HW2 Interrupt CIF Signal AD HW2 Interrupt Vector ENADC 1
11. 0 1 lint main void 2 3 Displaylnit 4 ClearLCDframe 5 InitUartPort 6 temp 0 7 Buffer_Start 0 8 DrvGPIO Open E 1 0 02 IO INPUT 9 DrvGPIO Open E PT1 0x02 E IO PullHigh 10 11 while 1 12 13 i DrvGPIO_GetBit E_PT1 1 read PT1 1 pin high or low 14 if i 0 15 16 DrvUART Enablelnt 1 1 17 Delay 0x8000 18 19 Delay 0x8000 20 LCD DATA DISPLAY temp 21 22 Subprogram 0 1 InitUartPort void 2 3 DrvGPIO Open E PT2 0x01 E IO OUTPUT PT1 0 output TX 1 4 DrvGPIO Open E PT2 0x02 E IO INPUT IIPT1 1 input RX 1 5 DrvCLOCK EnableHighOSC E EXTERNAL 50 HSXT 6 DrvUART ClkEnable 0 0 En UART Int 7 outw 0x40e00 0 65 00 8 outw 0x40e04 0 00 llur 04 outw 0x40e08 0 68 Set the baud rate is 3 9600 10 DrvUART ConfiglO 1 2 Set the Tx Rx as the IO 11 DrvUART Enablelnt 0 1 Enable the RX interrupt 12 13 asm volatile sethi r0 0 0000 14 asm volatile ori 0 0 Ox003f 15 asm volatile mtsr r0 INT MASK 16 asm volatile movi 0 0 70009 17 asm volatile mtsr r0 PSW 18 19 HWO ISR void 20 21 int a 22 a inw 0x40000 amp 0x08 amp amp inw 0x40000 amp 0x080000 DrvUART_GetTxFlag 23 24 25 i temp 26 outw 0x40e0c lt lt 16 TX set Buffer 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page254 HY16F19 series user man
12. 31 POWER SAVING MODE INTRODUCTION 31 1 Overall description The paragraph will describe different power modes and their corresponding function modules Under the active mode all peripheral circuits can be enabled and the clock of the MCU is HS CKorLS CK clock under the mode the system can freely switch to other modes and have shortest response time Under the low power mode all analog circuits can be enabled and the clock of the MCU is LS CK clock under the mode the MCU works under the lowest frequency and the system can switch to other modes by executing instructions There are four power saving modes able to make the MCU stop executing instructions These modes can be disabled by the interrupt Once the interrupt is triggered the internal 2MHz clock source will be enabled then the MCU will word under the clock source and the system will leave these power saving modes Before entering the power saving modes the chip should enable anyone of the interrupt vectors or the power saving effect cannot be achieved particular under different power saving modes only some function modules can be enabled and only some functions can waken the chip from the power saving modes For example under the sleep mode the timer interrupt is invalid and the chip can be wakened only by the communication interrupt IO port external interrupt and reset 31 2 Interrupt point configuration When the CPU is under different ope
13. VDD3V VDD3V T PT3PU AlOX A 75k PAD PT3DI gt 250 19 _ IOIP U C2 m FIG 15 1 PT3 function block diagram The has the functions of the input output and internal pull up resistors and different functions need to be set by different controllers Internal pull up resistor The controller PT3PU 7 0 can enable or disable the internal pull up resistor of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the port is set as 1 the internal 75k pull up resistor will be enabled if it is set as 0 the internal 75k pull up resistor will be disabled If the IO port is under the input mode and there is no external pull up resistor the internal pull up resistor should be enabled especially in low power consumption mode which can prevent from electric leakage and increase the power consumption If it serves as the analog signal input port it is not necessary to enable the internal pull up resistor Output mode 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page119 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash poderi The controller PT3OE 7 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of
14. 2014 HYCON Technology Corp 0 16 198 01 www hycontek com page165 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash HYCON TECHNOLOGY 1 Enable PT10 0 Input Enable Bit 2 PT100IE 0 Disable 1 Enable PT10 0 Output Data 100000 Output Low 1 Output High PT10 0 Input Data PT100DI 0 Input Low 1 Input High When LCD Mode GPIO Base Address 0x90 0x40890 Symbol SEG34 SEG35 PT10 Control Register 0 31 24 23 22 21 20 19 18 16 SEG35 Data RW RW Bit 15 08 7 0 SEG34 Dat Bit Name Description LCD Segment 35 Data Segment Data LCD Segment 34 Data Segment Data Bit 21 16 SEG 35 Data Bit b 0 SEG 34 Data 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page166 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 20 3 2 PT10 2 PT10 3 register When GPIO Mode GPIO Base Address 0x94 0x40894 Symbol PT102CFG PT103CFG PT10 Control Register 1 31 24 23 22 21 20 19 18 16 0 0 PT103D Bt 1508 7 6 M 0 Name MASK 211020 1020 PTi02bI
15. 21 GPIO MANAGEMENT 21 1 Overall description The chip has multiple universal IO ports and most of them have reuse functions their reuse functions should be controlled by the registers The chapter will introduce the control of the reuse functions of the IO ports Each IO port has multiple reuse functions but only one of these functions can work at a time thus if it is not necessary to use the reuse functions please remember to disable them for other functions However some reuse functions can work together such as PT1 PT2 when they are set as the external input ports they can be set as the input ports of the SPI and UART etc Please note that the above situation is on the condition that they are set as the input ports in this way the external interrupt functions generated by communication can be realized by the communication signals and the external interrupt functions In general the reuse functions should be used on a group basis and only one group can work at a time If the SPI function is used the CS 1 CK 1 MISO 1 and MOSI 1 are the first group and the CS 2 CK 2 MISO 2 and MOSI 2 are the second group and so on When using the SPI the user can select the first group or the second group according to the actual requirements but only one group can work at a time When the user needs use the communication SPI I2C UART and the like the user can set the SPI to use the first group CS 1 CK 1 MISO 1 and MOSI 1
16. 1 0075 m ENCLIN mE 3 CL5 400 Clock Gen K 1 DL 101 CPRLL eec eu gt M 6 14 ne CPIS V d 0 1 gt 208 JE arre ames 2 UR 90 aus L4 4 2 91 5 CH3 10 5 CPPS 1 0 FIG 25 4 Touch button connection diagram One possible configuration 25 1 5 Comparator operation initialization The main function of the comparator is to compare the input signals however different modular combinations need different configurations to achieve different applications As a simple signal comparator Set the operating mode of the CMP to be low power or normal 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page219 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash Select the input channel including the positive input channel negative input channel If the RLO is selected as the positive input channel the reference voltage source and the voltage node of the multi node resistor should be set Enable the output function of the comparator Set whether the output passes through the low pass filter and the output is opposite in phase If the CMP comparison interrupt vector is used the interrupt function of the comparator should be enable
17. 32 bit MCU amp 64 KB Flash hat The CPOL clock polarity is to control the stable status value of the clock without any data transmission It be used in the master mode and the slave mode If the CPOL is 1 high potential the SCK is 1 when the SPI is under the idle mode the other hand if the CPOL is O low potential the SCK is 0 when the SPI is under the idle mode low potential The CPHA clock phase controls the capturing of the data clock edge of the SCK If the CPHA is 1 high potential the second clock edge of the SCK pin I the CPOL is 1 it is the falling edge if the CPOL is 0 it is the rising edge will capture the data of the MSB The data will be locked at the second clock edge of the SCK the other hand if the CPHA is 0 low potential the first clock edge of the SCK pin I the CPOL is 1 itis the rising edge if the CPOL is O it is the falling edge will capture the data of the MSB The data will be locked at the first clock edge of the SCK Therefore the combination of the CPOL and the CPHA can control the data capturing and outputs of the clock edges When CPHA 0 SCK CPOL 1 WU LLL SCK CPOL 0 LITT wen LL LE 2 CS master Capture Time FIG 26 3 SPI active mode clock diagram 0 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page230 16 19 series user manual HYGON 21 bit ENOB Z
18. m Vj Lu T pv v Power Good flag Bit 06 Ferg 0 Normal 1 The Power Good was trigged before CPU Core reset flag Bit 05 Normal 1 ICP Core was trigged before Bit 04 IDLE Idle mode control bit 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page294 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 1 demoe 00002 Sleep Idle Flag low voltage reset or reset circuit reset can clear the bit Bit 03 0 The chip enters the sleep mode or idle mode WDT flag the low voltage reset or external reset can clear the bit Bit 02 The reset or interrupt is generated by the WDT External reset flag the low voltage reset BOR can clear the bit 01 0 1 The RESET PIN reset or ICP software reset has occurred Low voltage reset BOR flag it will be automatically cleared when the voltage of the chip is high than 1 8V Bit OO 00 0 1 The low voltage reset has occurred Setting Description sys 04 0 10 Wait Mode asm syscall 13 sys 04 0 00 asm syscall 12 SYS 04 Address 0 40104 Sleep Mode sys 04 0 10 Idle Mode asm syscall 11 2014 HYCON Technology
19. PTOIE L PT9DO U FIG 19 1 9 function block diagram The 9 has input and output functions and different functions should be set by different controllers Output mode The controller PT9xOE 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT9xDO 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT9xIE 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enabled if it is set as 0 the input mode of the corresponding IO port will be disabled Whether current input mode of t
20. description TEES 57 8 2 5 5 nesciam n i A E 58 8 3 Register 58 8 4 Model prog nanny PR M E EM 59 8 5 Modell program 60 8 6 Model program description 2222222 1 0 10 0 0 aS a aii 61 9 A 62 9 1 62 9 2 Register address ico eee ba a ae 63 9 3 Register 63 9 4 65 www hycontek com page3 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 9 5 Model 65 9 6 Model program description 22222 1 0000000000 10 enne e nne en 66 10 TIMER E 67 10 1 a a 67 10 2 Register address uenit EIC 89 10 3 Register Tunctlon Ree 89 10 4 Model program flow cere itr n
21. 18 2 Register address GPIO Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0x70 0x40870 MASK1 PT81CFG MASKO PT80CFG GPIO Base Address 0x74 0x40874 MASK3 PT83CFG MASK2 PT82CFG GPIO Base Address 0x78 0x40878 MASKS PT85CFG MASK4 PT84CFG GPIO Base Address 0x7C 0x4087C MASK7 PT87CFG MASK6 PT86CFG LCD Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 70 0 40870 MASK1 SEG19 MASKO SEG18 GPIO Base Address 0x74 0x40874 MASK3 SEG21 MASK2 SEC20 GPIO Base Address 0x78 0x40878 MASK5 SEG23 MASK4 SEG22 GPIO Base Address 0x7C 0x4087C MASK7 SEG25 MASK6 SEG24 LCD Register Address 0x41B04 can determine the setting is the GPIO Mode or the LCD Mode 18 3 Register function 18 3 1 PT8 0 PT8 1 register When GPIO Mode Mame 16081 T HIT BOT Bit Description PT8 1 Output Enable Bit 19 PTBIOE 0 Disable 1 Enable PT8 1 Input Enable Bit 18 PT81lE 0 Disable 1 Enable PT8 1 Output Data 17 8100 0 Output Low 1 Output High Bi 16 PT81DI PT8 1 Input Data 0 Input Low 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page145 16 19 series user manual HYGON
22. 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 Input High PT8 0 Output Enable Bit 3 PT80OE 0 Disable 1 Enable PT8 0 Input Enable Bit 2 PT80IE 0 Disable 1 Enable PT8 0 Output Data PT80DO 0 Output Low 1 Output High PT8 0 Input Data Bit 0 PT80DI 0 Input Low 1 Input High When LCD Mode GPIO Base Address 0x70 0x40870 Symbol SEG18 SEG19 PT8 Control Register 0 31 24 23 22 21 20 19 18 16 Neme MAS SEG19 Data RW 1 LE IE IH TB OIBTIT S SEG18 Data Bit Name Description LCD Segment 19 Data Segment Data LCD Segment 18 Data Segment Data Bit 21 16 SEG 19 Data Bit 5 0 SEG 18 Data 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page146 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 18 3 2 PT8 2 PT8 3 register When GPIO Mode GPIO Base Address 0x74 0 40874 Name MASK PTE3DOPTB9DI Bt 501 7 6 0 Bit Name Description PT8 3 Output Enable Bit19 PT83OE 0 Disable 1 Enable PT8 3 Input Enable Bit 18 PT83IE 0 Disable 1 Enable PT8 3 Output Data PT83DO 0 Output Low 1 Output High PT8 3 Input Data Bit 16 PT
23. i Bit Name Description Bit 15 0 TB2CO Timer B2 counter overflow threshold value 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page97 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 11 2 4 Timer B2 register PWM2DOD Base Address 0x30 0 40 30 Symbol PWM2DOD PWM counter overflow condition Control Register 31 16 2 2 3 duty cycle counter overflow value TB2C2 PWM3 duty cycle counter overflow value RW FFFFh 15 0 TB2C1 PWM2 duty cycle counter overflow value RW FFFFh Bit Name Description Bit 31 16 TB2C2 duty cycle counter overflow value Bit 15 0 TB2C1 PWM2 duty cycle counter overflow value 0 16 198 01 2014 HYCON Technology Corp page98 www hycontek com 16 19 series user manual HYGON 21 bit ENOB 32 bit MCU amp 64 KB Flash 12 12 1 Overall description The timer C is designed to execute the capture function which can be used to perform frequency measurement event counting interval time measurement etc It can generate the interrupt signal when the counter overflow takes place and it should be used together with the TMB counter register EN TMC TMCOIF TimerC Frequency TCRO 15 0 Divider CP1PS 3 0 CPHP TMBR 15 0 CP
24. 2 Device ID 2 Address 2 Data 2 Stop 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page271 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash The program starts settings Hardware 2 initialization settings Detect 29 6 Model program function Model name test the hardware 2 Model description HYCON TECHNOLOGY Test the write in function of the hardware I2Cto the AT24C02 via the settings of the 2 pins and the 2 register 29 7 Model program description Main program 00 01 include HY16F19X h 02 03 04 volatile unsigned int i a 05 06 07 int main void 08 1 09 I2C_INI 11 12 while 1 13 14 i DrvGPIO GetBit E PT1 1 PT1 1 pin high or low 15 while i 0 16 17 I2C_Start Hardware 2 Start 18 19 Drvl2C_WriteData OxA0 24 02 Device ID 20 I2C_NACK 21 22 Drvl2C_WriteData 0x00 24 02 Address 0x00 23 I2C_NACK 24 25 Drvl2C_WriteData 0x55 Data1 0x55 Address 0x00 26 I2C_NACK 27 28 Drvl2C_WriteData OxAA Data2 0xAA Address 0x01 29 I2C_NACK 30 31 I2C_Stop Hardware 2 Stop 32 33 l 1 34 35 Delay 0x50 36 37 return 0 38 2014 HYCO
25. 8 3 Register function 8 3 1 WDT register WDTCR SoC Base Address 0x08 0x40108 WDTCR WDT Control Register 30 16 WDTO Bit 15 1 8 m 9 9 020 CLRWDT ENRWDT WDTP RW ROWO RW1 0 RW O RW1 0 RW7 counter register of WDT Bii 30 16 WDTO 0 1 1 interrupt operating mode selection mode 4 Reset Mode it cannot be switched to the Timer Mode again after switched to the Reset Mode WDT reset control Bit 05 CLRWDT 0 0 Disable E Enable Bit 04 ENWDT enable control www hycontek com page58 HY16F19 series user manual HYG N 21 bit ENOB 32 bit MCU 64 KB Flash HYCON TECHNOLOGV 0 Disable 1 Enable It cannot be disabled after enabled WDT overflow value configuration 000 001 010 Bi 2 0 WDTP 011 100 101 110 111 8 4 Model program flow 0 8 WCLK 32 WCLK 128 WCLK 512 WCLK 2048 WCLK 8192 WCLK 32768 gt WCLK 2 1 Overclocking settings only 35KHz is available internal low speed oscillator 2 DrvWDT Open will enable the WDT 4 DrvTIMER ClearlntFlag E WDT means clearing the WDT interrupt flag 3JDrvTIMER Enablelnt E WDT means interrupting enablement of the WDT 5 Timer A B C WDT belong to the HW1 interrupt and the format is void HW1 ISR void
26. RW 0 Bit Description DAC positive input source selection 000 VDD3V 001 VDDA 010 REFOI Bit 5b 4 DAPS 011 OPO 100 AlO4 101 AIO5 110 AIO6 111 AIO7 DAC negative input source selection 000 VSS 001 REFOI Bit 3 2 DANS 010 OPO 011 AIO7 100 111 Rsv DAC output enable control Bit 1 DAOE 0 Disable under high impedance 1 Enable the DAC outputs corresponding voltage DAC function enable control Bit 0 ENDA 0 Disable 1 Enable 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page212 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 24 3 2 DAC register 1 DAC Base Address 0x00 0x41704 DAC1 DAC Control Register 1 Bit 31 16 Name RSV RW t 1 5 q S8 7 0 2 ORW Bit Name Description Bit 7 0 DAO DAO 7 0 the ratio setting of the output voltage that is DAO 7 0 275 24 4 Model program flow EET DAC ERRE The program starts Initialization settings DAC settings DAC voltage output 24 5 Model program function Model name DAC usage method and description Model description Appropriately set the analog voltage and the digital voltage Connect the REFO to the positive end of the DAC Select the VSS as the negative end of the DAC which will use the AIO4 of the O2014HYCONTechnologyCop UG
27. is set as 0 the output of the comparator will be normal 25 1 4 Application of touch button The comparator has a special function measuring the touch button major principle is to set the comparison voltage via the multi node resistor and then input which into the RLO the multi node resistor provides voltage to charge the touch button and then the charges of the touch button charges the external reference capacitor of the negative input channel CH1 next the TMB counts the charge time that the voltage of the CH1 is higher than the voltage of the RLO and then determine the status that the touch button is touched or not according to the charge time Two switches need to be used to control the charging of the corresponding touch button and the charging of the touch button to the reference capacitor besides if one of the switches is close the other one must be open The comparator has a built in non overlap controller to control the switches to ensure one of them is close and the other one is open The operating frequency of the non overlap controller is provided by the operating clock of the TMB Therefore if the function should be used it is necessary to enable the counting function of the TMB and clear the counter register of the TMB 55 99 IH CPCLS 2 0 ru CPRH 2 0 EN N 4 e o CPNS 1 0 Rd N CPRLH PE 1 0 22258 5 5 C2 0 IE
28. clock 512 1001 clock 1024 1010 Timer clock 2048 1011 Timer clock 4096 1100 clock 8192 1101 clock 16384 1110 Timer clock 32768 1111 65536 www hycontek com page64 16 19 series user manual HYGON 21 bit ENOB gt gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 9 4 Model program flow The default value of the overclocking setting is 2MHz internal high speed oscillator and be up to 20 2 2 6 The HYCON C Library is adopted and the DrvTMA Open X Y can enable the TimerA and the Timer A Clock where X stands for the TMAR frequency dividing and if 15 is selected it will be divided by 65536 Y is to select the high speed or low speed to enter the Timer A HYCON C Library DrvTIMER Enablelnt E means enabling the Timer A interrupt HYCON C Library DrvTIMER ClearlntFlag E TMA means clearing Timer A interrupt flag Timer A B C and WDT belong to the HW1 interrupt and the format is void HW1 ISR void The program starts Initialization settings TimerA settings Wait for interrupt Interrupt the subprogram Clear the interrupt flag Reverse the Return to the main program 9 5 Model program function Model name Timer A usage instruction and description Model description Use Timer A interrupt
29. gt 05 gt 0 OPCS 1 OPOC dE OPOI M fs 9 vss OPOC i REFO Conversion Phase 0 ORO OPOR ins OPDFR 0 1 OPOD s 2us Uo 1 VSSA Delay AIO3 gt gt 0 OPCS 1 mo iu OPO 3 OPOC 1 5 vss OPOC Success Approximation Register 7 C Algorithm in Flash Memory 8 bit output 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page209 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 24 A D converter DAC 24 1 Overall description The chip has an embedded 8 bit A D converter DAC DAV8 module is an 8 bit A D converter which is composed of a step resistor with absolute monotonicity Features of DAC8 include 8 bit monotonic output Internal or external reference programmable selection It can serve as programmable resistor Operation of 8 When the ENDA is 0 the will be disabled and no power consumption will be incurred The Vrefp multiplexer is disabled and becomes a high impedance node However the Vrefn is still enabled and connects to one of the sources If the DAOE is set as 1 it will become a programmable resistor able to mark the ohm values 8 output The DA8 can generate the output voltages according to the data stored in the DABIT and VDA Vrefp VDA Vrefn DABIT is based on straight
30. www hycontek com page288 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 0110 6 0111 7 1000 8 1001 9 Other values Invalid The one s place of the year under the alarm clock mode BCD code format 0000 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid The tens place of the month under the alarm clock mode BCD code format Bit 12 10CMO O0 0 1 1 Bit 19 16 1CYE WwW gt Bit Name Description The one s place of the month under the alarm clock mode BCD code format 0000 0 0001 0010 0011 0100 Bit 11 8 1CMO 0101 0110 0111 1000 gt 1001 Others Invalid Bit 5 4 10CDAT The tens place of the date under the alarm clock mode BCD code format 00 0 01 1 2014 HYCON Technology Corp 0 16 198 01 www hycontek com page289 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash TECHNOLOGY 10 2 11 3 The one s place of the date under the alarm clock mode BCD code format 0000 0 0001 1 0010 2 0011 3 Bit 3 0 1TCDAT 1 0101 5 0110 6 0111 7 1000 8 1001 9 Other values Invalid 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page290
31. 2 0 CS 1 32 DrvSPI32 Write 0x02000000 0 02 gt Write EN 33 spi busy 1 34 while spi busy spi 00 gt gt 19 0 01 35 36 DrvSPI32 BitLength 24 37 DrvSPI32 Write 0x000300 0x03 38 spi busy 1 39 while spi_busy spi_busy spi_O0 gt gt 19 amp 0x01 40 41 DrvSPI32_BitLength 8 42 DrvSPI32_Write Ox1 1000000 Data 0x11 43 spi_busy 1 44 while spi_busy spi_busy spi_O0 gt gt 19 amp 0x01 45 46 47 DrvGPIO_SetBit E_PT2 0 PT2 0 CS 0 48 Delay 0x20 49 50 Delay 0x200 51 52 DrvGPIO_SetBit E_PT2 0 PT2 0 CS 1 53 i DrvGPIO GetBit E PT1 2 PT1 2 pin high or low 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page241 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 54 while i 0 55 56 i 1 57 DrvGPIO CIrBit E PT2 0 PT2 0 CS 1 58 DrvSPI32 Write 0x06000000 0 06 gt Write Read enable 59 spi busy 1 60 while spi busy spi 00 gt gt 19 80 01 61 DrvGPIO SetBit E PT2 0 I PT2 0 CS 0 62 Delay 0x20 63 64 DrvGPIO CIrBit E PT2 0 IIPT2 0 CS 1 65 DrvSPI32 Write 0x03000000 CMD 0x02 gt Read EN 66 spi busy 1 67 while spi busy spi busyz spi 002219
32. 21 20 19 18 16 TxBusy 0 ROW 0 RWO 0 R 15 08 4 3 B M MASK DLen RxIT ROW 0 Bit Name Description Rx Buffer over run error flag Bit 23 OErr 0 1 Rx Noise detected flag 22 0 1 Noise detected Rx Frame check error flag Bit 21 0 Normal 1 Frame check error Rx Parity check error Bit20 0 1 Parity check error Tx Busy flag Bit 19 TxBusy 0 Idle 1 Busy Tx Buffer Full flag TxBF 0 Empty 1 Full 2014 HYCON Technology Corp www hycontek com 0 16 198 01 245 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Rx Busy flag Bit 17 RxBusy 0 Idle 1 Busy Rx Buffer Full flag Bit 16 RxBF 0 Empty 1 Full Tx stop length control 0 0 5Bit Bit 6 1 1Bit 2 1 5Bit 3 2Bit data length Normal Mode Parity Check Mode Bit 5 4 0 6 Mode 5 1 7 6 Bit Mode 2 8 Bit Mode 7 Bit Mode 3 9BitMode 8 Bit Mode Rx interrupt method selection Send out the interrupt when the Rx Data Buffer has data 0 and the interrupt disappears after the data are read 1 Send out the interrupt after one piece of data is received by the Rx UART Rx control switch Bit2 RxEn 0 Disable 1 Enable Tx interrupt me
33. FIG 17 1 PT7 function block diagram The PT7 has input and output functions and different functions should be set by different controllers Output mode The controller PT7xOE 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT7xDO 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT7xIE 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enabled if itis set as 0 the input mode of the corresponding IO port will be disabled Whether the current input mode of the corresponding IO pin is 0 or 1 can be read the controlle
34. TBC1 15 0 4 L_ _ _ f www hycontek com 77 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY FIG 10 6 Waveform schematic view and counting waveform schematic view of PWM mode A www hycontek com page78 16 19 series user manual HYGON 21 bit ENOB AADC 32 bit MCU 64 KB Flash HYCON TECHNOLOGY PWMB mode The PWMB mode is a 16 bit PWM the counting value of the TBR is compared with the TBC2 and the waveform period of the PWM is controlled by the TBCO PWM 1 when TBR 15 0 gt TBC2 15 0 PWM 0 when TBR 15 0 lt TBC2 15 0 PWM period PWM Period TBR 15 0 TMCD HS CK or LS Ck PWM duty cycle PWM Duty TBC2 TBR 15 0 1 PWM Duty Cycle PWM Duty TMCD HS CK or 18 CK TBC2 15 0 Oh PWMB _ L1 LL FIG 10 7 Waveform schematic view and counting waveform schematic view of PWM mode B www hycontek com page79 16 19 series user manual HYGON 21 bit ENOB AADC 32 bit MCU 64 KB Flash HYCON TECHNOLOGY PWMC mode The PWMC mode is a 8 bit PWM the counting value of the TBR is compared with the TBC1 7 0 and many PWM waveforms appear within the period of the TBCO PWM output status control conditions PWM 1 when TBR 7 0 gt 1 7 0 PWM 0 when 7 0 lt TBC1 7 0 PWM period PWM Period TBR 7 0 TMCD HS CK or LS CK
35. nnn 249 28 1 Register address uet atender a RR e ERE e URL cent Ado o e 249 282 Register functione ieri d a P ERE RR c EY Rp c ERE 249 28 3 Model program gt gt 252 29 4 Modelprogram 253 285 Modelprogram description rene t 254 29 I2C COMMUNICATION 256 29 1 description 256 29 2 Communication 2 interface signal 257 29 3 Register address eccessi ican eee a 265 SEMEL ecniee 265 29 5 Model program 271 29 6 Model program function erect eps cu e ceo S ance 272 www hycontek com page8 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 29 7 Modelprogram description sees 272 30 HARDWARE REAL TIME CLOCK HW
36. 0 16 198 01 239 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HY16F198 32 bit Flash MCU Embdded 24 bit SD ADC W25X40 CS3 PT20 2 1 MISO PT22 MOSI 3 2 3 VDD3V 2014 HYCON Technology Corp www hycontek com 0 16 198 01 240 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYG N HYCON TECHNOLOGY 26 6 Model program description Main program 0 1 include HY16F19X h 2 3 4 volatile unsigned int i a 5 6 void InitalSPI32 void 7 void Delay unsigned int num 8 9 lint main void 10 11 SPI32 INI 12 DrvGPIO Open E PT1 0x06 E IO INPUT PT1 BIT3 0 pull high 13 DrvGPIO Open E PT1 0xf6 E IO PullHigh 14 15 1 16 17 DrvGPIO SetBit E 2 0 2 0 CS 1 18 i DrvGPIO GetBit E 1 1 PT1 1 pin high or low 19 while i 0 20 21 i 1 22 23 DrvGPIO CIrBit E PT2 0 2 0 CS 1 24 DrvSPI32 Write 0x06000000 lt 0 06 gt Write Read enable 25 spi busy 1 26 while spi_busy spi_busy spi_O0 gt gt 19 amp 0x01 27 DrvGPIO SetBit E PT2 0 2 0 5 0 28 Delay 0x20 29 30 31 DrvGPIO CIrBit E PT2 0
37. 1110 GPIO clock source 8192 1111 GPIO clock source 16384 ADC clock phase shift effective only at Core Clock 2 and Core Clock is HS CK Bit 7 ADCKP 0 ADC Clock Rising Edge generates from Core Clock Low 1 ADC Clock Rising Edge generates from Core Clock High ADC clock switch Bit 6 ENACDO Disable 1 Enable Bit 5 4 ADCD ADC clock frequency divider configuration www hycontek com page38 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 00 ADC clock source 6 01 ADC clock source 12 10 ADC clock source 30 11 ADC clock source 60 SPI clock switch Bit3 ENSD 0 Disable 1 Enable ADC clock frequency divider configuration 000 Reserved 001 SPI clock source 2 010 SPI clock source 4 Bit 2 0 SPCD 011 SPI clock source 8 100 SPI clock source 32 101 SPI clock source 128 110 SPI clock source 512 111 SPI clock source 2048 6 3 5 Clock system register CLKCR4 Clock Base Address 0x10 0x40310 CLK4 Clock Control Register 4 Bt 921 21 20 nA 1816 LCDCPD ROW 0 RW 0 RW 0 Bit 15 08 6 4 3 1 MASK LCDO LCKS ROW 0 Bit Name Description LCD charge pump regulator clock source selection 0 LS CK 10rHS CK 8 determines 15 CK or H8 CK Bit 22 23 LCDCPD1 LS CK 20rHS CK 16 LCKS determines LS CK or HS CK 2 LS CK 40rHS CK 32 LCKS determines LS CK or HS 3 LS
38. 18 16 MASK PT3IE7 PT3IE6 PT3IE5 PT3IE4 PT3IE3 PT3IE2 PT3IE1 PT3IEO RW 0 15 08 7 e 5 4 epe rp p Bit Name Description Port 3 PAD input mode enable control Bit23 16 0 Disable the input mode 1 Enable the input mode Port 3 PAD output status value Bit 7 0 PT3DO 0 Output low potential 1 Output high potential 15 3 3 PT3 register PT3CR2 Base Address 0x28 0 40828 Symbol 2 PT3 Control Register 2 Name ROWO 1150000 m e m n m 0 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page121 16 19 series user manual HYGON 21 bit ZAADC gt 32 bit MCU 8 64 KB Flash PT3DI 7 PT3DI 6 PT3DI S PT3DI 4 PT3DI S PT3DI 2 PT3DI 1 PT3DI O RW R 0 Bit Name Description DAO outputs to the PT3 1 enable control Bit 17 PT3A0 0 Disable 1 Enable Port3 PAD input status value Bit 7 0 PT3DI 0 input low potential 1 input high potential 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page122 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 16 GPIO PT6 MANAGEMENT 16 1 Overall description The PT6 has 8 IO pins which can be used as the common universal IO ports and can also
39. Capture comparator 1 The capture comparator 1 has four capture signal input sources and the input signal source can be set by setting the selector CPI1S 1 0 and the input signal should further pass the frequency divider C1PS 3 0 the frequency divider can perform the frequency dividing on the input signal to slow the input signal in this way the input signals with high frequency can be measured The setting of the controller TCPI1P can determine the trigger edge of the capture signal is the rising edge or the falling edge After the capture event is finished the interrupt signal can be generated and the interrupt flag is set as 1 The capture signal input source of the capture comparator 1 Input signal source Function description symbol CMPO The output status of the comparator OPOD The output status of the OP amplifier LS CK Chip low speed frequency source TCI1 Input from the IO The input of the capture comparator 1 Serial TCI1 TCI2 Serial TCI1 TCI2 number number 000 PT1 0 PT1 1 100 PT2 0 PT2 1 001 PT1 2 PT1 3 101 PT2 2 PT2 3 010 PT1 4 PT1 5 110 PT2 4 PT2 5 011 PT1 6 PT1 7 111 2 6 2 7 2014 Technology Corp UG HY16F198 V01 www hycontek com page100 16 19 series user manual HYGON 21 bit ENOB gt 32 bit MCU amp 64 KB Flash Operation of capture comparator 1 Select th
40. OPNS 5 0 000010 Vin x 1 R2 R1 2014 HYCON Technology Corp UG HY16F198 V01_TC www hycontek com page215 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 25 MULTIPLE FUNCTION COMPARATOR 25 1 Overall description The chip has an embedded low power Rail to Rail multi function comparator CMP for the comparing analog signals has the interrupt function when the comparison result generates the interrupt signal also generates and it can increase the operability for users It has different configuration settings for different applications Features of CMP include Rail to Rail input range Low operating current 2us peak pulse filter 4 bit step resistor DAC with different comparison sets Change and discharge paths measured by touch buttons Interrupt signals can be generated which belong to the interrupt vector HW3 CPCLS 2 0 piii CPDA 3 0 c Pi P ENCLIN 0 cesi pmi 9 ermee Nai ovorlap EBEN 1 E ock CDH eens CPDA 3 0 3 0 i We RLO i CPDF 0 CPOR 0 CPRL cPRLO CMPHS O0 CPPS 1 0 FIG 25 1 network diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page216 16 19 series user manual HYGON 21 bit ENOB XAADC
41. 111 Invalid The value of the Week BCD code format 30 3 7 Hardware RTC register RTCHRA Bit 3 ey it RTCHRA RTC Hour and min and seconds Control Register for alarm Name RO O m 15 _ 40 1CM1 10CSE 1CSE Base Address 0 18 0 41 18 14 12 11 8 7 Bit Name Description Bit 22 CPM The format of the alarm clock is am pm 0 AM or 24 hour system 1 PM when 1 the bit should be set as 1 Bit 21 20 10CHR The tens place of the hour under the alarm clock mode BCD code format 00 0 01 1 10 When 2 1 HRF 0 it is invalid 11 invalid 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page286 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash hae The one s place of the hour under the alarm clock mode BCD code format 0000 0 0001 0010 0011 0100 Bit 19 16 1CHR 0101 0110 0111 1000 ODN 1001 Other values Invalid The tens place of the minute under the alarm clock mode BCD code format 000 001 010 Bit 14 12 10CMI 011 100 101 Oni 110 111 Invalid The one s place
42. 16 PT20IE 0 Disable 1 Enable PT2 Bit 7 0 interrupt request Bit 15 8 PT2 IR 0 Disable 1 Enable PT27IF PT27 external interrupt flag Bii07 PT27IF 0 Normal T27 external interrupt occurs T26IF PT26 external interrupt flag Bios O PT25IF PT25 external interrupt flag PT25IF 0 1 PT25 external interrupt occurs PT24IF PT24 external interrupt flag Bit O4 PT24IF 0 Normal 1 24 external interrupt occurs PT23IF PT23 external interrupt flag PT23IF 0 Normal 1 23 external interrupt occurs PT22IF PT22 external interrupt flag Bit 02 PT22IF 0 Normal 1 22 external interrupt occurs PT24IF PT21 external interrupt flag Bit 01 PT21IF 0 Normal 1 21 external interrupt occurs PT20IF PT20 external interrupt flag Bit 00 PT20IF 0 Normal 1 20 external interrupt occurs www hycontek com page52 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 7 3 7 Interrupt control register INTUART2 INT Base Address 0x18 0x40018 mbol INTUART2 Interrupt Control Register 6 U2TXIE U2RKIE RWO RW ROWO 1 RW 0 Bit 15 12 11 10 98 74 3 no MASK U2TxIF U2RxIF _ ORW RO 17 1 RW0 2 When writing the regis
43. 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 16 2 Register address GPIO Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 50 0 40850 MASK1 PT61CFG MASKO PT60CFG GPIO Base Address 0x54 0x40854 MASK3 PT63CFG MASK2 PT62CFG GPIO Base Address 0x58 0x40858 MASKS PT65CFG MASK4 PT64CFG GPIO Base Address 0x5C 0x4085C MASK7 PT67CFG MASK6 PT66CFG LCD Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 50 0 40850 MASK1 SEG3 MASKO SEG2 GPIO Base Address 0x54 0x40854 MASK3 SEG5 MASK2 SEG4 GPIO Base Address 0x58 0x40858 5 5 SEG7 MASK4 SEG6 GPIO Base Address 0x5C 0x4085C MASK7 SEG9 MASK6 SEG8 LCD Register Address 0x41B04 can determine the setting is the GPIO Mode or the LCD Mode 16 3 Register function 16 3 1 PT6 0 PT6 1 register When GPIO Mode Mame 16087 T HIT BOT Bit Description IPT6 1 Output Enable Bit 19 PTOIOE 0 Disable 1 Enable PT6 1 Input Enable Bit 18 0 Disable 1 Enable PT6 1 Output Data 17 PT61DO 0 Output Low Output High 16 PT61DI 6 1 Input Data 0 Input Low d 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page125 16 19 seri
44. 8 SEG25 MOSI 6 Rx2 6 PWMS3 6 9 0 SEG26 CS 7 Tx 7 PWMO 7 9 1 SEG27 CK 7 Rx 7 1 7 9 2 SEG28 5 7 2 7 2 7 9 3 SEG29 MOSI 7 Rx2 7 PWMS3 7 PT9 4 SEG30 CS 8 Tx 8 PWMO 8 PT9 5 SEG31 CK 8 Rx 8 PWM1 8 9 6 32 5 8 2 8 PWM2 8 PT9 7 SEG33 MOSI 8 Rx2 8 PWMS3 8 PT10 0 SEG 34 PT10 1 SEG 35 Table 21 1 IO pin reuse functions and priority levels 21 2 Register address GPIO Register Address 31124 23 16 15 8 7 0 GPIO Base Address 0x40 0x40840 MASK1 GPIOMCR1 MASKO GPIOMCRO GPIO Base Address 0 44 0 40844 5 GPIOMCR3 MASK2 GPIOMCR2 GPIO Base Address 0x48 0x40848 MASK5 GPIOMCRS MASK4 GPIOMCRA GPIO Base Address 0 4 0 4084 MASK7 GPIOMCR7 MASK6 GPIOMCR6 21 3 Register function 21 3 1 GPIO reuse function control register GPIOMCRO GPIOMCR1 Base Address 0x40 0 40840 Symbol GPIOMCRO GPIOMCR1 GPIO multiplex Control Register 0 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 page171 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGZh HYCON TECHNOLOGY MASK PTCOPS PTCOPE _ _ PTCCPE 508g MASK PTCTC Z 0 PTPWIZ 0 PTPW1E PTPWOE RW 0 Bit Name Description Rail to Rail OPAMP digital signal output port selection Bit 19 PT
45. OPPS 3 0 Disable high impedance 1 Enable and connect to the REFO OPAMP positive input channel 2 Bit 18 OPPS 2 0 Disable high impedance 1 Enable and connect to the DAO OPAMP positive input channel 1 Bit 17 OPPS 1 0 Disable high impedance 1 Enable and connect to the AlO4 OPAMP positive input channel 0 Bit 16 OPPS 0 0 Disable high impedance 1 Enable and connect to the AlO2 OPAMP negative input channel 7 Bit 7 OPNS 7 0 Disable high impedance 1 Enable and connect to the AIO8 OPAMP negative input channel 6 Bit 6 OPNS 6 0 Disable high impedance 1 Enable and connect to the AlO2 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page205 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash OPAMP negative input channel 5 HYGON HYCON TECHNOLOGY Bit 5 OPNS 5 0 Disable high impedance 1 Enable and connect to the OPC internal 10pF capacitor OPAMP negative input channel 4 Bit4 OPNS 4 0 Disable high impedance 1 Enable and connect to the OPOI internal OPAMP output OPAMP negative input channel 3 Bit 3 OPNS 3 0 Disable high impedance 1 Enable and connect to the OPO internal OPAMP output OPAMP negative input channel 2 Bit 2 OPNS 2 0 Disable high impedance 1 Enable and connect to the DAO OPAMP negative input channel 1 Bit 1 OPNS 1 0 Disable high impedance 1 Enable and connect to the AIO5 OPAMP negative input channel 0 Bit O OPNS 0 0 Disable hi
46. PT720E 0 Disable 1 Enable PT7 2 Input Enable Bit 2 PT72lbE 0 Disable 1 Enable PT7 2 Output Data PT72DO 0 Output Low 1 Output High PT7 2 Input Data Bit 0 PT72DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page137 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode Base Address 0x64 0 40864 Name MASK SEG13 Data Bt 1508 7 6 5 4 B3 2 m W Name SEG12 Data Bit Name Description LCD Segment 13 Data Segment Data LCD Segment 12 Data Segment Data Bit 21 16 SEG 13 Data Bit b 0 SEG 12 Data UG HY16F198 VO1 2014 HYCON Technology Corp page138 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 17 3 3 PT7 4 PT7 5 register When GPIO Mode Name MASK PT7SDOPT SDI 15 01 7 6 5 B 2 m 0O Bit Name Description PT7 5 Output Enable Bit19 PT750E 0 Disable 1 Enable PT7 5 Input Enable Bit18 PT75IE 0 Disable 1 Enable PT7 5 Output Data Bit17 PT75DO 0 Output Low 1 Output High PT7 5 Input Data Bit 16 PT75
47. PWM duty cycle PWM Duty TBC1 7 0 TBR 7 0 1 PWM Duty Cycle PWM Duty TMCD HS CK or LS CK PENNE 0100h donec eee ced eee TBC1 7 0 1 1 4 FIG 10 8 Waveform schematic view and counting waveform schematic view of PWM mode C www hycontek com page80 16 19 series user manual HYGON 21 bit ENOB AADC 32 bit MCU 64 KB Flash HYCON TECHNOLOGY PWMD mode The PWMC mode is a 8 bit PWM the counting value of the TBR is compared with the TBC2 7 0 and many PWM waveforms appear within the period of the TBCO PWM output status control conditions PWM 1 when TBR 15 8 gt TBC2 7 0 PWM 0 when TBR 15 8 lt TBC2 7 0 PWM period PWM Period TBR 15 8 TMCD HS CK or LS CK PWM duty cycle PWM Duty TBC2 7 0 TBR 15 8 1 PWM Duty Cycle PWM Duty TMCD HS_CK or LS CK 2 7 0 4 1 Oh PWMD _ L1 fL LL FIG 10 9 Waveform schematic view and counting waveform schematic view of PWM mode D www hycontek com page81 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY waveform 8 8 bit PWM Set the TMB counter as the 8 8 bit mode a
48. amp 0x01 68 69 DrvSPI32 BitLength 24 70 DrvSPI32 Write 0x000300 I Address 0x03 71 spi busy 1 72 while spi busy spi 002219 amp 0x01 73 74 DrvSPI32 BitLength 8 75 DrvSPI32 Write 0x55000000 76 spi busy 1 77 while spi busy spi 00 gt gt 19 amp 0x01 78 temp spi 08 gt gt 24 amp Oxff 79 80 DrvGPIO SetBit E PT2 0 I PT2 0 CS 0 81 Delay 0x20 82 83 84 85 86 87 Subprogram 0 1 void HWO ISR void 2 3 DrvSPI32_ClrlntTxFlag 4 temp DrvSPI32 Read 5 6 7 InitalSPI32 void 8 if 9 asm NOP 10 Set SPI input pin Master2 3 wire mode 11 DrvGPIO Open E 2 0 IO OUTPUT CS PT2 0 output lt 0 CPOL 1 12 DrvGPIO Open E 2 0 04 IO INPUT 2 0 CS 13 Port2 1 CK 14 Port2 2 DI 15 Port2 3 DO 16 DrvGPIO SetPortBits E PT2 0x01 ISPI GPIO 17 18 DrvSPI32 Open E DRVSPI MASTER2 E DRVSPI 2 4 19 DrvSPI32 Enable 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page242 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash A 20 21 22 23 24 Delay unsigned int num 2 25 26 volatile unsigned int d 27 for d 0 d lt num d asm NOP 28 2014 HYCON Technology Corp www hycontek com 0 16
49. ready The offset and BandGap voltages can be enabled by setting the ENBGR is 1 Nest it still needs a 1 2V common mode voltage to enable the ADC The common mode voltage can be selected from the inside or outside The ADC also needs a clock input whose maximum is 350 KHz The inputted clock should be set to be higher than 40 KHz The detailed configuration and operation are as follows 1 Set and enable the operating clock source of the ADC it is suggested that the sampling frequency of the ADC is set to be about 330khz Enable the VDDA voltage and the BandGap reference voltage common mode reference 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page186 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash voltage REFO and analog ground source and the wait until the voltages are stable Select the input channels of the signals to be measured of the ADC including positive negative channels and turn off the input short circuit switch Set the internal magnifying power of the ADC according to the actual conditions to make the ASI within 0 9 VREF Set the zero point bias DCSET if it is not necessary please set 0 VREF Select the reference voltage input channel of the ADC turn off the input short circuit switch and select the reference voltage attenuation rate Set the over sampling frequency dividing value OSR 3 0 according to the actual ENOB Enab
50. x1 NT The program starts Initialization settings ADC settings Wait for interrupt 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page193 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash Interrupt the subprogram Clear the interrupt flag Reverse the value of the ADC Return to the main program 2014 HYCON Technology Corp www hycontek com HYGON HYCON TECHNOLOGY 0 16 198 01 page194 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash 22 5 Model program function Model name The ADC interrupt usage method HYCON TECHNOLOGY The ADC interrupt function can be realized by the related configuration of the ADC Set the powers of the ADC VDDA and REFO Set the clock of the ADC ADCCLK The Vin of the ADC is AIOO AIO1 The Vref of the ADC is REFO to VSS AIOO AIO1 VSS REFO 18 6Model program description 01 include HY16F19X h 03 unsigned int ADCData 05 define Disable 0 06 define Enable 1 08 lint main void 09 10 Set ADC input pin 12 DrvADC_SetADClInputChannel ADC_Input_AlO0 ADC_Input_AlO1 positive input AIOO Set ADC negative input AIO1 14 DrvADC_InputSwitch OPEN input short co
51. 16 198 01 14 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 2 2 CPU core block diagram 2 wire debug port EDM 32 bit N801 Core Boost ROM Instruction Load Store Flash ROM gt Fetch lt gt Unit Bus Interface Unit Digital Analog Sensor Communication IP IP IP IP FIG 2 2 CPU core block diagram www hycontek com page15 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 3 MEMORY STRUCTURE 3 1 Memory description The core of the CPU Central Processing Unit of HY16F19 series products is Andes N801 32 bit CPU The allocation of the memory addresses of the micro controller is as follows 0x00000 to OxO1FFF Static random access memory SRAM 8K Byte 0x40000 to Ox4FFFF SOC Register 0x80000 to 0x81FFF Boot ROM 8K Byte 0x90000 to Ox9FFFF Main Program Flash ROM 64K Byte 0X80000 Original built in standard Boot ROM 1 ISP UART Burn function 8KB 2 Encryption function user can not modify 0 00000 0 90000 Contains the interrupt handler stack initialization action SRAM Start Up Code Written in assembly is completed 8 According actual space planning and adjustment 0X40000 SOC User program d
52. 32 bit MCU amp 64 KB Flash 14 2 14 1 Overall description The PT2 has 8 IO pins and be used as common universal IO ports or reused as the input or output IO ports of many function modules such as capture comparator PWM external crystal oscillator and external interrupt input etc Different reuses need different configurations VDD3V T VDD3V PT2PU AIOX PAD PT2DI PT2IE E IOIP PT2DO FIG 14 1 2 function block diagram The PT2 has the functions of the input output internal pull up resistor and external interrupt input port and different functions need to be set by different controllers Internal pull up resistor The controller PT2PU 7 0 can enable or disable the internal pull up resistor of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the port is set as 1 the internal 75k pull up resistor will be enabled if the corresponding bit of the IO port is set as lt 0 gt the internal 75k pull up resistor will be disabled If the IO port is under the input mode and there is no external pull up resistor the internal pull up resistor should be enabled especially in low power consumption mode which can prevent from electric leakage and increase the power consumption If it serves as the analog signal input port it is not necessary to enable the internal pull up
53. 4 5 CK 32 LCKS determines LS CK or HS UART2 clock source selection Bit 21 UT2CKS 0 HSXT External high speed oscillator 1 HSRC Internal high speed oscillator Bit 20 ENUD2D UART2 clock source enablement control 0 Disable www hycontek com page39 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 Enable UART2 clock source frequency divider configuration UART2 clock source 1 UART2 clock source 2 UART2 clock source 4 UART2 clock source 8 UART2 clock source 16 UART2 clock source 32 UART2 clock source 64 UART2 clock source 128 LCD clock source 1 stage frequency divider configuration Disable LCD clock source 1 LCD clock source 2 LCD clock source 4 LCD clock source 8 LCD clock source 16 LCD clock source 32 Disable LCD clock source 2 stage frequency divider configuration LCD clock source 1 LCD clock source 3 LCD clock source 5 LCD clock source 7 LCD clock source 9 LCD clock source 11 LCD clock source 13 LCD clock source 15 LCD clock source selection Bit 0 0 LS 8 1 HS 64 18 16 UA2CD NM gt O Bi 6 4 LCDO Bi 3 1 LCDE gt O www hycontek com page40 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 3 6 Clock system register CLKCR5 Clock Base Address 0x014
54. 8 3 2 m IO MASK 10bEn EIRQFlag STARE STOP IRQFlag A NA ROW 0 Description Master mode enable flag Bip3 c Disable Enable Slave mode enable flag Bit 22 SAct 0 Disable Disable Rx Reception stop or restart flag Bit21 Bic The reception stop or restart flag has been sent or received The writing instruction has been sent or received The reading instruction has been sent or received ui 2 data have been sent or received NI signal ACK status flag mE The response signal ACK has yet to be sent or received The response signal ACK has been sent or received ct The general calling operation is performed now loss Sie mode enable control Bi SEn o Disable 4M Enable os qr Slave 10 bit address code mode enable control 52 Enable the 10 bit address code mode m sending 3 pieces of data function enable control Bil 3BEn 0 Disable J 1 Enable the slave continuously sending 3 pieces of data function CO2014HYCONTechnodogyCop ee UG HY16F198 VO1 www hycontek com page266 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash Error flag related to the error interrupt flag I2CEIF the 2 can be cleared after the bit is cleared 0 Normal time out or receiving accidental start stop signal arbitration failure takes place S Start signal contro
55. HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 30 4 Model program flow fest pata program starts Initialization settings RTC time setting RTC time output 30 5 Model program function Model name test the hardware RTC HYGON HYCON TECHNOLOGY Model description test the real time clock function of the hardware RTC 30 6 Model program description Main program 01 include HY16F19X h 02 j unsigned int sec min hour week day month year 03 04 void Delay unsigned int num 05 JInitial void 06 07 int main void 08 09 RTC_Initial initialization including time setting 11 12 while 1 13 14 asm NOP 15 IRTC backward reading time setting 16 DrvRTC_Read DRVRTC_CURRENT_TIME amp sCurTime RTC backward reading time data 17 18 sec sCurTime u32cSecond backward reading_second 19 min sCurTime u32cMinute backward reading_minute 20 hour sCurTime u32cHour backward reading_hour 21 week sCurTime u32cDayOfWeek backward reading_week 22 day sCurTime u32cDay backward reading_date 23 month sCurTime u32cMonth backward reading_month 2014 HYCON Technology Corp www hycontek com 0 16 198 01 291 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 K
56. PT85DO 0 Output Low 1 Output High PT8 5 Input Data Bit 16 PT85DI 0 Input Low 1 Input High PT8 4 Output Enable 84 0 Disable 1 Enable PT8 4 Input Enable Bit 2 PT84IE 0 Disable 1 Enable PT8 4 Output Data PT84DO 0 Output Low 1 Output High PT8 4 Input Data Bit 0 PT84DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page149 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode GPIO Base Address 0x78 0x40878 SEG23 Data Bit 15 08 7 60 5 A 0 Name MASK SEG22 Data Bit Name Description LCD Segment 23 Data Segment Data LCD Segment 22 Data Segment Data Bit 21 16 SEG 23 Data Bit b 0 SEG 22 Data 0 16 198 01 2014 HYCON Technology Corp page150 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 18 3 4 PT8 6 PT8 7 register When GPIO Mode GPIO Base Address 0 7 0x4087C PTWOEPTBTIE 7 Bt 501 7 6 0 Bit Name Description PT8 7 Output Enable Bit19 PT87OE 0 Disable 1 E
57. Software I2C 42 43 volatile unsigned int n 44 for n 0 n lt 0x10 n asm NOP 0x10 45 46 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page274 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash 30 HARDWARE REAL TIME CLOCK HW RTC 30 1 Overall description The real time clock controller provides the real time clock and calendar The clock source of the RTC is from the external 32 768 KHz crystal connected to the I O port or the internal 35kHz LPO oscillator The RTC controller shows the time information about hour minute second by binary coded decimal BDC and the calendar information about year month day The controller has a programmable alert interrupt program and a periodically programmable wake up interrupt program such that the system can be automatically wakened to deal with the low power mode The controller further has a 6 bit digital timing crystal oscillator offset compensation mechanism Function The time information hour minute second and the date information year month day are stored in the register Alert register year month day hour minute second All time and date information are shown by the BCD format Leap automatic compensation years 2012 2099 Week counter 6 bit digital timing crystal oscillator offset compensation Support periodically wake up the CPU from the idle mode
58. TACK TMAR 15 0 Interrupt TMAS 3 0 TMAR 15 0 TMAS 3 0 TMAR 15 0 0000 TACK 2 1000 TACK 512 0001 TACK 4 1001 TACK 1024 0010 8 1010 2048 0011 16 1011 4096 0100 TACK 32 1100 TACK 8192 0101 64 1101 16384 0110 TACK 128 1110 TACK 32768 0111 TACK 256 1111 65536 FIG 9 1 Timer A block diagram 9 2 Register address TMA Register Address 31 24 23 16 15 8 7 0 Base Address 0 00 0 40 00 1 TARO MASKO REGO 9 3 Register function 9 3 1 Timer A register TMACR Base Address 0x00 0 40 00 TMACR TMA Control Register 31 16 gt 15 8 ROW O Bit Bit RW Fh Bit Name Description Bit 31 16 Timer A Counter counting value www hycontek com page63 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY TAR 31 16 are the counting values of the 16 bit Timer A and the output value can be MSB to LSB Enable the Timer A Bit5b 0 Disable 1 Enable Clear the counting value of the Timer A Bit4 TACLRO Normal 1 Clear After the bit is cleared the bit will automatically become 0 Timer A frequency divider configuration 0000 Timer clock 2 0001 Timer A clock 4 0010 Timer clock 8 0011 Timer clock 16 0100 Timer clock 32 0101 Timer A clock 64 0110 Timer A clock 128 Bit3 0 TAS 0111 Timer A clock 256 1000
59. Tex pid The program starts Initialization settings WDT settings Wait for interrupt Interrupt the subprogram Clear the interrupt flag 2014 HYCON Technology Corp www hycontek com 0 16 198 01 59 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Reverse the Return to the main program 8 5 Model program function Model name the WDT usage instruction and description Model description 1 Use the WDT interrupt 2 Each WDT interrupt will reverse the IO PT2 0x05 before the interrupt PT2 0x0A after the interrupt www hycontek com HY16F19 series user manual 21 bit ENOB 32 bit MCU amp 64 KB Flash 8 6 Model program description HYG N TECHNOLOGY 00 01 HY16F19X h 02 03 unsigned int i 04 05 int main void 06 07 0 05 08 DrvGPIO Open E PT2 0x0FEE IO OUTPUT PT2 0 3 Set Output 09 DrvGPIO SetPortBits E PT2 i PT2 Output i 0x05 10 11 DrvWDT Open E IRQ E PRE SCALER D32 WDT IRQ open prescaler 32 12 13 DrvWDT_ClearWDT Clear WDT interrupt flag 14 DrvTIMER Enablelnt E WDT IWDT interrupt enable 15 16 SYS EnableGIE 7 Enable GIE 17 18 while
60. and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enabled if itis set as 0 the input mode of the corresponding IO port will be disabled Whether the current input mode of the corresponding IO pin is or 1 can be read the controller PT2DI 7 0 If the IO is set as the input mode and the chip is not connected to the external pull up resistor the internal pull up resistor should be enabled the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially in the low power mode it is suggested the IO pin should be set as the input mode If it serves as the analog signal input port it is not necessary to set the corresponding IO pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled External interrupt input The PT2 has 8 IO pins and all of them can be reused as external interrupt input pins The mode should set the IO port to be the input mode and enable the internal pull up resistor lt is necessary to set the external interrupt trigger edge by the controller PT2XITT 2 0 and enable the control bit PT2ITD 0 to enable the interrupt trigger edge The controller PT2XIE 7 0 can enable the interrupt response function of the corresponding IO pin when the external interrupt signal generates the interrupt flag of the corresponding pin is set
61. is controlled by the TBCO 15 8 and the overflow value of the TBR 7 0 is controlled by TBCO 7 0 The two counters will be automatically added by 1 at each rising edge of the TBCLK If the TBR 15 8 is equal to the TBCO 15 8 the TBR 15 8 will become 0 at the next rising edge of the TBCLK but the interrupt flag TMBIF is still 0 if the TBR 7 0 is equal to 7 0 TBR 7 0 will become 0 at the next rising edge of the TBCLK and the interrupt flag TMBIF will be set as lt 1 gt At this time if the TMB interrupt function and the global interrupt enable function are enabled the chip will reply to the TMB interrupt Under the mode the interrupt request is controlled by the counter TBR 7 0 therefore during the mode please pay attention to set the value of the TBCO 7 0 in order to control the TMB interrupt vector The schematic view of the counting waveform of the mode is as shown in the following figure In the mode the calculation method of the counting cycle of the interrupt method of the mode is T TBCO 7 0 TMCD HS CK or 5 CK www hycontek com page73 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY TBGO 15 8 ee ee ee Se ee lt TBR 15 8 Oh pe time TBCO T7 0 Oh TBM 10 time TBCLK TBR 15 8 TBRH max 00h 01h 20h 21h 22h 23h 24h TBR 7 0 10h 11h 12h 1 00h
62. 0 Bit 15 14 13 12 11 mo 9 8 17 9 3 n 0 MASK TOF WDTIF TMC1IF TMCOIF TMBIF TMAIF Name RTCIRWDTIR TMC1IR TMCOIR TMBIR TMAIR ROW 0 When writing the register the Bit15 8 are Mask when reading the register the Bit15 8 are general registers Description Real time clock RTC interrupt enable control Bit 21 0 Disable Enable Bit 20 WDTIE interrupt enable control 0 Disable www hycontek com page45 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash TMC interrupt enable control Bit 19 TMCO interrupt enable control Bit 18 s Timer TMB interrupt enable control Bit 17 0 imer TMA interrupt enable control Bit 16 o RTC interrupt request Bi f3 RTCIR WDT interrupt request Bit 12 imer C channel 1 interrupt request Bit 11 wen C channel 0 interrupt request Bit 10 TMCOIRO TMB interrupt request Bi TMBIR 0 TMA interrupt request Bit s TMAIR 0 Enable Real time clock RTC interrupt flag Bit 05 RTCIF 0 Normal Real time clock RTC interrupt occurs Bit 04 WDTIF WDT interrupt flag 0 2014 HYCON Technology Corp www hycontek com HYG N HYCON TECHNOLOGY UG HY16F198 VO1 TC page46 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY WDT interrupt occurs TMC1 i
63. 0 Disable the internal pull up 1 Enable the internal pull up Port 2 PAD output mode enable control Bit 07 00 PT2OE 0 Disable the output mode 1 Enable the output mode 14 3 2 1PT2 register PT2CR1 GPIO Base Address 0 14 0x40814 Symbol PT2CR1 PT2 Control Register 1 Bit 31 24 23 22 21 20 19 18 16 Name MASK PT2IE7 PT2IE6 PT2IE5 2 4 PT2IE3 PT2IE2 PT2IE1 PT2IEO RW ROW O RW 0 Bit 1508 7 6 4 I3 P n 0 Name MASK 2007 2006 PT2DO5 PT2DO4 PT2DO3 2002 PT2DO1 2000 RW ROW 0 RW 0 Bit Name Description Port 2 PAD input mode enable control Bit 23 16 PT2IE 0 Disable the input mode 1 Enable the input mode Port 2 PAD output status value 7 0 PT2DO 0 Output low potential 1 Output high potential 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page116 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 14 3 3 2 register PT2CR2 GPIO Base Address 0x18 0x40818 ymbol PT2CR2 PT2 Control Register 2 31 16 RW Bit 15 8 7 e 4 3 jPT2DI 7 PT2DI 6 PT2DI 5 PT2DI 4 PT2DI 3 PT2DI 2 PT2DI 1 PT2DI O Bit Name Description Port2 PAD input status value Bit 7 0 PT2DI 0
64. 05 int main void 06 07 0 05 08 DrvGPIO Open E PT2 0xX0FE IO OUTPUT 2 0 3 Set Output 09 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 10 11 DrvTMBC CIk Source 0 3 Prescaler 1 12 CK clock source 13 clock divider 8 14 15 DrvTMB Open E TMB MODEO E TMB NORMAL OxFFFF Timer B overflow OxFFFF 16 DrvTIMER ClearlntFlag E Clear TMB interrupt flag 17 DrvTIMER Enablelnt E Timer B interrupt enable 18 19 SYS EnableGIE 7 Enable GIE 20 21 while 1 for Interrupt 22 23 24 HW1 ISR void 25 1 26 DrvTIMER ClearlntFlag E Clear TMB interrupt flag 27 izi OxF Ifi OxF 28 DrvGPIO SetPortBits E PT2 i PT2 Output i 0x0A 0x05 29 30 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page94 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 11 2 11 1 Register address TMB2 Register Address 31 24 23 16 15 8 7 0 Base Address 0 24 0 40 24 MASK1 REG1 MASKO REGO Base Address 0 28 0 40 28 REG2 TB2CR TB2CR Base Address 0 2 0 40 2 TB2CO TB2CO Base Address 0x30 0x40C30 TB2C2 TB2C2 TB2C1 TB2C1 11 2 Register function 11 2 1 Timer B2 register TMB2CRO TMA Base Address 0x24 0 40 24 TMB2CRO TMB2 Co
65. 0x403148 CLK5 Clock Control Register 4 31 16 Name Reserved RW Bit 15 8 7 6 5 4 3 0 Name TM2CKS ENT2D TM2CD ROW 0 RW 0 Bit Name Description Timer B2 clock source selection Bit 7 TM2CKS 0 HS CK 1 LS CK Timer B2 clock source enablement control Bit 6 ENT2D 0 Disable 1 Enable Timer B2 clock source frequency divider configuration 0 Timer B2 clock source 1 1 Timer B2 clock source 2 2 Timer B2 clock source 4 3 Timer B2 clock source 8 Bit 5 4 TM2CD www hycontek com page41 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 7 INTERRUPT CONTROL SYSTEM 7 1 Overall description The interrupt module includes the interrupt startup controller interrupt enable controller and interrupt event flag register to manage the overall interrupt service such as communication interrupt timer interrupt ADC interrupt comparator interrupt and IO external interrupt The chip provides 9 stage interrupt source and also provides 9 stage interrupt vector priorities including HWO HW1 HW68 from high priority to low priority The interrupt service is composed of the interrupt event flag INTF interrupt event service intelligent startup INTE interrupt general control GIE and vector addresses HWO HW8 When the interrupt event occurs and the interrupt event service is enabled the program counter PC will turn to the interrupt servic
66. 1 Wait for Interrupt 20 21 22 HW1 ISR void 23 24 DrvTIMER ClearlntFlag E WDT Clear WDT interrupt flag 25 izi OxF Ili OxF 26 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 277 28 2014 Technology Corp www hycontek com UG HY16F198 VO1 TC page61 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 9 TIMER A 9 1 Overall description Timer A is a 16 bit up counter and can be operated in operation mode and IDEL mode It can be used to generate different output frequencies Main features Up counter 16 stage overflow values are available to be selected Overflow generates an interrupt event The values of the counter can be read Initial configuration of Timer TMA is a 16 bit up counter input clock source is the TACK and it will perform the counting according to each rising edge of the TACK and the frequency of the input clock source is controlled by the clock system management module The function of the TMA can be enabled or disabled by setting the control bit ENTA 1 as 1 or 0 The overflow value of the TMA can be adjusted by the frequency divider TAS 3 0 the user can change the overflow value by modifying the value of the frequency divider TAS to generate the counting values with different frequencies The control bit TACLR 1 is set as 1 but the TMA is reset and the counter register
67. 1 PTUR2 3 Port 2 6 2 Port 2 7 2 4 Port 8 2 2 Port 8 3 2 5 Port 8 6 Tx2 Port 8 7 Rx2 6 Port 9 2 Tx2 Port 9 3 Rx2 7 Port 9 6 Tx2 Port 9 7 2 GPIO UART2 control switch Bit 5 0 Disable 1 Enable 2014 HYCON Technology Corp www hycontek com 0 16 198 01 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 22 gt 24 BIT A D CONVERTER ADC 22 1 Overall description The chip has an embedded high performance 24 bit A D converter 24 bit2 AADC The ADC has pre low noise programmable gain amplifier Low Noise which can be used to amplify input signals The gain programmable setting range is 1 128 sampling rate of the ADC can be programmed by the register The designed sampling rate is 350KHZ per second It has 3 stage regulator for filtering the quantized noise of the regulator The programmable range of the over sampling rate of the ADC is 32 32768 It is designed to measure the sensors with extremely small signals such as strain meter pressure gauge and industry process control Features The settable sampling rate is 40KHZ 350KHZ The resolution of the effective number ENOB of bits is up to 21 bits The lowest input noise is 65nV RMS The settable over sampling rate is 32 32768 The highest output rate is 10 KHz The multiplier gain of the built in low noise programmabl
68. 1 Output High PT9 3 Input Data Bit 16 PT93DI 0 Input Low 1 Input High PT9 2 Output Enable Bit 3 PT920E 0 Disable 1 Enable PT9 2 Input Enable Bit 2 PT92lE 0 Disable 1 Enable PT9 2 Output Data Bit 1 PT92DO 0 Output Low 1 Output High PT9 2 Input Data Bit 0 PT92DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com page157 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode Base Address 0x84 0x40884 o SEGIO Data Bt 1500 7 0 SEG28 Data Bit Name Description LCD Segment 29 Data Segment Data LCD Segment 28 Data Segment Data Bit 21 16 SEG 29 Data Bit b 0 SEG 28 Data UG HY16F198 V01_TC 2014 HYCON Technology Corp page158 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 19 3 3 9 4 9 5 register When GPIO Mode Base Address 0x88 0x40888 Name MASK PT95OEPTOSIE PT95D0 PTOsDI Bit 1500 7 68 4M B B n 0 Bit Name Description PT9 5 Output Enable Bit 19 PT950E 0 Disable 1 Enable PT9 5 Input Enable Bit 18 PT9
69. 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 28 2 2 UART2 register 1 ol UART2CRT UART2ContrlRegister 1 Bit Name RO 15 08 r5 m I RxABDEn RxWUEn PrtODD RW ROWO RW Bit Name Description Automatic baud rate detection switch Bit 4 RXABDF 0 Disable 1 Enable Automatic baud rate detection error flag Bit 3 RxXABDEn 0 Normal 1 Error occurs Automatic wake up mode Bit2 RXWUEn 0 Disable 1 Enable Parity check switch Bit 1 PrtEn 0 Disable 1 Enable Select the odd parity check even parity check Bit PrtODD Even parity check 1 Odd parity check 28 2 3 UART2 register 2 UART2 Base Address 0x18 0x40E18 UART2CR2 UART2 Control Register 2 31 16 RSV lt 03 2 3 15 0 Baud Rate RW X 3 2 UARTZCR2 UART2ContolRegister2 2 Mi 80 7 Bt J 0 J A i g D 2 BaudRae 2 z Bit Name Description Bit 15 0 Baud Rate UART baud rate setting 28 2 4 UART2 register 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page251 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY UART2 Base Address 0x1
70. 198 01 243 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 27 ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMIT EUART 27 1 Overall description The chip has an embedded enhanced universal asynchronous receiver transmit EUART management The peripheral devices of the EUART is so called serial communication interface SCI The EUART can be set as the full duplex asynchronous system and its peripheral communication devices including ADC or DAC integrated circuit serial EEPROM Flash etc The EUART has extra features including the data frame error detection and automatic address identification The data frame error detection can determine whether a data frame is valid or passes the frame stop bit The automatic address identification can compare the address frame content with the single chip address and the serial interrupt can only be generated when both of them are conformed to each other 27 1 1 Communication IO pins The EUART communication bus only uses two wires TX RX the chip allocates 8 sets of communication IO pins each set includes the TX RX wires for the EUART module for users to perform designs freely However the reuse functions of the port can be used to conveniently select and enable the communication IO pins of the EUART the controller PTUR 2 0 PTURE accordingly when using the EUART the IO communication pins should be enable
71. 3 Register TUNCUON en eid 22 5 POWER MANAGEMENT 5 cnram rint nku tnb renean rand qu t ard rd nw gara aun nas es di 24 5 1 Overall 24 5 2 address utat ed debet 28 5 3 Register m 28 www hycontek com page2 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 CLOCK SYSTEM 30 6 1 Overall OE 30 6 2 Register address uite Di beo id adeo WR ein aU M idv a HR EHE dps 34 6 3 Register 35 7 INTERRUPT CONTROL SYSTEM avaa i Saa aasad 42 7 1 Overall 42 7 2 Register 43 7 3 Register UNCION 43 7 4 Modell program aden de ac eae 54 7 5 Model program function iiu eren cerne Ea terni e ie E 56 7 6 Model program description 7 56 8 WATCH DOG TIMER ada aana riaan aaa 57 8 1
72. 3 Register unctione bv 135 18 GPIO PT8 MANAGEMENT E 143 18 1 Overall description i rr e Rr ana NER FER AA 143 18 2 145 18 3 Registo TUNC 145 19 GPIO PT9 MANAGEMENT EE 153 www hycontek com page5 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 19 1 Overall de scription ciii tee ter ee oa c ee eee ene e Fe hax ede Ge ee 153 19 2 Register address 155 19 3 Register 155 20 GPIO PT10 MANAGEMENT nva ama 163 20 1 Overall description cnet RAN EE Ee ES 163 20 2 Register address ise ERE Ee t ER de a EU E dea au Ri dee aee ine e de ERE Re exeo deus 165 20 3 Register 165 21 1 169 21 1 Overall descriptlOn uice nte agn unde RD Xn X uua 169 21 2
73. 4000 MASK6 REG6 MASK7 7 INT Base Address 0 10 1 0x40010 MASK8 REG8 5 9 REG9 INT Base Address 0 14 PT2 0x40014 MASK10 REG10 MASK11 REG11 INT Base Address 0x18 UART2 0x40018 MASK12 REG12 MASK13 REG13 INT Base Address Ox1C TMB2 0x4001C MASK14 REG14 MASK15 REG15 Reserved 7 3 Register function 7 3 1 Interrupt control register INTCOM INT Base Address 0x00 0 40000 A ea ag E M 191 IS 18 14 3l 27 8 I2CIR UTxIR TRxIR STxIR TN I2CEIF I2CIF UTxIF URXIF STxIF SRxI D l c 2 RWO 0 Symbol INTCOM Interrupt Control Register O 31 24 23 22 21 20 19 18 17 16 MASK 12 2 6 SRxIE Aone 1 0 writing the register the Bit15 8 are Mask when reading the register the 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page43 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 5 8 are general registers Bit Description 2 error interrupt enable control Bit 21 I2CEIE mg 6 Oc oo 2C interrupt enable control Bit 20 I2CIE EI mg 6 Oc oo ART transmits TX interrupt enable control Bit 19 UTxIE BH mg
74. Band Gap Reference VDDA Hardware EUART VDD18 VDD3V 32 bit Hardware SPI VDD18 VDD3V Hardware 2 VDD18 VDD3V 2014 HYCON Technology Corp www hycontek com HYG N HYCON TECHNOLOGY Voltage Source VDD18 VDD3V VDDA VDDA VDDA VDD3V 0 16 198 01 27 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 5 2 Register address Power Management Register Address 31 24 23 16 15 8 7 0 PMU Base Address 0x00 0x40400 MASK REG1 MASKO REGO 5 3 Register function 5 3 1 Power management register PMU Power Management Base Address 0x00 0x40400 Symbol PMU PMU Control Register 31 28 27 24 dame _ R 0 ROW E 15 08 rval Bs Ale 12 1 oO MASK INN ENBGR ACMS ENRFO VDDLP ROW 0 Bit Description VDDA output voltage selection 00 VDDA 24V 19 18 VDAS 01 VDDA 2 7V 10 VDDA 3 0V 11 VDDA 3 3V VDDA LDO voltage source configuration for controlling the output voltage range of the VDDA 00 High impedance High Z Internally short circuited to the VDD3V the output of the VDDA is close to the VDD3V 10 Weak pull down the output of he is close to the VSS VDDA LDO the output of the VDDA can be adjusted 11 which is decided by the VDAS Band Gap voltage enablement control Bit O4 ENBGRO Disable 1 Enable when ENVA
75. Bit 31 15 RW RO 14 08 mM 54 3 0 MASK 10HR 1HR ROW 0 2 2 02 Bit Name Description Real time clock hour format am pm Bit6 0 AM or 24 hour system 1 PM it should be set as 1 if the HRF is set as 1 The tens place of the hour BCD code format 00 0 Bit 5 4 10HR 01 1 10 When 2 HRF 1 HRF 0 it is invalid 11 Invalid 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page281 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash Aa The one s place of the hour BCD code format 0000 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid Bit 3 0 1HR O ODN OA gt 30 3 4 Hardware RTC register RTCSMC RTC Base Address 0x41A0C ymbol RTCSMC RTC seconds and min Control Register For calendar i 31 24 23 Name MASK ROW 0 O 15 08 fe Bit Description Bit 22 20 10MIN The tens place of the minute BCD code format 000 0 001 010 011 100 101 110 20 NN 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page282 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash Aa 111 Invalid The one
76. CPI1S 01 OPOD OP amplifier output 10 Low frequency clock 15 CK 11 The input of the 1 from the IO port The frequency divider configuration of the input signal of the Capture1 0000 frequency 1 0001 frequency 2 0010 frequency 4 0011 frequency 8 0100 frequency 16 0101 frequency 32 0110 frequency 64 Bit 19 16 C1PS 0111 frequency 128 1000 frequency 256 1001 frequency 512 1010 frequency 1024 1011 frequency 2048 1100 frequency 4096 1101 frequency 8192 1110 frequency 16384 1111 frequency 32768 Capture2 trigger edge configuration Bit 02 TCPI2P 0 Rising edge trigger 1 Falling edge trigger Capture1 trigger edge configuration Bit01 TCP1P 0 Rising edge trigger 1 Falling edge trigger Timer C enablement control Bit 00 TCEN 0 Disable but the TCRO and are not cleared 1 Enable 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page103 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash 12 3 2 Timer C register TMCCR1 i HYGON HYCON TECHNOLOGY it 15 00 R X TCR1 Bit Name Description Bit 31 16 TCR2 Capture2 frequency capture counter Bit 15 00 TCR1 Capture1 frequency capture counter 12 4 Model program flow DrvTMB Open will enable the Timer B DrvCapture1 set Timer DrvCapture2 Open set Timer C1
77. Corp www hycontek com Set Wait Mode Set Mode Sleep Set Sleep Mode UG HY16F198 VO1 TC page295 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 32 LCD DRIVER 32 1 Overall description The LCD driver circuit is for the TN LCD and SYN LCD and it has the following features Built in voltage regulating circuit Regulated charge pump 4 stage adjustable driving voltage levels Support four kinds of LCD waveform operation 1 3 Duty 1 3 bias 3 mux 1 3bias 1 4 Duty 1 3 bias 4 mux 1 3bias 1 5 Duty 1 3 bias 5 mux 1 3bias 1 6 Duty 1 3 bias 6 mux 1 3bias Selectable input clock sources and programmable output frequency Blinking capability DSP 1 0 VLCD 2 0 IDF Duty 1 0 Display Data from GPIO Register LCD Control Unit LCD Panel 32 1 LCD structure diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page296 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 32 2 LCD initialization configuration Operating frequency and output frame frequency configurations The operating frequency can be provided by the 15 CK or HS CK which will pass two frequency dividers LCDE and LCDO to provide proper operating frequencies for the LCD output frame frequency The LCD operating waveform can be set by the output
78. Enable Bit 18 PT67IE 0 Disable 1 Enable PT6 7 Output Data PT67DO 0 Output Low 1 Output High PT6 7 Input Data Bit 16 PT67DI 0 Input Low 1 Input High PT6 6 Output Enable Bit 3 PT660E 0 Disable 1 Enable PT6 6 Input Enable Bit 2 PT66IE 0 Disable 1 Enable PT6 6 Output Data PT66DO Output Low 1 Output High PT6 6 Input Data Bit 0 PT66DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page131 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash When LCD Mode GPIO Base Address 0x5C 0x4085C Bk 50 m I BI M BS E oO SEG8 Data Bit Name Description LCD Segment 9 Data Segment Data LCD Segment 8 Data Segment Data Bit 21 16 SEG 9 Data Bit 5 0 SEG 8 Data 0 16 198 01 2014 HYCON Technology Corp page132 www hycontek com 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 17 GPIO PT7 MANAGEMENT 17 1 Overall description The PT7 has 8 IO pins which can be used as the common universal IO ports and can also be reused as the LCD function output port Different reuses need different configurations PAD PT7DI L PT7 DO U d
79. HYCON TECHNOLOGY 001 Gain 8 010 Reserved 011 Gain 16 100 Reserved 101 Reserved 110 Reserved 111 Gain 32 ADC positive signal input end selection 0000 AIOO 0001 AIO1 0010 AIO2 0011 0100 REFO 0101 OPO 0110 TSPO Bit 7 4 ADINP 0111 TSP1 1000 DAO 1001 VDDA 1010 AlO4 1011 AIO5 1100 AIO6 1101 AIO7 1110 Reserved 1111 Reserved Bit 3 0 ADINN ADC negative signal input end selection 0000 AIOO 0001 AIO1 0010 AIO2 0011 AIO3 0100 REFO 0101 OPO 0110 TSN1 0111 TSNO 1000 DAO 1001 VSS 1010 AlO4 1011 AIO5 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page191 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash airtel 1100 6 1101 7 1110 Reserved 1111 Reserved 22 3 3 Analog ADC register ADCCR2 ADC Base Address 0x08 0x41108 ADCCR2 ADC Control Register 2 31 16 Na ADCO RW it Name 0 ADCO 31 0 ADC transformed value output register only data higher than 24 bit are effective 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page192 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 22 4 Model program flow HYGON HYCON TECHNOLOGY
80. High PT7 0 Output Enable Bit 3 PT70OE 0 Disable 1 Enable PT7 0 Input Enable Bit 2 PT7OIE 0 Disable 1 Enable PT7 0 Output Data PT70DO 0 Output Low 1 Output High PT7 0 Input Data Bit 0 PT70DI 0 Input Low 1 Input High When LCD Mode GPIO Base Address 0x60 0x40860 Symbol SEG10 SEG11 PT7 Control Register 0 31 24 23 22 21 20 19 18 16 Name E SEG11 Data RW 1 mso FW LE IUE TH SEG10 Data Bit Name Description LCD Segment 11 Data Segment Data LCD Segment 10 Data Segment Data Bit 21 16 SEG 11 Data Bit 5 0 SEG 10 Data 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page136 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 17 3 2 PT7 2 PT7 3 register When GPIO Mode Base Address 0x64 0 40864 mask PT7300PT7201 Bt 1501 7 6 4M B B n 0 Bit Name Description PT7 3 Output Enable Bit 19 PT73OE 0 Disable 1 Enable PT7 3 Input Enable Bit18 PT73IE 0 Disable 1 Enable PT7 3 Output Data Bit 17 PT73DO 0 Output Low 1 Output High PT7 3 Input Data Bit 16 PT73DI 0 Input Low 1 Input High PT7 2 Output Enable 3
81. IDEL mode it will use lowest power consumption to perform the memory operation of the register and the SRAM During the IDEL mode the wide BandGap reference BOR and VDD18 LDO are enabled If the MCU is under the automatic wake up mode the low speed oscillator should be enabled 1uF 10yF 10uF 10yF I nb CL CH CP I VDD3V VLCD ENCHP 0 CLK Charge Pump Regulator LCD CLK LCD Charge VDD18 CP O 3 3V EN LCD Pump Regulator ENCHPIUE SUE LCDV 1 0 2 6 2 8 3 0 3 3 VDDA P NECS gt 2 4 2 7 3 0 3 3 VDDA b REFO ACMSIO EN REFO 0 1pF ADC common 1 510 voltage 0 STE ERI VSS REFO PT3 6 ENI FIG 5 1 Function block diagram www hycontek com page24 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Chip operating voltages VDD3V and VDD18 The operating voltage of the chip is inputted via the pin VDD3V and the voltage range is 2 2V 3 6V besides the pin should be connected to a 10 ground capacitor which can VDD3V become more stable If the operating voltage of the chip is used to drive a high current load the operating voltage of the c
82. IWDT interrupt enable 15 16 SYS EnableGIE 7 Enable GIE 17 18 while 1 Wait for Interrupt 20 21 22 HW1 ISR void 23 24 DrvTIMER ClearlntFlag E WDT Clear WDT interrupt flag 25 izi OxF Ili OxF 26 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 27 28 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page56 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 8 WATCH DOG TIMER WDT 8 1 Overall description The watch dog timer WDT is as the name implies the watcher of the chip and its main function is to generate the wake up event or execute basic reset function after the chip crashes accidentally Operation mode The WDT overflows and then generate the reset signal to reset the chip The WDT can be cleared by using software SLEEP mode The WDT is disabled and cannot work IDEL mode The WDT overflows and then generate the interrupt event to wake up the chip CWDT Clear Counter WODTP 2 0 Reset Signal ENWDT 0 Set TO on Overflow WDCK WDT Programmable Scaler WDTP 2 0 WDT Scalar 14 0 Non mask able Interrupt 000 FWT 2 001 FWT 8 010 FWT 32 011 FWT 128 WDT Interrupt 100 FWT 512 101 2048 IDLE 110 FWT 8192 111 32768 FIG 8 1 WDT block diagram 8 1 1 WDT operating instruction Setting the frequency
83. Mode Base Address 0X24 0X41F24 LCDCRO LCD Control Register 0 31 24 23 16 MASK ROW 0 15 8 1 0 MASK EN RShift ROW O i CL ai EN RShift Bit 1 0 EN RShft 1 0 Register address 0 41 24 Need to control MASK corresponding BIT1 BITO VLCD All Mode View ee ee Name Ren EN VLCDO EN Rs EN Rshit0 0 1 1 2 tf 0 0 1 1 2014 Technology Corp UG HY16F198 VO1 www hycontek com page300 0 9 pg 5 o3 0 0o 1 0 0 4 2 d 05 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 33 MODIFICATION RECORD HYGON HYCON TECHNOLOGY The following is the important modification of the document but it does not include the changes of the punctuation and character form Date Document Page Remark version 2014 10 01 V01 All First Edition 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page301
84. Output Enable Bit19 PT97OE 0 Disable 1 Enable PT9 7 Input Enable Bit 18 PT97IE 0 Disable 1 Enable PT9 7 Output Data PT97DO 0 Output Low 1 Output High PT9 7 Input Data Bit 16 PT97DI 0 Input Low 1 Input High PT9 6 Output Enable Bit 3 96 0 Disable 1 Enable PT9 6 Input Enable Bit 2 96 0 Disable 1 Enable PT9 6 Output Data PT96DO 0 Output Low 1 Output High PT9 6 Input Data Bit 0 PT96DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page161 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode GPIO Base Address 0x8C 0x4088C SEG33 Data Bit 501 7 60 5 4A Name MASK SEG32 Data Bit Name Description LCD Segment 33 Data Segment Data LCD Segment 32 Data Segment Data Bit 21 16 SEG 33 Data Bit 5 0 SEG 32 Data UG HY16F198 VO1 2014 HYCON Technology Corp page162 www hycontek com 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 20 10 20 1 Overall description The PT10 has 4 IO pins which can be used as the common universal IO ports and can also be reused as the LCD function output port Different reuses need different confi
85. PT16 external interrupt enable control Bit 22 PT16IE 0 Disable 1 Enable PT15IE PT15 external interrupt enable control Bit21 PT15IE 0 Disable 1 Enable www hycontek com page49 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYG N TECHNOLOGY 14 PT14 external interrupt enable control Bit20 PT14IE 0 Disable 1 Enable 1 PT13 external interrupt enable control Bit 19 PT13IE 0 Disable 1 Enable PT12IE PT12 external interrupt enable control Bit 18 PT121bE 0 Disable 1 Enable PT11IE PT11 external interrupt enable control 17 PT11IE 0 Disable 1 Enable PT10IE PT10 external interrupt enable control Bit 16 PT10IE 0 Disable 1 Enable PT1 Bit7 0 interrupt request Bit 15 8 PT1IR 0 Disable 1 Enable PT17IF PT17 external interrupt flag Bit 07 PT17IF 0 Normal 1 PT17 external interrupt occurs PT16IF PT16 external interrupt flag Bit 06 PT16IF 0 Normal 1 PT16 external interrupt occurs PT15IF PT15 external interrupt flag 05 PT15IF 0 Normal 1 PT15 external interrupt occurs PT14IF PT14 external interrupt flag Bit 04 PT14IF 0 Normal 1 PT14 external interrupt occurs PT13IF PT13 external interrupt flag Bit 03 PT13IF 0 Normal 1 PT13 external interrupt occurs PT12IF PT12 ext
86. Reverse output OPAMP built in capacitor purpose configuration Bit 4 OPCS 1 The capacitor serves as integrated capacitor and the lower end is connected to the OPOI 0 The capacitor serves as sampling capacitor and the lower end is connected to the VSS OPAMP output digital filter enable control Bit 3 OPDFR 0 Disable 1 Enable Pass through the 2us deglitch digital output function control Bit 2 OPDEN 0 Disable 1 Enable OPAMP analog output function control Bit 1 OPEO 0 Disable 1 Enable OPAMP function enable control Bit 0 ENOP 0 Disable 1 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com page203 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page204 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 23 3 2 Analog register 1 Base Address 0x04 0x41904 ol OPAMP1 OPAMP Control Register 1 ROW 0 Bit Name Description OPAMP positive input channel 6 Bit22 OPPS 6 0 Disable high impedance 1 Enable and connect to the AlO7 OPAMP positive input channel 5 Bit 21 OPPS 5 0 Disable high impedance 1 Enable and connect to the AlO6 OPAMP positive input channel 4 Bit 20 OPPS 4 0 Disable high impedance 1 Enable and connect to the AlO5 OPAMP positive input channel 3 Bit 19
87. SCK 1 Capture data at the second clock edge of the SCK SPI bus operating frequency polarity control 2 CPOL 0 low potential is idle 1 SCK high potential is idle SPI operating mode configuration Bit 11 M S 0 Passive mode 1 Active mode SPI function enable control O Disable 1 Enable 26 3 2 SPI register 1 SPI Base Address 0x04 0 40 04 SPI CR1 SPI Control Register 1 31 29 28 24 23 21 20 19 18 17 16 en d MASK ad ME tee UR Rowo RW 0 15 5 4 0 BE Bit Name Description Chip internal wake up CS signal simulator control applicable to the 3 wire mode Bit 20 CSO 0 CS signal simulator works 1 CS signal simulator stands by CS signal polarity configuration for enabling devices Bit 19 CSL 0 Low potential enablement 1 High potential enablement Data transmission order Bit 18 LBF 0 Transmit MSB first 1 Transmit LSB first Bit 17 16 MD SPI interface operating mode configuration 00 SPI standard 4 wire communication interface mode 01 SPI universal 3 wire interface mode 10 TI mode 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com page234 16 19 series user manual HYGON 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash TECHNOLOGY 11 mode SPI signal word length transmission configura
88. Support 8 periodical wake up period options 1 128 1 64 1 32 1 16 1 8 1 4 1 2 and 1 Support two time modes 12 24 systems 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page275 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash KEY 3 0 lt 2 0 gt PFEN O Digital Compensation Controller LSXT Pre Scalar Secondary Scalar RTC Pi scaler 128 64 32 16 8 4 2 1 LSRC Input 256 128 Periodic Timer Interrupt Mux LPYF Time BCD Year Month Day Wday Hour Min Sec TAF PTF RTCEn Alarm BCD Year Month Day Hour Min Sec 30 1 structure diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page276 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash Access the register The frequency of the RTC clock is different from that of the system clock thus the register will be updated after two RTC clock pulses if the user has written new data in the register The RTC data should be updated frequently A protection button for writing data in the register is provided When writing data in the RTC register the RTKEY button should be set as 0110 and other values of the RTKEY button will not allow any data to be written in the RTC register Please note that the RTC will not check the data format wr
89. TMC Set the capture signal input source which is to set the values of the CPI2S 0 Set the capture signal trigger edge which is to set the value of the TCPI2P If the TCI2 is selected to be the capture signal input source it is necessary to set the input to select the corresponding IO as the input mode If the interrupt function is used it is necessary to enable TMC1IE 1 and enable the global interrupt function GIE 1 Enable the TMC and enable the TCEN 12 2 Register address TMC Register Address 31 24 23 16 15 8 7 0 Base Address 0 14 0 40 14 MASK1 REG1 MASKO REGO TMA Base Address 0x18 0x40C18 TCR2 TCR2 TCR1 TCR1 12 3 Register function 12 3 1 1Timer C register TMCCRO Base Address 0x14 0x40C14 TMCCRO TMC Control Register 0 31 24 23 22 21 20 19 16 MASK CPSS ROW 0 15 08 MASK ROW 0 Bit Description Bit 23 CPI2R Timer B TC1 input mode control 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page102 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash TECHNOLOGY 0 Level trigger 1 Rising edge trigger Capture 1 input signal source selection Bit22 25 0 The input of the TC2 from the IO port 1 The input source the same with the capture 1 Capture 0 input signal source selection 00 CMPO comparator output Bit21 20
90. as 1 When the global interrupt GIE and the IO external interrupt function are enabled the chip will stop the current program right away and execute the IO external interrupt program 14 2 Register address 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page114 HY16F19 series user manual lt 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash HYG n HYCON TECHNOLOGY GPIO Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 10 0 40810 MASK1 PT2PU MASKO 2 Base Address 0 14 0 40814 5 PT2IE MASK2 PT2DO GPIO Base Address 0x18 0x40818 PT2DI Base Address Ox1C 0x4081C PT2IDF PT2ITT 2 Reserved 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page115 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 14 3 Register function 14 3 1 2 register PT2CRO GPIO Base Address 0x10 0 40810 Symbol PT2CRO PT2 Control Register 0 31 24 23 22 21 20 19 18 16 MASK PT2PU7 PT2PU6 PT2PU5 PT2PU4 2 2 2 PT2PU1 PT2PUO 0 RW ROW 0 RW 15 08 7 5 4 I3 2 m 0 MASK 2 7 2 6 2 2 4 2 2 2 2 1 PT20E0 ROW O Bit Name Description Port 2 internal pull up control Bit 23 16 PT2PU
91. be reused as the LCD function output port Different reuses need different configurations PAD PT6DI PT6IE L PT6DO U FIG 16 1 PT6 function block diagram The PT6 has input and output functions and different functions should be set by different controllers Output mode The controller PT6xOE 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT6xDO 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT6xIE 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enable
92. binary system the following figure is the transmission function diagram DAbit Voac_vretp Vac vie 256 _ Vpac Output Voltage IDA BIT Data 000h FFh FIG 24 1 DAC conversion diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page210 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash DAPS 2 0 0 VDD3 VDDA gt REFO OPO gt DA Vrefp DABIT 7 0 HYGON HYCON TECHNOLOGY DAOE 0 Internal DAO 256 PT3 1 X DABIT 7 0 DABIT DENEN 0X00 1 256 DA Vrefn E 0X01 2 256 254 256 255 256 DANS 2 0 FIG 24 2 DAC function block diagram 24 2 Register address DAC Register Address 31 24 23 16 15 8 7 0 0 00 0 41700 REGO DAC Base Address 0x04 0x41704 MASK1 REG1 Reserved 2014 HYCON Technology Corp www hycontek com 0 16 198 01 211 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 24 3 Register function 24 3 1 DAC register 0 y Bit Name Bit 1e MASK DANS 2 DAPS 2 0 DANS 1 0 DAOE ENDA
93. crystal oscillator configuration Matter needing attentions of using external crystal oscillators The operating voltage of the chip should be kept high when using a 16MHZ oscillator or above The stabilization time of the external 4MHZ 8MHZ crystal oscillators is about 25ms www hycontek com page30 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY and that of the external 32768HZ crystal oscillator is about 1 3s After the SLEEP instruction is executed all external crystal oscillators will stop Please pay attention to the I O configuration of the pins when connecting to external crystal oscillators when using the external crystal oscillators the pins configuration should be set as input mode and no internal pull up resistor is used so as to make sure they can work normally Besides the external resistors are necessary www hycontek com page31 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 1 2 Internal crystal oscillators HAO and LPO The HAO is an external high speed RC oscillator of the chip and its typical output frequency is 2MHZ AMHZ 10MHZ 16MHZ besides it has several features such as quick start high anti interference and low power consumption etc The output frequency of the HAO is adjustable therefore the user can adjust the output frequency of the HAO by software Matter needing attentions of using i
94. gt 32 bit MCU amp 64 KB Flash 25 1 1 Multiplexing input channel selector The input channel of the comparator is composed two parts one is the input channel of the comparator which can be set by the controller CPPS 1 0 CPNS 1 0 to respectively set the positive input channel and the negative input channel of the comparator the other one is the touch button input channel which can be set by the controller CPCLS 2 0 Via proper configuration and the combination of the input channels of the two parts the applications of the touch button be realized When using the comparator the user can set the control bit CPIS as 1 to realize the short circuit between the positive input end and the negative input end on the contrary if the CPIS is set as 0 the short circuit will not be realized CPNS 1 0 CPCLS 2 0 CHI go 2 0 CPRLH CPN CH2 01 CH3 e CL2 E RLO ENCLIN Non overlap TBCLK CPIS CL5 CL6 CH1 00 CL7 CH2 01 CH3 10 9 CL8 221111 V12 CH1 CPPS 1 0 25 2 input channel framework diagram 25 1 2 Built in multi node resistor and resistor node selection The comparator has a built in multi node resistor and the resistor includes three parts 22 5R 16R and 20R The 16R resistor is connected to a 16 stage resistor no
95. input of the master device and the output of the slave device MOSI pins are the output of the master device and the input of the slave device The SCK pin is from the serial communication clock output of the master device The CS pin is from the chip selection of the master device to enable the SPI communication of the slave device The MOSI MISO SCK CS pins of the master device or the salve device are connected together to execute tasks The communication is always enabled by the master device The master device transmits data to the slave device via the MOSI pins and the slave device replies to the master device via the MISO pins So that is full duplex communication the data input and output synchronously and use the same clock source Read Buffer SDIX shift register EI SO SDO Gs Multiplex Sync Write Buffer 2 CSX SPICK Clock Control 5 FIG 26 2 SPIIO pin diagram Function description pin setting The SPI pins be programmed for different I O pins Clock phase and clock polarity Four different clock types can be formed by software and controlled by the CPOL and CPHA registers 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page229 16 19 series user manual HYGON 21 bit ENOB
96. list partial 8 8 bit PWM waveform changes under different configurations of the TBC2 7 0 for your reference 8 8bit PWM Overflowing times of TBN 1 1 2 2 2 2 TBC2 0 1 2 3 4 5 6 if 8 9 10 2 2 5 5 5 5 RE 7 0 7 8 2 3 4 5 01h 1 2 N N NH N N NH N NH N NH N N NH N NH 02h 1 4 N N NH N N N NH N N N N N N N NH N www hycontek com page84 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 HYG N HYCON TECHNOLOGY N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 NH N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N 1 N N N N N N 1 8 1 16 1 32 1 64 1 128 1 256 3 4 5 8 7 8 15 16 04h 08h 10h 20h 40hh 80h 03h 05h 07h OFh HY16F19 series user manual 21 bit ENOB AADC 32 bit MCU 64 KB Flash ES z z EN gt 1 1 1 2 2 2 gt 1 1 1 Te Bp fp PES z 2 ES8 L 6 g 2 2 2 6 5 4 B 2 7 9 c 5 356 _ Se 2 2 2 2 2 g 2 gl im 9 2 2 A E i
97. negative short circuit switch control 20 VRSHRO 1 Short circuit switch opens Short circuit switch closes Reference voltage positive input source selection 00 Bit 19 18 VRPS 01 10 11 VDDA AIO2 AlO4 Reference buffer output REFO Reference voltage negative input source selection 00 Bit 17 16 VRNS 01 10 11 VSS AlO3 AlO5 Reference buffer output REFO Fast chopper stable mode configuration Bit 06 ADFDRO 1 2014 HYCON Technology Corp www hycontek com Normal mode the frequency of the chopper ADCLK 128 Fast chopper mode the frequency ADCLK 32 suitable for OSR lt 512 0 16 198 01 page188 16 19 series user manual HYGON 21 bit ZAADC gt 32 bit MCU 8 64 KB Flash ADC over sampling output frequency configuration on the condition that the clock source of the ADC is 327680Hz 0000 32768 Data output frequency 10sps 0001 16384 Data output frequency 20sps 0010 8192 Data output frequency 40sps 0011 4096 Data output frequency 80sps 0100 2048 Data output frequency 160sps 0101 1024 Data output frequency 320sps 0110 512 Data output frequency 640sps Bit 5 2 OSR 0111 276 Data output frequency 1280sps 1000 128 Data output frequency 2760sps 1001 64 Data output frequency 5120sps 1010 32 Data output frequency 10240sps 1011 Reserved 32768 1100 Reserved 32768 1101 Reserved 32768 1110 Reserved 32768 1111 Reserved 32768 Comb filter enable c
98. of the TMB is H8 or LS CK which will pass through the frequency divider to generate the frequency source TBCLK to provide the operating frequency for the TMB t provides the setting frequency divider TMCD 1 0 which can set different counting cycles for the TMB The clock source of the TMB can be set at the clock system control module TBR 16 bit timer counter register The TBR is a 16 bit timer counter register which can be separated into two independent 8 bit timer counter registers in order to satisfy the four different counting methods of the TMB The TBR will crease or decrease at each rising edge of the TBCLK under different counting methods the TBR will increase or decrease according to different conditions TBR can be automatically cleared by setting the control bit TBRST 1 as 1 and the control bit TBRST will automatically become 0 after the is cleared The program can also read the current counting value of the TBR for other purposes The TBEN is the enable control signal of the TMB If the bit is set as 1 the counting function of the TMB will be enabled if the bit is set as 0 the counting function of the will be disabled The TBEBS 1 0 is the counting trigger signal source controller the controller can provide four different counting trigger signal sources TBM 1 0 is the counting method controller of the TMB the controller can provide four www hycontek com page69 16 19 series user manual HYGO
99. of the minute under the alarm clock mode BCD code format 0000 0 0001 0010 0011 0100 Bit 11 8 1CMI 0101 0110 0111 1000 gt 1001 Other values Invalid Bit 6 4 10 5 tens place of the second under the alarm clock mode BCD code format 000 0 001 1 010 2 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page287 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 011 3 100 4 101 5 110 6 111 Invalid Bit 3 0 1CSE The one s place of the second under the alarm clock mode BCD code format 0000 0 0001 0010 0011 0100 0101 0110 0111 1000 OIN gt 1001 Other values Invalid 30 3 8 Hardware register RTC Base Address Ox1C 0x41A1C RTCYMDA RTC Year month date Control Register For alarm 31 24 Na Rw RO RW RW2 Bit 15 13 12 10 1CMO 10CDAT RW RW1 RWO Bit Name Description Bit 23 20 10CYE The tens place of the year under the alarm clock mode BCD code format 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 2014 HYCON Technology Corp UG HY16F198 VO1
100. or MSB is transmitted first If the LSB is set to be transmitted first the position where the data are stored will be influenced and the TXB effective data will be right justified For example if the BL is set to be under the 8 bit mode the received data will be stored at the TXB 7 0 if the BL is set to be under the 9 bit mode the received data will be stored at the TXB 8 0 and so on If the MSB is set to be transmitted first the TXB effective data will be left justified For example if the BL is set to be under the 8 bit mode the received data will be stored at the TXB 31 24 if the BL is set to be under the 9 bit mode the received data will be stored at the TXB 31 23 and so on 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page238 HY16F19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 26 4 Model program flow TERSSPITJ program starts settings Hardware initialization settings Detect Detect 26 5 Model program function WREN 0X06 WREN 0X06 WRITE 0x02 READ 0x03 Address 0x03 Address 0x03 Data 0X1 1 o Model name communication SPI interrupt settings The setting can be done via the SPI pins and the SPI register Test the write in function of the hardware SPI to the AT93C46 2014 HYCON Technology Corp www hycontek com
101. series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Set the counting cycle of the TMB and enable the TMB which means TBEN 1 and writing value in TBCO Select the operating mode duty cycle and output waveform phase of the PWM that is to set OOMD OOPMR and O1MD O1PMR and write values in TBC1 TBC2 Select the output IO port of the PWM and the corresponding port should be set as the output mode the enablement and disablement of the output 10 can control the output and disablement of the PWM if the user wants to completely disable the PWMs it is necessary to disable the TMB The waveform of the PWM is generated by the combination of the TBR TBCO TBC1 and and there are 6 kinds of operating modes thus the operating conditions of the operating modes are different from each other The 6 operating modes will be respectively specified later The usage conditions and the controls of the two independent PWMs PWMOO and PWMO therefore they will not be specified separately PWMA mode The PWMA mode is a 16 bit PWM the counting value of the TBR is compared with the TBC1 and the waveform period of the PWM is controlled by the TBCO PWM 1 when 15 0 gt TBC1 15 0 PWM 0 when 15 0 lt 15 0 PWM period PWM Period TBR 15 0 TMCD HS CK or LS PWM duty cycle PWM TBC1 TBR 15 0 1 PWM Duty Cycle PWM Duty TMCD HS CK orLS
102. set the 12C to use the third group SCL and SDA 3 and set the UART to use the third group Tx 3 and Rx 3 In this way the desired effect can be achieved by the different configuration of the pins The following table lists the reuse functions of all IO pins and their priority level O stands for the highest level and 6 stands for the lowest level Timer C Special Analog HIST Function INT Capture Funcion SPI 2 UART IP Analog 2 PWM Output i5 0 1 2 3 4 5 6 Priority 1 0 INT1 0 TCI1 1 CS 1 SCL 1 Tx 1 CH1 PWMO 1 PT1 1 INT1 1 TCI2 1 CK 1 SDA 1 Rx 1 CH2 PWM1_1 PT1 2 INT1 2 TCI1 2 MISO 1 SCL 2 2 1 CH3 PWMA2 1 PT1 3 INT1 3 TCI2 2 MOSI 1 SDA 2 Rx2 1 PWMS3 1 PT1 4 INT1 4 TCI1 3 CS 2 SCL 3 Tx 2 CL2 PWMO 2 PT1 5 INT1 5 TCI2 3 CK 2 SDA 3 2 CL3 PWM1 2 PT1 6 INT1 6 TCI1 4 MISO 2 SCL 4 2 2 CLA PWM2 2 PT1 7 INT1 7 TCI2 4 MOSI 2 SDA 4 2 2 PWM3 2 2 0 INT2 0 TCI1 5 CS 3 SCL 5 Tx 3 CL5 PWMO 3 2014 Technology Corp UG HY16F198 V01 www hycontek com page169 16 19 series user manual HYGON 21 bit ENOB 32 bit MCU amp 64 KB Flash PT2 1 INT2 1 TCI2 5 CK 3 SDA 5 Rx 3 CL6 PWM1 3 PT2 2 INT2 2 6 MISO 3 SCL 6 Tx
103. the corresponding IO port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT3DO 7 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT3IE 7 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the input mode of the corresponding IO port will be enabled if it is set as 0 the input mode of the corresponding IO port will be disabled Whether the current input status of the corresponding IO pin is 1 or 0 can be read the controller PT3DI 7 0 If the IO is set as the input mode and the chip is not connected to the external pull up resistor the internal pull up resistor should be enabled the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially in the low power mode it is suggested the IO pin should be set as the input mode If it
104. transmitted Data byte has been transmitted NACK has been received ACK has been received SPIA 0000 Data byte will be transmitted STA 30h SPIA 0010b A STOP has been received SPIA 1000 SPIA 0000 A START will be transmitted Idle or Slave Mode will be when the bus becomes free entered To Master Mode C To Slave Mode FIG 29 6 Slave Transmitter Mode 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page262 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 29 2 5 2 Slaver RX flow Slave Mode Enable STA 44h SPIA 0010b Own slave A W has been received ACK has been transmitted STA 45h SPIA 0010b Arbitration lost as master Own slave A W has been received NACK has been transmitted SPIA 0000 Data byte will be received NACK will be transmitted STA 48h SPIA 0010b Data byte has been received NACK has been transmitted STA 31h SPIA 0010b A repeated START has been received SPIA 1000 A START will be transmitted when the bus becomes free To Master Mode C FIG 29 7 Slave Receiver Mode 2014 HYCON Technology Corp www hycontek com SPIA 0001 Data byte will be received ACK will be transmitted STA 4Ch SPIA 0010b Data byte has been received ACK has been transmitted STA 30h SPIA 0010b A STOP has been received SPIA
105. waveform controller Duty 1 0 the frame frequency and the operating waveform should be set according to the specification of the LCD to be connected or ghost shadow work section or other abnormal phenomena may take place on the LCD The operating of the LCD is as shown in the following table LCKS cpE LCDO Pre scale Voltage doubling circuit and LCD operating voltage configuration The operating voltage source of the LCD is VLCD there are two methods to generate it The VLCD voltage source is inputted from outside and it is necessary to set the VL CD 2 0 as 0 and disable the voltage doubling circuit then the voltage should be inputted from the external VLCD pin to determine the LCD operating voltage When driving the LCD of big size or load the LCD output buffer Ben 0 should be set as 1 to enable the buffer in order to increase the driving ability of the LCD the contrary if the Ben 0 is set as 07 the buffer will be disabled to decrease the current consumption of the The different LCD voltage sources can be generated from the internal voltage doubling circuit by setting the voltage doubling circuit controller VLCD 2 0 as 2 5 to make it not vary with the operating voltage of the chip to influence the operation of the LCD VLCD 2 0 cab be set to provide four different operating voltages but the voltage doubling circuit should be enabled besides the voltage doubling circuit may influence high
106. working the power supply is inputted from the 1 to generate and output stable voltage from to the input of the VDD3V If the charge pump is not enabled the voltage of the will be equal to the voltage of the CP and the voltage will be also outputted from the CP to the input of the VDD3V If the charge pump boot circuit will not be used it is not necessary to install the external capacitors Ccp2 Ccp1 and Ccp3 the operating voltage of the chip will be directly provided by VDD3V When the charge pump is working it is suggested that the capacitances of the CH CL pins are 1uF and cannot be lower than O 1uF Itis suggested that the capacitance of the CP is at least ten times the capacitance of the capacitors connected in series between the CH CL pins If the capacitance of the CH CL pins is 1uF it is suggested that the capacitance of the is higher than or equal to 10uF If the capacitance of the is large the system will be more stable The connection of the output of the and the pins of VDD3V should be done by short circuit from the external PCB BandGap reference voltage and common mode voltage REFO When the VDDA is higher than 2 4V the analog circuit can work However the analog circuit needs the current offset and the reference voltage Therefore the BandGap reference voltage should be enabled before the analog circuit is enabled the BandGap reference voltage can be enabled by setting the re
107. 0 Bit Description The positive input source selection of the touch button function of the comparator 000 CL1 001 CL2 010 CL3 Bit 19 17 CPCLS 011 CL4 100 CL5 101 110 CL7 111 The built in non overlap function enable control of the comparator clock source of the non overlap controller is TBCLK Bit 16 ENCLINO Disable 1 Enable the TBCLK is used as the driving clock source of the non overlap controller The low step short circuit switch control of the built in step resistor of the comparator Bit 4 CPRL 0 The short circuit switch opens the low step resistor is not short circuited 1 The short circuit switch closes the low step resistor is short circuited The voltage source selection of the built in step resistor of the comparator 000 Disable no voltage supply under high impedance Bit 2 0 CPRH 001 CP consistent with the input voltage source of the charge pump 010 VDD3V chip operating voltage source 100 VDD18 1 8V voltage source from the internal LDO voltage regulator of the chip 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com 224 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 25 4 Model program flow The program starts Initialization settings CMP settings Wait for interrupt Interrupt the subprogram Clear the inter
108. 0 2 4 0 16M HSRC MCUCKS 0 HAOTR 7 0 Hz ENMCD 0 MCCK LSXT Enable ENOLS LSXT 32 768KHz LSRC 35KHz LSRC Table 6 1 CPU operating frequency source configuration diagram 32 768KHz O201sHYCONTechnologyCop SSS TO www hycontek com page33 HY16F19 series user manual 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash CKS 0 RTCEn 0 En 0 SPCD 2 0 Pre scale 1 244 2048 I2CEn 0 CRG 7 0 I2CK UACD 3 0 IOCKS 0 3 0 HYG N HYCON TECHNOLOGY ENACD 0 ADCD 1 0 Pre scale ENADC 0 ENWDT 0 K LSRC WDC TACKSIO ENTADIO LCKSID PDE 3 0 LCDO 1 0 Table 6 2 External peripheral operating frequency configuration diagram 6 2 Register address Clock Register Address 31 24 23 16 15 8 7 0 CLK Base Address 0x00 0 40300 REGO CLK Base Address 0x04 0x40304 HAOTR CLK Base Address 0x08 0x40308 MASK1 REG1 MASK2 REG2 REG3 MASK4 REG4 CLK Base Address 0x10 0x40310 5 5 5 MASK6 REG6 CLK Base Address 0 0 0 4030 CLK Base Address 0x14 0x40314 MASK7 REG7 Reserved 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page34 16 19 series user
109. 0000 Idle or Slave Mode will be entered To Slave Mode 0 16 198 01 263 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 29 2 6 2 General Call flow HYGON HYCON TECHNOLOGY Slave Mode Enable STA 01001x10b SPIA 0010b General call address has been received One data byte has been received NACK has been transmitted STA 01001x11b SPIA 0010b Arbitration lost as master General call address has been received One data byte has been received NACK has been transmitted SPIA 0000 Data byte will be received NACK will be transmitted STA 4Ah SPIA 0010b Data byte has been received NACK has been transmitted STA 4Eh SPIA 0010b Data byte has been received ACK has been transmitted STA 31h SPIA 0010b A repeated START has been received SPIA 1000 A START will be transmitted when the bus becomes free To Master Mode C SPIA 0001 Data byte will be received ACK will be transmitted STA 4Eh SPIA 0010b Data byte has been received ACK has been transmitted STA 30h SPIA 0010b A STOP has been received SPIA 0000 Idle or Slave Mode will be entered To Slave Mode FIG 29 8 General Call Mode 2014 HYCON Technology Corp www hycontek com 0 16 198 01 264 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 29 3 R
110. 07 1 RW DO Bit Register RX 7 0 for receiving address or data Bit 7 1 Rx A7 1 D7 10 Seto The received data is the 0 value of the read write instruction data RW DO 0 1 29 4 5 2 register 5 Transmitter Data Buffer 0 TXAD 2 Base Address 0x14 0x41014 ymbol 2 5 I2C Control Register 5 RW OO RO 2 Bt 1508 rt A 2 lt 3 c Transmission register 2 for transmitting the address 1 Set 1 Transmission register 2 for transmitting the read write instruction Bitj16 Flag DO or the value of the data 0 i 0 Seto 1 Sei Bit 15 8 1 A7 0 D7 0 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page270 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash or the value of the data 7 0 0 Set 0 1 Set 1 Transmission register 0 for transmitting the address or the value of the data 7 1 Bit 7 1 TXO 7 1 07 1 0 Set 0 1 Set 1 Transmission register O for transmitting the read write instruction or the value of the data 0 0 Set 0 1 Set 1 Bit 00 RW DO Note During the communication process when no data are transmitted the data transmission register should be set as OxFF Because the SDA bus tends to be locked at 0 when the lowest bit is drawn to low for a long time 29 5 Model program flow 2 Start 2
111. 1 Gain 1 1 2 Table 22 3 Reference voltage attenuation power The input impedance of the positive input channels and the negative input channels is 500 and the input voltage of the VREFP or VREFN cannot be lower than the VSS and VDDA if it is set as external input channel by the controller the input impedance can be increased However it is necessary to pay attention to the voltage range of the external input channel In order to obtain the high resolution and linearity of the ADC output it is suggested that the reference voltage AVREF 0 8V 1 8V 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page182 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY External Voltage input range input channel AIO2 AIO4 VSS VREFP VDDA AIO3 AIO5 VSS VREFN VDDA Table 22 4 Voltage input range of reference voltage external input channel 22 1 4 Input bias of input signal The ADC has zero point bias translation controller and the zero point bias translation controller DCSET 3 0 can change the position of the zero point of the signal to prevent the voltage of the input signal from being too high to exceed the maximal measurement range After the signal to be measured adjusted via the pre PGA the ADC modulator and the zero point bias translation the calculation formula of the equivalent signal to be measured ASI 1 i
112. 11b it will be automatically enabled ADC analog ground input source selection Bit 03 ACMS 0 External analog ground 1 Internal analog ground used with the ADC Bit 17 16 ENVA 01 Charge Pump enablement control Bit 02 ENCHP Disable 1 Enable www hycontek com page28 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Common mode voltage REFO enablement control Bit 01 ENRFO Disable 1 Enable VDD18 LDO low power control Bit 00 VDDLP 0 Normal the bit should be set as 0 after the SLEEP mode 1 Low power www hycontek com page29 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 CLOCK SYSTEM 6 1 Overall description The clock control system provides the clocks for the whole chip including the system clocks CPU clock APB clock and all peripheral operating clocks timer communication interface RTC analog circuit etc Each function module has a clock switch controller clock source selection and frequency divider Under the SLEEP mode the controller always closes the external crystal oscillators internal crystal oscillators and system clocks to minimize the system power consumption The operating clock sources include the external crystal oscillators internal HAO and LPO oscillators with the frequency divider the frequency sources of the CPU and the peripheral devices can be flexibly allocate
113. 15 8 10h 11h 12h TBR 7 0 TBRLes TBRLimay 00h Oth TBRLimayr1 TBRLimay 00h Oth TBRL mav 1 TMBIF lt ___ Clear by user em by user FIG 10 5 Schematic view of counting waveform of counting method 3 www hycontek com page75 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 10 1 2 PWM function mode When the timer B works under the PWM mode the combinations of the different counting methods and different PWM mode selectors can generate different PWM waveforms chip has only two PWMs PWMO PWM 1 which be simply considered two PWM waveform generators the combinations of the different counting methods and different PWM operating modes can generate many kinds of PWM waveforms The chip provides many output pins for the output of the PWM and each PWM waveform generator is corresponding to 8 output IO ports therefore the usage and output of the PWM is very flexible However the TMB is necessary for the function that is to say the TMB should be enabled to set the counting cycle of the TMB Each of the PWM waveform generators PWMO PWM 1 has many operating modes PWMB PWMC PWMD PWME PWMF and PWMG operating modes of the PWM1 can be changed by setting the control bits OOMD 2 0 and O1MD 2 1 The phase of the output waveform of the PWM can be changed by setting the control bits O1PMR and OOPMR The user can c
114. 2 3 CL7 PWM2 3 2 3 INT2 3 2 6 MOSI 3 SDA 6 Rx2 3 CL8 PWM3 3 2 4 INT24 TCI1 7 LS XOUT CS 4 SCL 7 Tx 4 PWMO 4 PT2 5 INT2 5 TCI2 7 LS XIN CK 4 SDA 7 Rx 4 PWM1 4 PT2 6 INT2 6 TCI 8 HS MISO 4 SCL 8 2 4 PWM2 4 2 7 INT2 7 TCI2 8 HS XOUT MOSI 4 SDA 8 Rx2 4 PWM3 4 PT3 0 1 AIO8 PT3 1 OPO2 DAO PT3 2 AlO4 PT3 3 AIO5 PT3 4 AlO6 PT3 5 AIO7 PT3 6 REFO PT3 7 OPO AIOO AIO1 AIO1 AIO2 AIO2 COMO COMO COM1 COM 1 2 COM2 COM3 COM 3 PT10 2 oe AISEG 0 PT10 3 5 1 6 0 2 6 1 3 2 4 6 3 5 4 SEG 6 PT6 5 SEG 7 PT6 6 SEG 8 6 7 9 7 0 10 PT7 1 4 SEG 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page170 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY PT7 2 SEG 12 PT7 3 2 SEG 13 PT7 4 SEG 14 PT7 5 3 SEG 15 PT7 6 SEG 16 PT7 7 4 SEG 17 8 0 18 CS 5 5 PWMO 5 PT8 1 5 SEG 19 CK 5 Rx 5 1 5 PT8 2 SEG20 MISO 5 2 5 PWM2 5 PT8 3 6 SEG21 MOSI 5 Rx2 5 PWMS3 5 PT8 4 SEG22 CS 6 Tx 6 PWMO 6 PT8 5 7 SEG23 CK 6 Rx 6 PWM1 6 PT8 6 SEG24 MISO 6 2 6 PWM2 6 PT8 7
115. 2 bit MCU HY Protool 2 Wi USB2 0 USB control is 9 Board gt FIG 3 4 Chip development connection diagram www hycontek com page21 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 4 SOC REGISTER 4 1 Overall description Manage the operating mode of the system and the reset status of the chip such as WDT external reset under voltage reset etc 4 2 Register address SoC Status Register Address 31 24 23 16 15 8 7 0 SoC Status Base Address 0x04 0x40104 MASKO REGO Reserved 4 3 Register function Operate the register SoC 4 can set the operating mode of the system as SLEEP mode IDEL mode WAIT mode The user can check the register SoC 3 0 to understand what the current operating mode of the system is The setting of the operating mode of the chip will be specified at the chapter 25 4 3 1 SOC register SoC Status Base Address 0x04 0x40104 SoC Status Register 31 24 23 16 ICE Configuration SoC Configuration R OFh R COh Bit 158 7 0 Fere Fors IDLE Fse Fwoog Frst Name Power Good Flag Bit 06 Fpre 0 Normal 1 Power Good has already been triggered before CPU Core Reset Flag Bit 05 Forst 0 Normal 1 Core has already been triggered before IDEL Mode Control Bit 04 IDLE 0 Sleep Mode 1 Mod
116. 5 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash therefore the GTS be derived or slope NDS Vis o K Vis US 273 15 289 S Equation 22 4 Grs 1 TPS eH Jb Le TPS HE gt GERE The gain or slope of the TPS sensor The voltage of the TPS sensor Environmental temperature Absolute temperature TPS model description If the temperature calibration point is 25 298 15 Configuration 1 the measurement result is VTSP 25 C 52 515 1 Configuration 2 the measurement result is 5 25 53 626mvV 2 1 2 2 to obtain AVTS 27 C 53 0705mV VTSQO K 0 0mV The curve slope is GTS VTS 298 15 K 5 0 298 15 0 178uV K Thus the temperature of any points is TC VTSQ T GTS 285 22 1 7 ADC operation description The ADC is the A 2 structure of 24 bit resolution If the user wants to enable the functions of the ADC some peripheral circuits should be correct set The power supply of the ADC is the VDDA voltage Thus the VDDA should be higher than 2 4V If the user wants to better the performance of the ADC a stable VDDA power supply is a must the VDDA needs some time to get ready the ADD should start the measurement after the VDDA
117. 5IE 0 Disable 1 Enable PT9 5 Output Data PT95DO 0 Output Low 1 Output High PT9 5 Input Data Bit 16 PT95DI 0 Input Low 1 Input High PT9 4 Output Enable Bit 3 PT94OE 0 Disable 1 Enable PT9 4 Input Enable Bit 2 94 0 Disable 1 Enable PT9 4 Output Data Bit 1 PT94DO 0 Output Low 1 Output High PT9 4 Input Data Bit 0 PT94DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page159 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode Base Address 0x88 0x40888 Name MASK SEG31 Data Bit 1501 1 4 3 B m W Name MASK SEG30 Data Bit Name Description LCD Segment 31 Data Segment Data LCD Segment 30 Data Segment Data Bit 21 16 SEG 31 Data Bit 5 0 SEG 30 Data 0 16 198 01 2014 HYCON Technology Corp page160 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 19 3 4 9 6 9 7 register When GPIO Mode GPIO Base Address 0x8C 0x4088C PTSTDOPTO7D Bt 501 7 68 0 Bit Name Description PT9 7
118. 6 oo ART receives RX interrupt enable control 181 URxIE B o D Enable PI transmits TX interrupt enable control 42 Bi 17 STxIE EI mg 6 Oc oo receives RX interrupt enable control Bit 16 SRxIE 2C interrupt error request Bit 13 I2CEIR ii 52 512 2C interrupt request Bit 12 I2CIR Interrupt B 2 S ART Tx interrupt request Bit 11 UTxIR B 2 3 D Interrupt ART Rx interrupt request Bit 10 TRxIR nie 52 4 3 A c 512 CD Tx interrupt request Bi 9 STxIR 5 2 3 5 8 e BHE mg 6 Oc oo Bit 8 SRxIR CD Rx interrupt request www hycontek com page44 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 0 Interrupt 2 error interrupt flag level trigger 12CEIF 0 Normal Bil04 Noma Nomad 0 Normal BNO2 URXIF 0 Noma SPI transmission TX interrupt flag level trigger Bi STXIF 0 0 5 SPI reception RX interrupt flag level trigger Bigoo SRXIF 0 7 3 2 Interrupt control register INTTMR INT Base Address 0x04 0x40004 INTTMR Interrupt Control Register 1 Bit 31 24 23 22 21 20 19 18 17 16 Name MASK J RTCIEWDTIE TMCAIE TMCOIE TMBIE TMAIE 0 RW ROW 0 RW
119. 6 CM RTC clock frequency compensation value configuration 0111111 126 PPM crystal oscillator frequency compensation maximum 0111110 124 PPM crystal oscillator frequency compensation Incremental step 2 PPM crystal oscillator frequency compensation 0000001 2 PPM crystal oscillator frequency compensation 0000000 0 PPM crystal oscillator frequency compensation 1000000 0 PPM crystal oscillator frequency compensation 1000001 2 PPM crystal oscillator frequency compensation Decremental step 2 PPM crystal oscillator frequency compensation 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page280 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1111110 124 PPM crystal oscillator frequency compensation 1111111 126 PPM crystal oscillator frequency compensation minimum RTC high speed clock source enable control it is suggested that the function be enabled under the test mode Bit4 CKH 0 Disable the low speed clock source is used 1 Enable the high speed clock source is used Timer timing wake up time configuration 000 1 128 s 001 1 64 s 010 1 32 s Bit2 0 PT 011 1 16 s 100 1 8 s 101 1 4 s 110 1 25 111 15 30 3 3 Hardware register Base Address 0x08 0x41A08 RTCHRC RTC Hour Control Register For calendar
120. 6 3 Input Data Bit 16 PT63DI 0 Input Low 1 Input High PT6 2 Output Enable Bit 3 PT620E 0 Disable 1 Enable PT6 2 Input Enable Bit 2 62 0 Disable 1 Enable PT6 2 Output Data Bit 1 PT62DO 0 Output Low 1 Output High PT6 2 Input Data Bit 0 PT62DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page127 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash When LCD Mode Base Address 0x54 0x40854 Bt 809 B BI M Bl El JU SEG4 Data Bit Name Description LCD Segment 5 Data Segment Data LCD Segment 4 Data Segment Data Bit 21 16 SEG 5 Data Bit b 0 SEG 4 Data 0 16 198 01 2014 HYCON Technology Corp page128 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 16 3 3 6 4 6 5 register When GPIO Mode GPIO Base Address 0x58 0 40858 Name MASK PT 5OEPTGSIE Bt 501 7 68 4M B B n 0 Bit Name Description PT6 5 Output Enable Bit 19 65 0 Disable 1 Enable PT6 5 Input Enable Bit 18 PT65IE 0 Disable 1 Enable PT6 5 Out
121. 7 0 as 20h which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 64 output periods as one set where 63 of them continuously outputs N and the last one outputs N 1 Set the TBC2 7 0 as 40h which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 128 output periods as one set where 127 of them continuously outputs N and the last one outputs N 1 Set the TBC2 7 0 as 80h which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 256 output periods as one set where 255 of them continuously outputs N and the last one outputs N 1 m Logic calculation OR superposition type Only 1 2 1 4 1 2 1 8 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 2 1 4 1 8 1 16 1 32 1 64 1 256 are used to illustrated Set the TBC2 7 0 as 03h 1 2 1 4 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 4 output periods as one set where one of them outputs N and then the other 3 output N 1 Set the TBC2 7 0 05h 1 2 1 8 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 8 output periods as one set where 3 of them output N and then the other 5 output N 1 Set the TBC2 7 0 as 09h 1 2 1 16 which makes the waveform of the PWM duty cycle generates the
122. 83DI Input Low 1 Input High PT8 2 Output Enable Bit 3 PT82OE 0 Disable 1 Enable PT8 2 Input Enable Bit 2 PT82IE 0 Disable 1 Enable PT8 2 Output Data Bit 1 PT82DO Output Low 1 Output High PT8 2 Input Data Bit 0 PT82DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com page147 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash When LCD Mode GPIO Base Address 0 74 0 40874 Name MASK SEG21 Data Bit 1501 7 6 5 4 B B m W SEG20 Data Bit Name Description LCD Segment 21 Data Segment Data LCD Segment 20 Data Segment Data Bit 21 16 SEG 21 Data Bit b 0 SEG 20 Data 0 16 198 01 2014 HYCON Technology Corp page148 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 18 3 3 PT8 4 PT8 5 register When GPIO Mode Base Address 0x78 0 40878 Name MASK PTB5OEPTBSIE Bt 501 7 68 M B B n 0 Bit Name Description PT8 5 Output Enable Bit 19 PT85OE 0 Disable 1 Enable PT8 5 Input Enable Bit 18 PT85IE 0 Disable 1 Enable PT8 5 Output Data Bit 17
123. A Table 22 1 Input signal voltage range table 22 1 2 Built in gain amplifier The ADC has two built in gain amplifiers one is the low noise low temperature coefficient programmable gain amplifier PGA whose magnifying power is 8 16 32 the other one is the programmable gain amplifier 2 whose magnifying power is 1 2 and 4 Thus the maximal magnifying power of the combination of the two gain amplifiers is 128 However the magnifying power is in inverse proportion to the effective number of bits ENOB of the ADC output if the magnifying power is larger the ENOB will be smaller Thus the magnifying power should be set according to the actual requirements The magnifying power of the PGA can be set by the controller PGA 2 0 and the selection of the magnifying power of the PGA is as shown in the following table The magnifying power of the ADC modulator can be set by the controller ADGN 1 0 and the selection of the magnifying power of the ADC modulator is as shown in the following table PGA ADC Modulator PGA 2 0 000 001 011 111 ADGN 1 0 00 01 10 11 Magnifying Disable x 8 x16 x32 Magnifying x1 x2 RSV x4 power power Table 22 2 Internal gain magnifying power 22 1 3 Reference voltage input channel The reference voltage input of the ADC is fully differential input mode in other words the reference voltage input end is composed of the positive input end and negative inpu
124. AADC 32 bit MCU amp 64 KB Flash When 1 1 LELIELELELELELE LI CK Q CPOL 0 MLL LL LLY SDI master SDO Hi Z master CS master Strobe FIG 26 4 SPI active mode clock diagram CPHA 1 Data frame format The bit length of the transaction word for transmission and reception can be defined in the SPITBL lt 4 0 gt The lowest bit length is 4 bits and the highest bit length is 32 bits The transmission format of the data of the shift register can be to transmit the MSB first or transmit the LSB first which is defined by the SPILBF If the SPILBF is 0 the data transmission format is to transmit the MSB of the shift register first Then the second MSB is transmitted finally the LSB is transmitted If the SPILBF is 1 the data transmission format is to transmit the LSB of the shift register first Select the level from the slave device chip The CS pin can be defined as 0 or 1 low potential or high potential to enable the slave device That is controlled by the SPISCL register If the SPISCL of the master device is 0 the CS pin will output 0 low potential to enable the slave device On the other hand if the SPISCL is 1 the CS pin will output 1 high potential to enable the slave device If the SPISCL of the slave device is 0 the slave device will be enabled after receiving the input 0 low potential of the CS On the other hand if the SPISCL of the slav
125. B Flash HYCON TECHNOLOGY 24 year sCurTime u32Year backward reading_year 25 asm NOP 26 27 return 0 28 29 00 01 void RTC_Initial void 02 03 RTC 04 08 0x8080ff04 05 RTC KEY 06 DrvRTC WriteEnable 07 00 0 0404 08 09 11 ClockSource E INTERNAL CLOCK 35KHz 12 DrvRTC ClockSource E EXTERNAL CLOCK 32768Hz 13 14 DrvRTC PeriodicTimeEnable 0 set 1 128 15 DrvRTC 16 DrvRTC_HourFormat 0 17 18 asm NOP 19 S DRVRTC TIME DATA T sCurTime setting start 20 DrvRTC Read DRVRTC CURRENT TIME amp sCurTime 21 sCurTime u8cClockDisplay 1 22 sCurTime u8cAmPm 0 23 sCurTime u32cSecond 19 setting_second 24 sCurTime u32cMinute 50 setting _munite 25 sCurTime u32cHour 10 setting hour 26 sCurTime u32cDayOfWeek 5 setting week 27 sCurTime u32cDay 9 setting date 28 sCurTime u32cMonth 8 setting_month 29 sCurTime u32Year 2013 setting year 30 sCurTime u8lsEnableWakeUp 0 31 DrvRTC Write DRVRTC CURRENT TIME amp sCurTime 32 33 34 2014 Technology Corp www hycontek com UG HY16F198 VO1 TC page292 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash
126. BCO on the basis that the step is 1 16 bit up down counter triangle wave type counting method 01 the counting will increase to the maximum TBCO on the basis that the step is 1 and then decrease to O 2 independent 8 Bit up counters TBR 15 8 and TBR 7 0 sawtooth wave type counting method the two counters will increase to the maximums TBCO 15 8 and TBCO 7 0 at the same time on the basis that the step is 1 2 8 Bit up counters TBR 15 8 and TBR 7 0 sawtooth wave type counting method with step being 1 after the counter 11 TBR 7 0 increases and then overflows the counter TBR 15 8 is automatically added by 1 and then the TBR 7 0 restarts the counting from O Timer B counting trigger mode selection 00 1 Always enable continuous counting method CMPO trigger the multi function comparator to output high Bit 1 0 TBEBS 01 potential 10 OPOD trigger the OP amplifier to output high potential trigger the output of the Timer C to output high 11 potential Bit 3 2 TBM 10 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page90 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 10 3 2 Timer register TMBCR1 Base Address 0x08 0 40 08 TMBCR1 TMB Control Register 1 Bit 31 22 21 20 19 18 PWMF PWMD PWMC 1 U UJ V gt R X 15 0 Timer B counting value R
127. C 0x40E1C 31 27 15 8 e Z z 4 w a Bit Name Description Bit 24 16 Tx Data Tx Data Buffer Bit 7 0 Rx Data Rx Data Buffer 28 3 Model program flow BEBSUART pij Temp AGA ESAE DUR REEL The program starts IO setting Hardware UART initialization settings and display Detect Transmit the current Temp Interrupt the subprogram Clear the interrupt flag 2014 HYCON Technology Corp www hycontek com UART2CR3 UART2 Control Register 3 24 16 Tx Data W X 7 0 Rx Data R X 0 16 198 01 252 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash The current Temp is changed to be the reception value Return to the main program 28 4 Model program function Model name communication protocol EUART interrupt setting Connect the TX and RX PIN to the RS232 related circuits 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page253 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash 28 5 Model program description Main program HYG N HYCON TECHNOLOGY
128. C and Multi Comparator moreover the HY16F19 series products provide high performance peripheral interfaces such as the EAURT SPI I2C GPIO and built in power management system etc and support low voltage detection and multiple peripheral interface wake up functions The HY16F19 series products are of low voltage low power low stand by current high integrity and high efficient operation and support the 32 bit micro controller of the development platform Therefore the HY16F19 series products can provide various resources for designers to design a low current and low cost mixed signal processing system The AFE circuit of the controller includes an 8 bit D A converter a Rail to Rail OPAMP and a Rail to Rail input comparator n particular 8 bit D A converter has monotonicity which is a step resistor and the least significant bit LSB is close to 730 ohm and the resistor has the low temperature coefficient The Rail to Rail OPAMP has an input network which is applicable for the differential analog circuit configuration such as integrator current to voltage converter programmable gain amplifier and successive approximation A D converter The Rail to Rail input comparator can continuously monitor analog signals by extremely low power consumption thus it can serves as a power supply voltage monitor external wake up triggering source or capacitive touch key driver The 24 bits A D converter with extremely low noise is embedded Its
129. CMP_OutputPinEnable 0 Enable CMP digital output to port 11 0 PT1 7 12 13 14 DrvCMP ClearlntFlag Clear CMP interrupt flag 15 DrvCMP Enablelnt Enable CMP Interrupt 16 17 18 19 SYS_EnableGIE 7 Enable GIE Global Interrupt Enable 20 while 1 loop 21 22 23 HW3 ISR void 2014 HYCON Technology Corp mI erv TC www hycontek com page226 16 19 series user manual HYGON 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash vines se 24 25 DrvCMP ClearlntFlag Clear CMP interrupt flag 26 27 25 7 application circuit It serves as low voltage detector lt e lt CPRH 3 E CPNS oo CPDF CPOR mux REO u CPIS d CMPO CPRLS 208 no 245 1 1 v12 pa CPPS 25 8 CMP application circuit Il It is used to measure capacitors lt 2 9 CPNS N lt 2258 T M CPDF CPOR ri 16 RLO 16R 2 7 CPIS a CPRLS 1 20R 245 1 7 CH2 4 71 pr CPPS p d Mu Voltage lt CH2 _ Threshold Voltage is set by CPDA lt 3 0 gt amp CPDM lt 3 0 gt External RC Use TMC to WV capture time Time 2014 HYCON Technology Corp UG HY16F198 V01
130. COPS 0 Port 3 0 1 Port 3 1 Rail to Rail OPAMP digital signal output port enable control Bit18 PTCOPE 0 Disable no output 1 Enable output to the set target port Comparator output end IO port enable control Bit 16 PTCCPE 0 Disable only used as a common IO and no signal outputted 1 Enable Capture comparator signal input end IO selection 000 Port 1 0 Port 1 1 2 Port 7 1 001 Port 1 2 Port 1 3 2 Port 7 3 010 Port 1 4 Port 1 5 2 Port 7 5 011 Port 1 6 Port 1 7 2 Port 7 7 100 Port 2 0 Port 2 1 2 Port 8 1 101 Port 2 2 TCI Port 2 3 2 Port 8 3 110 Port 2 4 Port 2 5 2 Port 8 5 111 Port 2 6 Port 2 7 2 Port 8 7 PWM output end IO port selection 000 Port 1 0 ZPWMO Port 1 1 ZPWM1 001 Port 1 4 ZPWMO Port 1 5 PWM1 010 Port 2 0 ZPWMO Port 2 1 PWM1 011 Port 2 4 ZPWMO Port 2 5 PWM1 100 Port 8 0 ZPWMO Port 8 1 PWM1 101 Port 8 4 ZPWMO Port 8 5 lt 1 110 Port 9 0 ZPWMO Port 9 1 ZPWM1 111 Port 9 4 ZPWMO Port 9 5 ZPWM1 PWM 1 IO port input enable control Bit1 PTPW1E 0 Disable no output from the IO port 1 Enable the output port is set by the PTPW PTPWOE PWM IO port input enable control 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page172 16 19 series user manual HYGON 21 bit ENOB ZAADC 32
131. DC is 200K The positive and negative signal input channels can be selected via the controllers ADINP 3 0 and ADINN 3 0 however the positive input end can only select one signal input channel at a time and the negative input end can only select one signal input channel at a time positive and negative input ends can select the same input channel in this way the differential signal is close to 0 and only the offset is left The ADC has an internal signal input channel short circuit switch the positive and negative the input ends can be set short circuit via the control bit VISHR The following figure lists the signal input channels of the positive and negative ends 0111 TSP1 0111 5 0 E 1000 1000 BINNEN es FIG 22 2 ADC signal input channel The input signal is internally amplified and transferred so the voltage range of the input signal is also limited 5 as to obtain high resolution and linearity of the ADC outputs it is suggested the differential voltage of the input signal beASI x0 9 AVREF ASIZINP INN The input signal voltages are as shown in the following table 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page180 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY External input Voltage input range channel ADINP VSS 0 2V INP VDDA ADINN VSS 0 2V INN VDD
132. DI 0 Input Low 1 Input High PT7 4 Output Enable Bit 3 PT74OE 0 Disable 1 Enable PT7 4 Input Enable Bit 2 0 Disable 1 Enable PT7 4 Output Data PT74DO 0 Output Low 1 Output High PT7 4 Input Data Bit 0 PT74DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page139 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode Base Address 0x68 0x40868 Name SEG15 Data Bt 115 08 7 6 5 B3 B m W Name MASK SEG14 Data Bit Name Description LCD Segment 15 Data Segment Data LCD Segment 14 Data Segment Data Bit 21 16 SEG 15 Data Bit b 0 SEG 14 Data UG HY16F198 VO1 2014 HYCON Technology Corp page140 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 17 3 4 PT7 6 PT7 7 register When GPIO Mode Base Address 0x4086C Symbol PT76CFG PT77CFG PT7 Control Register 3 31 24 23 22 21 20 19 18 16 mask Bt 501 7 68 4 B B n 0 Bit Name Descriptio
133. E OPOD 1i 9 Pte H 414 LS 19277 FIG 10 1 B block diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page68 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 10 1 1 Timer mode The Timer B is a 16 bit up counter which can be used to generate the PWM waveforms It can be used to perform the time counting time controlling clock generating etc and can generate the interrupt signal when the counter overflow takes place The TMB can be operated under the operation mode and the IDEL mode It has four different counting methods and can generate the counting values with different frequencies 16 bit up counting method which can generate the interrupt signal 16 bit counting method it will increase to the overflow value and then decrease to 0 which can generate the interrupt signal Two independent 8 bit up counting methods the low 8 bit counter overflows and then the high 8 bit counter is automatically added by 1 which can generate the interrupt signal It has four different counting trigger signal sources which can be applied to count different events Continuous counting method is always enabled The comparator outputs CMPO high potential trigger The OP amplifier outputs OPOD high potential trigger The Timer C outputs CPI1 high potential trigger The operating clock source
134. Each Timer A interrupt will reverse the IO 2 0 05 before the interrupt and PT2 0x0A after the interrupt www hycontek com page65 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 9 6 Model program description 00 01 include HY16F19X h 02 03 unsigned int i 04 05 int main void 06 07 0 05 08 DrvGPIO Open E 2 0 IO OUTPUT 2 0 3 Set Output 09 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 10 11 DrvTMA Open 15 0 A Overflow 12 15 taclk 65536 32 TMRDV 32 13 HS CK 14 15 DrvTIMER ClearlntFlag E Clear Timer A interrupt flag 16 DrvTIMER Enablelnt E TMA A interrupt enable 17 18 SYS EnableGIE 7 Enable GIE 20 21 while 1 Wait for Interrupt 227 23 24 void HW1 ISR void 25 26 DrvTIMER ClearlntFlag E Clear TMA interrupt flag 27 izi OxF Ili OxF 28 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 29 30 www hycontek com page66 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 10 TIMER B 10 1 Overall description The Timer B is a 16 bit counter which can be used to perform time counting time controlling clock generating and time delaying etc It
135. G 3 2 The total length of a register is 32 bit and most registers have 16 MASK bits The MASK bits include two 8 bit groups and each 8 bit group controls corresponding 8 control register bits According to the content allocation of a register BIT 31 24 controls BIT 23 16 and BIT 15 8 controls BIT 7 0 Only when the MASK bit is 1 the corresponding control bit can be validly written in For example if a user wants to write 101010b in BIT 5 0 and the write value of the register should be 0011111100101010b where 00111111b are the MASK bits of BIT 5 0 and can make written in corresponding control bits valid and 00101010b are the values written in BIT 5 0 INT Base Address 0x10 0x40010 Symbol INTPT1 PT1 Interrupt Control Register 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page17 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY RW 0 Bit 15 08 6 9 3 fy MASK PT17IF PT16IF PT15IF PT14IF PT13IF PT12IF PT11IF PT10IF ROW 0 RWO 0 FIG 3 2 Basic structure of register 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page1 8 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 3 3 Static random access memory SRAM HY16F198 has a 8Kbyte SRAM The initial address is from 0 00000 to 0x02000 MCU can select to access on
136. HS CK 1 LS CK Timer B C clock source enablement control 0 Disable 1 Enable Timer B C clock source frequency divider configuration 00 clock 1 01 clock 2 10 clock 4 11 clock 8 Timer A clock source selection 0 HS CK 1 LS CK Timer A clock source frequency divider configuration 0 Disable the frequency divider 1 Timer A clock 32 MCU input clock source frequency divider configuration 0 MCU clock 1 1 MCU clock 2 MCU input clock source selection MCUCKS 0 HS CK 1 LS CK 0 16 198 01 page37 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 3 4 Clock system register CLKCR3 Clock Base Address 0x0C 0 4030 31 24 23 21 20 19 16 __ IOCKS RW 0 71 4 B 20 ADCKP ENACD ADCD ENSD SPCD Bit Name Description GPIO input clock source selection Bit20 IOCKS 0 HS CK 1 LS CK GPIO clock frequency divider configuration 0000 Disable 0001 GPIO clock source 1 0010 GPIO clock source 2 0011 GPIO clock source 4 0100 GPIO clock source 8 0101 GPIO clock source 16 0110 GPIO clock source 32 Bit 19 16 0111 GPIO clock source 64 1000 GPIO clock source 128 1001 GPIO clock source 256 1010 GPIO clock source 512 1011 GPIO clock source 1024 1100 GPIO clock source 2048 1101 GPIO clock source 4096
137. HY16F198 VO1 TC www hycontek com page213 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 4 and DAC should be selected together HYGON HYCON TECHNOLOGY 256 stage DAC outputs can be measured at the output end of the AlO4 via proper DAC network setting Or adopt the DAC dedicated analog voltage output pin PT3 1 24 6 Model program description 01 include HY16F19X h 02 inti 03 lint main void 04 05 DrvPMU VDDA 100 Ctrl E LDO ON 06 DrvPMU VDDA Voltage E VDDA3 0 INDDA 3 0 08 DrvOP DAC PVDD3V output with AlO4 PIN29 09 DrvDAC Enable DAC IP enable 10 DrvDAC EnableOutput IDAC output enable 11 DrvDAC Open 1 0 0x10 12 DrvDAC SetoutputlO 1 output with PT3 1 13 while 1 Iwhile loop 2014 HYCON Technology Corp www hycontek com 0 16 198 01 214 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 24 7 DAC application circuit 1 Use DAO Output DAPS 1 0 DABIT lt 7 0 gt DA_Vrefp DA_Vrefn 24 8 DAC application circuit Il Use as Programmable Gain Amplifier OPPS 3 0 0010 DAPS 1 0 ENDA 1 Vin Signal Input DA Vrefp DANS lt 1 0 gt OPOC
138. HYGON HY16F19 Series User manual High Precision Mixed Signal Micro Controller 4x36 6x34 LCD Driver 32 bit Low Power Micro Controller 21 bit ENOB ZAADC 64Kb Flash ROM 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Table of Contents 1 CHIP OVERVIEW 11 1 1 Brief 11 1 2 Type description table ete 13 2 FUNCTION X 14 2 1 Block Gla Gram nist 14 2 2 CPU Core block diagratm ioc S 15 3 MEMORY STRUCTURE M 16 3 1 Memory descr ptlomers icici 16 3 2 Memory 17 3 3 Static random access memory 19 3 4 Eze 19 3 5 Cres 19 3 6 Boot ROM EP WO 19 3 7 Embedded debug module EDM 21 4 SOC E 22 4 1 Overall 22 4 2 5 22 4
139. IO Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 80 0 40880 MASK1 PT91CFG MASKO PT90CFG GPIO Base Address 0x84 0x40884 MASK3 PT93CFG MASK2 PT92CFG GPIO Base Address 0x88 0x40888 MASKS PT95CFG PT94CFG GPIO Base Address 0x8C 0x4088C PT97CFG MASK6 PT96CFG LCD Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0x80 0x40880 MASK1 SEG27 SEG26 GPIO Base Address 0x84 0x40884 MASK3 SEG29 MASK2 SEG28 GPIO Base Address 0x88 0x40888 MASKS SEG31 MASK4 SEG30 GPIO Base Address 0x8C 0x4088C MASK7 SEG33 MASK6 SEG32 LCD Register Address 0x41B04 can determine the setting is the GPIO Mode or the LCD Mode 19 3 Register function 19 3 1 9 0 9 1 register When GPIO Mode GPIO Base Address 0x80 0x40880 Mame Mask PTOIOEPTOWIE 16081 T HIT LB IG Bit Description 9 1 Output Enable Bit 19 PTOIOE 0 Disable 1 Enable PT9 1 Input Enable Bit 18 0 Disable 1 Enable PT9 1 Output Data Bi17 9100 0 Output Low 1 Output High Bi 16 PT91DI PT9 1 Input Data 0 Input Low _ 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com 155 16 19 series user manual HYGON
140. IO port will be disabled Whether the current input mode of the corresponding IO pin is 0 or 1 can be read the controller PT8xDI 0 If the IO is set as the input mode and the chip should be connected to the external pull up resistor and 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page143 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially the low power mode it is suggested the IO pin should be set as the input mode f it serves as the analog signal input port it is not necessary to set the corresponding IO pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled LCD mode The controller SEGx 5 0 determines the output data of the LCD SEGMENT If the LCD is under the 1 6 duty mode the SEGx 5 0 can determine the data content of the 1 6 duty data content if the LCD is under the 1 5 duty mode the SEGx 4 0 can determine the 1 5 duty data content if the LCD is under the 1 4 duty mode the SEGx 3 0 can determine the 1 4 duty data content if the LCD is under the 1 3 duty mode the SEGx 2 0 can determine the 1 3 duty data content 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page144 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash
141. Input low potential 1 Input high potential 14 3 4 PT2 register PT2CR3 RW RW 0 RW w Bt 5 11412 11 9 8 6 211 RW 0 Bit Description PT2 interrupt condition flag When ITT 0 Always 0 1 Inverse 2 Same as Bit 31 24 PT2IDF 3 Same as S1 4 Same 5 Inverse DI 6 Same as DI 7 Inverse DI Bit 23 00 PT2 ITT Port 2 2 select the interrupt trigger method 000 Disable the GPIO interrupt trigger to not reply to the interrupt 001 Rising edge trigger 010 Falling edge trigger 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com 117 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 16 19 series user manual HYGON 2014 HYCON Technology Corp www hycontek com 011 100 101 110 TH Potential change trigger Low potential trigger High potential trigger Low potential trigger High potential trigger 0 16 198 01 page118 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 15 GPIO PT3 MANAGEMENT 15 1 Overall description The has 8 IO pins be used as common universal IO ports or reused as the input or output IO ports of many function modules such as OP amplifier DAC and ADC converters etc Different reuses need different configurations
142. L OxFFFF means the TimerB IP settings including the Mode selection the Timer B enablement and the Timer B counter counting settings The HYCON C Library DrvTIMER Enablelnt E TMB means enabling the Timer B interrupt The HYCON C Library DrvTIMER ClearlntFlag E means clearing the TimerB interrupt flag The Timer A B C and WDT belong to the HW1 interrupt and the format is void HW1 16 fex xpi D The program starts Initialization settings Timer B settings Wait for interrupt Interrupt the subprogram Clear the interrupt flag Reverse the Return to the main program 10 5 Model program function 2014 HYCON Technology Corp UG HY16F198 V01_TC www hycontek com page92 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash Use the TimerB interrupt Each TimerB interrupt will reverse the IO Ex it is 0x5 before the interrupt it will become OxA after the interrupt 2014 HYCON Technology Corp www hycontek com HYGZh HYCON TECHNOLOGY 0 16 198 01 page93 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash 10 6 Model program description HYCON TECHNOLOGY 00 01 include HY16F19X h 02 03 junsigned int i 04
143. N 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY different counting methods TBRST is the control bit of the TMB counter register If the bit is set as lt 1 gt the counter register will be automatically cleared and then the bit will automatically become 0 Operating configuration when TMB serves as timer counter Set the operating clock source of the TMB and set the control bits 0 40308 6 and 0x40308 5 4 TMCD Select the counting mode and set the control bit TBM 1 0 Select the counting trigger signal source and set the TBEBS 1 0 as a timer it can be set as 00b which means it is always enabled and continuously perform counting Set the timer counter overflow value is TBCO 15 0 Set the control bit TBRST as lt 1 gt to clear the counting register Enable the TMB and the control bit TBEN is set as lt 1 gt The calculation of the theoretical overflow value of the Timer B T TBCO 1 TBCLK TBCLK HS CK or LS CK TMCD Equation 10 1 then T TBCO TMCD HS CK orLS CK Equation 10 2 www hycontek com page70 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY The TMB has four different counting methods and different counting method have different overflow conditions which will be specified later TMB counting method 0 When TBM 1 0 00 the TBR serves as a 16 bit up counter Under the mode the TBR will be automatically a
144. N 1 and N outputs which is to generate a waveform using 16 output periods as one set where 7 of them output N and then the other 9 output N 1 Set the TBC2 7 0 as 11h 1 2 1 32 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 32 output periods as one set where 15 of them output N and then the other 17 output N 1 Set the TBC2 7 0 as 21h 1 2 1 64 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 64 output periods as one set where 31 of them output N and then the other 33 output N 1 Set the TBC2 7 0 as 41h 1 2 1 128 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 128 output periods as one set where 63 of them output N and then the other 67 output N 1 2014 HYCON Technology Corp UG HY16F198 V01_TC www hycontek com page83 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Set the TBC2 7 0 as 81h 1 2 1 256 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 256 output periods as one set where 127 of them output N and then the other 129 output N 1 Set the TBC2 7 0 as 07h 1 2 1 4 1 8 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform us
145. N Technology Corp www hycontek com UG HY16F198 VO1 TC page272 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page273 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Subprogram 00 01 void I2C INI void 12C Initial 02 03 DrvGPIO Open E PT1 0x06 E IO INPUT IIPT1 1 input 04 DrvGPIO Open E PT1 0xf6 E IO PullHigh 05 06 07 08 pio 44 0 09 i2c 00 0xFFOOFFO0 1 0 41000 12 OFF 11 i2c 14 0 0000 0 44014 12 13 14 15 void I2C Start void I2C Start 16 17 DrvI2C 1 0 0 0 1000 18 2 NOP 19 20 21 void 2 Stop void Hardware I2C Stop 22 23 Drvl2C_Ctrl 0 1 0 0 ISPIA 0100 24 I2C_NOP 25 26 27 void I2C_Write unsigned int I2C Data Hardware 12C Write 28 29 Drvl2C_WriteData I2C_Data 30 12 04 0 01 10x41004 31 I2C_NOP 32 33 34 void 12 NACK void I2C 35 36 2 ClearlRQ 37 Drvl2C_ClearEIRQ 38 while i2c 04 amp 0 00000002 39 40 41 void 12 NOP void
146. Normal 4 Frame check error Rx Parity check error 20 PEr 0 Normal 1 Parity check error Tx Busy flag Bit 19 TxBusy O 1 Busy 2014 HYCON Technology Corp www hycontek com RW 0 0 16 198 01 249 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash Tx Buffer Full flag Bit 18 TxBF 0 Empty 1 Full Rx Busy flag Bit 17 RxBusy 0 Idle 1 Busy Rx Buffer Full flag Bit 16 0 Empty HYGON HYCON TECHNOLOGY 1 Full Tx stop length control 0 0 5Bit Bit 6 1 1Bit 2 1 5Bit 3 2Bit data length Normal Mode Parity Check Mode Breed D 6 Bit Mode 5 Bit Mode 1 7 Bit Mode 6 Bit Mode 2 8 Bit Mode 7 Bit Mode 3 9Bit Mode 8 Bit Mode Rx interrupt method selection Send out the interrupt when the Rx Data Buffer has data Bit 3 RxIT 0 and the interrupt disappears after the data read 1 Send out the interrupt after one piece of data is received by the Rx UART Rx control switch Bit 2 RxEn 0 Disable 1 Enable Tx interrupt method selection Send out the interrupt when the Tx Data Buffer is idle Bit 1 TxIT 0 the interrupt disappears after the data written in 1 Sent out the interrupt after one piece of data is transmitted by the Tx UART Tx control switch Bit 0 Disable 1 Enable 2014 HYCON Technology Corp www hycontek com 0 16 198 01 250
147. OLOGY Attention 1 HYCON Technology Corp reserves the right to change the content of this datasheet without further notice For most up to date information please constantly visit our website http www hycontek com HYCON Technology Corp is not responsible for problems caused by figures or application circuits narrated herein whose related industrial properties belong to third parties Specifications of any HYCON Technology Corp products detailed or contained herein stipulate the performance characteristics and functions of the specified products in the independent state We does not guarantee of the performance characteristics and functions of the specified products as placed in the customer s products or equipment Constant and sufficient verification and evaluation is highly advised Please note the operating conditions of input voltage output voltage and load current and ensure the IC internal power consumption does not exceed that of package tolerance HYCON Technology Corp assumes no responsibility for equipment failures that resulted from using products at values that exceed even momentarily rated values listed in products specifications of HYCON products specified herein Notwithstanding this product has built in ESD protection circuit please do not exert excessive static electricity to protection circuit Products specified or contained herein cannot be employed in applications which require extremely high levels of r
148. ON Technology Corp 0 16 198 01 www hycontek com page109 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash neste GPIO Base Address 0x08 0x40808 RW 15 8 m l6 5 m B 2 m 0 Name PTIDI7PT1DI6PT1DI5PT1DI4PT1DI3 PT1DIZIPT1DIT PT1DIO RW Bit Name Description Port1 PAD input status value Bit 7 0 PT1DI 0 input low potential 1 input high potential 13 3 4 PT1 register PT1CR3 RW 0 RW 15 14 12 11 9 86 2 0 15 PT14ITT PT12ITT PTT11ITT PT10ITT 0 Bit Name Description PT1 interrupt condition flag when Always 0 Inverse DI Same as DI Same as 51 Same as DI Inverse DI Same as DI Inverse DI Bit 23 00 PT1 ITT Port 1 select the interrupt trigger method 000 Disable the GPIO interrupt trigger to not reply to the interrupt 001 Rising edge trigger 010 Falling edge trigger 011 Potential change trigger 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page110 Bit 31 24 PT1IDF 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 100 Low potential trigger 101 High potential trigger 110 Low potential trigger 111 High potential trigger 13 4 Model program flow
149. R 7 0 sawtooth wave type counting method the two counters will increase to the maximums TBCO 15 8 and TBCO 7 0 at the same time on the basis that the step is 1 2 8 Bit up counters TBR 15 8 and TBR 7 0 sawtooth wave type counting method with step being 1 after the counter 11 TBR 7 0 increases and then overflows the counter TBR 15 8 is automatically added by 1 and then the TBR 7 0 restarts the counting from 0 Timer B2 counting trigger mode selection Bit 3 2 TB2M 10 00 1 Always enable continuous counting method CMPO trigger the multi function comparator to output high Bit 1 0 2 5 01 potential 10 OPOD trigger the OP amplifier to output high potential CPI1 trigger the output of the Timer C CPI1 to output high 11 potential 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page96 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 11 2 2 Timer B2 register TMB2CR1 Base Address 0x28 0x40C28 TMB2CR1 TMB Control Register 1 6 PWMF PWME PWMC PWMB PWMA PRW i Name Bit Name Description PWM A B C D F operating mode status flag Bit 21 16 PWM Flag 0 Normal 1 Enable Bit 15 0 TMBC Timer B2 16 bit counting value 11 2 3 Timer B2 register TMB2COD Base Address 0x2C 0x40C2C TMB2COD TMB Counter overflow condition Register 31 16 Na
150. SI 100 Port8 0 CS Port8 1 CK Port8 2 MISO Port8 3 MOSI 101 Port8 4 CS Port8 5 CK Port8 6 MISO Port8 7 MOSI 110 Port9 0 CS Port9 1 CK Port9 2 MISO Port9 3 MOSI 111 Port9 4 CS Port9 5 Port9 6 MISO Port9 7 MOSI SPI communication reuse function enable control 0 Disable only used as a common IO port PTSPE 08 xu Enable The IO port is reused as the SPI communication port 1 and the communication IO port is set by the SPPTS Bit 3 1 PTUR UART communication IO port selection 000 Port 1 0 Port 1 1 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page174 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 001 Port 1 4 TX Port 1 5 RX 010 Port 2 0 TX Port 2 1 RX 011 Port 2 4 TX Port 2 5 RX 100 Port 8 0 TX Port 8 1 RX 101 Port 8 4 TX Port 8 5 RX 110 Port 9 0 TX Port 9 0 RX 111 Port 9 4 TX Port 9 5 RX EURAT communication reuse function enable control PTURE 0 Disable only used is a common IO port Enable The IO port is reused the EUART communication 1 port and the communication IO port is set by the PTUR MISO Master input mode Slave output mode MOSI Master output mode Slave input mode 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page175 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash H
151. SS 0 1 UV TCR1 15 0 TCI2 0414 EN CPI2P A MN 205 232 E CP1PS 3 0 Divider CP1PS 3 0 CPI1 Divider 0000 CPI1 1 1000 CPI1 256 0001 CPI1 2 1001 11 512 0010 4 1010 1024 0011 1 8 1011 CPI1 2048 0100 1 16 1100 CPI1 4096 0101 1 32 1101 CPI1 8192 0110 1 64 1110 11 16384 0111 28 Fig 12 1 TC function block diagram 2014 HYCON Technology Corp UG HY16F1 98 01 www hycontek com page99 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash clock source The clock source of the TMC is equal to that of the TMB all of them are generate by make the 5 CK or LS CK pass the frequency divider to generate the clock source TMBCLK The capture function of the TMC can be enabled or disabled by setting the control bit TCEN O TMC capture counting value The capture counting value of the TMC is finished by the counter TBR of the TMB When the TMC captures the first trigger edge of the input signal the TBR will start the counting when the TMC captures the second trigger edge of the input signal the TBR will stop the counting After the capture event is finished the hardware will automatically write the value of the TBR into the TMCR1 or TMCR2 and generate the interrupt flags TMC1IF and TMC2IF The user can read the values of the TCR1 TCR2 by program
152. TBR 15 0 lt TBC2 15 0 PWM 0 when TBR 15 0 TBC2 15 0 or TBR 15 0 lt TBC1 15 0 PWM 1 the time is t tclock x TBC2 1 PWM period PWM Period TBR 15 0 TMCD HS CK or LS CK PWM duty cycle PWM Duty TBC2 TBC1 TBR 15 0 1 PWM Duty Cycle PWM Duty TMCD HS CK or 18 CK TBC2 15 0 TBC1 15 0 FIG 10 10 Waveform schematic view and counting waveform schematic view of PWM mode F 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU 8 64 KB Flash PWMG mode The PWNG is a 16 bit PWM mode and the duty cycle of the output waveform is 5096 which is the PFD waveform counting value of the is not compared with the TBC1 TBC2 and the period of the output waveform is related to the TBCO PWM period PWM Period TBCO 15 0 TMCD HS CK or LS Ck FIG 10 11 Waveform schematic view and counting waveform schematic view of PWM mode G 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page88 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 10 2 Register address TMB Register Address 31 24 23 16 15 8 7 0 Base Address 0 04 0 40 04 MASK1 REG1 MASKO REGO Base Address 0 08 0 40 08 REG2 TBCR TBCR B
153. TC www hycontek com page227 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU 8 64 KB Flash 26 SERIAL PERIPHERAL INTERFACE SPI 26 1 Overall description The HY16F19X has a serial peripheral interface SPI The SPI uses the synchronous serial data communication protocol and works under the full duplex mode It communicates with the 4 wire bidirectional interface and can work under the master slave mode Under the master mode it has several configurations to execute different client devices Functions Full duplex synchronous transmission Support master mode operation or slave mode operation Support transmitting MSB first or transmitting LSB first The transmission frame is 4 32 bit and can provide programmable bit length setting High speed SPI bus busy status flag Programmable clock pulse rate Support high low potential slave end selection Programmable clock polarity and phase Master Slave MSBit LSBit MSBit LSBit shift register m shift register Read Write Buffer Buffer SPI Clock SCKx SCK SPI Controller FIG 26 1 Serial communication SPI structure diagram SPI Controller CSx CS 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page228 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash MISO pins the
154. Workable 4MHZ 1 01B 0 Stop Workable HAO 10MHZ 1 10B 0 Stop Workable 16MHZ 1 11B 0 Stop Workable Start after the chip is 4 35KHZ CKLS 0 Stop Oscillate power on Table 6 2 Internal crystal oscillator configuration www hycontek com page32 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 1 3 CPU and external peripheral operating frequency sources configuration Both of the external and internal crystal oscillators can provide the frequency sources for the CPU and the frequency sources will be provided for the CPU after passing the frequency dividers The chip can determine the frequency source of the CPU is the HS CKorLS CK via the frequency selector MCUCKS 1 and perform the frequency division via the frequency divider ENMCD 1 Thus there are multiple operating frequency modes for the CPU to select from to determine the instruction cycle of the chip Similarly the external peripheral operating frequency sources are also provided by the external internal crystal oscillators and the HS CK or LS CK passing the frequency dividers or the frequency sources can be directly provided by the crystal oscillators such as the WDT As the external peripheral operating frequency configuration may vary with the different operations please refer to the following figure for more information HSXT Enable ENOHS CKHS 0 2 20MHz HSXT HS ENHAO 0 HER d HAO 1
155. X UJ mt Bit Name Description PWM A B C D F operating mode status flag Bit 21 16 PWM FlagQ Normal 1 Enable Bit 15 0 TMBC Timer 16 bit counting value 10 3 3 Timer B register TMBCOD Base Address 0 0 0x40COC TMBCOD TMB Counter overflow condition Register 31 16 15 0 TBCO Timer B Overflow Condition RW OxFFFF o z 9 Bit Name Description Bit 15 0 TBCO Timer B counter overflow threshold value 10 3 4 Timer B register PWMDOD Base Address 0x10 0x40C10 PWMDOD PWM counter overflow condition Control Register 31 16 TBC2 PWM 1 duty cycle counter overflow value RW FFFFh 15 0 TBC1 PWMO duty cycle counter overflow value 2 O RW FFFFh 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page91 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash Name Description Bit 31 16 TBC2 1 duty cycle counter overflow value Bit 15 0 TBC1 duty cycle counter overflow value 10 4 Model program flow The HYCON C Library is adopted the DrvTMBC Source X Y can select the clock source of the Timer B X can select the high speed or low speed 0 is HS CK Y is the frequency dividing selection if Y 3 it means the Timer B IP clock and the frequency dividing is 8 The function DrvTMB Open E MODEO E NORMA
156. YGON HYCON TECHNOLOGY 21 3 3 GPIO reuse function control register GPIOMCR4 GPIOMCR5 GPIO Base Address 0x48 0x40848 RW RWO RW0 Bit Name Description TCI 3 mode control Bit 5 PTCISE 0 The is the same with the TC1 1 The TCIS configuration is set by the PTCTC PWM communication IO port selection 0 Port 1 2 2 Port 1 3 ZPWM3 1 Port 1 6 ZPWM2 Port 1 7 ZPWM3 2 Port 2 2 2 Port 2 3 PWM3 Bit4 2 PTPW2 3 Port 2 6 2 Port 2 7 PWM3 4 Port 8 2 2 Port 8 3 PWM3 5 8 6 2 Port 8 7 PWM3 6 Port 9 2 2 Port 9 3 ZPWM3 7 Port 9 6 2 Port 9 7 PWM3 GPIO PWMS control switch Bit 1 PTPW3E 0 Disable 1 Enable GPIO PWM control switch PTPW2E 0 Disable 1 Enable 2014 HYCON Technology Corp www hycontek com 0 16 198 01 176 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 21 3 4 GPIO reuse function control register GPIOMCR6 GPIOMCR7 GPIO Base Address 0 4 0x4084C RW 15 08 7 4 3 1 MES UN MASK Q PTUR2 PTUR2E 0 RW RWO RW Bit Name Description UART2 communication port selection 0 Port 1 2 Tx2 Port 1 3 Rx2 1 Port 1 6 Tx2 Port 1 7 Rx2 2 Port 2 2 Tx2 Port 2 3 Rx2 Bit3
157. a Acknowledge signal Data reception Slave starts right after the initial 8 bits Transmitting data to the device Host is to send a low potential which means the data are received STOP signal Under the master mode the SCL is high potential The SDA sent from low potential to high potential to end the data transmission START condition ADDRESS R W ACK DATA ACK DATA ACK STOP condition FIG 29 3 12C bus clock diagram 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page257 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash Data transmission rate calculation The 2 internal register CRG 7 0 can control the data transmission rate of the master mode The CRG 7 0 value of the internal counter generates a master mode via the signals of the SCL pin such that the data transmission rate can be based on the frequency of the I2C clock source 2 CK The data transmission of the SCL pin of the I2C bus is clock signal which is determined by the CRG of the clock source frequency I2CLK of the I2C circuit according to the clock rate of the SCI pin and the following equation Data Baud Rate 12 1 4X CRG 1 Equation 29 1 Timing function Time Out Timing function is to prevent the 2 controller from locking the 2 communication bus when the 2 works in order to provide enough time to de
158. abled Whether current input mode of the corresponding pin is 0 or 1 can be read the controller PT10xDI 0 If the IO is set as the input mode and the chip should be connected to the external pull up resistor and the IO pin is not allowed to be floating in order to prevent from the electric leakage of the 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page163 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash chip Especially the low power mode it is suggested the IO pin should be set as the input mode If it serves as the analog signal input port it is not necessary to set the corresponding pin as the input mode output mode of the IO pin should be disabled before its input mode is enabled LCD mode The controller SEGx 5 0 determines the output data of the LCD SEGMENT If the LCD is under the 1 6 duty mode the SEGx 5 0 can determine the data content of the 1 6 duty data content if the LCD is under the 1 5 duty mode the SEGx 4 0 can determine the 1 5 duty data content if the LCD is under the 1 4 duty mode the SEGx 3 0 can determine the 1 4 duty data content if the LCD is under the 1 3 duty mode the SEGx 2 0 determine the 1 3 duty data content but the SEGO only supports the 1 3 duty and 1 4duty and the SEG1 supports the 1 3 duty 1 4 duty and 1 5duty 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com pa
159. al with the MCU I2C controller Therefore the response of the I2C controller to each bit will occur only after the SCL is reduced to low potential at this time the master end cannot receive the next clock signal in other word a clock stretching takes place However when the MCU is too busy or cannot reply to he I2C controller for other reasons the I2C communication bus be locked under the low potential In order to prevent from the above situation the time out controller will determine whether the SCL status is under low potential time out according to the frequency divider DI2C 2 0 and time condition controller I2CTLT 3 0 The condition treatment has the following states When the machine detects the SCL is drawn to the low potential and conforms to the condition the SCL I2C controller will be forced to let go and send an interrupt event to the CPU When the SCL fails to conform to the time out condition and under high potential the internal counter of the time out controller will be reset and the next SCL is drawn to low potential to restart the counting 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page258 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 2 communication pin 2 bus only has two wires but the chip allocates 8 sets of communication IO pins for the I2C module Each set of IO pins includes SCL SDA whi
160. as Capture 2 23 input source selection 24 25 DrvTIMER ClearlntFlag E TMCO Clear TMCO interrupt flag 26 DrvTIMER ClearlntFlag E TMC1 Clear TMC1 interrupt flag 27 28 DrvTIMER Enablelnt E TMCO 0 interrupt enable 29 DrvTIMER Enablelnt E 1 1 interrupt enable 30 31 SYS EnableGIE 7 Enable GIE 32 33 while 1 for Interrupt 34 37 38 HW1 ISR void 39 40 DrvTIMER ClearlntFlag E TMCO Clear TMCO interrupt flag 41 DrvTIMER ClearlntFlag E TMC1 Clear TMC1 interrupt flag 42 izi OxF Ifi OxF 43 DrvGPIO SetPortBits E PT2 i PT2 Output i 0x0A 0x05 44 45 2014 HYCON Technology Corp 0 16 198 01 www hycontek com page105 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 13 GPIO PT1 MANAGEMENT 13 1 Overall description The PT1 has 8 IO pins which can be used as the common universal IO ports and can also be reused as the input or output IO ports of the capture comparator SPI comparator PWM and external interrupt modules etc Different reuses need different configurations VDD3V VDD3V PT1PU AlOX PAD PT1DI et gut PT1IE IOIP A I PT1DO FIG 13 1 PT1 function block diagram PT1 has the functions of the input output internal pull up resistors and the external interrupt input port and different functions should
161. ase Address 0 0 0 40 0 TBCO TBCO Base Address 0x10 0x40C 10 TBC2 TBC2 TBC1 TBC1 Reserved 10 3 Register function 10 3 1 Timer B register TMBCRO Base Address 0x04 0 40 04 TMBCRO TMB Control Register 0 31 24 23 22 20 18 16 MASK O1PMR O1MD w 0 15 8 Reg TBEN T TBEBS ROW 0 NM Bit Name Description 1 waveform output phase control Bit 23 OTPMR 0 Inverted output 1 Normal output 1 operating mode selection 000 PWMA 001 PWMB 010 PWMC Bit 21 20 O1MD 011 PWMD 100 PWME 101 PWMF 110 PWMG 111 PWMG PWMO waveform output phase control Bit 19 OOPMR 0 Inverted output 1 Normal output Bit 18 16 PWMO operating mode selection 000 PWMA 001 PWMB 2014 HYCON Technology Corp 0 16 198 01 www hycontek com page89 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 010 PWMC 011 100 PWME 101 110 PWMG 111 Timer enablement control Bit 5 TBEN 0 Disable 1 Enable Timer B reset 0 N Bi 4 TBRST al _ Clear the counting register TBR of the Timer B it will be 1 automatically set as 0 after finished Timer B counting mode selection 16 bit up counter sawtooth wave type counting method the 00 counting will increase to the maximum T
162. atform The chip has the circuit simulation function and provides a good environment for troubleshooting The chip can work in 2 2V to 3 6V and 40 C to 85 www hycontek com page12 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU 8 64 KB Flash HYCON TECHNOLOGY 1 2 Type description table The bit type description table of the register 3 Description Initial value No Use RSV Reserve X Unknown Write R Read RO Only Read 0 R1 Only Read 1 WO Only Write 0 W1 Only Write 0 RW 0 Read Write Initial O RW 1 Read Write Initial 1 0 Read 0 Write Initial O R1W 1 Read 1 Write Initial 1 R X Read Initial 1 or O Unknown TOZOTEHYCON Technology Cop 9m HY EIB TO www hycontek com page13 HY16F19 series user manual 21 bit ENOB AADC 32 bit MCU 64 KB Flash 2 FUNCTION OVERVIEW 2 1 Block diagram HYG N HYCON TECHNOLOGY E UART 2 32 bit SPI 2 2 Clock System TimerB2 4ch PWM 2KB 8KB Debug SRAM Module N8 32 bit MCU 16KB 64KB Power Flash Management Reset Control Rail to Rail Wet Pod Bandgap OPAMP Low Noise Analog PGA 4 36 LCD Controller 8 bit DAC Charge Pump FIG 2 1 Chip function structure diagram 2014 HYCON Technology Corp www hycontek com 0
163. be set by different controllers Internal pull up resistor The controller PT1PU 7 0 can enable or disable the internal pull up resistor of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the internal 75k pull up resistor will be enabled if it is set as 0 the internal 75k pull up resistor will be disabled If the IO port is under the input mode and there is no external pull up resistor the internal pull up resistor should be enabled especially in low power consumption mode which can prevent from electric leakage and increase the power consumption If it serves as the analog signal input port it is not necessary to enable the internal pull up resistor Output mode The controller PT1OE 7 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT1DO 7 0 can 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page106 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash determine whether the output status the pin of the corresponding IO port is 1 or 0 Under the low power mode if the IO should enable the outp
164. becomes 0 after the counter register is cleared the control bit TACLR will automatically become 0 After the TMA overflows the interrupt request will be generated and the TMA interrupt flag will be set as lt 1 gt if the TMA interrupt function is enabled and the global interrupt control bit is set as the chip will enter the TMA interrupt service event in response to the TMA interrupt request The TMA interrupt request can be cancelled by clearing the TMA interrupt flag in this way the chip will not reply the TMA interrupt Under the IDEL mode the TMA interrupt can be used to wake up the chip Under the SLEEP mode the TMA interrupt is not available The TMA has a 16 stage frequency dividing configuration which allows the TMA to have a wide counting range the calculation of the overflow value of the TMA is as follows TAR 15 0 1 TACK 32 TAS 3 0 Equation 9 1 The TACK is the input clock source of the TMA and the TAS 3 0 is the frequency dividing value Assuming the TMA selects the LS CK and the LS CK is from the LPO then TACK 35KHZ TAS 3 0 1001B 1024 and the theoretical value of the overflow value of the Timer A 35000 2 32 1 5 1024 35000 2 32 1024 1 068 2 www hycontek com page62 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY ENTA O 9 TMAR STOP Sleep TACLR O TAS 3 0 TMA Overflow TMAIF
165. bit MCU amp 64 KB Flash TECHNOLOGY 0 Disable no output for the IO port 1 Enable the output port is set by the PTPW 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page173 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 21 3 2 GPIO reuse function control register GPIOMCR2 GPIOMCR3 GPIOMCR2 GPIOMCR3 GPIO Multiplex Control Register 1 Bit 3124 2320 197 nea _ 7 I2CPTS I2CPTEn RW ROWO Name RW Bt 1550 r5 4 BI RW RW ROW 0 RW Bit Name Description 2 communication IO port selection 000 Port 1 0 SCL Port 1 1 SDA 001 Port 1 2 SCL Port 1 3 SDA 010 Port 1 4 SCL Port 1 5 SDA Bit 19 17 I2CPTS 011 Port 1 6 SCL Port 1 7 SDA 100 Port 2 0 SCL Port 2 1 SDA 101 Port 2 2 SCL Port 2 3 SDA 110 Port 2 4 SCL Port 2 5 SDA 111 Port 2 6 SCL Port 2 7 SDA 2 communication IO port reuse function enable control Bil16 I2CPTEn 0 Disable no signal Enable the IO port is reused as the 2 communication port 1 and the IO port is set by the I2CPTS SPI communication IO port selection 000 Port1 0 CS Port1 1 Port1 2 MISO Port1 3 MOSI 001 Port1 4 CS Port1 5 CK Port1 6 MISO Port1 7 MOSI 010 Port2 0 CS Port2 1 CK Port2 2 MISO Port2 3 MOSI Bit 7 5 PTCSP 011 Port2 4 CS Port2 5 Port2 6 MISO Port2 7 MO
166. ch is for the reuse functions of the IO port In this way users can conveniently select different communication pins corresponding communication pins can be selected and enabled via the controllers I2CPTS 2 0 I2CPTEN When using the functions of the 12C the communication IO pins should be enabled and the corresponding IO pin should be set under the input mode or output mode The following table is the communication pin distribution table I2CPTS 2 0 12 SCL SDA I2CPTS 2 0 12 SCL SDA 000 1 PT1 0 PT1 1 100 1 PT2 0 2 1 001 1 1 2 1 3 101 1 2 2 2 3 010 1 1 4 1 5 110 1 2 4 2 5 011 1 PT1 6 PT1 7 111 1 2 6 27 Table 29 1 12 communication IO pin distribution 29 2 1 Communication 12C interface flow I2C serial interface terms SPIA It means giving instructions to the Action control register where S is the Start instruction and P is the Stop instruction is the interrupt flag and is the Acknowledge instruction SPIA It means reading the value of the Action control register which can be used to determine the interrupt flag or other instructions are finished or not STA It means reading the value of the Status register which is used to show the current operating status of the I2C circuit The following flow chart will respectively express the statuses of the I2C interface by circular frame with gray background
167. channel selector of the OPAMP is not a multiplexer but an independent selection switch The positive input channel of the OPAMP is controlled by 7 switches AIO 2 4 DAO REFO 5 AlO6 and AIO7 which can be respectively controlled by the control bits OPPS 0 OPPS 1 OPPS 2 OPPS 3 OPPS 4 OPPS 5 and OPPS 6 besides multiple positive input channels can be selected at the same time The negative input channel of the OPAMP is controlled by 8 switches AIO3 AIO5 DAO OPOI OPO AIO2 and AlO8 which be respectively controlled by the control bits 0 OPNS 1 OPNS 2 OPNS 3 OPNS 4 OPNS 5 OPNS 6 and OPNS 7 similarly multiple negative input channels can be selected at the same time AIO2 gt orrsi 7 AIO3 OPNSIO AIOA 1 AIO5 OPNS 1 DAO 92787 DAD 22 92881 7 978 24 p 6 OPPS 5 515 gt 107 OPPSI6 AIO2 OPNSIS OPNSI 7 FIG 23 2 Input channel configuration diagram 23 1 2 Built in 10pF capacitor The OPAMP has a built in 10uF capacitor which can have different functions under different configurations upper end of the capacitor is connected to the OPOC and can be connected to the negative input end the switch is set by the control bit OPNS 6 the lower end of the capacitor can be connected to the OPOI or VSS which can be set by
168. circuit switch closes The digital output phase control of the comparator Bit 3 0 Normal output 1 Inversed output The output low pass filer enable control of the comparator Disable the output of the comparator does not pass through Bit 2 CPDF 0 the 2us low pass filter Enable the output of the comparator passes through 1 the 2us low pass filter The high speed mode enable control of the comparator Bit 1 CMPHS 0 Low power mode 2014 HYCON Technology Corp www hycontek com 1 High speed mode 0 16 198 01 221 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash Aaa Comparator function enable control ENCMP 0 Disable the output status is O 1 Enable 25 3 2 CMP register 1 Bit Name RW MASK CPPS RW ROWO RWO Bit Name Description The CPDA 3 outputs hystersis enable control and the value of the CPDAJ3 is controlled by the CMPO and keep consistent 0 Disable 1 Enable CPDA 3 CMPO CPDA 2 outputs hystersis enable control and the value of the CPDA 2 is controlled by the CMPO and keep consistent 0 Disable 1 Enable CPDA 2 CMPO The CPDA 1 outputs hystersis enable control and the value of the CPDA 1 is controlled by the CMPO and keep consistent 0 Disable 1 Enable CPDA 1 CMPO The CPDA 0 outputs hystersis enable control and t
169. circular frame with white background and white rectangular frame Error An object cannot be established by editing the function variable code Circular frame with gray background it means the I2C status that the interrupt flag is established Circular frame with white background it means the I2C status that the interrupt flag is not established and needs to be read actively by the MCU White rectangular frame it means the instructions to the I2C should be given by the MCU 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page259 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 29 2 2 2 Master TX flow Set S to generate a START SPIA 1000 From Slave Mode C STA 90h SPIA 00106 C Status with IRQ A START has been transmitted Status without IRQ Action Slave W will be transmitted SPIA 0000 From Master Receiver B STA 84h SPIA 00105 Slave A W has been transmitted has been received STA 80h SPIA 0010b Slave A W has been transmitted NACK has been received SPIA 1000 A repeated START will be transmitted SPIA 1100 STOP followed by a START will be transmitted STA 31h SPIA 0000b A STOP has been transmitted SPIA 0000 Data byte wil
170. cycle adjuster TBC2 7 0 where is the width of the duty cycle PS N TBC1 7 0 Basictype Setthe TBC2 7 0 as 01h which makes the waveform of the PWM duty cycle generates the N 1 and outputs which is to generate a waveform using 2 output periods as one set where one outputs and then the other one outputs 1 Setthe TBC2 7 0 as 02h which makes the waveform of the PWM duty cycle generates the N 1 and outputs which is to generate waveform using 4 output periods as one set where 3 of them continuously outputs and the last one outputs N 1 Setthe TBC2 7 0 as 04h which makes the waveform of the PWM duty cycle generates the N 1 and outputs which is to generate a waveform using 8 output periods as one set where 7 of them continuously outputs and the last one outputs N 1 www hycontek com page82 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Set the TBC2 7 0 as 08h which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 16 output periods as one set where 15 of them continuously outputs N and the last one outputs N 1 Set the TBC2 7 0 as 10h which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 32 output periods as one set where 31 of them continuously outputs N and the last one outputs N 1 Set the TBC2
171. d Enable the function of the comparator Touch button application initialization Set the TMB set the operating mode of the TMB is mode 0 set the counting trigger source is CMPO set the operating clock and overflow Set the CMP operating mode to be low power or normal operating mode Select the input channel including the positive input channel negative input channel the positive input channel is RLO and the negative input channel is CH1 Set the reference voltage source and the voltage node of the multi mode resistor and the resistor short circuit switch of the resistor Enable the output function of the comparator Set whether the output passes through the low pass filter and the output is opposite in phase If the CMP comparison interrupt vector is used the interrupt function of the comparator should be enabled Enable the function of the comparator Release the charges of the touch button and the reference capacitor before charging Disable the non overlap controller first and then disable the reference voltage source of the non overlap controller and enable the resistor short circuit switch of the resistor Enable the input end short circuit switch discharge from the reference capacitor of the CH1to ground the resistor Set the corresponding IO pin of the touch button as the output mode and the output status is 0 to discharge from the touch button to ground Then enable the charging function Disconnect the input e
172. d and the corresponding IO pins should be set as the input mode or output mode The distribution of the EUART communication IO pins is as shown in the following table UART PTUR 2 0 PTURE TX RX PTUR 2 0 PTURE TX RX 000 1 1 0 1 1 100 1 PT8 0 8 1 001 1 1 4 1 5 101 1 PT8 4 8 5 010 1 2 0 PT2 1 110 1 PT9 0 PTO9 1 011 1 PT2 4 PT2 5 111 1 PT9 4 9 5 UART2 PTUR2 2 0 PTURE TX2 RX2 PTUR2 2 0 PTURE 2 RX2 000 1 PT1 2 PT1 3 100 1 PT8 2 PT8 3 001 1 PT1 6 PT1 7 101 1 PT8 6 PT8 7 010 1 2 2 2 3 110 1 9 2 9 3 011 1 2 6 2 7 111 1 9 6 9 7 Table 22 1 EUART communication IO pin distribution 2014 HYCON Technology Corp www hycontek com 0 16 198 01 244 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 27 2 Register address HYGON HYCON TECHNOLOGY UART Register Address 31 24 23 16 15 8 7 0 UART Base Address 0 00 0 40 00 Mask1 REG1 UART Base Address 0 04 0 40 04 Mask2 REG2 UART Base Address 0 08 0 40 08 Baud Rate UART Base Address 0x0C 0x40E0C Tx Rx Reserved 27 3 Register function 27 3 1 UART register 0 UART Base Address 0x00 0 40 00 Symbol UARTCRO UART Control Register O 31 24 23 22
173. d if itis set as 0 the input mode of the corresponding IO port will be disabled Whether the current input mode of the corresponding IO pin is 0 or 1 can be read the controller PT6xDI 0 If the IO is set as the input mode and the chip should be connected to the external pull up resistor and 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page123 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially the low power mode it is suggested the IO pin should be set as the input mode f it serves as the analog signal input port it is not necessary to set the corresponding IO pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled LCD mode The controller SEGx 5 0 determines the output data of the LCD SEGMENT If the LCD is under the 1 6 duty mode the SEGx 5 0 can determine the data content of the 1 6 duty data content if the LCD is under the 1 5 duty mode the SEGx 4 0 can determine the 1 5 duty data content if the LCD is under the 1 4 duty mode the SEGx 3 0 can determine the 1 4 duty data content if the LCD is under the 1 3 duty mode the SEGx 2 0 can determine the 1 3 duty data content 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page124 16 19 series user manual HYGON
174. d and managed to adjust the power consumption of the chip in order to save the energy 6 1 1 External oscillators There are two external oscillators including the high speed crystal oscillator HSXT and the low speed crystal oscillator LSXT The chip has two independent input pins for the external high speed crystal oscillator and low speed crystal oscillator thus the user can connect the two external oscillators to the chip at the same time The external oscillator should be connected to a resistor in parallel or the crystal oscillator will not work even if it is soldered at the pin besides the crystal oscillator can be connected to two 10 20pF ground capacitors and the capacitance of each capacitor is subject to the parasitic capacitor caused by the layout of the PCB The parallel resistor between the pins of the oscillator and the capacitor C2 C1 parameters of each pin of the oscillator will vary with the frequency brand of the external crystal oscillator and the layout of the PCB The following table lists suggested allocation of the R1 C1 C2 parameters and the frequency sources for your reference Instruction execution External crystal oscillator parameters status Type Symbol Frequenc R1 O C1 C2 9169p ae u q y mode mode Low speed 15 32768HZ 10M 10pF 10pF Stop Available oscillator High speed 9 HSXT 2 16MHZ 1M 10pF 10pF Stop Available oscillator 6 1 Suggest external
175. dded by 1 at each rising edge of the TBCLK if the counting value of the TBR is higher than TBCO the TBR will become 0 at the next rising edge and the timer interrupt flag TMBIF is set as lt 1 gt if the interrupt function of the TMB and the global interrupt function are enabled the chip will reply the TMB interrupt Then the TMB will restart the up counting schematic view of the counting waveform of the mode is as shown in the follow figure The counting cycle calculation method of the TMB under the mode T TBCO TMCD HS CK orLS CK 15 0 ene unl Lt Le eaten TBR 15 0 Oh TBM 00 time TBCLK TBR TBR 4 TER 0000h 000th 1 0000h 000th P ee FIG 10 2 Schematic view of counting waveform of counting method 0 www hycontek com page71 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY TMB counting method 1 When TBM 1 0 01 the TMB will perform incremental counting and then perform decremental counting the TBR is a 16 bit counter After enabled the TMB will perform incremental counting and the TBR will automatically be added 1 at each rising edge of the TBCLK When the TBR is equal to TBCO the TBR will be changed to downward mode but the interrupt flag TMBIF is still 0 at the next rising edge of the TBCLK the TBR wil
176. de selector the selector divides the 16R resistor into 16 nodes which can be set by the controllers CPDA 3 0 and CPDM 3 0 to select different resistor nodes to output different voltages to the input channel RLO of the comparator If the control bits and CPRLL are set as 1 the short circuit between the 22 5R resistor and 20R resistor can be achieved which can adjust the resistor node voltage The voltage sources of the multi node resistor are VDD18 VDD3V CP 1 and the controller CPRH 1 0 can be used to select different voltage sources to increase the output range of the node voltage 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page217 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash The hysteresis controller CPDM 3 0 is linked up with the node selector CPDA 3 0 each bit of the hysteresis controller CPDM 3 0 is corresponding the control of the enablement and disablement of the each bit of the controller CPDA 3 0 respectively When the corresponding bit of the hysteresis controller CPDM 3 0 is set as 1 the hysteresis function of the corresponding bit of the node controller CPDA 3 0 will be enabled and the status of the bit is consistent with the output status of the comparator that is CPDA X CMPO In this way the node selector will be switched between the two nodes means no change
177. divider WDTP 2 0 can determine the operating frequency and the overflow value of the WDT After the WDT overflows the WDT reset signal or interrupt event can be generated The control bit WDTNMI 1 determines the reset signal or the interrupt request signal will be generated after the WDT overflows if O is written in the bit the WDT will generate the interrupt request signal Please refer to the chapter about the interrupt control chapter for more information about the interrupt mode The WDT can start up only when the chip is in operation the WDT can start up by setting the control bit ENWDT 0 as 1 It is necessary to enable the global interrupt control bit GIE before www hycontek com page57 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY enabling the interrupt function The operating frequency source of the WDT is LPOCK therefore the calculation of the theoretical values of the operating frequency and the overflow value of the WDT is as follows WDT LPOCK 256 WDTP 2 0 Equation 8 1 LPOCK is the frequency of the internal low speed RC oscillator and WDTP is the frequency divider Assuming that LPOCK 33 9KHZ and WDTP 32768 the operating frequency of the WDT is 33900Hz 256 WDT PS 32768 0 00404Hz 8 2 Register address SoC Register Address 31 24 23 16 15 8 7 0 SoC Base Address 0x08 0x40108 WDTO1 WDTOO MASKO REGO
178. e Sleep Idle Low voltage reset or reset circuit reset can reset the Bit O3 Faipupie bit 0 Normal www hycontek com page22 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY WDT Flag Low voltage reset or external reset can clear the bit Fwr 0 1 is reset or interrupted External Reset Flag Low voltage reset BOR can clear the bit Bit 01 0 Normal 1 PT4 0 reset or ICP software reset has occurred Low Voltage Reset BOR Flag The bit will be automatically cleared after the voltage of the chip is higher than 1 8V 0 Low voltage reset has occurred www hycontek com page23 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 5 POWER MANAGEMENT 5 1 Overall description Power management module includes a charge pump regulator a wide BandGap reference a narrow BandGap reference a VDDA LDO a VDD18 LDO and a reference output buffer Chip VDD3V can work by only one voltage source between 2 2V and 3 6V The power system can be classified into three parts I O circuit analog circuit and digital circuit The power supply of the circuit is driven by VDD3V power supply of the analog circuit is driven by the internal VDDALDO Finally the power supply of the digital circuit is driven by VDD18 LDO When the MCU is under
179. e it can be wakened by the system wake up interrupt program There are two sources able to wake up the MCU the periodic timer interrupt and alert interrupt 30 2 Register address Set the RTWFEN as 1 to enable the interrupt program RTC Register Address 31 24 23 16 15 8 7 0 Base Address 0x00 0 41 00 RTKEY 1 RTCCOM RTCCO RTC Base Address 0x04 0x41A04 RTCOM RTCO RTCPTM RTPT RTC Base Address 0x08 0x41A08 RTHRM RTHR RTC Base Address 0x0C 0x41A0C RTMIM RTMI RTSEM RTSE RTC Base Address 0x00 0x41A10 RTYEM RTYE RTMOM RTMO RTC Base Address 0x04 0x41A14 RTDAM RTDA RTWDM RTWDA RTC Base Address 0x08 0x41A18 RCHR RCMI RCSE RTC Base Address 0x41A1C RCYE RCMO RCDA 2014 HYCON Technology Corp www hycontek com UG HY16F198 V01_TC page278 16 19 series user manual HYGON 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Reserved 30 3 Register function 30 3 1 Hardware RTC register RTCCRO RTC Base Address 0x00 0x41A00 Symbol RTC Control Register 0 MASK LPYF PTF TAF RW ROWO 750 RWOO RO RWO 0 Bit 1534 13 8 7 0 8 3 Pl 0 0 MASK WUEn TAEn HRF CKS RTCEn ROWO RWO Description The secret key of the RTC re
180. e byte half word or one word MCU can access one word during each clock cycle 3 4 Flash ROM HY16F198 has 64Kbyte embedded Flash ROM The initial value is from 0 90000 to Ox9FFFF User programmable codes are stored in the Flash ROM A user needs to use CPU instructions to read and write the Flash ROM if wanting to edit the program codes of the Flash ROM The user can store data at any positions between the blocks 3 5 Bus interface unit Regarding the structure of a bus the reading and writing of the register are controlled by a 32 bit advanced peripheral bus APB which can write in 32 bit data during each clock cycle In order to prevent from the existing data be covered when writing in new data the user can use the MASK function to finish the operation As described in FIG 3 3 the original data in BIT 7 0 of the register are 10101010b and the written in data are made valid via the MASK bits when 0000111101010101b are written in BIT 15 0 the result will be 0000000010100101b which means the MASK bit can only be set as 1b and the read value will be Ob when 0101b are written in BIT 7 4 but the definition of BIT 15 13 is 000b therefore it means the write values of BIT 7 4 are invalid when 0101b are written in BIT 3 0 and the definition of MASK BIT 11 8 is 1111b therefore it means the write values of BIT 3 0 can be valid Original Data Byte 1 0 1 0 1 0 1 0 Write instruction Y W
181. e device is 1 the slave device will be enabled after receiving the input 1 high potential of the CS 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page231 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash SPIOVF The SPIOVF is the overflow flag of the When any additional SCK clock edge is inputted during the transmission period it will be high potential 1 For example if the bit length of a work is 16 bits and there are 15 clock edges from the master device before the CS is changed to high potential in this case the SPICSL is 0 the SPIOVF will be 1 when receiving the 17 clock edge That means that errors occur during the transmission If the 17 clock edge has occurred it means that the data transmitted first are lost SPIABF The SPIABF is the interrupt flag of the SPI which is only used in the slave mode During the transmission when the SCK clock edge inputs are insufficient it will be high potential 1 For instance if the bit length of a word is 16 bits there are 15 clock edges from the master device and the CS is changed to high potential in this case the SPICSL is 0 the SPIABF is 1 That means errors occur during the transmission The transaction is not finished and the transmitted data are updated to the read register The transmission is stopped and lost SPIBUF The SPIBUF is the busy flag of the When the SPI i
182. e gain amplifier is 1 128 Built in temperature sensor is provided Built in 4 bit DAC is provided to adjust the offset 3 stage comb filter is provided 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page178 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash ADINP 3 0 Y DCSET 3 0 ADGN 1 0 ADCLK FRb HYGON HYCON TECHNOLOGY j 05813 01 ADGN 1 2 3 4 if 1bit Comb 32bit VISHR O 0 2 order 9 p NES Filter ADO 31 0 x VREF x 0 5 1 VRSHR 0 REFN 9101 1 0111 VRPS 1 0 gt i4 VRNS 1 0 1000 i vss 1001 A045 4 ADINN 3 0 FIG 22 1 ADC function block diagram 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page179 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 22 1 1 Fully differential signal input end The input signal of the ADC is fully differential input mode in other words the input end is composed of the positive input end and the negative input end The positive and negative signal input channels comprises 4 external signal input channels and 6 internal signal input channels When the magnifying power of the ADC is 1 the input impedance of the signal input end of the A
183. e operating clock source TMBCLK of the TMC Set the capture signal input source and the input signal source frequency dividing value which is to set the values of the CPI1S 1 0 and C1PS 3 0 Set the capture signal trigger edge which is to set the value of the If the TCI1 is selected to be the capture signal input source it is necessary to set the input to select the corresponding IO as the input mode If the interrupt function is used it is necessary to enable TMCOIE 1 and enable the global interrupt function GIE 1 Enable the TMC and enable the TCEN 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page101 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash Capture comparator 2 The capture comparator 2 has 2 capture signal input sources and the input signal source can be set by setting the selector CPI2S 0 and the input signal does not have to pass the frequency divider The setting of the controller TCPI2P can determine the trigger edge of the capture signal is the rising edge or the falling edge After the capture event is finished the interrupt signal can be generated and the interrupt flag TMC2IF is set as 17 The capture signal input of the capture comparator 2 is Input from IO port It is consistent with the input source of the capture comparator 1 Operation of the capture comparator 2 Select the operating clock source TMBCLK of the
184. e vector addresses HWO HW8 of the program memory at the next instruction cycle to execute the interrupt service program HWO HW1 51 Enable KIP HEEE Interrupt Flag HW8 CPU N8 GIE interrupt settings Interrupt enable of each IP Interrupt enable of each IP Interrupt vector FIG 7 1 Interrupt service structure diagram Detail operation description The user can set the corresponding interrupt enable bit to be 1 or clear the bit to enable or disable the corresponding interrupt function The interrupt function can be enabled by setting the corresponding interrupt enable bit to be 1 After the interrupt event takes place the interrupt flag will be generated the user can clear the flag to cancel the interrupt request It is necessary to set the global interrupt enable bit GIE 1 or any interrupt cannot be enabled The interrupt vector priority will be determined when multiple interrupt requests take place at the same time the interrupt vector with high priority should be replied first During the execution of the interrupt vector service program the high level interrupt vector www hycontek com page42 HY16F19 series user manual 21 bit ENOB 32 bit MCU amp 64 KB Flash HYG N HYCON TECHNOLOGY cannot terminate the current interrupt service
185. eed different configurations PAD PT8DI PTSIE L PT8DO U FIG 18 1 PT8 function block diagram The 8 has input and output functions and different functions should be set by different controllers Output mode The controller PT8xOE 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding IO port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT8xDO 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT8xIE 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enabled if itis set as 0 the input mode of the corresponding
186. egister ADCO 23 0 and the highest bit is the symbol bit so the relations of the conversion results and the input signals are as shown in the following table 2 polarity output 2 s complement format Equivalent ADCO 23 0 signals to be Hexadecimal _ Binary system measured system AVR 7F FF FF 0111 1111 1111 1111 1111 1111 AVR 1 2 00 00 01 0000 0000 0000 0000 0000 0001 00 00 00 0000 0000 0000 0000 0000 0000 AVR FF FF 1111 1111 1111 1111 1111 1111 AVR 80 00 00 1000 0000 0000 0000 0000 0000 Table 22 7 Relation table of ADCO 23 0 and input signals The comb filter provides the reset control function when the control bit CFRST is set as lt 0 gt the comb filter will be reset and then the comb filter will be enabled by setting the CFRST 1 In this way the ZAADC will automatically throw the first three pieces of data When the user is waiting for the interrupt taking place the first piece of the ADC conversion data which is read is the effective ADC value 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page184 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 22 1 6 Temperature sensor TPS The temperature sensor is composed of a bipolar junction transistor etc and the change of the voltage signal to the temperature has passed the 0 K curve thus it has the following features When the envir
187. egister address HYCON TECHNOLOGY 2 Register Address 31 24 23 16 15 8 7 0 2 Base Address 0x00 0 41000 MASKO 12 CONO 2 Base Address 0x04 0x41004 MASK1 12 1 MASK2 12 CON2 I2C Base Address 0x08 0x41008 MASK3 12 CON3 5 4 12 4 I2C Base Address 0x4100C MASK5 MASK6 12 12 CONG I2C Base Address 0 10 0 41010 2 I2C Base Address 0 14 0x41014 2 CON8 Reserved 29 4 Register function 29 4 1 2 register 0 2 Base Address 0x00 0x41000 ymbol I2CCRO I2C Control Register 0 Bit 31 16 Name RSV R 15 8 Ln I2CEn Row 0 RO Description General calling reset enable control Bi 2 GCRst Disable 1 Enable Time out reset function enable control Bit01 TOEn n pae 1 I2C function enable control Bit 00 I2CEn i ene 1 29 4 2 2 register 1 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page265 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash Action Register ACT I2C Base Address 0x04 0 41004 Symbol I2CCR1 I2C Control Register 1 31 24 23 22 21 20 19 18 17 16 MASK RxP Sr RW DF GC ARB RO RW ROW O 15 08 7 6
188. eliability such as device or equipment affecting the human body health medical equipments security systems or any apparatus installed in aircrafts and other vehicles Despite the fact that HYCON Technology Corp endeavors to enhance product quality as well as reliability in every possible way failure or malfunction of semiconductor products may happen Hence users are strongly recommended to comply with safety design including redundancy and fire precaution equipments to prevent any accidents and fires that may follow Use of the information described herein for other purposes and or reproduction or copying without the permission of HYCON Technology Corp is strictly prohibited 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page10 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 CHIP OVERVIEW 1 1 Brief introduction The HY16F19 is a low power and high precision mixed signal micro controller MCU with LCD driver Liquid Crystal Display and is applicable to perform high precision measurement and control besides the controller can work in a wide voltage range 2 2V 3 6V and the clock of the controller can be up to 20MHZ further the controller has a built in 64 32 16kbyte embedded Flash ROM and 8 4 2kbyte SRAM The HY16F19 series products integrate a high precision 24 bit 2A A D converter Rail to Rail OPAMP 8 bit D A converter Hardware RT
189. ernal interrupt flag 02 PT12IF 0 Normal 1 PT12 external interrupt occurs Bit 01 PT11IF PT11IF PT11 external interrupt flag 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page50 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 0 Normal 1 PT external interrupt occurs PT10IF PT10 external interrupt flag Bi o0 PT10IF Normal 4 0 external interrupt occurs 7 3 6 Interrupt control register INTPT2 INT Base Address 0x14 0 40014 INTPT2 Interrupt Control Register 5 3124 23 22 21 20 19 16 MASK PT27IE PT26IE PT25IE PT24l1E PT23IE PT22IE PT21IE PT20IE 0 7 1 E R 508 1 BI 2 0 PT2IR PT27IF PT26lF PT25IF PT24IF PT23IF PT22IF PT21IF PT20IF When writing the register the Bit15 8 are Mask when reading the register the Bit15 8 are general registers Name Description PT27IE PT27 external interrupt enable control Bi23 PT27IE 0 Disable W NP PT261E 0 Bip PTZ o see SSS Big PTZ 0 O PTEME psbe SSCS www hycontek com page51 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY PT21IE PT21 external interrupt enable control PT211E O Disable ____ PT20IE PT20 external interrupt enable control
190. es user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 Input High PT6 0 Output Enable Bit 3 PT60OE 0 Disable 1 Enable PT6 0 Input Enable Bit 2 PT60IE 0 Disable 1 Enable PT6 0 Output Data PT60DO 0 Output Low 1 Output High PT6 0 Input Data Bit 0 PT60DI 0 Input Low 1 Input High When LCD Mode GPIO Base Address 0x50 0x40850 Symbol SEG2 SEG3 PT6 Control Register 0 31 24 23 22 21 20 19 18 16 Name _ SEG3 Dat RW 1 NW LE IE IH Bit Name Description LCD Segment 3 Data Segment Data LCD Segment 2 Data Segment Data Bit 21 16 SEG 3 Data Bit 5 0 SEG 2 Data 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page126 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 16 3 2 6 2 6 3 register When GPIO Mode GPIO Base Address 0x54 0x40854 Name MASK Bt 501 7 6 0 Bit Name Description PT6 3 Output Enable Bit 19 PT63OE 0 Disable 1 Enable PT6 3 Input Enable Bit 18 0 Disable 1 Enable PT6 3 Output Data Bit 17 PT63DO 0 Output Low 1 Output High PT
191. es user manual HYGON 21 bit ENOB gt 32 bit MCU amp 64 KB Flash 27 3 3 UART register 3 UART Base Address 0x0C 0 40 0 UARTCR3 UART Control Register 3 Bit 31 27 24 16 Tx Data W X 15 8 7 0 Rx Data RX Bit Description Bit 24 16 Tx Data Tx Data Buffer Bit 7 0 Rx Data Rx Data Buffer 2014 HYCON Technology Corp 0 16 198 01 www hycontek com page248 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 28 ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMIT EUART2 28 1 Register address UART2 Register Address 31 24 23 16 15 8 7 0 UART2 Base Address 0 00 0 40 10 Mask1 REG1 UART2 Base Address 0 04 0 40 14 Mask2 REG2 UART2 Base Address 0x08 0x40E 18 Baud Rate UART2 Base Address 0x0C 0x40E1C TX Rx Reserved 28 2 Register function 28 2 1 UART2 register 0 UART2 Base Address 0x10 0x40E10 UART2CRO UART2 Control Register 0 31 24 23 22 21 Name PErr Mask RW RWO 0 DLen R xBusy RxBF 0 2 m 0 RxIT ROW 0 RW 2 Bit Description Rx Buffer over run error flag Bit 23 0 Normal 1 Over run IRx Noise detected flag Bi 22 0 1 Noise detected IRx Frame check error flag Bit21 FErr 0
192. ess 0x60 0x40860 MASK1 PT71CFG MASKO PT7OCFG GPIO Base Address 0x64 0x40864 MASK3 PT73CFG MASK2 PT72CFG GPIO Base Address 0x68 0x40868 MASKS PT75CFG MASK4 PT74CFG GPIO Base Address 0x6C 0x4086C PT77CFG MASK6 PT76CFG LCD Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0 60 0 40860 MASK1 SEG11 MASKO 5 10 GPIO Base Address 0x64 0x40864 MASK3 SEG13 MASK2 SEG12 GPIO Base Address 0x68 0x40868 MASKS SEG15 MASK4 SEG14 GPIO Base Address 0x6C 0x4086C MASK7 SEG17 MASK6 SEG16 LCD Register Address 0x41B04 can determine the setting is the GPIO Mode or the LCD Mode 17 3 Register function 17 3 1 PT7 0 PT7 1 register When GPIO Mode GPIO Base Address 0x60 0x40860 Mame PIMOEPTHIE s mso mA e IE D S Bit Description PT7 1 Output Enable Bit 19 PITIOE 0 Disable 1 Enable PT7 1 Input Enable Bit 18 PT71IE 0 Disable 1 Enable PT7 1 Output Data Bi17 PT71DO 0 Output Low 1 Output High 16 PT71DI 7 1 Input Data 0 Input Low d 2014 HYCON Technology Corp UG HY16F198 V01_TC www hycontek com page135 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 1 Input
193. evelopment space C ASM Register Data Flash Data memory self burning EEPROM the configuration can be defined in any position FIG 3 1 Memory address allocation diagram www hycontek com page16 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 3 2 Memory address The detailed address allocation of the SOC registers of the micro controller is as follows ae Description Base Address module INT Interrupt Flag 0x40000 SoC System control register 0x40100 CLK Clock system control register 0x40300 PMU Power management control register 0x40400 MC Memory controller register 0x40600 PIO GPIO port control register 0x40800 TMR Timer register 0x40C00 UART UART mode control register 0 40 00 SPI mode control register 0 40 00 2 2 mode control register 0x41000 ADC Analog to Digital module control register 0x41100 DAC Digital to Analog module control register 0x41700 CMP Comparator network module control register 0x41800 OPAMP Operational amplifier control register 0x41900 RTC Real time clock control register 0x41A00 Table 3 1 SOC registers Some important registers have MASK bits as describe in FIG 3 3 MASK is used to control written in bits only when the MASK bit corresponding to the control bit is 1 the corresponding control bit can be written in or the written in operation will be invalid and cannot actually modify the value of the register as shown in FI
194. ge164 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 20 2 Register address GPIO Mode Register Address 31 24 23 16 15 8 7 0 Base Address 0 90 0 40890 5 1 PT101CFG MASKO PT100CFG GPIO Base Address 0x94 0x40894 MASK3 PT103CFG MASK2 PT102CFG LCD Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Address 0x90 0x40890 MASK1 SEG35 SEG34 GPIO Base Address 0x94 0x40894 MASK3 SEG1 MASK2 SEGO LCD Register Address 0x41B04 can determine the setting is the GPIO Mode or the LCD Mode 20 3 Register function 20 3 1 PT10 0 PT10 1 register When GPIO Mode GPIO Base Address 0x90 0x40890 100 101 PT10 Control Register 0 Bit 31 241 23 22 21 20 19 18 17 16 16 _ Name PMOIOEPTIOIE PTI01DO Bit 15 08 7 9 1000 PT100D Bit Name Description PT10 1 Output Enable Bit 19 PT1010E 0 Disable 1 Enable PT10 1 Input Enable Bit 18 PT101IE 0 Disable 1 Enable PT10 1 Output Data Bit 17 PT101DO O0 Output Low 1 Output High PT10 1 Input Data Bit 16 PT101DI 0 Input Low 1 Input High Bit 3 PT100OE PT10 0 Output Enable 0 Disable
195. gh impedance 1 Enable and connect to AIO3 23 4 Model program flow FEAA DI r OPA ate ASAE The program starts Initialization settings settings voltage output 2014 HYCON Technology Corp www hycontek com 0 16 198 01 206 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 23 5 Model program function Model name The OPAMP usage and setting method Enable the analog voltage REFO 1 2V Connect the REFO to the positive end V of the OPAMP Select the OPOI as the negative end of the OPAMP now it will be the Unit Gain Buffer Via proper OPAMP network setting the REFO 1 2V can be measured at the output end of the OPO 23 6 Model program description 00 01 include HY16F19X h 02 03 lint main void 04 05 DrvPMU VDDA LDO Ctrl E LDO ON 06 DrvPMU VDDA VDDA3 0 INDDA 3 0 07 DrvPMU REFO Enable ON 08 09 DrvOP 10 11 DrvOP 0 08 positive reference input selection REFO 12 Ninput 0x10 negative reference input selection OPOI 13 14 DrvOP OPOoutEnable OoutEnable 15 16 while 1 while loop 17 18 2014 Technology Corp 0 16 198 01 www
196. gister it can be locked to protect the register to prevent data from being written in the register Bit 23 20 The write in secret key it can lift the protection of the register data be written in the register only after it is unlocked Lock the register to protect it Others data can be written in the register Leap year flag Bit 19 The current year is not a leap year The current year is a leap year imer wake up interrupt flag 1 Timer wake up is triggered Wake up interrupt flag Bit 17 Normal 1 The wake up interrupt is triggered Alarm clock status flag Bitr16 Bits Dae COZWAHYCONTechnolgy Cop Or NO www hycontek com page279 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash Bit 04 WUFENO Disable W RTC alarm clock function enable control Bit 03 TAEN 0 Disable 1 Enable RTC hour format configuration 24 12 Bi02 HRF 12 hour system PM AM 1 4 hour system RTC clock source input selection Bit 01 CKS 0 External low speed crystal oscillator source 1 low speed crystal oscillator source RTC function enable control Bit 00 RTCEN 0 Disable the function of the RTC 1 Enable the function of the RTC 30 3 2 Hardware RTC register RTCCR1 Base Address 0x04 0x41A04 RTCCR1 RTC Control Register 1 22 16 CM RW 0 2 0 T RW 0 Bit Name Description Bit 22 1
197. gister PMU 4 ENBGR as 1 Only after the BandGap reference voltage is enabled the common mode voltage REFO can effectively output 1 2V Itis necessary to provide a common mode voltage REFO for the ADC to enable it If the user wants to use the internal power supply the ACMS should be set as 1 if the user wants to the external power supply the ACMS should be set as 0 to output a common mode voltage REFO The user will need to use a reference voltage to drive the external circuit therefore the ENRFO should be set as 1 to output the common mode voltage to the pin besides the REFO is the BandGap reference voltage with buffer The output voltage of the REFO pin is about 1 2V and has 200uA push pull driving ability 1t can drive a 22 1000nF big capacitor load If the external REFO voltage output is used the common mode voltage for the ADC can be provided by an external power supply in this case the ACMS can be set as 0 to save more power www hycontek com page26 HY16F19 series user manual 21 bit ENOB 32 bit MCU 64 KB Flash The following table shows the voltage sources for all modules Table 5 1 Chip Power supply distribution Block name Voltage source Block name 32 bit CPU Core N801 VDD18 Timer A B C PWM 08KB SRAM VDD18 GPIO Port 64KB Flash ROM VDD3V VDD18 24 bit SD ADC Clock System VDD18 08 bit DAC Watch Dog Timer VDD18 Rail to Rail OPAMP Hardware RTC VDD18 Analog Comparator Charge Pump VIN BOR VDD3V VDD18
198. gurations PAD PT10DI PT10IE L 10 3 5 m FIG 20 1 PT10 function block diagram The PT10 has input and output functions and different functions should be set by different controllers Output mode The controller PT10xOE 0 can enable or disable the output mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding IO port will be enabled if it is set as 0 the output mode of the corresponding port will be disabled The control bit PT10xDO 0 can determine whether the output status of the pin of the corresponding IO port is 1 or 0 Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled Input mode The controller PT10xIE 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit controller is set as 1 the input mode of the corresponding IO port will be enabled if itis set as 0 the input mode of the corresponding IO port will be dis
199. h a EH 2 2 2 2 EX 0 BE 2 W 00 2 0 agar e CO8L YLO COEL IC0 COR inem taz 8 19 8 2 2 fe WO LL iL IL 85 0 16 198 01 FIG 10 10 Schematic view of PWME output waveforms 2014 HYCON Technology Corp www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY PWME output operation description Initialization The PWM frequency and duty cycle configuration Setting the TMCKS 0 can select the operating frequency source of the TMB and setting the TMCD 1 0 can determine the operating frequency of the TMB When the TBM 1 0 is set as 11 the TMB serves as 8 8 bit counter When the OOMD 2 0 or OTMD 2 0 is set as 100 the output waveform is the PWME Setting the TBEBS 1 0 as 00 can set the counting trigger signal as Always Enable which means cycle counting Write data in the TBCO 7 0 to determine the frequency of the PWM Write data in the TBC1 7 0 to determine the duty cycle of the PWM Write data in the TBC2 7 0 to determine the duty cycle fine adjustment method of the PWM Setting the TBEN 0 as 1 to enable the counter W Generate PWME waveform When the counting value of the TBR 7 0 is equal to that of the TBC1 7 0 the PWME will be 031 When the cou
200. he corresponding pin is 0 or 1 can be read via the controller PT9xDI 0 If the IO is set as the input mode and the chip should be connected to the external pull up resistor and the 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page153 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash is not allowed to be floating in order to prevent from the electric leakage of the chip Especially in the low power mode it is suggested the IO pin should be set as the input mode If it serves the analog signal input port it is not necessary to set the corresponding pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled LCD mode The controller SEGx 5 0 determines the output data of the LCD SEGMENT If the LCD is under the 1 6 duty mode the SEGx 5 0 can determine the data content of the 1 6 duty data content if the LCD is under the 1 5 duty mode the SEGx 4 0 can determine the 1 5 duty data content if the LCD is under the 1 4 duty mode the SEGx 3 0 can determine the 1 4 duty data content if the LCD is under the 1 3 duty mode the SEGx 2 0 can determine the 1 3 duty data content 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page154 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 19 2 Register address GP
201. he value of the CPDA 0 is controlled by the CMPO and keep consistent 0 Disable 1 Enable 0 Voltage division node configuration of the built in multi node resistor of the comparator 0000 0 0001 1 16 0010 2 16 0011 3 16 0100 4 16 Bit 23 CPDM 3 Bit 22 CPDMI2 Bit 21 CPDM 1 Bit 20 4 GBA CPRLH CPRLL CPRLH CPRLL CPRLH CPRLL CPRLH CPRLL P p prm 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page222 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash Bit 5 4 Bit 1 0 CPNS CPPS 2014 HYCON Technology Corp www hycontek com 0101 5 16 CPRLH CPRLL 0110 6 16 CPRLL 0111 7 16 CPRLL 1000 8 16 CPRLL 1001 9 16 CPRLL 1010 10 16 CPRLH CPRLL 1011 11 16 CPRLH CPRLL 1100 12 16 CPRLH CPRLL 1101 13 16 CPRLH CPRLL 1110 14 16 CPRLL 1111 15 16 CPRLL The negative input end selection of the comparator 00 CH1 01 CH2 10 CH3 11 RLO The positive input end selection of the comparator 00 CH1 01 CH2 10 CH3 11 V12 HYGON HYCON TECHNOLOGY 0 16 198 01 223 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU 8 64 KB Flash Aare 25 3 3 CMP register 2 Bit 19 17 16 Name MASK ENCLIN Bit MAS MASK Row
202. heck the current operating mode of the PWM via the PWM operating mode flag register if the flag is 1 it means the operating mode is enabled The 1 2 are the duty cycle controller of the PWMO PWM 1 respectively the duty cycles of the PWMs can be changed by setting the values of the TBC1 TBC2 The chip provides 8 output 10 for each PWM and the corresponding pins distributed over the PT1 PT2 the selection and enablement of the output pins of the PWM1 and PWMO are controlled by the controllers PTPW 2 0 PTPW1E PTTPWOE The output and disablement of the PWMs can be controlled by the enablement and disablement of the output pins of the PWMs If the user wants to completely disable the PWMs it is necessary to disable the output pins of the TMB and the PWMs The output pins of the are as shown in Table 10 1 Serial PWMO PWM1 Serial PWMO 1 number Output pins Output pins number Output pins Output pins PTPW 2 0 TPW 2 0 000 PT1 0 100 2 0 2 1 001 1 2 1 3 101 2 2 2 3 010 1 4 1 5 110 2 4 PT2 5 011 PT1 6 PT1 7 111 PT2 6 PT2 7 Table 10 1 PWM output pin distribution PWM operation description Set the operating clock frequency source of the TMB and set the ENTD 1 TMCD 1 0 Select the counting method and counting trigger signal source of the TMB and set the control bits TBM and TBEBS www hycontek com page76 16 19
203. hip may be decreased and the chip may be reset in this situation it is necessary to enable the charge pump boost circuit to output a stable voltage to VDD3V via the CP_O pin so as to make sure the chip can work normally The VDD18 LDO output a stable voltage 1 8V via the VDD18 pin and the pin should be connected to a 1uF bypass capacitor The VDD18 LDO has a low power voltage mode the register PMU 0 VDDLP should be set as 1 to achieve lowest power consumption Before the control bit enters the IDEL mode the user can set it as 1 after the MCU is wakened the bit will be cleared to be 0 VDDA voltage The chip has a voltage regulator circuit LDO VDDA and the VDDA voltage should be enabled when using ADC It can have different operating modes and different output voltages has four different operating modes the first mode is to be short circuited to the VDD3V and the VDDA is close to the VDD3V during the mode The second mode is Weak pull down during the mode the CDDA is close to the VSS The third mode is High Z and it is possible to input the voltage into the CDDA from outside but the inputted voltage should not exceed VDD3V The four mode is adjustable voltage regulating mode LDO during the mode the VDDA can output four different voltages 2 4V 2 7 3 0V and 3 3V For better performance the voltage difference between VDD3V and VDDA Should be higher than 0 2V and can drive at most 10mA Additionally it also needs to be connected t
204. hour system Calendar information The calendar information is stored in the RTYE RTMO RTDA RTWDA registers which use BCD format The algorithm for leap year is performed by the hardware 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page277 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash The effective year period is between 2012 2099 The year is expressed by two digits which stands for 20xX year system is reset is 12 1 1 Sunday January 2 2012 The maximal year is 99 and the year will become 00 1 1 after 99 12 31 but the leap year compensation will fail if the above condition takes place Week counter HYGON HYCON TECHNOLOGY If the RTLPYF is 1 it is the leap year The default date after the The RTC controller provides the information about one week The WDA value is defined from 0 to 6 which stands for Sunday to Saturday respectively Alert interrupt If the registers RTYE RTMO RTDA RTHR RTMI RTSE conform to the registers RCYE RCMO RCDA RCHR RCMI RCSE and the RTAEN is 1 the RTTAF interrupt flag will be set as 1 to MCU Periodic timer interrupt The periodic timer has 8 periodic options for interrupt 1 128 1 64 1 32 1 16 1 8 1 4 1 2 and 1 second Set the RTPFEN 1 to enable the periodic timer interrupt controlled by the RTPT lt 2 0 gt System wake up interrupt These periodic options are When the MCU enters the idle mod
205. hycontek com page207 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU 8 64 KB Flash Aare 23 7 OPAMP application circuit system I Use as a Unit Gain Buffer 5 0 AlO4 OPPSI1 j DAO OPPS 2 Y REFO _ 5 0 OPO1 OPO2 R2ROP 1 OPNS 0 AlO5 OPNS 1 DAO OPNS 2 7 CHPCK OPNS 3 2271 OPNS 5 7777711 23 8 OPAMP application circuit system ll Use as an Integrator 0 gt 1 1 2 1 R2ROP Signal aos gt s OPOI BIOS TS OPCS DAO mm Signal2 AIO7 SEG 10pF ES LIS OPOC Can use DAC as OPOI 0 vss Programmable Resister 5 m 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page208 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 23 9 OPAMP application circuit system Use as a 8 bit SAR ADC Sample Phase Signal Input gt 2 AIO4 0 2 3 OPOR 1 OPOD OPO zu 0 bes Delay gt
206. inally the lower end of the capacitor can be connected t the output end of the OPAMP which means setting the OPCS 0 Meanwhile the AIO3 and the AlO5 pins can be used to perform cumulative charge 2014 HYCON Technology Corp UG HY16F198 VO1 TC www hycontek com page200 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash 23 1 3 Comparator function If the configuration of the OPAMP is set as the open loop function the OPAMP can serve as comparator The 1 bit binary codes can be outputted by the OPOD If the positive input is higher than the negative input the OPOD outputs 1 if the positive input is smaller than the negative input the OPOD outputs O In order to prevent from the peak pulse interference the outputs of the OPOD can further pass the 2us low pass filter If any peak pulse is smaller than 2us the outputs of the comparator will not change outputs of the comparator can be changed by setting the control bit OPDR The output of the comparator can be also connected to the I O pins The PT3 0 PT3 1 are respectively the output pins of the OPO1 OPO2 The output results of the comparators can further be multiplied by the clock frequency of the charge pump CHPCK to output a high frequency signal which can serve as the LED driver 23 1 4 Operation description The OPAMP is a more universal Rail to Rail OP amplifier It can be used to deal with analog signal
207. ing 8 output periods as one set where one of them outputs N and then the other 7 output N 1 Set the TBC2 7 0 as 07h 1 2 1 4 1 8 1 16 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 16 output periods as one set where one of them outputs N and then the other 15 output N 1 Set the TBC2 7 0 as 1Fh 1 2 1 4 1 8 1 16 1 32 which makes the waveform of the PWM duty cycle generates the N 1 and N outputs which is to generate a waveform using 32 output periods as one set where one of them outputs N and then the other 31 output 1 Set the TBC2 7 0 3Fh 1 2 1 4 1 8 1 16 1 32 1 64 which makes the waveform of the PWM duty cycle generates the 1 and outputs which is to generate a waveform using 64 output periods as one set where one of them outputs N and then the other 63 output N 1 Set the TBC2 7 0 as 7 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 which makes the waveform of the PWM duty cycle generates the N 1 and outputs which is to generate a waveform using 128 output periods as one set where one of them outputs N and then the other 127 output N 1 Set the TBC2 7 0 as FFh 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 which makes the waveform of the PWM duty cycle generates the N 1 and outputs which is to generate a waveform using 256 output periods as one set where one of them outputs N and then the other 255 output N 1 The following Table 10 2 and FIG 10 10
208. isters comparator output interrupt enable control Bit 17 CPOIE 0 Disable 1 www hycontek com page48 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Low noise OP amplifier output OPO interrupt enable control Multi function comparator output interrupt request 9 CPOIR 0 0 0 Interrupt Low noise OP amplifier output OPO interrupt request Bis Multi function comparator output interrupt flag CPO O Noma 4 Multi function comparator output CPO interrupt occurs Low noise OP amplifier output OPO interrupt flag 90 OPOIF 0 Noma 1 Low noise OP amplifier output OPO interrupt occurs 7 3 5 Interrupt control register INTPT1 INT Base Address 0x10 0x40010 INTPT1 Interrupt Control Register 4 31 24 23 22 21 20 19 18 16 MASK PT16IE PT15IE PT14IE PT13IE PT12IE PT11IE PT10IE 1 RW 0 Bit 1508 m 69 2 Uu 0 Name PT17IF PT16IF PT15IF PT14IF PT13IF PT121F PT111F PT10IF RW RO RWO O When writing the register the Bit15 8 are Mask when reading the register the Bit15 8 are general registers Bit Name Description PT17IE PT17 external interrupt enable control Bit23 PT17IE 0 Disable 1 Enable 16
209. itten in the register thus the user should be extremely careful with the write in operation Enable the RTC It is necessary to write 0110 in the RTKEY before writing data into the RTC register If the user wants to enable the RTC the user should check whether the LPOSC or LS can be used first Then set the RTCEN as 1 Frequency compensation The RTC allows the digital compensation for the clock input The central frequency of the RTC is 32768Hz Any imperfect operations may result in the frequency offset digital compensation can be used to reduce the frequency offset The compensation method is to execute 2 at each step the permissible maximal frequency change is 126 and the permissible minimal frequency change is 126ppm The maximal input frequency is 32772Hz and the minimal input frequency is 32763Hz The maximal reference frequency that the user can input is 16MHz to measure the RTC clock during the manufacturing period The measurement value is calculated to obtain the compensation value Then the compensation value will be stored in the flash memory Once the system starts up the compensation value will be loaded into the lt 6 0 gt Time information The time information is stored in the RTHR RTMI RTSE registers which use BCD format The user can set the time as the 24 hour system or 12 hour AM PM system The time default value is 00 00 00 hour minute second and it is 24
210. l be changed to perform decremental counting the interrupt request will take place until the TBR is decreased to 0 and the interrupt flag TMBIF is set as lt 1 gt and then the TBR will start to perform incremental counting at the next rising edge of the TBCLK The above process will be kept repeating The schematic view of the counting waveform of the mode is as shown in the following figure In the mode the calculation method of the counting cycle of the TMB is T 2 TBCO TMCD HS CK orLS CK TBR 15 0 Oh TBM 01 time TBCLK TBR TBRaa1 TBR may 1 2 0002h O001h 5456 UP Down Up Mode Down Mode www hycontek com page72 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY TBCLK TBR 0001h 0000h 0000h 0001h 0002h Clear by TMBIF lt user UP Down Down Mode Up Mode FIG 10 3 Schematic view of counting waveform of counting method 1 TMB counting method 2 When TBM 1 0 01 the TMB will perform incremental counting but the TBR is separated into two independent 8 bit counters TBR 15 8 and TBR 7 0 Besides the two independent 8 bit counters perform incremental counting at the same time The overflow value of the TBR 15 8
211. l be transmitted SPIA 0100 A STOP will be transmitted STA 8Ch SPIA 0010b Data byte has been transmitted ACK has been received STA SPIA 00106 A repeated START has been transmitted STA 30h SPIA 0000b A STOP has been transmitted STA 88h SPIA 0010b Data byte has been transmitted NACK has been received STA 000xxx01b SPIA 0010b Arbitration lost SPIA 0000 Slave A R W will be transmitted SPIA 0000 Idle or Slave Mode will be entered To Slave Mode SPIA 1000 START will be transmitted when the bus becomes free To Master Receiver A FIG 29 4 Master Transmitter Mode 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page260 16 19 series user manual HYGON 21 bit ENOB AADC gt 32 bit MCU 8 64 KB Flash 29 2 3 I2C Master RX flow SPIA 1000 Set S to generate a START STA 90h SPIA 0010b A START has been transmitted From Slave Mode C Status with IRQ C Status without IRQ Action 0000 Slave will be transmitted From Master Transmitter A STA 91h SPIA 0010b Slave A has been transmitted NACK has been received STA 94h SPIA 0010b Slave A R has been transmitted has been received SPIA 0000 SPIA 0001 Data byte will be received Da
212. l bit 1 Start 5 Start signal control bit 1 control bit Generate the start signal from the 12C bus Stop signal control bit 9 Normal 1 Generate the stop signal from the 12C bus Genet control bit 0 Normal Bit 01 IRQFI Reply to the interrupt the device will reply to the interrupt after ag l receiving 9 clocks and then draw the SCL to low potential until the bit is cleared and release the SCL signal wire writing in O will clear the device status control bit and make the I2C proceed to the next status AINA T Response signal replying control bit Bit 00 A a Fail to reply to the ACK or reply to NACK The response signal ACK has been replied 25 3 4 I2C register 2 2 Base Address 0x08 0 41008 Symbo I2CCR2 I2C Control Register 2 RW 2 X O I2C bus data serial transmission rate control register Bit 23 16 CRG Set 1 The data serial transmission rate of the I2C bus is determined by the values of the clock source of the I2C and the serial transmission rate control register CRG the data serial transmission rate of the I2C bus can be calculated according to the following equation Data Baud Rate I2CLK 4x CRG 1 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page267 HY16F19 series user manual HYGON _24 bit ZAADC 32 bit MCU amp 64 KB Flash Time out flag Bit 7 mo
213. le the ADC interrupt function according to the actual requirements and enable the global interrupt GIE Enable the ADC Reset the comb filter CFRST 0 and enable the comb filter CFRST 1 the hardware automatically throws the first 3 pieces of the data and then waits until the first ADC interrupt signal occurs after that the output data ADCO 23 0 of the ADC can be sampled 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page187 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash 22 2 Register address ADC Register Address 31 24 23 16 15 8 7 0 ADC Base Address 0x00 0 41100 MASKO REGO MASK1 REG1 ADC Base Address 0x04 0x41104 REG2 REG3 MASK4 REG4 ADC Base Address 0x08 0x41108 ADO3 ADO2 ADO1 0x00 Reserved 22 3 Register function 22 3 1 Analog ADC register ADCCRO Symbol ADC Base Address 0x00 0x41100 ADCCRO ADC Control Register 0 Bit 3124 23 2 21 120 19 18 VISHR VRSHR VRPS VRNS RW 0 RW ROWO 58 m MASK ADFDR OSR CFRST ENADC Rw Bit Name Description Bit 21 VISHR 0 1 ADC signal input end positive and negative short circuit switch control Short circuit switch opens Short circuit switch closes ADC reference voltage input end positive and
214. manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 3 Register function 6 3 1 Clock system register CLKCRO Clock Base Address 0x00 0x40300 CLKO Clock Control Register 0 31 16 Bit Name RSV Reserved RW Bit Bit Name RW Bt 158 7 6 5 43 12 m 0 MASK OHS HS CKLS CKHS HAO ENOLS ENOHS ENHAO RW ROWO A RWO0 RW Bit 7 HSXT 4MHz HSXT gt 4MHz Chip low speed frequency source selection Bit 6 Internal low speed oscillator OSC LSRC 1 External low speed oscillator LSXT Chip high speed frequency source selection Bit 5 CKHS External low speed oscillator 5 1 External high speed oscillator HSXT Internal high speed oscillator mode configuration Bit 4 3 HA b 10 10MHz 11 16MHz External low speed oscillator enablement control Bi 02 ENOLS External high speed oscillator enablement control Bit 01 ENOHS 1 Internal high speed oscillator enablement control ENHAO 1 5 c www hycontek com page35 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 6 3 2 Clock system register CLKCR1 Clock Base Address 0x04 0x40304 CLK1 Clock Control Register 1 31 16 Reserved 15 8 7 0 HAOTR 80 RW 80H 1 LSB Step 0 125 0000 0000 is the lo
215. maximal output rate is 10 24KSPS its ENOB Effective number of bit is 21 and its minimal resolvable signal is 65nV RMS Noise Root Mean Square The programmable gain amplifier with low noise is used with the A D converter together and the maximal gain is 128 times magnification There is a built in 4 bit A D converter at the input of the A D converter to expand the measurement range The power management provides selectable analogous regulating voltage which can serve as reference voltage source or the power supply of a transducer The working power source of the core of the CPU is also provided by the internal linear stabilized power supply The charge pump is used to block the power interference from the system 64Kbyte embedded Flash ROM can be used to execute programs or store data the data can be still stored into the Flash ROM even if the Flash ROM is executing a program www hycontek com 11 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY A built in 8kbyte SRAM is provided for the system to use The core of the 32 bit high performance mixed signal micro controller can execute an instruction during each clock cycle which can be up to 20MIPS Millions of Instructions Per Second and conform to low power consumption indicator HYCON Technology provides convenient programming tools for users to write programs by language or assembly language in the development pl
216. n PT7 7 Output Enable Bit 19 PT77OE 0 Disable 1 Enable PT7 7 Input Enable Bit 18 PT77IE 0 Disable 1 Enable PT7 7 Output Data Bit 17 PT77DO 0 Output Low 1 Output High PT7 7 Input Data Bit 16 PT77DI 0 Input Low 1 Input High PT7 6 Output Enable PT76OE 0 Disable 1 Enable PT7 6 Input Enable Bit 2 PT76IE 0 Disable 1 Enable PT7 6 Output Data PT76DO 0 Output Low 1 Output High PT7 6 Input Data Bit 0 PT76DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page141 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode GPIO Base Address 0x4086C MASK gt Data Bk 50 U BI M 0 SEG16 Data Bit Name Description LCD Segment 17 Data Segment Data LCD Segment 16 Data Segment Data Bit 21 16 SEG 17 Data Bit 5 0 SEG 16 Data UG HY16F198 VO1 2014 HYCON Technology Corp page142 www hycontek com 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 18 GPIO PT8 MANAGEMENT 18 1 Overall description The PT8 has 8 IO pins which be used as the common universal IO ports and can also be reused as the LCD function output port Different reuses n
217. nable PT8 7 Input Enable Bit 18 PT87IE 0 Disable 1 Enable PT8 7 Output Data PT87DO 0 Output Low 1 Output High PT8 7 Input Data Bit 16 PT87DI 0 Input Low 1 Input High PT8 6 Output Enable Bit 3 86 0 Disable 1 Enable PT8 6 Input Enable Bit 2 PT86IE 0 Disable 1 Enable PT8 6 Output Data PT86DO Output Low 1 Output High PT8 6 Input Data Bit 0 PT86DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page151 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash When LCD Mode GPIO Base Address 0 7 0x4087C o SEG2S Data Bit 15 00 7 6 i 0 Name MASK SEG24 Data Bit Name Description LCD Segment 25 Data Segment Data LCD Segment 24 Data Segment Data Bit 21 16 SEG 25 Data Bit b 0 SEG 24 Data 0 16 198 01 2014 HYCON Technology Corp page152 www hycontek com 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 19 GPIO PT9 MANAGEMENT 19 1 Overall description The PT9 has 8 IO pins which can be used as the common universal IO ports and can also be reused as the LCD function output port Different reuses need different configurations PAD PT9DI
218. nableGIE 7 Enable GIE 57 58 while 1 for Interrupt 59 60 61 62 void HW2 ISR void interrupt 63 64 DrvADC Clear ADC interrupt flag 65 ADCData DrvADC GetConversionData Get ADC data 66 67 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 TC page196 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 23 RAIL TO RAIL OPAMP 23 1 Overall description The chip has an embedded Rail to Rail OPAMP network which is mainly used to deal with analog signals The input range and the output range are from VSS to VDDA When the input signal range is between VSS 0 1 V and VDDA 0 1V the open loop gain is higher than 80dB When the output load is 50PF the unit gain bandwidth is 1MHz It has the 1mA input and output push pull driving ability The maximal drivable capacitor load is 100pF The positive input end has 4 independent selection switches and the negative input end has 6 independent selection switches The OPAMP network has a built in 10pF capacitor It can serve as input sampling capacitor or integrator Different input channel configurations and 8 bit DAC configurations can achieve different applications output end of the OPAMP can be connected to an pin or used by other internal IPs When it serves as comparator its output is digital format user can set the output
219. nd select the PWME as the output waveform of the PWM then the 8 8bit PWM output is acquired The 8 8 bit PWM is composed of the control registers TBR 7 0 TBR 15 8 TBCO 7 0 TBC1 7 0 and TBC2 T7 0 etc and the internal digital circuits where the TBR 7 0 is the accumulating counter the TBCO 7 0 is the PWM frequency controller and when the counting of the TBR 7 0 reaches the TBCO 7 0 the TBR 15 8 will be added by 1 the TBC1 7 0 is the PWM duty cycle controller and the TBC2 7 0 is 8 8 bit PWM duty cycle adjuster The following waveform description is under the conditions that the O1PMR is set as lt 0 gt and outputs inversely The configuration and description of the 8 8 bit PWM duty cycle adjuster TBC2 7 0 are as shown in the follow table Configuration TBC2 7 0 Weighted quanti 01h 02h O4h O8h 10h 20h 40h 80h PWM duty cycle fine 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 adjustment d 5 z vs 00 vs 00 5 w w 2 2 o E E za 214 gi 3 8 2 8 Fla 9 a wf2 5 6 8 3 Description i Pl pl 2 3 2 2 2 2 2 gt 8585 8584 e 310 3 n n n N 0 2 z 2 3 3 Table 10 1 Configuration table of duty cycle adjuster The description of the duty
220. nd short circuit switch disconnect the resistor short circuit of the resistor and enable the reference voltage source of the resistor Disable the IO output mode of the touch button Clear the counter register of the TMB Enable the non overlap function and select the touch button to be charged Read the counting value of the TMb after the charging is finished 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page220 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYGON HYCON TECHNOLOGY 25 2 Register address CMP Register Address 31 24 23 16 15 8 T 0 Base Address 0x00 0 41800 5 1 REG1 Base Address 0x04 0 41804 MASK2 REG2 MASK3 REG3 CMP Base Address 0x08 0x41808 MASK4 REG4 MASK5 REG5 Reserved 25 3 Register function 25 3 1 CMP register 0 Base Address 0x00 0x41800 Symbol CMPCRO CMP Control Register 0 Bit 31 17 16 Name CMPO RW R 0 Bit 15 08 7 5 4 3 2 1 0 Name MASK CPIS CPOR CPDF CMPHS ENCMP RW ROW 0 RW 0 Bit Name Description The comparison result input transferring out status of the comparator Bit 16 CMPO 0 Negative input signal gt Positive input signal 1 Positive input signal gt Negative input signal The short circuit switch control of the comparator Bit 4 CPIS 0 Short circuit switch opens 1 Short
221. ng the ENOP 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page201 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 23 2 Register address HYGON HYCON TECHNOLOGY OPAMP Register Address 31 24 23 16 15 8 7 0 Base Address 0x00 0 41900 MASKO REGO OPAMP Base Address 0x04 0x41904 OPPSM OPPS OPNSM OPNS Reserved 2014 HYCON Technology Corp www hycontek com 0 16 198 01 202 Bit HY 16F19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 23 3 Register function 23 3 1 Analog register 0 Name R 0 Bit 1508 7 6 5 OB 2 m O MASK OPOD OPOS OPDR OPEO RW ROWO RO Name Description OPAMP digital output value read only Bit 7 0 Negative input end signal gt positive input end signal 1 Positive input end signal Negative input end signal Set the outputs of the OPO1 OPO2 pass through the CPCLK multi functioner If the outputs fail to pass the CPCLK multi functioner Bit 6 0 outputs of the OPO1 OPO2 are equivalent to the OPOD If the outputs pass the CPCLK multi functioner 1 the OPO1 OPO2 are equivalent to the OPOD CPCLK OPAMP digital output phase selection Bit 5 0 Normal output 1
222. nternal crystal oscillators The operating voltage of the chip should be kept high when using the 16 2 HAO The output frequency of the HAO can be adjusted by modifying the register HAOTR The default oscillator of the chip is the internal 2MHZ HAO the user can modify the default settings and change the output frequencies of other HAOs The stabilization time of the 4MHZ HAO is about 0 5ms After the SLEEP instruction is executed all HAO oscillators will stop and enter the SLEEP mode After the IDEL instruction is executed all HAO oscillators will not stop but the CPU will enter the IDEL mode The LPO is the internal low speed RC oscillator of the chip its output frequency is 35kHZ and has low power consumption it will immediately start after the chip is power on or wakened besides it cannot be enabled in other words the LPO will keep working during the whole operation process of the chip The stabilization time of the LPO is about 510us and it is the only operating clock source of the WDT After the SLEEP instruction is executed all LPO oscillators will stop After the IDEL instruction is executed all LPO oscillators will not stop but the CPU will enter the IDEL mode Typical output frequencies of the HAO and LPO are as shown in following Table 6 2 Instruction execution Frequency source configuration Symbol Frequency status ENHAO 1 HAO 1 0 CKHS 1 Sleep Idle 2MHZ 1 00B 0 Stop
223. nterrupt flag Bit 03 TMC1IF Normal 1 interrupt occurs TMCO interrupt flag Bit 02 TMCOIF O0 Normal 1 interrupt occurs Timer TMB interrupt flag Bit 01 TMBIF Normal 4 Timer TMB interrupt occurs Timer TMA interrupt flag 00 TMAIF 0 Normal 1 TMA interrupt occurs www hycontek com page47 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 7 3 3 Interrupt control register INTADC INT Base Address 0x08 0x40008 mbol INTADC Interrupt Control Register 2 Nam MASK AE ROW 0 E ee 15 9 8 07 01 Name ADCIR ADCIF RO eee RWO 0 When writing the register the Bit15 8 are Mask when reading the register the Bit 8 is general register _ Bit Name Description ADC converter interrupt enable control Bi 16 ADCIE 0 Disable ADC interrupt request 8 ADCIR 1 hnterrupt ADC converter interrupt flag Bit 00 ADCIF 1 converter interrupt occurs 7 3 4 Interrupt control register INTCMP INT Base Address OxOC 0 4000 ymbol INTCMP Control Register 3 POE RW ROWO RW 0 gp MASK Name CPOIR OPOIR CPOIF OPOIF Rw RWO 0 When writing the register the Bit15 8 are Mask when reading the register the Bit9 8 are general reg
224. nting value of the TBR 7 0 is equal to that of the TBCO 7 0 again the PWME will be 130 Y And the overflowing event takes place to set the TBxIF 0 as 17 and reset and restart the incremental counting at this time if the TBxIE 0 is set as lt 1 gt the interrupt event service will take place Atthis time the set value of the TBC2 7 0 adjusts the outputs of the PWME to be N 1 and as shown in the table where N TBC1 7 0 W PWM output control Set the OOPMR 0 or OTPMR 0 to determine whether the output waveform of the pins is opposite in phase or not Set the PTPWOE 0 or PTPW1E 1 as lt 1 gt to set the pin of the PWM waveform be under output status select appropriate PWM waveform output pin for the PTPW 2 0 Set the TBEN 0 as 0 to disable the counter and the PWM output W The calculation formula of the frequency and duty cycle of the PWME TECI T TECO4 1 Fine adjustment Fine adjustment is effective when the duty cycle is 1 the formula is as follows lt X gt stands for each bit of the TBC2 lt 0 gt 126 lt 1 gt 64 lt 2 gt 32 lt 3 25 16 4 gt 8 5 54462244 7 Fine adjustment www hycontek com page86 PWMF mode PWMF is 16 bit PWM counting value of the is compared with the TBC1 and TBC2 and the TBC2 should be larger than TBC1 the TBR will keep increasing until overflowing PWM output status control conditions PWM 1 when TBC1 15 0 lt
225. ntrol 15 DIvADC ReflnputShort OPEN ADC reference short control 17 DrvADC Gain ADC Disable ADC Disable Input signal gain 19 DrvADC DCoffset 0 offset 20 DrIvADC RefVoltage REF BUFFER OUT VSSA IADC reference voltage 22 DrvADC_FullRefRange 0 full reference range select 0 Full reference range input 1 1 1 2 reference range input 2014 HYCON Technology Corp www hycontek com 0 16 198 01 page195 HY16F19 series user manual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYG N HYCON TECHNOLOGY 28 29 ADC Speed 30 31 DrvADC_OSR 1 OSR 16384 32 DrvADC CombFilter Enable Enable OSR 33 34 DrvADC ClkEnable O0 1 ADC CLOCK 35 I ADCK HS CK 6 36 Rising edge is high 37 38 VDDA voltage 39 40 DrvPMU VDDA Voltage E VDDA2 4 INDDA 2 4 41 VDDA Ctrl E 100 ON 42 DrvPMU BandgapEnable 43 DrvPMU REFO Enable 44 45 DrvPMU AnalogGround Enable analog ground source set 46 1 Enable buffer 47 use internal source 48 to work with ADC 49 50 Set ADC interrupt 51 52 DrvADC Enablelnt 53 DrvADC ClearlntFlag 54 DrvADC Enable 55 56 SYS E
226. ntrol Register 0 31 24 23 22 20 19 18 16 O3PMR O3MD O2PMR O2MD 0 1411 92 0 Reg TB2EN TB2RST TB2M 2 5 ROW 0 RW ROW 0 RW 0 Bit Name Description PWM3 waveform output phase control Bit 23 OSPMR 0 Inverted output 1 Normal output PWMS3 operating mode selection 0 PWMA 1 PWMB 2 PWMC 21 20 O3MD 3 PWMD 4 PWME 5 PWMF 6 PWMG 7 PWMG 2 waveform output phase control Bit 19 O2PMR 0 Inverted output 1 Normal output Bit 18 16 O2MD PWM2 operating mode selection 0 PWMA 1 PWMB 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page95 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash HYCON TECHNOLOGY 2 3 PWMD 4 PWME 5 PWMF 6 PWMG 7 PWMG Timer B2 enablement control Bit5b TB2bN 0 Disable 1 Enable Timer B2 reset TB2RST Do Clear the counting register TBR of the Timer B it will be 1 automatically set as 0 after finished Timer B2 counting mode selection 16 bit up counter sawtooth wave type counting method the 00 counting will increase to the maximum TBCO on the basis that the step is 1 16 bit up down counter triangle wave type counting 01 method the counting will increase to the maximum TBCO on the basis that the step is 1 and then decrease to 0 2 independent 8 Bit up counters TBR 15 8 and TB
227. o a 1uF bypass capacitor Low voltage detection circuit BOR The BOR circuit is used to monitor the stability of the power system and the MCU When the BOR detects the VDD3V and VDD18 are lower the detecting voltage of the BOR the BOR will be triggered to reset the system and the chip the chip will work normally until the BOR detects the operating voltage of the chip exceeds the voltage of the BOR Charge Pump The charge pump regulator provides stable voltage for the chip which can also be used to separate the power supply of the system from the power supply of the chip Some applications will need to use high current external circuit such as driving a DC motor in this case it is necessary to enable the charge pump to make sure the operating voltage of the chip is stable and the interference caused by the surge current from the inductors of the www hycontek com page25 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY motor can be reduced So as to enable the charge pump the register PMU 2 should be set as 1 and the ADC clock source should be enabled the external circuit needs connect an external capacitor Ccp2 in series between the CH CL pins and respectively connect an external ground capacitor to the CP_I CP_O pins the voltage regulating output end of the charge pump should be short circuited to the operating voltage pin VDD3V of the chip When the charge pump is
228. of the to pass 2us peak pulse filter Besides the output of the comparator be on and off or opposite in phase The features of the OPAMP include Rail to Rail input range and Rail to Rail output range Under a 2pF load it can provide a 1MHz unit gain bandwidth and 60 phase margin The DC gain can be higher than 80dB 1 push pull output driving ability The positive input end has 4 independent selection switches and the negative input end has 6 independent selection switches Built in 10pF capacitor It can serve as comparator with the function of a chopper Built in peak pulse digital low pass filter 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page197 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash TECHNOLOGY rae PT3IE 7 m SS OPO 4 5 9 DAO 028207 6 OPDEN O 3 OPDFR O OPDR O OPOS 0 AIO6 7 OPODJ O AlO5 9ENS DAO 22 2_ _ OPCS 0 Re 9285 7 10 VSS AIO2 9PNSBL 77 FIG 23 1 OPAMP function block diagram 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page198 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 23 1 1 Input channel independent selection switch The input
229. onmental temperature is 0 K the output voltage of the temperature sensor is V tps 0 k OV The asymmetry between the offset voltage VADC OFFSET of the ADC and the BUT can be automatically cancelled by the measuring The temperature calibration only needs single point calibration to satisfy the 2 error VDDA FIG 22 4 Temperature sensor application block diagram The TPS initialization configuration and calculation method are as follows Enable the ADC and the function of the TPS can be automatically enabled right away Fix the related configuration of the ADC and the system operating frequencies and the configurations for the TPS calibration and measurement should be the same with each other When it is under the same temperature Ta C and the values of the VTSHO VTSLO and VTSH1 VTSL1 are measured add the two values and calculate the average to obtain the corresponding voltage VTS Ta of the TPS under the temperature Ta When measuring the VTSHO VTSLO set the INxP 3 0 as 0111 and set the INxN 3 0 as 0110 When measuring the VTSH1 VTSL1 set the INxP 3 0 as 0110 and set the INxN 3 0 as 0111 Calculate the 2 s complement of the VTSH1 VTSL1 add which to the values of the VTSHO VTSLO and then divide which by 2 to obtain the VIS Ta The variation of the output voltage VTS of the TPS to the temperature is a linear curve 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page18
230. ontrol Bit 01 CFRST 0 Reset Level reset 1 Enable ADC enable control Bit 00 ENADCO Disable 1 Enable 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page189 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 22 3 2 Analog ADC register ADCCR1 ADC Base Address 0x04 0 41104 Symbol VADO Control 1 Name Reg DESEE 12 71 ADGN RW 1 RwO RWO gt Bit Name Description DC zero point translation input voltage selection VREF REFP REFN 0000 0 VREF 0001 1 8 VREF 0010 1 4 VREF 0011 3 8 VREF 0100 1 2 VREF 0101 5 8 VREF 0110 3 4 VREF Bit 27 24 DCSET 0111 7 8 VREF 1000 0 VREF 1001 1 8 VREF 1010 1 4 VREF 1011 3 8 VREF 1100 1 2 VREF 1101 5 8 VREF 1110 3 4 VREF 1111 7 8 ADC input signal magnifying power Gain adjustor configuration 00 Gain 1 Bit 21 20 ADGN 01 Gain 2 10 Reserved 11 Gain 4 Reference voltage range selection Bit 19 0 Full reference voltage input it is VREF 1 1 1 2 reference voltage input VREF 1 2 Bit 18 16 PGA ADC input signal magnifying power PGA adjustor configuration 000 Gain 1 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page190 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU 64 KB Flash
231. ormally Bit 2 0 VLCD VLCDmode VLCDmode 00000000000 Pump is disabled VLCD R NN MS Type rem Pump is disabled VLCD R is enabled Data1 00 011 3 43V Charge Pump is enabled VLCD R is disabled 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page298 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash Vicodin Disable Charge Pump is disabled E VLCD R is disabled VLCD buffer is disabled Disable Charge Pump is disabled VLCD R is disabled VLCD buffer is disabled Data bit1 0X41F24 EN Rshift1 EN Rshift0 0OX41BOO VLCD2 VLCD1 VLCDO 32 4 2 LCD register LCDCR1 LCD Base Address 0x04 0x41B04 LCDCR1 LCD Control Register 1 31 24 23 16 9 RX 0 15 8 7 0 PT7LEn PT6LEn RX 0 Bit Name Description PT9 x mode selection Bit 31 24 PT9LEn CNN O mode 1 LCD mode PT6 x mode selection Bit 7 0 PT6LEn NUS mode 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page299 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash LCD register LCDCR2 LCD Base Address 0x08 0x41B08 LCDCR2 LCD Control Register 2 i EA 16 Name Name X COMEn PHM En o o RWJ 0 B 21 COMER Bii PTIOLENO Ome LCD register LCDCR3 LCD
232. oth 02h TMBIF lt Clear by user FIG 10 4 Schematic view of counting waveform of counting method 2 TMB calculation method 3 When TBM 1 0 211 the TMB will perform incremental counting and the TBR is separated into two counters TBR 15 8 and TBR 7 0 and both of them are under incremental counting mode The overflow value of the TBR 7 0 is controlled by the TBCO 7 0 and the overflow value of the TBR 7 0 is controlled by TBCO 7 0 TBR 7 0 will be automatically added by 1 at each rising edge of the TBCLK if the TBR 7 0 is equal to the TBCO 7 0 the TBR will become 0 at the next rising edge of the TBCLK besides the TMBIF will become 1 and the 15 8 will be automatically added by 1 At this time if the TMB interrupt function and the global interrupt enable function are enabled the chip will reply to the TMB interrupt The schematic view of the counting waveform of the mode is as shown in the following figure www hycontek com page74 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY In the mode the calculation method of the counting cycle of the interrupt method of the mode is T TBCO 7 0 TMCD HS CK or LS CK TBCO 7 0 Oh time 1 1 1 1 TBR 15 8 gt Mode 11 time TBCLK TBR
233. plication circuit system 209 24 VAMSOLNUITSU C 210 24 1 description aaisa eaaa aa aE EAE 210 24 2 211 24 3 tars 212 244 Modell program flow eret cena eaa Ran a d 213 24 5 213 24 6 Model program description 9 9 214 24 7 DAC application circuit e eee 215 24 8 DAC application 215 25 MULTIPLE FUNCTION COMPARATOR 216 25 1 Overall GOSCHPUUON t uode 216 25 2 Register address eee eee a hi 221 29 3 teile 221 25 4 Model program 225 255 225 25 6 Model program descriptiOD ccs rnaen se
234. ption Rx register update flag Bi 2 2 Nemea m The reception RX register is updated the reception register cannot 1 be read now SPI bus data over length flag ovr 2 The length of the received data length is higher than the set data 1 length BL 4 0 writing in 0 can clear the OVF flag SPI bus data insufficient length flag Bi o 9 Normal The length of the received data length is lower than the set data 1 length BL 4 0 writing in 0 can clear the flag SPI bus busy flag Bit 19 BUF 0 SPI bus interface space status 1 SPI bus interface busy status Data lost flag 0 Normal The reception register is full but still keeps receiving data the old data will be lost and reading the reception register can clear the bit Bit 18 TX transmission register full flag 0 TX transmission register is empty and can transmit data TX transmission register is full and keeping writing data in the register will overwrite old data Rx reception register full flag Bit 16 RxBF 0 RX reception register is empty 1 RX reception register is full reading the reception can clear the bit Bit 17 TxBF 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page233 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash airtel Clock phase configuration for the SPI bus capturing data Bit 3 0 Capture data at the first clock edge of the
235. put Data PT65DO 0 Output Low 1 Output High PT6 5 Input Data Bit 16 PT65DI 0 Input Low 1 Input High PT6 4 Output Enable Bit 3 64 0 Disable 1 Enable PT6 4 Input Enable Bit 2 PT64IE 0 Disable 1 Enable PT6 4 Output Data Bit 1 PT64DO 0 Output Low 1 Output High PT6 4 Input Data Bit 0 PT64DI 0 Input Low 1 Input High 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page129 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU 8 64 KB Flash When LCD Mode Base Address 0x58 0x40858 50 U I BI M iS El 0 SEG6 Data Bit Name Description LCD Segment 7 Data Segment Data LCD Segment 6 Data Segment Data Bit 21 16 SEG 7 Data Bit 5 0 SEG 6 Data 0 16 198 01 2014 HYCON Technology Corp page130 www hycontek com 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 16 3 4 PT6 6 PT6 7 register When GPIO Mode GPIO Base Address 0 5 0x4085C PTS7OEPTS7IE 67 67 Bt 501 7 68 4 B B n 0 Bit Name Description PT6 7 Output Enable Bit 19 PT67OE 0 Disable 1 Enable PT6 7 Input
236. put mode The output mode of the IO pin should be disabled before its input mode is enabled External interrupt input The PT1 has 8 IO pins and all of them can be reused as external interrupt input pins The mode should set the IO port to be the input mode and enable the internal pull up resistor lt is necessary to set the external interrupt trigger edge by the controller PT1XITT 2 0 and enable the control bit PT1ITD 0 to enable the interrupt trigger edge The controller PT1XIE 7 0 can enable the interrupt response function of the corresponding IO pin when the external interrupt signal generates the interrupt flag of the corresponding pin is set as 1 When the global interrupt GIE and the IO external interrupt function are enabled the chip will stop the current program right away and execute the IO external interrupt program 13 2 Register address GPIO Register Address 31 24 23 16 15 8 7 0 GPIO base address 0 00 0 40800 MASK1 PT1PU MASKO PT1OE GPIO base address 0x04 0x40804 MASK3 PT1IE MASK2 PT1DO GPIO base address 0x08 0x40808 PT1DI GPIO base address 0 0 0x4080C PT1IDF Reserved 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page108 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 13 3 Register function 13 3 1 PT1
237. r PT7xDI 0 If the IO is set as the input mode and the chip should be connected to the external pull up resistor and 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page133 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially the low power mode it is suggested the IO pin should be set as the input mode f it serves as the analog signal input port it is not necessary to set the corresponding IO pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled LCD mode The controller SEGx 5 0 determines the output data of the LCD SEGMENT If the LCD is under the 1 6 duty mode the SEGx 5 0 can determine the data content of the 1 6 duty data content if the LCD is under the 1 5 duty mode the SEGx 4 0 can determine the 1 5 duty data content if the LCD is under the 1 4 duty mode the SEGx 3 0 can determine the 1 4 duty data content if the LCD is under the 1 3 duty mode the SEGx 2 0 can determine the 1 3 duty data content 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page134 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 17 2 Register address GPIO Mode Register Address 31 24 23 16 15 8 7 0 GPIO Base Addr
238. r i inn ne inen esent nnne nnns 92 10 5 Model program function oot db ede eun 92 11 TIMER 2 95 11 1 Register 95 11 2 Register 95 12 A 99 12 1 Overall description itr itn 99 12 2 102 123 Register TunictlOn concen Re Na toa dk 102 124 Model program flow iade 104 12 5 Model program 105 12 6 Model program description 105 13 GPIO PT1 MANAGEMENT RR SCA 106 135 1 OVverall descriptiOn ett ater eR gen eun ne ena ea den and XR een Hd eund e AREE Ae CENE RR RARE 106 13 2 108 13 3 Register TulictiOnzs etie cie 109 13 4 Model program flow iiie eere ee eben ebat een endian adele 111 www hycontek com page4 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 13 5
239. rating modes the interrupt triggered items supported by the CPU are also different the following table shows the interrupt and wake up levels supported by each function Similarly different modes have different current consumption the current consumption from high to low is active mode gt wait mode gt idle mode gt sleep mode For instance the interrupt function of the I2C TX pin only supports the idle mode wait mode and active mode That is to say after the chip enters the sleep mode the chip cannot be wakened by the signals of the I2C TX pin to enter the interrupt For example after the chip enters the sleep mode only following actions and interrupts can make the chip leave the sleep mode Power On Reset Reset PIN 2 RX IRQ UART1 2 RX IRQ SPI RX IRQ CMP IRQ PT1 IRQ and PT2 etc oos needed eren ResetPN v v hipReset 2014 Technology Corp UG HY16F198 V01 www hycontek com page293 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY UARTNZRXIRQ V PTE EDM 31 3 Register function SoC Status Base Address 0x04 0x40104 SoC Status Register it 31 24 23 16 Name ICE Configuration SoC Configuration Bit 1568 7 5 4 _ Name MASK Reg Fero Fers IDLE Fsiemie Fwoog Frsr lt 2 x lt m m V V 20 x m 0 m y
240. re mode under the slave mode It needs to use the CS signal of the CSO bit analog SPI bus use the CSO CS signal to simulate and should be similar to the standard 4 wire mode 26 3 3 SPI register 2 Bit Name it 15 0 ame RXB15 0 Bit Name Description Bit 31 0 SPIRB SPIRB 31 0 is the 32 bit reception register Use the LBF bit to set whether the LSB or MSB is transmitted first If the LSB is set to be transmitted first the position where the data are stored will be influenced and the RXB effective data will be right justified For example if the BL is set to be under the 8 bit mode the received data will be stored at the RXB 7 0 if the BL is set to be under the 9 bit mode the received data will be stored at the RXB 8 0 and so on If the MSB is set to be transmitted first the RXB effective data will be left justified For example if the BL is set to be under the 8 bit mode the received data will be stored at the RXB 31 24 if the BL is set to be under the 9 bit mode the received data will be stored at the RXB 31 23 and so on 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page237 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 26 3 4 SPI register 3 Bit Name it 15 0 TXB15 0 Bit Name Description Bit 31 0 SPITB SPITB 31 0 is the 32 bit transmission register Use the LBF bit to set whether the LSB
241. register PT1CRO GPIO Base Address 0x00 0 40800 Symbol PT1CRO PT1 Control Register O 31 24 23 22 21 20 19 18 16 MASK PT1PU7 PT1PU6 PT1PU5 PT1PU4 PT1PU3 PT1PU2 PT1PU1 PT1PU0 0 RW ROW 0 RW 5 08 7 6 5 M 3 2 m 0 MASK 1 7 1 6 1 1 4 1 1 2 1 1 1 ROW 0 Bit Name Description Port 1 internal pull up control Bit23 16 PT1PU Disable the internal pull up 1 Enable the internal pull up Port 1 PAD output mode enable control Bit 07 00 O Disable the output mode 1 Enable the output mode 13 3 2 PT1 register PT1CR1 GPIO Base Address 0x04 0x40804 Symbol PT1CR1 PT1 Control Register 1 PTACRA PT1 Control Register 000000 Bit 31 24 23 22 21 20 19 18 16 Name MASK 7 PT1IE6 PT1IE5 PT1IEA PT1IE3 PT1IE2 PT1IE1 PT1IEO Bit 11508 7 6 5 4 I3 2 m I0 Name MASK PT1DO7 PT1DO6PT1DO5 PT1DO4 PT1DO3 PT1DO2 PT1DO1 PT1DOO 2 7 RW ROW 0 RW 0 RW 0 Bit RW Bit Name Description Port 1 PAD input mode control Bit23 16 PT1IE 0 Disable the input mode 1 Enable the input mode Port 1 PAD output status value Bit 07 00 PT1DO 0 Output low potential 1 Output high potential 13 3 3 PT1 register PT1CR2 2014 HYC
242. res The 2 bus clock wire poen control is overtimed m E cues I2CLK 64 6 TOPS I2CLK 8 010 CLKPS I2CLK 4 001 5 I2CLK 2 THIS I2CLK 1 Bit 3 0 TOLimit 29 4 3 2 register 3 Slave IDO SIDO 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page268 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 2 Base Address OxOC 0 4100 ymbol 2 I2C Control Register 3 Bt 159 O SID1 MASK Bit 31 24 SID1 i 1 Enable NE MASK 23 16 120 Disable Bifl5 9 501 the bit should be 1 when writing in the address code Bit 08 Valid1 0 Fhe slave address code is invalid _ 100 slave address code configuration 7 1 500 0 Slave address code valid control bit the bit should be 1 when writing in the address code Bit 00 ValidO slave address code is invalid 1 The slave address code is valid 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page269 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 29 4 4 2 register 4 2 Base Address 0x10 0x41010 I2CCRA I2C Control Register 4 31 16 RSV i 15 8 7 1 Rx 7 1
243. resistor PS When 2 4 2 7 serve as the external crystal oscillator input pins the internal pull up resistor cannot be enabled or the crystal oscillator cannot work normally Output mode The controller PT2OE 7 0 can enable or disable the output mode of each IO port and 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page113 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the output mode of the corresponding port will be enabled if it is set as 0 the output mode of the corresponding IO port will be disabled The control bit PT2DO 7 0 can determine whether the output status of the pin of the corresponding IO port is 1 or O Under the low power mode if the IO should enable the output mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled PS When the PT2 4 PT2 7 serve as the external crystal oscillator input pins the output mode should be disabled Input mode The controller PT21E 7 0 can enable or disable the input mode of each IO port
244. resolution conversion performance of the A D converter SD18 When the internal voltage doubling circuit is used to generate the VLCD voltage source the Ben 0 buffer will be automatically enabled by the internal hardware circuit 32 3 Register address LCD Register Address 31 24 23 16 15 8 7 0 LCD Base Address 0x00 0 41 00 REGO Mask1 REG1 LCD Base Address 0x04 0x41B04 PT9LEn PT8LEn PT7LEn PT6LEn LCD Base Address 0x08 0x41B08 REG2 Reserved 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page297 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 32 4 Register function 32 4 1 Register LCDCRO LCD Base Address 0x00 0x41B00 Symbol LCDCRO LCD Control Register 2 31 24 23 21 IDE Rw Rowo f _ B4 H Pu ON Idle control flag Bit 20 ue ATI mode Normal mode Bit 17 16 D The LCD is turned on no matter what the input is The LCD is turned off no matter what the input is Normal mode IDF Flip Reverse the order between COM and SEG Noma SSCS LCD operating period selection O O Duy Ol Duy VLCD buffer control Bit 3 en Disable Disable Enable it should be enabled and the functions of the LCD be used n
245. rite Data Byte 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 OXOF55 MASK Byte 1190 1 0 0 1 0 1 oxas FIG 3 3 Data flow structure 3 6 Boot ROM 8Kbyte Boot ROM is provided and the initial value is from 0x80000 to Ox81FFF www hycontek com page19 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY blocks are for boot codes flash codes and security codes When the chip is reset the program timer will start from 0 80000 The software of the Boot ROM includes many information such as system program protocol security protocol and the like www hycontek com page20 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 3 7 Embedded debug module EDM The embedded debug module EDM is a debug interface which can be used by the chip in the development environment When the chip has no security protection the user can transmit instructions to the MCU via EDM interface to read the information of the debug mode EDM is the bridge of the communication between the chip and the computer The PC USB and the chip EDM are connected via HY Protocol USB control board by only using a two wire protocol interface EDM can access the control register general GPR register SRAM DLM and Flash ROM ILM of a chip PC NB Tablet AndeSight HY 16F 19x GCC 3
246. rupt flag Return to the main program 25 5 Model program function Model name CMP usage method description By means of proper CMP register and IO settings Connect the CH3 PT1 2 to the positive end of the CMP Connect the CH2 PT1 1 to the negative end of the CMP HYGON HYCON TECHNOLOGY If the positive voltage of the CH3 is higher than the negative voltage of the CH2 the digital output of the CMPO is high If the positive voltage of the CH3 is lower than the negative voltage of the CH2 the digital output of the CMPO is low 2014 HYCON Technology Corp www hycontek com 0 16 198 01 TC page225 16 19 HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash CPCLS 2 0 H x cess ra Ew CPDA 3 2 1 CPDA 0 foie d Non overlap TBCK E J Clock Gen oon 1 2111 SE CPDA 3 0 0 CPRL OdNW2 CPPS 1 0 25 6 Model program description 00 01 include HY16F19X h 02 03 lint main void 04 05 DrvGPIO Open E PT1 0x80 E IO OUTPUT 1 7 set Output 06 DrvCMP Pinput 2 positive input CH3 07 DrvCMP Ninput 1 negative input CH2 08 09 DrvCMP Enable enable 10 Drv
247. s The standard 2 serial interface includes the SDA and the SCL with two pins The pin has the open type open drain output structure which needs the external pull up resistor to ensure the high level output The standard 2 serial interface is be set to be under the master mode slave mode or the master slave mode The programmable clock is allowed to adjust the transmission rate of the I2C The data are bi directionally transmitted between the master and the slave The 2 allows large operating voltage range The reference design of the I2C uses 7 bit length address space but reserves 16 address to deal with a group of buses and the communication between up to 112 nodes 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page256 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash z VDD3V 2 Wire Device Pull Up Resistor Sensor HY16F19X LCD Driver HY2613 EEPROM 24 02 Master Device All Slave Device FIG 29 2 12C bus device hooking diagram 29 2 Communication 2 interface signal Start signal START Under the master mode the SCL is high potential The SDA sent from high potential to low potential to enable the data transmission DATA and ADDRESS signals 2 serial interface protocol is only needed when the SCL is low potential The SDA can be changed only according to the dat
248. s When it is used as OP amplifier the voltage of the VDDA is higher than 2 4V and the reference voltage of the BandGap should be enabled in advance Within the effective input range the OPAMP is Rail to Rail However in order to achieve better performance it is suggested that the input common mode voltage range is between VSS 0 1V VDDA 0 1V The input impedance of the OPAMP is higher than 160 Initialization configuration Enable the reference voltages of the VDDA and BandGap the voltage of the VDDA should be higher than 2 4V and wait until the voltages are stable Select the output pins of the OPO1 OPO2 and set the corresponding IO pins as the input mode is not necessary to set the above configuration if the above function is not used Select the positive input channel negative input channel according to the actual applications Set the 2us low pass filter and enable or disable it according to the actual requirements Set the clock frequency of the charge pump and determine whether it is multified by the frequency or not Enable the analog output of the OPAMP which means enabling the OPOE Enable the digital output of the OPAMP according to the actual requirements which means enabling the OPDEN If the digital output of the OPAMP is enabled the output result should be set to be opposite in phase or not according to the actual requirements which means setting the OPDR Enable the OPAMP to enable the OP amplifier which means enabli
249. s as follows ASI PGA x ADGN x ASI DCSET x AVREF Equation 18 3 DCSET 3 0 2 0000 0001 0010 0011 0100 0101 0110 0111 Translation 18 14 3 8 1 2 58 43 47 8 Value VREF VREF VREF VREF VREF VREF VREF Ride 1000 1001 1010 1011 1100 1101 1110 1111 Translation 178 44 38 4 9 58 34 8 valine VREF VREF VREF VREF VREF VREF VREF Table 22 5 Zero bias configuration conversion table of input signal to be measured 22 1 5 Comb filter adopts the 3 stage comb filter and different over sampling rates can be obtained by setting the controller OSR 3 0 and the different combinations of the sampling rates of the ADC so as to realize different ADC conversion output frequencies The configuration parameters of the OSR 3 0 are as follows OSR 3 0 Setting 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 value Frequency 32768 16384 8192 4096 2048 1024 512 276 128 64 32 dividing value 2014 HYCON Technology Corp www hycontek com UG HY16F198 VO1 page183 HY16F19 series user manual 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash HYGON Table 22 6 Frequency dividing table of over sampling rates The A D conversion results are stored in the r
250. s place of the minute BCD code format 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid Bit 19 16 1MIN gt O The tens place of the second BCD code format 000 0 001 010 Bit 6 4 10SEC 011 100 101 110 111 Invalid The one s place of the second BCD code format 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid Bit 3 0 15 30 3 5 2014 Technology Corp UG HY16F198 VO1 www hycontek com page283 16 19 series user manual HYGON 21 bit ENOB 32 bit MCU amp 64 KB Flash Base Address 0 10 0x41A10 Symbol RTCYMC RTC Year and Month Control Register For Calendar 31 24 23 20 19 16 MASK 10YEAR 1YEAR RW 2 15 o 07 05 04 03 00 MASK mo 1MO RW ROWO RW 1 Bit Name Description The tens place of the year BCD code format 0000 0 0001 1 0010 2 0011 3 0100 4 Bit 23 20 10YEAR 0101 5 0110 6 0111 7 1000 8 1001 9 Other values Invalid The one s place of the year BCD code format 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Other values Invalid Bit 19 16 1YEAR
251. s transmitting or receiving data it is high potential 1 Under the master mode when the SPI starts to transmit data it is high potential 1 Once the SPI stops transmitting data or transmission is finished it will be cleared automatically Under the slave mode when the SPI is ready to communicate with the master device it is 1 Once the SPI stops transmitting data or transmission is finished it will be cleared automatically Flag 1 SPITIF the flag SPITIF is the transmission interrupt of the When the write in register is loaded into the shift register it is set as 1 2 SPIRIF the SPIRIF is the reception interrupt of the When the shift register is loaded into the read register it is set as 1 26 2 Register address SPI Register Address 31 24 23 16 15 8 7 0 SPI Base Address 0 00 0 40 00 SPIC2M SPIC2 SPIC1M SPIC1 SPI Base Address 0x04 0x40F04 SPICOM SPICO BL SPI Base Address 0x08 0x40F08 RXB3 RXB2 RXB1 RXBO SPI Base Address 0x0C 0x40F0C TXB3 TXB2 TXB1 TXBO 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page232 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 26 3 Register function 26 3 1 SPI register 0 SPI Base Address 0x00 0x40F00 SPICRO SPI Control Register 0 19 18 16 RO O Bit Description Rece
252. serves as the analog signal input port it is not necessary to set the corresponding IO pin as the input mode The output mode of the IO pin should be disabled before its input mode is enabled 15 2 Register address GPIO Register Address 31 24 23 16 15 8 7 0 Base Address 0 20 0 40820 5 1 MASKO PTSOE GPIO Base Address 0x24 0x40824 PTSIE MASK2 PT3DO GPIO Base Address 0x28 0x40828 REG4 PT3DI Reserved 15 3 Register function 15 3 1 PT3 register PT3CRO GPIO Base Address 0x20 0x40820 PT3CRO PT3 Control Register O Name PT3PU4 PT3PUO 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page120 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash ROW 0 Bit 15 08 7 6 5 4 3 2 1 0 MASK 4 PT3OE2 1 ROW 0 RW 0 Bit Description Port 3 internal pull up enable control Bit 23 16 PT3PU Disable the internal pull up 1 Enable the internal pull up Port 3 PAD output mode enable control 7 0 PT30E 0 Disable the output mode 1 Enable the output mode 15 3 2 PT3 register PT3CR1 GPIO Base Address 0x24 0x40824 PT3CR1 PT3 Control Register 1 Bit 3124 23 22 21 20 19
253. t end Both of the positive input end and negative input end respectively have two external input channels and two internal input channels The positive input end can only select one input channel at a time and the negative input end can only select one input channel at a time The reference voltage end further has a short circuit switch and the short circuit switch can be enabled or disabled by the control bit VRSHR to achieve the short circuit between the positive input end and the negative input end The reference voltage can be generated after the AVREF voltage difference generated after the inputs from the VREFP and VREFN and then pass the programmable reference voltage attenuator The attenuation power of the reference voltage can be set by the controller FRb 0 and the attenuation power of the reference voltage is as shown the 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page181 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY following table The calculation of the reference voltage is as follows AVREF VREFP VREFN Equation 22 1 VREF Gain x AVREF Equation 22 2 AVREF the voltage difference of the reference voltage VREF the internal reference voltage of the ADC VREFP VREFN input reference voltage VRPS 1 0 VRNS 1 0 FIG 18 3 Reference voltage input channel Reference voltage attenuation power 0
254. ta byte will be received NACK will be transmitted ACK will be transmitted STA 98h SPIA 0010b Data byte has been received NACK has been transmitted STA 9Ch SPIA 0010b Data byte has been received ACK has been transmitted SPIA 1000 A repeated START will be transmitted D x 0010b STA 30h SPIA 0000b STA 31h SPIA 0000b Heise UST A STOP has been transmitted A STOP has been transmitted transmitted SPIA 0000 Slave will be transmitted PU SPIA 00106 rbitration lost wW To Master Transmitter B SPIA 1100 A STOP followed by a START will be transmitted SPIA 0100 A STOP will be transmitted SPIA 0000 SPIA 1000 Idle or Slave Mode will be A START will be transmitted entered when the bus becomes free To Slave Mode FIG 29 5 Master Receiver Mode 29 2 4 12C Slaver TX flow 2014 HYCON Technology Corp UG HY16F198 V01_TC www hycontek com page261 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash Slave Mode Enable STA 54h SPIA 0010b Own slave A R has been received ACK has been transmitted STA 55h SPIA 0010b Arbitration lost as master Own slave A R has been received NACK has been transmitted SPIA 0000 Data byte will be transmitted STA 58h SPIA 0010b STA 5Ch SPIA 0010b Data byte has been
255. tae 226 25 1 CMP application circuit losies innean re RR Y Roe NE REPRE RR EN A aa 227 25 8 application 1 227 26 SERIAL PERIPHERAL INTERFACE 5 228 www hycontek com page 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 26 1 Overall description isi 228 20 2 Register address o ode o e p aie GR EUR E Pea Aue 232 26 3 Register 233 20 4 Modelprogram flow icc oed tad vue ccv v uad dde 239 26 5 Modell program f bictiO ceret ene et reor n EEA nne Rd Ee TA 239 26 6 Model program 241 27 ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMIT EUART 244 27 1 GOSCHPUUON err ee 244 27 2 Register address eet nr enn eet T eet eade 245 Cni 245 28 ENHANCED UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMIT EUART2
256. ter the Bit15 8 are Mask when reading the register the Bit11 10 are general registers Name Description UART2 transmits TX interrupt enable control Bit 19 UZTME O Disable UART2 receives RX interrupt enable control Bit 18 U2RME O Disable UART Tx interrupt request Bitty UTR o Noma O O Interrupt ART interrupt request Bi 10 TRxIR 0 Normal 1 Interrupt UART transmits TX interrupt flag level trigger Bit 03 UTXIF Normal UART transmission TX interrupt occurs UART receives RX interrupt flag level trigger URXIF UART reception RX interrupt occurs www hycontek com page53 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY 7 3 8 Interrupt control register INTTMB2 INT Base Address 0x1C 0x4001C 5 mbol N LIMBA Interrupt cont Register 7 BE ROW 0 RWO Bit 1510 9g m MASK Name TMB2IR pRW 0 1 gt RWO When writing the register the Bit15 8 are Mask when reading the register the Bit9 is general register _ Bit Name Description Timer B2 interrupt enable control Bi 17 TMB2IE 0 Disable a Emse oo Timer B2 interrupt request Bit 9 TMB2IR 0 0 Normal 2 Interrupt Timer B2 interrupt flag level trigger Bit 1 TMB2IF 0 Normal mur transmission interrupt occurs 7 4 Model program flow 1 Dr
257. the control bit OPCS 0 There are two methods to sample the analog inputs One is the open loop sampling technique and the method requires the analog signals are inputted from the AIO or AIO 5 The configuration of the channel switch is as follows first set the OPNS 5 as 1 and set the OPCS 0 as 1 then set the OPNS 0 1 select the or set the OPNS 1 1 select the AlO5 after the sampling is finished ser the OPNS 5 0 the voltage data are stored in the capacitor corresponding to the VSS The other one is the close loop sampling technique the method should enable the OPAMP first which means setting the ENOP 1 then enable the OPOI and OPO which means setting the OPNS 4 1 and 3 1 afterward the lower end of the capacitor is connected to the OPOI which means the OPCS 1 enable the AlO2 and AIO 4 which means setting the OPPS 0 1 and OPPS 1 1 after the sampling is finished disable the OPOC which means setting the 5 0 the voltage data are also stored in the capacitor corresponding to the VSS close loop method can store the offset of the OPAMP in 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page199 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash the capacitor Additionally if the applications have the sensors with very high output impedance the close loop sampling technique is a better choice F
258. thod selection Send out the interrupt when the Tx Data Buffer is idle 0 and the interrupt disappears after the data are written in Bit 3 RxIT Bit 1 TxIT 1 Sent out the interrupt after one piece of data is transmitted by the Tx UART Tx control switch TxEn 0 Disable 1 Enable 23 3 2 UART register 1 UART Base Address 0x04 0 40 04 UARTCR1 UART Control Register 1 Bit 31 16 RSV 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page246 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash ieri Bit 508 B m 0 RxABDF RXWUEn PrtODD Rw eR Bit Name Description Automatic baud rate detection switch Bit 4 RXABDF 0 Disable 1 Enable Automatic baud rate detection error flag 0 Normal 1 Error occurs Automatic wake up mode Bit 2 RxWUEn 0 Disable 1 Enable Parity check switch Bit 1 PrtEn 0 Disable 1 Enable Select the odd parity check even parity check Bit 0 PrtODD Even parity check 1 Odd parity check 27 3 2 UART register 2 UART Base Address 0x08 0x40E08 Nam 7 i ame RW X Bit Name Description Bit 15 0 Baud Rate UART baud rate setting 2014 HYCON Technology Corp UG HY16F198 VO1 www hycontek com page247 16 19 seri
259. tion 00000 8 bits length 00001 16 bits length 00010 24 bits length 00011 4 bits length 00100 5 bits length 00101 6 bits length 00110 7 bits length 00111 8 bits length 01000 9bits length 01001 10 bits length 01010 11 bits length 01011 12 bits length 01100 13 bits length 01101 14 bits length 01110 15 bits length Bit 4 0 SPIBL 01111 16 bits length 10000 17 bits length 10001 18 bits length 10010 19 bits length 10011 20 bits length 10100 21 bits length 10101 22 bits length 10110 23 bits length 10111 24 bits length 11000 27 bits length 11001 26 bits length 11010 27 bits length 11011 28 bits length 11100 29 bits length 11101 30 bits length 11110 31 bits length 11111 32 bits length When the MD is set as the 3 wire mode the original CS pin will become the GPIO mode You can use the random wave type to generate the desired signal or used in other 2014 HYCON Technology Corp UG HY16F198 V01 www hycontek com page235 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash applications but you still need to use the CS SPIC interface as the synchronous signal 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page236 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash 3 mode under the master mode No any special treatment for the internal synchronous circuit The 3 wi
260. to execute the high level interrupt service the high level interrupt request can be executed only after the current interrupt vector service is finished After the interrupt service program is finished it will automatically return to the program address where the interrupt occurred and continuously execute the program The corresponding interrupt vector program entry addresses of the interrupts of the chip are as shown in the following table Interrupt Vector Address Vector Interrupt Function INT Base Address 0x00 I2C UART SPI HWO void HWO ISR void communication interfaces INT Base Address 0x04 Timer WDT HW HW1 void HW1 ISR void INT Base Address 0x08 ADC HW2 void HW2 ISR void INT Base Address 0 CMP OPA HW3 void HW3 ISR void INT Base Address 0 10 PT1 4 void 4 ISR void INT Base Address 0 14 2 HW5 void HW5 ISR void INT Base Address 0x18 Software Interrupt HW6 void HW6 ISR void INT Base Address Ox1C UART2 HW7 void HW7 ISR void INT Base Address 0x20 TMB2 HW8 void HW8_ISR void 7 2 Register address Interrupt Register Address 31 24 23 16 15 8 7 0 INT Base Address 0x00 COM 0x40000 MASKO REGO MASK1 REG1 INT Base Address 0x04 TMR 0x40004 MASK2 REG2 MASK3 REG3 INT Base Address 0x08 ADC 0x40008 MASK4 REG4 MASK5 REG5 INT Base Address 0 0 CMP 0
261. ual 21 bit ENOB XAADC 32 bit MCU amp 64 KB Flash HYG N HYCON TECHNOLOGY 27 outw 0x40000 0 08000800 int_00 28 29 a inw 0x40000 amp 0x04 amp amp inw 0x40000 amp 0 040000 RX interrupt 30 31 32 temp inw 0x40e0c amp Oxff RX get Buffer 33 outw 0x40000 0 04040400 int 00 34 35 36 asm volatile sethi r0 0 0000 37 asm volatile ori 0 r0 Ox003f 38 asm volatile mtsr r0 INT MASK 39 asm volatile movi r0 0 70009 40 asm volatile mtsr r0 PSW 41 2014 HYCON Technology Corp www hycontek com 0 16 198 01 255 16 19 series user manual HYGON 21 bit ENOB XAADC gt 32 bit MCU amp 64 KB Flash 29 12C COMMUNICATION INTERFACE 29 1 Overall description Communication interface 2 serial communication major classes 2 serial interface Cross integrated circuit serial interface 2 communication interface has two operating modes including the master mode and the slave mode SCL H SDA Master Slave TX Ctrl I2CEN 0 TOPS 2 0 Pre scale Clock Time out APCK 1 2 4 Register Ctrl 128 Intetnal System Bus FIG 29 1 2 communication structure diagram 29 1 1 Communication I2C interface feature
262. ut mode the output status can be set according to the peripheral circuit to decrease the power consumption of the chip During the mode the internal pull up resistor of the IO cannot be enabled and the input mode and the output mode cannot be enabled at the same time therefore when the output mode is enabled the input mode of the IO port should be disabled 2014 HYCON Technology Corp UG HY16F198 V01 TC www hycontek com page107 16 19 series user manual HYGON 21 bit ZAADC 32 bit MCU 8 64 KB Flash Input mode The controller PT1IE 7 0 can enable or disable the input mode of each IO port and each bit is corresponding to each IO port pin If the corresponding bit of the IO port is set as 1 the input mode of the corresponding IO port will be enabled if it is set as 0 the input mode of the corresponding IO port will be disabled The control bit PT1DI 7 0 can determine whether the input status of the pin of the corresponding IO port is 1 orO If the is set as the input mode and the chip is not connected to the external pull up resistor the internal pull up resistor should be enabled the IO pin is not allowed to be floating in order to prevent from the electric leakage of the chip Especially in the low power mode it is suggested the IO pin should be set as the input mode If it serves as the analog signal input port it is not necessary to set the corresponding IO pin as the in
263. vTIMER Enablelnt X means enable the Timer system interrupt 2 DrvTIMER ClearlntFlag x means clear the Timer system interrupt flag 3 Timer A B C WDT belong to the HW1 interrupt and the format is void HW1 ISR void www hycontek com page54 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY fest PHA The program starts Initialization settings Interrupt settings Wait for interrupt Interrupt the subprogram Clear the interrupt flag Return to the main program www hycontek com 55 HY16F19 series user manual 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash 7 5 Model program function Model name the interrupt usage instruction and description Model description use the WDT interrupt service 7 6 Model program description HYG N HYCON TECHNOLOGY 00 01 include HY16F19X h 02 03 unsigned int i 04 05 main void 06 07 0 05 08 DrvGPIO Open E 2 0 IO OUTPUT 2 0 3 Set Output 09 DrvGPIO SetPortBits E PT2 i PT2 Output 0 05 10 11 DrvWDT Open E PRE SCALER D32 WDT IRQ open prescaler 32 12 13 DrvWDT ClearwDT Clear WDT interrupt flag 14 DrvTIMER Enablelnt E WDT
264. west speed 1000 0000 is the default speed 1111 1111 is the higher speed 6 3 3 Clock system register CLKCR2 Clock Base Address 0x08 0x40308 CLK2 Clock Control Register 2 MASK TUCKS ROW 0 RWO RW 0 15 08 7 6 54 3 2 I 0 MASK TMCKS ENTD TMCD TACKS ENTAD MCUCKS ROW 0 Bit Name Description RTC clock source control Bit 23 ENRTCK 0 Disable The RTC register cannot be written in and unlocked 1 Enable The RTC register can be unlocked EUART clock source selection Bit 21 TUCKS 0 HSXT External high speed oscillator 1 HSRC Internal high speed oscillator EUART clock source enablement control Bit 20 ENUD 0 Disable 1 Enable www hycontek com page36 16 19 series user manual HYGON 21 bit ENOB ZAADC gt 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY Bit 19 16 Bit 07 Bit 06 Bit 5 4 Bit 03 Bit 02 Bit 01 Bit 00 UACD TMCKS ENTD TMCD TACKS ENTAD ENMCD 2014 HYCON Technology Corp www hycontek com EUART clock source frequency divider configuration 0000 EUART clock source 1 0001 EUART clock source 2 0010 EUART clock source 4 0011 EUART clock source 8 0100 EUART clock source 16 0101 EUART clock source 32 0110 EUART clock source 64 0111 EUART clock source 128 1000 1111 Reserved Timer B C clock source selection 0
265. will generate the interrupt signal when the counting flow takes place and the program can read the current counting value of the TMB besides the TMB be also used to generate the waveform of the PWM lIt can be operated under the operation mode and the IDEL mode The 16 bit counter register of the Timer B can be separated into two independent 8 bit counter registers thus the TMB has four counting methods 16 bit up counting method which can generate the interrupt signal 16 bit counting method it will increase to the overflow value and then decrease to 0 which can generate the interrupt signal Two independent 8 bit up counting methods the low 8 bit counter overflows and then the high 8 bit counter is automatically added by 1 which can generate the interrupt signal Moreover the TMB has three counter overflow controller TBCO TBC1 and TBC2 TMB can also serve as the PWM waveform generator which can provide two PWM waveforms PWMO PWM 1 and each has multiple operation modes and can satisfy different PWM output requirements the operation modes are as follows PWMA PWMB PWMC PWMD PWME PWMF PWMG www hycontek com page67 16 19 series user manual HYGON 21 bit ENOB ZAADC 32 bit MCU amp 64 KB Flash HYCON TECHNOLOGY UE ee 2 0 TMB M Interrupt TBM 1 0 O1MD 2 0 PTPW 2 0 TBM 00 TBM 01 TBM 10 TBM 11 cPHMS to 7777 pe Logic High PME CMPO 01 M

HY16F19 Series User manual

Contents

Download Pdf Manuals

Related Search

Related Contents