to this file: /sn820x_ds
Contents
1. SN820XUFL Top and Side View FIGURE 2 1 SN820X and SN820XUFL Top and Side View 2014 by Murata Electronics N A Inc Page 8 of 42 SN820X R 3 0 8 22 14 www murata com 2 3 PCB Footprint top view 60 FIGURE 2 2 Detailed Pad Dimensions top view 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 9 of 42 www murata com 2 4 Pinouts TABLE 2 2 Pinouts Pin Name GND Description Ground 0SC32 IN Optional precision 32 768 KHz slow clock input No connect if not used OSC32 OUT No connect WIFI VDD EN No connect ADC3 General purpose I O or ADC3 ADC4 General purpose I O or ADC4 ADC5 General purpose I O or ADC5 VDD DC supply for MCU and I O ADC6 General purpose I O or ADC6 DAC2 General purpose I O or DAC2 DAC1 General purpose I O or DAC1 ADC1 General purpose O or ADC1 Reserved No connect Reserved No connect GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground VDD WIFI IN Wi Fi power supply Reserved No connect Reserved No connect Reserved No connect WIFI SLEEP CLK IN Optional precision 32 768 kHz Wi Fi2. 2014 by Murata Electronics N A Inc Page 37 of 42 SN820X R 3 0 8 22 14 www murata com 6 Regulatory Information The table below shows the regulatory compliance status of the SN820X Module family TABLE 6 1 Regulatory Compliance Regulatory Body Standard CFR Part 15 Certificate ID QPU8200 RSS 210 4523A SN8200 Compliant ANATEL Anatel Resolution NO 506 1322 14 8488 For more information refer to the SN820X Wi Fi Network Controller Module Family User Manual reference 3 on page 7 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 38 of 42 www murata com 7 Packing and Marking Information 7 1 Carrier Tape Dimensions la I 40 401 pa lt gt Y pr gt Le Y A Y kh Mpc KG Pe y y Mga oy FIGURE 7 1 SN820X 820XUFL Carrier Tape Dimensions 7 2 Module Marking Information The following marking information may be printed on a permanent label affixed to the module shield or permanently laser written into the module shield itself The 2D barcode is used for internal purposes A pin 1 ID is stamped into the shield The Model will vary according to the module used SN8200 SN8200UFL SN8205 SN8205UFL however the FCC ID and IC certification numbers apply to all modules in the SN820X Family Model SN8200 Lot No YYWW FCC ID QPU8200 IC 4523A SN8200 CEO FIGURE 7 2
3. Max frequency for a correct DAC_OUT change when small variation in the input code from code i to it1LSB CLoAD lt 50 pF Rj 0ap 25kO twaxeup o PSRR Wakeup time from off state Setting the ENx bit in the DAC Control register Power supply rejection ratio to VDDA static DC measurement CLoap 50 pF RLoap 2 5kQ input code between lowest and highest 40 dB No Rj pap Croan 50 pF 1 Guaranteed by design not tested in production 2 Preliminary values eee 2014 by Murata Electronics N A Inc Page 31 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 8 2 DAC Characteristic SN8205 8205UFL Parameter Analog supply voltage Comments Reference supply voltage Ground Resistive load with buffer ON Impedance output with buffer OFF When the buffer is OFF the Minimum resistive load between DAC OUT and VSS to have a 1 accuracy is 1 5 MQ Capacitive load Maximum capacitive load at DAC_OUT pin when the buffer is ON DAC_OUT min Lower DAC_OUT voltage with buffer ON DAC_OUT max Higher DAC OUT voltage with buffer ON It gives the maximum output excur sion of the DAC It corresponds to 12 bit input code Ox0E0 to 0xF1C at Vpep 3 6 V and 0x1C7 to 0xE38 at Va 1 8 V DAC_OUT min Lower DAC_OUT voltage with buffer OFF DAC_OUT max Higher DAC OUT voltage with bu
4. BIT1 OUT LSB OUT ty MO th MO gt FIGURE 3 5 SPI Timing Diagram Master Mode SN8200 8200UFL and SN8205 8205UFL Measurement points are done at CMOS levels 0 3Vpp and 0 7Vbp 3 7 12 Bit ADC Characteristics Unless otherwise specified the parameters given below are preliminary values derived from tests performed under ambient temperature fPCLK2 frequency and VDDA supply voltage conditions NOTE It is recommended to perform a calibration after each power up TABLE 3 7 1 ADC Characteristics SN8200 8200UFL Parameter Conditions Vopa Power supply 2 4 a 3 6 V Vrer Positive reference voltage 2 4 VDDA V lureF Current on the VREF input pin 160 2200 HA fapc ADC clock frequency 0 6 14 MHz f5 Sampling rate 0 05 1 MHz frio fanc 14 MHz 823 kHz External trigger frequency E 17 ano 0 Vssa OF Vper a VREF V VAIN Conversion voltage range 3 tied to ground Ran See Equation 1 a 50 External input impedance for details kQ 2014 by Murata Electronics N A Inc Page 23 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 7 1 ADC Characteristics SN8200 8200UFL R Apc Sampling switch resistance 1 kQ Cape Internal sample and hold 8 pF capacitor tcaL faoc 14 MHz 5 9 KS Calibration time 83 apa tat fanc 14 MHz 0 214 us Injection trigger conversion E 3 4 1 f latency bi Man that fanc
5. Slave mode after enable edge Master mode after enable edge 2 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 20 of 42 www murata com TABLE 3 6 2 SPI Characteristics SN8205 8205UFL Parameter Conditions fsck SPI1 master slave mode Vtusck SPI clock frequency SB 2 SP13 master slave mode tyscL SPI clock rise and fall Capacitive load C 30 pF tiso time fecix 30 MHZ SPI slave input clock Slave mode DuCy SCK duty cycle 30 tswnss 1 NSS setup time Slave mode 4tPCLK tinss 1 NSS hold time Slave mode 2tPCLK tuscui tl Master mode fecLk 3 MHz trcik 3 SCK high and low time presc 2 tum 1 Master mode Data input setup time Slave mode thm 1 Master mode Data input hold time Slave mode Data output access Slave mode fp x 30 MHz time Data output disable Slave mode time Data output valid time Slave mode after enable edge Data output valid time Master mode after enable edge Slave mode after enable edge Data output hold time Master mode after enable edge 1 Based on characterization not tested in production 2 Min time is for t
6. 25 C Gain error Integral linearity error Measurements made after 1 ADC DC accuracy values are measured after internal calibration 2 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is rec ommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current 3 Based on characterization not tested in production 2014 by Murata Electronics N A Inc Page 25 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 7 4 ADC Accuracy 2 3 SN8200 8200UFL Parameter Test conditions Max 4 Total unadjusted error Offset error fPCLK2 56 MHz fapc 14 MHz RAIN lt 10 KQ VDDA 2 4 V to 3 6 V Integral linearity error Measurements made after Gain error Differential linearity error 1 ADC DC accuracy values are measured after internal calibration 2 Better performance could be achieved in restricted VDD frequency VREF and temperature ranges 3 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input I
7. SN8205 8205UFL Cparasitic represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Cparasitic value downgrades conversion accuracy To remedy this fADC should be reduced 2014 by Murata Electronics N A Inc Page 29 of 42 SN820X R 3 0 8 22 14 www murata com 3 8 DAC Electrical Specifications TABLE 3 8 1 DAC Characteristics SN8200 8200UFL Parameter Analog supply voltage Comments Reference supply voltage Vper must always be below VDDA Ground Resistive load vs Vsga with buffer ON Resistive load vs Vppa with buffer ON Impedance output with buffer OFF When the buffer is OFF the Minimum resistive load between DAC_OUT and Vss to have a 1 accuracy is 1 5 MO 1 Croan Capacitive load Maximum capacitive load at DAC_OUT pin when the buffer is ON DAC_OUT min DAC_OUT max Lower DAC_OUT voltage with buffer ON Higher DAC_OUT voltage with buffer ON It gives the maximum output excursion of the DAC It corresponds to 12 bit input code Ox0E0 to OxF1C at Vpep 3 6 V and 0x155 and OxEAB at Vger 24V DAC_OUT Lower DAC_OUT voltage with min buffer OFF 0 5 mv DAC OUT Higher DAC OUT voltage Veepz 10 It gives the maximum output excursion of max with buffer OFF mV V the DAC DAC DC current consump With no load worst code 0x0E4 at paaa
8. TABLE 2 3 Signal Pinouts for SN820X 820XUFL STM32F103RF STM32F205RG pin PAO WKUP ADC123_0 USART2_CTS TIM2_CH1_ETR TIM5_CH1 TIM8_ETR PA1 ADC123_1 USART2_RTS TIM2 CH2 TIM5 CH2 PA2 ADC123 2 USART2 TX TIM2 CH3 TIM5 CH3 TIM9 CH1 PA3 ADC123 3 USART2 RX TIM2 CH4 TIM5 CH4 TIM9 CH2 PA4 ADC12 4 DAC1 USART2 CK SPI1 NSS ADC1 PAS ADC12 5 DAC2 SPI1 SCK PA7 ADC12_7 SPI1_MOSI UART_TX PA9 UART1_TX UART_RX PA10 UART1_RX UART_CTS PA11 UART1_CTS USB2_DM CAN_RX UART_RTS JTMS PA12 UART1_RTS USB2_DP CAN_TX PA13 JTMS SWIO JTDI SPI NSS PA15 JTDI SPI3_NSS 1253_WS JTCK PA14 JTCK SWCLK JTDO SPI SCK PB3 JTDO SPI3_SCK I2S3_CK JTRST SPI MISO PB4 JTRST SPI3_MISO SPI_MOSI PB5 I2C1_SMBA SPI3_MOSI 253_SD 12056L PB6 12C1_SCL TIM4 CH1 I2C SDA PB7 I2C1_SDA TIM4 CH2 ADC2 PA6 ADC12_6 SPI1_MISO 2014 by Murata Electronics N A Inc Page 12 of 42 SN820X R 3 0 8 22 14 www murata com 3 DC Electrical Specifications The I O pins from SN820X are based on the built in STM32 microcontroller The information shown in sections 3 2 through 3 8 is derived from the ST Microelectronics Data Sheet for user convenience For original information see reference 1 and 2 on page of References 3 1 Typical Power Consumption TABLE 3 1 1 SN8200 SN8200UFL and SN8205 SN8205 UFL Typical Power Consumption Condition Receive mode Tran
9. 28 dB dB 20 MHz to 30 MHz 28 dB to 45 dB dB 30 MHz to 33 MHz 45 dB dB 8 dB 0 Constellation Error EVM 2 Out of band spurious emissions 30 MHz to 1 GHz BW 100 kHz 96 dBm 1 GHz to 12 75 GHz BW 1 MHz 1 dBm 1 8 GHz to 1 9 GHz BW 1 MHz 65 dBm 85 dBm 5 15 GHZ to 5 3 GHz BW 1 MHz Received Minimum Sensitivity 65 Mbps PER s 10 Maximum input level PER s 1096 Adjacent channel rejection PER lt 10 Notes 1 Derate by 1 5 dB for temperatures less than 10 C or more than 55 C in both transmit and receive modes AAA SSS SSS SSS 2014 by Murata Electronics N A Inc Page 36 of 42 SN820X R 3 0 8 22 14 www murata com 5 Environmental Specifications 5 1 Absolute Maximum Rating TABLE 5 1 Absolute Maximum Rating Description Minimum Maximum Tsop Specification operating temperature Top Operating temperature Tst Storage temperature VDD Power supply VBAT Power supply for backup circuitry when VDD is not present VDD WiFi Wi Fi Power Supply RFin RF input power MSL Moisture Sensitivity Level 3 RoHS2 Restriction of Hazardous Substances Compliant Note RF performance may be degraded at extreme temperatures 5 2 Recommended Operating Conditions TABLE 5 2 Recommended Operating Conditions Supply Current Specification Minimum V Typical V Maximum V mA VDD VBAT VDD WiFi
10. Built in STM ARM Cortex M3 TABLE 1 1 SN820X WiFi Network Controller Module Family RAM Size Flash Size 768KB SN8200UFL 88 00151 02 ARM Cortex M3 768KB SN8205 88 00158 00 ARM Cortex M3 1024KB SN8205UFL 88 00158 02 e 2 4 GHz IEEE 802 11 b g n radio technology e Dimensions 30 5 x 19 4 x 2 8 mm ARM Cortex M3 e Antenna configurations On board antenna or U FL connector e Transmitter power 18 dBm 80211b e Receiver sensitivity 96 dBm e MCU ARM Cortex M3 e Serial Interface Options UART SPI e Peripheral Interface Options ADC DAC 12C 12S GPIO e Operating temperature range 40 C to 85 C e RoHS2 compliant e MSL Level 3 e FCCIIC certified and CE compliant e Compatible with Broadcom WICED SDK 1024KB 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 6 of 42 www murata com 1 3 Block Diagram VBAT VDD VDD WIFI IN UART SPI 12 125 ADC DAC GPIO for on board antenna version ANT Wi Fi SoC 802 11b g n D Cortex M3 LPF p SPDT for U FL connector version 32 KHz WIFI SLEEP y WIF y optional QS _CLK_IN optional FIGURE 1 1 SN820X Block Diagram Murata offers Serial to WiFi and EZ Web Wizzard software for SN820x in the SN820x EVK The modules are also compatible with Broadcom WICED SDK The customer can obtain the WICED SDK from Broadcom directly The modules are delivered
11. STA 0 tuso gt e tysDA 1 1 a Yo NG Nf twSCLH H e SDA p lg tg SDA n gt lw STO STA w e a ty SCL e gt tf SCL pg l51 STO 9i14149 FIGURE 3 1 SN8200 8200UFL I2C bus AC Waveforms and Measurement Circuit 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 18 of 42 www murata com STM32Fxx START NA SDA Pre He t SDA gt e lsu SDA gt ista je obiyscii ethsDa SCL Da ale SCL SCL FIGURE 3 2 SN8205 8205UFL I2C bus AC Waveforms and Measurement Circuit TABLE 3 5 3 SCL Frequency PcLK1 36 MHZ Voo 3 3 V 2 SN8200 8200UFL I2C CCR value fsc kHz Rp 4 7 kQ 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384 1 RP External pull up resistance fsci l2C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 15 For other speed ranges the tolerance on the achieved speed is 2 These variations depend on the accuracy of the external components used to design the application 2014 by Murata Electronics N A Inc Page 19 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 5 4 SCL Frequency PCLK1 30 MHz Von 3 3 V SN8205 8205UFL fscL kHz 12C_CCR value RP 4 7 KQ 0x8019 0x8021 0x8032 0x0096 0x012C 1 Rp External pull up resistance fsc l2C speed 0x02EE 2 For speeds around 200 kHz the tolerance on
12. Typical SN820X 820XUFL module marking Page 39 of 42 2014 by Murata Electronics N A Inc www murata com SN820X R 3 0 8 22 14 8 RoHS Delcaration To the best of our present knowledge given our supplier declarations this product does not contain substances that are banned by Directive 2002 95 EC or contain a maximum concentration of 0 196 by weight in homogeneous materials for e Lead and lead compounds e Mercury and mercury compounds e Chromium VI e PBB polybrominated biphenyl e PBDE polybrominated biphenyl ether And a maximum concentration of 0 01 by weight in homogeneous materials for e Cadmium and cadmium compounds 2014 by Murata Electronics N A Inc Page 40 of 42 SN820X R 3 0 8 22 14 www murata com 9 Ordering Information TABLE 9 1 SN8200 8200UFL Ordering Information RFM Model RFM Part Standard Order Product Number Number Increment SN8200 Evaluation Kit SN8200 EVK 88 00151 95 1 pe SN8200 Module in Tape amp Reel SN8200 88 00151 00 400 pcs SN8200UFL Evaluation Kit SN8200UFL EVK 88 00151 97 1 pc SN8200UFL Module in Tape amp Reel SN8200UFL 88 00151 02 400 pcs TABLE 9 2 SN8205 8205UFL Ordering Information RFM Model RFM Part Standard Order Product Number Number Increment SN8205 Evaluation Kit SN8205 EVK 88 00158 95 1 pe SN8205 Module in Tape amp Reel SN8205 88 00158 00 400 pcs SN8205UFL Evaluation Kit SN8205UFL EVK 88 00158 97 1 pc SN8205UFL Module
13. ee 28 TABLE 3 8 1 DAC Characteristics SN8200 8200UFL 0200 es 30 TABLE 3 8 2 DAC Characteristic SN8205 8205UFL 2 ee 32 TABLE 4 1 1 RF Characteristics for IEEE 802 11b 0 0 0 2 cee es 34 TABLE 4 2 1 RF Characteristics for IEEE 8027119 w 0s eceseeee heen Gree BADA ab ksa 35 TABLE 4 3 1 RF Characteristics for IEEE 802 11n eee 36 TABLE 5 1 Absolute Maximum Rating essere as Pac he Ng eee ae DP PDA e 37 TABLE 5 2 Recommended Operating Conditions ooooooocccoc ee 37 TABLE 6 1 Regulatory Compliance 02 2a 00 eee a ee 38 TABLE 9 1 SN8200 8200UFL Ordering Information 0 0 0 c cee ee 41 TABLE 9 2 SN8205 8205UFL Ordering Information 0 000 c eee 41 2014 by Murata Electronics N A Inc Page 5 of 42 SN820X R 3 0 8 22 14 www murata com 1 Introduction 1 1 Model SN820X Module Family The SN820X Module Family is a portfolio of low power self contained embedded wireless module solutions that address the connectivity demands of M2M applications These products integrate a micro controller a Wi Fi BB MAC RF IC an RF front end and two clocks into small form factor modules The module family includes 2 different micro controller options as shown below The modules can also be purchased with either a standard on board chip antenna or a U FL connector where remote antenna flexibility is required 1 2 Model SN820X Module Features Model SN8200 88 00151 00
14. in Tape amp Reel SN8205UFL 88 00158 02 400 pcs 2014 by Murata Electronics N A Inc Page 41 of 42 SN820X R 3 0 8 22 14 www murata com 10 Technical Support Contact For technical support please contact tech sup murata com Murata Electronics N A Inc 4441 Sigma Road Dallas TX 75244 USA AAA Ass UUU ULIMI 2014 by Murata Electronics N A Inc Page 42 of 42 SN820X R 3 0 8 22 14 www murata com
15. in conversion mode faoc 30 MHz 480 sampling time y f 60 HA 12 bit resolution 1 IFIRROFF is set to Von this value can be lowered to 1 7 V when the device operates in the 0 to 70 C temperature range _ 2 Itis recommended to maintain the voltage difference between Vrer and Vppa below 1 8 V 3 Based on characterization not tested in production 4 Vrerz is internally connected to Vopa and Vrer is internally connected to Vssa 5 Rapc maximum value is given for Vop 1 8 V and minimum value for Vop 3 3 V 6 For external triggers a delay of 1 fpc k2 must be added to the latency specified above Equation 1 SN8205 8205UFL Rajy Max Formula E k 0 5 Ran a Rape fane X Cane X In 2 The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 1 4 of LSB N 12 from 12 bit resolution and k is the number of sampling periods defined in the ADC SMPR1 register TABLE 3 7 6 ADC Accuracy SN8205 8205UFL Parameter Test conditions Max 2 Total unadjusted error Offset error fPCLK2 60 MHz Gain error fADC 30 MHz RAIN lt 10 kQ VDDA 1 8 3 to 3 6 V Differential linearity error Integral linearity error 1 Better performance could be achieved in restricted VDD frequency and temperature ranges 2 Based on characterization not tested in production 3 If IRROFF is set to VDD this value can be low
16. sleep clock input Tie to GND if not used GND Ground UART TX General purpose I O or UART TX UART RX General purpose I O or UART RX UART CTS General purpose I O or UART CTS UART RTS General purpose I O or UART RTS JTMS General purpose I O or JTMS 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 10 of 42 www murata com TABLE 2 2 Pinouts Continued JTDI SPI NSS General purpose I O or JTDI or SPI NSS Pin Name JTCK Description General purpose I O or JTCK Ground Ground JTDO SPI SCK General purpose I O or JTDO or SPI SCK JTRST SPI MISO General purpose I O or JTRST or SPI MISO SPI_MOSI General purpose I O or SPI_MOSI I2C SCL General purpose I O or I2C_SCL I2C SDA General purpose I O or 12C SDA BOOT Normal operation if connected to ground at power up ADC2 MICRO RST N General purpose I O or ADC2 Module reset VBAT Power supply for backup circuitry when VDD is not present GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground GND Ground Reserved No connect GND Ground 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 11 of 42 www murata com Pin name
17. t Vollage Levels s sisid a A AA Ad 15 3 5 I2C Interface Characteristics A A E id 17 3 02S SPI ChiaraCleniSuGs cards AA 20 3 7 12 Bit ADC Characteristics gt ms a e it ci 24 3 8 DAC Electrical Specifications 2 3 a A A TEA a ARA 31 4 RF a A A 35 4 1 DC RF Characteristics for IEEE 802 11b 0c eens 35 4 2 DC RF Characteristics for IEEE 802 119 2 4 2 4 wa des riada haba Lo RN Kag LPA 36 4 3 DC RF Characteristics for IEEE 002 Mins xa ese hh Oe PARAN ee eee ek ee ted DL 37 5 Environmental Specifications 0 ccc eee eee teens 38 5 1 Absolute Maximum Rating sist Na aaa Sd te od oP a 38 5 2 Recommended Operating Conditions 8 ELA ee ee 38 6 Regulatory InformavlOn Sarria NA ha GG NG PAANAN li DAANG LL an 39 7 Packing and Marking Information sectors ds ee ADAN GEL et Pasan 40 7 1 Carrier Tape Dimensions wird NA DADA DW RG DARA BADIAN LANGKA Be eee a NG 40 7 2 Module Marking Informations 2 ceo oe GNG PBA ina bp pd Ba bal DYN 40 8 ROHS Delcaration 234414 Cut sA E cate Apa aa a Vibe dea sea Bats KYA 41 9 Ordering NLA AA AA AA 42 10 Technical Support Contact acs bee Da de ed MER a A Wk LA a PA Ba Nha 43 2014 by Murata Electronics N A Inc Page 3 of 42 SN820X R 3 0 8 22 14 www murata com List of Figures FIGURE 1 1 SN820X Block Diagram a NAY LO aide oe Gare NG ALA ane NADA DAP 7 FIGURE 2 1 SN820X and SN820XUFL Top and Side View o o o ooooooooooooo 8 FIGURE 2 2
18. the achieved speed is of 45 For other speed ranges the tolerance on the achieved speed is 2 These variations depend on the accuracy of the external components used to design the application 3 6 12S SPI Characteristics The 12S interface is multiplexed with SPI and can operate in master or slave mode Unless otherwise specified the parameters below for 12S derive from tests performed under ambient temperature PCLKx frequency and Vpp supply voltage conditions TABLE 3 6 1 SPI Characteristics SN8200 8200UFL fsck 1 tusck Parameter SPI clock frequency Conditions Master mode Slave mode tusck tisck SPI clock rise and fall time Capacitive load C 30 pF DuCy SCK SPI slave input clock duty cycle Slave mode tens NSS setup time Slave mode tung NSS hold time Slave mode 1 1 twiScLH twisCLL SCK high and low time Master mode fpe x 36MHz presc 4 tsumi 1 tus Data input setup time Master mode Slave mode thm m tasn Data input hold time Master mode Slave mode tesog Data output access Slave mode fecix 20 MHz tuis so N2 Data output disable Slave mode tuso Data output valid time Slave mode after enable edge tumo Data output valid time Master mode after enable edge 1 Based on characterization not tested in production Data output hold time
19. tion in quiescent mode 380 pA Vrer 3 6 V in terms of DC consump Standby mode tion on the inputs 380 PA With no load middle code 0x800 on the Ibba DAC DC current consump inputs paa aa a 480 pA With no load worst code 0xF1C at y Vrer 3 6 V in terms of DC consump tion on the inputs DNL 2 Differential non linearity LSB Difference between two 0 5 Given for the DAC in 10 bit configuration consecutive code 1LSB 3 LSB Given for the DAC in 12 bit configuration INL 2 Integral non linearity difference 1 LSB Given for the DAC in 10 bit configuration between measured value at Code i and the value at Code i on a line drawn between code D and last 4 LSB Given for the DAC in 12 bit configuration Code 1023 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 30 of 42 www murata com TABLE 3 8 1 DAC Characteristics SN8200 8200UFL Continued Parameter Offset error difference between measured value at Code 0x800 and the ideal value Vrer 2 Comments Given for the DAC in 12 bit configuration Given for the DAC in 10 bit at VreF 3 6V Given for the DAC in 12 bit at Vpepz 3 6V Gain error 2 Gain error Given for the DAC in 12bit configuration 2 t5ETTLING Settling time full scale for a 10 bit input code transition between the lowest and the highest input codes when DAC OUT reaches final valuet1LSB CLoap 50 pF R pap 2 5 kQ
20. with no application firmware pre installed Finalize the firmware image and then download the firmware to the module For more details please see reference 4 1 4 Acronyms ADC Analog to Digital Converter DAC Digital to Analog Converter GPIO General Purpose Input Output 12C Intelligent Interface Controller 128 Integrated Interchip Sound ISM Industrial Scientific and Medical MAC Medium Access Control MSL Moisture Sensitivity Level PER Packet Error Rate ROHS Restriction of Hazardous Substances SPI Serial Peripheral Interface UART Universal Asynchronous Receiver Transmitter 1 5 References 1 STM32F103RF Data Sheet ST Microelectronics 2 STM32F205RG Data Sheet ST Microelectronics 3 SN820X Wi Fi Network Controller Module Family User Manual Murata 4 AN_SN8200_002 SN820X Firmware Downloading Application Note Murata 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 7 of 42 www murata com 2 Mechanical Specifications 2 1 Module Dimensions TABLE 2 1 Module Dimensions Typical ae Dimensions LxWxH 30 5 x 19 4 x 2 8 Dimension tolerances LxWxH 0 2 2 2 Top and Side View UI TI E B nig la AH G Top View p ara Ol nal SN820X Top and Side View KA y
21. 14 MHz 0 143 us Regular trigger conversion a 24 11 latency bi ADS t5 fanc 14 MHz 0 107 17 1 us Sampling time 1 5 2395 faoc Power up time 1 fanc 14 MHz 18 Total conversion time including 14 to 252 ts for sampling 12 5 for suc sampling time a PO Na cessive approximation 1 Based on characterization not tested in production 2 Guaranteed by design not tested in production 3 Vrer can be internally connected to Vopa and Vrer can be internally connected to Vssa depending on the package 4 For external triggers a delay of 1 frcLx2 must be added to the latency specified above aay Ew tit i 10N uanll ififiresxs OHHH 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 24 of 42 www murata com Equation 1 SN8200 8200UFL RAIN max formula T gt Rape Rain lt AA aaa Ha fane X Cape x In 2 The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 1 4 of LSB Here N 12 from 12 bit resolution TABLE 3 7 2 Ram max for fapc 14 MHz SN8200 8200UFL Ts cycles RAIN max kO 239 5 17 1 NA 1 Guaranteed by design not tested in production TABLE 3 7 3 ADC accuracy SN8200 8200UFL limited test conditions 2 Parameter Test conditions Max 3 Total unadjusted error fPCLK2 56 MHz Offset error fADC 14 MHz RAIN lt 10 kQ VDDA 3 V to Differential linearity error 3 6 V TA
22. 8205 SN8205 UFL Typical Power Consumption 13 TABLE 3 2 1 Digital I O Characteristics SN8200 SN8200UFL 2 2 0 13 TABLE 3 2 2 Digital I O Characteristics SN8205 8205UFL a 14 TABLE 3 3 1 Voltage Characteristics SN820X dora eel ea Ka KAN a 14 TABLE 3 3 2 Current Characteristics SN8200 8200UFL 0000 ee 15 TABLE 3 3 3 Current Characteristics SN8205 8205UFL 1 2 a 15 TABLE 3 4 1 Output Voltage Characteristics SN8200 SN8200UFL 0 00s aa 15 TABLE 3 4 2 Output Voltage Characteristics SN8205 SN8205UFL lau aa aa 16 TABLE 3 5 1 I2C Characteristics SN8200 8200UFL 0 00 es 17 TABLE 3 5 2 12C Characteristics SN8205 8205UFL ee 18 TABLE 3 5 3 SCL Frequency fPCLK1 36 MHZ VDD 3 3 V 1 2 SN8200 8200UFL 19 TABLE 3 5 4 SCL Frequency fPCLK1 30 MHZ VDD 3 3 V 1 2 SN8205 8205UFL 20 TABLE 3 6 1 SPI Characteristics SN8200 8200UFL ee 20 TABLE 3 6 2 SPI Characteristics SN8205 8205UFL ee 21 TABLE 3 7 1 ADC Characteristics SN8200 8200UFL aneneen 23 TABLE 3 7 2 RAIN max for fADC 14 MHz 1 SN8200 8200UFL 0 aaa 25 TABLE 3 7 3 ADC accuracy SN8200 8200UFL limited test conditions 1 2 25 TABLE 3 7 4 ADC Accuracy 1 2 3 SN8200 8200UFL 2 2 2 26 TABLE 3 7 5 ADC Characteristics SN8205 8205UFL ee 27 TABLE 3 7 6 ADC Accuracy SN8205 8205UFL 2
23. D supply voltage conditions The SN8200 8200UFL and SN8205 8205UFL performance line 12C interface meets the requirements of the standard I2C communication protocol with the following restrictions the I O pins to which SDA and SCL are mapped are not true open drain When configured as open drain the PMOS connected between the I O pin and VDD is disabled but is still present The 12C characteristics are described in Table 3 5 1 and Table 3 5 2 TABLE 3 5 1 12C Characteristics SN8200 8200UFL Standard mode Fast mode 12C 1 Parameter M Min tw SCLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 z tsu SDA SDA setup time 250 100 th SDA SDA data hold time 003 0 4 90003 tr SDA 7 1000 20 0 1Cb 300 tr SCL SDA and SCL rise time ti SDA 300 300 ns t SCL SDA and SCL fall time th STA Start condition hold time 4 0 0 6 tsu STA Repeated Start 4 7 0 6 Us condition setup time tsu STO Stop condition setup time 4 0 0 6 us tw STO STA Stop to Start condition 4 7 1 3 us time bus free Cb Capacitive load for each 400 400 pF bus line 1 Guaranteed by design not tested in production 2 fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies It must be at least 4 MHz to achieve the fast mode 12C frequencies and it must be a multiple of 10 MHZ in order to reach the 12C fast mode maximum clock speed of 400 kHz 3 The ma
24. Detailed Pad Dimensions top view 0000 tee 9 FIGURE 3 1 SN8200 8200UFL I2C bus AC Waveforms and Measurement Circuit 18 FIGURE 3 2 SN8205 8205UFL 12C bus AC Waveforms and Measurement Circuit 19 FIGURE 3 3 SPI Timing Diagram Slave Mode and CPHA 0 SN8200 8200UFL and SN8205 83205UFL rpe oat eee eee bos Pa naa beaten Me eae ia de 23 FIGURE 3 4 SPI Timing Diagram Slave Mode and CPHA 1 1 SPI Timing Diagram Slave Mode and CPHA 0 SN8200 8200UFL and SN8205 8205UFL 23 FIGURE 3 5 SPI Timing Diagram Master Mode SN8200 8200UFL and SN8205 8205UFL 24 FIGURE 3 6 ADC Accuracy Characteristics SN8200 8200UFL 0 02 02 e eee 27 FIGURE 3 7 ADC Accuracy Characteristics SN8205 8205UFL ee 30 FIGURE 3 8 Typical Connection Diagram Using the ADC SN8205 8205UFL 30 FIGURE 7 1 SN820X 820XUFL Carrier Tape Dimensions 00000 cece eee 40 FIGURE 7 2 Typical SN820X 820XUFL module marking 2 0c cece eee eee 40 2014 by Murata Electronics N A Inc Page 4 of 42 SN820X R 3 0 8 22 14 www murata com List of Tables TABLE 1 1 SN820X WiFi Network Controller Module Family a 6 TABLE 2 1 Module DIMENSIONS i r Baa KA GARA Ses hg BOK ace MANG a Rb whee BAKBAKAN 8 TABLE 2 22 PINOUIS yt PALANG ee as Pek PRL DES TAKA eee Ret EA 10 TABLE 2 3 Signal Pinouts for SN820X 820XUFL ee 12 TABLE 3 1 1 SN8200 SN8200UFL and SN
25. SB VREF 3 6 V Gain error 4 Gain error Given for the DAC in 12 bit configu i B 0 5 ration t 4 Settling time full scale for a 10 bit SETTLING input code transition between the lowest and the highest input codes Cloan 50 pF when DAC_OUT reaches final z value 4LSB 3 e HS Rioap 2 5 kQ THD Total Harmonic Distortion Cj pap S 50 pF Buffer ON dB Rioap 2 5 KQ Update rate 2 Max frequency for a correct CLoap S 50 pF DAC_OUT change when MS s Rioap 2 5 kQ small variation in the input 1 code from code i to it1LSB Laue Wakeup time from off state Cloap 50 pF R gap 2 5 kA Setting the ENx bit in the z 6 5 10 us input code between lowest and highest possible ones DAC Control register PSRR Power supply rejection ratio to VDDA static DC measurement _67 _40 dB No RLOAD CLOAD 50 pF 1 If IRROFF is set to VDD this value can be lowered to 1 7 V when the device operates in the 0 to 70 C temperature range 2 Guaranteed by design not tested in production 3 The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs 4 Guaranteed by characterization not tested in production eee 2014 by Murata Electronics N A Inc Page 33 of 42 SN820X R 3 0 8 22 14 www murata com 4 RF Specifications 4 1 DC RF Characteristics for IEEE 802 11b Conditions 25 C VDD_WIFI_IN 3 6 V VDD 3 3 V 11 MBps mode unless otherwise spe
26. cified Parameters measured at RF connector TABLE 4 1 1 RF Characteristics for IEEE 802 11b Parameters Specification Standards conformance IEEE 802 11b Modulation DSSS CCK Physical layer data rate 1 2 5 5 11 Mbps RF Characteristics Minimum Typical Maximum Frequency range 2400 2483 5 Carrier frequency error Transmit output power 1 Spectrum mask 15t side lobes 24 side lobes Power on and power down ramp RF carrier suppression Modulation accuracy EVM Out of band spurious emissions 30 MHz to 1 GHz BW 100 kHz 1 GHz to 12 75 GHz BW 1 MHz 1 8 GHz to 1 9 GHz BW 1 MHz 5 15 GHz to5 3 GHz BW 1 MHz Receive sensitivity 1 1 Mbps FER lt 8 11 Mbps FER lt 8 Maximum input level FER lt 8 Adjacent channel rejection FER lt 8 Notes 1 Derate by 1 5 dB for temperatures less than 10 C or more than 55 C in both transmit and receive modes 2014 by Murata Electronics N A Inc Page 34 of 42 SN820X R 3 0 8 22 14 www murata com 4 2 DC RF Characteristics for IEEE 802 11g Conditions 25 C VDD_WIFI_IN 3 6 V VDD 3 3 V 54 Mbps mode unless otherwise specified Parameters measured at RF connector TABLE 4 2 1 RF Characteristics for IEEE 802 11g Parameters Specification Standards conformance IEEE 802 11g Modulation OFDM Data rate 6 9 12 18 24 36 48 54 Mbps RF Characteristics Minimum Typical Maximum Frequenc
27. cted to the external power supply in the permitted range Negative injection disturbs the analog performance of the device Positive injection is not possible on these I Os A negative injection is induced by Vin lt Vss ling pin Must never be exceeded A positive injection is induced by Viy gt Vpp while a negative injection is induced by Viy lt Vss ling pin Must never be exceeded ak ON a When several inputs are submitted to a current injection the maximum Z1 ny pin is the absolute sum of the positive and negative injected currents instantaneous values 3 4 Output Voltage Levels Unless otherwise specified the parameters given in Table 3 4 1 and Table 3 4 2 are derived from tests performed under ambient temperature and Vpp supply voltage conditions All l Os are CMOS and TTL compliant TABLE 3 4 1 Output Voltage Characteristics SN8200 SN8200UFL Parameter Conditions Output low level voltage for an I O pin when 8 pins are sunk at same time TTL port Output high level voltage for an I O pin lio 8 MA when 8 pins are sourced at same time 2 7 V lt VDD lt 3 6 V Output low level voltage for an I O pin CMOS port when 8 pins are sunk at same time lo 8MA Output high level voltage for an I O pin 2 7 V lt VDD lt 3 6 V when 8 pins are sourced at same time 2014 by Murata Electronics N A Inc Page 15 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 4 1 Output Voltage Characteri
28. document to new Murata visual identity Added Anatel certification page 39 3 1 8 22 14 R Willett Revised Table 5 1 to include VDD VBAT and VDD_WiFi 2010 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 www murata com This page intentionally left blank 2010 2014 by Murata Electronics N A Inc 42 SN820X R 3 0 8 22 14 Page 2 of 2 www murata com Table of Contents LINTODUCION 0 Kana ad e EI A ELP EN Wak an 6 1 1 Model SN820X Module Family maaagaw haws 28 20 WIGAN oe GA AD GA tbe GA Dae a al 6 1 2 Model SN820X Module Features oc icissccatecanticcescbad Ves DD PENA ee en be LNG ad 6 ole AB AAA PAA dee AA AA AA eee 7 FAACrONYMS supe iris Ayden AE PIG Bi tha A as anes NA NIN NG AG A O 7 A e AAA Bad eNOS ihe ho AW oad Roh Rigby gene ead DA ADAN 7 2 Mechanical Specifications 481 a ka wo te Peres Sec ma Bes cheek es SES eed Ka apan Tes 8 2 1 Module Dimensions e paa abd yt Gad aad A a ye aes 8 2 2 Top and Side VIEW 748K ra nG neta yi dual ernie BALA ph elon inion hese igen WO dha hg 8 2 3 PCB Footprint top view 1 vee ho See lo ds Oe deh ma Ka Da a Nan ln Aa ha AMAG kad Oot diet 9 ZA BINOUES a GA sna A os hh eae a aa NE ae AE ae ae eae NA 10 3 DC Electrical Specifications Ga aan AG ean hap pa ars a ha ede ood 13 3 1 Typical Power Consumption an baa kak o KN kaa Nad so ket nla tele diia a 13 3 2 GPlOInterace AA 13 3 3 OQutp t driving Curent 03 a eae e a a Meee a daa a wes Bias esas AG 14 3 4 OQ tp
29. e 13 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 2 2 Digital I O Characteristics SN8205 8205UFL Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage 3 6 Input Low Voltage MICRO_RST_N 0 8 Input High Voltage MICRO_RST_N VDD 0 5 Output Low Voltage 0 4 Output High Voltage Weak Pull up Equivalent Resistor 50 15 Weak Pull down Equivalent resistor 50 15 1 for pins 5 6 7 9 10 11 12 42 46 2 for pins 32 38 40 41 43 44 Pin 33 3 3 Output driving current The GPIOs general purpose input outputs can sink or source up to 8 mA and sink or source up to 20 mA with a relaxed VOL VOH except PC13 PC14 and PC15 which can sink or source up to 3mA When using the PC13 to PC15 GPIOs in output mode the speed should not exceed 2 MHz with a maximum load of 30 pF e Inthe user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Table 3 3 1 e The sum of the currents sourced by all the I Os on VDD plus the maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute maximum rating IVDD TABLE 3 3 1 Voltage Characteristics SN820X Ratings External main supply voltage including Vppa Vpop Input voltage on five volt tolerant pin Input voltage on any other pin AVopx Variations between different VDD power pins Vss
30. ered to 1 7 V when the device operates in the 0 to 70 C temperature range NOTE ADC accuracy vs negative injection current injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recom mended to add a Schottky diode pin to ground to analog pins which may potentially inject negative currents 2014 by Murata Electronics N A Inc Page 28 of 42 SN820X R 3 0 8 22 14 www murata com V vV LSBipeaL os or ae depending on package 4095 4 4094 4093 2 NO A UA DN o 1 2 3 456 7 4093 4094 4095 4096 Vssa VDDA FIGURE 3 7 ADC Accuracy Characteristics SN8205 8205UFL Example of an actual transfer curve Ideal transfer curve End point correlation line ET Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves EO Offset Error deviation between the first actual transition and the first ideal one EG Gain Error deviation between the last ideal transition and the last actual one ED Differential Linearity Error maximum deviation between actual steps and the ideal one EL Integral Linearity Error maximum deviation between any actual transition and the end point correlation line BONZ STM32F Sample and hold ADC converter 12 bit converte FIGURE 3 8 Typical Connection Diagram Using the ADC
31. ffer OFF VREF 1LSB It gives the maximum output excur sion of the DAC DAC DC VREF current con sumption in quiescent mode Standby mode With no load worst code 0x800 at Veer 3 6 V in terms of DC con sumption on the inputs With no load worst code OxF1C at Veer 3 6 V in terms of DC con sumption on the inputs DAC DC VDDA current con sumption in quiescent mode 3 With no load middle code 0x800 on the inputs With no load worst code OxF1C at Vrer 3 6 V in terms of DC con sumption on the inputs Differential non linearity Difference between two consecutive code 1LSB Given for the DAC in 10 bit configura tion Given for the DAC in 12 bit configura tion Integral non linearity difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Given for the DAC in 10 bit configu ration Page 32 of 42 Given for the DAC in 12 bit configu www murata com TABLE 3 8 2 DAC Characteristic SN8205 8205UFL Continued Parameter Comments Offset 4 Offset error Given for the DAC in 12 bit configu difference between 10 mV ration measured value at Code Given for the DAC in 10 bit at 0x800 and the ideal value S x 3 LSB VREF 3 6 V BEAZ Given for the DAC in 12 bit at E 12 L
32. he minimum time to drive the output and the max time is for the maximum time to validate the data 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z eee 2014 by Murata Electronics N A Inc Page 21 of 42 SN820X R 3 0 8 22 14 www murata com NSS input la te SCKY s U NSS CPHA 0 CPOL 0 tw SCKH CPHA 0 tw SCKL 3 2 x o a CPOL 1 ta so ty sOo th SO t SCK tdis SO MISO OUTPUT LSB OUT BIT1 IN Y in Y IN LI mow A BIT6 OUT tsu Sl MOSI INPUT FIGURE 3 3 SPI Timing Diagram Slave Mode and CPHA 0 SN8200 8200UFL and SN8205 8205UFL CPHA 1 CPOL 0 CPHA 1 CPOL 1 tsu NS tW SGKH ly x Sjre m th NS sy sf 1 1 r 1 it pi ot wt 1 SCK Input gt e US SO itf SCK BIT6 OUT LSB OUT MISO OUTPUT e MOSI INPUT FIGURE 3 4 SPI Timing Diagram Slave Mode and CPHA 1 SPI Timing Diagram Slave Mode and CPHA 0 SN8200 8200UFL and SN8205 8205UFL 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 22 of 42 www murata com High NSS input a aaa CPHA 0 f 2 CPOL 0 Fi CPHA O i ii 1 N i CPOL 1 TAO YIN YUN f1 CPHA 1 CPOL 0 CPHA 1 SCK Input MISO lt lt tha gt MOSI 1 h OUTUT
33. muRata INNOVATOR IN ELECTRONICS Revision History RFM products are now Murata products SN820X Family Data Sheet Wi Fi Network Controller Module Revision Date Author Change Description 0 1 12 09 2012 Y Fang Initial version 0 5 02 03 2012 Y Fang Preliminary version 0 6 02 20 2012 N Nagayama Update performance data and adjusted table format 0 7 04 20 2012 J Gregus Update CE compliance information 1 0 08 27 2012 Y Fang Formal release 1 1 01 23 2013 Y Fang Added Power Rail Current specification and Standby Mode Current specification 1 2 05 30 2013 R Willett Changed specs in Table 1 for Pin 2 3 4 and 30 1 3 09 20 2013 R Willett Separated Data Sheet User Manual and created new data sheet combining SN8200 8200 UFL and SN8205 8205 UFL 1 4 11 07 13 R Willett Added Acronyms list Revised Fig 1 1 2 1 revised con tent and renumbered tables in Chap 3 added Chapters 4 10 and reorganized information amended regulatory information 1 5 11 11 13 R Willett Revised Operating Temperature specification on page 6 revised Table 5 1 Absolute Maximum Ratings page 38 2 0 11 25 13 R Willett Removed references to SyChip updated copyright deleted Chap 11 Disclaimer 2 1 12 17 13 R Willett Added text describing module software download in Chapter 1 page 7 2 2 02 28 14 R Willett Revised text on page 42 Table 9 2 3 0 07 25 14 R Willett Reformatted
34. re sourced at same time Output low level voltage for an I O pin when 8 pins are sunk at same time lo 20 mA Output high level voltage for an I O pin 2 7 V lt VDD lt 3 6 V when 8 pins are sourced at same time Output low level voltage for an I O pin when 8 pins are sunk at same time lo 6 mA Output high level voltage for an I O pin 2 V lt VDD lt 2 7 V when 8 pins are sourced at same time 1 PC13 PC14 PC15 and PI8 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 and PI8 in output mode is limited the speed should not exceed 2 MHz with a maximum load of 30 pF and these I Os must not be used as a current source e g to drive an LED 2 The IlO current sunk by the device must always respect the absolute maximum rating specified in Table 3 4 2 and the sum of IIO O ports and control pins must not exceed IVSS 3 The IlO current sourced by the device must always respect the absolute maximum rating specified in Table 3 4 2 and the sum of IIO I O ports and control pins must not exceed IVDD 4 Based on characterization data not tested in production ee 2014 by Murata Electronics N A Inc Page 16 of 42 SN820X R 3 0 8 22 14 www murata com 3 5 IC Interface Characteristics Unless otherwise specified the parameters given below are derived from tests performed under ambient temperature fPCLK1 frequency and VD
35. resolution Conversion voltage range 4 0 Vssa OF Vper tied to ground External input impedance See Equation 1 for details Sampling switch resistance Internal sample and hold capacitor Injection trigger conversion latency fanc 30 MHz Regular trigger conversion latency fanc 30 MHz Sampling time Power up time fanc 30 MHz tstaB p 5 a ng teony faoc 30 MHz 0 5 16 40 us 12 bit resolution faoc 30 MHz 0 43 16 34 us Total conversion time including sam 10 bit resolution pling time faoc 30 MHz 0 37 16 27 us 8 bit resolution faoc 30 MHz 0 3 16 20 us 6 bit resolution 9 to 492 ts for sampling n bit resolution for successive approxi Wfapc mation AS 12 bit resolution Single ADC _ E 2 Msps Sampling rate fapc 30 MHz 12 bit resolution Interleave Dual ADC 2 3 75 Msps mode 12 bit resolution Interleave Triple ADC 2 E 6 Msps mode 2014 by Murata Electronics N A Inc Page 27 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 7 5 ADC Characteristics SN8205 8205UFL Continued Parameter Conditions faoc 30 MHz 3 sampling time 12 300 500 PA 3 ADC VreF DC current consump bit resolution tion in conversion mode faoc 30 MHz 480 sampling time 16 HA 12 bit resolution 3 faoc 30 MHz 3 sampling time 12 1 6 1 8 mA ADC VDDA DC current con bit resolution sumption
36. smit mode 18 dBm 100 Duty Cycle Receive mode Transmitmode 14 5 dBm 100 Duty Cycle 11n Receive mode MCS7 110 mA Transmit mode 280 mA 13 5 ABM 100 Duty Cycle Standby Mode with IEEE802 11 Power DTIM 1 Telnet session estab 3 15 mA Save lished and idling Standby Mode with IEEE802 11 Power DTIM 3 Telnet session estab 1 28 mA Save lished and idling 3 2 GPIO Interface The general purpose I O GPIO pins available on the SN820X will connect to various external devices GPIOs are configured as input float ing by default Subsequently they can be programmed to be either input or output pins via the GPIO control register They can also be pro grammed to have internal pull up or pull down resistors The MICRO_RST_N pin is connected to a permanent pull up resistor Rpy TABLE 3 2 1 Digital I O Characteristics SN8200 SN8200UFL min max Input Low Voltage 0 3 0 28 VDD 2 0 8 Input High Voltage 0 41 VDD 2 1 3 VDD 0 3 Input Low Voltage 0 3 0 32 VDD2 0 75 Input High Voltage 0 42 VDD 2 1 VDD 0 5 Input Low Voltage MICRO RST N 0 5 0 8 Input High Voltage MICRO RST N 2 VDD 0 5 Output Low Voltage Output High Voltage Weak Pull up Equivalent Resistor Weak Pull down Equivalent resistor 1 for pins 5 6 7 9 10 11 12 42 46 2 for pins 32 38 40 41 43 44 2014 by Murata Electronics N A Inc Pag
37. stics SN8200 SN8200UFL Continued Parameter Conditions Output low level voltage for an I O pin when 8 pins are sunk at same time lo 20 mA Output high level voltage for an I O pin 2 7 V lt VDD lt 3 6 V when 8 pins are sourced at same time Output low level voltage for an I O pin when 8 pins are sunk at same time lo 6 mA Output high level voltage for an I O pin 2V lt VobpD lt 2 7 V when 8 pins are sourced at same time 1 The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 3 4 1 and the sum of IIO 1 O ports and control pins must not exceed IVSS 2 The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 3 4 1 and the sum of IIO I O ports and control pins must not exceed IVDD 3 TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52 4 Based on characterization data not tested in production TABLE 3 4 2 Output Voltage Characteristics SN8205 SN8205UFL Parameter Output low level voltage for an I O pin when 8 pins are sunk at same time Output high level voltage for an I O pin when 8 pins are sourced at same time Conditions CMOS port llo t 8mA 2 7 V lt VDD lt 3 6 V Output low level voltage for an I O pin when 8 pins are sunk at same time TTL port lo 8 mA Output high level voltage for an I O pin 2 7 V lt VDD lt 3 6 V when 8 pins a
38. t is rec ommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current 4 Preliminary values v v nia REF or PDA depending on package IDEAL 4006 4096 4 BOGA ad lt mgs lo ons is aod Bdo a a TE 1 Example of an actual transfer curve 2 The ideal transfer curve 4094 4 3 End point correlation line 4093 A Pa 2 Be P t Er Total Unadjusted Error maximum deviation Er e between the actual and the ideal transfer curves 74 i p 3 Eo 0ffset Error deviation between the first actual se 1 i transition and the first ideal one 6 saad Eg Gain Error deviation between the last ideal 5 transition and the last actual one Ep Differential Linearity Error maximum deviation 45 between actual steps and the ideal one E Integral Linearity Error maximum deviation Ep between any actual transition and the end point 2 4 i correlation line 17 1 LSBipeaL t t Lpi o 0 7 4093 4094 4095 4096 Vssa Vppa FIGURE 3 6 ADC Accuracy Characteristics SN8200 8200UFL m AAA gt 2014 by Murata Electronics N A Inc Page 26 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 7 5 ADC Characteristics SN8205 8205UFL Parameter Power supply Conditions Positive reference voltage ADC clock frequency VDDA 1 80 to 2 4 V VDDA 2 4 to 3 6 V External trigger frequency fADC 30 MHz with 12 bit
39. x 7 Vssl Variations between all the different ground pins Vesp HBM Electrostatic discharge voltage human body model 1 All main power Vpp Vppa and ground Vss Vasa pins must always be connected to the external power supply in the permitted range 2 Vin maximum value must always be respected eee 2014 by Murata Electronics N A Inc Page 14 of 42 SN820X R 3 0 8 22 14 www murata com TABLE 3 3 2 Current Characteristics SN8200 8200UFL Ratings lvpp Total current into Vpp Vpp power lines source lyss Total current out of Vss ground lines sink Output current sunk by any I O and control pin lio Output current source by any I Os and control pin Ine Injected current on five volt tolerant pins Injected current on any other pin 2 nuein Total injected current sum of all 1 O and control pins TABLE 3 3 3 Current Characteristics SN8205 8205UFL Ratings IvDD Total current into VDD power lines source 1 120 Ivss Total current out of Vss ground lines sink 1 120 Output current sunk by any I O and control pin 25 lio Output current source by any I Os and control pin 25 mA Injected current on five volt tolerant 1 0 3 5 0 IINJ PIN 2 Injected current on any other pin 4 t5 ZIINJ PIN 4 Total injected current sum of all I O and control pins 5 25 All main power Vpp Vppa and ground Vss Vssa pins must always be conne
40. ximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal 4 The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2014 by Murata Electronics N A Inc SN820X R 3 0 8 22 14 Page 17 of 42 www murata com TABLE 3 5 2 12C Characteristics SN8205 8205UFL tw SCLL Parameter SCL clock low time Standard mode Fast mode 12C 1 Min tw SCLH SCL clock high time tsu SDA SDA setup time th SDA SDA data hold time 900 3 tr SDA tr SCL SDA and SCL rise time 300 tf SDA tf SCL SDA and SCL fall time 300 th STA Start condition hold time tsu STA Repeated Start condition setup time tsu STO Stop condition setup time tw STO STA Stop to Start condition time bus free Cb Capacitive load for each bus line 1 Guaranteed by design not tested in production 2 feciKi must be at least 2 MHz to achieve standard mode l2C frequencies It must be at least 4 MHz to achieve fast mode l2C frequen cies and a multiple of 10 MHz to reach the 400 kHz maximum l2C fast mode clock 3 The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal START REPEATED xi AY A 5 Ing SDA SDA aa l pr
41. y range Carrier frequency error Transmit output power Spectrum mask 9 MHz to 11 MHz O dB to 20 dB 11 MHz to 20 MHz 20 dB to 28 dB 20 MHz to 30 MHz 28 dB to 40 dB dB dB dB 30 MHz to 33 MHz 40 dB 0 dB Constellation Error EVM 25 dB Out of band spurious emissions 30 MHz to 1 GHz BW 100 kHz 1 GHz to 12 75 GHz BW 1 MHz 96 dBm 1 dBm 1 8 GHz to 1 9 GHz BW 1 MHz 65 dBm 5 15 GHz to5 3 GHz BW 1 MHz 85 dBm Received Sensitivity 6 Mbps PER s 10 54 Mbps PER s 10 Maximum input level PER s 10 Adjacent channel rejection PER lt 10 Notes 1 Derate by 1 5 dB for temperatures less than 10 C or more than 55 C in both transmit and receive modes md SSS AAA AAA 5 2014 by Murata Electronics N A Inc Page 35 of 42 SN820X R 3 0 8 22 14 www murata com 4 3 DC RF Characteristics for IEEE 802 11n Conditions 25 C VDD_WIFI_IN 3 6 V VDD 3 3 V 65 Mbps mode unless otherwise specified Parameters measured at RF connector TABLE 4 3 1 RF Characteristics for IEEE 802 11n Parameters Specification Standards conformance IEEE 802 11n Modulation OFDM Data rate 6 5 13 19 5 26 39 52 58 5 65 Mbps RF Characteristics Minimum Typical Maximum Frequency range Carrier frequency error Transmit Output Power Spectrum mask 9 MHz to 11 MHz O dB to 20 dB dB 11 MHz to 20 MHz 20 dB to
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