Interrupts 1 - Cristinel Ababei
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1. SYSTICK Timer Control and Status Regs SYSTICK Control and Status ised 0xE000E010 pie name _____ Type Reser value _ Descrprion ______ COUNTFLAG Read as 1 if counter reaches 0 since last time this register is read clear to 0 automatically when read or when current counter value is cleared CLKSOURCE 0 External reference clock STCLK 1 Use core clock TICKINT 1 Enable SYSTICK interrupt generation when SYSTICK timer reaches 0 0 Do not generate interrupt ENABLE SYSTICK timer enable See page 505 of LPC17xx user manual for description SYSTICK Reload Value Register 0xE000E014 pei _ Name__ Type _ eer vate SYSTICK Current Value Register 0xE000E018 Bs ee me CURRENT Read to return current value of the timer Write to clear counter to 0 Clearing of current value also clears COUNTFLAG in SYSTICK Control and Status Register SYSTICK Calibration Value odbc 0xE000E01C Bits Name Type Reset Value Description Z o O 1 No aprem reference clock STCLK not available 0 External reference clock available 1 Calibration value is not exactly 10 ms 0 Calibration value is accurate Calibration value for 10 ms chip designer should provide this value via Cortex M3 input signals If this value is read as 0 calibration value is not available 16 Outline Introduction NVIC and Interrupt Control Interrupt Pending Examples Interrupt Service Routines Interrupt Pend2. Reset NMI Z Nonmaskable interrupt external NMI input Hard Fault MemManage Fault 1 Programmable All fault conditions if the corresponding fault handler is not enabled Memory management fault MPU violation or access to illegal locations Bus Fault Programmable Bus error occurs when AHB interface receives an error response from a bus slave also called prefetch abort if it is an instruction fetch or data abort if it is a data access Usage Fault Programmable Exceptions due to program error or trying to access coprocessor the Cortex M3 does not support a coprocessor Reserved NA SVCall Programmable System Service call Debug Monitor Programmable Debug monitor breakpoints watchpoints or external debug requests Reserved NA PendSV Programmable Pendable request for system device SYSTICK Programmable System Tick Timer List of external interrupts Exception Number Exception Type Priority 6 External Interrupt 0 Programmable 17 External Interrupt 1 Programmable External Interrupt 239 Programmable Interrupt Programming To arm disarm a device peripheral means to enable shut off the source of interrupts Each potential interrupting trigger has a separate arm bit One arms disarms a trigger if one is is not interested in interrupts from this source To enable disable means to al
3. gt TCR amp 1 lt lt 1 Stop resetting the timer see page 492 and 494 of user manual 2 Enable timer interrupt TIMERO_IRQn is 1 see lpc17xx h and page 73 of user manual NVIC_EnablelRQ TIMERO_IRQn see core_cm3 h header file LI 2 1 L LPC_TIMO gt TCR 1 lt lt 0 Start timer see page 492 and 494 of user manual LPC_SC gt PCONP 1 lt lt 15 Power up GPIO see lab1 LPC_GPIO1 gt FIODIR 1 lt lt 29 Put P1 29 into output mode LED is connected to P1 29 while 1 Why do we need this do nothing return 0 Example 2 Blink LED Here we describe what should be done when the interrupt on Timer 0 is handled We do that by writing this function whose address is recorded in the vector table from file startup_LPC17xx s under the name TIMERO_IRQHandler void TIMERO_IRQHandler void if LPC_TIMO gt IR amp 0x01 0x01 if MRO interrupt LPC_TIMO gt IR 1 lt lt 0 Clear MRO interrupt flag see page 492 and 493 of user manual LPC_GPIO1 gt FIOPIN 1 lt lt 29 Toggle the LED see lab1 Brief description of Example 2 Set up Timer 0 to run off the CPU Clock CCLK Match 0 is set to 2423 Ask Timer 0 to be reset on Match 0 and also an interrupt to be generated when Match 0 occurs The timer starts counts from 0 to 2423 At this point match occurs The timer is reset and the interrupt occurs Inside the interrupt han
4. Setup vector for IRQ 7 External IRQ priority base Set IRQ 7 priority to 0xC0 SETEN register IRQ 7 enable bit value 0x1 shifted by 7 bits Enable the interrupt 22 Simplified procedure for setting up an interrupt e If the application is stored in ROM and there is no need to change the exception handlers we can have the whole vector table coded in the beginning of ROM in the Code region 0x00000000 e This way the vector table offset will always be O and the interrupt vector is already in ROM e The only steps required to set up an interrupt are 1 Set up the priority group if needed 2 Set up the priority of the interrupt 3 Enable the interrupt include LPC17xx h MEENE Example 2 Blink LED 1 Timer 0 configuration see page 490 of user manual LPC_SC gt PCONP 1 lt lt 1 Power up Timer 0 see page 63 of user manual LPC_SC gt PCLKSELO 1 lt lt 2 Clock for timer CCLK i e CPU Clock see page 56 of user manual LPC_TIMO gt MRO 1 lt lt 23 Give a value suitable for the LED blinking frequency based on the clock frequency see page 492 and 496 of user manual PC_TIMO gt MCR 1 lt lt 0 Interrupt on Match 0 compare see page 492 and 496 of user manual PC_TIMO gt MCR 1 lt lt 1 Reset timer on Match 0 see page 492 and 496 of user manual PC_TIMO gt TCR 1 lt lt 1 Manually Reset Timer 0 forced see page 492 and 494 of user manual PC_TIMO
5. 0 31 bit 0 for interrupt 0 exception 16 bit 1 for interrupt 1 exception 17 bit 31 for interrupt 31 exception 47 Write 1 to set bit to 1 write 0 has no effect Read value indicates the current status OxEO00E280 CLRPENDO Clear pending for external interrupt 0 31 bit 0 for interrupt 0 exception 16 bit 1 for interrupt 1 exception 17 bit 31 for interrupt 31 exception 47 Write 1 to clear bit to 0 write 0 has no effect Read value indicates the current pending status See page 81 84 of LPC17xx user manual for description of ISPRO ISPR1 and ICPRO ICPR1 Active Status Each external interrupt has an active status bit When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed Interrupt Active Bit Status registers 0xEO00E300 0xEO00E31C Address Name Reset Value Description 0xE000E300 ACTIVEO 0 Active status for external interrupt 0 31 bit 0 for interrupt 0 bit 1 for interrupt 1 bit 31 for interrupt 31 OxE000E304 ACTIVE1 Active status for external interrupt 32 63 See page 85 86 of LPC17xx user manual for description of IABRO IABR1 Priority Levels e Each external interrupt has an associated priority level register which has a maximum width of 8 bits and a minimum width of 3 bits e Interrupt Priority Level registers 0xE000E400 0xE000E4EF Address Re
6. 2 Copy the hard fault and NMI handlers to a new vector table location if vector table relocation is required 3 The Vector Table Offset register should also be set up to get the vector table ready optional Procedure for setting up an interrupt 4 Set up the interrupt vector for the interrupt Since the vector table could have been relocated we might need to read the Vector Table Offset register then calculate the correct memory location for your interrupt handler This step might not be needed if the vector is hardcoded in ROM 5 Set up the priority level for the interrupt 6 Enable the interrupt 21 Example 1 The program in assembly 1 RO 0xEQOOEDOC R1 0x05FA0500 R1 RO R4 8 r Application Interrupt and Reset Control Register Priority Group 5 2 6 Set Priority Group Vector Table in ROM R5 NEW_VECT_TABLE 8 R4 RO R1 R5 RO R1 RO 0XE000ED08 R1 NEW_VECT_TABLE R1 RO Read vectors address for NMI and Hard Fault Copy vectors to new vector table Vector Table Offset Register Set vector table to new location Example 1 The program in assembly 2 RO IRQ7_Handler R1 0XE000ED08 R1 R1 r R1 R1 4 7 16 RO R1 RO 0xE000E400 R1 0xCO R1 RO 7 RO 0xE000E100 R1 1 lt lt 7 R1 RO r Get starting address of IRQ 7 handler Vector Table Offset Register Calculate IRQ 7 handler vector address
7. CD WDT_IRQHandler 16 Watchdog Timer DCD TIMERO_IRQHandler 17 Timer0 DCD UARTO_IRQHandler 21 UARTO Special registers PRIMASK FAULTMASK and BASEPRI e What if we quickly want to disable all interrupts e Write 1 into PRIMASK to disable all interrupt except NMI MOV RO 1 MSR PRIMASK RO e Write 0 into PRIMASK to enable all interrupts e FAULTMASK is the same as PRIMASK but also blocks hard fault priority 1 e What if we want to disable all interrupts below a certain priority e Write priority into BASEPRI MOV RO 0x60 MSR BASEPRI RO 14 Software interrupts e Software interrupts can be generated in two ways Use the SETPEND register Use the Software Trigger Interrupt Register STIR Software Trigger Interrupt Register 0xE000EF00 Name Type Reset Value Description INTID w Writing the interrupt number sets the pending bit of the interrupt for example write 0 to pend external interrupt 0 See page 90 of LPC17xx user manual for description of STIR The SYSTICK Timer Often a hardware timer is used To generate interrupts so that the OS can carry out task management As an alarm timer for timing measurement etc Cortex M3 processor includes a simple timer 24 bit down counter The SYSTICK Timer is integrated with the NVIC and can be used to generate a SYSTICK exception exception type 15 SYSTICK Timer is controlled by four registers 15
8. EE 379 Embedded Systems and Applications Interrupts 1 Cristinel Ababei Department of Electrical Engineering University at Buffalo Spring 2013 Note This course is offered as EE 459 500 in Spring 2013 Outline Introduction NVIC and Interrupt Control Interrupt Pending Examples Interrupt Service Routines How does it work Something tells the processor core which is running the main execution flow there is an interrupt exception Core transfers control to code that needs to be executed to address the interrupt Said code returns to the main old program Some questions How do you figure out where to branch jump to If you know number the possible interrupt cases and an interrupt comes in you can just branch to a location using that number as an offset How to you ensure that you can get back to where you started Store return address to stack or dedicated register Don t we have a pipeline What about partially executed instructions Complex architectures What if we get an interrupt while we are already processing an interrupt Nested interrupts handle directly ignore prioritize What if we are in a critical section Prioritization Interrupts An interrupt is the automatic transfer of software execution in response to a hardware event that is asynchronous with the current software execution This hardware event is called a trigger and it breaks the execu
9. dler we check for the source of the interrupt Timer O can produce interrupts from many sources like Mat0 Mat1 etc and then toggle the LED Note Because the start up code gets the chip running at 100Mhz by default 1 tick or period of the timer 1 100Mhz 10 ns Hence 2423 1 ticks 0 08388609 seconds You should see the LED blinking every other 0 083 s Assignment Create a uVision project and verify this example during the next lab session 24 Example 3 Blink LED include LPC17xx h volatile uint32_t del void my_software_delay uint32_t delay int main void NVIC_EnablelRQ TIMERO_IRQn Enable Timer 0 interrupt LPC_SC gt PCONP 1 lt lt 15 Power up GPIO LPC_GPIO1 gt FIODIR 1 lt lt 29 Put P1 29 into output mode LED is connected to P1 29 while 1 my_software_delay 1 lt lt 24 Wait for about 1 second This is a software interrupt as we call it from within the program It is not triggered from the outside NVIC_SetPendingIRQ TIMERO_IRQn Software interrupt return 0 Example 3 Blink LED void TIMERO_IRQHandler void LPC_GPIO1 gt FIOPIN 1 lt lt 29 Toggle the LED void my_software_delay uint32_t delay uint32_t i for i 0 i lt delay i del i do this so that the compiler does not optimize away the loop 25 Outline Introduction NVIC and Interrupt Control Interrupt Pending Examples Interr
10. er Software Trigger Interrupt register Priority Group Interrupt Enable and Clear Enable e The Interrupt Enable register is programmed via two addresses To set the enable bit we write to the SETENA register address Toclear the enable bit you need to write to the CLRENA register address e Interrupt Set Enable and Clear Enable 0xE000E100 0xE000E11C 0xE000E180 0xE000E19C OxE000E100 Enable for external interrupt 0 31 bit 0 for interrupt 0 exception 16 bit 1 for interrupt 1 exception 17 bit 31 for interrupt 31 exception 47 Write 1 to set bit to 1 write 0 has no effect Read value indicates the current status OxE000E180 CLRENAO Clear enable for external interrupt 0 31 bit 0 for interrupt 0 bit 1 for interrupt 1 bit 31 for interrupt 31 Write 1 to clear bit to 0 write 0 has no effect Read value indicates the current enable status See page 77 80 of LPC17xx user manual for description of ISERO ISER1 and ICERO ICER1 Interrupt Pending and Clear Pending If an interrupt takes place but cannot be executed immediately e g if another higher priority interrupt handler is running it will be pended The interrupt pending status can be accessed through the Interrupt Set Pending SETPEND and Interrupt Clear Pending CLRPEND registers e Set Pending amp Clear Pending OxEQ00E200 0xE000E21C 0xE000E280 0xE000E29C OxE000E200 SETPENDO Pending for external interrupt
11. ime 12 Vector Tables When an exception takes place and is being handled by the Cortex M3 the processor will need to locate the starting address of the exception handler This information is stored in the vector table Each exception has an associated 32 bit vector that points to the memory location where the ISR that handles the exception is located Vectors are stored in ROM at the beginning of the memory Vector Table Exception vector table after power up is located at address 0x00000000 Address Exception Number Value Word Size ox00000000 B MSP initial value 0x00000004 1 0x00000008 2 NMI handler starting address 3 Reset vector program counter initial value 0x0000000C Hard fault handler starting address m ie Other handler starting address ROM location 0x00000000 has the initial stack pointer Location 0x00000004 contains the initial program counter PC which is called the reset vector Reset vector points to a function called reset handler which is the first thing executed following reset Vector table can be relocated to change interrupt handlers at runtime vector table offset register 13 Vector Table e Example of a few vectors as defined inside startup_LPC17xx s __ Vectors DCD __initial_sp Top of Stack DCD Reset Handler Reset Handler DCD NMI_Handler NMI Handler DCD HardFault Handler Hard Fault Handler External Interrupts D
12. ing e The normal case Once Interrupt Request is seen processor puts it in pending state even if hardware drops the request IPS is cleared by the hardware once we jump to the ISR s Hardware cleared interrupt request Interrupt Request Interrupt Pending Status rd Handler Mode Thread Processor Mode Mode 17 Interrupt pending e Ifthe pending status is cleared before the processor starts responding to the pended interrupt e g because pending status register is cleared while PRIMASK FAULTMASK is set to 1 the interrupt can be canceled e The pending status of the interrupt can be accessed in the NVIC and is writable so you can clear a pending interrupt or use software to pend a new interrupt by setting the pending register Interrupt Request Interrupt Pending Status f Pending status cleared by software Thread Processor Mode Mode Active status during interrupt handling e When the processor starts to execute an interrupt the interrupt becomes active and the pending bit will be cleared automatically Interrupt request x cleared by software Interrupt Request Interrupt Pending Status Interrupt i L Active Status 7 Handler Mode Interrupt returned Processor Thread Mode Mode 18 Interrupt source continues to hold e If an interrupt source continues to hold the interrupt request signal active the interru
13. low interrupts at this time postponing interrupts until a later time On the ARM Coretx M3 processor there is one interrupt enable bit for the entire interrupt system In particular to disable interrupts we set the interrupt mask bit in PRIMASK register Interrupt Programming Interrupts on the Cortex M3 are controlled by the Nested Vectored Interrupt Controller NVIC To activate an interrupt source we need to set its priority and enable that source in the NVIC Activate Set priority Enable source in NVIC This activation is in addition to the arm and enable steps discussed earlier Outline Introduction NVIC and Interrupt Control Interrupt Pending Examples Interrupt Service Routines Nested Vectored Interrupt Controller NVIC Interrupts on the Cortex M3 are controlled by the Nested Vector Interrupt Controller NVIC NVIC supports 1 to 240 external interrupt inputs commonly known as IRQs NVIC control registers are accessible as memory mapped devices NVIC can be accessed as memory location OxEQOOEO00 NVIC contains control registers and control logic for interrupt processing registers for the MPU SYSTICK Timer debugging controls In the LPC17xx the NVIC supports 35 vectored interrupts Simplified Cortex M3 Architecture Cortex M3 Processor Core System Register Bank Debug YH System Instruction Fetch Unit Interrupts ALU Inte
14. pt will be pended again at the end of the interrupt service routine Interrupt request Interrupt Interrupt request stay active pending status Interrupt active status Processor mode Interrupt return Handler mode Interrupt reentered Interrupt is pulsed several times e If an interrupt is pulsed several times before the processor starts processing it it will be treated as one single interrupt request Interrupt Interrupt pending status Interrupt active status Processor mode Multiple interrupt pulses before entering ISR request Thread mode Handler mode Interrupt return 19 Interrupt de asserted then pulsed again e If an interrupt is de asserted and then pulsed again during the interrupt service routine it will be pended again Interrupt request pulsed again Interrupt Request Interrupt Interrupt Pending Status i pended again Interrupt Active Status Handler Mode AL Interrupt returned V Thread Processor Mode Interrupt re entered Mode Outline Introduction NVIC and Interrupt Control Interrupt Pending Examples Interrupt Service Routines Procedure for setting up an interrupt 1 When the system boots up the priority group register might need to be set up By default the priority group O is used bit 7 1 of priority level is the preemption level and bit 0 is the subpriority level
15. rrupt Controller Lh a i Trace Interface Memory Interface A dl Memory Instruction Bus Protection Data Bus Unit Bus Interconnect Memory System Private and Peripherals Peripherals Debug Interface T Optional NVIC Programmers Model Address Name Type Reset OxEGOGE004 ICTR RO OxEG00E100 NVIC_LISERO RW OxEG00E11C NVIC_ISER7 OxEG00E180 NVIC_LICERO RW GE000xE19C NVIC_ICER7 OxE00E200 NVIC_ISPRO OxEG00E21C NVIC_ISPR7 OxEGOGE280 NVIC_ICPRO OxE 00E29C NVIC_ICPR7 0xEG00E300 NVIC_IABRO OxEG00E31C NVIC_IABR7 OxEGOGE400 NVIC_IPRO OxEGOOE4EC NVIC_IPRS9 From Cortex M3 Technical Reference Manual Table 6 1 NVIC registers Description Interrupt Controller Type Register ICTR Interrupt Set Enable Registers Interrupt Clear Enable Registers Interrupt Set Pending Registers Interrupt Clear Pending Registers Interrupt Active Bit Register Interrupt Prionty Register 0xA0000000 Ox9FFFFFFF Basic Interrupt Configuration e Each external interrupt has several registers associated with it Enable and clear enable registers Set pending and clear pending registers Active status Priority level e In addition a number of other registers can also affect the interrupt processing Exception masking registers PRIMASK FAULTMASK and BASEPRI Vector Table Offset regist
16. s to put the EXC_RETURN value to the program counter This will cause the processor to perform the interrupt return LDR or LDM It is possible to produce an interrupt return using the LDR instruction with PC as the destination register Credits and references e Joseph Jiu The Definitive guide to the ARM Cortex M3 2007 Chapters 7 8 9 and Appendices C D e LPC17xx User s Manual Chapters 6 23 27
17. set Value 0xE000E400 0 8 bit OxE000E401 0 8 bit Description Priority level external interrupt 0 Priority level external interrupt 1 OxE000E41F R W 0 8 bit Priority level external interrupt 31 See page 87 89 of LPC17xx user manual for description of IPRO IPR8 Interrupt Priority An exception can be carried out can be affected by the priority of the exception A higher priority smaller number in priority level exception can preempt a lower priority larger number in priority level Cortex M3 supports three fixed exception highest priority levels and up to 256 levels of programmable priority a maximum of 128 levels of preemption Most Cortex M3 chips have fewer supported levels for example 8 16 32 11 Levels of priority e Reduction of levels is implemented by cutting out the LSB part of the priority configuration registers Example of 3 bit implemented gt OOO Implemented Not implemented read as zero e In this example we have possible priority levels 0x00 high priority 0x20 0x40 0x60 0x80 OxA0O OxCO and OxE0 the lowest e LPC17xx has 32 programmable interrupt priority levels Interrupt priority e Priority can be sub divided into priority groups e Splits priority register into two halves Preempt priority indicates if an interrupts can preempt another Sub priority used if 2 interrupts of the same group arrive at the same t
18. tion flow of the main thread of the program The event causes the CPU to stop executing the current program and begin executing a special piece of code called an interrupt handler or interrupt service routine ISR Typically the ISR does some work and then resumes the interrupted program Interrupts The hardware event can either be 1 A busy to ready transition in an external I O device Caused by the external world Peripheral device e g UART input output device Reset button Timer expires Power failure System error Names exception interrupt external interrupt 2 An internal event Bus fault memory fault Aperiodic timer Div by zero illegal unsupported instruction Names exception trap system exception When the hardware needs service signified by a busy to ready state transition it will request an interrupt by setting its trigger flag Cortex M3 Interrupts e Exceptions System exceptions numbered 1 to 15 External interrupt inputs numbered from 16 up e Different numbers of external interrupt inputs from 1 to 240 and different numbers of priority levels e Value of the current running exception is indicated by The special register Interrupt Program Status Register IPSR or From the NVIC s Interrupt Control State Register the VECTACTIVE field List of system exceptions Exception Type Priority Description Reset 3 Highest
19. upt Service Routines Interrupt Service Routines ISRs e When an interrupt exception takes place a number of things happen 1 Stacking automatic pushing of eight registers contents to stack PC PSR RO R3 R12 and LR 2 Vector fetch reading the exception handler starting address from the vector table 3 Exception vector starts to execute On the entry of the exception handler a number of regs are updated stack pointer SP to new location IPSR low part of PSR with new exception number program counter PC to vector handler link register LR to special value EXC_RETURN e Several other registers get updated e Latency as short as 12 cycles 26 Interrupt Exception Exits e At the end of the exception handler an exception exit a k a interrupt return in some processors is required to restore the system status so that the interrupted program can resume normal execution e There are three ways to trigger the interrupt return sequence all of them use the special value stored in the LR in the beginning of the handler Instructions that Can be Used for Triggering Exception Return Return Instruction Description BX lt reg gt If the EXC_RETURN value is still in LR we can use the BX LR instruction to perform the interrupt return POP PC or Very often the value of LR is pushed to the stack after entering the exception POP handler We can use the POP instruction either a single POP or multiple POP
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