LC87F2R04A - ON Semiconductor
Contents
1. EE GE 1 12 Li 0 35 0 15 0 75 q I MFP24S 300mil Package Dimensions Package Dimensions unit mm typ unit mm typ 3175C build to order 3366 build to order 78 TOP VIEW SIDE VIEW BOTTOM VIEW 124 13 3 0 0 125 As E C0 14 O 4 5 d H T E ka gro o 3 0 65 015 0 33 0 22 SIDE VIEW VCT24 3 0X3 0 SSOP24 275mil E Minimum Bus Cycle e 83 3ns 12MHz at VDD 2 7V to 5 5V e 100ns LOMHz at VDD 2 2V to 5 5V Note The bus cycle time here refers to the ROM read speed E Minimum Instruction Cycle Time e 250ns 12MHz at Vpp 2 7V to 5 5V e 300ns 10MHz at Vpp 2 2V to 5 5V No A1622 2 25 LC87F2R04A WPorts Normal withstand voltage I O ports Ports whose I O direction can be designated in 1 bit units 11 P1n P20 P21 P70 Ports whose I O direction can be designated in 4 bit units 8 POn Dedicated oscillator ports input ports 2 CF1 CF2 e Reset pin 1 RES e Power pins 2 Vssl VDDI MT imers e Timer O 16 bit timer counter with a capture register Mode 0 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit2. MFP24S MFP24S SSOP24 E SSOP24 DES 1 P70 INTO TOLCP AN8 13 P16 INT2 TOIN 2 RES 14 P17 INT1 TOHCP 3 vssi 15 P20 INT4 4 CF1 16 P21 INT4 5 CF2 17 POO ANO 6 Von 18 PO1 AN1 7 P10 19 PO2 AN2 8 P11 20 P03 AN3 9 P12 21 PO4 AN4 10 P13 SO1 DBGP12 22 P05 AN5 DBGP00 11 P14 SH SB1 DBGP11 23 POG ANGIT6O DBGPO1 12 P15 SCK1 INT3 TOIN DBGP10 24 P07 T70 DBGP02 No A1622 6 25 P04 AN4 P05 AN5 DBGP00 P06 AN6 T60 DBGP01 P07 T70 DBGP02 P70 INTO TOLCP AN8 RES VCT24 3 0x3 0 Lead Halogen free Type build to order LC87F2R04A 9 o cr ot E E lt lt lt Eg e e e T e e O O O N N a N A A A a E gt E a AIS 19 12 20 11 21 3 10 LC8 F2H04A 22 9 23 8 eal OO 7 VSS1 CF1 2 CF2 3 Vppi 4 P10 5 P11 6 P17 INT1 TOHCP P16 INT2 TOIN P15 SCK1 INTS TOIN DBGP10 P14 SH SB1 DBGP 1 1 P13 S01 DBGP12 Top view VCT24 NAME VCT24 NAME 1 Vssi 13 P20 INT4 2 CF1 14 P21 INT4 3 CF2 15 POO ANO 4 VDD1 16 P01 AN1 5 P10 17 P02 AN2 6 P11 18 P03 AN3 7 P12 19 P04 AN4 8 P13 S01 DBGP12 20 P05 AN5 DBGP00 9 P14 SH SB1 DBGP11 21 P06 AN6 T60 DBGP01 10 P15 SCK1 INT3 TOIN DBGP10 22 P07 T70 DBGP02 11 P16 INT2 TOIN 23 P70 INTO TOLCP AN8 12 P17 INT1 TOHCP 24 RES No A1622 7 25 LC87F2R04A System Block Diagram Interrupt control je gt IR PLA Standby contro
3. Figure 6 Pulse Input Timing Signal Waveform No A1622 23 25 LC87F2R04A POR release voltage N b KR PORRL Reset period 100us or longer Di i Res i Reset period a i SCH ar S VDD Unknown state POUKS RES Figure 7 Waveform observed when only POR is used LVD not used RESET pin Pull up resistor RRES only e The POR function generates a reset only when power is turned on starting at the Vgs level e No stable reset will be generated if power is turned on again when the power level does not go down to the Vgs level as shown in a If such a case is anticipated use the LVD function together with the POR function or implement an external reset circuit e A reset is generated only when the power level goes down to the Vss level as shown in b and power is turned on again after this condition continues for 100us or longer LVD hysteresis width LVHYS LVD release voltage LVDET LVHYS LVD reset voltage OM LVDET 1 sage VERE DE DEE AE Me Ii Se E HR Cw 1 Ie gt Reset period e eset period Ai Unknown state i LVUKS RES Figure 8 Waveform observed when both POR and LVD functions are used RESET pin Pull up resistor RRES only e Resets are generated both when power is turned on and when the power level lowers e A hysteresis width LVHYS is provided to prevent the repetitions of reset release and entry cycles near the detection level No A1622
4. Allowable Operating Conditions at Ta 40 C to 85 Vgg1 0V LC87F2R04A Specification Parameter Symbol Pin Remarks Conditions VppIVI min typ max unit Operating Vpp 1 Vpp1 0 245us lt tCYC lt 200us 27 5 5 supply voltage Vpp 2 0 294us lt tCYC lt 200us 2 2 5 5 Note 2 1 Memory VHD Vpp1 RAM and register contents sustained sustaining in HOLD mode 1 6 supply voltage High level Vu Ports 1 2 input voltage P70 port input 2 210 5 5 0 3Vpp 0 7 VDD interrupt side Vin 2 Port 0 2 2 t0 5 5 0 3Vpp 0 7 VDD Vu Port 70 watchdog V 2 2 to 5 5 0 9V V timer side DD BD Vind CF1 RES 2 2t05 5 0 75Vpp VDD Low level Vic 1 Ports 1 2 4 0 to 5 5 Vss 0 1Vpp 0 4 input voltage P70 port input interrupt side el Yss 0 2VDD ViL 2 Port 0 4 0 to 5 5 Vss 0 15Vpp 0 4 2 2 to 4 0 Vss 0 2Vpp ViL 3 Port 70 watchdog 221055 0 8Vnn 10 timer side i B ss TODO Vip 4 CF1 RES 2 2 to 5 5 Vss 0 25Vpp Instruction tCYC 2 7 to 5 5 0 245 200 cycle time Note 2 2 dose oad 200 US Note 2 1 ibis i External FEXCF CF1 e CF2 pin open 2 7 to 5 5 0 1 12 system clock e System clock frequency division frequency ratio 1 1 2 2 to 5 5 0 1 10 e External system clock duty 50 5 MH z e CF2 pin open e System clock frequency division 3 0 to 5 5 0 2 24 4 ratio 1 2 e External system clock duty 50 5 Oscillation FmCF 1 CF1 CF2 12MHz ceramic oscillation i 2 7 to 5
5. 2 2 to 3 6 0 14 0 36 e 1 2 frequency division ratio IDDHALT 6 e HALT mode e External FmCF oscillation stopped 2 7 to 5 5 1 3 27 e Internal medium speed RC oscillation stopped e System clock set to 8MHz with frequency variable RC oscillation RCCTD 0 2 7 to 3 6 0 93 1 8 e 1 1 frequency division ratio HOLD mode IDDHOLD 1 Vpp HOLD mode 221055 0 03 25 consumption CF1 Vpp or open External clock mode current 2 2 to 3 6 0 02 5 9 Note 9 1 IDDHOLD 2 HOLD mode 5 0 0 03 1 2 Note 9 2 CF1 Vpp or open External clock mode e Ta 10 to 50 C 3 3 0 02 0 56 2 5 0 01 0 40 IDDHOLD 3 HOLD mode 221055 3 0 IE RA CF1 Vpp or open External clock mode e LVD option selected 2 2 to 3 6 2 3 10 IDDHOLD 4 HOLD mode 5 0 3 0 73 e CF1 Vpp or open External clock mode e Ta 10 to 50 C 3 3 2 3 3 4 LVD option selected 2 5 2 0 2 9 Note9 1 Values of the consumption current do not include current that flows into the output transistors and internal pull up resistors Note9 2 The consumption current values do not include operational current of LVD function if not specified No A1622 19 25 LC87F2R04A F ROM Programming Characteristics at Ta 10 C to 455 Vss1 0V Specification Parameter Symbol Pin Remarks Conditions VppIVI min typ max unit Onboard IDDFW 1 Vpp 1 e Only current of the flash block programming 2 2 to 5 5 5 10 mA current Programming tFW 1 e
6. 25 Peak output IOPL 1 P02 to P07 Per 1 applicable pin 20 current Ports 1 2 IOPL 2 POO POI Per 1 applicable pin 30 mA z IOPL 3 P70 Per 1 applicable pin 10 Mean output IOML 1 P02 to P07 Per 1 applicable pin 15 current Ports 1 2 3 Note 1 1 IOML 2 POO P01 Per 1 applicable pin 20 9 IOML 3 P70 Per 1 applicable pin 75 E Total output ZIOAL 1 P10 to P14 Total of all applicable pins 50 current ZIOAL 2 Ports 0 2 Total of all applicable pins ad P15to P17 ZIOAL 3 Ports 0 1 2 Total of all applicable pins 70 ZIOAL 4 P70 Total of all applicable pins 7 5 Power Pd max 1 MFP24S 300mil Ta 40 to 85 C 129 Dissipation Package only Pd max 2 Ta 40 to 85 C Package with thermal 229 resistance board Note 1 2 m Pd max 3 SSOP24 225mil Ta 40 to 85 C ati Package only Pd max 4 Ta 40 to 85 C Package with thermal 334 resistance board Note 1 2 Operating ambient Topr 40 85 Temperature C Storage ambient Tstg 55 4125 temperature Note 1 1 The mean output current is a mean value measured over 100ms Note 1 2 SEMI standards thermal resistance board size 76 1x114 3x1 6tmm glass epoxy is used Stresses exceeding Maximum Ratings may damage the device Maximum Ratings are stress ratings only Functional operation above the Recommended Operating Conditions is not implied Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability No A1622 12 25
7. 91V 55 width 2 01V 55 2 31V 55 2 51V 55 mV 2 81V 60 3 79V 65 4 28V 65 Detection voltage LVUKS e See Fig 8 unknown state Note 8 4 ni one iJ Low voltage TLVDW e LVDET 0 5V detection e See Fig 9 minimum Width e UR Reply sensitivity Note8 1 The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled Note8 2 LVD reset voltage specification values do not include hysteresis voltage Note8 3 LVD reset voltage may exceed its specification values when port output state changes and or when a large current flows through port Note8 4 LVD is in an unknown state before transistors start operation No A1622 17 25 LC87F2R04A Consumption Current Characteristics at Ta 40 C to 85 Vgg1 0V Pin Specification Parameter Symbol Conditions Remarks VppIV min typ max unit Normal mode IDDOP 1 Vpp1 FmCF 12MHz ceramic oscillation mode consumption e System clock set to 12MHz side 2 7 to 5 5 6 1 10 current e Internal medium speed RC oscillation Note 9 1 stopped Note 9 2 e Frequency variable RC oscillation stopped 2 7 to 3 6 3 7 6 4 e 1 1 frequency division ratio IDDOP 2 e FmCF 10MHz ceramic oscillation mode e System clock set to 10MHz side 2 2 to 5 5 5 3 9 1 e Internal medium speed RC oscillation stopped e Frequency variable RC oscillation stopped 2 2 to 3 6 3 4 5 8 e 1 1 frequency division ratio IDDOP 3 e FmCF 4MHz ceramic
8. CF2 E M Rf In Rd ca III Lc CF 77 77 Figure 1 CF Oscillator Circuit Figure 2 AC Timing Measurement Point No A1622 21 25 LC87F2R04A VDD Operating VDD lower limit OV Power supply RES Internal medium speed RC oscillation G ooo o ER EE nM MM Operating mode Unpredictable P4 Reset Ka Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal valid HOLD reset HOLD reset signal X signal absent Internal medium speed emee 111 La tmsCF CF1 CF2 i Note State HOLD Bd HALT HOLD Reset Signal and Oscillation Stabilization Time Note External oscillation circuit is selected Figure 3 Oscillation Stabilization Times No A1622 22 25 LC87F2R04A VDD RRES RES CRES 7T Note External circuits for reset may vary depending on the usage of POR and LVD Please refer to the user s manual for more information Figure 4 Reset Circuit SIOCLK l DATAIN k Dio DIT DI2 DIS DI4 Y DI5 d Die DIT DATAOUT Doo DO1 DO2 DO3 H DO4 X DO5 X DO6 DO7 477 a 485 ege tSCKL gt _1SCKH_ SIOCLK N DE MI gt DATAIN tPIL
9. Conditions EET EIER Remarks VDDIV min typ max unit HALT mode IDDHALT 1 Vpp1 e HALT mode consumption e FmCF 12MHz ceramic oscillation mode 2 7 t0 5 5 23 41 current e System clock set to 12MHz side Note 9 1 e Internal medium speed RC oscillation Note 9 2 stopped e Frequency variable RC oscillation stopped 2 7 to 3 6 1 2 1 9 e 1 1 frequency division ratio IDDHALT 2 e HALT mode e FmCF 10MHz ceramic oscillation mode 2 2t0 5 5 19 3 4 e System clock set to 10MHz side e Internal medium speed RC oscillation stopped Frequency variable RC oscillation stopped 2 2 to 3 6 1 0 1 6 e 1 1 frequency division ratio IDDHALT 3 e HALT mode e FmCF 4MHz ceramic oscillation mode 221055 13 25 e System clock set to 4MHz side e Internal medium speed RC oscillation stopped e Frequency variable RC oscillation stopped 2 2 to 3 6 0 53 1 0 e 1 1 frequency division ratio IDDHALT 4 e HALT mode mA e CF oscillation low amplifier size selected CFLAMP 1 2 2 to 5 5 0 80 1 5 e FMCF AMHZ ceramic oscillation mode e System clock set to 4MHz side e Internal medium speed RC oscillation stopped 2 2 to 3 6 0 81 0 62 e Frequency variable RC oscillation stopped e 1 4 frequency division ratio IDDHALT 5 e HALT mode e External FMCF oscillation stopped 2 2 to 5 5 0 28 0 73 e System clock set to internal medium speed RC oscillation e Frequency variable RC oscillation stopped
10. P15 See Fig 5 3 AR 8 SCKL 3 6 Low level t 5 di 2 2 to 5 5 1 u se tCYC 5 High level tSCKH 3 j pulse width Frequency tSCK 4 SCK1 P15 e CMOS output selected 2 9 e See Fig 5 Low level tSCKL 4 3 q ee Gel 2 2 to 5 5 1 2 se Wi SP ISCK O High level tSCKH 4 as pulse width Data setup time tsDI 2 SB1 P14 e Must be specified with respect ua SI1 P14 to rising edge of SIOCLK 10 01 Q A amp e See Fig 5 fo 2 2 to 5 5 Data hold time thDI 2 o 0 01 Output delay time tADO 4 SO1 P13 Must be specified with respect US SB1 P14 to falling edge of SIOCLK E Must be specified as the time 8 o Ge 1 2 tCYC 3 to the beginning of output state 2 2 to 5 5 40 05 E change in open drain output i mode e See Fig 5 Note 4 These specifications are theoretical values Add margin depending on its use Pulse Input Conditions at Ta 40 C to 85 C Vssl OV Specification Parameter Symbol Pin Remarks Conditions VppiV min typ max unit High low level tPIH 1 INTO P70 e Interrupt source flag can be set idth tPIL 1 INT1 P17 Event inputs for timer 0 or 1 are pulse widt 1 e Event inpu i 221055 1 INT2 P16 enabled INTA P20 to P21 tPIH 2 INT3 P15 when noise e Interrupt source flag can be set tPIL 2 filter time constant is e Event inputs for timer 0 are 2 2 to 5 5 2 1 1 enabled tCYC tPIH 3 INT3 P15 when noise e Interrupt source flag can be set tPIL 3 filter time constant is e Event in
11. V v 4 tO 5 voltage range SS LE Analog port IAINH VAIN Vpp 2 4 to 5 5 1 A input current IAINL VAIN Vss 2 4 to 5 5 1 d Conversion time calculation formulas 12bits AD Converter Mode TCAD Conversion time 52 AD division ratio 2 x 1 3 xtCYC 8bits AD Converter Mode TCAD Conversion time 32 AD division ratio 2 x 1 3 xtCYC External Operating supply i AD division AD conversion time d System division ratio Cycle time oscillation voltage range ratio TCAD SYSDIV tCYC f FmCF VDD ADDIV 12bit AD 8bit AD 4 0V to 5 5V 1 1 250ns 1 8 34 8us 21 5us CF 12MHz 3 0V to 5 5V 1 1 250ns 1 16 69 5us 42 8us 4 0V to 5 5V 1 1 300ns 1 8 41 8us 25 8us CF 10MHz 3 0V to 5 5V 1 1 300ns 1 16 83 4us 51 4us 3 0V to 5 5V 1 1 750ns 1 8 104 5us 64 5us CF 4MHz 2 4V to 5 5V 1 1 750ns 1 32 416 5us 256 5us Note 6 1 The quantization error 1 2LSB must be excluded from the absolute accuracy The absolute accuracy must be measured in the microcontroller s state in which no I O operations occur at the pins adjacent to the analog input channel Note 6 2 The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register s are loaded with a complete digital conversion value corresponding to the analog input value The conversion time is 2 times the normal time conversion time when e The first AD conversion is performed in the 12 bit AD
12. conversion mode after a system reset e The first AD conversion is performed after the AD conversion mode is switched from 8 bit to 12 bit conversion mode No A1622 16 25 LC87F2R04A Power on Reset POR Characteristics at Ta 40 C to 85 Vsg l 0V Specification Parameter Symbol Pin Remarks Conditions Option selected voltage min typ max unit POR release PORRL e Select from option 1 67V 1 55 1 67 1 79 voltage Note 7 1 1 97V 1 85 1 97 2 09 2 07V 1 95 2 07 2 19 2 37V 2 25 2 37 2 49 2 57V 2 45 2 57 2 69 2 87V 2 75 2 87 2 99 y 3 86V 3 73 3 86 3 99 4 35V 4 21 4 35 4 49 Detection POUKS e See Fig 7 voltage Note 7 2 0 7 0 95 unknown state Power supply PORIS e Power supply rise 100 iis rise time time from OV to 1 6V Note7 1 The POR release level can be selected out of 4 levels only when the LVD reset function is disabled Note7 2 POR is in an unknown state before transistors start operation Low Voltage Detection Reset LVD Characteristics at Ta 40 C to 85 C Neel 0V Specification Parameter Symbol Pin Remarks Conditions Option selected voltage min typ max unit LVD reset Voltage LVDET e Select from option 1 91V 1 81 1 91 2 01 Note 8 2 Note 8 1 2 01V 1 91 2 01 2 11 E Se 2 31V 2 21 2 31 2 41 2 51V 2 41 2 51 2 61 V 2 81V 2 71 2 81 2 91 3 79V 3 69 3 79 3 89 4 28V 4 18 4 28 4 38 LVD hysteresis LVHYS 1
13. counter with an 8 bit capture register Mode 2 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register Mode 3 16 bit counter with a 16 bit capture register e Timer 6 8 bit timer with a 6 bit prescaler with toggle outputs e Timer 7 8 bit timer with a 6 bit prescaler with toggle outputs ESIO e SIO1 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512 tCYC transfer clocks Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048 tCYC baudrates Mode 2 Bus mode start bit 8 data bits 2 to 512 tCYC transfer clocks Mode 3 Bus mode 2 start detect 8 data bits stop detect BAD Converter 12 bits 8 bits x 8 channels e 12 8 bits AD converter resolution selectable MRemote Control Receiver Circuit sharing pins with P73 INT3 and TOIN e Noise rejection function noise filter time constant selectable from 1 tCYC 32 tCYC 128 tCYC MWatchdog Timer e External RC watchdog timer e Interrupt and reset signals selectable Interrupts e 12 sources 8 vector addresses 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt requests of the level equal to or lower than the current interrupt are not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For inte
14. e SKK SKK Type B Application version Single ganged SANYO FWS 1 05 or later Our company LC87F2R04A Onboard SKK DBG Type B Chip data version single ganged SANYO FWS 2 22 or later For information about AF Series Flash Support Group Inc TEL 81 53 459 1050 E mail sales j fsg co jp Notel On board programmer from FSG AF9101 AF9103 and serial interface driver from Our company SIB87 together can give a PC less standalone on board programming capabilities Note2 It needs a special programming devices and applications depending on the use of programming environment Please ask FSG or Our company for the information No A1622 5 25 Pin Assignment LC87F2R04A P70 INTO TOLCP AN8 1 RES 2 Vsst L 3 cri 14 cr2 5 Vppi U 6 pio L 7 P11 0 8 p2 0O 9 P13 SO1 DBGP12 10 P14 SH SB1 DBGP11 11 P15 SCK1 INT3 TOIN DBGP10 12 LC87F2R04A 24 23 22 21 20 19 18 17 16 15 14 13 P07 T70 DBGP02 P06 AN6 T60 DBGP01 P05 AN5 DBGP00 P04 AN4 P03 AN3 P02 AN2 P0O1 AN1 POO ANO P21 INT4 P20 INT4 P17 INT1 TOHCP P16 INT2 TOIN Top view MFP24S 300mil Lead Halogen free Type discontinued SSOP24Q25mil Lead Halogen free Type SSOP24 275mil Lead Halogen free Type build to order
15. into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PS No A1622 25 25
16. on the implementation of the oscillator circuit e Oscillation is influenced by the circuit pattern layout of printed circuit board Place the oscillation related components as close to the CPU chip and to each other as possible with the shortest possible pattern length e Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another e Be sure to insert a current limiting resistor Rd so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating e The oscillator circuit constants shown above are sample characteristic values that are measured using the Our designated oscillation evaluation board Since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the IC is installed it is recommended that the user consult the resonator vendor for oscillation evaluation of the IC on a user s production board when using the IC for applications that require high oscillation accuracy For further information contact your resonator vendor or Our company Semiconductor sales representative serving your locality e It must be noted when replacing the flash ROM version of a microcontroller with a mask ROM version that their operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same CFI
17. oscillation mode e System clock set to 4MHz side 2 2 to 5 5 2 6 55 e Internal medium speed RC oscillation stopped e Frequency variable RC oscillation stopped 2 2 to 3 6 1 9 3 4 e 1 1 frequency division ratio IDDOP 4 e CF oscillation low amplifier size selected mA CFLAMP 1 e FmCF 4MHz ceramic oscillation mode e System clock set to 4MHz side e Internal medium speed RC oscillation stopped e Frequency variable RC oscillation stopped e 1 4 frequency division ratio IDDOP 5 e External FmCF oscillation stopped e System clock set to internal medium speed RC oscillation 2 2 to 5 5 1 1 2 1 2 2 to 3 6 0 56 1 1 2 2 to 5 5 0 47 1 2 e Frequency variable RC oscillation stopped 22103 6 0 28 0 65 e 1 2 frequency division ratio IDDOP 6 e External FmCF oscillation stopped e Internal medium speed RC oscillation 2 7 to 5 5 4 2 8 1 stopped e System clock set to 8MHz with frequency variable RC oscillation RCCTD 0 2 7 to 3 6 3 3 5 6 e 1 1 frequency division ratio Note9 1 Values of the consumption current do not include current that flows into the output transistors and internal pull up resistors Note9 2 The consumption current values do not include operational current of LVD function if not specified Continued on next page No A1622 18 25 LC87F2R04A Continued from preceding page Pin Specification Parameter Symbol
18. 24 25 LC87F2R04A VDD LVD release voltage su 1 LVDET 0 5V Figure 9 Low voltage detection minimum width Example of momentary power loss Voltage variation waveform ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant
19. 5 12 frequency See Fig 1 range FmCF 2 CF1 CF2 10MHz ceramic oscillation 2 2 2 to 5 5 10 Note 2 3 See Fig 1 FmCF 3 CF1 CF2 4MHz ceramic oscillation CF oscillation normal amplifier size selected 2 2 to 5 5 4 CFLAMP 0 See Fig 1 4MHz ceramic oscillation Mile CF oscillation low amplifier size 2 2 to 5 5 4 selected CFLAMP 1 See Fig 1 FmMRC Frequency variable RC oscillation 1 2 frequency division ration 2 7 to 5 5 7 6 8 0 8 4 RCCTD 0 Note 2 4 FmRC Internal medium speed RC oscillation 2 2 to 5 5 0 5 1 0 2 0 Note 2 1 Vpp must be held greater than or equal to 2 2V in the flash ROM onboard programming mode Note 2 2 Relationship between tCYC and oscillation frequency is 3 FmCF at a division ratio of 1 1 and 6 FmCF at a division ratio of 1 2 Note 2 3 See Tables 1 and 2 for the oscillation constants Note 2 4 When switching the system clock allow an oscillation stabilization time of 100us or longer after the multifrequency RC oscillator circuit transmits from the oscillation stopped to oscillation enabled state No A1622 13 25 LC87F2R04A Electrical Characteristics at Ta 40 C to 85 Neel 0V Specification Parameter Symbol Pin Remarks Conditions VppIV min typ max unit High level input HO Ports 0 1 2 Output disabled Current P70 Pull up resistor off RES VIN VDD 2 2 to 5 5 1 Including
20. Erasing time 20 30 ms time NE 2 2 to 5 5 tFW 2 Programming time 40 60 US Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator e CF oscillation normal amplifier size selected CFLAMP 0 EMURATA Oscillation I Circuit Constant Operating VISA Nominal Stabilization Time Type Oscillator Name Voltage Range Remarks Frequency C1 C2 Rf Rd VI typ max pF pF Q Q ms ms Open 680 2 2 to 5 5 0 1 0 5 12MHz SMD CSTCE12M0G52 RO 10 10 Open 1 0k 2 5 to 5 5 0 1 0 5 Open 680 2 0 to 5 5 0 1 0 5 SMD CSTCE10M0G52 RO 10 10 Open 1 0k 2 1 to 5 5 0 1 0 5 10MHz Open 680 2 2 to 5 5 0 1 0 5 LEAD CSTLS10M0G53 B0 15 15 Open 1 0k 2 4 to 5 5 0 1 0 5 Open 1 0k 1 9 to 5 5 0 1 0 5 SMD CSTCE8M00G52 RO 10 10 Open 1 5k 2 0 to 5 5 0 1 0 5 8MHz Open 1 0k 2 0 to 5 5 0 1 0 5 Internal LEAD CSTLS8M00G53 B0 15 15 Open 1 5k 2 2 to 5 5 0 1 0 5 C1 C2 Open 1 5k 1 9 to 5 5 0 1 0 5 SMD CSTCR6M00G53 RO 15 15 Open 2 2k 2 0 to 5 5 0 1 0 5 6MHz Open 1 5k 2 0 to 5 5 0 1 0 5 LEAD CSTL
21. Ordering number ENA1622B LC87F2R04A CMOS IC 4K byte FROM and 128 byte RAM integrated 8 bit 1 chip Microcontroller Overview ON Semiconductor http onsemi com The LC87F2RO4A is an 8 bit microcontroller that integrates on a single chip a number of hardware features such as 4K byte flash ROM 128 byte RAM an On chip debugger 16 bit timers counters two 8 bit timers an asynchronous synchronous SIO interface an 8 channel AD converter an internal reset and an interrupt feature Features Package Dimensions MFlash ROM unit mm typ e 4096 x 8 bits 3287 e Capable of on board programming with wide range 2 2 to 5 5V of voltage source e Block erasable in 128 byte units e Writable in 2 byte units BRAM e 128 x 9 bits MPackage Form e SSOP24 225mil Lead Halogen free type 0 5 24 6 5 44 METTUS L 0 5 0 5 0 22 e MFP24S 300mil Lead Halogen free type discontinued e SSOP24 275mil Lead Halogen free type build to order e VCT24 3mmx3mm Lead Halogen free type build to order 1 5max 1 3 0 1 0 15 SSOP24 225mil This product is licensed from Silicon Storage Technology Inc USA Semiconductor Components Industries LLC 2013 May 2013 Ver 0 65 12313HK 51712HKIM 20120426 S00006 No A1622 1 25 LC87F2R04A Package Dimensions unit mm typ 3112B discontinued
22. S6M00G53 B0 15 15 Open 2 2k 2 1 to 5 5 0 1 0 5 Open 1 5k 1 8 to 5 5 0 2 0 6 SMD CSTCR4M00G53 R0 15 15 Open 3 3k 1 9 to 5 5 0 2 0 6 4MHz Open 1 5k 1 8 to 5 5 0 2 0 6 LEAD CSTLS4M00G53 B0 15 15 Open 3 3k 1 9 to 5 5 0 2 0 6 No A1622 20 25 LC87F2R04A e CF oscillation low amplifier size selected CFLAMP 1 EMURATA Circuit Constant Operatin oe I Nominal i parang Stabilization Time Type Oscillator Name Voltage Range Remarks Frequency C1 C2 Rf Rd VI typ max pF pF 9 9 ms ms Open 1 0k 1 9 to 5 5 0 2 0 6 CSTCR4M00G53 RO 15 15 Open 2 2k 2 1 to 5 5 0 2 0 6 SMD Open 1 0k 1 8 to 5 5 0 2 0 6 CSTCR4M00G53095 RO 15 15 Open 2 2k 1 9 to 5 5 0 2 0 6 Internal 4MHz Open 1 0k 2 0 to 5 5 0 2 0 6 C1 C2 CSTLS4M00G53 B0 15 15 Open 2 2k 2 1 to 5 5 0 2 0 6 LEAD Open 1 0k 1 8 to 5 5 0 2 0 6 CSTLS4M00G53095 B0 15 15 Open 2 2k 1 9 to 5 5 0 2 0 6 The oscillation stabilization time refers to the time interval that is reguired for the oscillation to get stabilized after VDD goes above the operating voltage lower limit see Figure 3 e Time till the oscillation gets stabilized after the CPU reset state is released e Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed e Till the oscillation gets stabilized after the HOLD mode is reset Notes
23. cution on debugger e Real time RAM data monitoring function on debugger All the RAM data map can be monitored on screen when the program is running The RAM amp SFR data can be changed by screen patch when the program is running e Two channels of on chip debugger pins are available to be compatible with small pin count devices DBGPO P0 DBGPI P1 MData Security Function flash versions only e Protects the program data stored in flash memory from unauthorized read or copy Note This data security function does not necessarily provide absolute data security No A1622 4 25 MDevelopment Tools LC87F2R04A e On chip debugger TCB87 TypeB LC87F2R04A TCB87 TypeC 3 wire version LC87F2R04A HProgramming Boards Package Programming boards MFP24S 300mil W87F2GM SSOP24 225mil W87F2GS SSOP24 275mil build to order VCT24 build to order HFlash ROM Programmer Maker Model Supported Version Device AF9708 Single AF9709 AF9709B AF9709C Rev 03 11 or later LC87F2L08A including Ando Electric Co Ltd models Flash Support Group Inc E 3 FSG AF9723 AF9723B Main unit A including Ando Electric Co Ltd models Ganged AF9833 Unit including Ando Electric Co Ltd models Flash Support Group Inc AF9101 AF9103 Main unit FSG Onboard FSG Note 2 single ganged SIB87 Interface driver Our company Note 1 Our company
24. l lt le Flash ROM Lime e 8 o de g Oo S a E 2 PC RC o MRC RES ACC gt E E n WDT 8 gl B register 2 Reset circuit amp LVD POR C register SIO1 i e gt Ch Bus interface ST meo es Port O Timer 6 Port 1 Pow Timer 7 gt Port 2 lt ADC le Port 7 si RAM RAR INTO 2 Stack pointer INT3 Noise filter e e Port 2 INT4 On chip debugger No A1622 8 25 Pin Description LC87F2R04A Pin Name VO Description Option Vssi power supply pins No Vpp 1 power supply pin No Port 0 VO e 8 bit VO port P00 to P07 e VO specifiable in 4 bit units e Pull up resistors can be turned on and off in 4 bit units e HOLD reset input e Port O interrupt input e Pin Mundos Ka PO6 Timer 6 toggle output P07 Timer 7 toggle output POO ANO to PO6 AN6 AD converter input P05 DBGP00 to P07 DBGP02 On chip debugger 0 port Port 1 VO e 8 bit VO port P10 to P17 e I O specifiable in 1 bit units e Pull up resistors can be turned on and off in 1 bit units e Pin functions P13 SIO1 data output P14 SIO1 data i
25. nction General purpose input port No A1622 9 25 LC87F2R04A Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in the output mode Port Name Option sell Option type Output type Pull up resistor units of POO to P07 1 bit 1 CMOS Programmable Note 1 2 Nch open drain No P10 to P17 1 bit 1 CMOS Programmable 2 Nch open drain Programmable P20 to P21 1 bit 1 CMOS Programmable 2 Nch open drain Programmable P70 a No Nch open drain Programmable Note 1 The control of the presence or absence of the programmable pull up resistors for port 0 and the switching between low and high impedance pull up connection is exercised in nibble 4 bit units P00 to 03 or P04 to 07 User Option Table Option Name Option Type SES Flash Version Option Selected Option Selection 1 in Units of Port output type POO to P07 e 1 bit CMOS Nch open drain P10 to P17 O O 1 bit CMOS Nch open drain P20 to P21 O O 1 bit CMOS Nch open drain Program start x O 00000h address 2 01E00h Low voltage Detect function O O a Enable Use detection reset Disable Not Used funetion Detect level o o i 7 level Power on reset Power On reset level O O 8 level function 1 Mask option selection No change possible after ma
26. nput bus VO P15 SIO1 clock I O INT3 input with noise filter timer 0 event input timer OH capture input P16 INT2 input HOLD reset input timer 0 event input timer OL capture input P17 INT1 input HOLD reset input timer OH capture input Yes P15 DBGP10 to P13 DBGP12 On chip debugger 1 port Interrupt acknowledge types e Rising amp Rising Falling H level L level Falling INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable Port 2 VO e 2 bit VO port P20 to P21 e VO specifiable in 1 bit units e Pull up resistors can be turned on and off in 1 bit units e Pin functions P20 to P21 INT4 input HOLD reset input timer OL capture input timer OH capture input Interrupt acknowledge types Yes no Rising amp Rising Falling H level L level Falling INT4 enable enable enable disable disable Port 7 VO e 1 bit VO port P70 e I O specifiable in 1 bit units e Pull up resistors can be turned on and off in 1 bit units e Pin functions P70 INTO input HOLD reset input timer OL capture input watchdog timer output P70 AN8 AD converter input No Interrupt acknowledge types ne Rising amp Rising Falling H level L level Falling INTO enable enable disable enable enable RES VO External reset Input internal reset output No CF1 I e Ceramic resonator oscillator input pin No e Pin function General purpose input port CF2 VO e Ceramic resonator oscillator output pin No e Pin fu
27. output Tr s off leakage current IHO CF1 Vin VpD 2 2 to 5 5 15 Low level input ly 1 Ports 0 1 2 Output disabled p current P70 Pull up resistor off RES ViN Vss 2 2 to 5 5 1 Including output Tr s off leakage current ILE CF1 VIN Vss 2 2 to 5 5 15 High level output Vou Ports 0 1 2 loH 1mA 4 5 to 5 5 Vpp 1 voltage VoH 2 OH 0 35mA 2 7105 5 Vpp 0 4 VoH 3 OH 0 15mA 2 2 to 5 5 Vpp 0 4 Low level output VoL 1 Ports 0 1 2 loL 10mA 4 5 to 5 5 1 5 voltage VoL 2 OL 1 4mA 2 7 to 5 5 0 4 Vo OL 0 8mA 2 2 to 5 5 0 4 V VoL 4 P70 OL 1 4mA 2 7 to 5 5 0 4 VOL OL 0 8mA 2 2 to 5 5 0 4 VoL 6 P00 PO1 loL 25mA 4 5 to 5 5 1 5 VOLG OL 4mA 2 7 to 5 5 0 4 VoL 8 OL 2mA 22t0 5 5 0 4 Pull up resistance Rpu 1 Ports 0 1 2 VOH O 9VDD 4 5 to 5 5 15 35 80 P70 When Port 0 selected Rpu 2 ow impedance pull up 2 210 4 5 18 50 230 Rpu 3 Port 0 VoH 0 9VDD o When Port O selected 2 2 to 5 5 100 210 400 high impedance pull up Hysteresis voltage VHYS 1 Ports 1 2 2 7 t0 5 5 0 1Vpp P70 V VHYS 2 BES 2 2 to 5 5 0 07Vpp Pin capacitance CP All pins For pins other than that under test EG 2 210 5 5 10 pF Ta 25 C No A1622 14 25 Serial VO Characteristics at Ta 40 C to 485 Vgg1 OV Note 4 LC87F2R04A Pin Specification Parameter Symbol Conditions Remarks VppIV min typ max unit Frequency tSCK 3 SCK1
28. puts for timer 0 are 2 2 to 5 5 64 1 32 enabled tPIH 4 INT3 P15 when noise e Interrupt source flag can be set tPIL 4 filter time constant is e Event inputs for timer 0 are 2 2 to 5 5 256 1 128 enabled tPIL 5 RES e Resetting is enabled 2 2 to 5 5 200 us No A1622 15 25 LC87F2R04A AD Converter Characteristics at Ta 40 C to 85 C Vgg1 OV 12bits AD Converter Mode Specification Parameter Symbol Pin Remarks Conditions VDDIV min typ max unit Resolution N ANO POO to 2 4 to 5 5 12 bit Absolute ET AN6 P06 Note 6 1 2 7 to 5 5 16 LSB accuracy AN8 P70 2 4 to 5 5 20 Conversion time TCAD e See Conversion time calculation 4 0 to 5 5 32 115 formulas 2 7 to 5 5 64 115 us Note 6 2 2 4 to 5 5 410 425 Analog input VAIN 2 4 to 5 5 Vss VDD V voltage range Analog port IAINH VAIN Vpp 2 4 to 5 5 1 A input current IAINL VAIN Vss 2 4 to 5 5 1 E 8bits AD Converter Mode Specification Parameter Symbol Pin Remarks Conditions VppIV min typ max unit Resolution N ANO POO to 2 4 to 5 5 8 bit Absolute ET AN6 P06 Note 6 1 241055 5 LSB 4 tO 5 1 accuracy AN8 P70 Conversion time TCAD e See Conversion time calculation 4 0 to 5 5 20 90 formulas 2 7 to 5 5 40 90 us Note 6 2 2 4 to 5 5 250 265 Analog input VAIN 241055 V
29. rnal Rf resistor CF oscillation state LC87F2R04A CF2 Mask ROM version High impedance OPEN CF oscillation state LC872R04A Power Pin Treatment Recommendations VDD1 VSS1 Connect bypass capacitors that meet the following conditions between the Vpp1 and Vss1 pins e Connect among the VDDI and veel pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires making sure that the impedances between the both pins and the bypass capacitors are as possible L1 L1 L2 L2 e Connect a large capacity capacitor Cl and a small capacity capacitor C2 in parallel The capacitance of C2 should approximately 0 1 UF C1 L2 L1 Vss1 Vpp1 L1 L2 No A1622 11 25 LC87F2R04A Absolute Maximum Ratings at Ta 25 C Vgg1 0V Specification Parameter Symbol Pin Remarks Conditions VppIVI min typ max unit Maximum supply Vpp max Vpp1 03 465 voltage Input voltage VI CF1 CF2 0 3 VDD 0 3 V Input output Vio Ports 0 1 2 A Vpp 0 3 voltage P70 Peak output IOPH Ports 0 1 2 CMOS output select 40 5 current Per 1 applicable pin E Mean output IOMH Ports 0 1 2 CMOS output select 5 current Per 1 applicable pin 7 5 S Note 1 1 9 Total output XIOAH 1 P10 to P14 Total of all applicable pins 20 s current XIOAH 2 P15 to P17 Total of all applicable pins E I Ports 0 2 XIOAH 3 Ports 0 1 2 Total of all applicable pins
30. rrupts of the same level the interrupt into the smallest vector address takes precedence No Vector Address Level Interrupt Source 1 00003H XorL INTO 2 0000BH XorL INT1 3 00013H HorL INT2 TOL INT4 4 0001BH HorL INT3 5 00023H HorL TOH 6 0002BH HorL None 7 00033H HorL None 8 0003BH HorL SIO1 9 00043H HorL ADC T6 T7 10 0004BH HorL Port 0 e Priority levels X gt H gt L e Of interrupts of the same level the one with the smallest vector address takes precedence WSubroutine Stack Levels 64levels The stack is allocated in RAM No A1622 3 25 LC87F2R04A HHigh speed Multiplication Division Instructions e 16 bits x 8 bits 5 tCYC execution time e 24 bits x 16 bits 12 tCYC execution time e 16 bits 8 bits 8 tCYC execution time e 24 bits 16 bits 12 tCYC execution time Oscillation Circuits e Internal oscillation circuits Medium speed RC oscillation circuit For system clock 1MHz Multifrequency RC oscillation circuit For system clock 8MHz e External oscillation circuits Hi speed CF oscillation circuit For system clock with internal Rf MS ystem Clock Divider Function e Can run on low current e The minimum instruction cycle selectable from 300ns 600ns 1 2us 2 4us 4 8us 9 6us 19 2us 38 4us and 76 8us at a main clock rate of 10MHz Internal reset function e Power on reset POR function 1 POR reset is generated only at power on time 2 The POR release le
31. sk is completed 2 Program start address of the mask version is 00000h Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software POO to P07 Open Output low P10 to P17 Open Output low P20 to P21 Open Output low P70 Open Output low CF1 Pulled low with a 100k resistor or less General purpose input port CF2 Pulled low with a 100kQ resistor or less General purpose input port On chip Debugger Pin Connection Requirements For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 on chip debugger installation manual and LC872000 series on chip debugger pin connection requirements Notes on CF1 and CF2 Pins e When using as general purpose input ports Since the CF1 and CF2 pins are configured as CF oscillator pins at system reset time it is necessary to add a current limiting resistor of 1kQ or greater to the CF2 pin in series when using them as general purpose input pins No A1622 10 25 Differences between LC872G00 and LC872R00 Series LC87F2R04A System Reset Time State After System Reset is Released Flash ROM version CF1 XT1 Set high via the internal Rf resistor CF oscillation state LC87F2G08A CF2 XT2 Set high CF oscillation state Mask ROM version CF1 XT1 Set low via the internal Rf resistor CF oscillation state LC872G08A CF2 XT2 Set low CF oscillation state Flash ROM version CF1 Set low via the inte
32. vel can be selected from 8 levels 1 67V 1 97V 2 07V 2 37V 2 57V 2 87V 3 86V and 4 35V through option configuration e Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level 2 The use disuse of the LVD function and the low voltage threshold level 7 levels 1 91V 2 01V 2 31V 2 51V 2 81V 3 79V 4 28V Standby Function e HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation is not halted automatically 2 There are three ways of resetting the HALT mode 1 Setting the reset pin to the low level 2 System resetting by watchdog timer or low voltage detection 3 Occurrence of an interrupt e HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 The CF RC and crystal oscillators automatically stop operation 2 There are four ways of resetting the HOLD mode 1 Setting the reset pin to the lower level 2 System resetting by watchdog timer or low voltage detection 3 Having an interrupt source established at either INTO INT1 INT2 INT4 INTO and INT1 HOLD mode reset is available only when level detection is set 4 Having an interrupt source established at port 0 BOn chip Debugger e Supports software debugging with the IC mounted on the target board e Software break point setting for debugger e Stepwise exe
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