VDIS2 Handbuch - W-IE-NE
Contents
1. ON E EN_SHORT R4 10k o sw201 Schalter 10k R203 Schalter mo 22 s 10K R236 u wx st 38 85 5202 Schalter R204 sun Schalter pk amp m 2 5 10k JR205 fi 8 203 Schalter R2375N DATA mod3k Sr 0306 0307 T2 T3 T4 T5 mod gt sje e eve sw204 Taster xj aad 2 2 2 e 2 R102 10k aay an an On rom S u 2 E i vDo Ocio2. VD SEL 051 050 LWORD DTACK BERR EN INT EN SHO 5 AM4 AM3 AM2 AM1 AMO ADR DATA VDIS DTACK DISPLAY ALL ENABLE HALT RESET HALT SYSCLK SYSFAIL s ACFAIL s BBSY BG3IN OUT BG2IN OUT BGIIN OUT BGOIN OUT IACK0UT s REM open Backplane Jumper Interrupt REM when ENable INTerrupt LED is on VDis2 SELectet s by SHORT ACCES flashing light when VD on and EN DATA on AS EN DATA is a internal Switch 051 050 WRITE VME CONTROL Signals LWORD BERR s ENable INTerrupt on by Interrupt Priority is set ENoble SHOrt when internal Switch is on VME ADDRES MODIFIER VME DATA All LEDs with s are light stretched to 8 ms Seite 4 3 FUNCTIONAL DESCRIPTION 31 Introduction VDIS displays most of the VMEbus signals with colored LED s on the front panel For easy recognizing all address and data signals are arranged in four groups with different colors allowing a fast transcriptionof the bit patterns into hexadecimal digits A shining LED shows an active signal For example the LED D0 Data 0 lights if the signal on this VME bus line has a level higher than the TTL active threshold Otherwise the LED AS is on if the signal on t
3. 28 3 ijit r 28820045 D MURHunaE ENN VDIS 2 VME test and diagnostic module User manual Wiener Plein amp Baus Ltd 1 19 02 Seite 1 Table of contents Wiener Plein amp Baus Ltd 1 19 02 Seite 2 1 GENERAL INFORMATION The new VDIS 2 is a new generation of the VDIS VME bus display and diagnostic module which has been successfully used in the VME applications in industry and research in the past 12 years VDIS 2 is a helpful tool for configuration set up and test of VME systems and software debugging as well as for maintenance and service of VME hardware New features e VDIS2 is equipped with 256 Byte VME SHORT address area for extended test functions fully programmable via VME e Enlarged LED s for better display New VME SHORT area functions e Software control for all front panel switches e Interrupt Logic for test purposes e All addresses data and VME control lines are stored for each VME cycle in a register for read back e 32 bit data register for read and write tests e 32 bit test counter VDIS2 standard features e LED display for all relevant VME bus lines Data Transfer Bus D00 D31 A00 A31 AM0 AM5 LWORD WRITE AS DS0 DS1 DTACK Interrupt Bus IRQx IACK IACKIN IACKOUT Arbitration Bus BRx BGxIN BGxOUT BBSY BCLR Utility Bus SYSRESET SYSFAIL ACFAIL SYSCLK Other 5Volt 12Volt 12Volt VDIS DTACK
4. EN SHORT VDis2 SELECT EN INTERRUPT HALT e Can hold and keep visible signal groups with corresponding qualifier in certain conditions BERR BBSY DTACK e Uses signal stretcher to increase visibility of signal groups and corresponding qualifier for better display IRQ VD VDIS DTACK diagnostic mode VDIS 2 generates in case of a missing DTACK from other units the DTACK at the end of a programmable time out time in this mode the data of the previous cycle are available for read back VME READ only EH ENABLE HALT diagnostic mode records the status of all bus signals in case of a bus error and holds it until manual resetting e VDIS 2 is simply to use and transparent for any software VDIS is a standard 60 slave module main operating elements are accessible on the front panel The display elements are color coded functionally grouped Wiener Plein amp Baus Ltd 1 19 02 Seite 3 2 FRONT PANEL VIEW off by TimeOut and VD Switch ist on VDIS DTACK s POWER BCLR s BR3 s BR2 s BR s BRO s IACKIN s VME ADDRES flashing light when VDIS2 is HALT Wiener Plein amp Baus Ltd 1 19 02 VDIS2 VD DA EH RH VD CLK 5 RES SYF 2 ACF BC BBY BR BGS BR BG2 BR BG1 BR BGO IAI INT IACK IRQ7 IRQ6 IRQS IRQ4 IRQ3 IRQ2 IRQ1
5. LED The hold state HALT can only be released by pushing the RH button This enables VDIS 2 to detect the next bus error button RESET HALT releases VDIS 2 from the hold state HALT to an active ENABLE HALTmode INT button INTERRUPT sets the interrupt flip flop The interrupt is only requested if an allowed interrupt priority value 1 7 is defined in the interrupt register In this case the LED EN INT lights A reset of the interrupt flip flop 1s only possible by software SHORT MODE Wiener Plein amp Baus Ltd 1 19 02 Seite 7 3 6 Internal Switches EN SHORT switch ENABLE SHORT enables or disables the SHORT area of VDIS 2 In this mode several VDIS 2 functions as well as the front panel switch configuration can be programmed All addresses and functions are described in detail in the following chapter EN DATA switch ENABLE DATA If both VD and EN DATA are switched on VDIS 2 transfers after the time out in case of a read cycle the content of the data register onto the VME bus Following a DTACK will be generated with a delay of about 30ns In case of EN DATA OFF no data can be retrieved from VDIS 2 except the SHORT READ for VDIS parameters features Wiener Plein amp Baus Ltd 1 19 02 Seite 8 4 REMARKS 41 General Comments The VDIS 2 display does not disturb or affect the VME bus or the functionality of any VME bus module except if used in one of th
6. D08 0 D00 areg23 aregl6 A31 A01 will be stored in areg in every cycle except HALT SO HALT 7 5 Data Register 0x40 Short Adr 40 WR VME DATA Register RD VME DATA Register dreg BYTE D15 D00 dreg15 00 LB or HB WORD D15 D00 dreg15 00 LWORD D31 D00 dr g31 00 Wiener Plein amp Baus Ltd 1 19 02 Seite 15 D31 D01 will be stored in dreg in every VME cycle except HALT or SO HALT 7 6 Test Counter 0x80 Short Adr 80 RD Counter cnt WORD Clear Counter data not used D15 D00 LWORD Clear Counter data not used D31 D00 cnt15 00 cnt31 00 The content of cnt will be increased by 1 with each cnt read Wiener Plein amp Baus Ltd 1 19 02 Seite 16 8 VDIS 2 PCB LAYOUT
7. 0 N C 30 N C D 31 N C 31 N C GND N C 32 N C 5V N C not connected on VDIS 2 All signals with are active in case of level below the TTL threshold Wiener Plein amp Baus Ltd 1 19 02 Seite 19 9 3 VME bus address modifiers Adress Modifier hex Funktion 3F 3E 3D 3C 3B 3A 39 38 2D 2C x 29 28 2E 2A 20 1F 10 0C 0B 0A 09 08 00 Standard Supervisory Block Transfer Standard Supervisory Programm Access Standard Supervisory Data Access Reserved Standard Nonprivileged Block Transfer Standard Nonprivileged Programm Access Standard Nonprivileged Data Access Reserved Short Supervisory Access Reserved Short Nonprivileged Access Reserved User defined Extended Supervisory Block Transfer Extended Supervisory Programm Access Extended Supervisory Data Access Reserved Extended Nonprivileged Block Transfer Extended Nonprivileged Programm Access Extended Nonprivileged Data Access Reserved Wiener Plein amp Baus Ltd 1 19 02 Seite 20 10 NOTES Wiener Plein amp Baus Ltd 1 19 02 Seite 21
8. 4 Jumper J2 for future function D13 Jumper J1 for future function D12 SW ENDATA Switch ENDATA D11 SW RH Switch RH D10 SW EH Switch EH D09 SW DA Switch DA DO8 SW VD Switch VD D07 SO HALT DO6 X DOS X SO ENDATA D04 SO ENDATA Software ENDATA SO RH puls D03 SO RH Software RW SO EH on D02 SO EH Software EH SO DA on SO DA Software DA SO VD on SO VD Software VD Data bit 0 means off Data bit 1 means on active By the help of the control register VDIS 2 can be completely controlled via software i e it is possible to define the VDIS 2 switch settings and operation modes by the setting of the corresponding bits DOO to D04 in the control register Please note that the final function mode is a logic OR of the front panel switch state and the control register setting Wiener Plein amp Baus Ltd 1 19 02 Seite 13 VDIS 2 has an additional software HALT function SO HALT bit D07 which allows to hold the content of the data address and VME control registers unchanged This makes it possible to read back the values from the previous VME cycle from these registers The VDIS 2 status register displays the condition of all switches as well as the software register The CLPW CLOCK and POWER bit indicates a correct VME environment and is determined in the following way AND AND NOT are logic operators CLPW SCLKOK AND 5VOK AND 12VOK AND 12VOK AND NOT 5VOV SCLKOK SYSCLK is
9. 560R418 560 R414 R402 10k ZH P5 Olreso t R4t9 560 R415 R4O1 10k css 204 0205 0206 P12 Olsyro ik R42d560 R416 U404 C25 C26 2 Ojacro Lik_k421 560 R417 id BCI 560 R424560 R422 Tm 33 p BR3 560 R428560 R423 El s 5 5 gt BR2 560R42d560 R424 5 8 BRI Olss ssoR43d560 R425 0201 0203 BRO Olsco 560R430560 R426 C5 1AIO ik R432 v401 a O PP2 55 55 SW205 Tost 10k R208 n M4A5 128 64 m 32 S ester 70k R209 8 M4A3 348 160 12YC n u U304 U204 10k 1k 8434 C28 C6 IRQ7 X 435 ROG 4 36 1805 1k_ R437 x z IRQ4 X R438 55 IRQ3 R439 5 2 5 Sz wie IRQ2 1 6440 0202 n K Tk R441 e o o C3 m 63 gt 9301 SELO 560 R442 en ASO 560 R220 U210 22 E 081 5608221 88 s 050 560 R222 x LWOR 560 R223 cg Lin Lon mm 560 R224 0505 u ER Eu 5 5 R214 10k 10k R210 55 R215 10k 2 10k R211 cuim Tir R216 10k 32 10k R212 s ENSH 560 R227 ni R217 10k 10k R213 S a ANS 560 R228 m c uis d AM4 560 R229 AM3 560 R230 4 o AM2 8 2 AMI 560 R232 zoo O AMO Bess S555 2228 Ole2 0208 cvi ast K Ojos 560 R301 560 R333 ERA A30 Oloso 560 R302 560 R334 29 Olp2s 560 303 560 R335 E A28 Olo2s 560 8304 on 560 R336 5 A27 Olpe 5 5 5 560 R33
10. 7 25 e a A26 O oe 560 R306 560 6338 REGI EM A25 Olp25 560 8307 ct L n 560 R339 CV9 L_n 82 A24 Olp2s 560 R308 0317 560 R34D 0315 A23 Olp23 s60 R309 560 R341 29 n A22 Olp22 560 R510 560 R342 0305 A21 Oi Geolrsn 560 R343 A20 Oo je 560 R344 N pe M9 Ojos o 3 5 560 R345 55 M8 Ote 560 R34 560 R346 Olo z 560 8315 cig L n 560 R347 ci7 6 Olpe 560 R516 U316 560 R348 0312 M5 Opis 560 R517 560 R349 AM Olp 560 R518 560 R350 2 m M3 560 319 E 560 R351 38 2 Ojos 560 320 5 560 R352 _ An Ojon 560 R321 5 5 560 8353 5 5 cn n i AIO Olo 560 R322 x 560 R354 U308 EI 9 Ojos 560 8323 560 R355 cig E Olos 560 8324 0315 560 R356 van _ A7 Ojo 560 R325 560 R357 25 r A6 Os 560 R326 560 R358 85 AS Ojos 560 R327 560 R359 o M Ojos 560 R328 5 560 6360 5 c2 Lon O Beh 3 5 560 6361 55 65 VDIS2 0 0309 EI A2 Olo2 560 R3530 560 R362 O xi M Ot 550 R331 22 560 8363 c21 Ln ARW co A0 bo 560 R332 560 R364 U310 5 61 03 JUN 01 GE TOP Layer 1 e L 2 C1 C29 100nF 0805 CV1 CV9 4 7uF 1206 nicht best ckt Wiener Plein amp Baus Ltd 1 19 02 Seite 17 9 VME BUS REFERENCE 9 1 VME bus J1 connector P1 on the VME module is a male 96 pin DIN 41612 connector style C with 3 rows a b and c Row A Row B Row C PIN
11. Signal Name Signal Name Signal Name 1 D 00 BBSY D 08 2 BCLR D 09 3 D 02 ACFAIL D 10 4 03 BGOIN 1 5 D 04 BGOOUT D 12 6 D 05 BGIIN D 13 7 D 06 BGIOUT D 14 8 D 07 BG2IN D 15 9 GND BG2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG30UT BERR 12 DS1 BRO SYSRESET 13 DS0 BRI LWORD 14 WRITE BR2 5 15 GND BR3 23 16 DTACK AM 0 22 17 GND AM 1 21 18 AS AM 2 20 19 GND AM 3 19 20 IACK GND 18 5 IACKIN SERCLK 17 22 IACKOUT SERDAT 16 23 AMA GND A 15 24 A 07 IRQ7 14 25 06 IRQ6 13 26 05 IRQS 12 27 04 IRQ4 All 28 03 IRQ3 10 29 02 IRQ2 09 30 A 01 IRQI A 08 31 12V 5V STBY 12V 32 5V 5V 5V Wiener Plein amp Baus Ltd 1 19 02 Seite 18 92 VME bus 2 Connector P2 on the VME module is a male 96 pin DIN 41612 connector style with 3 rows a b and Row A Row B Row C PIN Signal Name Signal Name Signal Name 1 N C 5V 2 N C GND N C 3 N C RESERVED N C 4 N C A 24 N C 5 N C A 25 N C 6 N C A 26 N C 7 N C 27 N C 8 N C A 28 N C 9 N C 29 10 N C A 30 N C 11 N C A31 N C 12 N C GND N C 13 N C 5V 14 N C D 16 N C 15 N C D 17 N C 16 N C D 18 N C 17 N C D 19 N C 18 N C D 20 N C 19 N C D 21 N C 20 N C D 22 N C 21 N C D 23 N C 22 N C GND N C 23 N C D 24 N C 24 N C D 25 N C 25 N C D 26 N C 26 N C D 27 N C 27 N C D 28 N C 28 N C D 29 N C 29 N C D 3
12. active on VME backplane 5VOK 5 Volt supply gt 4 6Volt 12VOK 12 Volt supply gt 10 6 Volt 12VOK 12 Volt supply lt 10 6Volt 5VOV 5 Volt supply gt 5 5 Volt OVERVOLTAGE The status of SCLKOK and the individual power line conditions are in addition stored in the VME address register offset 0x32 see paragraph 7 4 7 2 Interrupt and Timeout Register 0x10 Short Adr Short Adr 10 WRIT w a n RD I T RD LT Register Timout bit 1 Timout bit 0 Interrupt Mode 0 RORA 1 ROAC Interrupt Priority bit 2 Interrupt Priority bit 1 Interrupt Priority bit 0 Interrupt Vector it Interrupt Vector t Interrupt Vector t Interrupt Vector t Interrupt Vector it Timout bit 1 Timout bit 0 Interrupt Mode 0 RORA 1 ROAC Interrupt Priority bit 2 Interrupt Priority bit 1 Interrupt Priority bit 0 Interrupt Vector bit Interrupt Vector bit 6 Interrupt Vector bit 5 Interrupt Vector bit 4 Interrupt Vector bit 3 2 1 0 Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector bit Interrupt Vector bit Interrupt Vector bit 7 7 VDIS 2 has interrupt capability In order to be able to generate a VME bus interrupt a valid interrupt priority value 1 7 has to be defined within bits D08 D11 This is indicated by shining INT LED In this case the interrup
13. ble to get an indication about not responded or randomly generated Interrupts by selecting the right slot number for VDIS 2 and enabled EH mode Attention The interrupt daisy chain jumper has to be open 5 6 Utility Bus Check Failures are visible by looking to the relevant LED s Shortly occurring interferences on the ACFAIL line become visible due to the VDIS 2 signal stretching In case of multi master systems it is possible to detect a multiple inducted system clock SYSCLK because of the overlay interference effects may occur shown by changing intensity of flashing of the CLK LED Wiener Plein amp Baus Ltd 1 19 02 Seite 11 6 SHORT MODE OPERATION In addition to the front panel switches VDIS 2 has to internal switches for the EN SHORT und EN DATA functions see chapter 5 2 To enable the SHORT mode the EN SHORT switch has to be in ON position and the jumper array JA08 JA15 has to be configured for the correct short base address PLEASE NOTE The EN DATA switch function is independent from the SHORT mode and does not correspond to the SHORT data read 61 SHORT mode configuration VDIS 2 can be accessed in the SHORT address mode AM 29 2D if EN SHORT ON The jumper array JA8 to 15 defines the SHORT base address as following 15 A14 A13 A12 A11 A10 9 8 VME Short address 2 Ar IE z l t t f Factory setting 0x8800 _____ Jumper open logic 1 Jumper inserted log
14. d for all signals All VDIS 2 timing parameters are as specified within the VME bus Specification ANSI IEEE STD 1014 1987 IEC 821 and 297 for VME bus Slaves The VDIS 2 signal stretcher can capture signals with a width of typically at least 10ns and display them with visible extended length 4 3 Power Consumption Voltage Line to maximum 14 Wiener Plein amp Baus Ltd 1 19 02 Seite 9 5 RECOMMENDATIONS FOR VDIS 2 USE 51 Monitoring For a permanent monitoring of the VME bus activities VDIS 2 can be added to any VME system In this case VD should be switched off Depending on the required tasks may be active Please note that some VME operating systems during initialization check the available address space until the occurrence of the first bus error Further there are VME block modes CBLT according to VME P which are terminated by a time out In these cases e detected bus error represents a legal one As described following the position of VDIS 2 in the VME crate may allow different tests 5 2 Address Data Tests It is possible to test the VME bus data and address lines for disconnections or shortages by a cycle with alternating write read operations to different addresses in the VD mode Example i write all even address and data bits are 1 other 0 i 1 write all odd address and data bits are 1 other 0 In a continues cycle a homogeneously changing pattern has to be displayed fur
15. e special diagnostic modes for trouble shooting VDIS 2 adds TTL LS load to all VME bus lines The signals DTACK and IRQx have an additional load of one 74LS641 1 VDIS 2 bridges the Daisy Chain lines BGxIN to BGxOUT Similar bridges on the VME backplane do not affect the VDIS 2 function ATTENTION The signals IACKIN and IACKOUT have to be generated and to be controlled by the VDIS2 Interrupt logic circuit The corresponding bridge on the VME backplane has to be open VDIS 2 can be used in a crate with 30 high J1 P1 backplane only too In this case all the signals of the not present P2 J2 bus D16 D31 and A24 A31 are in a non defined state Usually open lines will be displayed as active ones Some older VME backplane do not have automatic daisy chain In this case there may be slots with not connected daisy chain lines Using VDIS 2 in such a slot causes a non defined state for these signals which are then shown as non active However random distortions may occur SYSRESET clears all displayed VME bus data however SYSRESET SYSFAIL ACFAIL und SYSCLK are shown themselves 42 VDIS 2 Timing All addresses data address modifiers IACKOUT LWORD WRITE AS DSO and DS1 are in normal operation stored at the DTACK or BERR negation phase All signals are transferred with a nearly similar delay into the LATTICE FPGA For normal operation a general set up and hold time of at least 15ns is expecte
16. his VME bus line has a level which is lower than the TTL switching threshold As described following in detail some of signals will be captured by the VDIS 2 logic or will be elongated via Stretcher signal elongation settings to a visible duration Some signals are displayed staticly 32 VME bus Signal Processing and Display The following signals are captured by a DTACK or BERR Data D00 D31 Addresses A01 A31 Address modifier 5 Control signals AS DSO 051 WRITE LWORD Interrupt Bus IACK IACKIN IACKOUT In case of missing DTACK or BERR the above listed bus signals are stored at the end of DSO DS1 This may cause a discrepancy between the stored data signals and the status of the VME cycle if the address data and AM hold times of the VME master are to short control signals are displayed correctly in such cases because of storage in start registers The DTACK und BERR signals are activity stored and displayed The following signals are captured with BBSY Arbitration Bus BGOIN BGOOUT BGIIN BGIOUT BG2IN BG20UT BG3IN BG3OUT The following signals are stretched to be visible Interrupt Bus IRQI IRQ7 IACK IACKIN IACKOUT Arbitration Bus BGx BRx BCLR BBSY Utility Bus SYSRESET SYSFAIL ACFAIL BERR Wiener Plein amp Baus Ltd 1 19 02 Seite 5 SYSCLK signal VDIS 2 detects the SYSCLK signal using a differential logic circ
17. ic 0 I The factory default VDIS 2 SHORT base address is 8800 0x8800 Important Notice Please make sure that this address space is not otherwise used 6 2 Access times Write to VDIS 2 duration from AS to DTACK about 120ns Read from VDIS 2 duration from AS to DTACK about 120ns All data are available on the VME bus 60ns before DTACK Wiener Plein amp Baus Ltd 1 19 02 Seite 12 7 SHORT MODE ADDRESS MAP Short Addres Access Type WR Function DATA RD Function DATA t Offset Reset COUNTER COUNTER Cnt31 Cnt00 LO 7F DATA Reg D07 D00 D15 D08 DATA Reg D07 D00 D15 D08 10 DATA Reg D15 D00 DATA Reg D15 D00 DATA Reg D31 D00 DATA REG D31 D00 7C AddrReg A23 A16 LO 32 CLK u Power Status NOE uidet LWORD WORD 30 3C WORD LWORD AddrReg A31 A 20 2C Software Interrupt Control VME Control Signal Reg 10 1C Word Interrupt Control Reg Interrupt Control Reg Timeout Reg u Timeout Reg 00 0C Control Function STATUS Register The VDIS 2 SHORT mode covers a 256 byte address space The base address has to be defined by the help of the jumpers JA8 JA15 The access to this area is only possible if EN SHORT ON LWORD calls to word addresses A2 0 are possible however the data bits D31 D16 are not relevant in this case 7 1 Control and status register 0x00 Short Addr 00 WR Control Register D15 1 gt CLPW OK 0 Error D1
18. l In this mode SHORT calls are possible to program or to read out VDIS 2 In a special mode this LED further indicates available data after the time out in case of missing DTACK switches VD and EN DATA ON This is shown by flashing inverting of the EN SHORT LED LED HALT The A00 address line does not exist on the VME bus Because of manufacturing reasons this LED is equipped on the display and used to indicate a HALT status by a short flashing of this LED for details see chapter 3 4 Please note that the A00 LED is not labeled on the front panel The following bus lines are not displayed 5VSTBY SERCLK SERDAT und RESERVED 3 4 VDIS 2 Switches and Jumpers For easy operation the common used switches are located on the VDIS 2 front panel i e there are 3 switches VD DA EH as well as 2 push buttons RH INT which are described following in Wiener Plein amp Baus Ltd 1 19 02 Seite 6 detail Further there 2 internal switches located on the PCB behind the front panel SHORT ENABLE DATA modes These switches have to be configured before inserting VDIS 2 into the VME crate The jumper array JA8 to JA15 defines the SHORT base address All other jumpers on the PCB are for future extensions and presently not used 3 5 Front panel switches switch VDIS DTACK activates the DTACK by VDIS 2 mode in which after a pre defined time out period VDIS 2 generates the DTACK signal on the VME b
19. t flip flop becomes active by pressing the INT button on the front panel or by requesting an interrupt via software please see paragraph 7 3 VME Control and Software Interrupt Control Register IRQx becomes active according to the defined interrupt priority Please note that in case of a VME master activated interrupt the corresponding interrupt vector has to be loaded first For a description of the interrupt mode RORA ROAC please consult the VME bus manual specification Wiener Plein amp Baus Ltd 1 19 02 Seite 14 In the VDIS DTACK mode VD ON the VME bus display VDIS 2 generates the DTACK signal after time out The length of the time out period is adjustable when working in SHORT mode TO bit1 TObit0 Time to DTACK In case of de activated SHORT mode SHORT OFF the time out length is fixed to Aus 73 VME Control Register SOIC 0x20 Short Adr 20 WR Softw Interrupt Control soic RD VME Contol Register creg IACK IACKIN IACKOUT DTACK BERR AS DSO DS1 WRITE LWORD 5 2 AM1 AMO D15 D02 x 01 T Software Interrupt 00 1 Reset Interrupt FF AMO IACK will be stored in every VME cycle except HALT or SO HALT 7 4 VME Adress Register 0x30 D00 D00 areg15 01 0 areg31 01 0 SCLKOK 1 SYSCLK aktiv 5V OK 1 U gt 4 6 V 12V OK 1 U gt 10 6V 12V OK 1 U gt 10 6V 5V OverVoltage 0 U lt 5 5
20. ther it is possible to read back addresses data address modifier and control signal for comparison with the Software HALT function ATTENTION Please make sure by selecting a suitable address modifier that no other slave module in the VME system is accessed in such a test 5 3 Detection of random bus errors Operating VDIS 2 in the EH mode allows to detect random bus errors even without using a software debugger These errors are usually caused by defective hardware or by incorrect software code as not initialized or disapearing pointer Even spurious interrupts can be detected Some VME master generate only local bus errors In these circumstances VDIS 2 can not detect a VME bus problem If using VDIS 2 in the VD and EH mode however errors can be detected The time out of the VME master has to be longer gt 5us than the VDIS 2 setting to allow to displa the access address in case of a time out error 5 4 Bus allocation test For this purpose VDIS 2 has to be plugged into the slot before to the left of the VME master In this case the LED s indicate how often the bus is allocated by the particular master or other ones of the same priority level This test can not be done for the VME bus master with system controller function which is located in slot 0 of the VME crate Wiener Plein amp Baus Ltd 1 19 02 Seite 10 5 5 Interrupt Daisy Chain Check Similar to the bus allocation test it is possi
21. uit Ina VME crate with multiple master modules only one should be configured as system controller In case of more system controllers on one bus the SYSCLK signal is fed multiple times to the bus This can be indicated by flashing CLK LED s One of the VDIS 2 status bits further contains the information about the presence of the SYSCLK signal 3 3 Other LED s Power LED s The power LED s are indicating the presence of the correct voltages on the VME bus power lines 5Volt 12Volt und I2Volt All voltages are monitored with a integrated circuit MAX 8215 with the following thresholds e 5Volt LED lights if gt 4 6Volt 12Volt LED lights if Usj2y gt 10 6 Volt e I2Volt LED lights if U_j2y lt 10 6 Volt It is assumed that 5V line used by the VDIS 2 is properly working If not the case this may cause wrong logic or display operations LED VD VDIS DTACK VD indicates that VDIS 2 is working in a mode to generate DTACK after the time out period if no other VME module generates this signal The display is stretched to approximately 8 ms In case of an active HALT this LED lights permanently LED INT INT corresponds to an activated interrupt priority in the interrupt register Pressing the switch an IRQx will be generated on the VME bus LED EN SHORT Displays that the VDIS 2 short address mode is switched on The EN SHORT switch is located on the PCB behind the front pane
22. us The length of the time out is fix 4us if EN SHORT off Using the VDIS 2 in the EN SHORT mode this time can be programmed to be either 3us 2us or lus In the mode VDIS DTACK ON VDIS 2 acts on all bus transfers which are not terminated before the end of the time out This covers not only regular data transfers but also interrupt acknowledge cycles Only in active mode the EN DATA function can be used DA switch DISPLAY ALL enables the non interpretive display mode In case of DA OFF the signals of all bus transfers are interpreted by the VDIS 2 logic for correct display Thus a Byte transfer changes only the lower byte of the display or in case of al6 bit short address cycle only the A01 A15 and D00 D15 are displayed In DA ON VDIS 2 shows all registered address data and address modifier lines EH switch ENABLE HALT activates the hold on error mode In case of a bus error all data address and control signals will be stored and displayed The status of the VD will cause different actions in this mode 1 VD ON in case of missing DTACK from other VME units VDIS 2 generates the DTACK indicated by the shining red LED VD and goes into the HALT mode shown by the flashing HALT LED 2 VD OFF in case of missing DTACK the BERR will be generated on the VME bus followed by VDIS 2 going into the HALT mode which is shown by the flashing HALT
Download Pdf Manuals
Related Search