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1. BLE113 DATA SHEET Wednesday 11 September 2013 Version 1 0 Copyright 2000 2013 Bluegiga Technologies All rights reserved Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual Furthermore Bluegiga Technologies reserves the right to alter the hardware software and or specifications detailed here at any time without notice and does not make any commitment to update the information contained here Bluegiga s products are not authorized for use as critical components in life support devices or systems The WRAP is a registered trademark of Bluegiga Technologies The Bluetooth trademark is owned by the Bluetooth SIG Inc USA and is licensed to Bluegiga Technologies All other trademarks listed herein are owned by their respective owners Bluegiga Technologies Oy VERSION HISTORY Version Comment 0 1 Draft 0 2 Confidential watermark added 0 3 Marketing information updated 0 4 Current consumption recommended land pattern layout guide example schematic antenna characteristics 0 5 Minor changes 0 51 Absolute maximum ratings all supply nets must have the same voltage 0 52 Pin dimensions and recommended land pattern 0 53 FCC and IC statements 0 54 TXP vs HW config setting 0 55 Dimensions 0 56 CE MIC Japan KCC 0 57 Chapter 2 1 rephrased 0 58 Missing dimensions added to Figure 7 1 0 Preliminary datasheet 5 production datasheet N
2. Bluegiga Technologies Oy Page 10 of 30 2 3 Electrical Characteristics 2 4 Absolute Maximum Ratings Note These are absolute maximum ratings beyond which the module can be permanently damaged These are not maximum operating conditions The maximum recommended operating conditions are in the table 6 Other Terminal Voltages All supply nets must have the same voltage Table 5 Absolute Maximum Ratings 2 5 Recommended Operating Conditions Supply voltage noise should be less than 10mVpp Excessive noise at the supply voltage will reduce the RF performance Table 6 Recommended Operating Conditions 2 6 DC Characteristics Logic 0 input voltage 555 Logic 1 input voltage Logic 0 input current Input equals OV VO pin pull up and pull down resistors For detailed I O terminal characteristic and timings refer to the CC2541 datasheet available in http www ti com lit ds symlink cc2541 pdf Bluegiga Technologies Oy Page 11 of 30 2 7 Current Consumption lt txpower power 1 gt lt slow clock enable true gt lt txpower power 7 gt lt slow clock enable true gt lt txpower power 15 gt lt slow clock enable true gt lt txpower power 1 gt lt slow clock enable false gt lt txpower power 7 gt slow clock enable false gt lt txpower power 15 gt lt slow clock enable false gt lt slow clock enable true gt Transmit Ta
3. 0 80mm J 1 15 725mm 0 300mm 1 450 Figure 7 Physical dimensions pinout top view 15 73 mm 0 1mm c o c lt 9 15 mm 0 1mm 0 6 mm 5 53 mm 9 6 mm 0 6 mm Figure 8 Physical dimensions top view Bluegiga Technologies Oy Page 16 of 30 ee 0 6 mm gt 15 73 0 1 mm Figure 9 Physical dimensions side view 2 00mm 5 35mm 0 50mm 0 80mm 3 _ 0 550 1 675 J Figure 10 Recommended land pattern for BLE113 A Bluegiga Technologies Oy Page 17 of 30 4 Power On Reset and Brownout Detector BLE113 includes a power on reset POR providing correct initialization during device power on It also includes a brownout detector BOD operating on the regulated 1 8 V digital power supply only The BOD protects the memory contents during supply voltage variations which cause the regulated 1 8 V power to drop below the minimum level required by digital logic flash memory and SRAM When power is initially applied the POR and BOD hold the device in the reset state until the supply voltage rises above the power on reset and brownout voltages Bluegiga Technologies Oy Page 18 of 30 5 Design Guidelines 5 1 General Design Guidelines LE113 can be used directly with a coin cell battery Due to relatively high internal resistance of a coin cell battery it is recommended to place a 100uF capacitor in parallel with the battery The internal resist
4. 4 alternate 1 lt timer index 4 alternate 2 ITI UJ c e gt Nje EE d opsseL fJ 5 4 3 2 1 0 Refer to Profile Toolkit Developer Guide for detailed settings SS is the slave select signal when BLE113 is set as SPI slave When set as SPI master any available I O can be used as chip select signal of BLE113 Table 3 Peripheral I O Pin Mapping Bluegiga Technologies Oy Page 9 of 30 2 1 l O Ports Each I O port can be configured as an input or output When configured as input each I O port except pins P1_0 and P1_1 can also be configured with internal pull up pull down or tri state Pull down or pull up can only be configured to whole port not individual pins Unused I O pins should have defined level and not be floating See the Profile Toolkit developer guide for more information about the configuration During reset the I O pins are configured as inputs with pull ups P1_0 and P1_1 are inputs but do not have pull up or pull down 2 2 UART UART baud rate can be configured up 2 Mbps See the Profile Toolkit developer guide for more information Following table lists commonly used baud rates for BLE113 Baud rate bps Error 2400 0 14 4800 0 14 9600 0 14 14 400 0 03 19 200 0 14 28 800 0 03 38 400 0 14 57 600 0 03 76 800 0 14 115 200 0 03 230 400 0 03 Table 4 Commonly used baud rates for BLE113
5. cett e e nes i totes 29 9 Contact Information nnn e ar dice era Rudd 30 Bluegiga Technologies Oy bive sis BLE113 Bluetooth Smart Module DESCRIPTION BLE113 is a Bluetooth Smart module targeted for small and low power sensors and accessories It integrates all features required for a Bluetooth Smart application Bluetooth radio software stack and GATT based profiles BLE113 Bluetooth Smart module can also host end user applications which means no external micro controller is required in size or price constrained devices BLE113 module has flexible hardware interfaces to connect to different peripherals and sensors BLE113 can be powered directly from a standard 3V coin cell battery or pair of AAA batteries In lowest power sleep mode it consumes only 500nA and will wake up in few hundred microseconds APPLICATIONS Health and fitness sensors Medical sensors iPhone and iPad accessories Security and proximity tags Key fobs Smart home sensors and collectors Wireless keys HID keyboards and mice KEY FEATURES Bluetooth v 4 0 single mode compliant o Supports master and slave modes o Up to eight connections Integrated Bluetooth Smart stack o GATT L2CAP and SMP o Bluetooth Smart profiles Radio performance o TX power 0 dBm to 23 dBm o Receiver sensitivity 93 dBm Ultra low current consumption o Transmit 18 2 mA 0dBm o Transmit
6. conditions suivantes 1 ce dispositif ne doit pas provoquer de perturbation et 2 ce dispositif doit accepter toute perturbation y compris les perturbations qui peuvent entrainer un fonctionnement non d sir du dispositif Selon les r glementations d Industrie Canada cet metteur radio ne doit fonctionner qu avec une antenne d une typologie sp cifique et d un gain maximum ou inf rieur approuv pour l metteur par Industrie Canada Pour r duire les ventuelles perturbations radio lectriques nuisibles d autres utilisateurs le type d antenne et son gain doivent tre choisis de mani re ce que la puissance isotrope rayonn e quivalente P L R E n exc de pas les valeurs n cessaires pour obtenir une communication convenable Bluegiga Technologies Oy Page 27 of 30 Responsabilites des OEM quant a la conformite avec les reglementations de FCC et d Industrie Canada Les modules BLE113 ont t certifi s pour entrer dans la fabrication de produits exclusivement r alis s par des int grateurs dans les conditions suivantes e l antenne ou les antennes doit tre install e de fa on maintenir tout instant une distance minimum de 5 mm entre la source de radiation l antenne et toute personne physique e Le module transmetteur ne doit pas tre install ou utilis en concomitance avec une autre antenne ou un autre transmetteur Tant que ces deux conditions sont r unies il n est pas n cessaire de proc der
7. descriptors that can be located anywhere in memory Many of the hardware peripherals AES core flash controller USARTs timers ADC interface etc can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash SRAM Each CC2541 contains a unique 48 bit IEEE address that can be used as the public device address for a Bluetooth device Designers are free to use this address or provide their own as described in the Bluetooth specification The interrupt controller services a total of 18 interrupt sources divided into six interrupt groups each of which is associated with one of four interrupt priorities and sleep timer interrupt requests are serviced even if the device is in a sleep mode power modes 1 and 2 by bringing the CC2541 back to the active mode The debug interface implements a proprietary two wire serial interface that is used for in circuit debugging Through this debug interface it is possible to erase or program the entire flash memory control which oscillators are enabled stop and start execution of the user program execute instructions on the 8051 core set code breakpoints and single step through instructions in the code Using these techniques it is possible to perform in circuit debugging and external flash programming elegantly The I O controller is responsible for all general purpose I O pins The CPU can configure whether peripheral module
8. 14 3 mA OdBm DC DC o Receive 14 3 mA o Sleep mode 3 0 4 uA Flexible peripheral interfaces o UART and SPI o 126 PWM GPIO o 12 bit ADC Host interfaces o UART Programmable 8051 processor for stand alone operation Dimensions 9 15 x 15 75 x 2 1 mm Bluetooth CE FCC IC South Korea and Japan qualified Bluegiga Technologies Oy 1 BLE113 Product numbering Antenna A Internal h X BLE113 A X Firmware revision Available products and product codes Product code Description BLE113 A v1 BLE113 with integrated chip antenna Bluegiga Technologies Oy Page 6 of 30 Pinout and Terminal Description GND 36 NC 35 Reset 34 L 33 1 32 2 31 3 30 po 4 L 29 po 5 L 28 Po 6 22 po 7 L 29 GND p2 NM R amp Figure 1 BLE113 PIN RESET Active low reset po 7 GND DVDD Supply voltage upply voltage 2V 3 6V AVDD B Supply voltage upply voltage 2V 3 6V Table 1 Supply and RF Terminal Descriptions Bluegiga Technologies Oy Page 7 of 30 PIN NUMBER PIN NAME PIN TYPE DESCRIPTION ae 2820 10 P21 412 P17 re 5176 19 7 P15 _ 2 Pi4 21 P13 22 Pi2 Digital I O Configurable I O port See table 3 _26 Po7 27 Po6 28 P05 29 P04 30 P03 East P02 83 Po1 KEN 10 11 12 13 19 0 1 2 6 7 8 9 0 1 2 3 3 4 14 15 2 2 2
9. 2 2 2 2 3 3 3 3 2 2 Configurable 1 0 port with 20mA driving Digital I O capability See table 3 P1 0 2 2 be used as I C clock pin or digital I O Leave EN GAK DE dika The floating if not used If grounded disable pull up 2 pah be used as data pin or digital I O Leave EBEN Cata en agal 1O floating if not used If grounded disable pull up Table 2 Terminal Descriptions BLE113 is configurable as either SPI master or SPI slave Bluegiga Technologies Oy Page 8 of 30 PERIPHERAL OP Ba HARDWAREXMLExmple E FUNCTION EI ED CLR CR RR me A CO LS AAA aa Peel dn ESSET Ede e ee ee en ee lt usart channel 0 mode spi master alternate 1 awa Vo M o ss lt usartchannel 0 mode spi master alternate 2 TT LT BITE USART 1 SPI usart channel 0 mode uart alternate 1 lt usart channel 0 mode uart alternate 2 lt usart channel 1 mode spi_master alternate 1 lt usart channel 1 mode spi_master alternate 2 USART 1 UART usart channel 1 mode uart alternate 1 usart channel 1 mode uart alternate 2 timer index 1 alternate 1 lt timer index 1 alternate 2 lt timer index 3 alternate 1 lt timer index 3 alternate 2 timer index
10. A low residue no clean solder paste should be used due to low mounted height of the component 250 200 150 3 3 o o 100 50 Zi k2 k3 0 50 100 150 200 250 300 Figure 16 Reference reflow profile Bluegiga Technologies Oy Page 22 of 30 7 Block diagram BLE113 is based on TI s CC2541 chip Embedded 32 MHz and 32 678 kHz crystals are used for clock generation Matched balun and low pass filter provide optimal radio performance with extremely low spurious emissions Small ceramic chip antenna gives good radiation efficiency even when the module is used in layouts with very limited space CC2540 Debug interface 8051 CPU core and memory arbitrator ms Analog comparator IRQ controller Radio arbiter Radio registers Link layer engine SRAM 1 0 48 043002 0 1 Demodulator Modulator 1 Assembly variant BLE112 A or JE BLE112 E USARTA Frequency Receive synthetisizer Transmit 1 U FI 1 connector TIERE BLE112 E TIMER 3 1 Balun Chip LPF antenna I BLE112 A TIMER 4 a Figure 17 Simplified block diagram of BLE113 CPU and Memory The 8051 CPU core is a single cycle 8051 compatible core It has three different memory access buses SFR DATA and CODE XDATA a debug interface and an 18 input extended interrupt unit The memory arbiter is at the heart of the system
11. Technical support Orders WWW Head Office Finland Postal address Finland Sales Office USA Sales Office Hong Kong sales bluegiga com support bluegiga com http techforum bluegiga com orders bluegiga com www bluegiga com www bluegiga hk Phone 358 9 4355 060 Fax 358 9 4355 0660 Sinikalliontie 5A 02630 ESPOO FINLAND P O BOX 120 02631 ESPOO FINLAND Phone 1 770 291 2181 Fax 1 770 291 2183 Bluegiga Technologies Inc 3235 Satellite Boulevard Building 400 Suite 300 Duluth GA 30096 USA Phone 852 3972 2186 Bluegiga Technologies Ltd Unit 10 18 32 F Tower 1 Millennium City 1 388 Kwun Tong Road Kwun Tong Kowloon Hong Kong Bluegiga Technologies Oy Page 30 of 30
12. ance of a coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the longer the life time for the application The minimum value for the capacitor depends on the end application and the maximum transmit power used The leakage current of a 100uF capacitor is in the range of 0 5 uA to 3 uA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic capacitors Optionally TI s TPS62730 can be used to reduce the current consumption during TX RX and data processing stages TPS62730 is an ultra low power DC DC converter with by pass mode and will reduce the current consumption during transmission nominally by 20 when using 3V coin cell battery 128858888 BATTERYHOLDER AMD 82092 5 52 T PROGRAMMING INTERFACE Figure 11 Example schematic for BLE113 with a coin cell battery TPS62730 DCDC converter and an 2 accelerometer 5 2 Layout Guide Lines Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog signal traces If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emissio
13. as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus The memory arbiter has four memory access points access of which can map to one of three physical memories an SRAM flash memory and XREG SFR registers It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory The SFR bus is a common bus that connects all hardware peripherals to the memory arbiter The SFR bus also provides access to the radio registers in the radio register bank even though these are indeed mapped into XDATA memory space Bluegiga Technologies Oy Page 23 of 30 The 8 KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces The SRAM is an ultralow power SRAM that retains its contents even when the digital part is powered off power modes 2 and 3 The 128 256 KB flash block provides in circuit programmable non volatile program memory for the device and maps into the CODE and XDATA memory spaces Peripherals Writing to the flash block is performed through a flash controller that allows page wise erasure and 4 bytewise programming A versatile five channel DMA controller is available in the system accesses memory using the XDATA memory space and thus has access to all physical memories Each channel trigger priority transfer mode addressing mode source and destination pointers and transfer count is configured with DMA
14. ble 7 Current consumption of BLE113 TX Peak CUrrent mA 6 8 10 lt txpower power X gt Figure 2 BLE113 TX peak current as a function of the setting in the HW configuration file Bluegiga Technologies Oy Page 12 of 30 x E 8 10 txpower power X gt Figure 3 BLE113 TX power as a function of the setting in the HW configuration file 2 8 Antenna characteristics The antenna is monopole type of chip antenna The antenna impedance matching is optimized for 1 mm 2 mm mother board PCB thickness The radiation pattern is impacted by the layout of the mother board Typically the highest gain is towards GND plane and weakest gain away from the GND plane Figures 4 6 show the radiation pattern of BLE113 when mounted to the development board The typical efficiency of the antenna is 25 35 depending on the mother board layout Maximum gain is 0 5 dBi Bluegiga Technologies Oy Page 13 of 30 Legend 2400 00 MHz 2440 00 MHz 2485 00 MHz Figure 4 Radiation pattern of BLE113 top view Udeg Legend 2400 00 MHz 2440 00 MHz 2485 00 MHz 270deg Figure 5 Radiation pattern of BLE113 front view Bluegiga Technologies Oy Page 14 of 30 Figure 6 Radiation pattern of BLE113 side view Bluegiga Technologies Oy Page 15 of 30 3 Physical Dimensions 1 50mm 5 35mm 0 50mm 4
15. des tests suppl mentaires sur le transmetteur Cependant l int grateur est responsable des tests effectu s sur le produit final afin de se mettre en conformit avec d ventuelles exigences compl mentaires lorsque le module est install exemple missions provenant d appareils num riques exigences vis vis de p riph riques informatiques etc REMARQUE IMPORTANTE En cas d inobservance de ces conditions en ce qui concerne certaines configurations ou l emplacement du dispositif proximit d un autre metteur les autorisations de FCC et d Industrie Canada ne seront plus consid r es valables et l identification de FCC et le num ro de certification d IC ne pourront pas tre utilis s sur le produit final Dans ces cas l int grateur OEM sera charg d valuer nouveau le produit final y compris l metteur et d obtenir une autorisation ind pendante de FCC et d Industrie Canada tiquetage du produit final Le module BLE113 est tiquet avec sa propre identification FCC et son propre num ro de certification IC Si l identification FCC et le num ro de certification IC ne sont pas visibles lorsque le module est install l int rieur d un autre dispositif la partie externe du dispositif dans lequel le module est install devra galement pr senter une tiquette faisant r f rence au module inclus Dans ce cas le produit final devra tre tiquet sur une zone visible avec les informations suivantes Contie
16. e delimiter is received transmitted or the exact time at which transmission ends There are two 16 bit timer compare registers and two 24 bit overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts Timer 3 and timer 4 are 8 bit timers with timer counter PWM functionality They have a programmable prescaler an 8 bit period value and one programmable counter channel with an 8 bit compare value Each of the counter channels can be used as PWM output USART 0 and USART 1 are each configurable as either an SPI master slave or a UART They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high throughput full duplex applications Each USART has its own high precision baud rate generator thus leaving the ordinary timers Bluegiga Technologies Oy Page 24 of 30 free for other uses When configured as SPI slaves the USARTs sample the input signal using SCK directly instead of using some oversampling scheme and are thus well suited for high data rates The AES encryption decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128 bit keys The AES core also supports ECB CBC CFB OFB CTR and CBC MAC as well as hardware support for CCM The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30 kHz to 4 kHz respectively DC and audio conversions with up to eight input cha
17. m As a controller subsystem the module can be used as such with a Host Subsystem to make a Bluetooth end product without additional qualification or QDID The Bluetooth QDID of BLE13 is B021015 The Bluetooth listing can be vied from the link below https www bluetooth org tpg QLI viewQDL cfm aid 21015 8 2 FCC and IC This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Any changes or modifications not expressly approved by Bluegiga Technologies could void the user s authority to operate the equipment FCC RF Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment End users must follow the specific operating instructions for satisfying RF exposure compliance This transmitter meets both portable and mobile limits as demonstrated in the RF Exposure Analysis and should not be used closer than 5 mm from a human body in portable configuration This transmitter must not be co located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures IC Statements This device complies with Industry Canada licence exempt RSS standard s Operation is subject to the following two co
18. ments etc IMPORTANT NOTE In the event that these conditions can not be met for certain configurations or co location with another transmitter then the FCC and Industry Canada authorizations are no longer considered valid and the FCC ID and IC Certification Number can not be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter and obtaining a separate FCC and Industry Canada authorization End Product Labeling The BLE113 module is labeled with its own FCC ID and IC Certification Number If the FCC ID and IC Certification Number are not visible when the module is installed inside another device then the outside of the device into which the module is installed must also display a label referring to the enclosed module In that case the final end product must be labeled in a visible area with the following Contains Transmitter Module FCC ID QOQBLE113 Contains Transmitter Module IC 5123 A BGTBLE113 or Contains FCC ID 113 Contains IC 5123A BGTBLE113 The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change FF related parameters in the user manual of the end product 8 2 1 FCC et IC D claration d IC Ce dispositif est conforme aux normes RSS exemptes de licence d Industrie Canada Son fonctionnement est assujetti aux deux
19. n from the edges of the PCB Connect all the GND pins directly to a solid GND plane and make sure that there is a low impedance path for the return current following the signal and supply traces all the way from start to the end A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to supply voltage planes and traces and route all the signals on top and bottom layers of the PCB This arrangement will make sure that any return current follows the forward current as close as possible and any loops are minimized Bluegiga Technologies Oy Page 19 of 30 Signals GND Power Signals Figure 12 Typical 4 layer PCB construction CC KCC D Overlapping GND layers without Overlapping GND layers with GND stitching vias GND stitching vias shielding the RF energy Figure 13 Use of stitching vias to avoid emissions from the edges of the PCB 5 3 BLE113 A Layout Guide For optimal performance of the antenna place the module at the corner of the PCB as shown in the figure 14 Do not place any metal traces components battery etc within the clearance area of the antenna Connect all the GND pins directly to a solid GND plane Place the GND vias as close to the GND pins as possible Use good layout practices to avoid any excessive noise coupling to signal lines or supply voltage lines Avoid placing plastic or any other dielectric material closer than 5 mm from the anten
20. na Any dielectric closer than 5 mm from the antenna will detune the antenna to lower frequencies 3 50mm Board outline learance area Figure 14 Recommended layout for BLE113 A Bluegiga Technologies Oy Page 20 of 30 2550 Freq MHz Figure 15 Typical return loss of BLE113 A with two different mother board PCB thickness Bluegiga Technologies Oy Page 21 of 30 6 Soldering Recommendations BLE113 is compatible with industrial standard reflow profile for Pb free solders The reflow profile used is dependent on the thermal mass of the entire populated PCB heat transfer efficiency of the oven and particular type of solder paste used Consult the datasheet of particular solder paste for profile configurations Bluegiga Technologies will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering Since the profile used is process and layout dependent the optimum profile should be studied case by case Thus following recommendation should be taken as a starting point guide Refer to technical documentations of particular solder paste for profile configurations Avoid using more than one flow Reliability of the solder joint and self alignment of the component are dependent on the solder volume Minimum of 150um stencil thickness is recommended Aperture size of the stencil should be 1 1 with the pad size
21. nditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Under Industry Canada regulations this radio transmitter may only operate using an antenna of a type and maximum or lesser gain approved for the transmitter by Industry Canada To reduce potential radio interference to other users the antenna type and its gain should be so chosen that the equivalent isotropically radiated power e i r p is not more than that necessary for successful communication OEM Responsibilities to comply with FCC and Industry Canada Regulations Bluegiga Technologies Oy Page 26 of 30 The BLE113 module has been certified for integration into products only by OEM integrators under the following condition e The antenna s must be installed such that a minimum separation distance of 5 mm is maintained between the radiator antenna and all persons at all times e The transmitter module must not be co located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi transmitter product procedures As long as the two condition above is met further transmitter testing will not be required However the OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed for example digital device emissions PC peripheral require
22. nnels I O controller pins are possible The inputs can be selected as single ended or differential The reference voltage can be internal AVDD or a single ended or differential external signal The ADC also has a temperature sensor input channel The ADC can automate the process of periodic sampling or conversion over a sequence of channels The 2 module provides a digital peripheral connection with two pins and supports both master and slave operation support is compliant with the NXP 12 specification version 2 1 and supports standard mode up to 100 kbps and fast mode up to 400 kbps In addition 7 bit device addressing modes are supported as well as master and slave modes The ultralow power analog comparator enables applications to wake up from PM2 or PM3 based on an analog signal Both inputs are brought out to pins the reference voltage must be provided externally The comparator output is connected to the I O controller interrupt detector and can be treated by the MCU as a regular I O pin interrupt RF front end RF front end includes combined matched balun and low pass filter and ceramic chip antenna with matching network Optimal matching combined with effective low pass filter provides extremely low in band spurious emissions and harmonics Bluegiga Technologies Oy Page 25 of 30 8 Certifications BLE113 is compliant to the following specifications 8 1 Bluetooth BLE113 is BT qualified as a controller subsyste
23. nt module metteur identification FCC QOQBLE113 Contient module metteur IC 5123A BGTBLE113 ou Contient identification FCC QOQBLE113 lt Contient IC 5123A BGTBLE113 gt Dans le guide d utilisation du produit final int grateur OEM doit s abstenir de fournir des informations l utilisateur final portant sur les proc dures suivre pour installer ou retirer ce module RF ou pour changer les parametres RF Bluegiga Technologies Oy Page 28 of 30 8 3 CE BLE113 is conformity with the following standards SAFETY e EN 60950 1 2006 A11 2009 A1 2010 A12 2011 EMC Art 3 1 a e EN 301 489 1 v 1 9 2 e EN 301 489 17 V2 2 1 o Radiated electric field immunity EN 61000 4 3 2006 SPECTRUM Art 3 2 e EN 300 328 v1 7 1 o Equivalent isotropic radiated power o Maximum spectral power density e EN 300 328 V1 8 1 o Occupied channel bandwidth o Transmitter unwanted spurious emissions in the out of band domain o Transmitter unwanted spurious emissions in the spurious domain o Receiver spurious emissions 8 4 MIC Japan BLE113 is certified as a module with type certification number 007 AB0103 As a certified module BLE113 can be integrated to an end product without a need for additional MIC Japan certification of the end product 8 5 KCC Korea BLE113 has type certification in Korea with certification number KCC CRM BGT BLE113 Bluegiga Technologies Oy Page 29 of 30 9 Contact Information Sales
24. o changes Bluegiga Technologies Oy TABLE OF CONTENTS 1 BEET S Product Umber ims ANAN KANA NID rene AGANG ANG 6 2 Terminal Description icici aaa mate ete pan haba 7 2 1 VO POLLS Y eode aaa PAENG on dana elon ed ee ee hos 10 2 27 AA 10 2 3 Electrical Characteristics siens 11 2 4 Absolute Maximum Ratings aas saa a Nga mm er tn dt fonts 11 2 5 Recommended Operating Conditions is 11 262 DC CharacteristiCs anakan RA 11 247 Gurrent Gohns mptiolts zt PANA PDA PA andre annee ane ent 12 2 8 Antenna characteristics eissir tee np beca MO 13 3 Physical Dimensions if steel JA BAEN EN dere PRA gu 16 4 Power On Reset and Brownout Detector issus 18 5 Design Guidelines s n hates espiritu ise 19 5 1 General Design Guidelines 19 5 2 Eayout Guide Lines ia saih aie di NAA eie aa Ha 19 5 3 IBEETT9S A Layout Lu MARANAN N aR 20 6 Soldering Recommendations iii 22 7 BlOCK ADANG aito nr e eue E 23 6 C rtifications akak ag Mn 26 8 1 Bluetooth eren aaa a a A E A re 26 8 2 POC rail Ge a PERDE 26 Macc ETE IM 29 8 4 MIG Japa mie NANA NBA TAGA pe fr p Hate un eet Mere hd ees 29 8 5 KCC Korea co ete
25. s control certain pins or whether they are under software control and if so whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected Each peripheral that connects to the I O pins can choose between two different I O pin locations to ensure flexibility in various applications The sleep timer is an ultra low power timer that uses an external 32 768 kHz crystal oscillator The sleep timer runs continuously in all operating modes except power mode 3 Typical applications of this timer are as a real time counter or as a wake up timer to exit power modes 1 or 2 Timer 1 is a 16 bit timer with timer counter PWM functionality It has a programmable prescaler a 16 bit period value and five individually programmable counter capture channels each with a 16 bit compare value Each of the counter capture channels can be used as a PWM output or to capture the timing of edges on input signals It can also be configured in IR generation mode where it counts timer 3 periods and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction Timer 2 is a 40 bit timer used by the Bluetooth low energy stack It has a 16 bit counter with a configurable timer period and a 24 bit overflow counter that can be used to keep track of the number of periods that have transpired A 40 bit capture register is also used to record the exact time at which a start of fram

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