User Manual
Contents
1. Input Output Input Input Input Input 7 i 1 Input 1 1 1 Input 1 1 Input Input Mode 0 Basic Input RD Mode 0 Basic Output WR S A1 A0 OUTPUT Mode 0 Configurations CONTROL WORD 0 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A i CONTROL WORD 1 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A i PA7 PAO PB7 PBO PA7 PAO PCO PB7 PBO 82C55A CONTROL WORD 2 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A CONTROL WORD 3 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A d PA7 PC3 PCO PB7 PBO PA7 PC3 PCO PB7 PBO Mode 0 Configurations Continued CONTROL WORD 4 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A CONTROL WORD 5 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A al CONTROL WORD 6 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A CONTROL WORD 7 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A il PA7 PAO PCO PB7 PBO PA7 PAO PCO PB7 PBO PA7 PAO PC7 PC4 PC3 PCO PB7 PBO PA7 PAO PC7 PC4 PC3 PCO PB7 PBO 82C55A CONTROL WORD 8 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A dl CONTROL WORD 9 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A i CONTROL WORD 10 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A CONTROL WORD 112. 1 0 OUTPUT PORT B 1 INPUT 0 OUTPUT GROUP B MODE 0 MODE 0 1 MODE 1 FIGURE 11 MODE CONTROL WORD FIGURE 12 MODE 2 DATA FROM CPU TO 82C55A tSIB tAD gt tKD tPS gt PERIPHERAL a ge idae E EE EE BUS tPH gt tRIB gt DATA FROM DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU NOTE Any sequence where WR occurs before and STB occurs before RD is permissible INTR IBF MASK e STB RD OBF e MASK e ACK e WR FIGURE 13 MODE 2 BI DIRECTIONAL 11 MODE 2 AND MODE 0 INPUT CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO PC2 PCO 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 OUTPUT CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO LELO EE PC3 PA7 PAO PC7 PC6 PC4 PC5 PC2 PCO PB7 PBO PC3 PA7 PAO PC7 PC6 PC4 5 PB7 PBO PC1 PC2 PCO 82C55A ODE 2 AND MODE 0 OUTPUT CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO AA PC2 PCO 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO HAN FIGURE 14 MODE 2 COMBINATIONS 12 PC3 PA7 PAO PC7 PC6 PC4 PC5 PC2 PCO PB7 PBO PC3 PA7 PAO PC7 PC6 PC4 PC5 PB7 PBO PC2 PC1 PCO 82 55 MODE DEFINITION SUMMARY Special Mode Combination Considerations There are several combinations of modes possible For any
3. 2 IRQ2 All three interrupt sources can be set to the same level if desired However only one pulldown resistor should be installed for each interrupt level Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 7 6 Register Base Function Comments 0 DIO port 1A 0 are 82C55 1 registers 1 DIO port 1B 2 DIO port 1C 3 DIO port 1 configuration register 4 DIO port 2A 4 7 are 82C55 2 registers 5 DIO port 2B 6 DIO port 2C 7 DIO port 2 configuration register 8 Counter timer 0 data 8 11 are 82C54 registers 9 Counter timer 1 data 10 Counter timer 2 data 11 Counter timer mode configuration register 12 Counter timer input configuration register 13 maps to register 12 14 Interrupt configuration register 15 maps to register 14 Note that locations 12 and 13 both map to the same physical register on Onyx MM Likewise locations 14 and 15 both map to the same physical register on the board Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 8 7 Register definitions Base 0 Digital Register 82C55 no 1 1A7 1A0 Digital I O port 1 port A on 82C55 no 1 Base 1 Digital I O Register B 82C55 no 1 1 7 1 0 Digital port 1B port on 82C55 no 1 Base 2 Digital I O Register C 82C55 no 1 1 7 1 0 Digital port 1C port C 82C55 no 1 Base 4 Digital I O Register A 82C55 no 2 Bit Name 2A7 2A0 Digital I O port 2A port A on 82C5
4. combination some or all of Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 17 Through a Write Port command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output programmed as an output in Mode 1 group or to change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port Cea Bit command any Port C line programmed as an output including IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C fare not affected by a Set Reset Port C Bit command Writing to the correspond ing Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illustrated in Figure 17 13 INPUT CONFIGURATION D7 D6 D5 D4 D3 D2 D1 DO GROUP A GROUP B OUTPUT CONFIGURATION D7 D6 D5 D
5. 50 pin 2x25 headers contain 24 digital lines each and 5 ground and a third 14 pin 2x7 header provides the counter timer signals external interrupt and 5 ground J2 with 24 digital lines is on the right side of the module in the standard PC 104 position J3 with 24 additional digital I O lines is on the left side of the module and J4 with the counter timer and interrupt signals is on the top edge of the module The bottom edge of the module is defined as the edge with the PC 104 ISA bus connectors All signals are TTL compatible The boards operate on 5V power supply only Digital I O 48 TTL digital I O lines are provided by 2 82C55 chips 24 per chip Each line can source 2 5mA in a logic 0 state and sink 2 5mA in a logic 1 state I O lines are unbuffered i e there is a direct connection between the 82C55 and the I O header Bit CO of each 82C55 can be used to generate an interrupt on the PC bus see Interrupts below All digital I O lines are connected to 5V through 10K pull up resistors Digital I O lines are accessed through two 50 pin headers J3 and J4 with 24 lines one 82C55 on each header See page 8 for I O header pinouts Counter Timer I O Onyx MM contains three 16 bit counter timers provided by an 82C54 chip Each counter timer has an input pin a gate pin and an output pin The input pin responds to positive edges The gate pin is active high a counter will count whenever it
6. D7 D6 D5 D4 D3 D2 D1 DO A 82C55A Mode 0 Configurations Continued CONTROL WORD 12 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A j CONTROL WORD 13 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A al Operating Modes Mode 1 Strobed Input Output This functional configura tion provides a means for transferring I O data to or from a specified port in conjunction with strobes or hand shaking 82C55A CONTROL WORD 14 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A dl CONTROL WORD 15 D7 D6 D5 D4 D3 D2 D1 DO A 82C55A i CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO signals In mode 1 port A and port B use the lines on port C to generate or accept these hand shaking signals Mode 1 Basic Function Definitions Two Groups Group A and Group B Each group contains one 8 bit port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched PC6 PC7 1 0 OUTPUT The 4 bit port is used for control and status of the 8 bit port Input Control Signal Definition Figures 6 and 7 STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO DDD DIT P loaded into the input latch in essence and acknowledg ment IBF is set by STB input being low and is reset by the rising
7. edge of the RD input FIGURE 6 MODE 1 INPUT 82 55 INPUT FROM PERIPHERAL gt FIGURE 7 MODE 1 STROBED INPUT INTR Interrupt Request A high on this output can be used to interrupt the CPU when and input device is requesting service INTR is set by the condition STB is a one IBF is a one and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to request service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B Controlled by bit set reset of PC2 Output Control Signal Definition Figure 8 and 9 OBF Output Buffer Full F F The OBF output will go low to indicate that the CPU has written data out to be specified port This does not mean valid data is sent out of the part at this time since OBF can go true before data is available Data is guaranteed valid at the rising edge of OBF See Note 1 The OBF F F will be set by the rising edge of the WR input and reset by ACK input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted In essence a response from the peripheral device indicating that it is ready to accept data See Note 1 INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR i
8. equal to or greater than existing functionally equivalent products at Ordering Information a fraction of the power PART NUMBERS TEMPERATURE sur PACKAGE RANGE CP82C55A 5 CP82C55A OG to 70 E40 6 40 La PDIP ES IP82C55A 5 IP82C55A 407C to 85 E40 6 5 65820555 5007455 a CS82C55A 5 582 55 44 Ld PLCC 0 C to 70 C N44 65 IS82C55A 5 IS82C55A 40 C to 85 C N44 65 CD82C55A 5 CD82C55A 09C to 70 C F40 6 COSE SS m ID82C55A 5 ID82C55A CERDIP 40 C to 85 C F40 6 MD82C55A 5 B MD82C55A B 559C to 125 C 40 6 840660104 8406602QA SMD F40 6 MR82C55A 5 B MR82C55A B lenis 55 C to 125 C 8406601 XA 8406602XA SMD TT J44 A Pinouts 82C55A DIP 82C55A CLCC 82C55A PLCC TOP VIEW TOP VIEW TOP VIEW Q v c 39 RESET CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures File Number 2969 2 http www intersil com or 407 727 9207 Copyright Intersil Corporation 1999 1 82 55 Pin Description PIN SYMBOL NUMBER TYPE DESCRIPTION Vcc 26 Vcc The 5V power supply pin A 0 1uF capacitor between pins 26 and 7 is recommended for decoupling 00 07 27 34 DATA BUS The Data Bus lines are bidirectional three state pins connected to the system data bus RESET A high on this input clears the control register and all ports A B C are set to the input mode with the Bus Hold circuitry t
9. to almost any structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display compu tational results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple logical approach will surface The design of the 82C55A has taken into account things such as efficient PC board layout control signal defi nition vs PC layout and complete functional flexibility to sup port almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Figure 5 Any of the eight bits of Port C can be Set or Reset using a single Output instruction This feature reduces software requirements in control based applications When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were output ports CONTROL WORD 27 0605 Ba ps bs og X x X BIT SET RESET 1 SET 0 RESET BIT SELECT 0 1 2 3 4 5 617 0 1 0 1 0 1 0 1 0 0 1 1 oo 1 1 81 1 1 11 B2 BIT SET RESET FLAG 0 ACTIVE FIGURE 5 BIT SET RESET FORMAT Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 con
10. 4 D3 D2 D1 INTEA INTRA INTEB OBFB INTRB GROUP GROUP FIGURE 15 MODE 1 STATUS WORD FORMAT D7 D6 D5 D4 D3 D2 D1 DO EAS ES GROUP A GROUP B Defined by Mode 0 or Mode 1 Selection FIGURE 16 MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port A B or C can sink or source 2 5mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 82 55 Reading Port Status Figures 15 and 16 In Mode 0 Port C transfers data to or from the peripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or accepts hand shaking signals with the peripheral device Reading the contents of Port C allows the programmer to test or verify the status of each peripheral device and change the program flow accordingly There is not special instruction to read the status information from Port C A normal read operation of Port C is executed to perform this function INTERRUPT ALTERNATE PORT C ENABLE FLAG POSITION PIN SIGNAL MODE INTE ACKB Output Mode 1 or STBB Input Mode 1 INTE A2 c STBA Input Mode 1 or INTE A1 ACKA Output Mode 1 or Mode 2 Mode 2 FIGURE 17 INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 INTERRUPT REQUEST MODE 1 OUTPUT DATA READY ACK PAPER FEED FORWARD REV 82C55A MODE 1 OUTPUT INTERRUPT REQUEST Applications o
11. 4 DIAMOND SYSTEMS CORPORATION PC 104 Format Counter Timer amp Digital I O Module User Manual V1 4 Copyright 2001 Diamond Systems Corporation 8430 D Central Ave Newark CA 94560 USA Tel 510 456 7800 Fax 510 456 7878 techinfo diamondsystems com Table of Contents 1 General Information and 5 3 2 Onyx MM Board Dri Ra 5 3 LO Header PINGUS atril O ien 6 4 Base Address 7 5 Interrupt Gonfiguration toten 7 SM CS TL IIo 8 7 Register MON ed lado 9 8 Circuit Schematic 13 9 Interrupt Circuit 14 0 lt 5 15 User Manual v1 4 2001 Diamond Systems Corporation 2 1 General Information and Features ONYX MM is a PC 104 compliant module with 48 digital I O lines 16 bit counter timers and 3 interrupts It is an 8 bit module so it does not contain the 16 bit expansion bus connector This connector is available as an option by requesting the B16 suffix when ordering Three right angle pin headers are provided for I O Two identical
12. 5 no 2 Base 5 Digital I O Register 82C55 2 Bit Name 2B7 2B0 Digital I O port 2B port on 82C55 no 2 Base 6 Digital Register C 82C55 no 2 Bit Name 2C7 2C0 Digital I O port 2C port on 82C55 2 Onyx MM User Manual v1 4 2001 Diamond Systems Corporation Base 3 Digital I O Configuration Register 82 55 no 1 Base 7 Digital I O Configuration Register 82C55 no 2 These control registers determine the direction and mode of the 82C55 digital I O lines The diagram below comes from the 82C55 chip datasheet which is included at the back of this manual Base 3 is the control register for chip 1 and Base 7 is the control register for chip 2 Most applications use the simple I O configuration in which bit 7 is set to 1 and the Mode is set to 0 for all ports Here is a list of common configuration register control bytes Configuration Byte Hex Decimal Port A 9B 155 Input 92 146 Input 99 153 Input 90 144 Input 8B 139 Output 82 130 Output 89 137 Output 80 128 Output User Manual v1 4 Port B Port C both halves Input Input Input Output Output Input Output Output Input Input Input Output Output Input Output Output GROUP B PORT C LOWER 1 0 OUTPUT PORT 1 INPUT 0 OUTPUT MODE SELECTION 0 0 MODE 1 1 GROUP 1 IN 0 OUTPUT PORT C UPPER PUT PORTA 1 INP
13. Card type Temperature range Onyx MM User Manual v1 4 3 1K resistor selectable via jumper on each interrupt 2 7 3 550 x 3 775 5 0VDC 10 200mA typical all outputs open 8 bit PC 104 bus compliant 40 85 operating and storage 2001 Diamond Systems Corporation 15 intens 82C55A CMOS Programmable June 1998 Peripheral Interface Features Description Pin Compatible with NMOS 8255A The Intersil 82C55A is high performance CMOS version of the industry standard 8255A and is manufactured using self aligned silicon gate CMOS process Scaled SAJI IV It Fully TTL Compatible is a general purpose programmable I O device which may be p used with many different microprocessors There are 24 I O High Speed No Wait State Operation with 5MHz and pins which may be individually programmed in 2 groups of 8MHz 80C86 and 80C88 12 and used in 3 major modes of operation The high Direct Bit Set Reset Capability performance and industry standard configuration of the 82C55A make it compatible with the 80C86 80C88 and other microprocessors 24 Programmable I O Pins Enhanced Control Word Read Capability L7 Process Static CMOS circuit design insures low operating power TTL 2 5mA Drive Capability on All I O Ports compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull up resistors The Low Standby Power ICCSB Intersil advanced SAJI process results in performance
14. UT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE O 2001 Diamond Systems Corporation 10 Base 8 Counter Timer 0 Data 07 00 Divisor bits 7 0 or 15 8 Base 9 Counter Timer 1 Data Bit Name 07 00 Divisor bits 7 0 or 15 8 Base 10 Counter Timer 2 Data 07 00 Divisor bits 7 0 or 15 8 Base 11 Counter Timer Configuration The diagram below is from the 82C54 datasheet which is included at the back of this manual 07 06 05 D4 Ds D Do sco Rwo Bco SC Select Counter M MODE SC1 SCO M2 M1 MO 0 Select Counter 0 0 0 Mode 0 1 Select Counter 1 0 1 Mode 1 1 0 Select Counter 2 X 1 0 Mode 2 1 1 Read Back Command X 1 1 Mode 3 See Read Operations 1 0 4 RW Read Write 1 0 1 5 RW1 RWO BCD 0 0 Counter Latch Command see Read Operations 0 Binary Counter 16 bits 0 1 Read Write least significant byte only 1 Binary Coded Decimal BCD Counter 1 0 Read Write most significant byte only 4 Decades 1 1 Read Write least significant byte first then most significant byte Onyx MM User Manual v1 4 O 2001 Diamond Systems Corporation The registers described below are built in to the circuitry and are separate from the 82C55 and 82C54 chips In the register maps below blank locations are unused See the acc
15. al in pinout They provide 24 digital I O lines 5 and ground Pin 1 of J3 is in the upper right corner of the board and pin 1 of J4 is in the lower left corner A7 Gnd A6 Gnd 5 4 2 1 7 C6 Gnd C5 Gnd C4 Gnd C3 Gnd C2 Gnd C1 Gnd CO Gnd B7 Gnd B6 Gnd B5 Gnd B4 Gnd B3 Gnd B2 Gnd B1 Gnd BO Gnd 45 Gnd J5 Counter Timer and Interrupt Header This header is a 14 pin header with all counter timer signals the external interrupt pin 5 and ground In 0 In 1 Gate 0 Gate 1 Out 0 Out 1 In 2 External Interrupt Gate 2 Gnd Out 2 Gnd 5 Gnd Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 4 Base Address Configuration ONYX MM s base address is set with header J6 located at the lower right corner of the board Each of the six pairs of pins on J6 corresponds to a different address bit A pair left open is equal to a 1 anda pair with a jumper installed is equal to a 0 The header is used to select address bits 9 4 resulting in an 16 byte I O decode The leftmost pair selects address bit A9 and the rightmost pair selects address bit A4 Although any 16 byte location is selectable certain locations are reserved or may cause conflicts The table below lists recommended base address settings for ONYX MM The default setting is 300 Hex Open means an open position and Inst means a position with a jumper installed Base Address Header J6 Pos
16. circuit configuration and how the interrupt configuration register controls it See the control register description on page 12 INT J 82C55 1 Ca J3 31 QUT J5 5 SRCA INT 1 J8 82C55 2 BIT J4 31 QUT 1 05 6 5 1 INT 2 J9 EXTERNAL INT J5 9 QUT 2 25 11 SRC2 INTE2 UNDERLINE INDICATES CONTROL REGISTER BIT J5 11 PARENTHESES INDICATE 1 0 HEADER AND PIN NO Onyx MM User Manual v1 4 O 2001 Diamond Systems Corporation 14 10 Specifications Counter Timer Circuitry Chip Counter timers Maximum input frequency On board oscillator Signal type Input voltage all inputs Low High Input current Output voltage all outputs Low High Output current Pullup resistors 82C54 2 3 16 bits wide 10MHz 4MHz 01 100 ppm TTL 0 5V min 0 8V max 2 0V min 5 5V max 200A max low 2A max high 0 0V min 0 4V max 3 0V min Vcc 0 4V max 2 5 max each line 10K all input lines Digital Circuitry Chip Number of I O lines Direction Input voltage Low High Output voltage Low High Output current Pullup resistors 82C55A x2 48 All lines programmable for input or output in groups of 4 8 0 5V min 0 8V max 2 0V min 5 5V max 0 0V min 0 4V max 3 0V min Vcc 0 4V max 2 5mA max each line 10K all lines Interrupt Circuitry No of interrupts Pull down resistor Interrupt levels General Dimensions Power supply Vcc
17. f the 82C55A The 82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system It represents the optimum use of available pins and flexible enough to inter face almost any I O device without the need for additional external logic Each peripheral device in a microcomputer system usually has a service routine associated with it The routine manages the software interface between the device and the CPU The functional definition of the 82C55A is programmed by the I O service routine and becomes an extension of the system software By examining the I O devices interface characteristics for both data transfer and timing and matching this information to the examples and tables in the detailed operational description a control word can easily be developed to initialize the 82C55A to exactly fit the application Figures 18 through 24 present a few examples of typical applications of the 82C55A HIGH SPEED PRINTER HAMMER RELAYS PAPER FEED FORWARD REV RIBBON CARRIAGE SEN CONTROL LOGIC AND DRIVERS FIGURE 18 PRINTER INTERFACE 14
18. g the output is in high impedance mode and the resistor pulls it down to a logic 0 state Interrupt sources are programmable Interrupts can be generated from both digital I O and counter timer signals as follows Interrupt no 1 CO from 82C55 1 or Counter 0 output Interrupt no 2 Bit CO from 82C55 2 or Counter 1 output Interrupt no 3 External interrupt pin or Counter 2 output Interrupts are enabled and disabled under software control by manipulating a control register Block Diagram ONYX MM BLOCK DIAGRAM 5 DATA co 232 lt cc E 24 DIGITAL 1 0 ADDR INTERFACE 24 CTRL LOGIC UM ITAL COUNTER y OUTPUTS 3 INTERRUPTS OG E en COUNTER INTERRUPT INPUTS AG CONFIGURATION COUNTER a au LOGIC GATES HL OSC EXTERNAL TRIGGER PC 104 BUS Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 4 2 Onyx MM Board Drawing 96 BASE INT LEVEL 987654 ltem Description J1 PC 104 bus connector J3 Digital I O ports 1 1B 1C J4 Digital I O ports 2A 2B 2C J5 Counter timer signals J6 Board base address configuration J7 Interrupt O configuration J8 Interrupt 1 configuration J9 Interrupt 2 configuration Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 3 I O Header Pinouts 93 Digital I O Header for 82C55 1 44 Digital I O Header for 82C55 2 Each of these headers is identic
19. he control register to 9Bh and all ports A B C are set to the input mode Bus hold devices internal to the 82C55A will hold the I O port inputs to a logic 1 state with a maximum hold current of 400 Group A and Group B Controls The functional configuration of each port is programmed by the systems software In essence the CPU outputs a con trol word to the 82C55A The control word contains information such as mode bit set bit reset etc that ini tializes the functional configuration of the 82C55A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control logic receives control words from the internal data bus and issues the proper commands to its associated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the Basic Operation table Figure 4 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information 82 55 Ports A and The 82C55A contains three 8 bit ports A B and C All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of
20. ition Hex Decimal 9 8 7 6 5 4 220 544 Inst Inst Inst Open Inst 240 576 Open Inst Inst Open Inst Inst 250 592 Open Inst Inst Open Inst Open 260 608 Open Inst Inst Open Open Inst 280 640 Open Inst Open Inst Inst Inst 290 656 Open Inst Open Inst Inst Open 2A0 672 Open Inst Open Inst Open Inst 2B0 688 Open Inst Open Inst Open Open 2C0 704 Open Inst Open Open Inst Inst 2D0 720 Open Inst Open Open Inst Open 2E0 736 Open Inst Open Open Open Inst 300 768 Default Open Open Inst Inst Inst Inst 330 816 Open Open Inst Inst Open Open 340 832 Open Open Inst Open Inst Inst 350 848 Open Open Inst Open Inst Open 360 864 Open Open Inst Open Open Inst 380 896 Open Open Open Inst Inst Inst 390 912 Open Open Open Inst Inst Open 3A0 928 Open Open Open Inst Open Inst 3C0 960 Open Open Open Open Inst Inst 3E0 992 Open Open Open Open Open Inst 5 Interrupt Configuration Each interrupt signal has its own configuration jumper block The jumper block configures the interrupt level and the 1K Ohm pull down resistor pull down resistor is required on each active interrupt line on the PC 104 bus Only one resistor should be installed per interrupt level for the entire system J7 Interrupt 0 J8 Interrupt 1 J9 Interrupt 2 Position Function Open Jumper R 1K Ohm Resistor No pulldown Pulldown max 1 per level 7 IRQ7 6 IRQ6 Install only one jumper in each header 5 IRQ5 in any of these 6 locations 4 IRQ4 to select the interrupt level 3 IRQ3
21. o additional ini tialization required This eliminates the need to pullup or pull down resistors in all CMOS designs The control word register will contain 9Bh During the execution of the system program any of the other modes may be selected using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine Any port programmed as an output port is initialized to all zeros when the control word is written ADDRESS BUS CONTROL BUS DATA BUS PB7 PBO PC3 PCO 0 CONTROL CONTROL PA7 PAO OR I O OR I O PB7 PBO BI DIRECTIONAL PB7 PBO PA7 PAO CONTROL FIGURE 3 BASIC MODE DEFINITIONS AND BUS INTERFACE CONTROL WORD GROUP B PORT C LOWER 1 INPUT 0 OUTPUT PORT 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE 0 1 MODE 1 GROUP PORT UPPER 1 INPUT 0 OUTPUT PORTA 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE FIGURE 4 MODE DEFINITION FORMAT 82 55 The modes for Port and Port be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored
22. ompanying schematic diagrams on the following pages Base 12 Counter timer input configuration register Bit Name 21 S20 Counter 2 input select S21 S20 Input source 0 0 In2 0 1 4MHz oscillator 1 X Out1 11 10 Counter 1 input select 11 10 Input source 0 0 Int 0 1 oscillator 1 X 50 Counter 0 input select 0 InO 1 4MHz oscillator Base 14 Interrupt configuration register SRC2 Interrupt Source 2 0 External interrupt pin 1 Counter 2 output SRC1 Interrupt source 1 0 Bit CO from 82C55 2 base 6 bit 0 1 Counter 1 output SRCO Interrupt source 0 0 Bit CO from 82C55 1 base 2 bit 0 1 Counter 0 output INTE2 0 Interrupt enable signals 0 Disabled 1 Enabled Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 12 8 Counter Timer Circuit Schematic The schematic below illustrates the counter timer configuration and how the counter timer input configuration register controls it See the control register description on page 12 COUNTER 8 IN 15 11 IN GATE OUT IN 1 J5 2 COUNTER 1 IN GATE QUT J5 6 IN 2 5 7 COUNTER 2 IN GRTE OUT 4MHz OSCILLATOR 425 111 328 UNDERLINE INDICATES CONTROL REGISTER 95 11 PARENTHESES INDICATE 1 0 HEADER AND PIN NO Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 13 9 Interrupt Circuit Schematic The schematic below illustrates the interrupt
23. ords and status informa tion are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups CS Chip Select A low on this input pin enables the communcation between the 82C55A and the CPU RD Read A low on this input pin enables 82C55A to send the data or status information to the CPU on the data bus In essence it allows the CPU to read from the 82C55A WR Write A low on this input pin enables the CPU to write data or control words into the 82C55A AO and A1 Port Select 0 and Port Select 1 These input signals in conjunction with the RD and WR inputs control the selection of one of the three ports or the control word register They are normally connected to the least significant bits of the address bus A0 and A1 82C55A BASIC OPERATION ro mmm A1 cs READ Peppe Peppe bI PET esos OUTPUT OPERATION WRITE PPT Tr TII MP es CET p DISABLE FUNCTION rr POWER 5V SUPPLIES GND BI DIRECTIONAL DATA BUS INTERNAL DATA BUS FIGURE 1 82C55A BLOCK DIAGRAM DATA BUS BUFFER READ WRITE GROUP A amp CONTROL LOGIC FUNCTIONS RESET Reset A high on this input initializes t
24. s associated gate pin is high and will not count when the gate pin is low The input and gate pins are connected to 5V through 10K pull up resistors Counter timer I O lines are accessed through a 14 pin header J5 See page 8 for the pinout of J5 An on board oscillator provides a 4MHz clock that can be used to drive any counter Each counter has a maximum input rate of 10MHz Programmable features include input source selection and counter cascading Counter 0 input can be either INO from the I O header or 4MHz Counter 1 input can be either IN1 4MHz or Counter 0 output Counter 2 input can be either IN2 4MHz or Counter 1 output All three counter outputs can be programmed to generate PC bus interrupts as described below With appropriate configuration two or three counters can be cascaded to form a 32 bit or 48 bit counter and the output of this cascaded counter can generate an interrupt Onyx MM User Manual v1 4 2001 Diamond Systems Corporation 3 Interrupts ONYX MM provides a means to generate up to three active high interrupt signals on the PC 104 bus Three pin headers are provided to select interrupt levels for each interrupt signal Interrupt levels 2 through 7 are available on each header To enable interrupt sharing a 1K pull down resistor can be jumpered to each interrupt line and interrupt signals are driven by tristate drivers When an interrupt is pending the interrupt line is driven high and when it is not pendin
25. s set when is a OBF is a one and INTE is a It is reset by the falling edge of WR INTE A Controlled by Bit Set Reset of PC6 INTE B Controlled by Bit Set Reset of PC2 NOTE 1 To strobe data into the peripheral device the user must operate the strobe line in a hand shaking mode The user needs to send OBF to the peripheral device generates an ACK from the pe ripheral device and then latch data into the peripheral device on the rising edge of OBF MODE 1 PORT A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 DO PC4 PC5 1 0 OUTPUT CONTROL WORD D7 D6 05 D4 D3 02 01 DO PELO FIGURE 8 MODE 1 OUTPUT 82 55 tWIT gt tWB FIGURE 9 MODE 1 STROBED OUTPUT RD WR CONTROL WORD CONTROL WORD D7 D6 05 D4 03 D2 01 DO D7 D6 05 D4 D3 02 D1 DO PC6 PC7 PC4 PC5 1 INPUT 1 0 OUTPUT 0 OUTPUT WR RD PORT A STROBED INPUT PORT A STROBED OUTPUT PORT B STROBED OUTPUT PORT B STROBED INPUT Combinations of Mode 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I O applications FIGURE 10 COMBINATIONS OF MODE 1 Operating Modes Mode 2 Strobed Bi Directional Bus I O Output Operations The functional configuration provides a means for communi Output Buffer Full The output will go low to cating with a peripheral device or s
26. the 82C55A Port A One 8 bit data output latch buffer and one 8 bit data input latch Both pull up and pull down bus hold devices are present on Port A See Figure 2 Port B One 8 bit data input output latch buffer and one 8 bit data input buffer See Figure 2B Port One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port con tains a 4 bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B See Figure 2B INPUT MODE MASTER RESET OR MODE CHANGE INTERNAL DATA IN INTERNAL DATA OUT LATCHED EXTERNAL PORT A PIN OUTPUT MODE FIGURE 2A PORT A BUS HOLD CONFIGURATION RESET OR MODE CHANGE INTERNAL DATA IN INTERNAL DATA OUT LATCHED EXTERNAL PORT PIN OUTPUT MODE FIGURE 2B PORT B AND C BUS HOLD CONFIGURATION FIGURE 2 BUS HOLD CONFIGURATION Operational Description Mode Selection There are three basic modes of operation than can be selected by the system software Mode 0 Basic Input Output Mode 1 Strobed Input Output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by internal bus hold devices After the reset is removed the 82C55A can remain in the input mode with n
27. trol signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C This function allows the programmer to enable or disable a CPU interrupt by a specific I O device without affecting any other device in the interrupt structure INTE Flip Flop Definition BIT SET INTE is SET Interrupt Enable BIT RESET INTE is Reset Interrupt Disable NOTE All Mask flip flops are automatically reset during mode se lection and device Reset Operating Modes Mode 0 Basic Input Output This functional configuration provides simple input and output operations for each of the three ports No handshaking is required data is simply writ ten to or read from a specific port Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports Any Port can be input or output Outputs are latched Input are not latched 16 different Input Output configurations possible MODE 0 PORT DEFINITION PORTC PORTC D1 PORT A Upper PORT B Lower fo oue ouo ona Output Output 2 Output 4 Output 10 Output 11 Input 12 Output 13 Input 14 Output 15 Input ER E EXE ES 1 Output Output Output Input Output Input Output Input Output Input Input Output Input Output Input Output
28. tructure on a single 8 bit indicate that the CPU has written data out to port bus for both transmitting and receiving data bi directional bus I O Hand shaking signals are provided to maintain proper bus flow discipline similar to Mode 1 Interrupt gener ation and enable disable functions are also available ACK Acknowledge A low on this input enables the three state output buffer of port A to send out the data Oth erwise the output buffer will be in the high impedance state INTE 1 The INTE flip flop associated with OBF Con Mode 2 Basic Functional Definitions trolled by bit set reset of PC4 Used in Group A only One 8 bit bi directional bus Port Port A and a 5 bit Input Operations control Port Port C Both inputs and outputs are latched The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch STB Strobe Input A low on this input loads data into the input latch Bi Directional Bus I O Control Signal Definition Figures 11 12 13 14 INTE 2 The INTE flip flop associated with IBF Controlled by bit set reset of 4 INTR Interrupt Request A high on this output can be used to interrupt the CPU for both input or output operations 10 82 55 CONTROL WORD 07 D6 05 D4 03 D2 01 DO pA Jer 2
29. urned on cs CHIP SELECT Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications 5 READ Read is an active low input control signal used by the CPU to read status information or data via the data bus WR 36 WRITE Write is an active low input control signal used by the CPU to load control words and data into the 82C55A 1 ADDRESS These input signals conjunction with the RD and WR inputs control the selection of one of the three ports or the control word register AO and A1 are normally connected to the least significant bits of the Address Bus AO A1 PAO PA7 1 4 37 40 yo PORT A 8 bit input and output port Both bus hold high and bus hold low circuitry are present on this port PBO PB7 18 25 PORT B 8 bit input and output port Bus hold high circuitry is present on this port PCO PC7 10 17 PORT C 8 bit input and output port Bus hold circuitry is present on this port Functional Diagram POWER 5V GROUP A PORT A SUPPLIES GND GROUP A GROUPA PORT C BI DIRECTIONAL UPPER DATA BUS DATA BUS BUFFER 8 BIT GROUP B INTERNAL PORT C DATA BUS WRITE GROUP B CONTROL CONTROL GROUP B LOGIC 82 55 Functional Description Data Bus Buffer This three state bi directional 8 bit buffer is used to interface the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control w
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