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1. 3 25 SDRAM Ceneral Control Rep Bier cisini 3 25 SDRAM Timing Control Re eistet ccsiiaiccsscscnsssseviantsnccastanssnanssssnsncsicosaseesesanasonsecns 3 27 SDRAM Bank A B C D E F G and H Addressing Registers 3 30 SDRAM Serb Control Register scccisscssacssncvisrebnirsessasnuceteccdacedtueanssaumenssaubvanccens 3 32 SDRAM Seribs Address Conten fase cisscasssosacacexecacctenmnaiineranismmmncnnssonssaussacbeania 3 33 SDRAM Smple Dut Error SIOIS iiieuisenserr o tbrpiSR FARA ITIN SSH NH DEINDE ER a RERE 3 33 SDRAM Smole bit Error Address Register ie ee eren etaran tek tn St Rte etta 3 36 SDRAM Multi Dit Error Statis eed SEHE PEE EEUDUi t dU ep retp n RE ians 3 36 SDRAM Mul bit Error Address Register 4 csicincanescaacetanatcuassdsstnosoosentaceccsans 3 37 Power t t MI Bride 3 38 ACR Ro aie r N ea E AEEA 3 38 Bridge PCI Control and Status Regret ves sasecassasinasasesssensssscssdeatannanianaaiias 3 38 Bridge PowerPC Control and Status ResSisIer uieoeettiine niii einas inan daa tubas 3 41 PCI Intestupt Acknowledge Register siirron 3 43 Outbound Translation Address 0 1 and 2 Registers 3 44 Outbound Translation Offset Translation Attribute 0 1 and 2 Registers3 45 Outbound Translation Address 3 Register uem e eene 3 47 Outbound Translation Offset Translation Attribute 3 Registers 3 48 Passive Slave Address
2. cQyjJoaocccdocoocccGcdcacaococdGcacoccGcacccccceocdgcog The Error Exception Enable Register EEEN provides an array of enable bits pertaining to the various Error Exceptions that the Harrier can generate The fields within the EEEN register are defined as follows PMA PCI Master Abort If set the PCI Master Abort exception is enabled When the exception is enabled the status bit EEST PMA will indicate the state of the PCI Master Abort exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PTA PCI Target Abort If set the PCI Target Abort exception is enabled When the exception is enabled the status bit EEST PTA will indicate the state of the PCI Target Abort exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PAP PCI Address Parity Error If set the PCI Address Parity Error exception is enabled When the exception is enabled the status bit EEST PAP will indicate the state of the PCI Address Parity Error exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PDP PCI Data Parity Error If set the PCI Data Parity Error exception is enabled When the exception is enabled the status bit EEST PDP will indicate the state of the PCI Data Parity Error exception When the enable bit is cleared the exception is disabled and th
3. xx xx F1 11 11 20 Fi 11 0 63 63 0 18 10 08 00 Static Pattern to PCI Space 63 0 XX XX xx 11 11 26 F111 18 11 29 F1 11 11 24 F1 11 10 11 23 F1 11 11 2 F1 11 08 11 21 F1 11 11 20 xx XX 00 Incrementing Pattern to PCI Space Figure 2 14 Examples of Pattern Writes http www motorola com computer literature 2 55 Functional Descriptions There are two issues associated with writing 32 bit patterns When writing to PCI space the pattern will not be subjected to Endian byte swapping In addition a transfer count that is not an even multiple of four will result in the rounding off of the ast data pattern written to either PowerPC space or PCI space The rounding off will occur on the pattern according to the address space being written to A pattern written to PCI space will be rounded off starting from the left or MSB side of the pattern A pattern written to PowerPC space will be rounded off starting from the right or LSB side of the pattern Linked List Descriptors 2 56 The DMA PPC Master is responsible for fetching descriptors from PowerPC address space when using the Linked List Mode Each descriptor consumes 32 bytes and must be cache line aligned This cache line structure helps minimize PowerPC bus bandwidth used when fetching descriptors Th
4. The MP Generic Inbound Doorbell Register MGID is used for receiving inbound doorbell interrupts from PCI to the processor The processor reads this register to determine which doorbell bit was used to generate an inbound doorbell interrupt This register is visible from within the PMEP Register Group allowing a PCI master to write any doorbell bit which will then generate an interrupt to the processor The interrupts generated by this register may be cleared by writing to the appropriate fields within this register The fields within the MGID register are defined as follows IDBIx Inbound Doorbell Interrupt If any one of these bits are set from the PMEP Register Group a processor interrupt will be generated Writing a one to a particular bit position will clear the bit and remove the interrupt associated with the bit http www motorola com computer literature 3 95 Programming Model MP Generic Inbound Doorbell Mask Register Offset XCSR 2B0 guid dadas S a S 232232 s 123222333 o aad aac aod 4 aad ao aan DBM DBMA DBMIO R W IDBM15 R W IDBM14 R W IDBMI3 DBVD4 DBM Operation R V NW gt 2 lt I a lt cd c ed R W IDBMIO R W BA Reset The MP Generic Inbound Doorbell Mask Register MGIDM is used for individually masking inbound doorbell interrupts from PCI to the processor This
5. 3 112 MPIC Base Address a n 3 112 MPIC Control and Status Interrupt Request Sample Registers 3 113 AMPL BABIES LER acento gntons saps RI R MM DN rirP AED 3 113 Feature Reporting Register PME 3 114 lopa t ounouron Register enres 3 115 Vendor Identification Restat e eerrteer iiag 3 116 igo oe Ui 8 ipio e RAA A 3 117 IPI VectogPuonty 0 1 2 and 3 Berstete auuesesequemsecincistetiaerissen iens 3 118 Spunoms Vector RESIO irae erences naires 3 119 Timer Ppa WRN d Reiste Cn A A nnn 3 119 Timer Current Count 0 1 2 and 3 Rogiet f i c usenintt sn ladusipRin 3 120 Timer Base Count 0 1 2 and 3 Registers isis cccsececssastascecsctxounqascessaonens 3 121 Timer Vector Priority 0 1 2 and 3 Registers Lese eite tratta 3 122 Timer Destination D 1 2 and 3 Registers usse cei tees tiep rm 3 123 External Source Vector Priority 0 through 15 Registers 3 124 External Source Destination 0 through 15 Registers 3 125 Harrier Internal Functional Error Interrupt Vector Priority Register 3 126 Harrier Internal Functional Error Interrupt Destination Register 3 127 Processor 0 Processor 1 IPI Dispatch 0 1 2 and 3 Registers 3 128 Processor 0 Processor 1 Current Task Priority Registers 3 129 Processor 0 Processor Interrupt Acknowledge Registers 3 129 Processor 0 Processor
6. Name Error Diagnostics Operation Reset The Error Diagnostics Error Injection Register EDEI provides a way to inject certain types of errors to test the Harrier error capture and status circuitry The fields within the EDEI register are defined as follows DPEx Data Parity Error Enable These bits are used for test reasons to purposely inject data parity errors whenever the Harrier is sourcing PowerPC data A data parity error will be created on the corresponding PowerPC data parity bus if a bitis set For example setting DPEO will cause DPO to be generated incorrectly If the bit is cleared the Harrier will generate correct data parity APEx Address Parity Error Enable These bits are used for test reasons to purposely inject address parity errors whenever the Harrier is acting as a PowerPC bus master An address parity error will be created on the corresponding PowerPC address parity bus if a bit is set For example setting APEO will cause APO to be generated incorrectly If the bit is cleared the Harrier will generate correct address parity XDTT PPC Slave Retry Test Bit This bit is used for test reasons to impose a short PPC delayed transaction time out A short PPC delayed transaction time out will occur when this bit is set Note This bit is not used in Harrier 2 3 188 Computer Group Literature Center Web Site Error Diagnostics TMRTI1 T
7. Operation R W Reset 00000 Function The MP LO Outbound Post list Tail Register MIIPT is a word aligned pointer into PowerPC address space that represents the tail location of the Inbound Post list FIFO This pointer is manually maintained by the processor The fields within the MIIPT register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides http www motorola com computer literature 3 101 Programming Model MP 150 Control Register Offset XCSR 2E0 Bit Name 2 Operation BRL NEN PELE R R Reset daddddddadaaqagsea 00 00 The MP O Control Register MICT is used for controlling the I 0 Message Passing function The fields within the MICT register are defined as follows ENA Enable If this bit is set the I O Message Passing function will be enabled When enabled the IO FIFOs will be accessible to PCI If cleared the IO Message Passing function is disabled QSZ Queue Size This field represents the size of the I O quad FIFO circular queues Each of the four FIFOs are sized the same with the QSZ field indicating the size of each FIFO The following table shows the encoding of the QSZ field Table 3 35 MICT QSZ Encoding QSZ FI
8. AP ci ori o uM ePD NN m mr PN 2 96 A port Bos Transaction Examples iieeiopxndebupbt t bbip Pea R aspi p QUA a RUM inii 2 97 X port Bus Pere Mapping MN DaT 2 106 Apo Bus XAD Mappihg sccacsscidiisannn tebesir 2 108 Howk ompa liie o P m 2 109 Aport Bus Byte Mapping 12uiaiieebecctiakibut bible bte iu ME REEU pe PE PERIIT M Lak OtbAb i dE h 2 110 PUDE AAE AO AN on peche por cendtdenapadan an pun Font De uU OU M A POH COH DAE 2 113 PLEBE Lau attain dM M MM M iv M Md 2 115 hisusdi 2 120 ize of WE TT A mH P 2 122 Poor DOUNON O PPM ORTOS T TEETREO RUPEE ERUNT IPUNNOR E NRNSPIURINUNSENSNOUUNS 2 127 PowerPC Address Bus TIMET 122i nita ceblextbuble rbi eEREEEUDEIUR SPA LIUM niiina iai 2 129 rer PD ariin 2 130 Io d 2G PNEU Tec C SUNT 2 131 lg ddl ooo T 2 132 Hardware EID e 2 133 CHAPTER 3 Programming Model PROMO X a saci 3 1 Dp Group SUNN y reri E ERE 3 3 PowerPC Control and Status XCSR Register Group cc ccccoceinessassscssnseosscinnss 3 3 PowerPC Multi Processor Interrupt Controller XMPI Register Group 3 14 PowerPC to PCI Configuration Space XCFS Register Group 3 19 PCI Configuration Space PCES Register Group metn nnne 3 2 PCT Message Passing PMEP Register Group sente rct ttuan t rr rhon tb tee tint 3 23 SDRAM Bus n
9. MPU 8 bit Devices 16 bit Devices 32 bit Devices Address Device Xport Bus Device Xport Bus Xport Bus Device Xport Bus Xport Bus Address Address Address Address Address Address Address Address 4GB 128MB 16 bit 16 bit 24 bit Latch Latch Latch 4GB 256MB 4GB A31 AO A30 Al AO XADRI A29 A2 Al XADR2 AO XADR2 A28 A3 XADR3 A2 XADR3 XADR3 Al XADR3 XADR3 A27 A4 XADR4 XADR4 XADR4 A26 A5 XADRS A4 XADR5 XADR5 A3 XADR5 XADR5 A25 A6 XADR6 XADR6 XADR6 A24 A7 XADR7 A6 XADR7 XADR7 A5 XADR7 XADR7 A23 A8 XADO XADO LXADO A22 A9 XADI A8 XADI XADI A7 LXAD1 LXADI A21 A10 XAD2 XAD2 LXAD2 A20 All XAD3 A10 XAD3 XAD3 A9 LXAD3 LXAD3 A18 A13 XADS5 A12 XAD5 XADS5 All LXADS LXADS A17 A14 XAD6 XAD6 A12 LXAD6 LXAD6 A16 A15 XAD7 A14 XAD7 XAD7 A13 LXAD7 LXAD7 A15 A16 XAD8 XAD8 LXAD8 Al4 A17 XAD9 A16 XAD9 XAD9 A15 LXAD9 LXAD9 A13 A18 XADIO XADIO LXADIO A12 A19 XADII A18 XADII XADII A17 LXADII LXADII All A20 XADI2 XADI2 LXADI2 A10 A21 XAD13 A20 XAD13 XADI3 A19 LXADI3 LXADI3 A9 A22 XAD14 XAD14 LXAD14 A8 A23 XADI5 A22 XADIS XADIS A21 LXADIS LXADIS A7 A24 XAD16 A23 XADR24 LXADI6 A22 XADR24 LXADI6 A6 A25 XADI7 A24 XADR25 LXADI7 A23 XADR25 LXADI7 http www motorola com computer literature 2 107 Functional Descriptions Table 2 9 Xport Bus Address Mapping Continued MPU 8 bit Devices 16 bit Devices 32 bit Devices Address Device Xport Bus Device Xport Bus Xport Bus Device Xport
10. http www motorola com computer literature 3 13 Programming Model PowerPC Multi Processor Interrupt Controller XMP Register Group The PowerPC Multi Processor Interrupt Controller XMPT Register Group is a relocatable 256K Byte block of registers pertaining to the MPIC function The base address of this group is programmable using the MBAR register within the XCSR Register Group The registers in the Harrier PowerPC Multi Processor Interrupt Controller Register Group are listed in the following table along with each register s bit span and offset location 3 14 Computer Group Literature Center Web Site Register Group Summary Table 3 3 PowerPC Multi Processor Interrupt Controller XMP Register Group Function Offset MPIC Misc 01000 01010 01020 01030 etc 01070 01080 01090 010A0 010B0 010CO 010D0 Spur 010E0 Timers 010F0 01100 01110 01120 01130 01140 01150 01160 01170 01180 01190 011A0 011B0 http www motorola com computer literature 3 15 Programming Model Table 3 3 PowerPC Multi Processor Interrupt Controller XMP Register Group Continued 011C0 011D0 011E0 011F0 Function MPIC Timers External 10000 10010 10020 10030 10040 10050 10060 10070 10080 10090 100A0 100B0 100C0 100D0 100E0 100FO 1010
11. Inbound Translation Function 0 highest Inbound Translation Function 1 Inbound Translation Function 2 V Inbound Translation Function 3 lowest http www motorola com computer literature 2 29 Functional Descriptions PCI Message Passing Register Group The Harrier offers a 4K byte block of register space that supports I O and Generic Message Passing This block can be located anywhere within PCI Memory space using a traditional PCI defined base register within the 64 byte configuration header Refer to the section titled PCI Message Passing PMEP Register Group on page 3 23 for more information The PCI Slave provides the control logic needed to interface the PCI bus to the Inbound FIFO The PCI Slave can accept either 32 bit or 64 bit transactions however it can only accept 32 bit addressing There is no limit to the length of the transfer that the PCI Slave can handle The PCI Slave accepts four basic types of transactions PCI Slave Ly u Ly u 2 30 Posted Write Is accepted either in the form of a single beat or a burst transaction It generally accepts data with zero target wait states and inserts wait states whenever either the data or command FIFOs reach saturation It initiates a disconnect in accordance with PCI initial and subsequent latency requirements Compelled Write Is accepted either in the form of a single beat or a burst transaction however it is always terminated after the transfer of o
12. http www motorola com computer literature 3 107 Programming Model MP Generic Inbound Doorbell Register PMEP 118 qd ESERISSSESS Eg Generic Offset Bit Name 3 108 The MP Generic Inbound Doorbell Register MGID is used for generating inbound doorbell interrupts from PCI to the processor Writing a one to any bit position will cause the generation of a processor interrupt if the XCSR FEMA register permits This register is visible from within the XCSR Register Group allowing the processor to determine which doorbell bit was used to generate the inbound doorbell interrupt The fields within the MGID register are defined as follows IDBIx Inbound Doorbell Interrupt Writing a one to a particular bit position will set the bit and cause the generation of a processor interrupt Computer Group Literature Center Web Site Message Passing MP Generic Interrupt Status Register Offset Operation PMEP 120 Generic Reset The MP Generic Interrupt Status Register MGST is used for handling interrupt status associated with outbound message passing registers MGOMO and MGOM1 The fields within the MGST register are defined as follows OMII Outbound Message Interrupt 1 If set an outbound message has been written by the processor into the MGOM1 register If the MGMS register allowed it a PCI interrupt was al
13. 3 Compelled Read Can either be in the form of a single beat or a burst transaction May optionally be part of Read Ahead Always performed as a delayed transaction 2 16 Computer Group Literature Center Web Site PowerPC to PCI Bridge The PPC Slave supports a single level delayed transaction protocol A delayed transaction is a sequence of events used to process large latency transactions that would otherwise consume a large amount of PowerPC bus bandwidth In general all compelled transactions will be handled by the Harrier as a delayed transaction A delayed transaction is processed in the following manner 1 A PowerPC master issues a bus cycle with the intention of accessing a compelled resource hosted by the Harrier The Harrier will either accept or reject the transaction and in either case the PowerPC bus cycle will be terminated with ARTRY asserted 2 The Harrier only accepts a new transaction if the Outbound FIFO is in a favorable state A favorable state is when a There are no entries for a compelled transaction within the Command FIFO and b There is enough room in the Command FIFO and the Write Data FIFO if servicing a write to accept the current transaction Note that if the Harrier is in the process of serving a previously accepted delayed transaction the associated entry within the Command FIFO will violate rule a above and the Outbound FIFO will not be in a favorable state If conditi
14. Table 2 24 Harrier Hardware Configuration Function Sample Sampled Description Timing Pin s State Group PCI 64 bit Enable REQ64_ 0 64 bit PCI Bus PCI 32 bit PCI Bus Spec Xport Hawk Data XAD 30 Disabled 1 Compatibility Mode Enabled XCSR XPGC HDM UART Clock Select XAD 29 External 1 Internal PCI Slave Configuration XAD 28 Normal access 1 Holdoff XCSR BPCS CSH No access disconnect with retry http www motorola com computer literature 2 133 Functional Descriptions Table 2 24 Harrier Hardware Configuration Continued Function Sample Sampled Description Timing Pin s State Group PCI Slave Configuration XAD 27 0 Unlimited access 1 Mask XCSR BPCS CSM 1 Access limited to 64 byte header PowerPC Processor XAD 26 Processors 0 and 1 not 1 Holdoff XCSR BXCS P1H held off and XCSR BXCS POH Processors 0 and 1 held off SDRAM External Register XAD 25 No external registers in 1 XCSR SDTC SDER series for BAx RAx RAS_ CAS_ WE_ External registers in series for BAx RAx RAS CAS WE Response to Unmapped XAD 24 No Response from 1 Address Only Cycles See Harrier XCSR GCSR AOAO See Global Control and Status Register in next Chapter 3 Generic Power Up Status XAD 23 XCSR GCSR PUST3 Response from Harrier Cleared 1 Set Cleared 1 Set Cleared 1 Set Cleared 1 Set Generic Power Up Status XAD 22 XC
15. W Watchdog Timers function described 1 5 watchdog timers control of 2 120 described 2 120 programming 2 120 WDPL Wait on tDPL SDRAM Timing Control Register SDTC 3 28 word boundaries in I O address translations 2 38 word definition xxiii write posting mode 2 34 X XCLK relation to PCLK 2 2 XCSR 3 3 XCSR Register Group 3 3 Xport function described 1 5 interface to expansion bus 2 94 multiple data beats 2 99 Xport Block Diagram 2 95 Xport Bus transaction examples 2 97 Xport bus address mapping 2 106 byte mapping 2 110 XAD mapping 2 108 Xport bus interface 4 4 Xport Bus Master Xmuoz Xmozs Index 60x bus slave 2 95 Xport Bus master 2 96 attributes 2 96 Xport Bus transactions phases 2 96 Xport chip select relation to 60s address ranges 2 95 IN 8 Computer Group Literature Center Web Site
16. http www motorola com computer literature 3 137 Programming Model ERBFI Enable Received Data Available Interrupt This bit when set enables the Received Data Available Interrupt When DLAB 1 IEDHx IEDHx is the Divisor Latch High most significant byte Register that contains the upper 8 bits of the baud rate divisor for the UART This register in conjunction with the Divisor Latch Low Register form a 16 bit baud rate divisor The Interrupt Identification FIFO Control Register IDFCx consists of two separate registers whose accessibility is based on the mode of operation either read or write IDFCx IDFCx is the read only Interrupt Identification Register that identifies the source of an interrupt The fields within this register are defined as follows FENS1 0 FIFOs Enabled Status These bits are the FIFO status bits that are shown in the table below Table 3 38 FENS1 0 Status IID2 0 IPEN Interrupt ID Interrupt Pending These bits identify the interrupt control functions that are shown in the table below Table 3 39 UART Interrupt Control Functions ID2 IID1 IIDO IPEN Priority Interrupt Interrupt Source Interrupt Reset Level Type Control 0 0 0 1 No Interrupt Pending 0 1 1 0 Highest Receiver Line Overrun Error or Parity Reading the Line Status Error or Framing Error Status Register or Break Interrupt 3 138 Computer Group Literature Center Web Site U
17. sensitive http www motorola com computer literature 3 117 Programming Model IPI Vector Priority 0 1 2 and 3 Registers Offset nm v NNI n IPVP0 XMPI 010A0 IPVP1 XMPI 010B0 IPVP2 XMPI 010C0 IPVP3 XMPI 010D0 dad Function IPVPx R W R W d ed A e 0 0 00 00 The IPI Vector Priority Registers IPVP0 IPVP1 IPVP2 and IPVP3 establish vectoring and priority information for IPI interrupts The fields within the IPVPx registers are defined as follows 3 118 MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Priority Interrupt priority O is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR Vector This vector is returned when the Interrupt Acknowledge register is examined when the interrupt associated with this vector is requested Computer Group Literature Center Web Site Multi Processor Interrupt Controller Spurious Vector Register Offset XMPI 010E0 2 EEEEEGES EEGEGGEGE GEEGEGGE bases Name SPVE Spur Epp wo
18. 1AC 1BO 1B4 1B8 1BC Reserved 1C0 tC 1FC 3 8 Computer Group Literature Center Web Site Register Group Summary Table 3 2 PowerPC Control and Status XCSR Register Group Continued Function Offset Bits 7 8 15 16 23 24 PowerPC Control to PCI and Bridge Status 200 BPCS 204 BXCS 208 20C Interrupt Ack 210 PIAC 214 218 21C Address Translati on 220 OTADO 224 OTOFO OTATO 228 OTADI 22C OTOFI OTATI 230 OTAD2 234 OTOF2 OTAT2 238 OTAD3 23C OTOF3 OTAT3 240 244 248 24C PSOF PSAD http www motorola com computer literature Programming Model Table 3 2 PowerPC Control and Status XCSH Register Group Continued Function Offset Bits 0 T 15 16 23 24 31 DMA 250 DCTL 254 DSTA 258 25C 260 DSAD 264 DSAT 268 DDAD 26C DDAT 270 DNLA 274 DCNT 278 m 280 DCSA 284 DCDA 288 DCLA 28C 3 10 Computer Group Literature Center Web Site Table 3 2 PowerPC Control and Status XCSH Register Group Continued Register Group Summary Function Offset Bits 0 7 8 15 16 23 24 31 Message Generic
19. LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG C Stop condition should be generated to abort the transfer after a software wait loop 100us 100KHz SCL has been expired Figure 2 21 Programming Sequence for I C Page Write 2 90 Computer Group Literature Center Web Site I2C Interface Sequential Read Note that the IC sequential read can be initiated by either an PC random read described here or an PC current address read With an IC random read initiation the first step in the programming sequence should be to test the CMP bit for the operation complete status The next step is to initiate a start sequence by first setting the STA and ENA bits in the D2COx Register and then writing the device address bits 24 30 and write bit bit 3120 to the 2TDx Register The CMP bit will be automatically clear with the write cycle to the I2TDx Register The I2STx Register must now be polled to test the CMP and ACKI bits The CMP bit becomes set when the device address and write bit have been transmitted and the ACKI bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the initial word address will be loaded into the IZTDx Register to be transmitted to the slave device Again CMP and ACKI bits must be tested for proper response At this point the slave d
20. Name POIPDO XMPI 20040 POIPD1 XMPI 20050 POIPD2 XMPI 20060 POIPD3 XMPI 20070 P1IPDO XMPI 21040 P1IPD1 XMPI 21050 P1IPD2 XMPI 21060 P1IPD3 XMPI 21070 GEREEEEE EEEEGEEE CEGEGGEGGCGGGGGG Mai POIPDx P1IPDx Operation Reset 00 00 00 adddddad 3 128 The Processor 0 Processor 1 IPI Dispatch Registers POIPDO POIPD1 POIPD2 POIPD3 P1IPDO P1IPDI P1IPD2 and P1IPD3 are used to send interrupts to one or more processors Writing to an IPI Dispatch Register causes an interprocessor interrupt request to be sent to one or more processors A processor is interrupted if the bit in the IPI Dispatch Register corresponding to that processor is set during the write Two processors are supported with each processor owning four dispatch registers Reading these registers returns zeros The fields within the POIPDx P1IPDx registers are defined as follows P1 Processor 1 The interrupt is directed to processor 1 P0 Processor 0 The interrupt is directed to processor 0 Computer Group Literature Center Web Site Multi Processor Interrupt Controller Processor 0 Processor 1 Current Task Priority Registers Offset POCTP XMPI 20080 P1CTP XMPI 21080 CECE EE EEGEGEEECECEGGGG GEGGGGGE bases Name POCTP P1CTP CPU 0 TP or CPU 1 Reset 00 00 00 0 F The Processor O Processor 1 Current Task Priority Registers POCTP and P1CTP establi
21. Name Exceptions Operation Reset The Functional Exception Clear Register FECL provides a way to clear a previously asserted Functional Exception Note that not all Functional Exceptions are represented within this register Please refer to the previous section titled Exceptions for more information The fields within the FECL register are defined as follows DMA DMA If the FEST DMA status bit is set writing a one to this field will clear the status bit and the associated interrupt MM0 Message Passing Message Register 0 If the FEST MMO status bit is set writing a one to this field will clear the status bit and the associated interrupt MM I Message Passing Message Register 1 If the FEST MMI status bit is set writing a one to this field will clear the status bit and the associated interrupt ABT Abort If the FEST ABT status bit is set writing a one to this field will clear the status bit and the associated interrupt http www motorola com computer literature 3 169 Programming Model Error Exception Enable Register Offset XCSR 050 Bit 14444434dd34353 3844 45344844434 Name EEEN Exceptions SEEEE PD PSE PPE Operation Z R W XBT R W XAP A R W R W SS SSS cao a OC tn d an en ec co od cd cai ead R W XDP XD Reset 3 170
22. Passive Slave The PPC Slave supports a special function called Passive Slave which allows a user defined block of PowerPC memory space to be mapped to PCI memory space Any writes to this block of PowerPC memory space by any PowerPC bus master is copied to PCI memory space Any reads from this block of PowerPC memory space is ignored The PPC Slave does not actively respond to cycles that are mapped to the Passive Slave function The PPC Slave passively tracks PowerPC bus cycles and if a cycle qualifies as a Passive Slave transaction the PPC Slave posts the write command and write data as they are being acknowledge by the PowerPC slave Since the Passive Slave function uses the outbound path it is also restricted by the Outbound FIFO limitations If the Command FIFO or Write Data FIFO does not have enough room to service the current write or if the Command FIFO contains a previously posted delayed write transaction the PPC Slave will assert ARTRY at the earliest possible retry window to prevent the PowerPC slave from acknowledging the cycle The PPC Slave will continue to retry the cycle until the Outbound FIFO is in a favorable state The Passive Slave function has an associated set of registers The PSAD register defines the PowerPC memory space base address The PSOF register defines the offset to be added to the upper 16 bits of the PowerPC address bus to determine the PCI bus address The PSSZ register defines http www moto
23. Some CPU PowerPC masters do not always come back to get the original data If it appears that a CPU has abandoned an Xport bus read the PowerPC slave and Xport bus master also abandon the read and begin accepting new PowerPC accesses The PowerPC slave assumes that a CPU has abandoned a read if it begins a non matching Xport bound PowerPC access before completion of the original data tenure or if the CPU does not begin or request a new PowerPC access within 31 CLK periods of Xport s capturing data from the Xport bus Xport Bus Master 2 96 The Harrier Xport Bus master furnishes the interface between the PowerPC slave and the Xport Bus It performs one Xport Bus transaction for each corresponding PowerPC transaction Xport Bus transactions contain one address phase and one data phase made up of one or more data beats The number of data beats depends on the amount of data to move and the active Xport channel s data width configuration When performing an Xport Bus transaction the Xport Bus master adopts the active channel s Xport Bus attributes Refer to the section titled Xport on page 3 150 These attributes include basic mode enable data port width burst enable burst length access delay and burst access delay The following paragraphs describe these attributes Computer Group Literature Center Web Site XPORT The Harrier uses data port width to determine which data to use and how many data beats to issue If the port width
24. The WTXC register will always become unarmed after the second write regardless of byte lane selection Reads may be performed at any time from the WTXC register and will not affect the write arming sequence http www motorola com computer literature 2 121 2 Functional Descriptions Exceptions 2 122 There are two categories of exceptions that may be generated internal to the Harrier One category of exceptions is called Error Exceptions and the other is called Functional Exceptions The Error Exceptions are associated with critical events that represent a possible compromise in the integrity of the system The Functional Exceptions are associated with non critical events pertaining to the normal flow of information within the system The Harrier s internal error exceptions are grouped together and routed as a singular interrupt to a dedicated channel within the MPIC Similarly the Harrier s internal functional exceptions are grouped together and routed to another dedicated channel within the MPIC Please refer to the section titled Multiprocessor Interrupt Controller in this chapter for more information on how the two interrupts are handled within the MPIC Error Exceptions may also be programmed to generate a machine check to processor 0 processor 1 or both Each error exception has an enable bit a status bit a clear bit an interrupt enable bit a machine check 0 enable bit and a machine check 1 enable bit When the enable b
25. Transaction 32 bit PCI 64 bit PCI Clock Latency Continuous Latency Continuous Ratio PCIClocks Bandwidth PCIClocks Bandwidth MBytes sec MBytes sec Burst Write 3 1 1 1 133 3 1 1 1 267 5 2 Burst Read 9 1 1 1 9 1 1 1 267 Single Write 3 3 Single Read 9 9 http www motorola com computer literature 4 Assumes read ahead enabled and read ahead FIFO is initially empty a Does not include time taken to obtain grant for PowerPC bus The a PowerPC bus is idle at the time of the start of the transaction i e no pipeline effects 4 9 Performance Transaction Burst Write Burst Read 32 bit PCI 64 bit PCI Latency PCIClocks Continuous Bandwidth MBytes sec Latency PCIClocks Continuous Bandwidth MBytes sec Clock Ratio 3 2 Single Write Single Read Burst Write Burst Read Single Write Single Read Burst Write 3 1 2 1 Burst Read Single Write Single Read Burst Write Burst Read Single Write 1 1 4 10 Single Read a Assumes write posting enabled and write posting FIFO is initially empty a Assumes read ahead enabled and read ahead FIFO is initially empty a All transactions targeted to PowerPC memory space hosted by the Harrier SDRAM interface a Does not include time taken to obtain grant for PCI Bus The count starts on the same clock period that FRAME is asserted a One clock request one clock
26. s Computer Group Literature Center Web Site Xport Xport General Control Register Offset XCSR 170 Bit 4144449 3232 223 jdssaadsadsuss5a Function Name XPGC Operation Reset 00 00 Xport The Xport General Control Register XPGC defines the attributes that apply globally i e to all of Xport channels 0 1 2 and 3 The fields within the XPGC register are defined as follows HDM Hawk Data Compatibility Mode When set any channel that is configured for the Hawk compatibility mode also uses Hawk 16 bit data ordering When cleared no channel uses Hawk 16 bit data ordering Note that HDM initializes at power up reset to match the value on a certain signal pin at power up reset Refer to the previous section titled Hardware Configuration for more information 3 155 http www motorola com computer literature Programming Model Arbiters All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group PCI Arbiter Register Offset XCSR 090 Function Arbiters Operation Reset 00 The PCI Arbiter Register PARB provides control and status for the PCI Arbiter Please refer to the previous section titled PCI Arbiter for more information The fields within the P
27. 290 MGOMO Passing 294 MGOMI 298 MGOD 29C 2A0 MGIMO 2A4 MGIMI 2A8 MGID 2AC 2B0 MGIDM 2B4 2B8 2BC LO 2C0 MIOFH 2C4 MIOFT 2C8 MIOPH 2CC MIOPT 2D0 MIIFH 2D4 MIIFT 2D8 MIIPH 2DC 2bE0 2E4 2E8 2EC http www motorola com computer literature Programming Model Table 3 2 PowerPC Control and Status XCSH Register Group Continued Function Offset Bits 15 16 23 24 31 Reserved 2F0 2F4 2F8 2FC PowerPC Reflected to PCI PCI Bridge Config Space 300 VENI DEVI 304 CMMD STAT 308 CLC 30C REVI CLS HDT 310 MPBAR 314 ITBARO 318 ITBARI 31C ITBAR2 320 ITBAR3 324 328 32C SUBI SUBV 330 334 338 33C 340 344 348 34C 350 Computer Group Literature Center Web Site Register Group Summary Table 3 2 PowerPC Control and Status XCSH Register Group Continued Function Offset Bits 15 16 23 24 3l PowerPC to PCI Bridge Reflected PCI Config Space 354 358 ITOF2 35C 360 ITOF3 364 efc 380 PSTA 384 PGPR etC 3FC 380 PSTA 384 PGPR E o Or 3FC General Purpose Memory 400 404 etc BFC
28. A PCI master may access this register from within the PMEP Register Group and the processor may access this register from within the XCSR Register Group The processor may obtain status pertaining to either interrupt by reading the FEST register and may individually mask each interrupt from within the FEMA register Outbound traffic will use the Message Passing Generic Outbound Message MGOMO and MGOM T registers These registers are used when the processor wishes to send a message to a PCI master The processor may access this register from within the XCSR Register Group and a PCI master may access this register from within the PMEP Register Group A PCI master may obtain status pertaining to an interrupt by reading the Message Passing Generic Interrupt Status MGST register The interrupts may be individually masked within the Message Passing Generic Interrupt Mask MGMS register http www motorola com computer literature 2 67 Functional Descriptions 2 Multiprocessor Interrupt Controller MPIC The MPIC is a multi processor structured intelligent interrupt controller Its functions are explained in the following subsections MPIC Features a MPIC programming model Supports two processors a Supports 16 external interrupts a Supports 15 programmable Interrupt amp Processor Task priority levels a Supports the connection of an external 8259 for ISA AT compatibility a Distributed interrupt delivery for extern
29. Configur Operation R W 2 2 2 R W R W ation 4 ln Ron ZEZE Space Reset 00 dddddd 00 00 The Interrupt Line Register INTL contains interrupt routing information The Harrier does not have any hardware associated with this register and is not affected in any way by the contents of this register Initialization software may write interrupt routing information into this register during system configuration The Interrupt Pin Register INTP contains information pertaining to the PCI interrupt pin the Harrier is driving This register is read only from the PCFS Register Group and may be written at any time from within the XCSR Register Group The Harrier is a single function device and therefore is limited by the PCI Local Bus Specification to only driving 3 66 Computer Group Literature Center Web Site PowerPC to PCI Bridge INTA In special cases the Harrier may be programmed to drive any one of the four PCI interrupts This register may be modified to show which of the four interrupt lines the Harrier is driving The recommended encoding of this field is show in the table below Table 3 25 INTP INT Encoding INT PCI Interrupt 000 Undefined 001 INTA 010 INTB 011 INTC 100 INTD 101 111 Undefined Note that the selection of a particular INTx line is handled by the XCSR BPCS register The INTP register is for reference only and does not control any hardware The Minimum Grant Register MNGN is a read on
30. Functional MP DO Inbound post_list New entry written into Inbound Post_List queue MIIPH MIIPT FEST MIP MIIPH MIIPT MIIPH MIIPT Level Functional Functional UART 0 UART 1 UARTO Received data available interrupt time out interrupt in the FIFO mode Transmitter holding register empty interrupt Receiver line status interrupt or MODEM status interrupt UARTI Received data available interrupt time out interrupt in the FIFO mode Transmitter holding register empty interrupt Receiver line status interrupt or MODEM status interrupt FEST UAO FEST UAI IDFCO UARTO service routine UARTI service routine Level Level Functional Abort 2 126 Assertion of ABTSW pin fora short period FEST ABT FECL ABT XCSR Edge Computer Group Literature Center Web Site Error Diagnostics Error Diagnostics The Harrier provides a set of registers to efficiently diagnose error exceptions whenever a transaction terminates abnormally These registers are contained within the XCSR Register Group In the event of a PowerPC bus time out PowerPC delayed transaction time out PowerPC address parity error or PowerPC data parity error the corresponding PowerPC error status bit will be set in the EEST register if the corresponding error is enabled EEEN register any other PowerPC error status bit is not set In addition the Harrier will cap
31. I O Mode If set the corresponding Outbound Translation Function will generate PCI I O cycles using spread addressing as defined in the section titled Generating PCI Cycles in the previous chapter If cleared the corresponding Outbound Translation Function will generate PCI I O cycles using contiguous addressing This field only has meaning when the MEM bit is clear Computer Group Literature Center Web Site PowerPC to PCI Bridge Outbound Translation Address 3 Register Offset XCSR 238 Name OTADS3 STA END Operation R W R W Reset XCSR FEFF0000 gt 8000 XCSR FEFF0000 gt 807F XCSR FEFF1000 gt 8080 XCSR FEFF2000 gt 8100 XCSR FEFF3000 gt 8180 XCSR FEFF1000 gt 80FF XCSR FEFF2000 gt 817F XCSR FEFF3000 gt 81FF Function Address Translation The Outbound Translation Address Register 3 OTAD3 contains address information associated with the mapping of PCI I O space to PowerPC memory space OTAD3 in conjunction with OTOF3 and OTATS is the only register set that can be used to initiate an access to the PCT CONFIG ADDRESS 80000CF8 and CONFIG DATA 80000CFC registers The power up value of OTAD3 OTOF3 and OTATS are set to allow access to these special register spaces without initializing the PowerPC Control Register Group The fields within the OTAD3 register are defined as follows STA Start Address This field determines the start address o
32. Reset 00000 The MP I O Outbound Free list Tail Register MIOFT is a word aligned pointer into PowerPC address space that represents the tail location of the Outbound Free list FIFO This pointer is manually maintained by the processor The fields within the MIOFT register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides http www motorola com computer literature 3 97 Programming Model MP 150 Outbound Post list Head Register XCSR 2C8 Offset Reset 000 A 00000 ad The MP IO Outbound Post list Head Register MIOPH is a word aligned pointer into PowerPC address space that represents the head location of the Outbound Post list FIFO This pointer is manually maintained by the processor The fields within the MIOPH register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides MP 150 Outbound Post list Tail Register Offset XCSR 2CC CECE ERE ECE GGEEE CEGEGGEGGGCGGGGE me Name MIOPT LO QA E 7 BHH Operation td c R W E 00000 ds Reset 000 44 The MP LO Outbound Post list Tail Register MIOPT is a word aligned pointer int
33. The effect of reset on the bit is variable Most registers can be read from or written to as 1 2 4 or 8 byte entities Some registers may have special restrictions in which case these will be discussed on an individual basis All blank bit fields are considered reserved and read as O s xxvii xxvili Introduction This chapter provides a brief description of the Harrier ASIC a list of features block diagrams from a system level implementation and from a functional chip level as well as a description of each functional block within the Harrier Overview Features The Harrier is a multi function ASIC that offers a single chip solution for PowerPC based processor systems A complete system may be created using a single Harrier ASIC however multiple Harrier ASICs may reside on the same PowerPC bus to provide additional I O and peripheral support capabilities Harrier supports a maximum of four PowerPC bus masters Figure 1 1 on page 1 4 shows a typical single Harrier dual processor system implementation 4 PowerPC 60x Bus Interface Optimized for 100 MHz operation Address and data bus parity Supports PowerPC bus pipelining 4 SDRAM Interface X 1 1 1 cycle time for all burst accesses to SDRAM Double Bit Error detect Single Bit Error correct across 72 bits 8 banks with up to 256MB Uses 8 10 or PC100 SDRAMs Built in Refresh Scrub Error Notification Software Programmable Interru
34. cleared If the EEINT PDT is set a processor interrupt will be generated If the EEMCKO PDT is set a machine check to processor 0 will be generated and if the EEMCK1 PDT is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PDT bit PSE PCI SERR This bit is set anytime the PCI bus SERR signal is asserted when the EEEN PSE is enabled and all other PCI error status bits are cleared If the EEINT PSE is set a processor interrupt will be generated If the EEMCKO PSE is set a machine check to processor 0 will be generated and if the EEMCK1 PSE is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PSE bit PPE PCI PERR This bit is set anytime the PCI bus PERR signal is asserted when the EEEN PPE is enabled and all other PCI error status bits are cleared If the EEINT PPE is set a processor interrupt will be generated If the EEMCKO PPE is set a machine check to processor 0 will be generated and if the EEMCK1 PPE is set a machine check to Computer Group Literature Center Web Site Exceptions processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PPE bit PMR PCI Master Retry This bit is set when the PowerPC to PCI Bridge or the DMA Contr
35. information including register bit descriptions for the Harrier ASIC It describes the architecture of the Harrier ASIC by providing the functional description programming model register descriptions block diagrams performance data and programming issues Most of the information for programming the Harrier chip within a PowerPC PMC or CompactPCI board level system are contained in this manual This manual is intended to be used in conjunction with other Motorola Programming Guides whose product incorporates the Harrier ASIC as PowerPC PCI bus bridge SDRAM interface PCI interface DMA controller Message Passing device UART and EC interface interrupt controller arbiter and Xport device or portions of the aforementioned functions This manual is intended for anyone who wants to program SBC boards with one or more Harrier ASICs in order to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed The printed version of this document is bound in two parts Part 1 ASICHRA1I PG1 contains Chapter 1 and 2 plus a Table of Contents List of Figures and List of Tables for those chapters only It also contains an Index for both parts Part 2 ASICHRA2 PGI contains Chapter 3 4 and 5 and Appendix A plus a Table of Contents List of Figures and List of Tables for those chapters and appendix only It
36. 0E 64MB 04 64KB 0F 128MB 05 128KB 10 256MB 06 256KB 11 512MB 07 512KB 12 1 GB 08 1MB 13 2 GB 09 2MB 14 FF Reserved 0A 4MB The Passive Slave Attribute Registers PSAT contain attribute information associated with the mapping of PowerPC Memory space to PCI memory space The fields within the PSAT registers are defined as follows ENA Enable If set the corresponding Passive Slave Translation Function is enabled for read and write transactions SGE Store Gathering Enable If set the corresponding Passive Slave Translation Function participates in Store Gathering If cleared the corresponding Passive Slave Translation Function does not participate in Store Gathering http www motorola com computer literature 3 51 Programming Model XCFS Register Group The following subsections describe the registers in the XCFS Register Group CONFIG ADDRESS Register The description of the CONFIG ADDRESS register is presented in two perspectives from the PCI bus Little Endian bit ordering and from the PowerPC bus Big Endian bit ordering Note that the view from the PCI bus is purely conceptual since there is no way to access the CONFIG ADDRESS register from the PCI bus Conceptual perspective from the PCI bus Offset CFB CFA CF9 CFS Bit I amp a od y g ke lt o oN oa cj 1 jam SON od c lt i N ci Function Name CONFIG ADDRESS CONFI
37. 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PTA bit PAP PCI Address Parity Error This bit is set when an address parity error is detected by the Harrier on the PCI bus when the EEEN PAP is enabled and all other PCI error status bits are cleared If http www motorola com computer literature 3 173 Programming Model 3 174 the EEINT PAP is set a processor interrupt will be generated If the EEMCKO PAP is set a machine check to processor 0 will be generated and if the EEMCK1 PAP is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PAP bit PDP PCI Data Parity Error This bit is set when a data parity error is detected by the Harrier on the PCI bus when the EEEN PDP is enabled and all other PCI error status bits are cleared If the EEINT PDP is set a processor interrupt will be generated If the EEMCKO PDP is set a machine check to processor 0 will be generated and if the EEMCK1 PDP is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PDP bit PDT PCI Bus Delayed Transaction Time out This bit is set when a delayed transaction time out is detected on the PowerPC bus when the EEEN PDT is enabled and all other PCI error status bits are
38. 261100 128M 4 1024Mbytes 261101 128M 1024Mbytes 261110 256M 4 2048Mbytes 261111 Notes mputer literature 5 7 http www motorola com co Programming Considerations 1 Total Number of bank Locations L is 2R x 2 x 4 where R is the value in SPD byte 3 and C is the value in SPD byte 4 2 Primary Device Width is from SPD byte 13 3 Bank Size is the total number of bank locations L x 8 bytes 4 Refer to the section titled SDRAM Bank A B CD E E G and H Addressing Registers for more information 6 Determine the refresh rate from SPD byte 12 using the following table Table 5 3 Programming the SDRAM Refresh Period SPD Device Example Data Value to be Resulting Byte 12 Minimum Sheet Values programmed into Refresh Rate Value Refresh Rate XCSR SDGC MXRR 00 1 row per 15 6us 4096 rows 64ms 2000 1 row per 15 5us 01 row per 3 9us 16384 rows 64ms 10 1 row per 3 75us 02 row per 7 8us 8192 rows 64ms 01 1 row per 7 75us 03 1 row per 31 3us 2000 1 row per 15 5us 04 1 row per 62 5us 00 1 row per 15 5us 05 1 row per 125us 2000 1 row per 15 5us 06 SFF N A N A N A N A 7 Make sure software is no longer using SDRAM and disable the bank that was being used 8 Write to the SDRAM control registers a Program the SDRAM Timing Control Register using the information obtained in steps 3 and 4 and the fact that the XCSR SDTC WDPL bit should be set to 1 Be careful not to a
39. 32 bit Device Byte Lane Mappimg eerta purse encantan enean 2 112 Table 2 16 PPC Arbiter Pa See aC anere 2 113 Table 2 17 PCI Arbiter Pin DOSE DEN nardi dmt aqui ana oL Ep e eo Rina eei eti 2 115 Table 2 18 HEIR Encoding Tor Fixed Mode Priority 1 tetto 2 117 Table 2 19 HEIR Encoding for Mixed Mode Priority isnt anb nit 2 117 Tabie 2 20 PRE EROOB Lone ne E pU raa M Ue 2 118 Table 2 21 WTEC Programming iueeiede ein tole ia Ep eet FER RUM FP R EEEL ENDE UL Et 2 121 Table 2 22 Exception DUDIUBNE aeeai neren a e E SNe AAAA ARREA 2 123 Table 2 23 Error Exceptions and Address Attribute Capture 2 128 Table 2 24 Harrier Hardware Con Igutationi ise aibbsbritepaan nana SE pP ad iiM td dba dac d ap aa 2 133 Table 3 1 Harriet PowerPC and PCI Resources cuscritti 3 1 Table 3 2 PowerPC Control and Status XCSR Register CIGUP isir a A GRN 3 4 Table 3 3 PowerPC Multi Processor Interrupt Controller XMPI 2 401 CPOUD uan AGREE PPP pU EUN E M RM DRM E CM pM M ME EE 3 15 Table 3 4 PowerPC to PCI Configuration Space XCFS Register Group 3 20 Table 3 5 PCI Configuration Space PCFS Register Group sese rri 3 22 Table 3 6 PCI Message Passing PMEP Register Group esee 3 24 Table 3 7 MARK Control of Refresh Rate iade rtl PEE bI SE DUR EIE a 3 25 Table 3 8 SDTC 4 IB Example M 3 26 THe ASDIC TRE ENCON n 3 28 xvii xviii Table 3 10 Table 3 11 Table 3 12 Table 3 13
40. 37 41 45 49 53 57 65 71 7 bytes 16 8 bytes 16 5 bytes 8 5 43 48 53 58 63 68 78 93 6 bytes 8 6 49 55 61 67 73 79 91 109 7 bytes 8 7 55 62 69 76 83 90 104 125 8 bytes 8 8 61 69 77 85 93 101 117 141 http www motorola com computer literature 4 5 Performance Table 4 2 PowerPC 60x Bus Performance for Xport Bus Bound Cycles 60x Xport Number Number of CLK periods required for 60x data Beat 1 when Transfer Channel of data Device access time is Size Width beatson sons 60ns 70ns 80ns 90ns 100ns 120ns 150ns In bits Xport Bus 32 bytes 32 32 bytes 16 16 109 125 141 157 173 189 221 269 32 bytes 8 32 205 237 269 301 333 365 429 525 Background Information 4 6 CLK frequency is 100 MHz For 32 byte transfers data beats 2 3 4 require 1 1 1 CLKs The numbers for data beat 1 come from the formula tDB1 OVH DAT 1 x NXB Where tDB1 is the number of CLK periods from TS to the first TA_ OVH is the overhead expressed in CLK periods associated with any read cycle OVH is 13 if the PowerPC master comes back to get the data just as it becomes ready OVH increases by one for each CLK period that the PowerPC master is late DAT is the device access time expressed in CLK periods And NXB is the number of data beats required on the Xport bus for the transaction Computer Group Literature Center Web Site Xport Bus Interface The following table s
41. Function Name External a a Operation R R R 4 e4 ed c ed ed v 3 q Reset 00 00 00 dddddadd The External Source Destination Registers EXDEO through EXDE15 indicate the destination of external interrupts These interrupts operate in the Distributed interrupt delivery mode The fields of the EXDEx registers are defined as follows P1 Processor 1 The interrupt is pointed to processor 1 P0 Processor 0 The interrupt is pointed to processor 0 http www motorola com computer literature 3 125 Programming Model Harrier Internal Functional Error Interrupt Vector Priority Register Offset IFEVP XMPI 10200 IEEVP XMPI 10220 IFEVP IEEVP Internal PRIOR VECTOR Operation R W R R W R R R R R R Reset adaddagd 0 00 00 3 126 The Harrier Internal Functional Error Interrupt Vector Priority Register IFEVP IEEVP establishes vectoring and priority information for the Harrier internal functional error interrupts An internal interrupt is an interrupt that is generated within the Harrier The fields within the IFEVP IEEVP registers are defined as follows MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been request
42. Gather Timer apply globally to all applicable outbound traffic and is determined by the SBT field within the BXCS register http www motorola com computer literature 2 21 Functional Descriptions Read Ahead 2 22 The Store Gather Sync Flush is an option that causes a collection to be flushed whenever the PPC Slave detects a Sync bus cycle from the processor responsible for the current collection This is also a globally programmable option and is controlled by the SSF field within the BXCS register The Harrier has an optional Read Ahead mode that enables the PCI Master to prefetch data whenever a read transaction occurs on the PowerPC bus The prefetched data would be readily available from the Outbound FIFO if multiple contiguous address read transactions occur on the PowerPC bus This option may be individually enabled for each Outbound Translation Function from within the OTATXx register The PPC Slave only attempts to perform read ahead actions on word 32 bit dword 64 bit and cache line operands The PPC Slave keeps the read ahead command open until a forced flush condition occurs If forced to flush the PPC Slave closes the current read ahead command and clears the Outbound FIFO Once the PCI Master sees that the read ahead command 1s closed it discontinues with the read and close the command There are two groups of events that can force a collection flush Mandatory Flush Events and Optional Flush Events A Mandatory Fl
43. Group Literature Center Web Site Miscellaneous Functions General Purpose Memory Offset XCSR 400 gt BFC Bit 4 44444 442434 2334253284848358593585 Function Name GPM General Operation R W Purpose Memory Reset XXXXXXXX The General Purpose Memory GPM is a 2Kilobyte RAM It is provided for inter process message passing or general purpose storage It does not control any hardware The GPM group is the only group within the XCSR that supports all transfer sizes supported by the PowerPC and all alignments within the 8 byte boundary On power up reset the contents of the GPM are unknown Software is required to initialize the GPM Local reset does not change the contents of the GPM therefore the GPM may be used for storing critical information when performing commanded reset cycles http www motorola com computer literature 3 201 Programming Model 3 202 Computer Group Literature Center Web Site Performance SDRAM Interface The following table shows the performance summary for SDRAM when operating at 100 MHz using PC100 SDRAM with a CAS latency of 2 The figure on the following page defines the times that are specified in the table Table 4 1 PowerPC 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAM s ACCESS TYPE Access Time Comments tB1 tB2 tB3 tB4 4 Beat Read after idle 10 1 1 1 SDRAM Internal Bank
44. Groups are generally represented in the Endian mode associated with the bus that may access the registers The XCSR and XMPI PowerPC Register Groups are represented as a Big Endian resource The PCFS and PMEP PCI Register Groups are represented as a Little Endian resource The XCFS Register Group and specifically the CONFIG ADDRESS and CONFIG DATA registers are actually represented as PCI space to the processor and are subject to data swapping The PIAC register within the XCSR Register Group also represents PCI space to the processor and is subject to data swapping http www motorola com computer literature 2 47 2 Functional Descriptions DMA Controller 2 48 The Harrier has a single channel DMA Controller that facilitates the transfer of large blocks of data without processor intervention The DMA Controller is programmed by a simple set of registers that reside within the PowerPC accessible XCSR Register Group If so desired an Inbound Translation Function may be set up to allow access to the control registers from PCI space Particular emphasis has been placed on the ability of the DMA Controller to provide a very high data throughput rate and a very simple programming interface Please refer to the section titled PowerPC Control and Status XCSR Register Group on page 3 3 for a summary of the DMA Controller register set A block diagram of the DMA Controller is shown in the following figure Computer Group Literature
45. If cleared the Harrier will never drive PERR_ If set the Harrier will drive PERR_ active when a data parity error is detected SERR System Error Enable This bit enables the SERR_ output pin If cleared the Harrier never drives SERR If set the Harrier drives SERR_ active when a system error is detected The Status Register STAT is used to record information for PCI bus related events The fields within the STAT register are defined as follows P66M PCI 66 MHz This bit indicates the Harrier is capable of supporting a 66 67 MHz PCI bus FAST Fast Back to Back Capable This bit indicates that the Harrier is capable of accepting fast back to back transactions with different targets DPAR Data Parity Detected This bit is set when three conditions are met 1 the Harrier asserted PERR_ itself or observed PERR_ asserted 2 Harrier was the PCI master for the transfer in which the error occurred 3 the PERR bit in the CMMD register is set This bit is cleared by writing it to 1 writing a 0 has no effect SELTIM DEVSEL Timing This field indicates that the Harrier always asserts DEVSEL_ as a medium responder http www motorola com computer literature 3 57 Programming Model SIGTA Signalled Target Abort This bit is set by the Harrier whenever it terminates a slave transaction with a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVTA Received Target Abort This bit is set by the Harrie
46. If the abort took affect before the completion of a transaction then the DSTA ABT field will be set once the DMA Controller reaches the aborted state Reading this field will always return a zero PAU Pause Writing a one to this field will pause a DMA transaction This bit is only applicable to Linked List Mode transactions When pausing a DMA transaction the DMA controller will stop at the completion of the current linked list transfer If the pause took affect before the completion of a transaction then the DTSA PAU field will be set once the DMA Controller reaches the paused state A paused transaction may be restarted by writing a one to the DGO field Reading this field will always return a zero Computer Group Literature Center Web Site DMA Controller Abort has overriding authority over pause If a commanded pause is followed by an commanded abort then the DMA controller will honor the commanded abort DGO DMA Go Writing a one to this field will start a DMA transaction Setting the DGO field will cause the DSTA BSY field to be set and will clear all DSTA completion status bits i e SMA RTA etc Reading this field will always return a zero MOD Mode This field establishes the type of DMA transaction to be performed If set a Direct Mode transaction will be performed A Direct Mode transaction performs one transfer according to the contents of the DSAD DSAT DDAD DDAT and DCNT registers If cleared a Linked List Mo
47. Inactive 4 Beat Read after idle 12 1 1 1 SDRAM Internal Bank Active Page Miss 4 Beat Read after idle 7 1 1 1 SDRAM Internal Bank Active Page Hit 4 Beat Read after 4 Beat Read 5 1 1 1 SDRAM Internal Bank Active Page Miss 1 1 1 is an average of 2 1 half of the time and 3 1 1 1 the other half 4 Beat Read after 4 Beat Read 2 5 1 1 1 2 5 SDRAM Internal Bank Active Page Hit 1 1 4 Beat Write after idle 4 1 1 1 SDRAM Internal Bank Active or Inactive 4 Beat Write after 4 Beat Write 6 1 1 1 SDRAM Internal Bank Active Page Miss 4 1 Performance Table 4 1 PowerPC 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAM s Continued ACCESS TYPE Access Time Comments tB1 tB2 tB3 tB4 4 Beat Write after 4 Beat Write SDRAM Internal Bank Active Page Hit 3 1 1 3 1 1 1 for the second burst write after idle 2 1 1 1 for subsequent burst writes 1 Beat Read after idle SDRAM Internal Bank Inactive 1 Beat Read after idle SDRAM Internal Bank Active Page Miss 1 Beat Read after idle SDRAM Internal Bank Active Page Hit 1 Beat Read after 1 Beat Read SDRAM Internal Bank Active Page Miss 1 Beat Read after 1 Beat Read SDRAM Internal Bank Active Page Hit 1 Beat Write after idle SDRAM Internal Bank Active or Inactive 1 Beat Write after 1 Beat Write SDRAM Internal Bank Active Page Miss 1 Beat Write after 1 Beat Write SDRAM Internal Bank Active Page H
48. Mosa P 3 84 DMA Destination Address Register s2isiissssonsinci lt ccccsccancansonnssassossesunadscuansacssontins 3 86 DMA Destination Attribute Register i sc isnsicesccnnnsacasnsdsnndarioadoasndatcecnenaseennonmnapiatnn 3 87 DMA Next Link Address REgIStEr sasiscskccidenscessiennestasaicacedicccatenesssnsnsenstqasevacien 3 89 DNA Cont 002p oo ara EA E EAE 3 90 DMA Current Source Address B glelgt accsciisisanssnseancssccsnaccncssecesmsesnsnmoancsscnatn 3 90 DMA Current Destination Address Beplatet uuo rtetara etu ni nn etate puit 3 01 DMA Current Link Address Paglbelep ue eieeodiebd eme et Set erIS Rio anae 3 92 p C o I PL bi NE D NIU REINUEERBUIN A 3 93 Rie 4 Resister COUP M n 3 93 MP Generic Outbound Message 0 and 1 Registers esset 3 93 MP Generic Outbound Doorbell Register issiisscisscsssscassosscassiacdascasaresaacens 3 94 MP Generic Inbound 0 and 1 Message Registers ssssse 3 94 MP Geueric Inbound Doorbell Remsistet ioeeuasasasssein edu tesa kbe tbe rhe 3 95 xi xii MP Generic Inbound Doorbell Mask Besilsiete cesi ether nante area 3 96 MP I20 Outbound Free Vist Head ReSister iue ses sesas snas s ted odes ade taivids 3 96 MP I20 Outbound Pese Bst Tall Bergh a eenscosiiai ria tins Cete ena 3 97 MP I20 Outbound Post list Head Register ssc ssississsasswssosscsnsssccranssnaaseancion 3 98 MP I20 Outbound Post list Tail Register edidit erbe d aorta bre ra ripa 3 08 MP I20 Inbound Free list Head KRe
49. Offset PCFS 2C Function Name Operation Reset Perspective from the PowerPC Bus Offset XCSR 32C Bit Function Name Reflected Operation PCI Configur Reset ation Space The Subsystem Vendor ID Register SUBV is a read only register from within the PCFS Register Group and may be written at any time from within the XCSR Register Group The SUBV register provides a second level of identification for the manufacturer of this particular device This identifier is allocated by the PCI SIG to ensure uniqueness This register is configured to the Motorola value of 1057 upon release of reset http www motorola com computer literature 3 65 Programming Model The Subsystem ID Register SUBT is a read only register from within the PCFS Register Group and may be written at any time from within the XCSR Register Group The SUBI register provides a second level of identification for this particular device This register will be configured to 0000 upon the release of reset Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Registers Perspective from the PCI Bus Offset PCFS 3C Bit oj od c lt cj o od d dg cl 3 cd Function Name MXLA MNGN INTP INTL Header Operation R R R R W Reset 00 00 01 00 Perspective from the PowerPC Bus Offset XCSR 33C Bit v zl dogy 4 c doc c doc Function INTL INTP MNGN MXLA Reflected INT PCI
50. PCI SERR Assertion of SERR EEST PSE None EECL PSE Edge Note that this may XCSR or may not be as a result of the Harrier detecting an address parity error Error PCI PERR Assertion of PERR EEST PPE None EECL PPE Edge Note that this may XCSR or may not beas a result of the Harrier detecting a data parity error Error PCI Any unclaimed PCI EEST PDT EXAD EXAT EECL PDT Edge Delayed delayed transaction XCSR Trans originating from any action PCI bus master Time out Error PCI Master Bridge or DMA asa EEST PMR EPAD EPAT EECL PMR Edge Retry Error PCI master has XCSR exceeded the maximum number of sequential retries Functional DMA Completion of a FEST DMA DSTA FECL DMA Edge Controller Direct Mode XCSR transfer or a Linked List Mode transaction May be accompanied by an error condition Functional MP Assertion of any FEST MDB MGID MGID DBIx Edge Generic Inbound Doorbell XCSR Doorbell bit http www motorola com computer literature 2 125 Functional Descriptions Table 2 22 Exception Summary Continued Category Exception Description Primary Status Additional Status Clear Edge Level Functional MP Generic Message 0 New message written to Message Passing Register 0 FEST MMO MGIMO0 FECL MMO XCSR Edge Functional MP Generic Message 1 New message written to Message Passing Register 1 FEST MMI MGIM1 FECL MM1 XCSR Edge
51. PowerPC address signals 0 28 If the error was due to a scrub SDSEA matches the value that was in the scrub address counter Bits 29 31 are always 0 s Note that power up reset is the only kind of reset that affects SDSEA SDRAM Multi bit Error Status Offset XCSR 148 Bit Function Name SDRAM ESB Error Logging Operation R c c A d cd d n R R Reset 00 pale ee PR S 00 00 The SDRAM Multi bit Error Status Register SDMES provides status for logged SDRAM multi bit errors SDMES s one and only field is defined as follows 3 36 Computer Group Literature Center Web Site SDRAM Interface ESB Error Scrub Bank ESB indicates which bank the scrubber was accessing when if the Harrier logged a scrub multi bit error refer to the section titled Error Exception Enable Register on page 3 170 The table on the previous page SDSES ESB Encoding shows the encoding Note that power up reset is the only kind of reset that affects this field SDRAM Multi bit Error Address Register Reset XCSR 14C Function SDRAM Error Logging 00000000 P aad The SDRAM Multi bit Error Address Register SDMEA reflects the address present when the Harrier last logged a multi bit error SDMEA s one and only field is defined as follows SDMEA SDRAM Multi bit Error Address This field contains the address of the last multi bit error logged by the Harrier refer to the section titled E
52. PowerPC bus Computer Group Literature Center Web Site PowerPC to PCI Bridge PowerPC Bus i Reg I I E Su een ee rt 1 Er n 1 eene PPC PCI Clock Phasing bains inbound riro 77 i 1 em I u Rom C Read Data Et 1 i 1 T Figure 2 5 PowerPC to PCI Bridge Block Diagram All inbound transactions use the PCI Slave and PPC Master functions for maintaining bus tracking and control During both write and read transactions the PCI Slave places command information into the Inbound FIFO The PPC Master draws this command information from the Inbound FIFO when it is ready to process the transaction During write transactions write data is captured from the PCI bus within the PCI Input block This data is fed into the write data path of the Inbound FIFO The PPC Output http www motorola com computer literature 2 13 Functional Descriptions block removes the data from the FIFO and presents it to the PowerPC bus During read transactions read data is captured from the PowerPC bus within the PPC Input block From there the data is fed into the read data path of the Inbound FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus Cache line locking via PCI Lock is handled by the PPC Lock and PCI Slave blocks The PCI Slave accommodates the PCI bus portion of lock and the PPC Lock accommodates the PowerPC bus portion of lock Parity checking and generat
53. PowerPC bus PowerPC bus seen on the cycle normally cycle normally PowerPC bus Provide corrected Correct the data Write corrected data to the read from data back to PowerPC bus SDRAM merge SDRAM if so master with the write N A enabled data and write the corrected merged data to SDRAM Assert Interrupt or Assert Interrupt or Machine Check if Assert Interrupt or Machine Check if Machine if so so enabled ces enabled Double Bit Terminate the Terminate the This cycle is not Error PowerPC bus PowerPC bus seen on the cycle normally cycle normally PowerPC bus Provide miss Do not perform Do not perform corrected raw the write portion N A the write portion SDRAM data to of the read of the read the PowerPC bus modify write modify write master cycle to SDRAM cycle to SDRAM Assert Interrupt or Assert Interrupt or Assert Interrupt or Machine Check if Machine Check if machine check if so enabled so enabled so enabled Triple or Some of these errors are detected correctly and are treated the same as double greater bit errors The rest could show up as no error or single bit error both of Bit Error which are incorrect http www motorola com computer literature 2 9 Functional Descriptions Refresh Scrub 2 10 Error Logging Harrier logs single and double bit SDRAM errors When an error occurs Harrier records the address and syndrome bits associated with the data in error The section titled SDRAM
54. R C 9 ad R C R R R R R R R C R C R C Reset 3 178 aqaqqg cQyjoogcccGccccccacacacococdcadcoccgccGcocccocccccocqccog The Error Exception Clear Register EECL provides a way to clear a previously asserted Error Exception The fields within the EECL register are defined as follows PMA PCI Master Abort If the EEST PMA status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PTA PCI Target Abort If the EEST PTA status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PAP PCI Address Parity Error If the EEST PAP status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PDP PCI Address Parity Error If the EEST PDP status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PDT PCI Bus Delayed Transaction Time out If the EEST PDT status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PSE PCI SERR If the EEST PSE status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check Computer Group Literature Center Web Site Exceptions PMR PCI Master Retry If t
55. Read 19 24 Burst Write 5 1 1 1 5 1 1 1 133 267 3 1 Burst Read 48 1 1 1 51 1 1 1 133 267 Single Write 5 5 Single Read 30 33 27 33 Burst Write 5 1 1 1 5 1 1 1 133 5 1 1 1 5 1 1 1 267 2 1 Burst Read 35 1 1 1 42 1 1 1 133 27 1 1 1 33 1 1 1 267 Single Write 5 5 5 5 Single Read 23 24 22 24 Burst Write 5 1 1 1 5 1 1 1 267 5 1 1 1 5 1 1 1 355 1 1 Burst Read 22 1 1 1 24 1 1 1 267 18 1 1 1 24 1 1 1 304 Single Write 5 5 5 5 Single Read 16 24 15 15 Bus Idle represents a PowerPC master continually retrying a transaction until the transaction is ready In some cases the timing of transaction ready may not line up with the timing of repetitive retry cycles 4 8 Computer Group Literature Center Web Site PowerPC to PCI Bridge 4 Best Case represents a mixture of transactions allowing the most effective alignment between a retried transaction and transaction ready 4 Assumes write posting enabled and write posting FIFO is initially empty count starts on the same clock period that TS is asserted a All transactions are cache word aligned a Default FIFO threshold settings 4 PCI medium responder with zero wait states a One clock request one clock grant PCI arbitration 4 Clock counts represent best case alignment between PCI and PowerPC clock domains An exception to this is continuous bandwidth which reflects the average affects of clock alignment Inbound Performance
56. The interrupt can be polled by setting the enable bit and setting the mask bit FEMA MIDB When the enable bit is cleared the exception is disabled and the status bit will always read zero 3 164 Computer Group Literature Center Web Site Exceptions MIMO Message Passing Inbound Message Register 0 If set the Message Passing Inbound Message 0 exception is enabled When the Message Passing Inbound Message 0 exception is enabled the status bit FEST MIMO will indicate the state of the exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA MIMO When the enable bit is cleared the exception is disabled and the status bit will always read zero MIM1 Message Passing Inbound Message Register 1 If set the Message Passing Inbound Message 1 exception is enabled When the exception is enabled the status bit FEST MIMI1 will indicate the state of the Message Passing Inbound Message 1 exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA MIM1 When the enable bit is cleared the exception is disabled and the status bit will always read zero MIP Message Passing Inbound Post list If set the Message Passing Inbound Post list exception is enabled When the exception is enabled the status bit FEST MIP will indicate the state of the Message Passing Inbound Post list exception The interrupt can be polled by setting the enable bit and setting the mask bit FEM
57. When a break occurs only one zero character is loaded into the FIFO The next character transfer is enabled after the SIN line goes to the marking state and receives the next valid start bit FE Framing Error In the non FIFO mode this bit is set to a logic 1 whenever the stop bit following the last data bit or parity bitis detected as a logic 0 bit It is cleared by a read from the LSTAx register In the FIFO mode this error is associated with the particular character in the FIFO it applies to and is revealed when its associated character is at the top of the FIFO The UART will try to re synchronize after a framing error by assuming that the framing error was due to the next start bit so it samples this start bit twice and then takes in the data PE Parity Error In the non FIFO mode this bit is set to a logic 1 upon detection of a parity error if the PEN bit in the LCTLx Register is set It is cleared by a read from the LSTAx register In the FIFO mode this error is associated with the particular character in the FIFO it applies to and is revealed when its associated character is at the top of the FIFO Computer Group Literature Center Web Site UART Controller OE Overrun Error In the non FIFO mode this bit is set to a logic 1 upon detection of an overrun condition in the receiver This means that the data in the Receiver Buffer Register was not read before the next character was transferred into the Receiver Buffer Register ther
58. XDP PowerPC Bus Data Parity Error If set an interrupt will be generated through the Harrier s MPIC whenever the EEST XDP bit is set If cleared an interrupt will not be generated XDT PowerPC Bus Delayed Transaction Time out If set an interrupt will be generated through the Harrier s MPIC whenever the EEST XDT bit is set If cleared an interrupt will not be generated Note PowerPC Bus delayed transaction time outs can occur during normal operation The XDT bit should NOT be set Computer Group Literature Center Web Site Exceptions Error Exception Machine Check 0 Enable Register Offset XCSR 060 Bit 4 44444 442434 23425322848458358593585 Function Name EEMCKO Exceptions D H S n Hj zEd8200832822 ud MNMEFEEEEEEEEEECEDEDEEEEEEDEEDEEBGER Reset cdaoadgoaococcadgocdcadaagdggoecocdgadcoococcdoococcdcacocooodGog The Error Exception Machine Check 0 Enable Register EEMCKO provides an array of machine check 0 enable bits pertaining to the various Error Exceptions The fields within the EEMCKO register are defined as follows PMA PCI Master Abort If set a machine check to processor 0 will be generated whenever the EEST PMA bit is asserted If cleared a machine check to processor 0 will not be generated PTA PCI Target Abort If set a machine check to processor 0 will be generated whenever the EEST PTA bit is asserted If cleared a mac
59. a variable threshold to control the effects of read ahead Each Outbound Translation Function offers a unique set of parameters Each Inbound Translation Function offers a distinct set of parameters for PCI Read Read Line commands and for PCI Read Multiple commands http www motorola com computer literature 2 41 Functional Descriptions The table below summarizes the options provided by the Harrier Table 2 7 Harrier Read Ahead Options Virtual FIFO Initial Subsequent FIFO Threshold Read Size Resume Size 64 Bytes 2 cache lines FIFO lt 1 cache line FIFO 0 cache lines 128 Bytes 4 cache lines FIFO lt 2 cache lines FIFO 0 cache lines 8 cache lines FIFO lt 4 cache lines Empty FIFO 0 cache lines Subsequent Stop FIFO 2 cache lines FIFO 4 cache lines FIFO 8 cache lines Selecting an optimal set of parameters is related to the expected average transfer size The ideal solution is to match the prefetch size to the transfer size The next level of success is to minimize the amount of unnecessary prefetching A example of a poorly optimized solution would be to select a very large virtual FIFO size for very small transfers This solution results in a large portion of the prefetched bandwidth being wasted Some general guidelines and characteristics associated with the outbound path are as follows outbound transaction size a Select the smallest FIFO size that is still great
60. a cache line means a savings of PowerPC bus bandwidth since the PPC Master does not have to initiate its own read cycle from local memory The PPC Master pays close attention to the copy back write cycle It must make sure that the cycle following a snoop hit is an associated copy back cycle If the cycle does not meet the criteria of a valid copy back cycle then the PPC Master simply performs a read of the needed cache line The Copy back Snarfing mode can be controlled by the CSE field within the BXCS register The default state for this option is enabled http www motorola com computer literature 2 35 Functional Descriptions Bus Hog The Harrier has an optional mode called Bus Hog When Bus Hog is enabled the PPC Master continually requests the PowerPC bus for the entire duration of each PCI transfer When Bus Hog is not enabled the PPC Master structures its bus request actions around its desire to satisfy FIFO thresholds The Bus Hog mode was primarily designed to assist with system level debugging and is not intended for normal modes of operation It is brute force method of guaranteeing that all inbound transactions are performed without any intervention by host CPU transactions The Bus Hog mode can be controlled by the BHG field within the BXCS register The default state for BHG is disabled Error Handling There is only one distinct type of error associated with the Inbound Function Delayed Transaction Time out Delaye
61. also contains an Index for both parts The pdf version of this document is formatted in one book so that all cross reference and other hyperlink text work correctly Summary of Changes This is the initial publication of this document consequently there are no changes at this time xxi Overview of Contents Chapter 1 Introduction provides an overview of the Harrier its basic features and a description of its functional blocks Chapter 2 Functional Descriptions describes the operational characteristics of all functional components within the Harrier Chapter 3 Programming Model provides an architectural overview a register group summary and a detailed description of all registers Chapter 4 Performance provides details of several interfaces including the SDRAM interface the Xport Bus interface and the PowerPC to PCI Bridge Chapter 5 Programming Considerations provides explanations for programming certain registers as well as what the implications of those programming changes might have Appendix A Related Documentation provides a listing of other Motorola documents third party documents and industry specifications related to this product Manual Terminology xxii Throughout this manual special character symbols are used to identify the numeric format of data and address parameters These symbols precede the parameters and identify their numeric format as follows dollar specifies a hexadecimal
62. an action from the opposing bus The DMA Controller works in a read ahead and write posted manner and there will be no compelled options available for DMA transfers Normal Endian rules apply for all DMA data movement Please refer to the section titled Endian Conversion on page 2 45 earlier in this chapter for more information Operating Modes 2 50 The following figure demonstrates the operating modes of the DMA Controller Computer Group Literature Center Web Site DMA Controller Transfer Transfer Program LT Program Data Data Read Write ET Direct Mode Same Start End Domain Transfer Direct Mode Pattern Write Transaction Transfer Transfer Transfer Processor Program DGO Start Linked List Mode Various Transfers Figure 2 13 DMA Controller Operating Modes The DMA Controller considers all DMA activity to consist of transfers and transactions A transfer is a coordinated movement of data from one place to another The amount of data moved during a transfer is only limited by 32 bit PCI and PowerPC addressing and the direction of data movement during a transfer remains fixed A transaction always consists of one or more transfers Each transfer within a transaction is completely independent of any other The amount of data moved and the direction of data movement may change between transfers within a transaction There are no limits on the
63. are used to provide status information from the watchdog timer functions within the Harrier The field within WTXS registers is defined as follows CNT Count This read only field reflects the instantaneous counter value of the WTx http www motorola com computer literature 3 163 Programming Model Exceptions All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group Functional Exception Enable Register Offset XCSR 040 Function Exceptions Operation Reset The Functional Exception Enable Register FEEN provides an array of enable bits pertaining to the various Functional Exceptions that the Harrier can generate The fields within the FEEN register are defined as follows DMA DMA If set the DMA Controller exception is enabled When the exception is enabled the status bit FEST DMA will indicate the state of the DMA Controller exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA DMA When the enable bitis cleared the exception is disabled and the status bit will always read zero MIDB Message Passing Inbound Doorbell If set the Message Passing Inbound Doorbell exception is enabled When the exception is enabled the status bit FEST MIDB will indicate the state of the Message Passing Inbound Doorbell exception
64. as the initial latency allows before issuing a disconnect When performing a read the Harrier also waits for the maximum allowable initial latency period before converting the read to a delayed transaction The PCI Slave supports a single level delayed transaction protocol A delayed transaction is a sequence of events used to process large latency transactions that would otherwise consume a large amount of PCI bus bandwidth In general all read transactions are handled by the Harrier as a delayed transaction A delayed transaction is processed in the following manner 4 A PCI master issues a bus cycle with the intention of accessing a resource hosted by the Harrier The Harrier attempts to service the transaction before the initial latency period expires If unable to provide service the Harrier terminates the PCI bus cycle with a disconnect retry 4 The Harrier only accepts a new transaction if the Inbound FIFO is in a favorable state A favorable state is when There are no entries for a previously issued but uncompleted delayed transaction within the Command FIFO and There is enough room in the Command FIFO to accept the current transaction If conditions are favorable the Harrier accepts the transaction posts the new entry in the Command FIFO and the PCI Slave retains a copy of the address and attributes of the transaction for future reference If conditions are not favorable the Harrier does not accept
65. at which a write error occurred During a FIFO empty XBT error with the PowerPC bus as the transfer destination this register will represent the PowerPC address at which a write error occurred http www motorola com computer literature 3 91 Programming Model DMA Current Link Address Register Offset XCSR 288 Bit 3 lt oc R Function Name DMA Reset 00000000 EFEEEE The DMA Current Link Address Register DCLA is a read only register that contains the current Linked List Mode descriptor address fora DMA transfer This will always represent a PowerPC address and is presented in 32 byte cache line resolution Software can read this register aftera DMA error to determine how far along a DMA transfer went before the error occurred At the beginning of and up to the first descriptor fetch of a Linked List transaction this register will hold the address of the to be fetched descriptor Once the descriptor has been fetched this register will hold the address of the next descriptor If an XBT error occurs during a descriptor fetch this register will hold the address that incurred the error 3 92 Computer Group Literature Center Web Site Message Passing Message Passing The Message Passing function has registers located within two register groups The processor may gain access to a majority of the control and status registers located within PowerPC address space as a part of the XCSR Register Group A
66. be generated PMR PCI Master Retry If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PMR bit is set If cleared an interrupt will not be generated SSE SDRAM Memory Controller Single Bit Error If set an interrupt will be generated through the Harrier s MPIC whenever the EEST SSE bit is set If cleared an interrupt will not be generated SSC SDRAM Memory Controller Single Bit Error Count Overflow If set an interrupt will be generated through the Harrier s MPIC whenever the EEST SSC bit is set If cleared an interrupt will not be generated SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access If set an interrupt will be generated through the Harrier s MPIC whenever the EEST SMX bit is set If cleared an interrupt will not be generated http www motorola com computer literature 3 181 Programming Model 3 182 SMS SDRAM Memory Controller Multi Bit Error on Scrub If set an interrupt will be generated through the Harrier s MPIC whenever the EEST SMS bit is set If cleared an interrupt will not be generated XBT PowerPC Bus Time out If set an interrupt will be generated through the Harrier s MPIC whenever the EEST XBT bit is set If cleared an interrupt will not be generated XAP PowerPC Bus Address Parity Error If set an interrupt will be generated through the Harrier s MPIC whenever the EEST XAP bit is set If cleared an interrupt will not be generated
67. be to test the CMP bit for the operation complete status The next step is to initiate a start sequence by first setting the STA and ENA bits in the I2COx Register and then writing the device address bits 24 30 and write bit bit 3120 to the I2TDx Register The CMP bit will be automatically clear with the write cycle to the IZTDx Register The I2STx Register must now be polled to test the CMP and ACKI bits The CMP bit becomes set when the device address and write bit have been transmitted and the ACKI bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the word address will be loaded into the IZTDx Register to be transmitted to the slave device Again CMP and ACKI bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the STA and ENA bits in the I2COx Register and then writing the device address bits 24 30 and read bit bit 3121 to the IZTDx Register After CMP and ACKI bits have been tested for proper response the PC master controller writes a dummy value data don t care to the IZTDx Register This causes the IC master controller to initiate a read transmission from the slave device Again CMP bit must be tested for proper response After the C master controller has received a byte of data indicated
68. by first setting the STP and ENA bits in the I2COx Register and then writing a dummy data data don t care to the I2TDx Register The I2STx Register must now be polled to test CMP bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the Harrier master s possession of the C bus The following figure shows the suggested software flow diagram for programming the IC byte write operation http www motorola com computer literature 2 83 Functional Descriptions DEVICE ADDR WORD ADDR DATA MI wa TTT I A TTT Ja SDA START S RIC C C STOP B l Ki I K Ik ACK from Slave Device READ I2C STATUS REG LOAD 09 START CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR WR BIT TO I2C TRANSMITTER DATA REG READ I2C STATUS REG LOAD WORD ADDR TO I2C TRANSMITTER DATA REG READ I2C STATUS REG 3 LOAD DATA TO I2C TRANSMITTER DATA REG LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Figure 2 18 Programming Sequence for lc Byte Write 2 84 Computer Group Literature Center Web Site I2C Interface Random Read The I C random read be gins in the same manner as the PC byte write The first step in the programming sequence should
69. bytes may be read from and the actual byte enable pattern used during the read is passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the Harrier presents the resulting vector information obtained from the PCI bus as read data FIFO Tuning Write Posting Read Ahead The selection of a FIFO size and threshold levels used in conjunction with write posting and read ahead determines the performance characteristics of a bridge device The Harrier is designed to work with an average transfer size of 128 bytes or more however there are mechanisms in place to improve performance for smaller transfer sizes The tuning of write transactions is much easier than the tuning of read transactions Write transactions always have a finite transaction size Read transactions involve a bit of speculation An incorrect speculation usually results in a certain level of system performance degradation The characteristics of the inbound data write FIFO are identical to those of the outbound data write FIFO The Harrier does not provide programmable options associated with these FIFOs Both FIFO sizes are fixed at 256 bytes 8 cache lines The start threshold is fixed at the half way mark i e 4 cache lines and the stop threshold is fixed at the almost empty mark i e lt cache line The characteristics of the inbound data read FIFO are identical to those of the outbound data read FIFO Both FIFOs offer virtual sizing and
70. complement of the Data Set Ready DSRx input When LOOP 1 this bit is equivalent to DTR in the MCTLx Register CTS Clear To Send When LOOP 0 this bit is the complement of the Clear To Send CTSx input When LOOP 1 this bit is equivalent to RTS in the MCTLx Register http www motorola com computer literature 3 145 Programming Model DDCD Delta Data Carrier Detect This bit is set to logic 1 if the DCDx_ input to the UART has changed state since the last time it was read TERI Trailing Edge Ring Indicator This bit is set to logic 1 if the RIx_ input to the UART has changed from logic 0 to logic 1 state since the last time it was read DDSR Delta Data Set Ready This bit is set to logic 1 if the DSRx_ input to the UART has changed state since the last time it was read DCTS Delta Clear To Send This bit is set to logic 1 if the CTSx_ input to the UART has changed state since the last time it was read The Scratch Register SCRTXx is an 8 bit general purpose read write register for programmer to use as a temporary storage space It has no defined purpose in the UART 3 146 Computer Group Literature Center Web Site UART Controller UART General Registers Offset XCSR 0D0 Bt 4 44444444d4sd343d32q44 d448544834 Fein UART Operation The UART Control Register UCTL contains the Hardware Flow Control bits the sta
71. disable the timer The ENA bit may only be modified on the second step of a successful two step arming process ARM Armed This read only bit indicates the armed state of the register If this bit is a zero the register is unarmed If this bit is a one the register is armed for a write RES Resolution This field determines the resolution of the timer The RES field may only be modified on the second step of a successful two step arming process The following table shows the different options associated with this bit Table 3 56 WTxC RES Encoding RES Timer Resolution Approximate Max Time 0000 l us 64 msec 0001 2 Us 128 msec 0010 4 us 256 msec 0011 8 us 512 msec 0100 16 us 1 sec 0101 32 us 2 sec 0110 64 us 4 sec 0111 128 us 8 sec 1000 256 us 16 sec 1001 512 us 32 sec 1010 1024 us min 1011 2048 us 2 min 1100 4096 us 4 min 1101 8192 us 8 min 1110 16 384 us 16 min 1111 32 768 us 32 min 3 162 Computer Group Literature Center Web Site Watchdog Timers RLD Reload This field is written with a value that will be used to reload the timer The RLD field may only be modified on the second step of a successful two step arming process Watchdog Timer Status Registers Offset WTOS XCSR 084 WTIS XCSR 08C Bit m d N ed ci g N oo o ga GN AAA Function WTxS Watchdog Name CNT Timers Operation R Reset FFFF The Watchdog Timer Status Registers WTOS and WT1S
72. from the rising edge of the CLK that samples the first TA low in a burst data tenure to the rising edge of CLK that samples the second TA low in that data tenure tB3 is the number of CLK periods from the rising edge of CLK that samples the second TA low in a burst data tenure to the rising edge of CLK that samples the third TA low in that data tenure tB4 is the number of CLK periods from the rising edge of CLK that samples the third TA_ low in a burst data tenure to the rising edge of CLK that samples the last TA low in that data tenure Xport Bus Interface The following subsections describe the latency periods of Xport bound reads and provides background information Computer Group Literature Center Web Site Xport Bus Interface Latency of Xport bound Reads Xport read bursting disabled Table 4 2 PowerPC 60x Bus Performance for Xport Bus Bound Cycles 60x Xport Number Number of CLK periods required for 60x data Beat 1 when Transfer Channel of data Device access time is Size Width beatson sons 60ns 70ns 80ns 90ns 100ns 120ns 150ns In bits Xport Bus 1 byte 8 16 or 1 19 20 21 22 23 24 26 29 32 2bytes 160r 32 3 bytes 32 4 bytes 32 2 bytes 8 2 25 27 29 31 33 35 39 45 3 bytes 16 4 bytes 16 5 bytes 32 6 bytes 32 8 bytes 32 7 bytes 32 3 bytes 8 3 31 34 37 40 43 46 52 61 5 bytes 16 6 bytes 16 4 bytes 8 4
73. gt PARBS gt PARBA PARB3 gt PARB2 100 PARB2 gt PARBI gt PARBO gt HARR gt PARB6 gt PARBS gt PARB4 gt PARB3 101 PARB3 gt PARB2 gt PARB1 gt PARBO gt HARR gt PARB6 gt PARB5 gt PARB4 110 PARBA gt PARB3 gt PARB2 gt PARBI gt PARBO gt HARR gt PARB6 gt PARB5 111 PARB5 gt PARB4 gt PARB3 gt PARB2 gt PARB1 gt PARBO gt HARR gt PARB6 http www motorola com computer literature 3 157 Programming Model When using the mixed priority scheme the encoding of this field is show in the following table Table 3 53 PARB HIE Mixed Mode Encoding HIE Priority ordering highest to lowest 000 Group 1 gt Group 2 gt Group 3 gt Group 4 001 Group 4 gt Group gt Group 2 Group 3 010 Group 3 gt Group 4 gt Group 1 gt Group 2 011 Group 2 gt Group 3 gt Group 4 gt Group 1 100 Reserved 101 Reserved 110 Reserved 111 Reserved POL Park on Lock If set the PCI Arbiter will park the bus on the master who successfully obtains a PCI bus lock The PCI Arbiter will keep the locking master parked and will not allow any non locked masters to obtain access of the PCI bus until the locking master releases the lock If cleared the PCI Arbiter does not distinguish between locked and non locked cycles ENA Enable This read only bit indicates the enabled state of the PCI Arbiter If
74. has successfully completed a commanded abort A successful command abort must meet the following criteria A write of a logic 1 to the DCTL ABT field The DMA Controller has not received any other errors SMA RTA MRC or XBT between the time the transaction was started and the time that the DMA Controller goes to the idle state The commanded abort took place before the DMA Controller was able to complete a transaction PAU Pause This read only field will be set if the DMA Controller has successfully completed a commanded pause A successful command pause must meet the following criteria A write of a logic 1 to the DCTL PAU field The DMA Controller has not received any other errors SMA RTA MRC or XBT between the time the transaction was started and the time that the DMA Controller goes to the idle state The DMA Controller has not been issued a commanded abort Computer Group Literature Center Web Site DMA Controller The commanded pause took place before the DMA Controller was able to complete a transaction DON Done This read only field will be set of the DMA Controller has successfully completed a DMA transaction A successful transaction must meet the following criteria The DMA Controller has not received any other errors SMA RTA MRC or XBT between the time the transaction was started and the time that the DMA Controller goes to the idle state fa command
75. in tri state If the internal arbiter mode is selected then XARBO and XARBI are driven to an active state no more than ten clock periods after the Harrier has detected a rising edge on RST The PPC Arbiter implements a fully rotational prioritization scheme Each master is guaranteed at least one access on the PowerPC bus The timing of a priority switch is controlled by a bus master Once a master obtains ownership of the bus the priority remains in the favor of that master until the master momentarily releases it s request This release is a signal to the PPC Arbiter to switch to the next rotated priority The end effect is that each master has complete control of how much PowerPC bandwidth it consumes It is the responsibility of each PowerPC master to control it s bandwidth consumption according to system level requirements The GCSR XBS field controls how much bandwidth the Harrier consumes The relationship between the retention of priority and leaving request asserted is called Latching Request This function is intended to give bridge devices a way to guarantee a portion of the PowerPC bandwidth It is not intended to be used by processor devices The PPC Arbiter always implements the latching request function for the HARR and EXTL bus masters Latching Request is optionally implemented for the CPU1 bus master and is never implemented for the CPUO bus master The PPC Arbiter supports four parking modes Parking is implemented only on t
76. indicate the state of the PowerPC Bus Time out exception When the enable bit is cleared the exception is disabled and the status bit will always read zero XAP PowerPC Bus Address Parity Error If set the PowerPC Bus Address Parity Error exception is enabled When the exception is enabled the status bit EEST X AP will indicate the state of the PowerPC Address Parity Error exception When the enable bit is cleared the exception is disabled and the status bit will always read Zero XDP PowerPC Bus Data Parity Error If set the PowerPC Bus Data Parity Error exception is enabled When the exception is enabled the status bit EEST XDP will indicate the state of the PowerPC Bus Data Parity Error exception When the enable bit is cleared the exception is disabled and the status bit will always read zero XDT PowerPC Bus Delayed Transaction Time out If set the PowerPC Delayed Transaction Time out exception is enabled When the exception is enabled the status bit EEST XDT will indicate the state of the PowerPC Delayed Transaction Time out exception When the enable bit is cleared the exception is disabled and the status bit will always read zero Note PowerPC Bus delayed transaction time outs can occur during normal operation The XDT bit should NOT be set Computer Group Literature Center Web Site Exceptions Error Exception Status Register Offset XCSR 054 Bit 4 44444 442434 23342532848483
77. is programmable through the QSZ field within the Message Passing IO Control MICT register The I O specification states that an IMU must be optionally enabled or disabled By default the IMU comes up out of reset in the disabled state The processor must first setup all the queue sizes and interrupt logic Then the processor must allocate some Message Frames and MFAs The Computer Group Literature Center Web Site Message Passing Inbound Free list FIFO must be filled with these MFAs Once the processor is ready the IMU is enabled This is done by setting the ENA bit within the MICT register While the IMU is disabled the I5O specification states that any accesses to the Queue ports MIIQ and MIOQ must not affect the IMU Writes to these ports will be discarded Reads from these ports will return all FFFF FFFF The head and tail pointers will not be affected IMU Interrupts LO is an interrupt driven protocol As a Host the Harrier must be able to recognize and respond to PCI interrupts This is typically handled by routing the PCI interrupts through the MPIC As an IOP the Harrier must be able to generate a PCI interrupt A PCI interrupt will be generated whenever there is a difference between the Outbound Post list Queue head and tail pointers This is an indication to the Host that there is a full MFA that needs servicing within the IOP s outbound queue The interrupt will remain asserted until the Host reads all of the o
78. is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual nag dcr b o xxi Al ul o Eri sic i hrc eee eee xxi o tunriT aui SET o DULL xxii Commen and giu uoi CNN Epi EEn e Ra A AAEE xxiii Conventions Used in This Mantal e rici n DAR MEC CH ERDOHE hU endi nna Xxiv Bot NaS A PEE EM EE REALM HM E EE XX V C EU N NP Mt E XXV Register ang BK Nanun qusdadisiiuiulatixbrlstiebiiei enceten aia ii iiai XXV Resister Dose OUS esene EEE RAEE xxvi CHAPTER 1 Introduction E i CUE A OE A EEE dent Fe S S 1 1 EN ER LAEE TPUT A AE EE EAE AE I A A T NE P M RII AE 1 1 Functional Blocks of Harriet uet uestupte npe ye FREE vanar e enna ieai EEEN 1 4 CHAPTER2 Functional Descriptions odii m 2 1 SPERANTE EO T i U U UAw4 Y i E I A X 2 4 Pover Pe BB up ee 2 5 Respoudmg to Address DrabsIers ox ccsciansitaseandeaatasvarssonsenesssccacnsaceatsntaeaniennss 2 5 Compenis Data TRIES e ne MEA EPI Di PORE Pe 2 5 Wr D is o PP 2 5 DRAM Es Ls ae ene ae edente abt aua RM 2 6 SDRAM CHRODISUDOU oosa raiser PI arno eSEE 2 6 SD
79. itself as a I0 Controller Please refer to the section titled Revision ID Class Code Registers on page 3 58 for more information on class codes The selection of a class code depends on the absence or existence of an external resistor during the release of reset Please refer to the section titled Hardware Configuration on page 2 133 in this section for more information Generic Message Passing The Harrier provides hardware that supports a more generic form of message passing This hardware is not related to the IpO Message Passing hardware The support offered is in the form of Doorbell registers and Message Passing registers Doorbell Registers 2 66 The Harrier has two Doorbell registers One register is for inbound traffic and one is for outbound traffic A Doorbell register consists of an array of bits that may be individually set by a sending agent The receiving agent receives an interrupt anytime a single doorbell bit is set The receiving agent may scan the Doorbell register to determine which doorbell was set and will write a one to the corresponding doorbell bit to clear the associated interrupt Inbound traffic uses the Message Passing Generic Inbound Doorbell MGID register This register is used when a PCI master wishes to assert a doorbell interrupt to the processor There are a total of twenty eight interrupt doorbells A PCI master may access this register from within the PMEP Register Group and the processor
80. may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the Harrier presents http www motorola com computer literature 3 43 Programming Model the resulting vector information obtained from the PCI bus as read data The data from the PCI bus is swapped as described in the section titled Endian Conversion on page 2 45 Outbound Translation Address 0 1 and 2 Registers Offset OTADO XCSR 220 OTADI XCSR 228 OTAD2 XCSR 230 Bit ec ci od eA gJ lt C and e and Function Name OTADx Address STA END Translation Operation R W R W Reset 0000 0000 The Outbound Translation Address Registers OTADO0 OTAD1 and OTAD2 contain address information associated with the mapping of PCI Memory or I O space to PowerPC memory space The fields within the OTADXx registers are defined as follows STA Start This field determines the start address of a particular memory area on the PowerPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PowerPC address END End This field determines the end address of a particular memory area on the PowerPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PowerPC address 3 44 Computer Group Literatu
81. not update the XCSR SDTC CL3 bit at this point You will use the information from this step later 4 Determine the values to use for TRAS TRP TRCD and TRC The values to use for XCSR SDTC TRAS XCSR SDTC TRP XCSR SDTC TRCD and XCSR SDTC TRC can be obtained from the SPD XCSR SDTC TRAS determines the minimum tRAS time produced by the Harrier XCSR SDTC TRP determines the minimum tRP time produced by the Harrier etc Each set of bits should accommodate the slowest bank of SDRAM The SPD parameters are specified in nanoseconds and have to be converted to PowerPC clock periods for the Harrier Use the table on the following page to convert SPD bytes 27 29 and 30 to correct values for TRAS TRP TRCD and TRC Computer Group Literature Center Web Site Programming SDRAM Related Control Registers Do not actually update these bits in Harrier at this time You will use the information from this step later Table 5 1 Deriving TRAS TRP TRCD and TRC Control Bit Values from SPD Control Bits Parameter Parameter Possible Control Bit Values Expressed in CLK Periods 0 0 lt tRAS_CLK lt TRAS 00 4 0 4 0 lt tRAS_CLK lt 5 0 TRAS 01 XCSR SDTC TRAS tRAS tRAS_CLK adi 50 tRAS CLK lt TRAS 10 SPD Byte T 2 CLK Period 6 0 30 in nanoseconds See Notes 1 2 and 9 6 0 tRAS CLK lt TRAS 11 7 0 7 0 lt tRAS_CLK Illegal 0 0 tRP CLK 2 TRP 0 XCSR SDTC TRP tRP tRP CLK tRP T 20 tRP CLK lt 3 TRP
82. on to PCI as a normal I O Space transfer The CONFIG ADDRESS register is located at offset 0CF8 from the bottom of PCII O space The CONFIG DATA register is located at offset 0CFC from the bottom of PCI I O space Outbound Translation Function 3 is designed so OTAD3 OTOFS3 and OTAT3 must be used for mapping PCI Configuration consequently I O space This register group is initialized at reset to allow PCI I O accesses starting at address 80000000 The power up location i e Little Endian disabled of the CONFIG ADDRESS register is 80000CF8 and the CONFIG DATA register is located at 80000CFC The CONFIG ADDRESS register must be prefilled with four fields the Register Number the Function Number the Device Number and the Bus Number The Register Number and the Function Number are passed along to the PCI bus as part of the lower address bits When performing a configuration cycle the Harrier uses the upper 20 address bits to drive IDSEL lines During the address phase of a configuration cycle only one of the upper address bits is set The device that has its IDSEL connected to the address bit being asserted is selected http www motorola com computer literature 2 39 Functional Descriptions 2 40 for a configuration cycle The Harrier decodes the Device Number to determine which of the upper address lines to assert The decoding of the 5 bit Device Number is show in the table below Table 2 6 Configuration Device Decod
83. s here ax PAPAE APA XGSx 1o Wee cx edes XAD 6 0 XADR 7 1 DX tiaddr X low adir X XAD 31 16 gt a EE XWAIT_ mmm E Figure 2 33 Xport Bus One Beat Write Transaction in Hawk Compatibility Mode Xport Bus Address Mapping 2 106 Xport Bus has a 10 bit dedicated address bus XADR 25 24 and 7 0 and a 32 bit multiplexed address and data bus XAD31 0 The highest bit number is the most significant bit and bit zero is the least significant bit The number of address lines available depends on the width of the device and whether an external latch is used The following table shows how 8 16 and 32 bit wide devices are connected to Xport Bus These tables assume the Xport Bus width is configured to match the device width A latch is not required for 8 bit devices A latch is not required for 16 bit devices unless more than 128MB of address space is required A latch is required for 32 bit devices if more than 256 bytes of address space is required Address lines prefixed by an L for example LXADRO indicate a latched version of the address line A 373 type transparent latch should be used to latch the address lines If a latch is used 8 and 16 bit devices may be connected to either the latched or unlatched version of the address line Computer Group Literature Center Web Site Table 2 9 Xport Bus Address Mapping XPORT
84. set writing a one to this field will clear the status bit and the associated interrupt or machine check XDT PowerPC Bus Delayed Transaction Time out If the EEST XDT status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check http www motorola com computer literature 3 179 Programming Model POF PCI Error Overflow If the EEST POF bit is set writing a one to this field will clear the EEST POF bit and the associated interrupt or machine check SSOF SDRAM Memory Controller Single Bit Error Overflow If the EEST SSOF bit is set writing a one to this field will clear the EEST SSOF bit and the associated interrupt or machine check SMOF SDRAM Memory Controller Multi Bit Error Overflow If the EEST SMOF bit is set writing a one to this field will clear the EEST SMOF bit and the associated interrupt or machine check XOF PowerPC Bus Error Overflow If the EEST XOF bit is set writing a one to this field will clear the EEST XOF bit and the associated interrupt or machine check Error Exception Interrupt Enable Register Offset XCSR 05c Bit daa idv rl ggg WAN eo gay aug ggg Function Name EEINT Exceptions LLI SEEEBBEEEEE FEE Opi S 33 SS SS SS d d e cy 3 F F F o a ff d d o am cc am a ed ec Reset ogg ooog ogg eGooooc ooo ooo ooo The Error Exception Interrupt Enable Regi
85. standard PCI Memory Space interface for IO and Generic Message Passing is provided within the PMEP Register Group XCSR Register Group The message passing registers associated with the XCSR register group are described in the following subsections MP Generic Outbound Message 0 and 1 Registers Offset Bit Name MGOMO XCSR 290 MGOMI XCSR 294 MGOMx Generic Operation Reset 00 00 00 00 BYTEO BYTEI BYTE2 BYTE3 The MP Generic Outbound Message Registers MGOMO and MGOM1 are used for generating outbound messages from the processor to PCI Writing to either MGOMO or MGOMI will cause the generation of a PCI interrupt if the MGMS register permits These registers are visible from within the PMEP Register Group allowing a PCI master to receive the outbound message being passed from the processor http www motorola com computer literature 3 93 Programming Model MP Generic Outbound Doorbell Register Offset XCSR 298 EFEEEEECEEEEEEE EECEFECEEEEE 21 Operation gggggg 3343333333343 Reset So 99 9g999gqg9999g9 So 9s gog 9g 999 99 gqg99999099 g The MP Generic Outbound Doorbell Register MGOD is used for generating outbound doorbell interrupts from the processor to PCI Writing a one to any bit position will cause the generation of a PCI interrupt if the MGODM register permits This register is visible from w
86. status bits set within the EEST register During a string of successive errors this register will retain information pertaining to the first error The fields within the EPAT register are defined as follows DMA DMA Error This read only bit will be set to a 1 when the current transaction is DMA originated and will be set to a 0 when the current transaction is PowerPC to PCI bridge originated Additionally this bit may only be set to a 1 if the error being captured is a PMA PTA or PMR Otherwise this bit will read as a 0 DDI DMA Direction This read only bit will be set to a 1 when the DMA error occurred during fifo fill and will be set to a 0 when the DMA error occurred during fifo empty Additionally this bit may only be set to a 1 if the error being captured is a PMA PTA or PMR and the error being captured is DMA Otherwise this bit will read as a 0 COMMx PCI Command This field contains the PCI command of the PCI transfer in which the Error Exception occurred 3 192 Computer Group Literature Center Web Site Miscellaneous Functions Miscellaneous Functions All of the remaining miscellaneous registers described in this section are located within PowerPC address space as a part of the XCSR Register Group Vendor ID Device ID Registers Offset XCSR 000 Bit c d d cd oo q o cd o O q fe and Function Name VENI DEVI ID Operation R R Reset 1057 480B The Vendo
87. supplied by software The DMA Controller can be programmed to work in terms of 8 bit patterns or 32 bit patterns Software may also specify whether the pattern should be static or incrementing The figure below shows some examples of pattern writes 2 54 Computer Group Literature Center Web Site Writing 8 Bit Patterns DSAD xx xx xx 20 Start Pattern 20 DDAD 02J Destination Address 02 DCTL 00 00 00 1B Transfer Count 27 DMA Control Registers 0 63 2 N 18 20 20 20 20 20 xx XX XX 10 20 20 20 20 20 20 20 20 08 20 20 20 20 20 20 20 20 00 XX Xx 20 20 20 20 20 20 Static Pattern to PowerPC Space 0 63 ns gt 18 36 37 38 39 SA Xx XX XX 10 2E 2F 30 831 32 33 34 35 08 26 27 28 29 2A 2B 2C 2D 00 X XX 20 21 2223 24 25 Incrementing Pattern to PowerPC Space 63 0 f 5x XX XX Xx 20 20 20 20 20 18 20 20 20 20 20 20 20 20 10 20 20 20 20 20 20 20 20 08 20 20 20 20 20 20 xx xx 00 Static Pattern to PCI Space 63 0 _ NIE EA A EE XX XX XX 3A 39 38 37 36 18 35 34 33 32 31 130 2F 2E 10 2D 2C 2B 2A 29 28 27 26 08 25 24 23 22 21 20 xx xx 00 Incrementing Pattern to PCI Space 18 10 08 00 DMA Controller Writing 32 Bit Patterns
88. tells the Harrier the bank s component configuration and size The table below shows SIZE s encoding Note that power up reset is the only kind of reset that affects this field 3 30 Computer Group Literature Center Web Site SDRAM Interface Table 3 14 SDBA SIZE Encoding SIZE Component Bank Size Components per Technology configuration Bank 0000 OMB ytes 0001 4Mx16 32MBytes 5 64Mbit 0010 8Mx8 64MBytes 9 64Mbit 0011 8Mx16 64MBytes 5 128Mbit 0100 16Mx4 128MBytes 18 64Mbit 0101 16Mx8 128MBytes 9 128Mbit 0110 16Mx16 128MBytes 5 256Mbit 0111 32Mx4 256MBytes 18 128Mbit 1000 32Mx8 256MBytes 9 256Mbit 1001 32Mx16 256MBytes 5 512Mbit 1010 64Mx4 512MBytes 18 256Mbit 1011 64Mx8 512MBytes 9 512Mbit 1100 64Mx16 512MBytes 3 IGbit 1101 128Mx4 1024MB ytes 18 512Mbit 1110 128Mx8 1024MBytes 9 1Gbit 1111 256Mx4 2048MBytes 18 1Gbit ENB Bank Enable When set the Harrier allows PowerPC accesses to the bank When cleared the Harrier disallows PowerPC accesses to the bank Note that ENB does not affect scrub accesses to the bank http www motorola com computer literature 3 31 Programming Model SDRAM Scrub Control Register Offset XCSR 130 Bit T o Function Sw Scrubbing Operation Reset d The SDRAM Scrub Control Register SDSC controls the scrubber The fields within the SDSC register are de
89. the IZTDx to the responding slave device The I2TDx 24 30 is the device address and the ITTDx 31 is the WR RD bit OZWRite 1 ReaD After a start sequence with IZTDx 31 0 subsequent writes to the I2TDx Register will cause the contents of IZTDx to be transmitted to the responding slave device After a start sequence with IZTDx 31 1 subsequent writes to the IZTDx Register data don t care will cause the responding slave device to transmit data to the IZRDx Register If a value is written to IZTDx data don t care when the STP and ENA bits in the I2COx Register are set a stop sequence is generated http www motorola com computer literature 3 133 Programming Model I C Status Register Offset Bit Name XCSR 194 XCSR 1B4 GEGEEEES EEGEEEEEEGEEGEGEEGEGGGGG khiti I2STO Dc Operation Reset 00 00 00 daddad 3 134 The I2C Status Register I2STx provides status for the Harrier s PC function Please refer to the section titled C Interface in the previous chapter for more information The fields within the I2STx register are defined as follows DIN Data In This bit is set whenever the IC master controller has successfully received a byte of read data from an PC bus slave device This bit is cleared after the IZRDx Register is read ERR Error This bit is set when both STA and STP bits in the IZCOx Register are set at the same time The PC master controller will t
90. three major components the command path the read data path and the write data path The command path incorporates a 50 bit by 8 entry FIFO that is used to hold command information being passed between the PPC Slave and the PCI Master If write posting has been enabled then up to eight single beat burst or store gathered transactions may be posted If this limit is exceeded then any pending PowerPC transactions are retried until the PCI Master has completed a portion of the previously posted transactions and created some room within the command FIFO Each data path uses a 256 byte 32 entries 8 cache lines by 64 bit FIFO The operation of the write data path is completely independent of the read data path This allows the Harrier to accept write posted transactions while servicing a delayed read transaction If a read data path FIFO limit is reached then the PCI Master stops prefetching until the PPC Slave has emptied the FIFO beyond a certain programmable threshold If a write data path FIFO limit is reached then the PPC Slave continually issues retries until the PCI Master has managed to empty some portion of the FIFO The Harrier does not support byte merging or byte collapsing Each and every single beat byte transaction presented to the PPC Slave will be presented to the PCI bus as a unique single beat transfer Store Gathering is supported for word operand transfers See Store Gathering on page 2 20 for more information The Harrie
91. to prefetch data in bursts and store it in the Inbound FIFO The contents of the Inbound FIFO is then used to satisfy the data requirements for the remainder of the PCI read transaction Upon completion of a prefetched read transaction any residual read data left within the Inbound FIFO is invalidated discarded When servicing a delayed read transaction the contents of the Inbound FIFO is invalidated upon disconnect if at least one data beat of the delayed transaction has been transferred The PPC Master never performs prefetch reads beyond the address range mapped within the Inbound Translation Function map decoders As an example assume the Harrier has been programmed to respond to PCT address range 10000000 through 1001FFFF with an offset of 2000 The PPC Master performs its last read on the PowerPC bus at cache line address 3001FFFC or dword address 3001FFF8 Copyback Snarfing Many times an inbound read takes place in coherent memory space that is held within the processor s cache When this happens the processor detects a snoop hit on the Harrier s bus cycle The processor then performs a copy back write cycle to return the modified cache line to local memory The Harrier has an optional Copy back Snarfing mode that enables the PPC Master to snarf the processor s copy back write cycle Snarfing means that the PPC Master listens to the processor write cycle and grabs a copy of the data for its own use A successful snarf of
92. w w ww wy 07 0 32KB 03 WwW wW WwW WwW wW wW WWW WW w ww w w wo 07 0 64KB 04 WwW WwW WwW WwW WwW wW w w www www w wojlojlojo 128KB 05 WwW wW WwW WwW wW wW w w w WW ww WW0 0 0 0 0 256KB 06 WwW wW WwW wW wW wW w w w WW WWW0 0 0 0 0 0 512KB WwW wW wW wW wW W WWW WW WW 0 0 0 0 0 0 0 1MB wW wW wW wW w w E w ww wo 0 0 0 0 OF 0 O 2MB ww www w w w w ww 0 0 0 0 0 0 Of OF 0 ww www ww w w wo 0 0 0 0 0 0 OF OF 0 ww www ww ww 0 0 0 0 0 0 0 0 OF OF 0 wW wW wW wW w www oo 0 0 0 07 0 07 0 OF OF OF O WwW wW wW wW w w w 0 0 0 0 0 0 0 0 0 0 0 0 w w w wW ww o 0 0 0 0 0 0 0 0 0 OF 0 0 w wW Ww wojo 0 0 0 0 0 0 0 0 0 OF 0 0 256MB 10 w wW w wo 0 0 0 07 07 0 OF OF OF OF OF OF OF OF O 3 64 Computer Group Literature Center Web Site PowerPC to PCI Bridge Table 3 24 BASE Encoding and Resource Size Continued Resource ITSZx Effects on BASE Field PCFS Register Group Size W gt Writable Bit Position 0 gt Fixed Zero Bit Position o r o v iI c alo ALAILALATATATaAlTalsla 512MB 11 w w wy do 0 0 0 0 0 OF OF OF O 0 0 0 0 0 1GB 12 w wo o 0 0 0 0 0 OF OF OF O 0 0 0 0 0 2GB 13 w 0 0 0 0 0 0 0 OF O OF OF OF OF OF OF OF OF OF O Subsystem Vendor ID Subsystem ID Registers Perspective from the PCI Bus
93. widths It has deep write posting buffers and advanced read ahead algorithms to ensure a very high bandwidth interface between the PowerPC bus and the PCI bus Computer Group Literature Center Web Site Overview DMA Controller A highly flexible DMA controller allows fast and efficient block data transfers between any domain including PCI to PCI PCI to PowerPC PowerPC to PCI and PowerPC to PowerPC An option exists that allows complex patterns to be written to PCI or PowerPC spaces 1 0 and Generic Message Passing This functional block offers a fully 1 0 compliant Message Passing Unit allowing the Harrier to participate in IlO Message Passing as either a Host or an I O Processor IOP Additional hardware is provided that allow the use of more generic forms of message passing Multi Processor Interrupt Controller This functional block is a dual processor version of the OPIC interrupt controller that supports 16 external interrupts 4 internal timer interrupts with timers and one internal source interrupt The control and status resources for this function are offered directly to the PowerPC bus PC Controller This functional block offers two standard master only PC interfaces providing flexibility in chip to chip communication UART This functional block offers two full duplex Universal Asynchronous Receiver Transmitter UART interfaces that support communication with modems or other serial peripheral devices Xport A mult
94. 0 10110 10120 EXVP9 10130 EXDE9 10140 EXVP10 10150 EXDE10 Computer Group Literature Center Web Site Register Group Summary Table 3 3 PowerPC Multi Processor Interrupt Controller XMP Register Function MPIC External 10160 Group Continued EXVPII 10170 EXDEII 10180 EXVP12 10190 EXDE12 101A0 EXVP13 101B0 EXDE13 101C0 EXVP14 101D0 EXDEI4 101E0 EXVPI5 101F0 EXDEIS5 Internal 10200 IFEVP 10210 IFEDE 10220 IEEVP 10230 IEEDE Reserved 10240 Ote 20020 20040 POIPDO 20050 20060 POIPDI POIPD2 20070 POIPD3 20080 20090 POCTP 200A0 200B0 http www motorola com computer literature 3 17 Programming Model Table 3 3 PowerPC Multi Processor Interrupt Controller XMP Register Group Continued Function Offset MPIC Reserved 200CO ele 21020 CPU 1 21040 P1IPDO 21050 PIIPD1 21060 PIIPD2 21070 P1IPD3 21080 PICTP 21090 210A0 PIIAC 210B0 PIEOI Reserved 210CO elec 3FFFF 3 18 Computer Group Literature Center Web Site Register Group Summary PowerPC to PCI Configuration Space XCFS Register Group The generation of PCI configur
95. 0 pee soc MIIQ 040 NUM Generic MGOMO 100 MGOMI 104 pmqp qpqpe uc 110 114 118 11C MGST 120 MGMS 124 MGODM 128 12C Reserved 130 ele FFF 3 24 Computer Group Literature Center Web Site SDRAM Interface SDRAM Interface All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group For a functional description refer to the section titled SDRAM Interface on page 2 4 SDRAM General Control Register Offset XCSR 100 Function SDRAM Interface The SDRAM General Control Register SDGC affects functions that apply to all banks of SDRAM The fields in the SDGC register are defined as follows MXRR Multiply the Refresh Rate When set the Harrier increases the effective refresh rate as shown in the table below For an example of programming these bits see the section titled Optional Method for Sizing SDRAM on page 5 9 Table 3 7 MXRR Control of Refresh Rate MXRR 4 Row Refresh Effective Interval Refresh Rate T 01 31us default Row 7 75us 10 15us 1 Row 3 75us 11 Tus 1 Row 1 75us http www motorola com computer literature 3 25 Programming Model DREF Disable Refresh When set the Harrier stops refreshing SDRAM When cleared the Harrier resumes refreshing SDRAM This bit should not be s
96. 0 0 of 0 of 0 of Of 0 Of 0 Of Oo 128MB w w WwW wlo ojo 0 0 0 0 0 0 of of of o Oo o 256MB 10 w ww wo 0 0 0 0 of 0 of of Oo Of OJ Of Of oO oO 512MB 11 wl w wi 0 0 0 0 0 0 0 0 0 0 0 of 0 of of of o 1GB 12 w WwW 0 0 0 0 0 0 0 0 0 0 0 0 of oJ of of oj o 2GB 3 WO 0 0 0 0 0 0 0 0 0 0 0 0 of oJ of of oj o Passive Slave Offset Translation Attribute Registers Offset PSOF PSAT XCSR 24c Bit Function Name Address Translation Operation Reset The Passive Slave Offset Registers PSOF contain offset information associated with the mapping of PowerPC Memory space to PCI memory space The PSOF field represents a 16 bit offset that is added to the upper 16 bits of the PowerPC address to determine the PCI address used for outbound transfers This offset allows PCI resources to reside at addresses that would not normally be visible from the PowerPC bus 3 50 Computer Group Literature Center Web Site PowerPC to PCI Bridge The Passive Slave Size Registers PSSZ establish the size of a resource offered by the Passive slave translation function The value selected within this register determines the characteristics of the PSAD registers Valid selections for a resource size are shown in the table below Table 3 22 PSSZ Encoding PSSZ Resource PSSZx Resource Size Size 00 4KB 0B 8MB 01 8KB 0C 16MB 02 16KB 0D 32MB 03 32KB
97. 1 Although both timers are functionally equivalent each timer operates completely independent of each other WTO and WT1 are initialized at reset to a count value of 8 seconds and 16 seconds respectively The timers are designed to be reloaded by software at any time When not being loaded the timer continuously decrements itself until either reloaded by software or a count of zero is reached If a timer reaches a count of zero an output signal will be asserted and the count will remain at zero until reloaded by software or the Harrier s reset is asserted External logic can use the output signals of the timers to generate interrupts machine checks etc Each timer is composed of a prescaler and a counter The prescaler determines the resolution of the timer and is programmable to any binary value between 1 us and 32 768 us The counter counts in the units provided by the prescaler For example the watchdog timer would reach a count of zero within 24 us if the prescaler was programmed to 2 us and the counter was programmed to 12 The watchdog timers are controlled by registers mapped within the XCSR Register Group Each timer has a WTxC register and a WTXsS register The WTXC register can be used to start or stop the timer write a new reload value into the timer or cause the timer to initialize itself to a previously written reload value The WTXS register is used to read the instantaneous count value of the watchdog timer Programming th
98. 1 SPD Byte T 2 CLK Period 27 in nanoseconds See Notes 3 4 and 9 0 0 lt tRCD_CLK 2 TRCD 0 XCSR SDTC TRC tRCD tRCD CLK tRCD T 2 0 tRCD CLK lt 3 TRCD 1 D T CLK Period SPD Byte T CIS Feng 3 lt tRCD_CLK Illegal 3 lt tRP_CLK Illegal 29 in nanoseconds See Notes 5 6 and 9 0 0 tRC_CLK lt 6 0 TRC 110 6 0 lt tRC_CLK lt 7 0 TRC 111 8 0 lt tRC_CLK lt 9 0 TRC 001 XCSR SDTC TRC tRC tRC_CLK tRAS SPD Bytes tRP T 10 0 lt tRC CLK lt TRC 011 30 and 27 T CLK Period 11 0 in nanoseconds See Notes 7 8 and 9 11 0 lt tRC_CLK illegal Notes http www motorola com computer literature 5 5 Programming Considerations 5 6 Use tRAS from the SDRAM bank that has the slowest tRAS tRAS CLK is tRAS expressed in CLK periods Use tRP from the SDRAM bank that has the slowest tRP tRP CLK is tRP expressed in CLK periods tRCD CLK is tRCD expressed in CLK periods Use tRC from the SDRAM bank that has the slowest tRC tRC_CLK is tRC expressed in CLK periods 2 3 4 5 Use tRCD from the SDRAM bank that has the slowest tRCD 6 7 8 9 Remember that CLK is Harrier s PowerPC clock input pin 5 Determine the size for each bank that is present Do not actually program the Harrier s size bits at this point You use this information to program them later Each bank s size can be determined using the following algor
99. 1 End Of Interrupt Registers 3 130 Pe Cale P O7 r 3 131 LI lock Proscaler Begbiiiteaonooipiveudepnia o qdqu eq d Sia RER 3 131 ir dido Moos c MUT E T 3 132 DEC Transmitter Dota Register isiccccscccccasccacccasecccquncecntversnsadnieistanstniwcatacatatersies 3 133 DE ANUS BRI La een udin NEM M MA dM MM MAE 3 134 PEU Receiver Data OPI oopSOREPIIMIWPODd IND MEM p e un E 3 135 UAET LOO ciet op p nd oiu ner cre MEME ny M M EE 3 136 VART CO Reo ene or a ea EA 3 136 UART General Ret BES aena AET EENE 3 147 boo A A PEA E YO 3 150 X port Address Range 0 1 2 3 REpIStotS scccaicscsasciastasssonssaansncccansscccansansinains 3 150 Apon Attributes 0 1 2 3 BGIESIBES Lie spun nini pn t RA a Mem na Eie bo RUN REA RUE 3 151 Aport General Control Register Lies esee ed rtm to ke rri EIE PRIPENER RUE RUE a pA qa 3 155 IDE ec ee ae Re ep nar hdd E N A un Md MEN un MM MA M QUE 3 156 PCI Arbiter Beer P Pe 3 156 Powe PC Arbiter REDE pectorrevediciemntansoinnaneoeraneekwns 3 159 Wakehdog TIMET asuscin baa adi beue a id Eia be PUR Cm EUM EM a pL UP LATER 3 161 Waichdog Timer Coniol Registo Sorrera naen rk talus Geo p o lap ncn 3 161 Watchdog Timer Status RES S060S aiu ceo rt aRpRE ab PEPA BE LM REM MPCMER ELEME 3 163 DEO UL aea Deo EH RO in ine aaa 3 164 Functional Exception Enable Register eosina 3 164 Functional Ex
100. 180 XCSR 1A0 Bit 7 ddcdad 4 B ro og g lt d N od o c Function Name I2PSO I2C I2PS1 Operation R R R W Reset 00 00 01F3 The I2C Clock Prescaler Register I2PSx is used to specify a frequency of the PC gated clock signal The formula for calculating a value is shown below PC CLOCK SYSTEM CLOCK I2PSx 1 2 After power up I2PSx is initialized to 01F3 which produces a 100KHz PC gated clock signal based on a 100 0 MHz system clock Due to the SDAx hold time requirement the value written to I2PSx must be greater than 0020 Writes to this register will be restricted to 2 4 or 8 byte only and must be aligned http www motorola com computer literature 3 131 Programming Model 12C Control Register Offset 3 132 XCSR 184 XCSR 1A4 dua E Function The I2C Control Register I2COx provides control for the Harrier s C function Please refer to the section titled IC Interface in the previous chapter for more information Writes to this register are restricted to 4 bytes only and must be aligned The fields within the I2COx register are defined as follows STA Start When set the C master controller generates a start sequence on the IC bus on the next write to the I2TDx Register and clears the CMP bit in the I2STx register After the start sequence and the I2TDx Register contents have been transmitted the PC master controller will automatically clear the STA bit and t
101. 26 LXAD5 LBAO A3 A27 LXAD6 LBAI Xport Bus Byte Mapping 2 110 The following tables describe how the data bytes are mapped to 8 16 and 32 bit devices When the Hawk compatibility mode is used there are two data mapping options When the Hawk data compatibility mode is not used the data is mapped as shown in the second table in this section When the Hawk data compatibility mode is used the data is mapped as shown in the third table in this section Refer to the section titled Hardware Configuration on page 2 133 for information on configuring the Xport modes Computer Group Literature Center Web Site XPORT Table 2 12 8 bit Device Byte Lane Mapping PowerPC Bus 8 bit Device Byte Address Address XAD 31 24 00000000 0 00000001 00000001 1 00000002 00000002 2 00000003 00000003 3 Table 2 13 16 bit Device Byte Lane Mapping PowerPC Bus 16 bit Device Byte Byte Address Address XAD 31 24 XAD 23 16 00000000 00000000 0 1 00000002 00000002 2 3 00000004 00000004 4 5 00000006 00000006 6 7 Table 2 14 Hawk Data Compatibility Byte Lane Mapping PowerPC Bus 16 bit Device Byte Byte Address Address XAD 31 24 XAD 23 16 00000000 00000000 0 00000001 00000001 1 00000002 00000002 2 00000003 00000003 3 00000004 00000004 4 00000005 00000005 5 00000006 00000006 6 00000007 00000007 7 http www motorola com
102. 3 33 SDSEA SDRAM Single bit Error Address SDRAM Single bit Error Address Reg ister SDSEA 3 36 SDTC Register 3 27 SECNT Single bit Error Count SDRAM Single bit Error Status Register SDSES 3 34 serial port interface device 2 94 Serial Presence Detect SPD used to configure SDRAM 5 2 single word definition xxiii single beat Reads Writes Computer Group Literature Center Web Site SDRAM accesses 2 6 SIZE Bank Size SDRAM Addressing Registers 3 30 sizing SDRAM optional method 5 3 5 9 snarfing defined 2 35 special cycles 2 40 spread I O address translation 2 38 spurioous vector generation 2 70 status bit definition xxiii store gathering mode 2 20 SWVT Swap Vector table SDRAM General Control Register SDGC 3 26 T TDPL SDRAM timing paramter tDPL SDRAM Timing Control Register SDTC 3 29 terminations types of DMA transfers 2 57 time out function PPC bus 2 129 timers 2 72 Timing DRAM Access 4 1 transfer throttling DMA activity 2 59 transfers address 2 5 data 2 5 TRAS SDRAM timing parameter tRAS SDRAM Timing Control Register SDTC 3 28 TRC SDRAM timing parameter tRC SDRAM Timing Control Register SDTC 3 27 TRCD SDRAM timing parameter tRCD SDRAM Timing Control Register SDTC 3 29 TRP SDRAM timing parameter tRP http www motorola com computer literature SDRAM Timing Control Register SDTC 3 29 true definition xxiii U UART as serial port device 2 94 function described 1 5
103. 4MB 128Mx8 00000000 00008000 20000000 1024MB 128Mx4 00000000 00010000 512MB 64Mx16 00000000 10000000 512MB 64Mx8 00000000 00008000 10000000 1 512MB 64Mx4 00000000 00008000 10000000 1 256MB 32Mx16 00000000 00004000 08000000 2 256MB 32Mx8 00000000 00004000 08000000 2 256MB 32Mx4 00000000 00008000 Computer Group Literature Center Web Site Programming SDRAM Related Control Registers Table 5 4 Address Lists for Different Bank Size Checks Size Addresses to Check Notes 128MB 16Mx16 00000000 04000000 128MB 16Mx8 00000000 00004000 3 128MB 16Mx4 00000000 00004000 3 64MB 8Mx16 00000000 00002000 4 64MB 8Mx8 00000000 00002000 4 32MB 4Mx16 00000000 00001000 5 Notes 1 64Mx8 and 64Mx4 are the same If the real size is either one of these this algorithm will program for 64Mx8 regardless of whether the SDRAM size is 64Mx8 or 64Mx4 This is not a problem because the Harrier behaves identically when programmed for either size 2 32Mx16 and 32Mx8 are the same The same idea that applies to 64Mx8 and 64Mx4 applies to them 3 16Mx8 and 16Mx4 are the same The same idea that applies to 64Mx8 and 64Mx4 applies to them 4 8Mx16 and 8Mx8 are the same The same idea that applies to 64Mx8 and 64Mx4 applies to them 5 This is needed only to check for non zero size e Read back all of the addresses th
104. 8 CONFIG_DATA 2 38 configuration cycles 2 38 Configuration Mechanism 1 2 38 3 19 control bit definition xxiii conventions manual xxii Copy back Snarfing controlling register BXCS 2 35 copyback snarfing 2 35 copy back write cycles 2 35 counter as part of watchdog timer 2 120 Critical Word First CWF transfers 2 20 CSR s Readability 2 69 Current Address Read I2C 2 87 current task priority processor 2 69 Current Task Priority Level 2 81 cycle types SDRAM ECC 2 7 D data types within Xport transactions 2 97 data parity PowerPC data 2 130 data transfers how done 2 5 decimal number xxii decoding configuration devices 2 40 delayed transaction protocol PPC Slave 2 17 DERC Disable Error Correction SDRAM General Control Register SDGC 3 26 DEVSEL pin IN 2 for mapping PCGS Register Group 2 25 direct delivery mode 2 72 distributed delivery mode 2 73 DMA Controller function described 1 5 Doorbell registers 2 66 double word definition xxiii DREF Disable Refresh SDRAM General Control Register SDGC 3 26 E EEPROM use with SDRAM configuration 5 2 ENB Bank Enable SDRAM Addressing Registers 3 31 ENRV Enable Reset Vector SDRAM General Control Register SDGC 3 26 EOI register MPIC 2 81 EOS Error On Scrub SDRAM Single bit Error Status Register SDSES 3 34 EREADY 2 132 Error Diagnostics function described 1 6 error diagnostics Harrier registers used 2 127 error exceptions how reported 2 71 erro
105. 859935585 Function Name EEST Exceptions 3uunsuszugis CEBE 2225 A a A a a A y A d amp 2 Operation d d ed d eo cd ed d d ed d en ed eo en ed eo en d d ed cd d d cr ed e en ad Reset ecoadgooeodgococdaccaGcaGccoccacGcaogocoococococcocogdcaooocoo The Error Exception Status Register EEST is a read only register that provides an array of status bits pertaining to the various Error Exceptions that the Harrier can generate The fields within the EEST register are defined as follows PMA PCI Master Abort This bit is set when the PowerPC to PCI Bridge or the DMA Controller performs a master abort when the EEEN PMA is enabled and all other PCI error status bits are cleared If the EEINT PMA is set a processor interrupt will be generated If the EEMCKO PMA is set a machine check to processor 0 will be generated and if the EEMCKI PMA is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PMA bit PTA PCI Target Abort This bit is set when the PowerPC to PCI Bridge or the DMA Controller receives a target abort when the EEEN PTA is enabled and all other PCI error status bits are cleared If the EEINT PTA is set a processor interrupt will be generated If the EEMCKO PTA is seta machine check to processor 0 will be generated and if the EEMCK1 PTA is set a machine check to processor
106. A MIDP When the enable bit is cleared the exception is disabled and the status bit will always read zero UAO0 UART 0 If set the UART 0 exception is enabled When the exception is enabled the status bit FEST UAO will indicate the state of the UART 0 exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA UAO When the enable bit is cleared the exception is disabled and the status bit will always read Zero UA1 UART 1 If set the UART 1 exception is enabled When the exception is enabled the status bit FEST UA 1 will indicate the state of the UART 1 exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA UA1 When the enable bit is cleared the exception is disabled and the status bit will always read Zero http www motorola com computer literature 3 165 Programming Model ABT Abort If set the Abort exception is enabled When the exception is enabled the status bit FEST ABT will indicate the state of the Abort exception The interrupt can be polled by setting the enable bit and setting the mask bit FEMA ABT When the enable bit is cleared the exception is disabled and the status bit will always read Zero Functional Exception Status Register Offset XCSR 044 Function Exceptions Operation Reset The Functional Exc
107. A registers in the case of an SDRAM multi bit scrub error and SDMEA register in the case of an SDRAM multi bit error due to a PowerPC access In the case any SDRAM multi bit error detected while any other SDRAM multi bit error status bit is already set the SDRAM multi bit overflow EEST SMOF bit will be set in the EEST register and further logging of SDRAM multi bit errors is suspended until software clears the first error and the EEST SMOF bit The following table shows how the Harrier captures address and attribute information for various error exceptions Table 2 23 Error Exceptions and Address Attribute Capture Error Status Error Address and Attributes XBT From PowerPC bus XAP From PowerPC bus XDP From PowerPC bus XDT From PowerPC bus PMA From PCI bus PTA From PCI bus PAP From PCI bus PDP From PCI bus Computer Group Literature Center Web Site PowerPC Address Bus Timer Table 2 23 Error Exceptions and Address Attribute Capture Continued Error Status Error Address and Attributes PMR From PCI bus PDT From PCI bus PSE Invalid PPE Invalid PowerPC Address Bus Timer The PPC Timer allows the current bus master to recover from a potential lock up condition caused when there is no response to a transfer request The time out length of the bus timer is determined by the BTO field within the GCSR register The PPC Timer is designed to handle the case where an address tenur
108. ARB register are defined as follows PRI Priority This field is used by the PCI Arbiter to establish a particular bus priority scheme The encoding of this field is show in the following table Table 3 50 PARB PRI Encoding PRI Priority Scheme 00 Fixed 01 Round Robin 10 Mixed 11 Reserved 3 156 Computer Group Literature Center Web Site Arbiters PRK Parking This field is used by the PCI Arbiter to establish a particular bus parking scheme The encoding of this field is shown in the following table Table 3 51 PARB PRK Encoding Parking Scheme Park on last master Park always on PARB6 Park always on PARB5 Park always on PARB4 Park always on PARB3 Park always on PARB2 Park always on PARBI Park always on PARBO Park always on HARR 1111 None HIE Hierarchy This field is used by the PCI Arbiter to establish a particular priority ordering when using a fixed or mixed mode priority scheme When using the fixed priority scheme the encoding of this field is show in the following table Table 3 52 PARB HIE Fixed Mode Encoding HIE Priority ordering highest to lowest 000 PARB6 gt PARBS PARBA gt PARB3 PARB2 PARBI PARBO gt HARR 001 HARR gt PARB6 gt PARBS gt PARB4 gt PARB3 gt PARB2 gt PARBI gt PARBO 010 PARBO gt HARR gt PARB6 gt PARB5 gt PARB4 gt PARB3 gt PARB2 gt PARBI 011 PARBI PARBO gt HARR PARB6
109. ART Controller Table 3 39 UART Interrupt Control Functions Continued IID2 IID1 IIDO IPEN Priority Interrupt Interrupt Source Interrupt Reset Level Type Control 0 1 0 0 Second Received Data Receiver Data Reading the Receiver Available Available or Trigger Buffer Register or Level reached the FIFO drops below the Trigger Level 1 1 0 0 Second Character No characters have Reading the Receiver Time out been removed from or Buffer Register Indication input to the RCVR FIFO during the last 4 Char Times and there is at least 1 Char in it during this time 0 0 1 0 Third Transmitter Transmitter Holding Reading the Interrupt Holding Register Empty Identification Register Register if source of Empty interrupt or Writing into the Transmitter Holding Register 0 0 0 0 Fourth MODEM Clear To Send or Data Reading the Status Set Ready or Ring MODEM Status Indicator or Data Register Carrier Detect IDFCx IDFCx is the write only FIFO Control Register that is used to enable the FIFOs clear the FIFOs set the receiver FIFO trigger level and select the type of DMA signalling The fields within this register are defined as follows http www motorola com computer literature 3 139 Programming Model RFTL 1 0 Receiver Trigger Level These bits are used to set the trigger level as shown in the following table for the Received Data Available interrupt ERBFD Table 3 40 Receiver FIFO Trigger Level RF
110. Burst 10010 Write with flush atomic PCI Status Register Perspective from the PCI Bus Offset PCFS 80 Bit Aa qz d o oq d A o od didla Function Name PSTA Status Operation a n A A y R R R Reset Aala ala 00 00 00 http www motorola com computer literature 3 75 Programming Model Perspective from the PowerPC Bus Offset XCSR 380 Bit p E ddcddad lt qd N od o g 4 goyaga Function Name PSTA Reflected PCI Configur ation Operation R R R Mudo Space Reset 00 00 00 adaddd The PCI Status Register contains the Loop Back Access bit The LBA bit allows software to determine if the configuration space access is looping back to the PCI configuration space in the Harrier In other words if the Harrier is reading its own configuration space The LBA bit is defined as follows LBA Loop Back Access The LBA bit is read as a one when read by the PCI bus master in the Harrier The LBA bit is read as a zero when read by another PCI bus master The LBA bit always reads zero from the PowerPC bus PCI General Purpose Register Perspective from the PCI Bus Offset PCFS 84 Bit o o od cd Function Name General Operation R W Purpose Register Reset 00000000 3 76 Computer Group Literature Center Web Site PowerPC to PCI Bridge Perspective from the PowerPC Bus Offset XCSR 384 Bit c P dtcdad
111. Bus Xport Bus Address Address Address Address Address Address Address Address 4GB 128MB 16 bit 16 bit 24 bit Latch Latch Latch 4GB 256MB 4GB A5 A26 XADIS A25 XADRO LXADI18 A24 XADRO LXAD18 A4 A27 XADI9 LXADI9 A25 XADRI LXADI9 A3 A28 XAD20 LXAD20 A26 LXAD20 A2 A29 XAD21 LXAD21 A27 LXAD21 Al A30 XAD22 LXAD22 A28 LXAD22 AO A31 XAD23 A30 LXAD23 A29 LXAD23 Xport Bus XAD Mapping The table below shows the function of the XAD lines during the address phase and data phase During the address phase XAD 23 0 are address lines During the data phase the width of the device determines which XAD signals are address lines and which are data lines The data lines of 8 bit devices are connected to XAD 31 24 The data lines of 16 bit devices are connected to XAD 31 16 The data lines of 32 bit devices are connected to XAD 31 0 Table 2 10 Xport Bus XAD Mapping XAD Address Data Phase Data Phase Data Phase Phase 8 bit 16 bit 32 bit XAD7 XADO 60x A24 A31 60x A24 A31 60x A24 A31 Device D7 DO XADIS5 XADS8 60x A16 A23 60x A16 A23 60x A16 A23 Device D15 D8 XAD23 XAD16 60x A8 A15 60x A8 A15 Device D7 DO Device D23 D16 XAD29 XAD24 Byte Count Device D5 DO Device D13 D8 Device D29 D24 XAD30 Reserved Device D6 Device D14 Device D30 XAD31 Read Write Device D7 Device D15 Device D31 2 108 Computer Group Literature Center Web Site XPORT Hawk Compatibility Mode In a previous design Hawk
112. C bus transfer characteristics Each Inbound Translation Function also includes a programmable 16 bit address offset that is added to the PCI address in a two step process The first step is to subtract the base address from the PCI address This essentially zero s out all bit positions of the PCI address that correspond to programmable bit positions within the BAR The second step is to add the programmable offset to the 16 most significant bits of the results of the first step and the result is used as the PowerPC address This offset provides a high degree of decoupling between PowerPC address space and PCI address space An example of this is show in the figure below Computer Group Literature Center Web Site PowerPC to PCI Bridge PCI Bus Address 4 0 4 112 3 4 5 4 0 4 0 4 1 2 3 31 5 31 0 161 0 1615 is A J Zero Out O0 0 01 2 3 4 5 0 0 0 0 0 1 2 3 PCI Base Address 31 1615 0 31 1615 0 ITOFx Register C Y y E C y bd 1 Y PowerPC Bus Address 6 0 6 1 2 3 4 5 6 0 6 0 0 1 2 3 0 1516 31 0 1516 31 Figure 2 9 Inbound Address Translation All address decoding is prioritized so that programming multiple functions to respond to the same address is not a problem When the PCI address falls into the range of more than one function only the highest priority one will respond The functions are prioritized as shown in the table below Table 2 3 Map Decoder Priority Decoder Priority
113. CI space then this field will represent a PCI address If the source is PowerPC space then this field will represent a PowerPC address Software can read this register after a DMA error to determine how far along a DMA transfer went before the error occurred 3 90 Computer Group Literature Center Web Site DMA Controller During a FIFO fill SMA RTA or MRC error with the PCI bus as the transfer source this register will represent the PCI address at which a read error occurred During a FIFO fill XBT error with the PowerPC bus as the transfer source this register will represent the PowerPC address at which a read error occurred DMA Current Destination Address Register Offset Bit XCSR 284 Function DCDA R 00000000 Name Operation Reset The DMA Current Destination Address Register DCDA is a read only register that contains the current destination address for a DMA transfer The current destination address is the next address that the DMA Controller is about to attempt If the destination is PCI space then this field will represent a PCI address If the destination is PowerPC space then this field will represent a PowerPC address Software can read this register after a DMA error to determine how far along a DMA transfer went before the error occurred During a FIFO empty SMA RTA or MRC error with the PCI bus as the transfer destination this register will represent the PCI address
114. CS provides control and status information associated with PCI functions The fields within the BPCS are defined as follows OFBR Outbound Flush Before Read If set the Harrier guarantees that all outbound write posted transactions are completed before any inbound read transactions are allowed to complete If cleared there is 3 38 Computer Group Literature Center Web Site PowerPC to PCI Bridge no correlation between these transaction types and their order of completion Please refer to the section titled Transaction Ordering in the previous chapter for more information DLR Disregard Latency Requirements If set the Harrier does not honor PCI initial and subsequent latency requirements If an access exceeds these requirements the Harrier does not initiate a disconnect and inserts wait states as needed to complete a transaction If cleared the Harrier complies with PCI latency requirements Users are strongly encouraged to leave the DLR field cleared Please refer to the section titled PCI Slave in the previous chapter for more information HIL Host Bridge Initial Latency This field is only applicable if the DLR field is cleared If set the Harrier implements a 32 clock i e cache hit host bridge initial latency If cleared the Harrier implements a 16 clock non host bridge initial latency MRC Maximum Retry Count This field enables a 274 counter in both the DMA and Bridge PCI masters that keep track of the number of sequen
115. CTLO LSTAO MSTAO SCRTO 0C8 RTDLI IEDHI IDFCI LCTL1 0CC 0D0 MCTLI LSTAI MSTAI SCRTI 0D4 0D8 0DC http www motorola com computer literature 3 5 Programming Model Table 3 2 PowerPC Control and Status XCSH Register Group Continued Function Offset Bits 0 7 s 15 16 23 24 31 MPIC 0E0 MBAR 0EA MCSR MIRS 0ES8 melos 0FC SDRAM Control 100 SDGC Interface 104 SDTC 108 Address 110 SDBAA 114 SDBAB 118 SDBAC 11C SDBAD 120 SDBAE 124 SDBAF 128 SDBAG 12C SDBAH Scrub 130 SDSC 134 SDSA 138 13C Error 140 SDSES Log 3 6 Computer Group Literature Center Web Site Register Group Summary Table 3 2 PowerPC Control and Status XCSH Register Group Continued Function Offset Bits 0 7 s 15 16 23 24 31 Xport Address 150 XPARO amp 154 XPATO Attribute 158 XPARI 15C XPAT1 160 XPAR2 164 XPAT2 168 XPAR3 16C XPAT3 General 170 XPGC Control 174 178 17C I2CO 180 I2PSO 184 I2COO 188 18C I2TDO 190 194 I2STO 198 19C I2RDO http www motorola com computer literature 3 7 Programming Model Table 3 2 PowerPC Control and Status XCSR Register Group Continued Function Offset I2C1 1A0 1A4 1A8
116. Center Web Site DMA Controller 4 PowerPC Bus Byte Steering Master Figure 2 12 DMA Controller Block Diagram Architecture The DMA Controller is a stand alone function that does not infringe on other Harrier resources The core of the DMA Controller is the DMA FIFO This FIFO is a 64 bit by 64 entry 512 byte FIFO The FIFO is used for all transfers regardless of the direction of the transfer All interactions with the PowerPC bus are handled by the DMA PPC Master This module is optimized to transfer data over the PowerPC bus in multiple cache line bursts All interactions with the PCI bus are handled by the DMA PCI Master This module strives to transfer data in continuous 64 bit burst http www motorola com computer literature 2 49 Functional Descriptions transfers although 32 bit burst transfers are supported if used within a 32 bit PCI environment The DMA Scheduler is a module that oversees the entire DMA operation The cache coherency rules for the inbound and outbound FIFOs apply to the DMA FIFO The Harrier does not snoop the PowerPC bus for data held within the DMA FIFO therefore caution should be exercised when using the DMA Controller to move data within coherent memory space The DMA Controller does not need to participate in any contention handling protocol There will never be a time when the completion of a transaction on either the PCI bus or the PowerPC bus is depending on
117. FO Size 000 2 KBytes 001 4 KBytes 010 8 KBytes 011 16 KBytes 100 32 KBytes 101 64 KBytes 110 128 KBytes 111 256 KBytes 3 102 Computer Group Literature Center Web Site Message Passing MP 150 Queue Base Register Offset XCSR 2E4 Operation Reset The MP LO Queue Base Register MIQB represents the base address of the IO Quad FIFO circular queues The circular queues may be placed anywhere within PowerPC address space on 1MB boundaries The field within the MIQB register is defined as follows QBA Queue Base Address Base address of circular queue structure PMEP Register Group The following subsections identify and describe the registers within the PMEP Register Group MP 150 Interrupt Status Register Offset PMEP 030 did d A o H d Function Bit o o oq g o o od d OC o od Name MIST LO G 00 00 00 Reset o 99o 9g og g The MP DO Interrupt Status Register MIST contains status information for interrupts associated with the Outbound Post_list circular queue The field within the MIST register is defined as follows http www motorola com computer literature 3 103 Programming Model OPI Outbound Post list Interrupt This is a read only bit indicating a new entry resides within the Outbound Post list FIFO If the MIMS register permits the setting of this bit will also generate a PCI interrupt This bit and the interrupt associated with this
118. G BUS DEV FUN REG ADDRESS TT Hase Wo 3 a a cd a w ea ed Reset A4cociececg 00 00 0 00 ad Perspective from the PowerPC bus Offset CFS CF9 CFA CFB Bit DH ci i d and g and cei xe c N ed g o Function Name CONFIG ADDRESS Operation Reset 3 52 Computer Group Literature Center Web Site PowerPC to PCI Bridge The register fields are defined as follows REG Register Number Configuration Cycles Identifies a target word within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all zeros FUN Function Number Configuration Cycles Identifies a function number within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all ones DEV Device Number Configuration Cycles Identifies a target s physical PCI device number Refer to the section titled Generating PCI Cycles on page 2 36 for a description of how this field is encoded Special Cycles This field must be written with all ones BUS Bus Number Configuration Cycles Identifies a targeted bus number If written with all zeros a Type 0 Configuration Cycle will be generated If written with any value other than all zeros then a Type 1 Configuration Cycle will be generated Special Cycle
119. Harrier Application Specific Integrated Circuit ASIC Programmer s Reference Guide Parts 1 and 2 ASICHRA1 PG1 and ASICHRA2 PG1 May 2001 Edition Copyright 2001 Motorola Inc All Rights Reserved Printed in the United States of America PowerPC and the PowerPC logo are registered trademarks of International Business Machines Corporation and are used by Motorola Inc under license from International Business Machines Corporation Motorola and the Motorola symbol are registered trademarks of Motorola Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved
120. IDE1 XMPI 01170 TIDE2 XMPI 011B0 TIDE3 XMPI 011F0 Bit Function Name Timers a a Operation R R R 4 e4 c4 c ed ed a 3 q Reset 00 00 00 dddddadd The Timer Destination Registers TIDE0 TIDE1 TIDE2 and TIDE3 indicate the destination for timer interrupts Timer interrupts operate in the Directed delivery interrupt mode This register may specify multiple destinations multicast delivery The fields within the TIDEx registers are defined as follows P1 Processor 1 The interrupt is directed to processor 1 P0 Processor 0 The interrupt is directed to processor 0 http www motorola com computer literature 3 123 Programming Model External Source Vector Priority 0 through 15 Registers Offset Bit Name EXVP0 XMPI 10000 EXVP1 XMPI 10020 efc EXVP14 XMPI 101C0 EXVP15 XMPI 101E0 EXVPx External PRIOR VECTOR Operation R W MASK ACT R W R Reset 0 00 00 The External Source Vector Priority Registers EX VP0 through EXVP15 establish vectoring and priority information for external interrupts The fields within the EXVPx registers are defined as follows 3 124 MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The acti
121. IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers is used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when the MASK bit is lowered Interrupt Selector IS There is a Interrupt Selector IS for each processor The IS receives interrupt requests from the IPR If the interrupt requests are from an external source they are qualified by the destination bit for that interrupt and processor If they are from an internal source they have been qualified The output of the IS will be the highest priority interrupt that has been qualified This output is the priority of the selected interrupt and its source identification The IS will resolve an interrupt request in two PowerPC clock ticks The IS also receives a second set of inputs from the ISR During the End Of Interrupt cycle these inputs are used to select which bits are to be cleared in the ISR http www motorola com computer literature 2 75 Functional Descriptions Interrupt Request Register IRR There is a Interrupt Request Register IRR for each processor The IRR always passes the output of the IS except during Interrupt Acknowledge cycles This guarantees that the vector which is read from the Interrupt Acknowledge Register is not changing due to the arrival of a higher priority interrupt The IRR als
122. MB The Inbound Translation Offset Registers ITOF0 ITOF1 ITOF2 and ITOF3 contain offset information associated with the mapping of PowerPC address space to PCI memory space The ITOFx field represents 3 70 Computer Group Literature Center Web Site PowerPC to PCI Bridge a 16 bit offset that is added to the upper 16 bits of the PCI address to determine the PowerPC address used for inbound transfers This offset allows PowerPC resources to reside at addresses that would not normally be visible from the PCI bus Note that the ITOFXx register is byte swapped when accessing from the XCSR Register Group For example programming an offset of 1234 within the PCFS Register Group would be the same as programming 3412 within the XCSR Register Group Inbound Translation Attribute 0 1 2 and 3 Registers Perspective from the PCI Bus Offset ITATO PCFS 4C ITATI PCFS 54 ITAT2 PCFS 5C ITAT3 PCFS 64 Bit Function Name Address Transla 3 z gt Z g amp 3 tion E Operation R a I Ja PPEPEEEE LEEECEEE EEEEECEE Reset 00 ceecc cdcdcozo d2 c d Acdcada dad http www motorola com computer literature 3 71 Programming Model Perspective from the PowerPC Bus Offset ITATO XCSR 34C ITAT1 XCSR 354 ITAT2 XCSR 35C ITAT3 XCSR 364 Bit Name Function Reflected PCI Configur ation Operatio
123. MMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 100us 100KHz SCL has been expired Figure 2 19 Programming Sequence for I2C Random Read 2 86 Computer Group Literature Center Web Site I2C Interface Current Address Read The PC slave device should maintain the last address accessed during the last C read or write operation incremented by one The first step in the programming sequence should be to test the CMP bit for the operation complete status The next step is to initiate a start sequence by first setting the STA and ENA bits in the I2COx Register and then writing the device address bits 24 30 and read bit bit 31 1 to the IZTDx Register The CMP bit will be automatically clear with the write cycle to the 2TDx Register The I2STx Register must now be polled to test the CMP and ACKI bits The CMP bit becomes set when the device address and read bit have been transmitted and the ACKI bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the I C master controller writes a dummy value data don t care to the IZTDx Register This causes the PC master controller to initiate a read transmission from the slave device Again CMP bit must be tested for proper response After the IC master controller has received a byt
124. NVNVTNYTNYTNYTNYN Data latching edge Figure 2 30 Xport Bus One Beat Read Transaction in Basic Mode The following figure shows an Xport Bus write when XCSR XPAT BAM is set AD inserts 0 15 CLK s here Kk ok Ann nannini NIAYNTNTNYNTNYAY Cu ea ee ee NL anvo ra X ok XA DX XAD Dx adress XALE z XWExx XWAIT_ Figure 2 31 Xport Bus One Beat Write Transaction in Basic Mode 2 104 Computer Group Literature Center Web Site XPORT Xport s Xport Bus master has a special Hawk compatibility mode that is enabled when the XCSR XPAT DW bits are set to 1 1 When in this mode the channel width is fixed at 16 bits XALE s polarity reverses and the XCSR XPAT BAM control bit has the same effect on timing whether in Hawk compatibility mode or not The following figure shows Hawk compatibility mode an Xport Bus single read transaction in a AD inserts 0 15 CLK s here k ek ADDIS Mose Ts a uc XAD 6 0 XADR 7 1 DX hraddr X lowaddr 4 XAD 31 16 CT AE GSC O4 MAUVE i37 3 JIE XOE 0 0 Ne i XWAIT_ Data latching edge j Figure 2 32 XportBus One Beat Read Transaction in Hawk Compatibility Mode The following figure shows an Xport Bus single write transaction in a Hawk compatibility mode http www motorola com computer literature 2 105 Functional Descriptions di AD inserts 0 15 CLK
125. O PCFS 14 ITBARI PCFS 18 ITBAR2 PCFS 1C ITBAR3 PCFS 20 Bit Function Name ITBARx Header BASE tds adda Operation R W R R td c4 c rd Reset 00000 0 0 Jog q 3 62 Computer Group Literature Center Web Site PowerPC to PCI Bridge Perspective from the PowerPC Bus Offset ITBARO XCSR 314 ITBARI XCSR 318 ITBAR2 XCSR 31C ITBAR3 XCSR 320 Bit Function Name Reflected PCI Configur ation Space Operation Reset The Inbound Translation Base Address Registers ITBARO ITBAR1 ITBAR2 and ITBAR3 control the mapping of the Inbound Translation function within PCI Memory space IO ME I O Space Indicator This is a read only inverted copy of the MEM bit defined in the ITATx register The IO MEM field reflects the ability of the Inbound Translation Function to support either memory space or I O space accesses This field is accessible only when the ENA bit is set in the ITATx register Upon reset this bitis set to a zero indicating this resource is a memory space resource MTYP Memory Type These bits are hard wired to zero to indicate that the Inbound Translation Function can be located anywhere in the 32 bit address space PRE Prefetch This is a read only copy of the PRE bit defined in the ITATx register The PRE field reflects the ability of the Inbound Translation Function to support prefetching This field is accessible only when the ENA bit is set in the ITATx regis
126. O signal asserted for 100 us after the reset inputs are negated The Harrier provides support for an external reset switch that can be connected to the RSTSW_ input The RSTSW input is debounced and has a three second delay The RSTSW_ signal must be asserted for three seconds before the RSTO_ signal is generated The three second delay is included to allow the RSTSW_ and the ABTSW_ abort switch signals to be connected together This allows a single switch to be used for the abort and reset functions When the switch is pressed an abort interrupt is generated and if the switch is held for three seconds the RSTO_ signal is asserted The Harrier provides an auxiliary reset input signal AUXRST_ The AUXRST input allows other reset sources on the board to be combined with the Harrier s internal reset sources For example a watchdog timer output from the Harrier can be connected to the AUXRST_ input Software can initiate a reset out signal by setting the reset out bit XCSR MCSR RSTOUT The reset out bit will remain asserted until it is reset by the RST_ signal When the Harrier receives a reset in signal RST_ it saves the state of reset out bit reset switch and auxiliary reset input Software can determine the source of the reset by reading the bits in the XCSR GCSR register PPMC Features 2 132 The Harrier includes several signals for use in the PPMC environment These are the SCON_ EREADY INT A D _ and BRDFL_ signals The SC
127. ON_ signal is an input signal that can be connected to the MONARCH signal on the PPMC connector This allows software to read the state of the MONARCH signal Computer Group Literature Center Web Site Hardware Configuration The EREADY signal is an open drain bi directional signal that can be connected to the EREADY signal on the PPMC connector When PURST_ or RST is asserted the EREADY bit is cleared and the EREADY signal is driven low This indicates that the board is not ready After the software has initialized the board the EREADY bit can be set When all the boards are ready the EREADY signal is pulled high The software can check the status of the EREADY signal by reading the EREADYS bit Hardware Configuration Harrier has the ability to perform custom hardware configuration to accommodate different system requirements It has several functions that may be optionally enabled or disabled using passive hardware external to the Harrier itself Normally pullup and pulldown resistors are used to configure the state of the XAD bus while PURST is asserted The selection process occurs when PURST_ is asserted and the configuration values are latched when PURST_ is negated All of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time The following table summarizes the Harrier s hardware configuration options The power up reset timing requirements are shown in the figure following this table
128. PCI Slave manages to empty the FIFO beyond a certain programmable threshold If a write data path FIFO limit is reached then the PCI Slave continually issues retries until the PPC Master manages to empty some portion of the FIFO The Harrier does not support byte merging or byte collapsing Each and every single beat byte transaction presented to the PCI Slave is presented to the PowerPC bus as a unique single beat transfer The Harrier does not support PowerPC or PCI bus snooping Care should be exercised when using write posting or read ahead within coherent address space PPC Master The PPC Master can transfer data either in 1 to 8 byte single beat transactions or 32 byte four beat burst transactions This limitation is strictly imposed by the PowerPC bus protocol The PPC Master attempts to move data using burst transfers whenever possible If a transaction starts on a non cache line address the PPC Master performs as many single beat transactions as needed until the next highest cache line boundary is reached If a write transaction ends on a non cache line boundary then the PPC Master finishes the transaction with as many single beat transactions http www motorola com computer literature 2 33 Functional Descriptions as needed to complete the transaction The table below shows the relationship between starting addresses and PowerPC bus transaction types when write posting and read ahead are enabled Table 2 4 PPC Master Tran
129. PowerPC Arbiter to control how bus pipelining will be affected after all single beat write cycles The encoding of this field is shown in the following table http www motorola com computer literature 3 159 Programming Model Table 3 54 XARB FBR FSR FBW FSW Encoding FBR FSR FBW FSW Effects on Bus Pipelining o 01 None 10 Flatten always 11 Flatten if switching masters TBS Three Bridge System If set the PowerPC Arbiter will enable the latching request protocol on the CPU1 request grant pair This protocol is normally reserved for bridge devices and is not intended to be used with processor devices If cleared the latching request protocol will not be enabled for the CPU1 request grant pair PRK Parking This field determines how the PowerPC Arbiter will implement CPU parking The encoding of this field is shown in the following table Table 3 55 XARB PRK Encoding PRK CPU Parking 00 None 01 Park on last CPU 10 Park always on CPUO 11 Park always on CPUI ENA Enable This read only bit indicates the enabled state of the PowerPC Arbiter If set the PowerPC Arbiter is enabled and is acting as the system arbiter If cleared the PowerPC Arbiter is disabled and external logic is implementing the system arbiter Please refer to the section titled Hardware Configuration on page 2 133 for more information on how this bit gets set 3 160 Computer Group Literature Center Web Site
130. R 164 XPAT3 XCSR 16C Bit 4 44444 44434 2334253228484838593585 Function Name XPAT Xport z Li BR BW d a AD a D D Operation zi zi z c 3x32 RW loose ddd RW gda RW Repet 199999 F GAGqadqdqgqaaqa 0 o aa 0 The Xport Attributes Registers XPATO XPAT1 XPAT2 and XPAT3 define the attributes for each of Xport channels 0 1 2 and 3 The fields within the XPATX registers are defined as follows REN Read Enable When set the channel responds to PowerPC reads When cleared it does not respond unless the access is to the FFF00000 SFFFFFFFF address range and RVENO RVEN1 RVEN2 or RVENG is set WEN Write Enable When set the channel responds to PowerPC writes When cleared it does not respond unless the access is to the FFF00000 SFFFFFFFF address range and RVENO RVEN1 RVEN2 or RVEN3 is set BAM Basic Mode When set the channel uses basic conservative timing as shown in the section titled Xport Bus Transaction Examples RVEN Reset Vector Enable Together with RVEN from the other three channels RVEN determines which if any of Xport channels 0 1 2 or3 is the source for reset vector fetches or for any other accesses in the range SFFF00000 SFFFFFFFF The following table shows the encoding Note that RVEN enables SFFF00000 SFFFFFFFF accesses regardless of the state of the REN and WEN control bits RVENO http www motorola com computer literature 3 151 Programming Mo
131. RAM RCM S odd etos MM uM MU ME ME 2 6 ipli l de a n 2 7 LE ais eatin ae eee es 2 10 FN aaa MQ P 2 10 gi ix og 7 PRICE mn MATRE 2 11 Data Flow Vert FNIT OO 2 11 PIE D NT 2 12 Outbound Fonctions TOT 2 14 PPL oc 2 14 vii DU dino aes teas isn vn Sanda DSA EAM NEAN EE 2 16 Sean FIFI esisiini tn na N 2 19 eB rn A E E nantes 2 19 O AE E E E RA T 2 20 i1 0p a har A A 2 22 Pate SG sn NAAN 2 23 ID Uod seenen ARANNA 2 24 issu Fane honi csar n tne 2 25 aa o T EN E E Ce E E OT 2 25 Pe E EE E E EE RU 2 30 inet o 8 epe 2 32 PPC Mioi aas e d dd lieu ane adc bU d cs M D 2 33 bb o dl 0 2 34 IDE I EUR AER NP P TW He PCIE IS 2 35 OIG Ge NEB TR 2 35 3 S RTT err ttre 2 36 Pr vn c in ice Hd 2 36 Lucr Fees iis erat RP A EA NM RM MEM 2 36 FEO o Jer 2 41 blur uo lr NN T 2 41 i09 M HEY 2 41 TRACT EUG IL 2 44 PX a eerie eerie 2 45 DMA Controller E i8i6Si 2 48 Pool fer RC EE 2 49 EDU MODE e oed ERE AEA 2 50 Direction OF Data MOVERSE ree ie aao OO Oo Qd bitutebitetgi icon 2 52 Addressing ma EU I DIZES MEMENTO REOR 2 53 Mary a IL MEET TITEL 2 54 Bn DC IE E rp o ET 2 56 Tronsrer Tarmin
132. RD XCSR XPAT BWD for each beat after the first in the burst The following figure shows a two beat read transaction with no bursting and XCSR XPAT BAM http www motorola com computer literature 2 99 Functional Descriptions AD inserts 0 15 CLK s here ert zi Vege evan PU PSP auae Nose TERAS T Te ec emis XAD DXaddress gt Gat Gat Wee aie XWAIT EH WE E WES Data latching edges Figure 2 26 Xport Bus Two Beat Read Transaction No Bursting The following figure shows a multi beat read transaction with bursting on and XCSR XPAT BAM cleared The burst size matches the number of beats to transfer Note the use of XWAIT_ to extend the last data beat 2 100 Computer Group Literature Center Web Site me CLK s XPORT BRD inserts 0 7 CLK s here ek AAAA ATAATA AAAA Mes EEE ls a XA ae address _ b address X address X address P XAD DXadiress5 QI Gai DEES TE Ed E ERE HER ERERERER HEINE MOE ee ee ee lt WAT_ YY amr 27 E Data latching edges Figure 2 27 Xport Bus 4 beat Read Transaction with Burst Size of 4 The following figure shows a multi beat write transaction with bursting turned on and XCSR XPAT BAM cleared The burst size is greater than the number of beats to transfer XWAIT delays one data http www motorola com computer literature 2 101 Functiona
133. RI Cache line Read Invalidate When set forces the use of Read with intent to modify commands This forces processor cached data in the E and S states to be invalidated during snoop hits When cleared uses non RWITM commands which allows the processor to retain cached data in the E and S states Please refer to the following table for the transfer codes associated with this bit AWL Atomic With Lock When set will force the use of atomic transfer types whenever possible during PCI lock cycles When cleared non atomic transfer types are used Please refer to the following table for the transfer codes associated with this bit Computer Group Literature Center Web Site PowerPC to PCI Bridge Table 3 28 Harrier Generated Transfer Types Origin CRI CWF AWL Transfer Size TT 0 4 Transfer Type PCI Read or X Single Beat or 01010 Read DMA Read Burst X Single Beat or 01110 Read with intent to modify Burst PCI Read 0 Single Beat or 01010 Read Lock Burst 1 Single Beat or 11010 Read atomic Burst 0 Single Beat or 01110 Read with intent to modify Burst 1 Single Beat or 11110 Read with intent to modify atomic Burst PCI Write or X Single Beat 00010 Write with flush DMA Write x Burst 00110 Write with kill X Burst 00010 Write with flush PCI Write X 0 Single Beat 00010 Write with flush EDGE x 0 Burst 00110 Write with kill x 0 Burst 00010 Write with flush X 1 Single Beat 10010 Write with flush atomic x 1 Burst 00110 Write with kill X 1
134. Read 2 87 Page Write 2 89 Random Read 2 85 Sequential Read 2 91 I20 Message Passing 2 60 I2O Generic Message Passing function described 1 5 I2RDx Register Current Address Read 2 87 Random Read 2 85 Sequential Read 2 91 I2STx Register 2 83 Current Address Read 2 87 Page Write 2 89 Random Read 2 85 Sequential Read 2 91 I2TDx Register 2 83 Current Address Read 2 87 Page Write 2 89 Random Read 2 85 Sequential Read 2 91 IDSEL lines in configuration lines 2 39 role in configuration cycles 2 39 IMU Enable 2 64 IMU Interrupts 2 65 IMU Queue Structure 2 63 Inbound FIFO Xmuoz xmo z Index role components 2 32 inbound tansaction key elements 2 25 inbound transaction defined 2 25 Inbound Translation Function address offset 2 28 initializing SDRAM control registers 5 3 In Service Register ISR 2 76 Interprocessor Interrupts IPI 2 70 Interrupt Acknowledge Cycles 2 41 interrupt acknowledge register MPIC 2 81 interrupt delivery modes 2 72 interrupt events nesting 2 70 Interrupt Pending Register IPR 2 75 Interrupt Request Register IRR 2 76 Interrupt Router 2 76 Interrupt Selector IS 2 75 interrupt source priority 2 69 interrupts for DMA Controller 2 58 IOP Agent ID 2 65 IOP Message Unit 2 61 IRQO_ active state 2 77 ITATx registers role in read ahead mode 2 35 role in write posting mode 2 34 L latency requirements 2 31 manual terminology xxii manufacturers documents A 2 map decode PPC 2 14 mast
135. Register Offset XMPI 01020 Name GLBC Misc 38 Operation R R R c 3 3 e4 a a ed Reset dddddddda 00 00 00 The Global Configuration Register GLBC contains global MPIC control information The fields within the GLBC register are defined as follows RESET Reset Controller Writing a one to this bit forces the controller logic to be reset This bit is cleared automatically when the reset sequence is complete While this bit is set the values of all other register are undefined M Cascade Mode Allows cascading of an external 8259 pair connected to the first interrupt source input pin 0 In the pass through mode interrupt source 0 is passed directly through to the processor 0 INT pin The MPIC is essentially disabled In the mixed mode 8259 interrupts are delivered using the priority and distribution mechanism of the MPIC The Vector Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources Table 3 36 Cascade Mode Encoding M MODE 0 Pass Through 1 Mixed TIE Tie Mode Writing a one to this register bit will cause a tie in external interrupt processing to swap back and forth between processor 0 and 1 The first tie in external interrupt processing always http www motorola com computer literature 3 115 Programming Model goes to Processor 0 after a reset When this register bit is set t
136. Register MGOD is used for receiving outbound doorbell interrupts from the processor to PCI A PCI master reads this register to determine which doorbell bit was used to generate the outbound doorbell interrupt This register is visible from within the XCSR Register Group allowing the processor to write any 3 106 Computer Group Literature Center Web Site Message Passing doorbell bit which will then generate a PCI interrupt if the MGODM register permits The interrupts generated by this register may be cleared by writing to the appropriate fields within this register The fields within the MGOD register are defined as follows ODBIx Outbound Doorbell Interrupt If any one of these bits are set from the XCSR Register Group a PCI interrupt will be generated Writing a one to a particular bit position will clear the bit and remove the interrupt associated with the bit MP Generic Inbound Message 0 and 1 Registers Offset MGIMO PMEP 110 MGIM1 PMEP 114 Function Generic BYTE3 BYTE2 BYTEI BYTEO Operation R W R W R W R W Reset The MP Generic Inbound Message Registers MGIMO and MGIM1 are used for generating inbound messages from PCI to the processor Writing to either MGIMO or MGIM1 will cause the generation of a processor interrupt if the XCSR FEMA register permits These registers are visible from within the XCSR Register Group allowing the processor to receive the inbound message being passed from PCI
137. Registers 1 cei podria ddl Db d RR HR RUD ai 3 49 Passive Slave Offset Translation Attribute Registers 3 50 bibo c cgi eec 3 52 CONFIG ADDRESS RESIBIES in pipi EpRP ERR FIRE EPA pRN inania naai 3 52 CONFIG DATA Repe aerea rin b i pa MIR PHI IM PEE 3 54 xv do c cg tior PETER 3 55 Vendor I Device IO Registers 3 55 Command Stats ICD T oy neosasani iaaa TERN 3 56 Revision ID Clazs Code Reeser uu esescerissier E Poerr Ust ci Setia rena ur E RR 3 58 Cache Line Size Master Latency Timer Header Type Register 3 59 Message Passing Register Group Base Address Register 3 61 Inbound Translation Base Address 0 1 2 and 3 Registers 3 62 Subsystem Vendor ID Subsystem ID Registers cesse 3 65 Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Registers3 66 Message Passing Attribut Registe acronimo 3 68 Inbound Translation Size Offset 0 1 2 and 3 Registers 3 69 Inbound Translation Attribute 0 1 2 and 3 Registers 3 71 PCI Status Reger RP 3 75 PCI General Puonpose Ts SE oeiiuorcarnadancd ie ia pomo pen m ceOR Enna 3 76 oEX amp 5 M 3 78 DMA Contool ar o I 3 78 UI FS i NIC oc NENNT EP PUE 3 81 DMA Source Address Repisteg uie eene eir o uaa Riana ERI e dE IE eR 3 83 DMA Somece nici
138. SDRAM controller does not write the data for that access Depending upon when the retry occurs the controller may cycle the SDRAM but it will not transfer data http www motorola com computer literature 2 5 Functional Descriptions SDRAM Controller SDRAM Organization SDRAM is organized as 1 2 3 4 5 6 7 or 8 banks 72 bits wide with 64 of the bits being normal data and the other 8 being checkbits The 72 bits of SDRAM for each bank can be made up of x4 x8 or x16 components or of 72 bit DIMMs that are made up of x4 or x8 components 72 bit unbuffered DIMMs can be used as long as AC timing is met and they use the components listed All components must be organized with 4 internal banks SDRAM Accesses Four beat Reads Writes Because of the burst nature of SDRAM the SDRAM interface performs best when responding to PowerPC burst four beat accesses When a PowerPC master begins a burst read to SDRAM the SDRAM controller begins an access When the access time is reached the SDRAM provides all four beats of data one on each clock Consequently the PowerPC slave can provide the four beats of data with zero idle clocks between each beat When a PowerPC master begins a burst write to SDRAM as soon as the PowerPC data transfer begins the PowerPC slave latches and acknowledges the PowerPC data so that the PowerPC master is freed to continue with new accesses The SDRAM controller then performs an SDRAM access to write the l
139. SR GCSR PUST2 Generic Power Up Status XAD 21 XCSR GCSR PUST1 Generic Power Up Status XAD 20 XCSR GCSR PUSTO See Global Control and Status Register in next Chapter 3 1 0 IOP Agent XAD 19 1 o oi o c 2 134 Computer Group Literature Center Web Site Hardware Configuration Table 2 24 Harrier Hardware Configuration Continued Function Sample Sampled Description Timing Pin s State Group Internal PCI Arbiter XAD 18 0 Disabled 1 1 Enabled Internal PowerPC Arbiter XAD 17 0 Disabled 1 1 Enabled XCSR Register Group Base XAD 16 1 00 Base Address 1 Address 5 FEFF0000 01 Base Address FEFF1000 10 Base Address FEFF2000 11 Base Address FEFF3000 PowerPC PCI Clock Ratio XAD 14 1 000 Reserved 1 2 100 fia 010 2 1 110 3 1 001 3 2 101 Reserved 011 5 2 111 Reserved Xport Channel 0 Data XAD 11 1 00 8 Bit Width 1 Width XCSR XPATO DW 0 01 16 Bit Width 10 32 Bit Width 11 16 Bit Width Hawk compatibility mode Xport Channel 0 as Reset XAD 9 0 Disabled 1 Vector Source 1 Enabled Only if Channels 1 3 are Disabled http www motorola com computer literature 2 135 Functional Descriptions Table 2 24 Harrier Hardware Configuration Continued Function Sample Sampled Description Timing Pin s State Group Xport Channel 1 Data XAD 8 7 00 8 Bit Width 1 Widt
140. Single bit Error Status on page 3 33 describes how the error logging control and status bits operate Harrier can be programmed to generate interrupts machine checks when it logs SDRAM errors See the section titled Exceptions on page 3 164 for more details The Harrier performs refresh by doing a burst of 4 CBR refresh cycles to all SDRAM banks once every 4 Row Refresh Interval Refer to the section titled SDRAM General Control Register on page 3 25 for more information Once every so many refresh bursts Harrier replaces the refresh burst with a scrub cycle The scrub cycle involves an 8 byte read followed conditionally by an 8 byte write The 8 byte write occurs only if the read detects a single bit error and GCSR SDSC SCWE is set Otherwise the 8 byte write does not occur GCSR SDSC SCPA controls the frequency with which refresh bursts are replaced with scrubs Refer to the section titled SDRAM Scrub Control Register on page 3 32 for additional information If so enabled Harrier logs single and or double bit errors Logged scrub errors can be enabled as error exceptions Refer to the section titled Error Exception Enable Register on page 3 170 for more information Computer Group Literature Center Web Site PowerPC to PCI Bridge PowerPC to PCI Bridge The PowerPC to PCI Bridge contains the data paths and control logic that allows multiple PowerPC processors to interface with a 32 64 bit PCI Local Bus Data Flow Terminolo
141. Site Error Diagnostics SMS SDRAM Memory Controller Multi Bit Error on Scrub If set a machine check will be generated to processor 1 whenever the EEST SMS bit is asserted If cleared a machine check will not be generated to processor 1 XBT PowerPC Bus Time out If set a machine check will be generated to processor 1 whenever the EEST XBT bit is asserted If cleared a machine check will not be generated to processor 1 XAP PowerPC Bus Address Parity Error If set a machine check will be generated to processor 1 whenever the EEST X AP bit is asserted If cleared a machine check will not be generated to processor 1 XDP PowerPC Bus Data Parity Error If set a machine check will be generated to processor whenever the EEST XDP bit is asserted If cleared a machine check will not be generated to processor 1 XDT PowerPC Bus Delayed Transaction Time out If set a machine check will be generated to processor 1 whenever the EEST XDT bit is asserted If cleared a machine check will not be generated to processor 1 Note PowerPC Bus delayed transaction time outs can occur during normal operation The XDT bit should NOT be set Error Diagnostics All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group http www motorola com computer literature 3 187 Programming Model Error Diagnostics Error Injection Register Offset XCSR 06c Bit Function
142. Site PowerPC to PCI Bridge PCFS Register Group This register group represents the Harrier s PCI Configuration Space A reflection of this Configuration Space is represented within the XCSR Register Group Note that in many cases a register represented within the PCFS Register Group will have different read write characteristics than the same register represented within the XCSR Register Group In general the read write characteristics of the registers within the XCSR Register Group are quite liberal while those of the PCFS Register Group are strictly limited to the abilities defined by the PCI Local Bus Specification The reflected configuration space in the XCSR Register Group is byte swapped as described in the section titled Endian Conversation in the previous chapter Except where noted all bit definitions are discussed with respect to the register within the PCFS Register Group Vendor ID Device ID Registers Perspective from the PCI Bus Offset PCFS 00 Bit Function Name Header Operation Reset Offset Bit Function Name Reflected Operation PCI Configurati Reset 5710 0B48 on Space http www motorola com computer literature 3 55 Programming Model The Vendor ID Register VENIT is a read only register that identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola and is hardwired as a read only
143. Status FEEEEEEE o I peration z EE mem ELE R R Reset doddxddada ddd 00 00 The Miscellaneous Control Status Register MCSR provides miscellaneous control and status information for the Harrier The fields within the MCSR are defined as follows BRDFLS Board Fail Status This bit is the board fail status bit It is high when the Harrier s board fail BRDFL_ pin is asserted The board fail pin is open drain and may be driven low by the Harrier or external logic BRDFL Board Fail This bit is the board fail bit When the board fail bit is asserted the Harrier will assert its board fail BRDFL_ pin ERDYS PCI Bus Enumeration Ready Status This bit is the EREADY status bit It is high when the Harrier EREADY pin is high and low when the Harrier EREADY pin is low The EREADY pin is open drain and may be driven low by the Harrier or external logic EREADY PCI Bus Enumeration Ready This bit is the EREADY bit When the EREADY bit is low the Harrier will drive its EREADY pin low with an open drain driver When the EREADY bit is high the Harrier will not drive the EREADY pin SCON System Controller This bit is high when the Harrier SCON_ pin is asserted When this bit is high the Harrier is the system controller http www motorola com computer literature 3 199 Programming Model TBENO Time Base Enable 0 When set the Harrier will assert its TBENO pin TBENI Time Base Enable 1 W
144. TL1 RFTLO Receiver FIFO Trigger Level 1 byte 4 bytes 8 bytes 16 bytes O Oj DMAS DMA Mode Select This bit determines the DMA mode in which the TXRDYx_ and RXRDYx pins support When this bit is cleared the device operates in DMA Mode 0 When this bit is set the device operates in DMA mode 1 This bit has no effect unless the FIFOEN bit is set as well TFR Transmitter FIFO Reset Writing a 1 to this bit clears all the bytes in the Transmitter FIFO and resets its counter logic to 0 This bit is self clearing RFR Receiver FIFO Reset Writing a 1 to this bit clears all the bytes in the Receiver FIFO and resets its counter logic to 0 This bit is self clearing FIFOEN FIFO Enable Writing a 1 to this bit enables both the Transmitter and Receiver FIFOs This bit must be a 1 when other bits in this register are written to or they will not be programmed The Line Control Register LCTLx controls the format of the data that is transmitted and received by the UART It also contains a bit that controls the data loaded into the Divisor Latch High Low Registers The fields within the LCTLx register are defined as follows 3 140 Computer Group Literature Center Web Site UART Controller DLAB Divisor Latch Access Bit This bit must be set to logic 1 to access the Divisor Latches of the baud rate generator during a read or write operation It must be set to logic 0 to access the Receiver Buffer t
145. Table 3 14 Table 3 15 Table 3 16 Table 3 17 Table 3 18 Table 3 19 Table 3 20 Table 3 21 Table 3 22 Table 3 23 Table 3 24 Table 3 25 Table 3 26 Table 3 27 Table 3 28 Table 3 29 Table 3 30 Table 3 31 Table 3 32 Table 3 33 Table 3 34 Table 3 35 Table 3 36 Table 3 37 Table 3 38 Table 3 39 Table 3 40 Table 3 41 Table 3 42 Table 3 43 Table 3 44 Table 3 45 Table 3 46 Table 3 47 Table 3 48 SUTO TR A EM UI rE 3 28 BDIC TDPL EROS os RDUM DE MN RP DM IM ME 3 29 bled du zio o PT 3 29 SOTO Urb c e 3 29 SUBA SZET RODI 3 31 SDSES ESB Encoding iuueesiziviatateb EE rrr Edo Pa R EUR LiP DIAM ANS OM ike Pdl idu d dU 3 34 Syndrome Code Ordered by Bit in Bart csecsscssscccccscecssoeaspenssoacoesaszsens 3 35 BECS PINL EDU acannon 3 40 BXLS RET pieces eins nuu n MED Ud 3 42 BACS SBT EUCODDE aieuiniestibutapuiada hnc HMM M NNNM Ea 3 42 OTATIX RAS BANGOR iesscninstei tp iep bU AT 3 46 BASE Encoding and Resource SIE uiuos ien tip tiae a taa cU ut pi Ra 3 49 iv uds iei irc AMET Ur UP CINNROTPRUN 3 51 AP Saco M at 3 59 BASE Encoding and DOXonfob ONUS inthis denim rebus d inde 3 64 RO Be aii edes hmi KI Mm onan 3 67 DER y Non ld qe 3 70 E EE MER d eio cosiu o Mem 3 73 Harrier Generated Transiter Typs ccce 3 75 D uM Wil co pessian eenaa 3 79 DCTE ulgMic i P 3 80 LAT TIPEBR DUE 2ip
146. Type Memory Contiguous I O Spread I O If the MEM bit is set the Harrier performs Memory addressing on PCI The Harrier takes the PowerPC address applies the offset specified in the OTOFYx register and maps the result directly to the PCI bus The IBM CHRP specification describes two approaches for handling PCI I O addressing contiguous or spread address modes When the MEM bit is cleared the IOM bit is used to select between these two modes whenever a PCI I O cycle is performed The Harrier performs contiguous I O addressing when the MEM bit is clear and the IOM bit is clear The Harrier takes the PowerPC address applies the offset specified in the OTOFYx register and maps the result directly to the PCI bus http www motorola com computer literature 2 37 Functional Descriptions 2 38 The Harrier performs spread I O addressing when the MEM bit is clear and the IOM bit is set It takes the PowerPC address applies the offset specified in the OTOFx register and maps the result to the PCI bus as shown in the figure below PowerPC Address Offset 1211 54 0 0000000 PCI Address Figure 2 10 Spread I O Address Translation Spread I O addressing allows each PCI device s I O registers to reside on a different PowerPC memory page so device drivers can be protected from each other using memory page protection All I O accesses must be performed within natural word boundaries Any I O acces
147. Watchdog Timers Watchdog Timers All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group Watchdog Timer Control Registers Offset WTOC XCSR 080 WTIC XCSR 088 Bit 4 44444 4424343234253284848358593585 Function WTxC Watchdog Name Timers KEY 2 amp RES RLD Operation p w 3 ci R W R W Reset 00 EM yc FFFF The Watchdog Timer Control Registers WTOC and WTI1C are used to provide control information to the watchdog timer functions within the Harrier The fields within WTXxC registers are defined as follows KEY Key This field is used during the two step arming process of the Control register This field is sensitive to the following data patterns PATTERN 1 55 PATTERN 2 2 AA The Control register will be in the armed state if PATTERN 1 is written to the KEY field The Control register will be changed if in the armed state and PATTERN 2 is written to the KEY field An incorrect sequence of patterns will cause the Control register to be in the unarmed state A value of all zeros will always be returned within the KEY field during read cycles http www motorola com computer literature 3 161 Programming Model ENA Enable This field determines whether or not the WDT is enabled If a one is written to this bit the timer will be enabled A zero written to this bit will
148. acknowledged only one IPI will be generated The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC 8259 Compatibility The MPIC provides a mechanism to support PC AT compatible chip sets using the 8259 interrupt controller architecture After power on reset the MPIC defaults to 8259 pass through mode In this mode if the MCSR OPI bit is set interrupts from external source number 0 the interrupt signal from the 8259 is connected to this external interrupt source on the MPIC are inverted and passed directly to processor 0 IRQO If the pass through mode is disabled and the MCSR OPI bit is set the 8259 interrupts are delivered using the priority and distribution mechanisms of the MPIC MPIC does not interact with the vector fetch from the 8259 interrupt controller Harrier Internal Functional Interrupt Functional exceptions generated by the Harrier internal modules DMA message unit abort switch and UARTs are grouped together and sent to the MPIC interrupt logic as a singular interrupt source the Harrier Internal Functional Interrupt Please see the section titled Exceptions on page 2 122 for more information about the Harrier s functional exceptions This Harrier internal functional interrupt request is an active low level sensitive interrupt The interrupt delivery mode for this interrupt is dis
149. agent This will generate an interrupt to the receiving agent a The receiving agent recognizes the post MFA and processes the new Message Frame Once complete the receiving agent allocates the MFA as free IOP Message Unit The Harrier can participate in the I O protocol as either a Host or an IOP Participation as a Host requires no additional hardware Participation as an IOP requires an IOP Message Unit IMU The Harrier provides an IMU that is fully compatible with the IpO specification The Harrier shows the key elements of the IMU from the system perspective The FIFOs for the inbound and outbound queues and the Message Frames physically reside within local memory The Harrier implements all of the pointer registers the inbound and outbound queue ports and the interrupt structure in hardware The inbound queue is accessed from PCI through the Message Passing I 0 Inbound Queue MIIQ register The outbound queue is accessed from PCI through the Message Passing I O Outbound Queue MIOQ register The MIIQ and MIOQ registers reside within a relocatable 4K byte block of PCI Memory space called the PMEP PCI Message Passing Register Group This block is located into PCI memory space using the MPBAR register within the PCFS PCI Configuration Space Register Group All of these components are fully compliant with the IO specification Please refer to the section titled PowerPC to PCI Bridge on page 3 38 for more information http ww
150. al I O interrupts a Direct Multicast interrupt delivery for Interprocessor and timer interrupts Four Interprocessor Interrupt sources a Four timers a Processor initialization control Architecture 2 68 The Harrier implements an address decoder for placing the MPIC registers in PowerPC address space Access to these registers require PowerPC bus mastership These accesses include interrupt and timer initialization and interrupt vector reads The MPIC is run from PowerPC clock The MPIC receives interrupt inputs from 16 external sources four interprocessor sources four timer sources and two Harrier internal source interrupts the Harrier internal functional exception and the Harrier internal error exception The externally sourced interrupts 1 through 15 Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC have two modes of activation low level or active high positive edge External interrupt 0 can be either level or edge activated with either polarity The Harrier internal interrupt requests are active low level sensitive interrupts The Interprocessor and timer interrupts are event activated When the MPIC is in the 8259 pass through mode and if the XCSR MCSR OPI bit is set interrupts from external source number 0 are inverted and passed directly to processor 0 interrupt pin IRQO When the MPIC is out of 8259 pass through mode and if the XCSR MCSR OPI bit is set the Harrier
151. and is received This register should always be written with a value of zero which is the nonspecific EOI command Interrupt Acknowledge Register Upon receipt of an interrupt signal the processor may read this register to retrieve the vector of the interrupt source which caused the interrupt 8259 Mode The 8259 mode bits control the use of an external 8259 pair for PC AT compatibility Following reset this mode is set for pass through which essentially disables the advanced controller and passes an 8259 input on external interrupt source 0 directly through to processor zero interrupt pin IRQO During interrupt controller initialization this channel should be programmed for mixed mode in order to take advantage of the interrupt delivery modes Current Task Priority Level Each processor has a separate Current Task Priority Level register The system software uses this register to indicate the relative priority ofthe task running on the corresponding processor The interrupt controller will not deliver an interrupt to a processor unless it has a priority level which is greater than the current task priority level of that processor This value is also used in determining the destination for interrupts which are delivered using the distributed delivery mode http www motorola com computer literature 2 81 2 Functional Descriptions I C Interface Byte Write 2 82 The Inter Integrated Circuit DC interface provides 2 two wir
152. are don t cares when operated in this mode Round Robin mode is the default priority scheme on power up When the PCI Arbiter is programmed for mixed mode the 8 requestors are separated into 4 groups Each group has 2 requestors PARB6 and PARB5 are defined in group 1 PARB4 and PARB3 are defined in group 2 PARB2 and PARBI are defined in group 3 PARBO and HARR are defined in group 4 Arbitration is set for round robin mode between the 2 requestors within each group and set for fixed mode between the 4 groups The levels of priority for each group is programmable by writing the HEIR field in the PARB register Table 2 19 on page 2 117 describes all available settings for the HEIR field in mixed mode 2 116 Computer Group Literature Center Web Site Arbiters Table 2 18 HEIR Encoding for Fixed Mode Priority HEIR Priority Levels Highest Lowest 000 PARB6 PARB5 PARB4 PARB3 PARB2 PARBI PARBO HARR 001 HARR PARB6 PARBS PARBA PARB3 PARB2 PARBI PARBO 010 PARBO HARR PARB6 PARBS PARB4 PARB3 PARB2 PARBI 011 PARBI PARBO HARR PARB6 PARBS PARB4 PARB3 PARB2 100 PARB2 PARBI PARBO HARR PARB6 PARBS PARB4 PARB3 101 PARB3 PARB2 PARBI PARBO HARR PARB6 PARBS PARB4 110 PARB4 PARB3 PARB2 PARBI PARBO HARR PARB6 PARB5 111 PARBS PARBA PARB3 PARB2 PARBI PARBO HARR PARB6 Notes 1 000 is th
153. are must program this register when performing Direct Mode transactions When performing Linked List Mode transactions this register is automatically loaded from the destination attribute field of the current descriptor The fields within the DDAT register are defined as followed http www motorola com computer literature 3 87 Programming Model TYP Type This field indicates the type of destination to be used for a DMA transfer Different fields within the DDAT register are used depending on the type of destination selected The table below shows the different destination types and the associated fields within the DDAT register that apply Table 3 33 DDAT TYP Encoding DMA Applicable Fields Destination NIN CWF GBL PowerPC bus X X PCI Bus X NIN No Increment If set destination increment will be disabled during a DMA transfer If a PCI bus destination is selected then the destination address will not be incremented If cleared the destination will be incremented PWC PCI Write Command This field represents the command used during PCI write cycles Note that this field is only applicable if the TYP field represents a PCI bus DMA destination The encoding of this field matches that described within Section 3 1 1 Command Definition ofthe PCI Local Bus Specification The table below shows the recommended values for PWC Table 3 34 DDAT PWC Encoding PRC PCI Command 0011 IO W
154. are shared by both processors That is there is a total of four IPI dispatch registers in the MPIC The IPI mechanism may be used for self interrupts by programming the dispatch register with the bit mask for the originating processor Dynamically Changing I O Interrupt Configuration 2 80 The interrupt controller provides a mechanism for safely changing the vector priority or destination of I O interrupt sources This is provided to support systems which allow dynamic configuration of I O devices In order to change the vector priority or destination of an active interrupt source the following sequence should be performed a Mask the source using the MASK bit in the vector priority register a Wait for the activity bit ACT for that source to be cleared a Make the desired changes a Unmask the source This sequence ensures that the vector priority destination and mask information remain valid until all processing of pending interrupts is complete Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event If multiple nested interrupts are in service the EOI command terminates the interrupt service of the highest priority source Once an interrupt is acknowledged only sources of higher priority will be allowed to interrupt the processor until the EOI comm
155. at have been written If all of the addresses still contain exactly what was written then the bank s size has been found It is the size for which it is currently programmed If any of the addresses do not contain exactly what was written then the bank s memory size is less than that for which it is programmed Sizing needs to continue for this bank by programming its control bits to the next smaller size and repeating steps d and e http www motorola com computer literature 5 11 Programming Considerations f If no match is found for any size then the bank is unpopulated and has a size of OMB Its size should be programmed to 0 5 12 Computer Group Literature Center Web Site Operation without Firmware Operation without Firmware The Harrier includes features that allow a host processor on the PCI bus to initialize it load the operating code into SDRAM and start the local processor without on board firmware For example a Processor PCI Mezzanine Card PPMC can be designed to operate without on board firmware when it is used in an application where their is a host processor on the PCI bus In this application the PPMC would be installed on a host board and the processor on the host board would initialize the PPMC download the operating code and start the local processor When this mode is used the processor is held in reset HRESET is asserted after the board reset signal is negated Harrier s RST_ signal This is accompl
156. ata within the collection in 32 bit mode The PCI Master can support Critical Word First CWF burst transfers The PCI Master divides this transaction into two parts The first part starts on the address presented with the CWF transfer request and continues up to the end of the current cache line The second transfer starts at the beginning of the associated cache line and works its way up to but not including the dword addressed by the CWF request Even though the PCI Master can support burst transactions a majority of the transaction types handled are single beat transfers Typically PCI space is not configured as cache able therefore burst transactions to PCI space would not naturally occur It must be supported since it is conceivable that bursting could happen For example nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line Store Gathering The data transfer rate of outbound traffic is inherently slow due to the inability of the processor to perform anything but single beat bus cycles when moving data The Harrier has an optional Store Gathering mode that 2 20 Computer Group Literature Center Web Site PowerPC to PCI Bridge condenses multiple contiguous single beat outbound transactions into large PCI burst transactions This option may be individually enabled for each Outbound Translation Function from within the OTATYX register The PPC Slave only attempts to p
157. atched data Single beat Reads Writes Because of start up addressing and completion overhead single beat accesses to and from the PowerPC bus do not achieve data rates as high as do four beat accesses Single beat writes are the slowest because they require that the controller perform a read followed by a write to the SDRAM in order to complete Single beat accesses can be held to a minimum by using the data cache in copyback mode Computer Group Literature Center Web Site SDRAM ECC SDRAM Interface Address Pipelining The SDRAM interface takes advantage of the fact that PowerPC processors can do address pipelining Many times while a data transfer is finishing the PowerPC master begins a new address transfer The SDRAM controller can begin the next SDRAM access earlier when this happens thus increasing throughput Holding Open Pages Further savings come when the new address is close enough to a previous one that it falls within an open page in the SDRAM array When this happens the controller can transfer the data for the next cycle without having to wait to activate a new page in SDRAM SDRAM Speeds and PowerPC Access Times The SDRAM that the Harrier controls uses the PowerPC clock The SDRAM interface accommodates operation at several different PowerPC clock frequencies using SDRAMs that have various speed characteristics Refer to the section titled SDRAM Timing Control Register on page 3 27 for related programming info
158. ation cycles is supported by the Harrier using Configuration Mechanism 1 as specified in PCI Local Bus Specification 2 1 This mechanism is tied to the Outbound Translation Function 3 This translation function only offers PCI I O space to PowerPC address space mapping The CONFIG ADDRESS and CONFIG DATA registers are located within this translation space at the first occurrence i e closest to the base address of the 0CF8 and 0CFC offsets The following table shows the location of the CONFIG ADDRESS and CONFIG_DATA registers with respect to the PowerPC bus Note that since these registers are considered PCI resources Endian conversion rules are applicable This table represents these registers in Big Endian mode http www motorola com computer literature 3 19 Programming Model Table 3 4 PowerPC to PCI Configuration Space XCFS Register Group Function Offset Bits PowerPC PCI I O 0000 to PCI Space Em Bridge 0CFA Config 0CF8 CONFIG ADDRESS Mechanis 0CFC CONFIG DATA m PCI I O 0D00 Space ele FFFF 3 20 Computer Group Literature Center Web Site Register Group Summary PCI Configuration Space PCFS Register Group The PCI Configuration Space PCFS Register Group is a PCI compliant single function configuration register group This 256 byte block contains various control and status registers specific to the Harrier including base address registers for the Inbound Trans
159. atus Register Offset XCSR 204 Bit Function Name Control and Status Operation Reset The Bridge PowerPC Control and Status Register BXCS provides control and status information associated with PowerPC functions The fields within the BXCS are defined as follows IFBR Inbound Flush Before Read If set the Harrier guarantees that all inbound write posted transactions are completed before any outbound read transactions are allowed to complete If cleared there is no correlation between these transaction types and their order of completion Please refer to the section titled Transaction Ordering in the previous chapter for more information BHG Bus Hog If set the Harrier operates in Bus Hog mode Bus Hog mode means the Harrier continually requests the PowerPC bus for the entire duration of each transfer If cleared the Harrier requests the bus in anormal manner Please refer to the section titled PPC Master in the previous chapter for more information RSF Read Ahead Sync Flush If set a read ahead session is closed and the FIFO cleared if the Harrier detects a Sync cycle from the processor responsible for originating the read ahead If cleared the read ahead session remains open when a Sync is detected http www motorola com computer literature 3 41 Programming Model 3 42 SSF Store Gather Sync Flush If set a Store Gather collection is flushed if the Harrier
160. bility to perform byte write page write current address read random read and sequential read operations The I2STx Register contains the CMP bit which is used to indicate if the C master controller is ready to perform an operation Therefore the first step in the programming sequence should be to test the CMP bit for the operation complete status The next step is to initiate a start sequence by first setting the STA and ENA bits in the I2COx Register and then writing Computer Group Literature Center Web Site I2C Interface the device address bits 24 30 and write bit bit 3120 to the IZTDx Register The CMP bit will be automatically clear with the write cycle to the IZTDx Register The I2STx Register must now be polled to test the CMP and ACKI bits The CMP bit becomes set when the device address and write bit have been transmitted and the ACKI bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the word address will be loaded into the IZTDx Register to be transmitted to the slave device Again CMP and ACKI bits must be tested for proper response After the word address is successfully transmitted the next data loaded into the I2TDx Register will be transferred to the address location selected previously within the slave device After CMP and ACKI bits have been tested for proper response a stop sequence must be transmitted to the slave device
161. bit may be cleared by a PCI master by reading the MIOQ register until there are no more new entries within the Outbound Post list FIFO MP 150 Interrupt Mask Register Offset PMEP 034 Bit Reset The MP LO Interrupt Mask Register MIMS controls the masking of interrupts associated with the Outbound Post list circular queue The field within the MIMS register is defined as follows OPIM Outbound Post list Interrupt Mask If set the OPI bit within the MIST register will not generate a PCI interrupt If cleared a PCI interrupt will be generated whenever the OPI bit is set MP 150 Inbound Queue Register Offset PMEP 4 040 fame CEG GEGCEGEGGEGEE T DD Name MIIQ LO Operation R W Reset FFFFFFFF The MP DO Inbound Queue Register MIIQ is an access port to the Inbound Free_list and Post_list FIFOs 3 104 Computer Group Literature Center Web Site Message Passing Reading this register will return the oldest MFA entry from the Inbound Free list FIFO If there are no entries in the FIFO or the IO Message Passing function is disabled then this register will return OXFFFF FFFF Writing this register will place the newest MFA entry into the Inbound Post list FIFO If the IO Message Passing function is disabled then the write will be discarded MP 150 Outbound Queue Register Offset PMEP 044 Bit Name Operation Reset FFFFFFFF The MP I 0 Outbound Queue Register MIOQ i
162. bit tells software that the push button reset signal was asserted when the Harrier received an RST_ signal This bit is cleared by power up reset ARST Auxiliary Reset This bit tells software that the auxiliary reset signal was asserted when the Harrier received an RST_ signal This bit is cleared by power up reset PRST Program Reset This bit tells software that the software reset out bit was asserted when the Harrier received an RST_ signal This bit is cleared by power up reset PUSTx Power up Status PUSTx indicates the levels that were on four certain input signal pins during power up reset This field provides a means to pass information to software using pull up pull down resistors on the four inputs Refer to Table 2 24 on page 2 133 for more information Computer Group Literature Center Web Site Miscellaneous Functions AOAO Address Only Acknowledge Other When cleared the Harrier responds to PowerPC address only transactions only if they address one of its own resources When set the Harrier also responds to address only transactions to non Harrier addresses provided no other slave responds within 8 CLK periods AOAO reflects the value on a certain input signal at power up reset Refer to Table 2 24 on page 2 133 for more information XBS PowerPC Burst Size This field specifies the latching request burst size that is used by all the Harrier PowerPC bus masters When performing multiple burst transfers a master wi
163. ble 3 30 WISZC RES Bie ita iu tmd a a 3 162 Table 297 UOR ABS osos REPE 3 195 Table 3 58 GCSR BTO En odiNg AM 3 196 Table 3 39 SA MID EI P oen rieren ENEE aaraa 3 196 Table 00 OCSR RAT Encoding senpene iranere RAM PIRE aaa andana 3 197 Table 4 1 PowerPC 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PEDD DRAN eee 4 1 Table 4 2 PowerPC 60x Bus Performance for Xport Bus Bound Cycles 4 5 Table 4 3 Number of Xport Data Beats for Different PowerPC 60x Hia o c n7ooeee 4 7 Table 4 4 Outbound Performance Matrix Liuius kie inks inb d bana baa Rh Ra eI td ER e EI eroe eR tO 4 8 Table 5 1 Deriving TRAS TRP TRCD and TRC Control Bit Values i Rl Uem O A 5 5 Table 5 2 Programming the SDRAM SIZ Sits ssssscssscisccsasasaacscosdsdoiedsissaisiaiaiedaiadeians 5 7 Table 5 3 Programming the SDRAM Refresh Period eese 5 8 Table 5 4 Address Lists for Different Bank Size Checks ues 5 10 Table A 1 Motorola Computer Group Documents Liuius epi intererit rto tt htt A 1 Table A 2 Manulactuters DOCUMEDIS sss sssesssssssosssasscasesscciastdecssiepusdteniaiauasiaiaaasaoad A 2 Table A 3 Related Specifications ssiscccnssnsscsnancninwanoonssentoensenoterauntonsemartatnvaacnabeaniennts A 4 xix XX About This Manual The Harrier ASIC Programmer s Reference Guide provides chip level
164. by DIN 1 in the I2STx Register the system software may then read the data by polling the IZRDx Register The C master controller does not acknowledge the read data for a single byte transmission on the PC bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the STP and ENA bits in the I2COx Register and then writing a dummy data data don t care to the IZTDx Register The I2STx Register must now be polled to test CMP bit for the operation complete status The stop sequence will relinquish the Harrier s master possession of the I C bus The following figure shows the suggested software flow diagram for programming the C random read operation http www motorola com computer literature 2 85 Functional Descriptions DEVICE ADDR WORD ADDR DEVICE ADDR M w SDA START S R BL ACK and DATA from Slave Device LOAD 09 START CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR WR BIT TO i I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C STATUS REG LOAD DUMMY DATA TO LOAD WORD ADDR TO I2C TRANSMITTER DATA REG I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C RECEIVER DATA REG LOAD 09 REPEATED START CONDITION TO I2C CONTROL REG LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR RD BIT TO I2C TRANSMITTER DATA REG LOAD DU
165. by writing a one to the FECL MIM1 bit MIP Message Passing Inbound Post list This read only field indicates a message has been written by a PCI master to the Inbound Post list fifo If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt by continuously reading the Post list fifo i e look at the fifo contents and maintain the fifo pointers until all entries have been read UAO0 UART 0 This field will be set whenever UART 0 is requesting service If the FEMA register permits a processor interrupt will be generated UAI UART 1 This field will be set whenever UART 1 is requesting service If the FEMA register permits a processor interrupt will be generated ABT Abort This field will be set whenever the Harrier s ABTSW pin has been asserted for a short period at least 30 ms If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt by writing a one to the FECL ABT http www motorola com computer literature 3 167 Programming Model Functional Exception Mask Register Offset XCSR 048 Bit 444444444343334343284448453 89444 Function Name FEMA Exceptions Operation Reset 3 168 The Functional Exception Mask Register FEMA provi
166. ce A detailed description of each reflected configuration space register within the XCSR Register Group may be found within the description of the PCFS Register Group The Harrier s PowerPC Control and Status Register Group is shown in the following table http www motorola com computer literature 3 3 Programming Model Table 3 2 PowerPC Control and Status XCSH Register Group Function Offset Bits 0 7 8 15 16 23 24 31 Misc IDs 000 VENI DEVI 004 REVI 008 00C Control 010 GCSR n 014 XCFR tatus 018 CT32 01C MCSR General 020 GPRGO Purpose 024 GPRGI Registers sog GPRG2 02C GPRG3 030 GPRG4 034 GPRG5 038 03C Exceptions 040 FEEN 044 FEST 048 FEMA 04C FECL 050 EEEN 054 EEST 058 EECL 05C EEINT 060 EEMCKO 064 EEMCKI 3 4 Computer Group Literature Center Web Site Function Register Group Continued Offset Bits Register Group Summary Table 3 2 PowerPC Control and Status XCSR 15 16 23 24 3l Error Diagnostics 068 06C EDEI 070 EXAD 074 EXAT 078 EPAD 07C EPAT Watchdog Timers 080 WTOC 084 WTOS 088 WTIC 08C WTIS Arbiters 090 PARB 094 XARB 098 EfG 0BC UARTs 0CO RTDLO IEDHO IDFCO LCTLO 0C4 M
167. ception Status Register ia ioescisirioseerio edet Ubi tede dry dpud 3 166 Fonctional Exception Mask BSIBie egeatqasini etna naa i ERE P SIME IMa MEA eSERE 3 168 Functional Exception Clear Register osiscicsssdssasssnincpasececcsececctesonanssnassinnaunnatoanan 3 169 Error FE em cents Enable a LLLusruia edt o uten ninm a DU UE UM EDU M RPM DU Eu 3 170 Error Exception Statis Registe een esie la a e e pet dnd os D iniu MAE 3 173 Error ExosbO Clea Repo eoa ai ppp ee AEE GR ON REP I UM genase 3 178 Error Exception Interrupt Enable Registar sicccccccccasccsosnsssassenssonvccansesenasssasenanss 3 180 Error Exception Machine Check 0 Enable Register eee eere arorato 3 183 Error Exception Machine Check 1 Enable Register ene 3 185 in s dios o ici NENNT PN NURDN 3 187 Error Diagnostics Error Injection Register iie iisiose et btobetM Ma bitu MADRE i QM adalx 3 188 Error Diagnostics PowerPC Address RCE i assier 3 189 Error Diagnostics PowerPC Attribute Register iiccisscicsssscscissesssinsasieccisananneasn 3 190 Error Diagnostics PCI Address Register csrrreeriscionontii na ian 3 191 Error Diagnostics PCI Attribute Registet sccsisiieoitsiisisissisinainisiiairi 3 192 xiii Miscellaneous Functions ccccccccccccssssccccccecessscecccccscscscecccececssesscecesseceuseeses 3 193 bo git s ID oo co T 3 193 Revision ID Reise PI 3 193 Global Control and Status Register aca cscs ccd oniinn 3 194 PowerPC Clock Fregueney Regi
168. cess to these offsets from within the XCSR Register Group are not affected by this field If set writes to this range has no effect and reads return all zeros If cleared writes to and reads from this range occur in a normal fashion The default state of this bit is determined at the release of reset Please refer to the section titled Hardware Configuration on page 2 133 for more information CSH Configuration Space Holdoff This field controls the visibility of the Harrier s PCI configuration space The processor can use this field to hold off accesses to the Harrier s configuration space until after the inbound address and attribute fields have been established If set all attempts to access the Harrier s configuration space results in a disconnect retry The retry is always correct at the 16 clock maximum initial latency for a non host bridge device that has expired If cleared writes to and reads from the Harrier s configuration space are completed as normal The default state of this bit is determined at the release of reset Please refer to the section titled Hardware Configuration on page 2 133 for more information 3 40 Computer Group Literature Center Web Site PowerPC to PCI Bridge P64 PCI 64 bit If set the Harrier is connected to a 64 bit PCI bus Please refer to the section titled Hardware Configuration on page 2 133 for more information on how this field gets set Bridge PowerPC Control and St
169. character percent specifies a binary number amp ampersand specifies a decimal number For example 12 is the decimal number twelve and 12 is the decimal number eighteen Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition Note In some instances an underscore character _ following the signal name is used to indicate an active low signal In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes for MPC60x chips are defined as follows a A byte BYTE is eight bits numbered 0 through 7 with bit 0 being the least significant a AAalf word HWORD is 16 bits numbered 0 through 15 with bit 0 being the least significant a A word or single word WORD is 32 bits numbered 0 through 31 with bit 0 being the least significant a A double word DWORD is 64 bits numbered 0 through 63 with bit 0 b
170. cify the number of bits per character that are transmitted or received The encoding of the WLS1 0 bits is shown in the following table Table 3 41 WLS1 0 Encoding WLS1 WLSO Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Offset XCSR 0C4 XCSR 0CC Bit 44144444 j4343234434332343843 355553534 Function Name MCTLO LSTAO MSTAO UART MCTL1 LSTA1 MSTA1 SCRTO eH il A ea SCRT1 EEEEGECECEEEEEEE RES oci tr 333 a rj tr d d an ear ern d d am an end a R W Reset ad doaoedoe o ddoedddaddaddagao e XX The MODEM Control Register MCTLx controls the interface with the MODEM or a peripheral device emulating a MODEM The fields within the MCTLx register are defined as follows LOOP Loopback Mode This bit provides a local loopback feature for diagnostic testing of the UART In the loopback mode the receiver and transmitter interrupts are fully operational When this bit is set to logic 1 the following conditions occur a SOUTx is set to logic 1 state b SINx is disconnected 3 142 Computer Group Literature Center Web Site UART Controller c The output of the Transmitter Shift Register is looped back into the Receiver Shift Register input d The four MODEM control inputs DSRx CTSx RIx and DCDx are disconnected e The four MODEM control outputs DTRx RTSx OUTIUx and OUT2UX are inte
171. ck domains however there must be additional logic to make sure the phase cycle of the internal PCLK tree tracks that of the external PCI clock Shortly after the PowerPC clock starts running Harrier s internal PCLK tree starts running in a completely random but synchronous fashion with respect to the external PCI clock The Harrier then periodically samples the external PCI clock and adjusts the phase cycle of the internal PCLK tree until a match is met between the phase cycles of the external PCI clock and the internal PCLK tree In order to properly lock to the external PCI clock phase cycle the system must hold reset asserted and the PCI clock must be running while the PLL is attempting to lock to the PowerPC clock The Computer Group Literature Center Web Site Clocking PLL takes up to 100 Us to lock to the PowerPC clock If reset is asserted some time after the PLL has locked to the PowerPC clock then the system must hold reset active for a minimum of 500 PowerPC clock periods The following figure shows the synchronous relationships that must exist between the PowerPC and PCI clocks 5 2 Ratio PowerPC Clock V f FO Ye ke POlClck 7 d Tx Phase Cycle gt 3 2 Ratio PowerPC Clock V __ NV V f PCIClock VL 7 V 7S Vf Fa T 3 1 Ratio PowerPC Clock Lf A iiu on PCI Clock E Eus 2 1 Rati
172. ck associated with it may be cleared by writing a one to the EECL SSC bit SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access This bit is set when the SDRAM Memory Controller detects a multi bit error on any PowerPC access when the EEEN SMX is enabled If the EEINT SMX is set a processor interrupt will be generated If the EEMCK0 SMxX is set a machine check to processor 0 will be generated and if the EEMCK1 SMX is set a machine check http www motorola com computer literature 3 175 Programming Model 3 176 to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL SMxX bit SMS SDRAM Memory Controller Multi Bit Error on Scrub This bit is set when the SDRAM Memory Controller detects a multi bit error on a scrub when the EEEN SMS is enabled If the EEINT SMS is set a processor interrupt will be generated If the EEMCKO SMS is set a machine check to processor 0 will be generated and if the EEMCK1 SMS is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL SMS bit XBT PowerPC Bus Time out This bit is set when the PowerPC Address Bus Timer times out if the EEEN XBT is enabled and all other PowerPC error status bits are cleared If the EEINT XBT is set a processor interrupt will be generated If the EEMCKO XBT is set a machine check t
173. com VITA32 Draft 0 2 http www mcg mot com literature A 5 A Related Specifications A p A 6 Computer Group Literature Center Web Site Index Symbols _ 2 132 Numerics 60x bus relation of address ranges to Xport chip select 2 95 60x slave relation to Xport bus master 2 96 8259 compatibility 2 71 8259 mode 2 81 A INT 2 132 Access Timing DRAM 4 1 address offset Inbound Translation Function 2 28 Address Pipelining 2 7 address transfers responses to 2 5 Arbiers function described 1 5 arbiter PCI bus 2 115 arbiters internal PowerPC bus 2 113 ARTRY_ 2 5 assertion definition xxii asterisk xxii B BAR read write characteristics 2 28 BASE Bank Base Address SDRAM Addressing Registers 3 30 base address XCSR Register Group 3 3 Base Address Register BAR role in inbound translation function 2 27 binary number xxii BRDFL 2 132 bridge control logic subdivisions 2 12 inbound transactions 2 13 outbound transactions 2 12 bus cycles types 2 36 Bus Hog 2 36 bus number 2 40 BXCS register role in copyback snarfing 2 35 role with Bus Hog 2 36 byte write I2C 2 82 byte definition xxiii C cache coherency 2 5 channel Xport plus 60x bus 2 95 CL3 Cas Latency 3 SDRAM Timing Control SDTC 3 27 Register clock ratios supported 2 1 clock synchronization 2 2 xmo z Index clocking 2 1 CMP bit 2 82 compelled burst write transactions PPC Slave 2 18 CONFIG_ADDRESS 2 3
174. comes pending in MPIC processing http www motorola com computer literature 3 121 Programming Model Timer Vector Priority 0 1 2 and 3 Registers Offset nm v NEN n TIVP0 XMPI 01120 TIVP1 XMPI 01160 TIVP2 XMPI 011A0 TIVP3 XMPI 011E0 dad Function TIVPx Timers R W R W d ed A e 0 0 00 00 The Timer Vector Priority Registers TIVP0 TIVP1 TIVP2 and TIVP3 establish vectoring and priority information for timer interrupts The fields within the TIVPx registers are defined as follows 3 122 MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Priority Interrupt priority O is the lowest and 15 is the highest Note that a priority level of O will not enable interrupts VECTOR Vector This vector is returned when the Interrupt Acknowledge register is examined when the interrupt associated with this vector is acknowledged Computer Group Literature Center Web Site Multi Processor Interrupt Controller Timer Destination 0 1 2 and 3 Registers Offset TIDEO XMPI 01130 T
175. computer literature 2 111 Functional Descriptions Table 2 14 Hawk Data Compatibility Byte Lane Mapping Continued PowerPC Bus 16 bit Device Byte Byte Address Address XAD 31 24 XAD 23 16 00000008 00000008 8 00000009 00000009 9 0000000A 0000000A A 0000000B 0000000B B 0000000C 0000000C C 0000000D 0000000D D 0000000E 0000000E E 0000000F 0000000F F Table 2 15 32 bit Device Byte Lane Mapping PowerPC 32 bit Byte Byte Byte Byte Bus Device XAD 31 24 XAD 23 16 XAD 15 8 XAD 7 0 Address Address 00000000 00000000 1 2 3 00000004 00000004 5 6 7 00000008 00000008 9 A B 0000000C 0000000C D E F 2 112 Computer Group Literature Center Web Site Arbiters Arbiters The Harrier has an internal PowerPC bus arbiter The use of this arbiter is optional If the internal arbiter is disabled the Harrier must be allowed to participate in an externally implemented PowerPC arbitration mechanism The selection of either internal or external PowerPC arbitration mode is made by sampling an XAD line at the release of reset Please see the section titled Hardware Configuration on page 2 133 for more information The Harrier is designed to accommodate up to four PowerPC bus masters including itself HARR two processors CPUO CPU1 and an external PowerPC master EXTL EXTL can be a second bridge chip etc The PPC Arbiter can optionally support a thr
176. configuration as described in the section titled Hardware Configuration further on in this chapter Whenever the PURST_ signal is asserted it must be asserted for at least 50 Us The RST_ signal resets most of the Harrier s internal logic The SDRAM refresh logic is not reset by the RST_ signal This allows the contents of the SDRAM to be preserved when RST is asserted The RST_ signal must be asserted for at least 100 cycles of the CLK signal The PURST and RST_ signals may be asserted or negated in any sequence however the Harrier is not functional or does not respond to any PCI or PowerPC bus cycles until both PURST_ and RST_ are negated The hardware configuration is not changed when RST is asserted The Harrier also has a reset out signal RSTO The RSTO signal is asserted whenever the PURST_ signal is asserted the RSTSW signal is asserted and enabled AUXRST signal is asserted or the reset out bit XCSR MCSR RSTOUT is set The RSTO signal does not reset any of http www motorola com computer literature 2 131 Functional Descriptions Harrier s internal logic The RSTO signal is normally combined with other on board reset signals to generate the RST signal which is connected to the Harrier The on board reset logic must not generate any reset loops When the Harrier is used on a Processor PCI Mezzanine Card PPMC the RSTO_ signal may be connected to the RESET OUT signal on the PPMC connector The Harrier always keeps the RST
177. contained in the task register for that processor and when the priority of the interrupt is greater than any interrupt which is in service for that processor and when the priority of that interrupt is the highest of all interrupts pending for that processor and when that interrupt is not in service for the other processor If both destination bits are set for each processor the interrupt will be delivered to the processor that has a lower task register priority Note due to a deadlock condition that can occur when the task register priorities for each processor are the same and both processors are targeted for interrupt delivery the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode Additionally If priorities are set the same for competing interrupts external int 0 is given the highest priority in hardware followed by external int 1 through 15 and then followed by timer 0 through timer 3 and followed by IPI 0 and 1 For example if both extO and ext1 interrupts are pending with the same assigned priority during the following interrupt acknowledge cycles the first vector returned shall be that of ext0 and then extl This is an arbitrary choice Block Diagram Description The description of the block diagram shown in Figure 2 17 on page 2 74 focuses on the theory of operation for the interrupt delivery logic If the preceding section is a satisfactory description of the interrupt delivery modes and the rea
178. contents of Task Register 1 Q Set3 The source ID in IRR O is from an internal source The priority from IRR O is greater than the highest priority in ISR 0 The priority from IRR O is greater than the Task Register O contents http www motorola com computer literature 2 77 Functional Descriptions There is a possibility for a priority tie between the two processors when resolving external interrupts In that case the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode bit This case is not defined in the above rule set Programming Notes The following subsections discuss Programming Notes that are specific to the MPIC portion of the Harrier External Interrupt Service The following summarizes how an external interrupt is serviced a a 2 78 An external interrupt occurs The processor state is saved in the machine status save restore registers A new value is loaded into the Machine State Register MSR The External Interrupt Enable bit in the new MSR MSRee is set to zero Control is transferred to the O S external interrupt handler The external interrupt handler calculates the address of the Interrupt Acknowledge register for this processor MPIC Base Address 0x200A0 processor ID shifted left 12 bits The external interrupt handler issues an Interrupt Acknowledge request to read the interrupt vector from the MPIC If the interrupt vector indicates the i
179. cop Do pEPPODPODDOD VEI R RA 2 5 DOE obdstestiknt cited D EM pp vetta Lulu MUS Me M MEME rM MF DEDI E EDD 2 58 Hic MW rio e 2 59 Macon PURO ei inia et AARAU DUM M UEM DM MU RM DM MAE 2 60 PO Message Pas ARD M 2 60 i ii Pm TTE 2 61 MU Te Tas aso ah lL oe eer Db eb EDD tore tate er eet sere pret ater nr reer ery tiir iste rrr 2 63 i TE 2 64 INILI DlbrfOp S asiseiibbeb te T A E DM QE PDMMA MM M 2 65 TOP Agen DIG DIORBOG rie eiua id bun Dd bsp Men E E DR abbas 2 65 ienero Message Passe aao adatto udine usa iedalbda aiii 2 66 os IR Ai o c 2 66 viii Message Fassino BESIDE oid stdin Eo rt NU CUE 2 67 Multiprocessor Interrupt Controller MPIC sisasssicssssaonrcsiessccsassascssssasceanesaendaandcounss 2 68 MPE o P s 2 68 isi 00 RIC 2 68 CSR 3 corr 2 69 Totercups ee aac ieee DR RN RAND Dui enemas 2 60 Processor s Current Task Priority aue deer rro Yr pd iUe ee UNI Hiro to P PY A EAR E EE EE E pel 2 69 Nesting gt Iniernipt EYES e 2 70 Spurious Vector CSSA 2 70 nterpto essor interrupts IPI oaa A 2 70 Bel COMPA pa eL 2 71 Harrier Internal Functional ISO Lais eto torii tan atia s n dE SIRO p Ege e eet t 2 71 Hamer Intemal Error Tater pit lt cccccccccsssesssansasvcavadannssccantseniasnsannvscaiansecasenneensaas
180. croprocessor Technical Summary MPC750 D Motorola Literature Distribution Center Telephone 800 441 2447 or 303 675 2140 FAX 602 994 6430 or 303 675 2150 WebSite http e www motorola com webapp DesignCenter E mail Idcformotorola hibbertco com PowerPC750 M RISC Microprocessor User s Manual MPC750UM AD MPC7410 RISC Microprocessor User s Manual MPC7400UM AD Literature Distribution Center for Motorola Semiconductor Products Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 WebSite http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR IBM Microelectronics Programming Evnironment Manual G522 0290 01 Web Site http www chips ibm com techlib products powerpc manuals A 2 Computer Group Literature Center Web Site Related Documentation Table A 2 Manufacturers Documents Continued Publication Document Title and Source Number PowerPCIM Microprocessor Family The Programming Environments MPCFPE AD Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR IBM Microelectronics G522 0290 01 Programming Evnironment Manual Web Site http www chips ibm com techlib products powerpc manuals Intel 82559ER Fast Ethernet PCI Bus Controller with Integrated PHY 73825902 pdf External Design Specificat
181. ctivity This is considered a non recoverable termination and it will take affect almost immediately after the bit has been set If the commanded abort took affect before the completion of a DMA transaction then the DMA Controller will return an abort status to the DSTA register and will optionally interrupt the processor If the transaction completed before the commanded abort took affect then the DMA Controller will return a done status to the DSTA register 4 Detected Error Abort The DMA Controller is sensitive to the following system errors DMA PCI Master received a master abort DMA PCI Master received a target abort DMA PCI Master exceeds maximum retry count DMA PPC Master obtained an address bus time out If any of these conditions are encountered the DMA controller will abort all DMA activity This is considered a non recoverable termination and it will take affect almost immediately after the condition has been detected Once all DMA activity has ceased the DMA Controller will return the appropriate error status to the DSTA register and will optionally interrupt the processor The DSTA register only indicates that an error has been detected and the DMA transaction was aborted Further details associated with the error may be found within the Error Diagnostics function Refer to the section titled Error Diagnostics on page 2 127 for more details There is only one interrupt generated by the DMA C
182. d Transaction Time out The Harrier expects all delayed transactions to be continuously retried by a PCI master until the transaction has completed Besides being in violation of the PCI specification it is considered a serious error if a PCI master aborts i e stops retrying the transaction a delayed transaction before the Harrier finishes the transaction In the event that this happens the Harrier has special logic that facilitates recovery from this type of error An 8 microsecond timer starts counting once the PCT Slave is ready to close out a delayed transaction If a PCI master does not come back to complete the transaction before the timer expires then an Error Exception is generated The delayed transaction is invalidated and the contents of the Inbound FIFO are discarded Unless the transaction was targeted to read sensitive PowerPC address space the effects of an invalidated read transaction are minimal Generating PCI Cycles 2 36 There are four basic types of bus cycles that can be generated on the PCI bus a Memory and I O Computer Group Literature Center Web Site PowerPC to PCI Bridge a Configuration 4 Special Cycle Interrupt Acknowledge Memory and I O Cycles Each Outbound Translation Function may be configured to generate PCI I O or Memory accesses according to the MEM and IOM fields within the OTATx registers as shown in the following table Table 2 5 Memory and l O Attributes PCI Cycle
183. d by the PPC Slave Once closed The PCI Master will remove the remaining un transferred portion of the transaction from the Outbound FIFO Since the PPC Slave cannot detect the occurrence of a PCI error a Store Gather collection is not affected by the error and continues without interruption until a forced flush event occurs Computer Group Literature Center Web Site PowerPC to PCI Bridge a Ifthe transaction was a read and read ahead was not used then the PCI Master invalidates the remaining portion of the aborted transaction by filling the Outbound FIFO with all ones A transaction of this type will always be either a single beat or a burst transaction and the exact number of words to be filled is known by the PCI Master a Ifthe transaction was a read and read ahead was used then the PCI Master will continually fill the Outbound FIFO with all ones until the transaction is closed by the PPC Slave Since the PPC Slave cannot detect the occurrence of a PCI error a read ahead collection will not be affected by the error and will continue without interruption until a forced flush event occurs Inbound Functions An inbound transaction is originated from the PCI bus and is targeted to the PowerPC bus The key functional elements are the PCI Slave the Inbound FIFO and the PPC Master This section describes in detail the elements of the Harrier that are associated with inbound transactions PCI Decode The Harrier provides three res
184. d write accesses are allowed UART Core Registers Offset XCSR 0C0 XCSR 0C8 Bit Function Name Operation Reset The Receiver Buffer Transmitter Holding Divisor Latch Low Register RTDLx consists of three separate registers whose accessibility is based on the state of the DLAB bit in the Line Control Register When DLAB 0 RTDLx RTDLx is the read only Receiver Buffer Register that contains the data byte transmitted to the serial port The data in this register is valid only if the DR bit in the Line Status Register LSTA x is set In the non FIFO mode FIFOEN 0 in the FIFO Control Register the data in this register must be read before the next data arrives otherwise it will be overwritten In the FIFO mode FIFOEN in the FIFO Control Register this register accesses the top of the receiver FIFO If the receiver FIFO is full the data already in the FIFO will be preserved but any new incoming data will be lost 3 136 Computer Group Literature Center Web Site UART Controller RTDLx RTDLx is the write only Transmitter Holding Register that contains the data to be transmitted from the serial port In the non FIFO mode FIFOEN 0 in the FIFO Control Register a byte written to this register will be preserved if the THRE bit in the Line Status Register LSTAx is set If the THRE bit is cleared a write to this register causes the existing data in the r
185. ddress and data parity on the PowerPC bus Upon detection of either an address or data parity error the Harrier can optionally generate an exception Additional hardware allows for the intention injection of address and or data parity errors allowing further testing of the party error exception path Computer Group Literature Center Web Site o1nje1oj 1ojnduroo uroo e o1030ur mMM dy L I weibeig yoo g 1 3eH Z o4nDiJ PowerPC Bus Xport Bus SDRAM Bus Watchdog Timers EE SDRAM Interface IEEE PowerPC Address Bus Timer PowerPC Arbiter PowerPC Parity PowerPC to PCI Bridge Harrier PCI Bus 1 0 and Generic Message Passing PCI Arbiter DMA Controller IC Bus rc Controller amp UART J UART Bus Multi Processor Interrupts Interrupt Controller MOIAIOAQ Introduction 1 8 Computer Group Literature Center Web Site Functional Descriptions This chapter describes in detail the functions of the Harrier ASIC as listed in Chapter 1 Clocking The Harrier uses a fully integrated internal loop filter version of the PLL macrocell with an operating frequency between 400 MHz and 800 MHz The ratio of the PLL s operating frequency to its reference signal frequency is 8 1 and allows the Harrier to support synchronous PowerPC to PCI clock ratios of 1 1 2 1 3 1 3 2 and 5 2 Figure 2 1 shows the block PowerPC C
186. de transaction will be performed A Linked List Mode transaction will perform multiple transfers that are driven by a list of descriptors stored in PowerPC memory A Linked List Mode transaction will obtain the first descriptor from the starting address placed within the DNLA register XTH PowerPC Throttle This field is used to control the attempted transfer size on the PowerPC bus The Harrier associates a transfer size with the assertion of the PowerPC bus request The Harrier will remove the bus request only after completing the desired transfer size If there are more PowerPC transactions pending the Harrier will re assert the bus request after two clocks The encoding of this field is shown in the table below Table 3 29 DCTL XTH Encoding XTH Transfer Size Bytes Cache Lines 00 256 8 01 512 16 10 1024 32 11 Continuous Continuous PBT PCI Back off Timer This field establishes a maximum PCI bus bandwidth that the DMA function may use when performing transfers to or from PCI space The Harrier will attempt to complete an entire http www motorola com computer literature 3 79 Programming Model transfer in one burst unless interrupted by the PCI Master Latency Timer Once the Latency Timer expires and the current burst completes the PCI Back off Timer will start to count The Harrier will not attempt to restart the transfer until after the PCI Back off Timer has expired The back off time is spec
187. del RVENI RVEN2 and RVENG initialize at power up reset to match the values on 4 certain signal pins Refer to the section titled Hardware Configuration on page 2 133 Table 3 44 XPATx RVENx Encoding RVEN3 RVEN2 0 0 X X X X X 1 1 0 0 EE NN NONE RVENO Source of Reset Vectors 0 None of Xport Channels 0 3 1 Xport Channel 0 0 Xport Channel 0 Xport Channel 2 0 Xport Channel 3 DW Data Width This field indicates the Xport Bus s data width The following table shows the encoding Note that the DW bits initialize at power up reset to match the values on two certain input signal pins Refer to the section titled Hardware Configuration on page 2 133 for more details Table 3 45 XPATx DW Encoding 3 152 Data Width 8 bits 16 bits 32 bits 11 16 bits Hawk compatibility mode Computer Group Literature Center Web Site Xport AD Access Delay This field determines the number of CLK periods the Harrier will add to the Xport Bus access time The following table shows the encoding Table 3 46 XPATx AD Encoding AD Added Delay Device Access Time 0000 0 CLK s lons 0001 CLK s 20ns 1110 14 CLK s 150ns 1111 15 CLK s 160ns BLE Burst Length This field determines the maximum number of bytes Harrier will transfer per burst during burst reads or writes to the Xport Bus Note that burst length refers to the number of bytes transferred per burst not to the
188. dentified by the Harrier as CPU 1 See XCSR GCSR MID in the section titled Global Control and Status Register on page 3 194 SDRAM Timing Control Register Offset XCSR 104 Bit el elc dd xesadsmz4sussaddsdsssusas Function Name SDRAM Control Operation Reset The SDRAM Timing Control Register SDTC affects the timing for all banks of SDRAM The fields within the SDTC register are defined as follows CL3 Cas Latency 3 When set the Harrier accesses SDRAM assuming a cas latency of 3 When cleared the Harrier accesses SDRAM assuming a cas latency of 2 Note that the Harrier performs a register set command to SDRAM anytime software changes CL3 Also note that power up reset is the only kind of reset that affects this bit TRC SDRAM timing parameter tRC TRC determines the minimum number of CLK cycles the Harrier uses to satisfy the SDRAM s tRC parameter The following table shows the encoding http www motorola com computer literature 3 27 Programming Model Table 3 9 SDTC TRC Encoding TRC Time for tRC 000 8 CLK s 001 9 CLK s 010 10 CLK s 011 11 CLK s 100 reserved 101 reserved 110 6 CLK s 111 7 CLK s Note Power up reset is the only type of reset that affects this field TRAS SDRAM timing parameter tRAS This field determines the minimum number of CLK cycles the Harrier uses to satisfy the SDRAM s tRAS para
189. der is not interested the logic implementation this section can be skipped http www motorola com computer literature 2 73 Functional Descriptions Int signals Program Visible IPR ZTX rf fa Interrupt Interrupt Selector 1 Selector O IRR 1 IRR 0 ISR 1 ISR 0 Y Y Interrupt Router INT 1 INT 0 Figure 2 17 MPIC Block Diagram 2 74 Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC Program Visible Registers These are the registers that software can access They are described in detail in the MPIC Register section Interrupt Pending Register IPR The interrupt signals to MPIC are qualified and synchronized to the clock by the IPR If the interrupt source is internal to the Harrier or external with their Sense bit 0 edge sensitive a bit is set in the IPR That bitis cleared when the interrupt associated with that bit is acknowledged If the interrupt source is external and level activated the output from the IPR is not negated until the level into the IPR is negated Externally sourced interrupts are qualified based upon their Sense and or Poll bits in the Vector Priority register IPI and Timer Interrupts are generated internally to the Harrier and are qualified by their Destination bit Since the internally generated interrupts use direct delivery mode with multicast capability there are two bits in the
190. dered to be outbound since the completion of these types of accesses depends on the ability of the PCI bus to empty outbound write posted data The ERRAT signal is an open collector wired OR bi directional signal that is used to notify other PowerPC devices of an address bus timeout exception As an output ERRAT is asserted when the PPC Timer expires As an input Harrier uses ERRAT as an indication to the DMA controller that a DMA transaction must be aborted PowerPC Parity 2 130 The Harrier generates data parity whenever it is sourcing PowerPC data This happens when performing a write as a bus master and when servicing a read as a bus slave Valid data parity will be presented when DBB_ is asserted for write cycles and when TA is asserted for read cycles The Harrier checks data parity whenever it is sinking PowerPC data This happens when performing a read as a bus master and when servicing a write as a bus slave Data parity is considered valid anytime TA is asserted If a data parity error is detected then address and attribute information will be latched within the EXAD and EXAT registers and an interrupt or machine check will be generated depending on the programming of the EEMA EEDE and EEMS registers The Harrier has a mechanism to purposely induce data parity errors for testability The DPE field within the EPEI register can be used to purposely inject data parity errors on specific data parity lines Data parity error
191. des an array of bits pertaining to the masking of Functional Exceptions All mask bits will power up with the mask enabled The fields within the FEMA register are defined as follows DMA DMA If cleared an interrupt is generated whenever the FEST DMA bit is set If set an interrupt is not generated MIDB Message Passing Inbound Doorbell If cleared an interrupt is generated whenever the FEST MIDB bit is set If set an interrupt is not generated MIMO Message Passing Inbound Message Register 0 If cleared an interrupt is generated whenever the FEST MIMO bit is set If set an interrupt is not generated MIM1 Message Passing Inbound Message Register 1 If cleared an interrupt is generated whenever the FEST MIM 1 bit is set If set an interrupt is not generated MIP Message Passing Inbound Post list If cleared an interrupt is generated whenever the FEST MIP bit is set If set an interrupt is not generated UAO0 UART 0 If cleared an interrupt is generated whenever the FEST UAO bit is set If set an interrupt is not generated Computer Group Literature Center Web Site Exceptions UA1 UART 1 If cleared an interrupt is generated whenever the FEST UA1 bit is set If set an interrupt is not generated ABT Abort If cleared an interrupt is generated whenever the FEST ABT bit is set If set an interrupt is not generated Functional Exception Clear Register Offset XCSR 04C Bit o ooog Function e
192. detects a Sync cycle originating from the processor responsible for a collection If cleared a collection is not flushed when a Sync is detected RBT Read Ahead Backup Timer This field specifies the maximum time in processor clock cycles that may take place between qualified reads when using read ahead Please refer to the section titled Read Ahead in the previous chapter for more information The options available are shown in the following table Table 3 18 BXCS RBT Encoding RBT Time Out Length 00 32 clocks 01 64 clocks 10 256 clocks 11 disabled SBT Store Gather Backup Timer This field specifies the maximum time in processor clock cycles that may take place between collectable writes when using Store Gather Please refer to the section titled PPC Master on page 2 33 for more information The options available are shown in the following table Table 3 19 BXCS SBT Encoding SBT Time Out Length 00 32cocks 01 64 clocks 10 256 clocks 11 disabled P1H Processor 1 Holdoff This field is used to hold processor 1 in a reset state HRST1_ asserted following a local bus reset RST asserted This field may be used to allow a PCI master to program the Harrier using a wrapped back Inbound Translation Function before allowing the processor to start code execution Computer Group Literature Center Web Site PowerPC to PCI Bridge If set the HRST1_ signal is held in th
193. e Device Number Address Bit 00000 AD31 00001 01010 All Zeros 01011 ADII 01100 AD12 etc etc 11101 AD29 11110 AD30 11111 All Zeros The Bus Number determines which bus is the target for the configuration read cycle The Harrier always hosts PCI bus 0 Any access that is performed on the PCI bus connected to the Harrier must have zero programmed into the Bus Number If the configuration access is targeted for another PCI bus then that bus number should be programmed into the Bus Number field The Harrier detects a non zero field and converts the transaction to a Type Configuration cycle Special Cycles The Harrier supports the method stated in PCI Local Bus Specification 2 1 using Configuration Mechanism 1 to generate Special Cycles To prime the Harrier for a Special Cycle the host processor must write a 32 bit value to the CONFIG_ADDRESS register The contents of the write are defined in the section titled CONFIG_ADDRESS Register in Chapter 3 After the write to CONFIG_ADDRESS has been accomplished the next write to the CONFIG_DATA register causes the Harrier to generate a Special Cycle on the PCI bus The write data is driven onto AD 31 0 during the Special Cycle data phase Computer Group Literature Center Web Site PowerPC to PCI Bridge Interrupt Acknowledge Cycles Performing a read from the PIAC register initiates a single PCI Interrupt Acknowledge cycle Any single byte or combination of
194. e Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rdO 4A rd16 92 rd32 A4 rd48 29 ckd0 01 rdl 4C rd17 13 rd33 C4 rd49 31 ckd1 02 rd2 2C rd18 0B rd34 C2 rd50 BO ckd2 04 rd3 2A rd19 8A rd35 A2 rd51 A8 ckd3 08 rd4 E9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C rd21 07 rd37 Cl rd53 70 ckd5 20 rd6 1A rd22 86 rd38 Al rd54 68 ckd6 40 rd7 19 rd23 46 rd39 91 rd55 64 ckd7 80 rd8 25 rd24 49 rd40 52 rd56 94 rd9 26 rd25 89 rd41 62 rd57 98 rd10 16 rd26 85 rd42 61 rd58 58 rdl1 15 rd27 45 rd43 51 rd59 54 rd12 F4 rd28 3D rd44 4F rd60 D3 rd13 0E rd29 83 rd45 SEO rd61 38 rd14 0D rd30 43 rd46 D0 rd62 34 rd15 8C rd31 23 rd47 C8 rd63 32 http www motorola com computer literature 3 35 Programming Model SDRAM Single bit Error Address Register Function Offset XCSR 144 Bit ed g Name SDSEA Operation R t Reset 00000000 P a SDRAM Error Logging The SDRAM Single bit Error Status Register SDSEA reflects the address present when the Harrier last logged a single bit error The SDSEA s one and only field is defined as follows SDSEA SDRAM Single bit Error Address This field contains the address of the last single bit error logged by the Harrier refer to the section titled Error Exception Enable Register on page 3 170 for more information If the error was due to a PowerPC access SDSEA matches the value that was on
195. e Watchdog Timers is a two step process 1 First arm the WTxC register by writing PATTERN 1 into the KEY field Only the KEY byte lane may be selected during this process The WTxC register will not arm itself if any of the other byte lanes are selected or the KEY field is written with any other value than PATTERN 1 The operation of the timer itself remains unaffected by this write 2 Next write the new programming information to the WTxC register The KEY field byte lane must be selected and must be written with PATTERN 2 for the write to take affect The effects on Computer Group Literature Center Web Site Watchdog Timers the WTXxC register depend on the byte lanes that are written to during step 2 and are shown in the following table Table 2 21 WTxC Programming Byte Lane Selection Results KEY ENAB RELOAD WTx WTxC Register RES 0 7 8 15 16 23 24 31 Prescaler Counter RES ENAB RELOAD Enable No X X X NoChange NoChange NoChange No Change Yes No No X Update Update No Change No Change from from RES ENAB RELOAD Yes No X No Update Update No Change No Change from from RES ENAB RELOAD Yes Yes No X Update Update Update No Change from data from from data bus RELOAD bus Yes Yes X No Update Update Update No Change from data from from data bus RELOAD bus Yes Yes Yes Yes Update Update Update Update from data from data from data from bus bus bus data bus
196. e asserted state If cleared the state of the HRST1_ signal is determined RST The default state of this bit is determined at the release of reset Please refer to the section titled Hardware Configuration on page 2 133 for more information POH Processor 0 Holdoff This field is used to hold processor 0 in a reset state HRSTO asserted following a local bus reset RST_ asserted This field may be used to allow a PCI master to program the Harrier using a wrapped back Inbound Translation Function before allowing the processor to start code execution If set the HRSTO signal will be held in the asserted state If cleared the state of the SRSTO signal is determined by RST_ The default state of this bit is determined at the release of reset Please refer to the section titled Hardware Configuration on page 2 133 for more information CSE Copy back Snarfing Enable This field is used to enable snarfing on a processor s copy back cycle See the section titled Copyback Snarfing on page 2 35 for more information If set copy back snarfing will be attempted for inbound read cycles If cleared snarfing will not be attempted PCI Interrupt Acknowledge Register Offset XCSR 210 Bit Function Interrupt Acknowledge Reset 00000000 The PCI Interrupt Acknowledge Register PIAC is a read only register that is used to initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes
197. e corresponding Timer Base Count Register TIBC and the Count Inhibit CT bit in the corresponding TIBC register transitions from a 1 to a 0 CC Current Count The Current Count field decrements while the Count Inhibit bit in the Base Count register is zero When the Current Count register counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt becomes pending in MPIC processing 3 120 Computer Group Literature Center Web Site Multi Processor Interrupt Controller Timer Base Count 0 1 2 and 3 Registers Offset TIBCO XMPI 01110 TIBC1 XMPI 01150 TIBC2 XMPI 01190 TIBC3 XMPI 011D0 Function Timers Reset p 00000000 The Timer Base Count Registers TIBCO TIBC1 TIBC2 and TIBC3 are programmed with the base count value of the MPIC timers The fields within the TIBCx registers are defined as follows CI Count Inhibit Setting this bit to one inhibits counting for this timer Setting this bit to zero allows counting to proceed BC Base Count This field contains the 31bit count for this timer When a value is written into this register and the CI bit transitions from a 1 to a O it is copied into the corresponding Current Count register and the toggle bit in the Current Count register is cleared When the Current Count register counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt be
198. e default setting in fixed mode 2 HEIR only covers a small subset of all possible combinations It is the responsibility of the system designer to connect the request grant pair in a manner most beneficial Table 2 19 HEIR Encoding for Mixed Mode Priority HEIR PRIORITY Levels Highest Lowest 000 group 1 group 2 group 3 group 4 PARB 6 amp 5 PARB 4 amp 3 PARB 2 amp 1 PARB 0 amp HARR 001 group 4 group 1 group 2 group 3 PARB 0 amp PARB 6 amp 5 PARB 4 amp 3 PARB 2 amp 1 HARR http www motorola com computer literature Functional Descriptions Table 2 19 HEIR Encoding for Mixed Mode Priority Continued HEIR PRIORITY Levels Highest Lowest 010 group 3 group 4 group 1 group 2 PARB 2 amp 1 PARB 0 amp PARB 6 amp 5 PARB 4 amp 3 HARR 011 group 2 group 3 group 4 group 1 PARB 4 amp 3 PARB 2 amp 1 PARB 0 amp PARB 6 amp 5 HARR Notes 2 118 1 000 is the default setting in mixed mode 2 HEIR only covers a small subset of all possible combinations and the requestors within each group is fixed and cannot be interchanged with other groups It is the responsibility of the system designer to connect the request grant pair in a manner that is most beneficial to his or her design goals 3 All combinations of HEIR not specified in the table are invalid and should not be used Arbitration parking is programmable by writing to the PRK field of
199. e ext gntl_ PARBO2 Output Tristate ext gnt2 PARBO3 Output Tristate ext gnt3_ PARBO4 Output Tristate Output ext gnt4_ Output NA PARBOS Output Tristate Output ext gnt5_ Output NA PARBO6 Output Tristate Output ext gnt6_ Output NA http www motorola com computer literature 2 115 Functional Descriptions The PCI Arbiter is controlled by the PARB register within the XCSR Register Group The PCI Arbiter supports three different priority schemes fixed round robin and mixed mode It also provides different prioritization options within either the fixed and mixed mode Parking can be disabled given to any one requester or given to the last requester A special bit is added to hold grant asserted for an agent that initiates a lock cycle Once a lock cycle is detected the grant is held asserted until the PCI LOCK pin is released This feature works only when the POL feature is enabled The priority scheme can be programmed by writing the PRI field in the PARB register The Fixed mode holds each requestor at a fixed level in its hierarchy The levels of priority for each requestor are programmable by writing the HEIR field in the PARB register Table 2 18 on page 2 117 describes all available settings for the HEIR field in fixed mode When the PCI Arbiter is programmed for round robin priority mode the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants The contents of HEIR
200. e is not closed out by the assertion of AACK The PPC Timer will not handle the case where a data tenure is not closed out by the appropriate number of TA assertions The PPC Timer will start timing atthe exact moment when the PowerPC bus pipeline has gone flat In other words the current address tenure is pending closure all previous data tenures have completed and the current pending data tenure awaiting closer is logically associated with the current address tenure The time out function is aborted if AACK_ is asserted anytime before the time out period has passed If the time out period reaches expiration then the PPC Timer will assert AACK_ to close the faulty address tenure If the transaction was an address only cycle then no further action will be taken If the faulty transaction was a data transfer cycle then the PPC Timer will assert the appropriate number of TA_ s to close the pending data tenure Error information related to the faulty transaction will be latched within the EXAD and EXAT registers and an interrupt or machine check will be generated depending on the programming of the EEMA EEDE and EEMS registers There is one exception that will dynamically disable the PPC Timer If the transaction is outbound then the burden of closing out a transaction is left to the PCI bus Note that a transaction to the PowerPC Control Register http www motorola com computer literature 2 129 Functional Descriptions Group is consi
201. e master only serial ports to support communication with slave PC devices such as serial EEPROMs The C interface is compatible with these devices and the inclusion of a serial EEPROM in the memory subsystem may be desirable The EEPROM could maintain the configuration information related to the memory subsystem even when the power is removed from the system Each slave device connected to the C bus is software addressable by a unique address The number of interfaces connected to the IC bus is solely dependent on the bus capacitance limit of 400pF For C bus programming the Harrier is the only master on the bus and the serial EEPROM devices are all slaves The C bus supports 7 bit addressing mode and transmits data one byte at a time in a serial fashion with the most significant bit MSB being sent out first Five registers are required to perform the IC bus data transfer operations These are the PC Clock Prescaler I2PSx Register PC Control I2COx Register PC Status I2STx Register PC Transmitter Data IZTDx Register and PC Receiver Data I2RDx Register The IC serial data SDAx is an open drain bidirectional line on which data can be transferred at a rate up to 100 Kbits s in the standard mode or up to 400 kbits s in the fast mode The PC serial clock SCLx is programmable via the I2PSx Register The PC clock frequency is determined by the following formula C CLOCK SYSTEM CLOCK I2PSx41 2 The C bus has the a
202. e of data indicated by DIN 1 in the I2STx Register the system software may then read the data by polling the IZRDx Register The C master controller does not acknowledge the read data for a single byte transmission on the PC bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the STP and ENA bits in the I2COx Register and then writing a dummy data data don t care to the IZTDx Register The I2STx Register must now be polled to test CMP bit for the operation complete status The stop sequence will relinquish the Harrier master s possession of the IC bus The following figure shows the suggested software flow diagram for programming the C current address read operation http www motorola com computer literature 2 87 Functional Descriptions DEVICE ADDR DATA of last ADDR 1 M RIA I N SDA START S ple O STOP B K A c K ACK and DATA from Slave Device READ I2C STATUS REG LOAD 09 START CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR RD BIT TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Y LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C RECEIVER DATA REG LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Stop condition
203. e same order that they are issued on the originating bus A read or a compelled write transaction will force all previously issued write posted transactions to be flushed from the FIFO All write posted transfers will be completed before aread or compelled write is begun to assure that all transfers are completed in the order issued The Harrier can accept posted write transactions while servicing a delayed read however the ordering on the destination bus always allows the read transaction to complete before the write transactions The Harrier s design eliminates any adverse affects that can occur when control register bits are changed during transaction processing In some special cases a register access may be delayed while Harrier performs the necessary change but in general the register access time is unaffected The PCI Local Bus Specification 2 1 states that posted write buffers in both directions must be flushed before completing a read in either direction Harrier supports this by providing two optional FIFO flushing options The FBR Flush Before Read bit within the BXCS register controls the flushing of inbound write posted data when performing outbound read transactions The FBR Flush Before Read bit within the BPCS register controls the flushing of outbound write posted data when performing inbound read transactions Both FBR functions are completely independent of each other however both functions must be enabled to guarantee
204. e status bit will always read zero Computer Group Literature Center Web Site Exceptions PDT PCI Bus Delayed Transaction Time out If set the PCI Delayed Transaction Time out exception is enabled When the exception is enabled the status bit EEST PDT will indicate the state of the PCI Delayed Transaction Time out exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PSE PCI SERR If set the PCI SERR exception is enabled When the exception is enabled the status bit EEST PSE will indicate the state of the PCI SERR exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PPE PCI PERR If set the PCI PERR exception is enabled When the exception is enabled the status bit EEST PPE will indicate the state of the PCI PERR exception When the enable bit is cleared the exception is disabled and the status bit will always read zero PMR PCI Master Retry If set the PCI Master Retry exception is enabled When the exception is enabled the status bit EEST PMR will indicate the state of the PCI Master Retry SSE SDRAM Memory Controller Single Bit Error If set the SDRAM Memory Controller Single Bit Error exception is enabled When the exception is enabled the status bit EEST SSE will indicate the state of the SDRAM Memory Controller Single Bit Error exception When the enable bit is cleared the exception is disabl
205. e table below shows the format of a descriptor Table 2 8 DMA Controller Linked List Descriptors Offset Bits 0 31 32 63 00 DSAD DSAT 08 DDAD DDAT 10 DNLA DCNT 18 Each field in the descriptor corresponds to a DMA control register When a descriptor is loaded by the DMA Controller each field is placed into it s corresponding DMA control register A complete description of each control register may be found in the section titled Bridge PowerPC Control and Status Register on page 3 41 Computer Group Literature Center Web Site DMA Controller The descriptors are linked together by the DNLA register i e the DNLA field within a descriptor This field contains the address within PowerPC address space where the next descriptor may be found The LLA field Last Link descriptor Address within the DNLA indicates that this is the last descriptor Descriptors will not be prefetched by the DMA PPC Master A Linked List Mode transaction will be started by the DMA PPC Master reading one descriptor The DMA Controller will then perform the transfer associated with that descriptor If there are more descriptors to be executed then the fetching of the next descriptor will not occur until the current transfer has completed Transfer Termination There are four ways that DMA activity may be terminated 1 Transfer or Transaction Completion In most cases a Direct Mode transfer or a Linked List Mode tra
206. eared the DMA will use the Read transfer type This will allow the processor to retain cached data in the E and S states GBL Global If set the DMA will assert the GBL_ pin during PowerPC read cycles This will allow the processor to snoop the DMA transfer If cleared the GBL_ pin will not be asserted and the processor will not be able to snoop the DMA transaction DMA Destination Address Register Offset XCSR 268 Bit Name Operation R W Reset 00000000 The DMA Destination Address Register DDAD contains the destination address for a DMA transfer If the destination is PCI space then this field will represent a PCI address If the destination is PowerPC space then this field will represent a PowerPC address 3 86 Computer Group Literature Center Web Site DMA Controller User software must program this register when performing Direct Mode transactions When performing Linked List Mode transactions this register is automatically loaded from the destination address field of the current descriptor DMA Destination Attribute Register Offset XCSR 26C Bit Name Operation Reset Function DMA The DMA Destination Attribute Register DDAT contains the destination attributes for a DMA transfer Not all fields are used for all transfer types Fields that do not pertain to a particular transfer type are ignored User softw
207. eby destroying the previous character It is cleared by a read from the LSTAx register In the FIFO mode an overrun error will occur only after the receiver FIFO is full and the next character has been completely received in the Receiver Shift Register The OE bit is set as soon as this happens The character in the Receiver Shift Register is then overwritten but it is not transferred to the receiver FIFO DR Data Ready This bit is set to a logic 1 whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the receiver FIFO It is reset to a logic 0 by reading the Receiver Buffer Register or by reading all of the data in the receiver FIFO The MODEM Status Register MSTAx provides the current state of the MODEM control lines In addition four bits of the MSTAx Register provide change information These bits are set to a logic 1 whenever a control input from the MODEM changes state and are reset to a logic 0 whenever the MSTAx is read The fields within the MSTAx register are defined as follows DCD Data Carrier Detect When LOOP 0 this bit is the complement of the Data Carrier Detect DCDx input When LOOP this bit is equivalent to OUT2 in the MCTLx Register RI Ring Indicator When LOOP 0 this bit is the complement of the Ring Indicator RIx_ input When LOOP 1 this bit is equivalent to OUTI in the MCTLx Register DSR Data Set Ready When LOOP 0 this bitis the
208. ed If cleared a machine check to processor 0 will not be generated Note PowerPC Bus delayed transaction time outs can occur during normal operation The XDT bit should NOT be set Error Exception Machine Check 1 Enable Register Offset XCSR 064 Bit e c su co Modo due S999 RAS NS N ejcj Function Name EEMCK1 Operation Exceptions The Error Exception Machine Check 1 Enable Register EEMCK1 provides an array of machine check 1 enable bits pertaining to the various error exceptions The fields within the EEMCK1 register are defined as follows PMA PCI Master Abort If set a machine check will be generated to processor 1 whenever the EEST PMA bit is asserted If cleared a machine check will not be generated to processor 1 PTA PCI Target Abort If set a machine check will be generated to processor 1 whenever the EEST PTA bit is asserted If cleared a machine check will not be generated to processor 1 http www motorola com computer literature 3 185 Programming Model 3 186 PAP PCI Address Parity Error If set a machine check will be generated to processor 1 whenever the EEST PAP bit is asserted If cleared a machine check will not be generated to processor 1 PDP PCI Data Parity Error If set a machine check will be generated to processor 1 whenever the EEST PDP bit is asserted If cleared a machine check will not be generat
209. ed abort was issued then it did not take affect before the transaction was completed Ifacommanded pause was issued then it did not take affect before the transaction was completed BSY Busy This read only field reflects the status of the DMA Controller If set the DMA Controller is currently processing a DMA transaction If cleared the DMA Controller has completed a previous transaction and is now idle DMA Source Address Register Offset XCSR 260 Bit Function Name DSAD DMA Operation R W Reset 00000000 The DMA Source Address Register DSAD contains the source address for a DMA transfer If the source is PCI space then this field will represent a PCI address If the source is PowerPC space then this field will represent a PowerPC address If the source is a data pattern then this field will represent the beginning pattern This register is interpreted differently depending on if the data pattern transfer is represented in bytes or words When the pattern size is http www motorola com computer literature 3 83 Programming Model bytes then the starting pattern is represented by bit positions 24 thru 31 of this register If the pattern size is words then the starting pattern is represented by the entire 32 bits of this register User software must program this register when performing Direct Mode transactions When performing Linked List Mode transactions this register is automatically loaded
210. ed and the status bit will always read zero SSC SDRAM Memory Controller Single Bit Error Count Overflow If set the SDRAM Memory Controller Single Bit Count Overflow exception is enabled When the exception is enabled the status bit EEST SSC will indicate the state of the SDRAM Memory Controller Single Bit Count Overflow exception When the enable bit is cleared the exception is disabled and the status bit will always read Zero SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access If set the SDRAM Memory Controller Multi Bit Error on PowerPc Access exception is enabled When the exception is enabled the status bit EEST SMX will indicate the state of the SDRAM http www motorola com computer literature 3 171 Programming Model 3 172 Memory Controller Multi Bit Error on PowerPC Access exception When the enable bit is cleared the exception is disabled and the status bit will always read zero SMS SDRAM Memory Controller Multi Bit Error on Scrub If set the SDRAM Memory Controller Multi Bit Error on Scrub exception is enabled When the exception is enabled the status bit EEST SMS will indicate the state of the SDRAM Memory Controller Multi Bit Error on Scrub exception When the enable bit is cleared the exception is disabled and the status bit will always read Zero XBT PowerPC Bus Time out If set the PowerPC Bus Time out exception is enabled When the exception is enabled the status bit EEST XBT will
211. ed or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set SENSE Sense This bit sets the sense for the Harrier internal interrupts errors This bit is hard wired to 1 to enable active low level sensitive interrupts errors PRIOR Priority Interrupt priority O is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR Vector This vector is returned when the Interrupt Acknowledge register is examined when the interrupt associated with this vector is acknowledged Computer Group Literature Center Web Site Multi Processor Interrupt Controller Harrier Internal Functional Error Interrupt Destination Register Offset XMPI 10210 XMPI 10230 ibSiTpPEERI Name IFEDE IEEDE Internal al al Operation R R R n Reset 00 00 00 aAadaddad The Harrier Internal Functional Error Interrupt Destination Register IFEDE IEEDE indicates the destination of internal interrupts These interrupts operate in the Distributed interrupt delivery mode The fields of the IFEDE IEEDE register are defined as follows P1 Processor 1 The interrupt is pointed to processor 1 P0 Processor 0 The interrupt is pointed to processor 0 http www motorola com computer literature 3 127 Programming Model Processor 0 Processor 1 IPI Dispatch 0 1 2 and 3 Registers Offset Bit
212. ed to processor 1 PDT PCI Bus Delayed Transaction Time out If set a machine check will be generated to processor 1 whenever the EEST PDT bit is asserted If cleared a machine check will not be generated to processor 1 PSE PCI SERR If set a machine check will be generated to processor 1 whenever the EEST PSE bit is asserted If cleared a machine check will not be generated to processor 1 PPE PCI PERR If set a machine check will be generated to processor 1 whenever the EEST PPE bit is asserted If cleared a machine check will not be generated to processor 1 PMR PCI Master Retry If set a machine check will be generated to processor 1 whenever the EEST PMR bit is asserted If cleared a machine check will not be generated to processor 1 SSE SDRAM Memory Controller Single Bit Error If set a machine check will be generated to processor l whenever the EEST SSE bit is asserted If cleared a machine check will not be generated to processor 1 SSC SDRAM Memory Controller Single Bit Error Count Overflow If set a machine check will be generated to processor 1 whenever the EEST SSC bit is asserted If cleared a machine check will not be generated to processor 1 SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access If set a machine check will be generated to processor 1 whenever the EEST SMX bit is asserted If cleared a machine check will not be generated to processor 1 Computer Group Literature Center Web
213. ee bridge system in which case the third bridge device would be connected to the CPU1 request grant pair When the PPC Arbiter is disabled the Harrier generates an external request and listens for an external grant for itself It also listens to the other external grants to determine the PowerPC master identification field MID within the GCSR register When the PPC Arbiter is enabled the Harrier will receive requests and issue grants for itself and for the other three bus masters The MID field is determined by the PPC Arbiter The PowerPC arbitration signals and their functions are summarized in the table below Table 2 16 PPC Arbiter Pin Assignments Pin Name Reset Internal Arbiter External Arbiter Direction Function Direction Function XARBO Tristate Output CPUO Grant Input CPUO Grant XARBI BiDir Tristate Output CPUI Grant Input CPUI Grant XARB2 Output Output EXTL Grant_ Output HARR Request_ http www motorola com computer literature 2 113 Functional Descriptions Table 2 16 PPC Arbiter Pin Assignments Continued Pin Name Pin Reset Internal Arbiter External Arbiter Type Direction Function Direction Function XARB3 Input Input CPUO Request_ Input CPUO Request XARB4 Input Input CPU1 Request_ Input CPUI Request XARBS5 Input Input EXTL Request Input HARR Grant 2 114 While RST is asserted XARBO and XARBI are held
214. egister Interrupt Delivery Modes 2 72 The direct and distributed interrupt delivery modes are supported Note that the direct deliver mode has sub modes of multicast or non multicast The Inter Processor interrupts and Timer interrupts operate in the direct delivery mode The externally sourced or I O interrupts operate in the distributed mode In the direct delivery mode the interrupt is directed to one or both processors If it is directed to two processors i e multicast it will be delivered to two processors The interrupt is delivered to the processor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of the interrupt is greater than any interrupt which is in service for that processor An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC In the distributed delivery mode the interrupt is pointed to one or more processors but it will be delivered to only one processor Therefore for externally sourced or I O interrupts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority
215. egister to be overwritten In the FIFO mode FIFOEN 1 in the FIFO Control Register up to 16 bytes of data may be written to this register before the FIFO is full after which any new data written to this register will be lost When DLAB 1 RTDLx RTDLx is the Divisor Latch Low least significant byte Register that contains the lower 8 bits of the baud rate divisor for the UART This register in conjunction with the Divisor Latch High Register form a 16 bit baud rate divisor The output baud rate is calculated as follows BAUD RATE OSCILLATOR FREQUENCY 16 BAUD RATE DIVISOR The Interrupt Enable Divisor Latch High Register IEDHXx consists of two separate registers whose accessibility is based on the state of the DLAB bit in the Line Control Register When DLAB 0 IEDHx IEDHXx is the Interrupt Enable Register which contains four bits that control the generation of UART interrupts Each interrupt can be indicated as active in the Interrupt Identification Register IDFCx and can individually activate the interrupt output signal The fields within this register are defined as follows EDSSI Enable MODEM Status Interrupt This bit when set enables the MODEM Status Interrupt ELSI Enable Receiver Line Status Interrupt This bit when set enables the Receiver Line Status Interrupt ETBEI Enable Transmitter Holding Register Empty Interrupt This bit when set enables the Transmitter Holding Register Empty Interrupt
216. eing the least significant The terms control bit and status bit are used extensively in this document The term control bit is used to describe a bit in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions xxiii Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual XXiV The following typograp
217. elds within the OTAT3 register are defined as follows ENA Enable If set the corresponding Outbound Translation Function is enabled for read and write transactions WPE Write Post Enable If set write posting is enabled for the corresponding Outbound Translation Function IOM I O Mode If set the corresponding Outbound Translation Function will generate PCI I O cycles using spread addressing as defined in the section titled Generating PCI Cycles on page 2 36 If cleared the corresponding Outbound Translation Function will generate PCI I O cycles using contiguous addressing Computer Group Literature Center Web Site PowerPC to PCI Bridge Passive Slave Address Registers Offset PSAD XCSR 248 bip Name PSAD Address Operation R W R Reset 00000 0 The Passive Slave Address Register PSAD control the mapping of the passive slave function within the PowerPC memory space BASE Base Address These bits define the memory space base address of the Passive slave translation function Note that the actual number of writable bits positions depends on the size of the resource being offered The size of a resource can be changed using the PSSZ register The previous table in this chapter titled PCI Message Passing PMEP Register Group on page 3 23 shows the relationship between resource size and the BASE field The PSAD decoder is disabled when BASE is all zeros Table 3 21 BASE Encoding and Resource Si
218. emented If the source is a data pattern then the data pattern will not be incremented If cleared the source will be incremented PSZ Pattern Size If set the data size used during Data Pattern transfers will be bytes If cleared the data size will be words This field only applies to the generation of the data patterns used for a transfer It does not specify how the patterns are actually placed into the destination space i e selecting a byte pattern size does not result in a stream of single beat PowerPC or PCI bus cycles PRC PCI Read Command This field represents the command used during PCI read cycles Note that this field is only applicable if the TYP field represents a PCI bus DMA source The encoding of this field matches that described within the section titled Command Definition in the PCI Local Bus Specification The following table shows the recommended values for PRC http www motorola com computer literature 3 85 Programming Model Table 3 32 DSAT PRC Encoding PRC PCI Command 0010 IO Read 0110 Memory Read 1100 Memory Read Multiple 1110 Memory Read Line Using an encoding other than the recommended value will result in unpredictable DMA operation CRI Cache line Read Invalidate If set the DMA will use the Read with intent to modify transfer type during PowerPC read cycles This will force processor cached data in the E and S states to be invalidated during snoop hits If cl
219. eption Status Register FEST is a read only register that provides an array of status bits pertaining to the various Functional Exceptions that the Harrier can generate The fields within the FEST register are defined as follows 3 166 DMA DMA If set the DMA Controller has completed a DMA transaction If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt by writing a one to the FECL DMA bit MIDB Message Passing Inbound Doorbell If set a doorbell bit within the PMEP MGID register has been written by a PCI master If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt by writing a one to the applicable doorbell bits within the XCSR MGID register Computer Group Literature Center Web Site Exceptions MIMO Message Passing Inbound Message Register 0 If set an inbound message has been written to the PMEP MGIMO register by a PCI master If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt by writing a one to the FECL MIMO bit MIM1 Message Passing Inbound Message Register 1 If set an inbound message has been written to the PMEP MGIMI register by a PCI master If the FEMA register permits a processor interrupt will be generated The processor may clear this field and the associated interrupt
220. er than the expected a A continuous burst with a small FIFO size creates multiple smaller burst transfers on PCI The increase amount of transfers on PCI makes the overall transaction more susceptible to bandwidth degradation due to initial latencies on PCI 2 42 Computer Group Literature Center Web Site PowerPC to PCI Bridge 4 A continuous burst with a large FIFO size creates fewer but longer burst transfers on PCI and is less susceptible to initial latency bandwidth degradation 4 Selection of an empty threshold works well if the transactions are almost always smaller than the virtual FIFO size If the transaction size exceeds the FIFO size then the transaction bandwidth will be severely degraded since wait states will be incurred between when the FIFO goes empty and when the PCI Master can start filling the FIFO again 4 Boundary cases may not work as expected The PPC Slave is not very efficient at determining when a read ahead collection has completed For example if the processor reads 64 bytes and stops the PPC Slave will still consider the collection open until told otherwise by the processor If configured for an empty threshold with a 64 byte FIFO the completion of the transaction will more than likely result in another prefetch by the PCI Master Note that a transaction size that is slightly smaller than the FIFO size with an empty threshold will behave as expected In this case the processor PPC Slave has no problem
221. erform store gathering on word 32 bit dword 64 bit and cache line operands The PPC Slave continues to collect words indefinitely until either a forced flush condition occurs or the Outbound FIFO approaches the full state If forced to flush or unload the FIFO the PPC Slave closes the current store gathering collection The PCI Master then immediately attempts to move the remainder of the collection to the PCI bus There are two groups of events that can force a collection flush Mandatory Flush Events and Optional Flush Events A Mandatory Flush is caused by normal address or data flow events The following events are considered Mandatory Flush Events a An outbound write transfer size other than an aligned 32 bit word 4 An outbound write to a non contiguous address including byte misalignment of an existing collection a An outbound read cycle a An outbound write of any size or address from a processor other than the one responsible for the current collection There are two Optional Flush Events the Store Gather Backup Timer and the Store Gather Sync Flush The Store gather Backup Timer is a programmable timer that watches for large gaps of time between contributions to a collection The timer is reset anytime a contribution is made to a collection If another contribution is not made before the timer times out the current collection will be flushed The timer may be disabled if so desired The characteristics of the Store
222. ers PowerPC bus 2 113 IN 4 Memory and I O Cycles 2 37 message passing 2 60 Message Passing Registers 2 67 Motorola Computer Group documents A 1 MPIC block diagram 2 73 changing I O interrupt configuration 2 80 EOI register 2 81 external interrupt service 2 78 features architecture 2 68 function described 1 5 interprocessor interrupts 2 80 interrupt acknowledge register 2 81 operational characteristics 2 80 programming notes 2 78 reset state 2 79 MXRR Multiply the Refresh Rate SDRAM General Control Register 3 25 N naming conventions PowerPC PCI 2 11 negation definition xxii O OTATX registers role in memory and I O cycles 2 37 OTOFx register role in I O address translation 2 37 role in memory and I O handling 2 37 Outbound FIFO 2 19 outbound functions PowerPC to PCI bus 2 14 Outbound Translation Function attributes 2 15 Outbound Translation Function 3 3 19 P Page Write I2C 2 89 Passive Slave Computer Group Literature Center Web Site role 2 23 PCFS Register Group role in inbound transactions 2 25 PCI Arbiter 2 115 PCI bus 0 2 40 PCI bus cycles types 2 36 PCI Bus Errors as outbound error type 2 24 PCI Configuration Space PCFS Register Group 3 21 PCI Master role 2 19 PCI Message Passing PMEP Register Group 3 23 PCI Message Passing Register Group role in inbound transactions 2 30 PCI Slave types of transactions accepted 2 30 PCLK relation to XCLK 2 2 PIAC register role in interrupt ackno
223. es and ownership of the current PowerPC bus cycle with those of previously accepted delayed transaction bus cycle If there is a match then the PPC Slave will complete both the address tenure and the data tenure At this point a delayed transaction is considered complete The PPC Slave cannot perform compelled burst write transactions The PowerPC bus protocol mandates that the qualified retry window must occur no later than the assertion of the first TA of a burst transaction If the Harrier were to attempt a compelled linkage for all beats within a burst write there is a possibility that the transaction could be interrupted The interruption would occur at a time past the latest qualified retry window and the PPC Slave would be unable to retry the transaction Therefore all burst write transactions are posted regardless of the write posting attribute within the associated map decoder register The PPC Slave can accept posted writes to PCI when there is a delayed transaction within the Command FIFO The PPC Slave mandates that the delayed transaction within the Command FIFO must be a compelled read cycle and there is enough room in the Command FIFO and Write Data FIFO to accept the current write Computer Group Literature Center Web Site PowerPC to PCI Bridge Outbound FIFO The Outbound FIFO is used to hold data between the PPC Slave and the PCI Master to ensure that optimum data throughput is maintained The Outbound FIFO consists of
224. es the Harrier as the following Header Type 00 Single Function Configuration Header The Master Latency Timer Register MLAT represents the value used for the Master Latency Timer The Master Latency Timer specifies the amount of PCI clock periods that the Harrier may remain on the PCI bus during burst cycles after GNT_ is taken away The MLAT register provides a minimum granularity of the 8 PCI clock periods The PCI specification states that this register must power up to all zeros Severe performance degradation may result if this register is not adjusted from the reset value The Cache Line Size Register CLSZ represents the number of 32 bit words that define a Harrier cache line A Harrier cache line is defined as 32 bytes which is eight 32 bit words If a value of 08 is written to this register the value will be retained If any other value is written to this register a value of 00 will be retained The PCI specification states that this register must power up to all zeros The Harrier is not able to generate the Memory Write and Invalidate command therefore this register is only used to inform other PCI masters of the Harrier supported cache line size for Read Read Line and Read Multiple commands Computer Group Literature Center Web Site PowerPC to PCI Bridge Message Passing Register Group Base Address Register Perspective from the PCI Bus Offset PCFS 10 Bit Functio
225. es 2 71 ji st ND INN peer ne Ro PORE CR ENED Ay A E NE 2 72 cen Te qoo MM 2 72 Block Digsram DESC a puoni Pkw RA SRNREN NI BUM RR MUSEUM M MEME 2 73 las oru i0lMici s M 2 75 Interrupt Pending Rogister IP oe oae aint utut ana pud ML Pn i cM ER NU edu 2 75 enop selector ioco C 2 75 Interrupt Boquest Register WRR aee esee niocsssoniasedhdanaredaansaasonnnansnpnacatics 2 16 Disi Us Ror ster ISR PET 2 76 DN M doo MM 2 16 lucra innen Mao MH 2 78 Estormal rio o e oor P M P 2 78 Reset ALG HO 2 79 Bea ii E E AA DT E E E e ER 2 80 Interprocessor TATION IG seese assein tlepiaav cada ceaansdeenreemnaelaas 2 80 Dynamically Changing I O Interrupt Configuration 2 80 EOI FRO o 2 81 Buanupt Acknowledge Baplelit seti inaina 2 81 R239 no 2 81 Cun TRE POOUUE LOB dscoettt bruta mb aant ase MER RHENUM NH MEE 2 81 p 4 c7 7 2 82 B TUUM Loos ors NE A EE E A A bobo eG POR ORO una d NA t 2 82 Rindom Read MTTr 2 85 LAI PMG ES RGAE 2 87 D 0j M M 2 80 xig ca i M HUP 2 91 VART Dis m 2 94 Lip 2 94
226. eset that affects this field EOS Error On Scrub EOS set indicates that the Harrier was scrubbing at the last single bit error logging EOS cleared indicated that the Harrier was not scrubbing ESB Error Scrub Bank ESB indicates which bank the scrubber was accessing when if the Harrier logged a scrub single bit error The following table shows the encoding Note that power up reset is the only kind of reset that affects this field Table 3 15 SDSES ESB Encoding ESB Bank 000 001 010 011 100 101 110 111 mH QQ 7m o a w SECNT Single bit Error Count This field is the single bit error counter Each time the Harrier detects a single bit error SECNT increments by one SECNt always increments on detected single bit errors regardless of whether or not error logging is enabled SECNT s rolling over from FF to 00 generates a single bit error counter 3 34 Computer Group Literature Center Web Site SDRAM Interface exception if so enabled Refer to the section titled Error Exception Enable Register on page 3 170 Note that power up reset is the only kind of reset that affects this field Note When the Harrier reports a single bit error software can use the syndrome that was logged by Harrier to determine which bit was in error The following table shows the syndrome for each possible single bit error Table 3 16 Syndrome Code Ordered by Bit in Error Bit Syndrom
227. et during normal SDRAM operation DERC Disable Error Correction When set the Harrier does not correct SDRAM single bit errors When cleared the Harrier does correct single bit errors RWCB Read Write Checkbits When set the Harrier alters SDRAM accesses so that they read write checkbit data rather than normal data When cleared the Harrier does not alter SDRAM accesses The following table gives an example Table 3 8 SDTC RWCB Example PowerPC Unaltered view of Altered view of Data Address Data RWCB set RWCB cleared Bits 0 63 Bits 0 7 Bits 8 63 00000000 00000000 Checkbits for Undefined 0000000 00000008 01234567 Checkbits for Undefined 01234567 00000010 SAAAAAAAA Checkbits for Undefined SAAAAAAAA 00000018 SBBBBBBBB Checkbits for Undefined SBBBBBBBB ENRV Enable Reset Vector When set the Harrier redirects PowerPC accesses in the reset vector address range so that they go to whichever SDRAM bank is mapped at 00000000 When cleared the Harrier does not redirect accesses in the reset vector address range SWVT Swap Vector table When set the Harrier selectively swaps the first and second 16KBytes of whichever bank of SDRAM is mapped at 00000000 When cleared the Harrier does not swap SDRAM The selection for swapping is that the Harrier swaps when 3 26 Computer Group Literature Center Web Site SDRAM Interface this bit is set and when the current PowerPC master is i
228. evice is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the STA ACKO and ENA bits in the I2COx Register and then writing the device address bits 24 30 and read bit bit 31 1 to the IZTDx Register After CMP and ACKI bits have been tested for proper response the PC master controller writes a dummy value data don t care to the I2TDx Register This causes the IC master controller to initiate a read transmission from the slave device After the C master controller has received a byte of data indicated by DIN 1 in the IZSTx Register and the CMP bit has also been tested for proper status the C master controller will respond with an acknowledge and the system software may then read the data by polling the IZRDx Register As long as the slave device receives an acknowledge it will continue to increment the word address and serially clock out sequential data words The rc sequential read operation is terminated when the PC master controller does not respond with an acknowledge This can be accomplished by setting only the ENA bit in the I2COx Register before receiving the last data word A stop sequence then must be transmitted to the slave device by first setting the STP and ENA bits in the IZCOx Register and then writing a dummy data data don t care to the IZTDx Register The I2STx Register must now be polled to test CMP bit for the operation complete http www
229. f a particular memory area on the PowerPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PowerPC address END End Address This field determines the end address of a particular memory area on the PowerPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PowerPC address http www motorola com computer literature 3 47 Programming Model Outbound Translation Offset Translation Attribute 3 Registers Offset XCSR 23C Bit Name d e od a C lt gggggqa Jgd Function Address Translation Operation Reset R W XCSR FEFF0000 gt 8000 XCSR FEFF1000 gt 7F80 XCSR FEFF2000 gt 7F00 XCSR FEFF3000 gt 7E80 3 48 The Outbound Translation Offset Register 3 OTOF3 contains offset information associated with the mapping of PCI I O space to PowerPC memory space The OTOF3 field represents a 16 bit offset that is added to the upper 16 bits of the PowerPC address to determine the PCI address used for outbound transfers This offset allows PCI resources to reside at addresses that would not normally be visible from the PowerPC bus The Outbound Translation Attribute Register 3 OTAT3 contains attribute information associated with the mapping of PCI I O space to PowerPC memory space The fi
230. f cleared a prefetching will resume once the FIFO is completely empty Please refer to the section titled FIFO Tuning on page 2 41 for more information http www motorola com computer literature 3 73 Programming Model 3 74 RMS Read Multiple Size Functionally this field is the same as the RXS field except that this is the virtual fifo size that is applied during PCI Read Multiple command types Please refer to the section titled FIFO Tuning on page 2 41 for more information RMT Read Multiple Threshold Functionally this field is the same as the RXT field except that this is the threshold that is applied during PCI Read Multiple command types Please refer to the section titled FIFO Tuning on page 2 41 for more information GBL Global If set the GBL_ pin will be asserted for each PowerPC transaction indicating the transaction may be snooped by the processor If cleared the GBL_ pin is not asserted and the transaction is not snooped CWEF Cache line Write Flush When set forces the use of Write with Flush transfer types during cache line writes Forces the processor to perform copyback writes during snoop hits When cleared forces Write with kill transfer type during cache line writes Forces the processor to simply invalidate cache lines during snoop hits Used as a work around for processors that can not handle Write with kill correctly Please refer to the following table for the transfer codes associated with this bit C
231. fined as follows SCWE Scrub Write Enable When set the Harrier writes corrected data during scrubs that detect single bit errors When cleared the Harrier does not write during scrubs Note that power up reset is the only kind of reset that affects this bit SCCNT Scrub Counter SCCNT increments each time the Harrier completes a scrub of the entire SDRAM array When SCCNT reaches 3 it rolls over to 0 and continues Note that power up reset is the only kind of reset that affects this field SCPA Scrub Prescaler Adjust SCPA determines the Harrier s scrub rate by setting the roll over count for the scrub prescale counter Each time the Harrier performs a refresh burst the scrub prescale counter increments by one When the scrub prescale counter reaches the value stored in SCPA it clears and resumes counting from 0 Note that when SCPA is all 0 s the scrub Prescale counter does not increment which disables scrubs from occurring Since SCPA clears to 0 s at power up reset scrubbing comes up disabled until software programs a non zero value into SCPA Power up reset is the only kind of reset that affects this field 3 32 Computer Group Literature Center Web Site SDRAM Interface SDRAM Scrub Address Counter XCSR 134 Name Function SDRAM Operation R W Scrubbing Reset 00000000 P ad The SDRAM Scrub Address Counter SDSA provides the scrub address fo
232. following side affects a The associated bit in the Interrupt Pending Register is cleared a The In Service register is updated The fields within the POIA C P11IAC registers are defined as follows VECTOR Vector This vector is returned when the Interrupt Acknowledge register is read Processor O Processor 1 End Of Interrupt Registers Offset Bit Name Operation POEOI XMPI 200B0 P1EOI XMPI 210B0 POEOI P1EOI EOI Reset 3 130 R R R R w 00 00 00 0 0 The Processor 0 Processor 1 End Of Interrupt Registers POEOI and P1EOD are used to declare the end of an interrupt Two processors are supported with each processor owning an End Of Interrupt register The field within the POEOI P1EOI registers is defined as follows EOI End of Interrupt EOI Code values other than 0 are currently undefined Data values written to this register are ignored zero is assumed Writing to this register signals the end of processing for the highest priority interrupt currently in service by the associated processor The write operation will update the In Service register by retiring the highest priority interrupt Reading this register returns Zeros Computer Group Literature Center Web Site I2C Controller lC Controller All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group I C Clock Prescaler Register Offset XCSR
233. from the source address field of the current descriptor DMA Source Attribute Register Offset XCSR 264 Bit Function Operation Reset A gt E cac cac o 9g g 99g eG coc The DMA Source Attribute Register DSAT contains the source attributes for a DMA transfer Not all fields are used for all transfer types Fields that do not pertain to a particular transfer type are ignored User software must program this register when performing Direct Mode transactions When performing Linked List Mode transactions this register is automatically loaded from the source attribute field of the current descriptor The fields within the DSAT register are defined as followed Computer Group Literature Center Web Site DMA Controller TYP Type This field indicates the type of source to be used for a DMA transfer Different fields within the DSAT register are used depending on the type of source selected The table below shows the different source types and the associated fields within the DSAT register that apply Table 3 31 DSAT TYP Encoding TYP DMA Applicable Fields Source NIN PSZ CRI GBL 00 PowerPC bus 01 PCI Bus X Ix Data Pattern X X NIN No Increment If set source increment will be disabled during a DMA transfer If a PCI bus source is selected then the source address will not be incr
234. full compliance with PCI Local Bus Specification 2 1 Computer Group Literature Center Web Site PowerPC to PCI Bridge When the FBR bit within the BXCS register is set the Harrier handles outbound read transactions in the following manner 4 Outbound write posted transactions are flushed by the nature of the FIFO architecture The Harrier holds the processor with wait states until the outbound FIFO Outbound FIFO is empty 4 Inbound write posted transactions are flushed as a result of a decision by the PPC Slave to accept or reject a read transaction When the PPC Slave is asked to service an outbound read transaction the read is only accepted if there is no inbound write posted activity A non zero value on the inbound FIFO Inbound FIFO count is considered write posted activity If the read may not be accepted the PPC Slave issues a retry to the processor When the FBR bit within the BPCS register is set the Harrier processes inbound read transactions in the following manner 4 Inbound write posted transactions are flushed by the nature of the FIFO architecture The Harrier holds the PCI Master with wait states until the inbound FIFO Inbound FIFO is empty 4 Outbound write posted transactions are flushed as a result of a decision by the PCI Slave to accept or reject a read transaction When the PCI Slave is asked to service an inbound read transaction the read will only be accepted if there is no outbound write posted activit
235. gister is set to prevent the Harrier from updating EPAD and EPAT registers in the event of additional errors Thus the information related to the first erroneous transaction is latched until the error status bit is cleared by writing to EECL register http www motorola com computer literature 2 127 Functional Descriptions 2 128 The Harrier memory controller supports ECC for correcting single bit errors and detecting double bit errors In the event of a memory controller single bit error or single bit error count overflow the corresponding SDRAM error status bit will be set in the EEST register if the corresponding error is enabled EEEN register any other SDRAM single bit error status bit is not set In addition the Harrier will update SDSES and SDSEA registers in the case of an SDRAM single bit error In the case any SDRAM single bit error detected while any other SDRAM single bit error status bit is already set the SDRAM single bit overflow EEST SSOF bit will be set in the EEST register and further logging of SDRAM single bit errors is suspended until software clears the first error and the EEST SSOF bit In the event of a memory controller multi bit error on PowerPC access or multi bit error on a scrub the corresponding SDRAM error status bit will be set in the EEST register if the corresponding error is enabled EEEN register any other SDRAM multi bit error status bit is not set In addition the Harrier will update SDMES and SDME
236. grant PowerPC bus arbitration a All transactions are cache word aligned a Default FIFO threshold settings Computer Group Literature Center Web Site PowerPC to PCI Bridge 4 Clock counts represent best case alignment between PCI and PowerPC clock domains An exception to this is continuous bandwidth which reflects the average affects of clock alignment http www motorola com computer literature 4 11 Performance 4 12 Computer Group Literature Center Web Site Programming Considerations Programming SDRAM Related Control Registers The following subsections contain information that is helpful in programming a system that uses the Harrier ASIC Initializing SDRAM Related Control Registers In order to establish proper SDRAM operation software must configure control register bits that affect each SDRAM bank s speed refresh period size base address and enable The SDRAM speed attributes are the same for all banks and are controlled by one register The same is true for the refresh period On the other hand the size base address and enable can be different for each bank and are controlled in bank specific registers SDRAM Speed Attributes The SDRAM speed attributes come up from power up reset initialized to the slowest settings capable by Harrier This allows SDRAM accesses to be performed before the SDRAM speed attributes are known An example of a need for this is when software requires some working memory that
237. gtet sisincicascsasncassrsnaasccsecocacceacetsnssasaansaacdous 3 197 desi dre d 00 uo nna T 3 198 Miscellaneous Control and Status Kegistet iiiue ie etit terrre nnns 3 199 eco Mura M Rep Biot SNR AREAREN IREE ARa 3 200 Cresieral Purpose oui 3 201 CHAPTER4 Performance SORAW r o 4 1 Eris 420 300 TT 4d Latency of Xport bound Reads Xport read bursting disabled 4 5 dulcia nri 4 6 lu cg Ao PET PUI emm 4 8 R bound PorTODIBUDE soes e iea aiK a SSDD 4 9 CHAPTER5 Programming Considerations Programming SDRAM Related Control Registers eseeeeeeeeeeereseereereerrerrsessresrees 5 1 Initializing SDRAM Related Control Registers aont rte btt tatis 5 1 SDRAM Specd ADOBUIBRL aiia cre EEPUAMPIbRA bM MAUS Aa E 5 1 SPRAM Beer Feri c 5 1 SDRAM Ko e 5 2 4 23541 E 5 2 SDRAM Base Address and Enable sss uir kbb Odi PIS PP Ep tA turc nc kia l E 5 2 SDRAM Control Registers Initialization Example 5 3 Optional Method for Sizing SDRAM sirsiran 5 9 Spee FITNA a ea 5 13 APPENDIX A Related Documentation Motorola Computer Group Douei S reserare ear rwrtaiaibonanod an an Pponde A 1 Manulacturers Documents sme i ut pe an nni E te inne a Hi uM E A 2 Related Specifications udscbcleiticbtiada bib reb M uFEER ELDER I QAM CURL Pak Za
238. gy The following figure is a high level view that demonstrates the difference between the naming conventions of Outbound and Inbound traffic on a board using the Harrier ASIC Review the figure in conjunction with the text in the following paragraph f Outbound Traffic l Master Lr DE Ti Target OO Inbound Traffic Traffic um Target es a EN Master PowerPC Bus Domain PCI Bus Domain Figure 2 4 Harrier PowerPC PCI Data Flow Naming Convention The Outbound and Inbound naming convention relates to the direction of command information with respect to the PowerPC bus A transaction that originates from the PowerPC bus and is bound for the PCI bus is considered Outbound traffic Conversely a transaction that originates from the PCI bus and is bound for the PowerPC bus is considered Inbound traffic http www motorola com computer literature 2 11 Functional Descriptions Block Diagram 2 12 A functional block diagram of Harrier s PowerPC to PCI Bridge is shown in Figure 2 5 on page 2 13 The control logic is subdivided into the following functions PPC Master PPC Slave PCI Master and PCI Slave The data path logic is subdivided into the following functions Outbound FIFO Inbound FIFO PPC Input PCI Input PPC Output and PCI Output Address decoding is handled in the PPC Decode and PCI Decode blocks The control register logic is contained in the PPC Registers and PCI Registers blocks The clock p
239. h XCSR XPAT1 DW 01 16 Bit Width 10 32 Bit Width 11 16 Bit Width Hawk compatibility mode Xport Channel 1 as Reset XAD 6 Disabled 1 Vector Source 1 Enabled Only if Channels 2 3 are Disabled Xport Channel 2 Data XAD 5 4 8 Bit Width 1 Width XCSR XPAT2 DW 16 Bit Width 32 Bit Width 16 Bit Width Hawk compatibility mode Xport Channel 2 as Reset XAD 3 Disabled 1 Vector Source Enabled Only if Channel 3 is Disabled Xport Channel 3 Data XAD 2 1 8 Bit Width 1 Width XCSR XPAT3 DW 16 Bit Width 32 Bit Width 16 Bit Width Hawk compatibility mode Xport Channel 3 as Reset XAD 0 Disabled 1 Vector Source 1 Enabled 2 136 Computer Group Literature Center Web Site Hardware Configuration PURST XAD 30 0 Figure 2 34 Power Up Reset Timing Timing Group 1 http www motorola com computer literature 2 137 Functional Descriptions 2 138 Computer Group Literature Center Web Site Programming Model Architectural Overview The Harrier ASIC offers a variety of resources to the PowerPC and PCI address spaces The placement and sizing of these resources is highly flexible allowing the Harrier to support an unlimited number of possible resource mapping schemes The figure below summarizes all of the resources offered by the Harrier Table 3 1 Harrier PowerPC and PCI Resources Address Resource Size Relocation Page Space Options Mec
240. hanism PowerPC Control and KBytes One of four Determined at 3 3 Status Registers selectable base power up reset by XCSR addresses sampling RD x y FEFF0000 pins SFEFF1000 FEFF2000 FEFF3000 SDRAM Banks Variablefrom Any integer SDRAM Bank 3 30 A thru H 32MB to multiple of the Addressing 2GB corresponding registers SDBAx bank size within SDRAM Interface function of XCSR PCI Memory or Variable in Any 64K Byte Outbound 3 19 IO Space Ports multiples of boundary in Translation 0 thru 3 64K Byte PowerPC space registers OTADx translated to any and OTOFx 64K Byte within PowerPC boundary in PCI to PCI Bridge space function of XCSR 3 1 Programming Model Table 3 1 Harrier PowerPC and PCI Resources Continued Address Resource Size Relocation Page Space Options Mechanism PCI Entire Fixed None 3 19 Configuration Configuration CONFIG ADDR Space Space and XCFS CONFIG DATA registers within port 3 to PCI IO space MPIC 256 KBytes Any 256K Byte MBAR register 3 14 XMPI boundary within MPIC function of XCSR Xport Variable in Any integer XPARx XPATx 3 150 Channels multiples of multiple of the registers within 0 thru 3 64KBytes corresponding Xport function of device size down XCSR to 64KBytes PCI Configuration 256 Bytes Any Device IDSEL pin 3 21 Space Number PCFS PowerPC Variable Any Inbound 3 21 Memory Space binary corresponding Translation Ports 0 thru 3 progression bloc
241. hasing and reset control logic is contained within the PPC PCI Clock block The FIFO structure has been designed to allow independent data transfer operations to occur between inbound and outbound transactions The Outbound FIFO is used to support outbound transactions while the Inbound FIFO is used to support inbound transactions Both the Outbound FIFO and the Inbound FIFO support a command path a read data path and a write data path The split between read and write data paths allow Harrier to accept posted write transactions while servicing delayed read transactions The data paths also include logic to handle the PowerPC PCI Endian function All outbound transactions use the PPC Slave and PCI Master functions for maintaining bus tracking and control During both write and read transactions the PPC Slave places command information into the Outbound FIFO The PCI Master draws this command information from the Outbound FIFO when it is ready to process the transaction During write transactions write data is captured from the PowerPC bus within the PPC Input block This data is fed into the write data path of the Outbound FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus During read transactions read data is captured from the PCI bus within the PCI Input block From there the data is fed into the read data path of the Outbound FIFO The PPC Output block removes the data from the FIFO and presents it to the
242. he initialization http www motorola com computer literature 5 13 Programming Considerations 5 14 Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual You can obtain paper or electronic copies of Motorola Computer Group publications by 4 Contacting your local Motorola sales office a Visiting Motorola Computer Group s World Wide Web literature site http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Publication Number PrPMC800 Processor PMC Installation and Use PRPMC800A IH PrPMC800 Programmer s Reference Guide PRPMC800A PG PPCBug Firmware Package User s Manual Parts 1 and 2 PPCBUGAI UM PPCBUGA2 UM PPCBug Diagnostics Manual PPCDIAA UM To obtain the most up to date product information in pdf or html format visit our web site at http www motorola com computer literature A Manufacturers Documents Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 2 Manufacturers Documents Publication Document Title and Source Number PowerPC750 RISC Mi
243. he CPUs and is not implemented on either HARR or EXTL The parking options include parking on CPUO parking on CPUI parking on the last CPU or parking disabled Computer Group Literature Center Web Site Arbiters There are various system level debug functions provided by the PPC Arbiter The PPC Arbiter has the optional ability to flatten the PowerPC bus pipeline Flattening can be imposed uniquely on single beat reads single beat writes burst reads and burst writes It is possible to further qualify the ability to flatten based on whether there is a switch in masters or whether to flatten unconditionally for each transfer type This is a debug function only and is not intended for normal operation PCI Arbiter The Harrier has an optional internal PCI Arbiter The arbiter can support up to 8 PCI masters including the Harrier and 7 other external PCI masters The arbiter can be configured to be enabled or disabled at reset time by strapping the XAD 18 bit either high for enabled or low for disabled The table below describes the pins and its function for both modes Table 2 17 PCI Arbiter Pin Description External Arbiter Internal Arbiter Pin Name Direction Function Direction Function PARBIO Input ext reqO input HARR gnt PARBII ext req1 Input PARBD ext req2 PARBI3 ext req3 PARBIA ext req4 PARBIS extreq5 PARBI6 ext req6 PARBOO Tristate ext gnt0_ PARBOI Output Tristat
244. he EEST PMR status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check PPE PCI PERR If the EEST PPE status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check SSE SDRAM Memory Controller Single Bit Error If the EEST SSE status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check SSC SDRAM Memory Controller Single Bit Error Count Overflow If the EEST SSC status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access If the EEST SMX status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check SMS SDRAM Memory Controller Multi Bit Error on Scrub If the EEST SMS status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check XBT PowerPC Bus Time out If the EEST XBT status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check XAP PowerPC Bus Address Parity Error If the EEST X AP status bit is set writing a one to this field will clear the status bit and the associated interrupt or machine check XDP PowerPC Bus Data Parity Error If the EEST XDP status bit is
245. he Transmitter Holding or the Interrupt Enable Register SB Set Break This bit causes a break condition to be transmitted to the receiving UART When it is set to a logic 1 the serial output SOUTx is forced to the logic 0 state The break is disabled by setting this bit to a logic 0 SP Stick Parity When this bit is set to a logic 1 the parity bit is forced into a defined state as follows If EPS 1 and PEN 1 the parity bit is transmitted and checked as a logic O If EPS 0 and PEN 1 the parity bit is transmitted and checked as a logic 1 EPS Even Parity Select When EPS 0 and PEN 1 an odd number of ones is transmitted or checked When EPS 1 and PEN 1 an even number of ones is transmitted or checked PEN Parity Enable When this bit is set to logic 1 a parity bit is generated transmit data or checked receive data between the last data word bit and stop bit of the serial data STB Number Of Stop Bits When this bit is set to logic 1 two stop bits are added after each transmitted character unless the character length is 5 then only one and a half stop bits are added When this bit is set to logic 0 one stop bit is always added Note that only transmitted stop bits are programmable The receiver checks only the first stop bit so this bit has no effect when the UART receives the data http www motorola com computer literature 3 141 Programming Model WLS1 0 Word Length Select These two bits spe
246. he first Linked List Mode descriptor When continuing a Linked List Mode transaction the register is automatically loaded from the next link address field of the current descriptor The fields within the DNLA register are defined as follows NLA Next Link Address This is the address of the next descriptor when using Linked List Mode This is a PowerPC address and is presented in 32 byte cache line resolution http www motorola com computer literature 3 89 Programming Model LLA Last Link Address If set the current descriptor will be the last descriptor of a Linked List transaction If cleared the current descriptor will not be the last descriptor DMA Count Register Offset XCSR 274 Bit c 4 dede d N od o g x qd N od o g Function Name DCNT DMA Operation R W Reset 00000000 The DMA Count Register DCNT contains the byte count for a DMA transfer Note that a count of all zeros represents the maximum count of 4 GBytes User software must program this register when performing Direct Mode transactions When performing Linked List Mode transactions this register is automatically loaded from the count field of the current descriptor DMA Current Source Address Register Offset XCSR 280 Bit Function Name Operation Reset 00000000 The DMA Current Source Address Register DCSA is a read only register that contains the current source address for a DMA transfer If the source is P
247. hen clear the contents of the I2COx Register and further writes to the I2COx Register will not be allowed until after the I2STx Register is read A read from the I2STx Register will clear this bit ACKI Acknowledge In This bit is set if the addressed slave device is acknowledged to either start sequence or data writes from the PC master controller and cleared otherwise The C master controller will automatically clear this bit at the beginning of the next valid PC operation CMP Complete This bit is set after the PC master controller has successfully completed the requested PC operation and cleared at the beginning of every valid re operation This bit is also set after power up Computer Group Literature Center Web Site I C Receiver Data Register I2C Controller Dc Offset XCSR 19C XCSR 1BC ee CE GER GEG EEGEEEEE EEEEGGEG GGEGGEG Ditis Name I2RDO I2RDI Operation R R R R Reset 00 00 00 00 The I2C Receiver Data Register IZRDx contains the receive byte for PC data transfers During PC sequential read operation the current receive byte must be read before any new one can be brought in A read of this register will automatically clear the DIN bit in the I2STx Register http www motorola com computer literature 3 135 Programming Model UART Controller All of the registers for this function are located within PowerPC address space as a part of the XCSR Register Group and only aligned rea
248. hen set the CMP bit in the I2STx Register STP Stop When set the PC master controller generates a stop sequence on the C bus on the next dummy write data don t care to the I2TDx Register and clears the CMP bit in the I2STx Register After the stop sequence has been transmitted the PC master controller will automatically clear the STP bit and then set the CMP bit in the IZ2STx Register ACKO Acknowledge Out When set the IC master controller generates an acknowledge on the PC bus during read cycles This bit should be used only in the PC sequential read operation and must Computer Group Literature Center Web Site I2C Controller remain cleared for all other PC operations For PC sequential read operation this bit should be set for every single byte received except on the last byte in which case it should be cleared ENA Enable When set the I C master interface will be enable for PC operations If clear reads and writes to all PC registers are still allowed but no PC bus operations will be performed I C Transmitter Data Register Offset XCSR 18C XCSR 1AC irri qq Name I2TDO DC I2TD1 Operation R R R R W Reset 00 00 00 00 The I2C Transmitter Data Register I2TDx contains the transmit byte for IC data transfers If a value is written to ILTDx when the STA and ENA bits in the I2COx Register are set a start sequence is generated immediately followed by the transmission of the contents of
249. hen set the Harrier will assert its TBENI pin RSTOUT RESET OUT When a one is written to this bit the Harrier will assert its reset out RSTO pin ASWS Abort Switch Status This bit reflects the state of the ABTSW pin This bit is a one when the Abort Switch is pressed RSTINH Reset Inhibit When this bit is set the Harrier will inhibit asserting its reset out RSTO pin when RSTSW_ pin is asserted General Purpose Registers Offset GPRGO0 XCSR 020 GPRG1 XCSR 024 GPRG2 XCSR 028 GPRG3 XCSR 02C GPRG4 XCSR 030 GPRGS XCSR 034 Bt dl444444434d4d34343244842448934384 Name GPRGx General Operation R W Purpose Registers Reset GPRGO gt GPRG3 00000000 GPRGA gt GPRGS5 00000000 P The General Purpose Registers GPRG0 GPRG1 GPRG2 GPRG3 GPRG4 and GPRGS are provided for inter process message passing or general purpose storage They do not control any hardware Register groups GPRG0 GPRG1 GPRG2 GPRG3 and GPRG4 GPRGS5 and may be combined as single 64 bit registers GPRG0 thru GPRG3 will always be reset to all zeros following a power up reset or a local reset GPRG4 and GPRGS5 are only affected by power up reset A local reset will not change the contents of these registers therefore these registers may be used for storing critical information when performing commanded reset cycles 3 200 Computer
250. hical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts lt Enter gt lt Return gt or lt CR gt CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d Bus Naming The names PowerPC and 60x are used interchangeably throughout this document Note All references to PowerPC bus support via the Harrier ASIC are specifically related to the 60x bus mode and is not intended to imply support of any other PowerPC bus mode Bit Ordering The bit ordering convention for Harrier depends on which bus group a signal belongs All busses or bit fields relating to the PowerPC bus use Big Endian bit ordering 02MSB All remaining busses and bit fields use Little Endian bit ordering 02LSB Register and Bit Naming A register consists of a collection of 8 16 24 or 32 bits Some or all of the bits within a register are specifically defined while the remaining bits are undefi
251. hin PowerPC address space as a part of the XCSR Register Group For a functional description refer to the earlier section on Xport in this manual Xport Address Range 0 1 2 3 Registers Offset Bit XPARO XCSR 150 XPARI XCSR 158 XPAR2 XCSR 160 XPAR3 XCSR 168 J o ed o 9 i 19 o ca oj oO i oc o O a Function Name XPAR Xport STA END Operation R W R W Reset 0000 0000 3 150 The Xport Address Range Registers XPARO XPAR1 XPAR2 and XPAR3 define the PowerPC address ranges to which each of Xport channels 0 1 2 and 3 will respond The fields within the XPA Rx registers are defined as follows STA Starting Address This field defines the beginning of the address range The Harrier compares STA to the 16 upper PowerPC address signals END Ending Address This field defines the ending of the address range The Harrier compares END to the 16 upper PowerPC address signals Note that each channel s Address Range Register should be programmed so that its Xport Bus devices appear at an integer multiple of the size of the largest device on the channel This mapping is required because the Harrier performs no address translation between the PowerPC and Xport buses Computer Group Literature Center Web Site Xport Xport Attributes 0 1 2 3 Registers Offset XPATO XCSR 154 XPAT1 XCSR 15C XPAT2 XCS
252. hine check to processor 0 will not be generated PAP PCI Address Parity Error If set a machine check to processor 0 will be generated whenever the EEST PAP bit is asserted If cleared a machine check to processor 0 will not be generated PDP PCI Data Parity Error If set a machine check to processor 0 will be generated whenever the EEST PDP bit is asserted If cleared a machine check to processor 0 will not be generated PDT PCI Bus Delayed Transaction Time out If set a machine check to processor 0 will be generated whenever the EEST PDT bit is asserted If cleared a machine check to processor 0 will not be generated http www motorola com computer literature 3 183 Programming Model 3 184 PSE PCI SERR If set a machine check to processor 0 will be generated whenever the EEST PSE bit is asserted If cleared a machine check to processor 0 will not be generated PPE PCI PERR If set a machine check to processor 0 will be generated whenever the EEST PPE bit is asserted If cleared a machine check to processor 0 will not be generated PMR PCI Master Retry If set a machine check to processor 0 will be generated whenever the EEST PMR bit is asserted If cleared a machine check to processor 0 will not be generated SSE SDRAM Memory Controller Single Bit Error If set a machine check to processor 0 will be generated whenever the EEST SSE bit is asserted If cleared a machine check to processor 0 will not be genera
253. his bit is set during single beat transfers TSIZx Transfer Size This field contains the transfer size of the PowerPC transfer in which the Error Exception occurred TTx Transfer Type This field contains the transfer type of the PowerPC transfer in which the Error Exception occurred Error Diagnostics PCI Address Register Offset XCSR 078 Bit 4 44444444234 4342232844848358589 33585 Function Name EPAD Error Operation R Diagnostics Reset 00000000 The Error Diagnostics PCI Address Register EPAD captures addressing information from the PCI bus whenever an applicable Error Exception has been detected The register contents will only be updated when there are no status bits set within the EEST register During a string of successive errors this register will retain information pertaining to the first error http www motorola com computer literature 3 191 Programming Model Error Diagnostics PCI Attribute Register Offset XCSR 07C Bit Function Name Error Diagnostics Operation Reset The Error Diagnostics PCI Attribute Register EPAT captures attribute information from the PCI bus whenever an applicable Error Exception has been detected The register contents will only be updated when there are no
254. hows NXB for the different port widths and PowerPC transfer sizes Note that the table is for accesses that are aligned to the port size Some accesses that are not aligned to port size add 1 beat to the number shown in the table Table 4 3 Number of Xport Data Beats for Different PowerPC 60x Transfer Sizes 60x 8 Bit Xport Channel 16 Bit 32 Bit Transfer Size Width Beat 2 Beats Xport Channel Width Beat Beat Xport Channel Width Beat Beat 2 Bytes 3 Bytes 4 Beats 2 Beats Beat 3 Beats 5 Beats 2 Beats 3 Beats Beat 2 Beats 5 Bytes 6 Bytes 6 Beats 7 Beats 8 Beats 3 Beats 4 Beats 4 Beats 2 Beats 2 Beats 2 Beats 8 Bytes 32 Bytes 32 Beats http www motorola com computer literature 16 Beats 8 Beats 4 7 Performance PowerPC to PCI Bridge This section describes the differences between 32 bit and 64 bit outbound and inbound performance Table 4 4 Outbound Performance Matrix Transaction 32 bit PCI 64 bit PCI Clock Latency PPC Clocks Continuous Latency PPC Clocks Continuous Ratio Best Case Bus Idle MUS Best Case Bus Idle E Burst Write 5 1 1 1 5 1 1 1 133 267 5 2 Burst Read 42 1 1 1 42 1 1 1 133 267 Single Write 5 3 Single Read 26 33 Burst Write 5 1 1 1 5 1 1 1 267 533 3 2 Burst Read 28 1 1 1 33 1 1 1 267 533 Single Write 5 5 Single
255. i purpose four channel expansion port that can be used to connect Flash ROM or various peripheral devices to the Harrier ASIC Arbiters This functional block contains a PowerPC and a PCI arbiter Each arbiter offers a wide range of programmable options allowing the system designer to fine tune system configurations for the maximum level of performance If desired external arbitration can be selected for either or both arbiters Watchdog Timers This functional block offers two completely independent watchdog timers The use of these timers is optional These timers are designed to increase the integrity of software execution An output pin is associated with each timer allowing the timer to create virtually any system exception such as interrupt reset machine check etc http www motorola com computer literature 1 5 Introduction 1 6 Error Diagnostics This functional block contains support logic that helps capture information related to various system errors Programmable options exist that enable the system error to assert various forms of interrupt exceptions PowerPC Address Bus Timer This is a timer function that makes it possible for software to recover after an erroneous PowerPC access It contains PowerPC bus tracking logic that detects non responsive address tenures Once detected the address and data tenures are automatically closed and an exception is generated PowerPC Parity This functional block can generate a
256. if the EEEN XDT is enabled and all other PowerPC error status bits are cleared If the EEINT XDT is set a processor interrupt will be generated If the EEMCKO XDT is set a machine check to processor 0 will be generated and if the EEMCK1 XDT is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL XDT bit POF PCI Error Overflow This bit is set when any PCI error is detected and any of the PCI error status bits is already set SSOF SDRAM Memory Controller Single Bit Error Overflow This bit is set when any SDRAM Memory Controller single bit error is detected and any of the SDRAM Memory Controller single bit error status bits is already set SMOF SDRAM Memory Controller Multi Bit Error Overflow This bit is set when any SDRAM Memory Controller multi bit error is detected and any of the SDRAM Memory Controller multi bit error status bits is already set XOF PowerPC Error Overflow This bit is set when any PowerPC error is detected and any of the PowerPC error status bits is already set http www motorola com computer literature 3 177 Programming Model Error Exception Clear Register Offset XCSR 058 Bit 4444444443433343433284444453 89444 Function Name EECL Exceptions PMA PTA sis PSE PPE YELE XBT 3 XDP XD PO SSOF Operation R C dd R C R C a8 g gY a goog
257. ified in units of PCI clock periods The table below shows the encoding for this field Table 3 30 DCTL PBT Encoding PBT Back off Value PCI Clock Approx Time Approx Time Counts 33 MHz 66 MHz 000 0 0 000 us 0 000 us 001 32 0 960 us 0 480 us 010 64 1 920 us 0 960 us 011 128 3 840 us 1 920 us 100 256 7 680 us 3 840 us 101 512 15 360 us 7 680 us 110 1024 30 720 us 15 360 us 111 2048 61 440 us 30 720 us CSE Copy back Snarfing Enable This field is used to enable snarfing on a processor s copy back cycle Refer to the section titled Copyback Snarfing on page 2 35 for more information If set copy back snarfing is attempted for PowerPC DMA cycles If cleared snarfing will not be attempted CRI Cache line Read Invalidate If set the DMA will use the Read with intent to modify transfer type during PowerPC descriptor fetch read cycles This will force processor cached data in the E and S states to be invalidated during snoop hits If cleared the DMA will use the Read transfer type This will allow the processor to retain cached data in the E and S states GBL Global If set the DMA will assert the GBL_ pin during PowerPC descriptor fetch read cycles This allows the processor to snoop the DMA transfer If cleared the GBL_ pin is not asserted and the processor will not be able to snoop the DMA transaction 3 80 Computer Group Literature Center Web Site DMA Controller DMA Statu
258. igure 2 16 IMU Queene SMI siateccsiresnsenneessvnessnenshenssencteecebossssecssaelavdecedsctaceexe 2 64 Fieu S MPIC Block Tiag rani idan ede 2 74 Figure 2 18 Programming Sequence Tor I2C Byte Write Lieu npnes 2 84 Figure 2 19 Programming Sequence for I2C Random Read 2 86 Figure 2 20 Programming Sequence for I2C Current Address Read 2 88 Figure 2 21 Programming Sequence for I2C Page Weise trita 2 90 Figure 2 22 Programming Sequence for I2C Sequential Read 2 93 Figure 2 23 Xport Block Diagrami oreet irisean eeii RI td qud rnb ER ERA 2 95 Figure 2 24 Xport Bus One Beat Read Transaction eese eseniseertkeneet cesta eua 2 08 Figure 2 25 Xport Bus Two One beat Write Transactions sss 2 09 Figure 2 26 Xport Bus Two Beat Read Transaction No Bursting 2 100 Figure 2 27 Xport Bus 4 beat Read Transaction with Burst Size of 4 2 101 Figure 2 28 Xport Bus 3 beat Write Transaction with Burst Size of 4 2 102 Figure 2 29 Xport Bus 8 beat Read Transaction with Burst Size of 4 2 103 Figure 2 30 Xport Bus One Beat Read Transaction in Basic Mode 2 104 Figure 2 31 Xport Bus One Beat Write Transaction in Basic Mode 2 104 XV xvi Figure 2 32 Xport Bus One Beat Read Transaction in Hawk Omens no eT 2 105 Figure 2 33 Xpor
259. imer Test Bit 1 This bit is used for testing purposes only When set the sampling rate of the switch debouncers will change from lms to lus TMRT 2 Timer Test Bit 2 This bit is used for testing purposes only When set the RSTO pulse extender will change from 100us to lus TMRT 3 Timer Test Bit 3 This bit is used for testing purposes only When set the valid hold time for the push button RSTSW signal will be 3us instead of 3s and the RSTO signal will be generated upon the completion of that valid hold time PMRT PCI Master Retry Test Bit This bit is used for test reasons to reduce the amount of PCI master retries needed before generating the PCI Master Retry exception Setting this bit puts the PCI master in test mode PDTT PCI Delayed Transaction Test Bit This bit is used for test reasons to impose a short PCI delayed transaction time out A short PCI delayed transaction time out will occur when this bit is set Error Diagnostics PowerPC Address Register Offset XCSR 070 Bit E Function Name EXAD Error Operation R Diagnostics Reset 00000000 The Error Diagnostics PowerPC Address Register EXAD captures addressing information from the PowerPC bus whenever an applicable Error Exception has been detected The register contents will only be updated when there are no status bits set within the EEST register During a string of successive errors this register will retain information pertaining t
260. internal interrupts are passed on to the MPIC If the MCSR OPI bit is cleared the Harrier internal interrupts are passed directly to the processor 0 interrupt pin IRQO CSR s Readability Unless explicitly specified all registers are readable and return the last value written The exceptions are the IPI dispatch registers and the EOI registers which return zeros on reads the interrupt source ACT bit which returns current interrupt source status the interrupt acknowledge register which returns the vector of the highest priority interrupt which is currently pending and reserved bits which returns zeros The interrupt acknowledge register is also the only register which exhibits any read side effects Interrupt Source Priority Each interrupt source is assigned a priority value in the range from 0 to 15 where 15 is the highest In order for delivery of an interrupt to take place the priority of the source must be greater than that of the destination processor Therefore setting a source priority to zero inhibits that interrupt Processor s Current Task Priority Each processor has a current task priority register which is set by system software to indicate the relative importance of the task running on that processor The processor will not receive interrupts with a priority level http www motorola com computer literature 2 69 Functional Descriptions equal to or lower than its current task priority Therefore setting the current tas
261. ion 4 Xport Static RAM style control address and data signals 4individually programmable channels Programmable access time Programmable data widths of 8 16 or 32 bits Intended devices include Flash ROM External Control Registers and FIFO s 4 Supports synchronous PowerPC PCI clock ratios of 5 2 3 2 3 1 2 1 and 1 1 4 Voltage 2 5V power supply for I O s and internal core 3 3V power supply for I O s a 720 pin flip chip package http www motorola com computer literature 1 3 Introduction SDRAM PowerPC Bus Memory Interface Flash ROM Peripherals etc Harrier Auxiliary PowerPC PowerPC PowerPC Processor Processor Master ASIC PCI Bus Master Master Master Master and or and or and or and or Slave Slave Slave Slave Device Device Device Device Figure 1 1 Typical Harrier System Implementation Functional Blocks of Harrier 1 4 The following paragraphs describe the major functional blocks contained in the Harrier ASIC Figure 1 2 is a block diagram of these major elements SDRAM Interface This functional block is a high performance PowerPC to SDRAM memory interface It provides PowerPC masters with exceptional bandwidth and low latency connections to system memory PowerPC to PCI Bridge This functional block provides an interface between the PowerPC bus and a 33 MHz 66 MHz PCI bus It supports either 32 bit or 64 bit data
262. ion Intel Corporation http developer intel com design network datashts 738259 htm 3 Volt Intel Strata FLASH Memory 28F128J3A Web Site http developer intel com design flcomp prodbref 298044 htm TL 16C550C UART SLLS177C Texas Instruments P O Box 655303 Dallas Texas 75265 Web Site http www ti com ATMEL Nonvolitile Memory Data Book AT24Cxx Must request documentation at AT93CV6 http www atmel com atmel support 3 Volt Intel StrataFlash Memory 28F128J3A 290667 005 Web Site http developer intel com design flcomp prodbref 298044 htm http www mcg mot com literature A 3 A A Related Specifications Related Specifications Table A 3 lists the product s related specifications The appropriate source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 3 Related Specifications Publication Number IEEE Common Mezzanine Card Specification CMC P1386 Draft 2 1 Document Title and Source Institute of Electrical and Electronics Engineers Inc http standards ieee org catalog IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 1 Institute of Electrical and Electronics Engineers Inc http standards ieee org catalog IEEE Standard for Local Area Networks Carrier Sense Multiple Access TEEE 802 3 with Collision Detec
263. ion for the PCI bus is handled by the PCI Parity block Parity checking and generation for the PowerPC bus is handled outside of the PowerPC to PCI Bridge Outbound Functions PPC Decode 2 14 An outbound transaction is originated from the PowerPC bus and is targeted to the PCI bus The key functional elements are the PPC Slave the Outbound FIFO and the PCI Master This section describes in detail the elements of the Harrier that are associated with outbound transactions Harrier maps either PCI Memory space or PCI I O space into PowerPC address space using four programmable map decoders Each map decoder is accompanied by some address translation logic and is collectively referred to as an Outbound Translation Function The most significant 16 bits of the PowerPC address are compared with the address range of each Outbound Translation Function and if the address falls within the specified range the access is passed on to PCI An example of this is shown in the following figure Computer Group Literature Center Web Site PowerPC to PCI Bridge PowerPC Bus Address 8 0 8 21 2 3 4 81 i Decode is gt and lt r T yY A OTADx Register 7 0809000 81 Figure 2 6 Outbound Address Decoding There are no limits imposed by the Harrier on how large of an address space an Outbound Translation Function can represent There is a lower limit of a minimum of 64 KBytes due to the resolution of the address compare l
264. is 8 bits the Harrier uses data signals D31 D24 and issues one beat per data byte If the port width is 16 bits the Harrier uses data signals D31 D16 and issues one beat per 2 aligned data bytes Finally if the port width is 32 bits the Harrier uses D31 DO and issues one beat per 4 aligned data bytes The Harrier uses the other attributes to determine which access time to use for each data beat When bursting is disabled the Harrier uses the access delay XCSR XPAT AD for every data beat within a transaction When bursting is enabled the Harrier uses XCSR XPAT AD as the access delay for only the first beat of each burst The Harrier uses the burst access delay XCSR XPAT BRD XCSR XPAT BWD for the remaining beats of each burst In all cases the access time can be extended beyond the programmed time by using the XWAIT input signal If the XCSR XPAT BAM bit is set the Harrier accesses the Xport Bus in the basic timing mode In the basic timing mode the Harrier uses only non burst accesses and lengthens signal timings for compatibility with less flexible Xport Bus devices Xport Bus Transaction Examples Xport Bus accesses begin with the address phase in which the master presents address and attributes The accesses continue with the data phase in which the master transfers 1 to 32 beats of data Depending on programmed configuration the beats of data may involve bursting The following discussion shows different examples Note that
265. is a word aligned pointer into PowerPC address space that represents the tail location of the Inbound Free list FIFO This pointer is automatically incremented whenever a PCI master performs a read from the Inbound Free list FIFO The processor may also modify this register as needed The fields within the MIIFT register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides MP 150 Inbound Post list Head Register Offset Name Operation Reset XCSR 2D8 Sup MIOPH m Hp 7 HE d n4 R W E 000 ADU 00000 ds The MP DO Inbound Post list Head Register MIIPH is a word aligned pointer into PowerPC address space that represents the head location of the Inbound Post list FIFO This pointer is automatically incremented 3 100 Computer Group Literature Center Web Site Message Passing whenever a PCI master performs a write to the Inbound Post list FIFO The processor may also modify this register as needed The fields within the MIIPH register are defined as followss QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides MP 150 Inbound Post list Tail Register Offset XCSR 2DC Bit PTR
266. is bit is set to alogic 1 whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty In the FIFO mode this bit http www motorola com computer literature 3 143 Programming Model 3 144 is set to a logic 1 whenever the transmitter FIFO and the Transmitter Shift Register are both empty In both cases this bit is cleared when a byte is written to the transmitter data channel THRE Transmitter Holding Register Empty In the non FIFO mode this bit is set to a logic 1 whenever a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register and it is reset to logic 0 concurrently with the write to the Transmitter Holding Register In the FIFO mode this bit is set to a logic 1 whenever the transmitter FIFO is empty and it is cleared when at least one byte is written to the transmitter FIFO In both cases this bit when set also causes the UART to issue an interrupt when the Transmitter Holding Register Empty Interrupt enable ETBED is set high BI Break Interrupt In the non FIFO mode this bit is set to a logic 1 whenever the SINx line is held in the logic 0 state for more than a full word transmission time start bit data bits parity stop bits It is cleared by a read from the LSTAx register In the FIFO mode this error is associated with the particular character in the FIFO it applies to and is revealed when its associated character is at the top of the FIFO
267. is the first level of atwo level masking scheme The second level of masking is provided by the FEMA MIDB bit which provides a global masking of all inbound doorbell interrupts independent of the state of the MGIDM register The fields within the MGIDM register are defined as follows IDBMx Inbound Doorbell Mask Writing a zero to a particular bit position will enable the generation of the associated inbound doorbell interrupt Writing a one will mask the interrupt MP 150 Outbound Free list Head Register Offset XCSR 2C0 Bit ei ed a Function Name MIOFH LO QBA PTR Operation R t c R W Reset 000 miS 00000 The MP O Outbound Free list Head Register MIOFH is a word aligned pointer into PowerPC address space that represents the head location of the Outbound Free list FIFO This pointer is automatically 3 96 Computer Group Literature Center Web Site Message Passing incremented whenever a PCI master performs a write to the Outbound Free list FIFO The processor may also modify this register as needed The fields within the MIOFH register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides MP 150 Outbound Free list Tail Register Offset XCSR 2C4 Bit Function PTR Operation R W
268. ished by pulling up the XAD 26 signal The host processor on the PCI bus must have access to the Harrier s PCI registers This is accomplished by pulling down XAD 27 and XAD 28 Refer to the section titled Hardware Configuration on page 2 133 for more information The host processor on the PCI bus programs Harrier s PCI base address registers to allow access to Harrier s PowerPC 60x bus control registers and the SDRAM The host processor on the PCI bus then initializes the SDRAM controller and the SDRAM The SDRAM needs to be initialized with the correct CRCs before the ECC logic can be enabled Also the XCSR SDGC ENRV bit must be set Refer to the section titled SDRAM General Control Register on page 3 25 for more information When this bit is set the reset vector address range FFF0000 FFFFFFFF is mapped to the SDRAM bank at 00000000 The host processor on the PCI bus can then load the operation code into the SDRAM The local processor is released by negating the XCSR BXCS POH bit Refer to the section titled Bridge PowerPC Control and Status Register on page 3 41 for more information When the local processor starts executing code at FFF00100 the hardware will translate the address to location 00000100 in the SDRAM The processor on the PCI bus can completely initialize the Harrier and the SDRAM or it can initialize only the minimum required features to allow the local processor to start and then the local processor can complete t
269. it Notes 1 SDRAM speed attributes are programmed for the following CAS latency 2 tRCD 2 CLK Periods tRP 2 CLK Periods tRAS 5 CLK Periods tRC 7 CLK Periods tDPL 2 CLK 4 2 Computer Group Literature Center Web Site SDRAM Interface Periods and the WDPL bit is set in the Synchronous DRAM Control register 2 The Harrier is configured for no external registers on the SDRAM control signals Refer to the section titled Hardware Configuration on page 2 133 for more information 3 tB1 tB2 tB3 and tB4 are specified in the following figure tB4 gt tB3 tB2 tB1 From Idle 1B1 Back to Back CLK PPP PPL TTT ts NC V S V DBB ore 4 X Lu N N TA Ne 3x4 Ne Figure 4 1 Timing Definitions for Table 4 1 http www motorola com computer literature 4 3 Performance Notes When the bus starts out idle tB1 is the number of CLK periods from the rising edge of the CLK that drives TS low to the rising edge of CLK that samples the first TA low When the bus is busy and TS_ is being asserted as soon as possible after Harrier asserts aack_ the back to back condition occurs For back to back cycles tB1 is the number of CLK periods from the rising edge of CLK that samples the last TA low of a data tenure to the rising edge of CLK that samples the first TA low of the next data tenure tB2 is the number of CLK periods
270. it can use while gathering and evaluating SDRAM device data from serial EEPROMs SDRAM Refresh Period The SDRAM per row refresh period comes up from power up reset initialized to 7 75us For performance reasons software should set the refresh period to the longest value that still meets the device manufacturer s requirements 5 1 Programming Considerations SDRAM Size The SDRAM size control bits come up from power up reset cleared to zero Once software has determined the correct size for an SDRAM bank it should set the bank s size bits to match The value programmed into the size bits tells the Harrier how big the bank is for map decoding and how to translate that bank s PowerPC addresses to SDRAM addresses Programming a bank s size to non zero also allows it to participate in scrubbing if scrubbing is enabled I C EEPROMs Most of the information needed to program the SDRAM speed attributes refresh period and size is provided by EEPROM devices that are connected to the Harrier s IC bus The EEPROM s devices contain data in a specific format called Serial Presence Detect SPD Board designers can implement one EEPROM for each of the Harrier s SDRAM banks or they can implement one EEPROM for several such banks When using DIMMs the board designer can use the EEPROM that is provided on the DIMM C EEPROMs that are used for SPD can be wired to appear at one of 8 different device locations Board designers should estab
271. it is set the exception is enabled and the status bit reflects the status of the error exception When the enable bit is cleared the exception is disabled and the status bit will always read zero If the interrupt enable bit is set an interrupt will be generated whenever the corresponding status bit is set If the machine check 0 enable bit is set a machine check will be generated to processor 0 and if the machine check enable bit is set a machine check will be generated to processor 1 whenever the corresponding status bit is set If the status bit is set writing a one to clear bit will clear the status bit and the associated exception Each functional exception has an enable bit a status bit and a mask bit When the enable bit is set the exception is enabled and the status bit reflects the status of the functional exception When the enable bit is cleared the exception is disabled and the status bit will always read zero If the mask bit cleared an interrupt will be generated whenever the corresponding status bit is set If the mask bit is set an interrupt will not be generated In the case of DMA MDB MMO MM1 and ABT functional exceptions if the status bit is set writing a one to clear bit will clear the status bit and the associated exception Note that the clear bits are in FECL Computer Group Literature Center Web Site Exceptions register and MGID register In the case of MIP functional exception the status bit and the excepti
272. ithin the PMEP Register Group allowing a PCI master to determine which doorbell bit was used to generate the outbound doorbell interrupt The fields within the MGOD register are defined as follows ODBIx Outbound Doorbell Interrupt Writing a one to a particular bit position will set the bit and cause the generation of a PCI interrupt MP Generic Inbound 0 and 1 Message Registers Offset MGIMO XCSR 2A0 MGIMI XCSR 2A4 Bit 4 doce to co dao d o ed ei ez Function Name MGIMx Generic BYTEO BYTE1 BYTE2 BYTES3 Operation R W R W R W R W Reset 00 00 00 00 The MP Generic Inbound Message Registers MGIM0 and MGIM1 are used for receiving inbound messages from PCI to the processor The processor reads the MGIMO or MGIM1 register to obtain the inbound message These registers are visible from within the PMEP Register 3 94 Computer Group Literature Center Web Site Message Passing Group allowing a PCI master to write a message to either MGIMO or MGIMI which will then generate a processor interrupt The interrupts generated by these registers may be cleared from within the FECL register MP Generic Inbound Doorbell Register Offset XCSR 2A8 Bit dddadadddNda e cd i t3 c ggg yg y Nao a Function Name MGID Generic Operation i OY ttl cf cl cl ct ct ct ctl tcl oc Reset aadgagogcdgcdaoccaagcccdgGocdcoegoocoodooocdaocoacdGcGoasgm
273. itial address location of the slave device After CMP and ACKI bits have been tested for proper response the next data word loaded into the IZTDx Register will be transferred to the next address location of the slave device and so on until the block transfer is complete A stop sequence then must be transmitted to the slave device by first setting the STP and ENA bits in the I2COx Register and then writing a dummy data data don t care to the I2TDx Register The I2STx Register must now be polled to test CMP bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the Harrier master s possession of the PC bus The following figure shows the suggested software flow diagram for programming the PC page write operation http www motorola com computer literature 2 89 Functional Descriptions DEVICE ADDR WORD ADDR DATA 1 DATAn M w A A START S Re c Coes c STOP BI ie et sey EST pe pen e pape A WB 38 LI LIILLLIk A A A A ACK from Slave Device BEGIN LOAD 09 START CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR WR BIT TO I2C TRANSMITTER DATA REG READ I2C STATUS REG LOAD DATA DATA n TO I2C TRANSMITTER DATA REG LOAD WORD ADDR TO I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C STATUS REG N Y
274. itm a Calculate the number of rows in each device using SPD byte 3 If the number of rows is ROWS and the value in SPD byte 3 is R then ROWS 28 Calculate the number of columns in each device using SPD byte 4 If the number of columns is COLUMNS and the value in SPD byte 4 is C then COLUMNS 2 Calculate the total number of addresses within each device If the total number of addresses in a device is A then A ROWS x COLUMNS Calculate the total number of locations in the bank using the results of step c and SPD byte 17 If the total number of locations in the bank is L and the value in byte 17 is 4 then L Ax4 Computer Group Literature Center Web Site Or L 22x 2x4 Note that Harrier only works if byte 17 is 4 Obtain the primary device width from SPD byte 13 Programming SDRAM Related Control Registers f Determine the size bits based on the results of steps d and e using the following table Table 5 2 Programming the SDRAM SIZ Bits Total Number Primary Bank Size gt Value to be of Locations Device Width programmed within the into the Bank L Bank s SIZE bits 4 4M 16 32Mbytes 200001 8M 8 64Mbytes 200010 8M 16 64Mbytes 260011 16M 4 128Mbytes 260100 16M 128Mbytes 200101 16M 16 128Mbytes 260110 32M 4 256Mbytes 260111 32M 256Mbytes 1000 32M 16 256Mbytes 1001 64M 4 512Mbytes 1010 64M 512Mbytes 261011 64M 16 512Mbytes
275. ize affects the number of the initial prefetch read cycles and the duration of the subsequent prefetch read cycles Please refer to the section titled FIFO Tuning on page 2 41 for more information http www motorola com computer literature 3 45 Programming Model 3 46 The encoding of this field is shown in the following table Table 3 20 OTATx RXS Encoding RXS Virtual FIFO Size Bytes Cache Lines 00 64 2 01 128 4 1x 256 8 ENA Enable If set the corresponding Outbound Translation Function is enabled for read and write transactions WPE Write Post Enable If set write posting is enabled for the corresponding Outbound Translation Function SGE Store Gather Enable If set the corresponding Outbound Translation Function will participate in Store Gathering If cleared the corresponding Outbound Translation Function will not participate in Store Gathering This bit only has meaning if write posting is enabled RAE Read Ahead Enable If set the corresponding Outbound Translation Function will participate in read ahead If cleared the corresponding Outbound Translation Function will not participate in read ahead MEM Memory IO If set the corresponding Outbound Translation Function will generate transfers to or from PCI Memory space If cleared the corresponding Outbound Translation Function will generate transfers to or from PCI I O space using the addressing mode defined by the IOM field IOM
276. k priority to 15 prohibits the delivery of all interrupts to the associated processor Nesting of Interrupt Events A processor is guaranteed never to have an in service interrupt preempted by an equal or lower priority source An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an End of Interrupt EOI is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt Spurious Vector Generation Under certain circumstances the MPIC will not have a valid vector to return to the processor during an interrupt acknowledge cycle In these cases the spurious vector from the spurious vector register is returned The following cases cause a spurious vector fetch a IRQ is asserted in response to an externally sourced interrupt which is activated with level sensitive logic and the asserted level is negated before the interrupt is acknowledged a IRQ is asserted for an interrupt source which is masked using the mask bit in the Vector Priority register before the interrupt is acknowledged Interprocessor Interrupts IPI 2 70 Processor 0 and 1 can generate interrupts which are targeted for the other processor or both processors There are four Interprocessor Interrupts IPI channels The interrupts are initiated by writing a bit in the IPI dispatch registers If subsequent IPI s are initiated before the first is
277. k size registers ITBAx from 4K boundary in PCI ITOFx and Bytes to 2G space translated ITSZx within Bytes to any 64K Byte PCFS boundary in PowerPC space Message 4K Bytes Any 4K Byte MPBAR register 3 21 Passing Group boundary within PCFS PMEP 3 2 Computer Group Literature Center Web Site Register Group Summary Register Group Summary The following subsections describe the Harrier register groups in detail PowerPC Control and Status XCSH Register Group The PowerPC Control and Status Register Group consumes a 1K byte block and contains control and status registers specific to the Harrier This group resides within PowerPC address space and is byte halfword word and doubleword accessible Itis possible to place the base address of the XCSR Register Group at either FEFF0000 FEFF1000 FEFF2000 or FEFF3000 Having multiple choices for a base address allows the system designer to connect multiple Harrier ASICs in one system and thus multiple PCI busses to one PowerPC bus Please refer to the section titled Hardware Configuration on page 2 133 for more information Generally the processor is responsible for maintaining this group of registers It is possible however to setup an Inbound Translation Function that would place this register group as a PCI memory mapped resource thereby allowing access by external PCI masters This Register Group contains a reflection of the Harrier s PCI Configuration Spa
278. l Descriptions eem 0 15 CLK s Gt x ud 0 7 CLK s here ex DDD DADA DAD C NINTNY NF WE NT N NY NY NC KGS paco eto ee GE x bee L C pe C em xan ies XT Hae C a ae E XALE 5 N 2 er un mullis ao ye E Tr XWExx ES ly Mr Sa a XWAIT rw TW re as Figure 2 28 Xport Bus 3 beat Write Transaction with Burst Size of 4 The following figure shows a multi beat read with bursting turned on and XCSR XPAT BAM cleared Multiple bursts are employed because the number of beats to transfer exceeds the burst size 2 102 Computer Group Literature Center Web Site XPORT FP here Eme CLK XCSx XA XAD XALE XOE XWAIT s cc UU Jt BRD inserts 0 7 CLK s here Figure 2 29 Xport Bus 8 beat Read Transaction with Burst Size of 4 In all the preceding timing diagrams the XCSR XPAT BAM Basic Mode control bit is cleared In the next two it is set When XCSR XPAT BAM is set all Xport transactions are broken into single beats on the Xport Bus and cycle timing slows to allow longer setup and hold times The following figure shows an Xport Bus read when XCSR XPAT BAM is set http www motorola com computer literature 2 103 Functional Descriptions AD inserts 0 15 CLK s here K KE ESAS SASANN XCSx_ ee A A XA DX mages XAD D Gsres 3 XALE SAN XOE_ XWAIT_ V
279. lation Functions and for the PMEP Register Group The external connection of IDSEL to an AD line establishes the connection between Harrier s device number and it s configuration space The PCI Configuration Register Group is compliant with the configuration register set described in the PCI Local Bus Specification Revision 2 1 The Harrier is a single function device and consequently offers a Single Function Header Type 00 for Function 0 All write operations to reserved registers are treated as no ops That is the access is completed normally on the bus and the data is discarded Read accesses to reserved or un implemented registers are completed normally and a data value of 0 is returned A reflection of this Register Group is contained within the XCSR Register Group The description of each register within the PCFS Register Group will be accompanied by the appropriate register from the reflected configuration space within the XCSR Register Group The Harrier PCI Configuration Space Register Group is shown in the following table http www motorola com computer literature 3 21 Programming Model Table 3 5 PCI Configuration Space PCFS Register Group Function Bits Offset PowerPC Header 00 to PCI 04 Bridge 08 MLAT 0C MPBAR 10 ITBARO 14 ITBARI 18 ITBAR2 1C ITBAR3 20 24 28 2C 30 34 38 3C Address 40 Tra
280. lish an TC EEPROM addressing scheme that allows software to know which PC address to use to find information for each SDRAM bank For example hardware could always place the C EEPROM for SDRAM bank A at the first address bank B at the second etc Whatever addressing scheme is used should also deal with cases where multiple banks are described by one PC EEPROM SDRAM Base Address and Enable Each bank needs to be programmed for a unique base address that is an even multiple of its size Once a bank s speed attributes size and base address is programmed it can be enabled Computer Group Literature Center Web Site Programming SDRAM Related Control Registers SDRAM Control Registers Initialization Example The following is a possible sequence for initializing SDRAM control registers 1 Get a small piece of SDRAM for software to use for this routine Optional This routine assumes that SDRAM related control bits are still at the power up reset default settings We will use a small enough piece of SDRAM that the address signals that are affected by SDRAM size will not matter For each SDRAM bank a Set the bank s base address to some even multiple of 32Mbytes Refer to the previous section titled SDRAM Bank A B C D E F G and H Addressing Registers b Set the bank s size to 4Mx16 and enable it Refer to the previous section titled SDRAM Bank A B C D E F G and H Addressing Registers c Test the firs
281. ll attempt to empty the DMA FIFO 3 PowerPC to PowerPC Data is read from the PowerPC bus and written back sometime later to the PowerPC bus The DMA PPC Master will fill the DMA FIFO to a certain point after which the DMA PPC Master will empty the DMA FIFO 4 PCI to PCI Data is read from the PCI bus and written back sometime later to the PCI bus The DMA PCI Master will fill the DMA FIFO to a certain point after which the DMA PCI Master will empty the DMA FIFO Computer Group Literature Center Web Site DMA Controller 5 Data Pattern to PowerPC A data pattern is written into the DMA FIFO and then written to the PowerPC bus The Pattern Generator will attempt to fill the DMA FIFO at the same time that the DMA PPC Master will attempt to empty the DMA FIFO The data pattern may either be a fixed pattern or an incrementing pattern 6 Data Pattern to PCI A data pattern is written into the DMA FIFO and then written to the PCI bus The Pattern Generator will attempt to fill the DMA FIFO at the same time that the DMA PCI Master will attempt to empty the DMA FIFO The data pattern may either be a fixed pattern or an incrementing pattern Accesses to the PowerPC bus share some of the same attribute options that are offered by the Inbound Translation Functions For example the CRI Cache line Read Invalidate option may be used for PowerPC bus reads and the CWF Cache line Write Flush option may be used for PowerPC bus writes Accesse
282. ll leave its request asserted for the number of transfers indicated within this field Once the specified number of transfers has happened the master will momentarily remove its request If there are other masters requesting the PowerPC bus then the PowerPC Arbiter will grant the bus to the next highest priority master If there are no other requests pending then the original transaction continues on until the next burst boundary The Harrier is tuned to work with a burst size of 128 bytes however the actual average transfer size for each system varies and this field may be changed accordingly The burst size is encoded as shown in the following table Table 3 57 GCSR XBS Encoding XBS Burst Size 00 64 bytes 01 128 bytes 10 256 bytes 11 continuous http www motorola com computer literature 3 195 Programming Model 3 196 BTO Bus Time out This field specifies the enabling and time out length to be used by the PowerPC Address Bus Timer The time out length is encoded as shown in the following table Table 3 58 GCSR BTO Encoding BTO Time Out Length 00 256 usec 01 64 usec 10 8 usec 11 disabled MID Master ID This field is encoded as shown in the following table to indicate who is currently PowerPC bus master This information is obtained by sampling the XARBO thru XARB3 pins when in external PowerPC arbitration mode When in internal PowerPC arbitration mode this information is genera
283. lock CLK diagram of the Harrier s PLL implementation A sample of clocking options and their associated PowerPC and PCI frequencies is shown in Table 2 1 Test Root Muxes Buffers XCLK Tree 5 T AX i xX To PowerPC Hvo HA e our Div by f p FHHRHHHEHHHHHH l S i PLL J PCLK Tree i Div by N 0 ae Is Clock i I Se E US l XP X gt Clock Phase gt Clock Ratio l Harrier ASIC Figure 2 1 Block Diagram of PLL Implementation Functional Descriptions 2 2 Table 2 1 PowerPC PCI Clocking Options PowerPC Clock PCI PCI Clock Frequency Ratio Clock Frequency MHz PowerPC PCI Divisor MHz N 66 67 1 1 4 66 67 2 1 8 33 33 3 2 6 44 44 75 00 3 2 6 50 00 52 10 30 00 83 33 3 2 6 55 55 5 2 10 33 33 100 00 3 1 12 33 33 9 6 66 67 Harrier s PLL will phase lock the external PowerPC clock to the internal XCLK tree This phase locking creates a zero clock insertion delay on the XCLK tree The clock insertion delay of the PCLK tree is balanced to that of the XCLK tree which effectively makes the internal PCLK phase locked to the external PowerPC clock The system is responsible for maintaining a fully synchronous and minimum skew relationship between the external PowerPC and PCI clocks The PLL ensures a synchronous relationship exists between the four clo
284. lt d N od o g lt d N od og g Function Name PCIGP Reflected Operation R W PCI Configur Reset 00000000 ation Space The PCI General Purpose Register is provided for inter process message passing or general purpose storage It is accessible from the PCI bus and the PowerPC bus It does not control any hardware Note that the PCIGP register is byte swapped when accessing from the XCSR Register Group For example programming a value of 01234567 within the PCFS Register Group would be the same as programming 67452301 within the XCSR Register Group http www motorola com computer literature 3 77 Programming Model DMA Controller All of the registers for this function are located in the PowerPC address space as a part of the XCSR Register Group DMA Control Register Offset XCSR 250 Bit d desdarddodz IJINNA IINA J Function Name DCTL DMA Operat ion Reset 3 78 The DMA Control Register DCTL provides the control fields for the Harrier DMA function The fields within the DCTL register are defined as follows ABT Abort Writing a one to this field will abort a DMA transaction An abort is considered an unrecoverable operation to a DMA transaction meaning that an aborted transaction may not be restarted When issuing an abort both the PowerPC and or PCI masters are immediately stopped and all FIFO contents are invalidated
285. lter XCSR SDTC SDER b Program the XCSR SDGC MXRR bits in the SDRAM General Control Register using the information obtained in step 6 Note that XCSR SDGC DREF and XCSR SDGC RWCB should be cleared XCSR SDGC ENRV and XCSR SDGC SWVT should 5 8 Computer Group Literature Center Web Site Programming SDRAM Related Control Registers be programmed as desired and XCSR SDGC DERC should be left set until software has initialized all of SDRAM c Program the SDRAM Bank A B C D E F G and H Addressing Registers Each bank s base address should be programmed so that it is an even multiple of its size Only those banks that exist should be enabled Also only those that exist should be programmed with a non zero size The size information was obtained in step 5 9 SDRAM is now ready to be initialized for use Optional Method for Sizing SDRAM Generally SDRAM bank sizes can be determined by using SPD information Refer to the section titled SDRAM Control Register Initialization Example Another method for accomplishing this is as follows 1 Initialize the SDRAM interface control register bits to a known state a Make sure the PowerPC Clock Frequency Register matches the operating frequency b Make sure that the SDRAM Timing Control Register contains its power up reset values If not make sure that the values match the actual characteristics of the SDRAM being used c Make sure that the Error Exception Enable Register does
286. ly register from within the PCFS Register Group and may be written at any time from within the XCSR Register Group The MNGN register specifies how long of a burst period the Harrier requires The value is presented is in units of 0 25 us This register will be configured to 00 following the release of reset which indicates the Harrier has no particular grant requirements The Maximum Latency Register MXLA is a read only register from within the PCFS Register Group and may be written at any time from within the XCSR Register Group The MXLA register specifies how often the Harrier needs to gain access to the PCI bus The value is presented is in units of 0 25 us This register will be configured to 00 following the release of reset which indicates the Harrier has no particular latency requirements http www motorola com computer literature 3 67 Programming Model Message Passing Attribute Register Perspective from the PCI Bus PCFS 44 Function Address Translation Perspective from the PowerPC Bus Offset XCSR 344 Bit e e c n c egadadsduauuwdesau Function Name MPAT Reflected PCI 3 Z al Configur a B ation E Space Operation gt R s a4 a m a cd m a ed mae m ed c a nd Reset Goddddd aqqdddgddddddaad 00 RAE Read Ahead Enable The PMEP Register Group does not support read ahead howe
287. may access this register from within the XCSR Register Group The processor may obtain status pertaining to an interrupt by reading the FEST register and may mask the interrupt within the FEMA register Computer Group Literature Center Web Site Message Passing Outbound traffic will use the Message Passing Generic Outbound Doorbell MGOD register This register is used when the processor wishes to assert a doorbell interrupt to a PCI master There are a total of twenty eight interrupt doorbells The processor may access this register from within the XCSR Register Group and a PCI master may access this register from within the PMEP Register Group A PCI master may obtain status pertaining to an interrupt by reading the MGOD register The masking of the interrupt is through the Message Passing Generic Interrupt Mask MGMS register Message Passing Registers The Harrier has four Message Passing registers Two of the registers are used for inbound traffic and two are used for outbound traffic A Message Passing register is a 32 bit location that may be written with a unique 32 bit message by a sending agent The receiving agent will receive an interrupt whenever a new message has been written and will read the Message Passing register to obtain the message Inbound traffic will use the Message Passing Generic Inbound Message MGIMO and MGIM1 registers These registers are used when a PCI master wishes to send a message to the processor
288. meter The table below shows the encoding Note that power up reset is the only kind of reset that affects this field Table 3 10 SDTC TRAS Encoding TRAS Time for tRAS 00 4 CLK s 01 5 CLK s 10 6 CLK s 11 7 CLK s WDPL Wait on tDPL When set the Harrier always waits at least 4 CLK s after the write command portion of a single beat write before precharging SDRAM When cleared the Harrier does not impose the wait Software should always set WDPL to 1 Note that power up reset is the only kind of reset that affect this bit 3 28 Computer Group Literature Center Web Site SDRAM Interface TDPL SDRAM timing parameter tDPL TDPL determines the minimum number of CLK cycles the Harrier uses to satisfy the SDRAM s tDPL parameter The following table shows the bit encoding Note that power up reset is the only kind of reset that affects this bit Table 3 11 SDTC TDPL Encoding TDPL Time for tDPL 0 CLK s 1 2 CLK s TRP SDRAM timing parameter tRP TRP determines the minimum number of CLK cycles the Harrier uses to satisfy the SDRAM s tRP parameter The table below shows the bit encoding Note that power up reset is the only kind of reset that affects this bit Table 3 12 SDTC TRP Encoding TRP Time for tRP 0 2 CLK s 3 CLK s TRCD SDRAM timing parameter tRCD TRCD determines the minimum number of CLK cycles the Harrier uses to satisfy the SDRAM s tRCD pa
289. mine a resource size and is ultimately written with a value indicating where in PCI Memory or I O space the resource is to reside The upper portion of the PCI address is compared with the upper programmable portion of each BAR and if the address falls within the specified range the access is passed on to the PowerPC bus An example of this is shown in the figure below PCI Bus Address 4 0 5 1 2 3 4 5 4 0 4 0 4 1 2 3 31 1615 0 31 1615 0 Decodeis Decodeis ITBARx Register 4 0 4 0 0 0 0 0 4 0 4 0 4 0 0 0 31 1615 0 31 1615 0 V i A i J V A Programmable Fixed Programmable Fixed M UL V ITSZx Register 0 8 0 0 7 0 7 0 Figure 2 8 Inbound Address Decoding http www motorola com computer literature 2 27 Functional Descriptions 2 28 The size of each Inbound Translation Function is independent of each other and may be programmed to offer as small as 4KBytes or as large as 2 GBytes The read write characteristics of a BAR will change to reflect the size of the resource The BAR limits the placement of an Inbound Translation Function to binary boundaries according to resource size For example a 4KByte resource can be located on any 4KByte boundary Each Inbound Translation Function has an independent set of attributes These attributes are used to enable read and write accesses select either Memory or I O space enable read ahead and write posting and define the PowerP
290. motorola com computer literature 2 91 Functional Descriptions status The stop sequence will relinquish the Harrier s master s possession of the C bus The following figure shows the suggested software flow diagram for programming the PC sequential read operation 2 92 Computer Group Literature Center Web Site I2C Interface DEVICE ADDR WORD ADDR DEVICE ADDR DATA 1 M I LT I S ACK and DATA from Slave Device LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG LOAD 09 START CONDITION TO READ I2C STATUS REG I I2C CONTROL REG LOAD DEVICE ADDR WR BIT TO B 12C TRANSMITTER DATA REG Y READ I2C STATUS REG READ I2C RECEIVER DATA REG LOAD 01 TO I2C CONTROL REG LOAD WORD ADDR TO I2C TRANSMITTER DATA REG Y READ I2C STATUS REG N N Y LOAD 0B REPEATED START CONDITION TO I2C CONTROL REG COAR SIS STOF CONDITION TO 12C CONTROL REG LOAD DEVICE ADDR RD BIT TO I2C TRANSMITTER DATA REG PORE Bey DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C STATUS REG Figure 2 22 Programming Sequence for Ic Sequential Read http www motorola com computer literature 2 93 2 Functional Descriptions UART Interface XPORT 2 94 The Universal Asynchronous Receiver Transmitter UART interface provides two f
291. n Space Reset 3 72 The Inbound Translation Attribute Registers ITATO ITAT1 ITAT2 and ITAT3 contain attribute information associated with the mapping of PowerPC address space to PCI memory space The fields within the ITATYX registers are defined as follows PRE Prefetch Enable This field represents a control point for the ITBARx PRE field enabling software to establish the prefetchable status of an Inbound Translation Function This field does not affect any hardware If set the ITBARx PRE field will be set to a logic 1 If cleared the ITBARx PRE field will be set to a logic 0 RAE Read Ahead Enable If set read ahead is enabled on the PowerPC bus This forces the Harrier to perform a predefined number of cache line reads during the first fetch The number of lines initially read and the subsequent resume characteristics are controlled by the setting of the RMT RMS and RXT RXS fields If cleared the Harrier performs one single beat read and does not start a new read until a previously read beat has been transferred across PCI Each subsequent read is always be a single beat read WPE Write Post Enable If set write posting is enabled on the PCI bus The Harrier continues to collect data from the PCI bus Once a certain threshold is met the Harrier presents the collected data as Computer Group Literature Center Web Site PowerPC to PCI Bridge cache line writes t
292. n Name Header Operation Reset Perspective from the PowerPC Bus Offset XCSR 310 Bit e 4 ud odxedza d N od o g d N od o g Function Name MPBAR Reflected JJ pase BASE Loon B E Configur ef g E ation Space Operation R t c cc R W R R W Reset 0 add 0 0 00000 The Message Passing Register Group Base Address Register MPBAR controls the mapping of the PMEP Register Group within PCI Memory space IO MEM I O Space Indicator This bit is hard wired to a logic zero to indicate PCI memory space MTYPx Memory Type These bits are hard wired to zero to indicate that the PMEP Register Group can be located anywhere in the 32 bit address space PRE Prefetch This bit is hard wired to zero to indicate that the PMEP Register Group is not prefetchable http www motorola com computer literature 3 61 Programming Model Inbound Translation Base Address 0 1 2 and 3 Registers BASE Base Address These bits define the memory space base address of PMEP Register Group The group may be placed at any 4K Byte boundary This field is only accessible when the ENA bit field is set in the MPAT register Note that the BASE field is byte swapped when accessing from the XCSR Register Group For example programming a base address of 12345 within the PCFS Register Group would be the same as programming 53412 within the XCSR Register Group Perspective from the PCI Bus Offset ITBAR
293. ne data beat It inserts wait states until the beat of data has been transferred on the PowerPC bus It initiates a disconnect in accordance with PCI initial and subsequent latency requirements Posted Read read ahead enabled Is accepted either in the form of a single beat or a burst transaction It initiates a sequence of contiguous cache line reads on the PowerPC bus It generally returns read data to the PCI Slave before issuing an initial latency disconnect It incorporates a delayed transaction protocol to be compliant with the PCI Slave s initial and subsequent latency requirements Compelled Read read ahead disabled Is accepted either in the form of a single beat or a burst transaction however it is always terminated after the transfer of one data beat It initiates a single beat read on the PowerPC bus It generally returns read data to the PCT Computer Group Literature Center Web Site PowerPC to PCI Bridge Slave before issuing an initial latency disconnect It incorporates a delayed transaction protocol to be compliant with the PCI Slave s initial and subsequent latency requirements The Harrier is designed to always comply with the PCI Slave s initial and subsequent latency requirements It supports a programmable initial latency providing either a 16 clock target latency or a 32 clock host bridge cache hit latency During posted writes that cannot be serviced immediately i e a full FIFO the Harrier always waits as long
294. ned A register name is designated with bold and capital lettering as follows RGST A group of registers is called a Register Group A Register Group is designated by a four letter descriptor The first letter of the descriptor designates the addressing space that the Register Group resides in A Register Group residing within PowerPC address space begins with the letter X A Register Group that resides within PCI address space begins with the letter P A Register Group is designated with italic lettering as follows XGRP There are cases where a register from one Register Group may be referenced while discussing another Register Group A register can be referenced hierarchically as follows XGRP RGST There may be some cases where it is desirable to associate a bit name to a register name In these cases the bit name may be appended to the register name and or register hierarchy as follows RGST BIT XGRP RGST BIT Register Descriptions xxvi All register descriptions follow a fixed convention The possible operations for each bit within a register are as follows R The bit is a read only status bit R W The bit is a readable and writable R C The bit is cleared by writing a one to itself The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset PURST L The bit is affected by local reset RST X The bit is not affected by reset V
295. not enable SDRAM error exceptions d Make sure the following bits are initialized as follows XCSR SDGC MXRR 0 1 XCSR SDGC DREF 0 XCSR SDGC RWCB 0 XCSR SDGC DERC 1 XCSR SDGC ENRV 0 XCSR SDGC SWVT 0 http www motorola com computer literature 5 9 Programming Considerations a XCSR SDSC SCPA 00 Refer to the sections titled SDRAM General Control Register and SDRAM Scrub Control Register for more information Make sure that no other resources internal or external to Harrier are set up to respond in the range 00000000 4000001F For each of Banks A H Set the bank s base address to 00000000 Refer to the section titled SDRAM Bank A B C D E F G and H Addressing Registers Enable the bank and make sure that the other seven banks are disabled Refer to the section titled SDRAM Bank A B C D E F G and H Addressing Registers Set the bank s size control bits Start with the largest possible 2048Mbytes Refer to the section titled SDRAM Bank A B C D E F G and H Addressing Registers Write a unique 64 bit data pattern to each one of a specified list of addresses The list of addresses to be written varies depending on the size that is currently being checked The address lists are shown below Table 5 4 Address Lists for Different Bank Size Checks Size Addresses to Check Notes 2048MB 256Mx4 00000000 00010000 40000000 102
296. nsaction will simply finish without intervention or error When in Direct Mode the end of the transfer is considered completion When in Linked List Mode the end of the last transfer of a transaction is considered completion Upon completion the DMA Controller will return a done status to the DSTA register and optionally interrupt the processor 2 Commanded Stop This is an option available during Linked List Mode transactions Software may set the DCTL PAU bit at any time during a transaction When the DMA Controller reaches a transfer boundary i e ready to fetch the next descriptor it will stop all DMA activity If there are more Linked List transfers to be performed then the DMA Controller will return a paused status to the DSTA register and optionally interrupt the processor If the last transfer of a transaction has completed then the DMA Controller will return a done status to the DSTA register Once stopped a transaction may started again at any time The DMA Controller will simply pick up where it left off The first descriptor fetch will occur from the address that was placed within the DNLA register during the previously completed transfer http www motorola com computer literature 2 57 Functional Descriptions Interrupts 2 58 3 Commanded Abort This option exists for either Direct Mode or Linked List Mode Software may set the DCTL ABT bit at any time When set the DMA Controller will abort all DMA a
297. nslation 44 48 4C ITOF1 ITSZI 50 3 22 Computer Group Literature Center Web Site Register Group Summary Table 3 5 PCI Configuration Space PCFS Register Group Continued Function Bits Offset ITOF2 1Tsz2 58 ITAT2 5C ITOF3 52 60 ITAT3 64 Reserved etc Status PSTA 80 GP Reg PGPR 84 Reserved etc FF PCI Message Passing PMEP Register Group The Harrier provides a group of PCI Memory mapped resources for Message Passing This group is a 4K Byte block that contains both I O and generic message passing functions The I O components consists of inbound and outbound circular queue ports and interrupt status control registers These components are fully compliant with the Intelligent I O 150 Architecture Specification The generic components are the PCI bus mapped complimentary equivalents to the Message Passing functions found within the XCSR Register Group The mapping of this group is controlled by the MPBAR register within the PCFS Register Group The Harrier PCI Message Passing Register Group is shown in the following table http www motorola com computer literature 3 23 Programming Model Table 3 6 PCI Message Passing PMEP Register Group Function Bits Offset 31 24 23 16 15 8 7 0 Passing etc E99 vc MIST 03
298. nterrupt source is the 8259 the interrupt handler issues a second Interrupt Acknowledge request to read the interrupt vector from the 8259 The MPIC does not interact with the vector fetch from the 8259 The interrupt handler saves the processor state and other interrupt specific information in system memory and re enables for external interrupts the MSRee bit is set to 1 The MPIC blocks interrupts from sources with equal or lower priority until an End of Interrupt is received for that interrupt source Interrupts from higher priority interrupt sources continue to be enabled If the interrupt source was the 8259 the interrupt handler issues an EOI request to the MPIC Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC This resets the In Service bit for the 8259 with in the MPIC and allows it to recognize higher priority interrupt requests if any from the 8259 If none of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 The device driver interrupt service routine associated with this interrupt vector is invoked Ifthe interrupt source was not the 8259 the interrupt handler issues an EOI request for this interrupt vector to the MPIC If the interrupt source was the 8259 and any of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 Normally interrupts from ISA devices are c
299. number of data beats per burst The following table shows the encoding Table 3 47 XPATx BLE Encoding BLE Bytes not beats per Burst 00 4 01 8 10 16 11 32 BREN Burst Read Enable When set the Harrier performs burst reads for the corresponding channel if appropriate When cleared it does not http www motorola com computer literature 3 153 Programming Model BRD Burst Read Delay This field determines the number of CLK periods the Harrier will add for burst reads to the Xport Bus The following table shows the encoding Table 3 48 XPATx BRD Encoding BRD Added Delay Device Burst Page Read Access Time 000 0 CLK s 1 CLK 10ns 100 MHz 1 CLK s 2 CLK s 20ns 100 MHz 2 CLK s 3 CLK s 30ns 100 MHz 011 3 CLK s 4 CLK s 40ns 100 MHz 100 4 CLK s 5 CLK s 50ns 100 MHz 101 5 CLK s 6 CLK s 60ns 100 MHz 110 6 CLK s 7 CLK s 70ns 100 MHz 111 7 CLK s 8 CLK s 80ns 100 MHz 3 154 BWEN Burst Write Enable When set the Harrier performs burst writes for the corresponding channel if appropriate When cleared it does not BWD Burst Write Delay This field determines the number of CLK periods the Harrier will add for burst writes to the Xport Bus The following table shows the encoding Table 3 49 XPATx BWD Encoding BWD Added Delay 0 CLK s 1 CLK s 2 CLK s 3 CLK s 4 CLK s 110 5 CLK s 6 CLK s 111 7 CLK
300. number of transfers that may take place during a transaction http www motorola com computer literature 2 51 Functional Descriptions There are two operating modes for the DMA Controller Direct Mode and Linked List Mode Direct Mode performs one transfer according to a programmed set of values within the DMA control registers Once the transfer has completed an indication will be given to the DMA control registers and an optional interrupt will be given to the processor Linked List Mode performs numerous transfers within a transaction Information about each transfer is obtained from descriptors placed somewhere in PowerPC bus address space The Harrier fetches these descriptors as needed during the transaction Once all the descriptors are fetched and the associated transfers are complete an indication of the completed transaction is given to the DMA control registers and an optional interrupt is given to the processor Direction of Data Movement 2 52 There are six possible directions for data movement within a transfer Each is explained below 1 PowerPC to PCI Data is read from the PowerPC bus and written to the PCI bus The DMA PPC Master will attempt to fill the DMA FIFO at the same time that the DMA PCI Master will attempt to empty the DMA FIFO 2 PCI to PowerPC Data is read from the PCI bus and written to the PowerPC bus The DMA PCI Master will attempt to fill the DMA FIFO at the same time that the DMA PPC Master wi
301. o PowerPC Clock kJ U7 o7 POlClck wo 7 7 V f UL E E 1 1 Ratio PowerPC Clock LL NN AM MER TS POIClock O7 WLS LS V I NV Tf tus Cycle Figure 2 2 PowerPC and PCI Clock Relationships http www motorola com computer literature 2 3 Functional Descriptions The Harrier must be told what system clock ratio is being used so that the internal clock phasing logic knows how to lock the internal PCLK to the external PCI clock This information is given to the Harrier in the form of a state placed on three XAD lines at the release of power up reset Please consult the section titled Hardware Configuration on page 2 133 for more information SDRAM Interface The SDRAM interface provides PowerPC bus masters with high performance access to 8 banks of ECC SDRAM The interface s major blocks consist of a PowerPC 60x slave and an SDRAM controller The following figure shows a simplified block diagram SDRAM PowerPC Ctrl PowerPC Controller Slave MEM Ctrl PowerPC PowerPC a5 Address In Dec amp Latch Address Out PowerPC Data powerpc SDRAM Data In Mie Qut ux Reg Reg amp Mux amp CKBGen PowerPC Data Out Reg Figure 2 3 SDRAM Interface Block Diagram 2 4 Computer Group Literature Center Web Site SDRAM Interface Many of the SDRAM interface s functions are software programmable For a description of the rela
302. o 0 a tie in external interrupt processing will always go to processor 0 Mode used on Version 02 of the MPIC Table 3 37 Tie Mode Encoding MODE Processor 0 always selected Swap between Processor s Name VENI Offset XMPI 01080 piri Operation Reset The Vendor Identification Register VENI is a read only register that returns vendor identification There are two fields in the VENI which are not defined for the MPIC implementation but are defined in the MPIC specification They are the vendor identification and device ID fields The field within the VENI register is defined as follows STP Stepping The stepping or silicon revision number of the MPIC 3 116 Computer Group Literature Center Web Site Processor Init Register Multi Processor Interrupt Controller uvis al Operation R R R ed e4 ed g ia 3 q Reset 00 00 00 adqdddad Function Misc The Processor Init Register PINT is used to assert a soft reset to the processors The fields within the PINT register are defined as follows P1 Processor 1 Writing a one to P1 will assert the Soft Reset input of processor 1 SRST1_ Writing a zero to P1 will negate the SRST1_ signal P0 Processor 0 Writing a one to PO will assert the Soft Reset input of processor 0 SRSTO Writing a zero to PO will negate the SRSTO_ signal The Soft Reset input to the PowerPC processor is negative edge
303. o PowerPC address space that represents the tail location of the Outbound Post_list FIFO This pointer is automatically incremented whenever a PCI master performs a read from the Outbound Post_list FIFO The processor may also modify this register as needed The fields within the MIOPT register are defined as follows 3 98 Computer Group Literature Center Web Site Message Passing QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides MP 150 Inbound Free list Head Register Offset XCSR 2D0 Bit Function Name LO Operation Reset 00000 The MP LO Inbound Free list Head Register MIIFH is a word aligned pointer into PowerPC address space that represents the head location of the Inbound Free list FIFO This pointer is manually maintained by the processor The fields within the MIIFH register are defined as follows QBA Queue Base Address This read only field is a copy of the QBA field within the MIQB register PTR Pointer This is an offset from the QBA where the FIFO component resides http www motorola com computer literature 3 99 Programming Model MP 150 Inbound Free list Tail Register Offset Name XCSR 2D4 aoe CEG GECEG CEGEGGEECGGCEGGE GEGGGGGE bas Reset QBA PTR 00000 E The MP LO Inbound Free list Tail Register MIIFT
304. o determine the actual state of the EXTI pins Bit position 16 reflects the state of the EXTII5 pin and bit position 31 reflects the state of the EXTIO pin Note that this register samples the same EXTI lines that are routed to the MPIC therefore the effects of MPIC interrupt conditioning i e edge detection signal polarity etc will not be reflected in this register XMPI Register Group The following subsections describe the registers within the XMP7 Register Group http www motorola com computer literature 3 113 Programming Model Feature Reporting Register Offset Bit Name 3 114 XMPI 01000 The Feature Reporting Register FREP is a read only register that contains MPIC sizing and version information The fields within the FREP register are defined as follows NIRQ Number of IRQ s The number of the highest external IRQ source supported The IPI Timer and Harrier Detected Error interrupts are excluded from this count NCPU Number of CPU s The number of the highest physical CPU supported There are two CPU s supported by this design CPU 0 and CPU 1 VID Version ID Version ID for this Interrupt Controller This value reports what level of the MPIC specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification Computer Group Literature Center Web Site Multi Processor Interrupt Controller Global Configuration
305. o processor 0 will be generated and if the EEMCKI XBT is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL XBT bit XAP PowerPC Bus Address Parity Error This bitis set when an address parity error is detected on the PowerPC bus if the EEEN XAP is enabled and all other PowerPC error status bits are cleared If the EEINT XAP is set a processor interrupt will be generated If the EEMCKO XAP is set a machine check to processor 0 will be generated and if the EEMCKI XAP is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL XAP bit XDP PowerPC Bus Data Parity Error This bit is set when an data parity error is detected on the PowerPC bus if the EEEN XDP is enabled and all other PowerPC error status bits are cleared If the EEINT XDP is set a processor interrupt will be generated If the EEMCKO XDP is set a machine check to processor 0 will be generated and if the EEMCK1 XDP is set a machine check to Computer Group Literature Center Web Site Exceptions processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL XDP bit XDT PowerPC Bus Delayed Transaction Time out This bit is set when a delayed transaction time out is detected on the PowerPC bus
306. o serves as a pipeline register for the two tick propagation time through the IS In Service Register ISR There is a In Service Register ISR for each processor The contents of the ISR is the priority and source of all interrupts which are in service The ISR receives a bit set command during Interrupt Acknowledge cycles and a bit clear command during End Of Interrupt cycles The ISR is implemented as a 41 bit register with individual bit set and clear functions Fifteen bits are used to store the priority level of each interrupt which is in service Twenty six bits are used to store the source identification of each interrupt which is in service Therefore there is one bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router 2 16 The Interrupt Router monitors the outputs from the ISR s Current Task Priority Registers Destination Registers and the IRR s to determine when to assert a processor s IRQ pin When considering the following rule sets it is important to remember that there are two types of inputs to the Interrupt Selectors If the interrupt is a distributed class interrupt there is a single bit in the IPR associated with this interrupt and it is delivered to both Interrupt Selectors This IPR bit is qualified by the destination register contents for that interrupt before the Interrupt Selector compares its priority to the priority of all other requesting interrupts for tha
307. o the PowerPC bus If cleared each write transaction is fully compelled The Harrier writes each PCI 32 bit or 64 bit beat as a single beat transaction on the PowerPC bus MEM Memory If set the Harrier maps the corresponding Inbound Translation Function to PCI memory space If cleared the resource is mapped to PCI I O space The state of this field is reflected within the ITBARx IOMEM field If the ENA field is set then the IOMEM field is the inversion of the MEM field ENA Enable If set the corresponding Inbound Translation Function is enabled for read and write transactions RXS Read Any Size This field is used by the Harrier to determine a virtual FIFO size for inbound prefetch reads This field is applicable only to PCI Read or Read Line command types The selection of a virtual FIFO size will affect the number of the initial prefetch read cycles and the duration of subsequent prefetch read cycles Please refer to the section titled FIFO Tuning in the previous chapter for more information The encoding of this field is shown in the following table Table 3 27 ITATx RXS RMS Encoding RXS RMS Virtual FIFO Size Bytes Cache Lines 00 64 2 01 128 4 Ix 256 8 RXT Read Any Threshold This field sets a threshold for when read ahead prefetching will be resumed This field is applicable only to PCI Read or Read Line transaction types If set prefetching will resume once the FIFO is half empty I
308. o the first error http www motorola com computer literature 3 189 Programming Model Error Diagnostics PowerPC Attribute Register Offset XCSR 074 Bit Function Name Error Diagnostics Operation Reset The Error Diagnostics PowerPC Attribute Register EXAT captures attribute information from the PowerPC bus whenever an applicable Error Exception has been detected The register contents will only be updated when there are no status bits set within the EEST register During a string of successive errors this register will retain information pertaining to the first error The fields within the EXAT register are defined as follows MID Master ID This field contains the ID of the PowerPC master which originated the transfer in which the Error Exception occurred The encoding scheme is identical to that used in the GCSR register DMA DMA Error This read only bit will be set to a 1 when the current transaction is DMA originated and will be set to a 0 when the current transaction is PowerPC to PCI bridge originated Additionally this bit may only be set to a 1 if the error being captured is a PowerPC bus time out and the MID field of the error indicates the Harrier is the bus master If the error being captured is not a PowerPC bus time out or the MID field of the error indicates the Harrier i
309. of a read cycle When a delayed read completion is finally established between the Harrier and the PCI master the Harrier continues to provide burst read data as needed If a disconnect is issued any time after the first beat of data has been transferred the PCI master re attempts the transaction and the Harrier considers this to be an entirely new transaction The Inbound FIFO is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained The Inbound FIFO consists of three major components the command path the read data path and the write data path Computer Group Literature Center Web Site PowerPC to PCI Bridge The command path incorporates a 52 bit by 8 entry FIFO which is used to hold command information being passed between the PCI Slave and the PPC Master If write posting is enabled up to eight single beat or burst transactions may be posted If this limit is exceeded any pending PCI transactions are retried until the PPC Master completes a portion of the previously posted transactions and creates some room in the command FIFO Each data path uses a 256 byte 32 entries 8 cache lines by 64 bit FIFO The operation of the write data path is completely independent of the read data path This allows the Harrier to accept write posted transactions while servicing a delayed read transaction If a read data path FIFO limit is reached then the PPC Master stops prefetching until the
310. ogic Each Outbound Translation Function has an associated set of attributes These attributes are used to enable the map decoder write posting store gather and read ahead and to define the PCI transfer characteristics Each Outbound Translation Function also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the PowerPC address and the result is used as the PCI address This offset provides a high degree of decoupling between PCI address space and PowerPC address space An example of this is shown in the following figure http www motorola com computer literature 2 15 Functional Descriptions PowerPC Bus Address 8 0 8 0 12 3 4 OTOFx Register PCI Bus Address 1 0 8 0 1 2 3 4 Figure 2 7 Outbound Address Translation Care should be taken to assure that all functions decode unique address ranges since overlapping address ranges will lead to undefined operation PPC Slave The PPC Slave provides the interface between the PowerPC bus and the Outbound FIFO The PPC Slave is responsible for tracking and maintaining coherency to the PowerPC bus protocol The PPC Slave accepts three basic types of transactions Posted Write Can either be in the form of a single beat or a burst transaction May optionally be part of Store Gathering 2 Compelled Write Can only be single beat transaction without Store Gathering Always performed as a delayed transaction
311. oller as a PCI master has exceeded the maximum number of unsuccessful attempts to transfer data due to retries when the EEEN PMR is enabled and all other PCI error status bits are cleared If the EEINT PMR is set a processor interrupt will be generated If the EEMCKO PMR is set a machine check to processor 0 will be generated and if the EEMCK1 PMR is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL PMR bit SSE SDRAM Memory Controller Single Bit Error This bit is set when the SDRAM Memory Controller detects and corrects a single bit error when the EEEN SSE is enabled If the EEINT SSE is set a processor interrupt will be generated If the EEMCKOQO SSE is set a machine check to processor 0 will be generated and if the EEMCKI SSE is set a machine check to processor 1 will be generated This bit and the interrupt or machine check associated with it may be cleared by writing a one to the EECL SSE bit SSC SDRAM Memory Controller Single Bit Error Count Overflow This bit is set when the SDRAM Memory Controller detects a single bit error count overflow when the EEEN SSC is enabled If the EEINT SSC is set a processor interrupt will be generated If the EEMCKOQO SSC is set a machine check to processor 0 will be generated and if the EEMCK1 SSC is set a machine check to processor 1 will be generated This bit and the interrupt or machine che
312. ompletion status If the DMA Controller incurs multiple errors that are NOT simultaneously detected then the DSTA register will only reflect status pertaining to the first occurring error This is of particular importance to the PAU and ABT fields If an error is detected before the pause or abort takes affect then the DSTA register will only reflect status pertaining to the error The fields within the DSTA register are defined as follows http www motorola com computer literature 3 81 Programming Model SMA Signalled Master Abort This read only field will be set if the PCI master has signalled a master abort An error of this type will cause the DMA Controller to abort the current transaction RTA Received Target Abort This read only field will be set if the PCI master has received a target abort An error of this type will cause the DMA Controller to abort the current transaction MRC Maximum Retry Count This read only field will be set if the PCI master has exceeded the maximum 274 attempts to a target that is continually issuing disconnect retries An error of this type will cause the DMA Controller to abort the current transaction XBT PowerPC Bus Time out This read only field will be set if the PowerPC master has received an acknowledge due to a PowerPC bus time out An error of this type will cause the DMA Controller to abort the current transaction ABT Abort This read only field will be set if the DMA Controller
313. on will be cleared when the processor adjusts the inbound post list head and tail pointers to match For the UAO and UAI functional exceptions UART service routines will clear the status bit and the exception The following table summarizes the Harrier generated exceptions Table 2 22 Exception Summary Category Exception Description Primary Additional Clear Edge Status Status Level Error PowerPC Any unclaimed EEST XBT EXAD EXAT EECL XBT Edge Address PowerPC address XCSR Bus Time tenure originating out from any PowerPC bus master Error PowerPC Detection of an EEST XAP EXAD EXAT EECL XAP Edge Address address parity error XCSR Parity Error during any address tenure involving any PowerPC bus master Error PowerPC Detection of a data EEST XDP EXAD EXAT EECL XDP Edge Data parity error during XCSR Parity Error any data tenure involving any PowerPC bus master and any PowerPC bus slave Error PowerPC Any unclaimed EEST XDT EXAD EXAT EECL XDT Edge Delayed PowerPC delayed XCSR Transaction transaction Time out originating from any PowerPC bus master Error SDRAM Detection and EEST SSE SDSES EECL SSE Edge Memory correction of a SDSEA XCSR Interface single bit error Single BIt Error http www motorola com computer literature 2 123 Functional Descriptions Table 2 22 Exception Summary Continued Category Exception Description Primar
314. onnected to the 8259 interrupt controller ISA devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA device and system memory If interrupts from ISA devices are directly connected to the MPIC bypassing the 8259 the device driver interrupt service routine must read status from the ISA device to ensure buffers between the device and system memory are flushed Reset State After power on reset the MPIC state is d d Current task priority for all CPU s set to 15 All interrupt source priorities set to zero All interrupt source mask bits set to a one All interrupt source activity bits cleared Processor Init Register is cleared All counters stopped and interrupts disabled Controller mode set to 8259 pass through http www motorola com computer literature 2 79 Functional Descriptions Operation The following subsections describe the operational characteristics of the MPIC Interprocessor Interrupts Four interprocessor interrupt IPI channels are provided for use by all processors During system initialization the IPI vector priority registers for each channel should be programmed to set the priority and vector returned for each IPI event During system operation a processor may generate an IPI by writing a destination mask to one of the IPI dispatch registers Note that each IPI dispatch register is shared by both processors Each IPI dispatch register has two addresses but they
315. ons are favorable the Harrier accepts the transaction and anew entry is posted within the Command FIFO If the transaction is a write then write data is accepted from the data bus and posted in the Write Data FIFO The PPC Slave records which PowerPC master originated the transaction and retains a copy of the address and attributes of the transaction for future reference The PowerPC bus cycle is terminated with ARTRY If conditions are not favorable then the Harrier does not accept the transaction a new entry is not posted and data will not be accepted 3 The Harrier continues to service the delayed transaction to completion While doing so the PowerPC master continuously re http www motorola com computer literature 2 17 Functional Descriptions 2 18 attempts the transaction and the Harrier continuously terminates the PowerPC bus cycles with ARTRY asserted 4 The PCI Master is primarily responsible for completing the delayed transaction If the transaction is a compelled write then the PCI Master attempts to empty the contents of the Outbound FIFO to the PCI bus If the transaction is a read then the Outbound FIFO is filled from the PCI bus 5 The PPC Slave is notified by the PCI Master upon completion of the transaction at which time the PPC Slave is ready to close out the delayed transaction The PPC Slave waits for the PowerPC master to once again retry the transaction The PPC Slave validates the address attribut
316. ontroller Status on this interrupt may be obtained from within the Functional Exception Status FEST register and masking is supported within the Functional Exception Mask FEMA register The DMA interrupt may be cleared Computer Group Literature Center Web Site DMA Controller from within the Functional Exception Clear FECL register An interrupt will be generated anytime the DMA Controller changes from a busy state to a done paused or aborted state Transfer Throttling It is possible that the PCI or PowerPC bandwidth consumed by the DMA Controller could swamp the system with DMA activity This is particularly a problem if PCI or PowerPC arbitration is in favor of the Harrier The PCI bus has a built in system check on excessive bandwidth consumption The Master Latency Timer will be a driving factor for how much PCI bandwidth a DMA transfer may take In addition the PCI Back off Timer may be used to further control bandwidth consumption The PCT Back off Timer determines how long the DMA PCI Master will wait between starting burst transfers when a transfer is interrupted by the PCI Master Latency Timer This timer is controlled by the PBT field within the DCTL register Note that if the Master Latency Timer does not expire then the DMA PCI Master will attempt to complete a DMA transfer as one continuous PCI burst in accordance with the abilities of the DMA FIFO Bandwidth consumption on the PowerPC bus is controlled by the tran
317. ormity has been made and is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government
318. ose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem bem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take Warning adequate measures Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class A EN55024 Information Technology Equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety performance In accordance with European Community directives a Declaration of Conf
319. ources to PCT a PCFS Register Group mapped into PCI Configuration space 4 PowerPC bus address space mapped into PCI Memory or I O space a PMEP Register Group into PCI Memory space PCFS Register Group The PCFS Register Group is mapped within PCI configuration space according to how the system connects the Harrier s DEVSEL_ pin The Harrier provides a configuration space that is fully compliant with PCI Local Bus Specification 2 1 There are five base registers within the standard 64 byte header One register is dedicated to mapping the PMEP Register Group into PCI Memory space The remaining four base registers are associated with Inbound Translation Functions that map PowerPC http www motorola com computer literature 2 25 Functional Descriptions address space into PCI address space Additional control associated with each Inbound Translation Function is contained within device specific registers mapped above the 64 byte header 2 26 Computer Group Literature Center Web Site PowerPC to PCI Bridge PowerPC Bus Address Space The Harrier maps PowerPC address space into PCI Memory or I O space using four programmable map decoders Each map decoder is accompanied by some address translation logic and is collectively referred to as an Inbound Translation Function An Inbound Translation Function is mapped into PCI Memory or I O space using its own PCI compliant Base Address Register BAR A BAR is used by a PCI master to deter
320. pdidbibpi ti x E MEE Ha en duREU DM quadiVn id tu 3 85 DSAT PRG DNO Lecce n RDUM EADEM Dep M Pd NM UMS 3 86 DDATTYP EDU proio anie ERRER PERPE ENSE INEDITA 3 88 DERI Wu idi o oo 3 88 D TEI Z ENOCE ou amdettde sy pora put tie Spe Mna DESDE Md tt E bqR i dus 3 102 Cascade Mode Encoding 3 115 Tie hog s sanoen 3 116 FENSI SS aE EEE S 3 138 UART Interrupt Control Functom icssissicsicisssscesscrasssssessesesiuarnesaciannaa 3 138 Receiver FIFO Tugger Lge sicscscicsnsstsccassactsanesnstacnsanssancancsseramnanannans 3 140 WESIO End T P 3 142 UAR quibos d oos ea 3 148 Baud Rates and Divers La diepc niaidaiu i Ma pH PARE ERRARE DU VUE ML IMS Epid 3 148 APATI RS EPBOCEDOOQRUME ona 3 152 Ri EN Nucl rr 3 152 ASDATC AD OU aucaecdpusaiicdicdiabbi b in DERE RM In b 3 153 APATX BLE BBCi 3 153 APATI BRU coc o Jn 3 154 BEES ME d ESL JEU iii ERRANT RCM Up DNUS 3 154 Table 3 50 PARB PRI Encoding Leica sas cece eee n Mii QU URDU ED RN RE NM M S EE 3 156 Table 3 31 PARB PRK Encoding 1asseenenie dr RE E XR ES pRM RUP DAP ER PD DU DUAL MEE 3 157 Table 3 52 PARB HIE Fixed Mode Encoding 1 ceeeetne errare ota ntt aenean 3 157 Table 3 53 PARB HIE Mixed Mode Encoding ieeeeesie reete nen 3 158 Table 3 54 XARB FBR ESR FBW PSW Encoding wesciccssecassscccenacecssssccaiessesaees 3 160 Table 3 33 AARB PER Encoding sereine ee ikoe borip SCRI t AEREA 3 160 Ta
321. pt on Single Double Bit Error 1 1 Introduction Error address and Syndrome Log Registers for Error Logging PCI Interface Fully compliant with PCI Local Bus Specification Revision 2 1 32 bit addressing 32 bit or 64 bit data 33 MHz and 66 MHz operation Supports Memory I O and Configuration addressing space Multi level write posting buffers for writes to either PowerPC or PCI bus Read ahead buffer for reads from either PowerPC or PCI bus Eight independent software programmable address translation map decoders Store Gathering Copy Back Snarfing DMA Controller Single Channel Direct or Linked List PowerPC to PCI PCI to PowerPC PowerPC to PowerPC and PCI to PCI Fixed or incrementing pattern to PowerPC or PCI Message Passing Fully compliant with Intelligent I O 1 0 Architecture Specification Version 1 5 IOP Message Unit Generic functions 2 UART interfaces 2 PC bus master interfaces Interrupt Controller MPIC compliant Computer Group Literature Center Web Site Overview All control registers are directly accessible from the PowerPC bus Supports 16 external interrupt sources and two processors Multiprocessor interrupt control allows any interrupt source to be directed to either processor Multilevel cross processor interrupt control for multiprocessor synchronization Four 31 bit tick timers a Arbitration Internal or external PowerPC and PCI bus arbitrat
322. r whenever it detects a master transaction is terminated by a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bit is set by the Harrier whenever it detects a master transaction except for Special Cycles is terminated by a master abort It is cleared by writing it to 1 writing a 0 has no effect SIGSE Signaled System Error This bit is set whenever the Harrier asserts SERR It is cleared by writing it to 1 writing a 0 has no effect RCVPE Detected Parity Error This bit is set whenever the Harrier detects a parity error even if parity error response is disabled see bit PERR in the CMMD register It is cleared by writing it to 1 writing a 0 has no effect Revision ID Class Code Registers Perspective from the PCI Bus Offset PCFS 08 ge CCE EGEGE GEGGEEEECEGEGEGE GEEREGEE bases Name CLAS REVI Header Operation R R Reset 060000 or 0E0001 02 Perspective from the PowerPC Bus Offset XCSR 308 Bit c o Function Name Reflected PCI Configur Reset 02 000006 or 01000E ation Space Operation 3 58 Computer Group Literature Center Web Site PowerPC to PCI Bridge The Revision ID Register REVI is a read only register that identifies the Harrier revision level The Class Code Register CLAS is a read only register from within the PCFS Register Group and may be written at any time from within the XCSR Registe
323. r Group The CLAS register identifies the class code of the Harrier The initial contents of this register is established with external resistors placed on signals sampled at the release of reset Please refer to section titled Hardware Configuration in the previous chapter for more information The initial class code of the Harrier depends on the level of participation in the I O Message Passing protocol The table below shows the dependency between class codes and IO participation Table 3 23 CLAS Encoding LO CLAS PCFS Register Group Participation Base Sub Program None 06 Bridge Device 00 Host 00 Not Used Bridge LO Host 06 Bridge Device 00 Host 00 Not Used Bridge Bridge IO IOP Agent 0E O Controller 00 Not Used 01 Includes Interrupt Capability Cache Line Size Master Latency Timer Header Type Register Perspective from the PCI Bus Offset Reset PCFS 0C c Function Header 00 00 aaqddadada_ 00 http www motorola com computer literature 3 59 Programming Model Perspective from the PowerPC Bus Offset XCSR 30C Bit Name c dad lt c dad Function Na NX C odo ggl CLSZ MLAT HEAD Reflected CLS LAT PCI Operation Configur aa RW R W al aa R R ation Reset Space aa 00 00 qad 00 00 3 60 The Header Type Register HEAD is a read only register that identifi
324. r ID Register VENI identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola and is hardwired as a read only value The Device ID Register DEVI uniquely identifies this particular device The Harrier will always return 480B Revision ID Register Offset XCSR 004 Bit id d N od o1 S Se Ms e Ma d RSS SIM Function Name REVI Operation R R R R ID Reset 00 01 00 00 The Revision ID Register REVI identifies the Harrier revision level http www motorola com computer literature 3 193 Programming Model Global Control and Status Register Offset XCSR 010 Bit 44444444434333434324448453 49444 Name GCSR Control and Status PUSTI XBS BTO MID RAT Operation R Cr ed ed va 2 3 3 ECC CCC o c ed od o e o Cr a cd cd Reset 3 194 lt 5 0 0 P 0 X X je Ee E a E a E a E o E a 10 9 09099g0909g9g The Global Control Status Register GCSR provides miscellaneous control and status information for the Harrier The fields within the GCSR are defined as follows PUR Power up Reset This bit tells software when a power up has occurred Only power up reset sets PUR Only user software writing a one to PUR alone clears it SRST Push Button Reset This
325. r Register UPS is used to specify a frequency of the UART internal clock The formula for calculating a value is shown below UART INTERNAL CLOCK SYSTEM CLOCK UPS 2 After power up UPS is initialized to 1B which produces a 1 8519 MHz approximate UART clock signal based on a 100 0 MHz system clock Due to the IBM AC requirements on the UART oscillator clock input the value written to UPS must be greater than 02 The following table provides the decimal divisors IEDHx amp RTDLx when DLAB 1 to use with clock frequencies of 1 8432 MHz and 1 8519 MHz Table 3 43 Baud Rates and Divisors Baud Rate Decimal Percent Error Divisor 1 8432 MHz 1 8519 MHz 50 2304 0 0 469 75 1536 0 0 469 110 1047 0 026 0 496 134 5 857 0 058 0 411 150 768 0 0 469 300 384 0 0 469 600 192 0 0 469 1200 96 0 0 469 1800 64 0 0 469 2000 58 0 69 0 224 Computer Group Literature Center Web Site UART Controller Table 3 43 Baud Rates and Divisors Continued Baud Rate Decimal Percent Error Divisor 1 8432MHz 1 8519 MHz 2400 48 0 0 469 3600 32 0 0 469 4800 24 0 0 469 7200 16 0 0 469 9600 12 0 0 469 19200 6 0 0 469 38400 3 0 0 469 56000 2 2 86 3 34 128000 No suitable divisor 256000 No suitable divisor http www motorola com computer literature 3 149 Programming Model Xport All of the registers for this function are located wit
326. r all banks of SDRAM SDSA s one and only field is defined as follows SDSA SDRAM Scrub Address This field is the scrub address counter SDSA increments by eight each time the Harrier completes one scrub to all banks Bits 0 and 29 31 are always 0 s When SDSA reaches all 7fff fff8 it rolls over to 0 and continues counting SDSA s most significant bits are meaningful only for those banks whose SDRAM devices are large enough to require them Note that power up reset is the only kind of reset that affects SDSA SDRAM Single bit Error Status Offset XCSR 140 Bit ci ce odo g bam g 1 o od N g q q q oq Q A Function Name SDSES SDRAM ESYN ESB SECNT Error g Logging Operation R fav rd rd rd rd d d nd R W R Reset 00 P edis edel Aj aj 00 P 00 http www motorola com computer literature 3 33 Programming Model The SDRAM Single bit Error Status Register SDSES provides status for logged SDRAM single bit errors It also provides a single bit error counter The fields within the SDSES register are defined as follows ESYN Error Syndrome ESYN reflects the syndrome value at the last logging of a single bit error refer to the Error Exception Enable Register section further on in this chapter Software can use ESYN together with syndrome codes as listed in the Data section of the following chapter to determine which bit was in error Note that power up reset is the only kind of r
327. r does not snoop the command FIFO Use caution when using Store Gathering write posting or read ahead within coherent address space PCI Master The PCI Master in conjunction with the capabilities of the PPC Slave generally attempts to move data in either single beat or four beat transactions If Store Gathering is not enabled the PCI Master supports 32 bit and 64 bit transactions in the following manner http www motorola com computer literature 2 19 Functional Descriptions a All PowerPC single beat transactions regardless of the byte count are subdivided into one or two 32 bit transfers depending on the alignment and size of the transaction This includes single beat 8 byte transactions a All PowerPC burst transactions are transferred in 64 bit mode if the PCI bus has 64 bit mode enabled If at any time during the transaction the PCI target indicates it can not support 64 bit mode the PCI Master continues to transfer the remaining data within that transaction in 32 bit mode If Store Gathering is enabled the PCI Master supports 32 bit and 64 bit transactions in the following manner Q Once a Store Gather collection is to be transferred the PCI Master attempts to transfer the entire collection as a single contiguous burst in 64 bit mode if the PCI bus has 64 bit mode enabled If at any time during the transaction the PCI target indicates it can not support 64 bit mode the PCI Master continues to transfer the remaining d
328. r handling Inbound Function 2 36 error logging SDRAM errors 2 10 error reporting SDRAM data 2 8 errors outbound 2 24 ESB Error Scrub Bank SDRAM Single bit Error Status Register SDSES 3 34 Computer Group Literature Center Web Site ESB Error Scrub Bank SDRAM Multi bit Error Status SDMES 3 37 ESYN Error Syndrome SDRAM Single bit Error Status SD SES 3 34 exceptions error and functional 2 122 F false definition xxiii features of Harrier ASIC 1 1 Flash compatibility to Hawk mode 2 109 four beat Reads Writes SDRAM accesses 2 6 functional exceptions how reported 2 71 H half word definition xxiii hardware configuration 2 133 Harrier description 1 1 device number configuration space con nection 3 21 features 1 1 operation without firmware 5 13 resource table 3 1 Hawk Compatibility Mode 2 109 hexadecimal character xxii host slave Harrier to EEPROMs 2 82 Dc bus data transfer 2 82 Current Address Read 2 87 data transfer registers 2 82 Page Write 2 89 Sequential Read http www motorola com computer literature Sequential Read I2C 2 91 I2C Clock Prescaler I2PSx Register 2 82 I2C Control I2COx Register 2 82 I2C Controller function described 1 5 I2C interface 2 82 I2C Receiver Data I2RDx Register 2 82 I2C serial data SDAx 2 82 I2C Status I2STx Register 2 82 I2C Transmitter Data I2COx Register 2 82 I2C Transmitter Data I2TDx Register 2 82 I2COx Register 2 83 Current Address
329. rameter The table below shows the bit encoding Note that power up reset is the only kind of reset that affects this bit Table 3 13 SDTC TRCD Encodiing TRCD Time for tRCD 0 2 CLK s 1 3 CLK s SDER SDRAM External Registers or Buffers When SDER is set the Harrier increases the setup time for SDRAM command address to CS by one CLK period Note that SDER initializes at power up reset to match the values on a certain signal pin Refer to the section titled Hardware Configuration on page 2 133 for more information http www motorola com computer literature 3 29 Programming Model SDRAM Bank A B C D E F G and H Addressing Registers SDBA XCSR 110 SDBB XCSR 114 SDBC XCSR 118 SDBD XCSR 11C SDBE XCSR 120 SDBF XCSR 124 SDBG XCSR 128 SDBH XCSR 12C Hindi BASE Operation R W e4 ecd a c Lx 4i 5344443 The SDRAM Bank Addressing Registers SDBAA SDBAB SDBAC provide base address size and enable for each corresponding SDRAM bank A B C The fields within the SDBAx registers are defined as follows Function SDRAM Address BASE Bank Base Address This field determines the bank s base address The Harrier uses only those bits in BASE that correspond to integer multiples of the bank s size Consequently larger sized banks do not use BASE s lower significant bits SIZE Bank Size SIZE
330. re Center Web Site PowerPC to PCI Bridge Outbound Translation Offset Translation Attribute 0 1 and 2 Registers Offset OTOFO OTATO XCSR 224 OTOFI OTATI XCSR 22C OTOF2 OTAT2 XCSR 234 Bit Name Function Address Translation Operation The Outbound Translation Offset Registers OTOF0 OTOF1 and OTOEF2 contain offset information associated with the mapping of PCI Memory or I O space to PowerPC memory space The OTOFx field represents a 16 bit offset that is added to the upper 16 bits of the PowerPC address to determine the PCI address used for outbound transfers This offset allows PCI resources to reside at addresses that would not normally be visible from the PowerPC bus The Outbound Translation Attribute Registers OTATO OTATI and OTAT2 contain attribute information associated with the mapping of PCT Memory or I O space to PowerPC memory space The fields within the OTATx registers are defined as follows RXT Read Any Threshold This field sets a threshold for when read ahead prefetching will be resumed If set prefetching will resume once the FIFO is half empty If cleared prefetching will resume once the FIFO is completely empty Please refer to the section titled FIFO Tuning on page 2 41 for more information RXS Read Any Size This field is used by the Harrier to determine a virtual FIFO size for outbound prefetch reads The selection of a virtual FIFO s
331. rite 1111 Memory Write and Invalidate Using an encoding other than the recommended value will result in unpredictable DMA operation CWF Cache line Write Flush If set the DMA will use the Write with flush transfer type during PowerPC burst write cycles This will force the processor to perform copyback writes during snoop hits If cleared the DMA will use the Write with kill transfer type This Computer Group Literature Center Web Site DMA Controller will force the processor to invalidate it s associated cache entry during snoop hits This bit provides a work around solution for processors that cannot support Write with kill correctly This bit only applies to burst write cycles since all single beat cycles will use the Write with flush transfer type GBL Global If set the DMA will assert the GBL_ pin during PowerPC write cycles This will allow the processor to snoop the DMA transfer If cleared the GBL_ pin will not be asserted and the processor will not be able to snoop the DMA transaction DMA Next Link Address Register Offset XCSR 270 Bit Function Name DMA Operation Reset 00000000 The DMA Next Link Address Register DNLA contains information pertaining to the next Linked List Mode descriptor This register is not used when performing Direct Mode transactions When starting a Linked List Mode transaction software will program this register with the address of t
332. rmation Performance related information may be found within the section titled SDRAM Interface on page 4 1 The SDRAM controller uses single bit error correction and double bit error detection across 64 bits of data using 8 check bits Cycle Types To support ECC the controller always deals with SDRAM using full width 72 bit accesses When the PowerPC bus master requests any size read of SDRAM the controller reads the full width at least once When the PowerPC bus master requests a four beat write to SDRAM the controller writes all 72 bits 4 times When the PowerPC bus master requests a single beat write to SDRAM the SDRAM controller performs a full width read cycle to SDRAM merges in the appropriate PowerPC bus write data and writes the full width back to SDRAM http www motorola com computer literature 2 7 Functional Descriptions Error Reporting The Harrier checks data from SDRAM during PowerPC single and four beat reads during single beat writes and during scrubs There is no data from SDRAM to check during burst writes The following table shows the actions Harrier takes for the different errors that can occur during a PowerPC access 2 8 Computer Group Literature Center Web Site SDRAM Interface Table 2 2 SDRAM Single and Multi Bit Error Reporting Error Type Single Single Beat Four Beat Scrub Beat Four Beat Write Write Read Single Bit Terminate the Terminate the This cycle is not Error
333. rnally connected to the four MODEM control inputs OUT2 Output 2 signal This bit controls the Output 2 OUT2Ux signal which is an auxiliary user designated output When this bit is set to logic 0 the OUT2Ux_ output is forced to a logic 1 When this bit is set to logic 1 the OUT2Ux_ output is forced to a logic 0 OUT1 Output 1 signal This bit controls the Output 1 OUTIUx signal which is an auxiliary user designated output When this bit is set to logic 0 the OUTIUx output is forced to a logic 1 When this bit is set to logic 1 the OUTIUx output is forced to a logic 0 RTS Request To Send output This bit controls the Request To Send RTSx output When this bit is set to logic 0 the RTSx output is forced to a logic 1 When this bit is set to logic 1 the RTSx_ output is forced to a logic 0 DTR Data Terminal Ready output This bit controls the Data Terminal Ready DTRx output When this bit is set to logic 0 the DTRx output is forced to a logic 1 When this bit is set to logic 1 the DTRx output is forced to a logic 0 The Line Status Register LSTAx contains the status of the data transfer The fields within the LSTAx register are defined as follows FERR Error in Receiver FIFO This bit is set to 1 when there is at least one PE FE or BI in the Receiver FIFO It is cleared by a read from the LSTAx register provided there are no subsequent errors in the receiver FIFO TEMT Transmitter Empty In the non FIFO mode th
334. rola com computer literature 2 23 Functional Descriptions the resource size starting from the base address in the PSAD register The resource size is programmable from 4kbytes to 2Gbytes The PSAT register is used to enable the Passive Slave function and enable store gathering Error Handling 2 24 There is only one distinct type of error associated with the Outbound Function a PCI Bus Errors PCI Bus Errors While processing a transaction the PCI Master can encounter either a Master Abort or a Target Abort Both types of errors will terminate a transaction and cause an Error Exception to be generated There is no visibility of either type of error to the PPC Slave therefore it is the sole responsibility of the PCI Master to maintain the Outbound FIFO in the event that an error occurs The PCI Master takes the same action regardless of which error type is encountered There are four basic actions taken a If the transaction was a write and Store Gathering was not used then the PCI Master will invalidate the remaining portion of the aborted transaction by discarding the contents of the Outbound FIFO A transaction of this type will always be either a single beat or a burst transaction and the exact number of words to be discarded is known by the PCI Master Q Ifthe transaction was a write and Store Gathering was used then the PCI Master will continually discard the contents of the Outbound FIFO until the transaction is close
335. rror Exception Enable Register on page 3 170 If the error was due to a PowerPC access SDMEA matches the value that was on PowerPC address signals 0 28 If the error was due to a scrub SDMEA matches the value that was in the scrub address counter Bits 29 31 are always 0 s Note that power up reset is the only kind of reset that affects SDMEA http www motorola com computer literature 3 37 Programming Model PowerPC to PCI Bridge The PowerPC to PCI Bridge has registers located within three register groups Most of the control and status is contained within the PowerPC mapped XCSR Register Group Processor access to PCI Configuration Space is supported using PowerPC mapped registers within the XCFS Register Group Finally a standard PCI Configuration Space interface is provided within the PCFS Register Group XCSR Register Group This section does not cover the reflected PCI Configuration Space registers Please refer to the section titled PCI Configuration Space PCFS Register Group on page 3 21 for a detailed description of all XCSR Register Group registers applicable to the reflected PCI Configuration Space Bridge PCI Control and Status Register Offset XCSR 200 Bit esl alu c ocjo g mcns g dnd E c odo c Function Name Control and A g z Z Status Operation zzz gt R R 22822488388 us Reset Adddddddadcuuwaadad 00 00 The Bridge PCI Control and Status Register BP
336. s Identifies a targeted bus number If written with all zeros a Special Cycle will be generated If written with any value other than all zeros then a Special Cycle translated into a Type 1 Configuration Cycle will be generated EN Enable Configuration Cycles Writing a one to this bit enables CONFIG DATA to Configuration Cycle translation If this bit is a Zero subsequent accesses to CONFIG DATA will be passed though as I O Cycles http www motorola com computer literature 3 53 Programming Model Special Cycles Writing a one to this bit enables CONFIG DATA to Special Cycle translation If this bit is a zero subsequent accesses to CONFIG DATA will be passed though as I O Cycles CONFIG DATA Register The description of the CONFIG DATA register is also presented in two perspectives from the PCI bus Little Endian it ordering and from the PowerPC bus Big Endian bit ordering Note that the view from the PCI bus is purely conceptual since there is no way to access the CONFIG DATA register from the PCI bus Conceptual perspective from the PCI bus Offset Bit o d Function Name CONFIG Operation Reset Perspective from the PowerPC bus Offset CFC CFD CFE CFF Bit DL c a dan 9 1 a ans i g od OY g Function Name CONFIG DATA CONFIG Data A Data B Data C Data D DATA Operation R W R W R W R W Reset n a n a n a n a 3 54 Computer Group Literature Center Web
337. s Flash interface was routed through a connector to Flash devices located on another board To allow the Harrier to provide the same interface a Hawk compatibility mode was added This mode should only be used to provide backward compatibility with hardware developed for the Hawk ASIC The following table shows the address mapping when operating in the Hawk compatibility mode A 374 type edge triggered latch should be used to latch the address lines Table 2 11 Hawk Compatible Address Mapping MPU 16 bit Device Address Hawk Compatibility Mode Device Xport Bus Hawk Address Address Address 14 bit Latch 512MB A31 A30 AO XADRI RAO A29 Al XADR2 RAI A28 A2 XADR3 RA2 A27 A3 XADR4 RA3 A26 A4 XADRS5 RA4 A25 A5 XADR6 RA5 A24 A6 XADR7 RA6 A23 A7 XADO RA7 A22 A8 XADI RAS8 A21 A9 XAD2 RA9 A20 A10 XAD3 RAIO A19 All XAD4 RAII A18 A12 XADS BAO A17 A13 XAD6 BAI A16 A14 LXADRI LRAO A15 A15 LXADR2 LRAI http www motorola com computer literature 2 109 Functional Descriptions Table 2 11 Hawk Compatible Address Mapping Continued MPU 16 bit Device Address Hawk Compatibility Mode Device Xport Bus Hawk Address Address Address 14 bit Latch 512MB A14 A16 LXADR3 LRA2 A13 A17 LXADRA LRA3 A12 A18 LXADRS5 LRA4 All A19 LXADR6 LRAS A10 A20 LXADR7 LRA6 A9 A21 LXADO LRA7 A8 A22 LXADI LRAS8 A7 A23 LXAD2 LRA9 A6 A24 LXAD3 LRA10 A5 A25 LXAD4 LRA11 A4 A
338. s Register Offset XCSR 254 Bit Function Name DMA Operation cd cd d d d cc Cr d d d m d m ard R R Reset Addagdad Addddaad 00 00 The DMA Status Register DSTA provides the status fields for the Harrier DMA function The BSY field represents the current state of the DMA controller and the remaining fields indicate completion status Note that there will always be only one field set within the DSTA register at all times When the DMA controller is starting a transaction 1 e the DCTL DGO field is set the BSY field will be asserted and all of the completion status fields will be cleared The BSY field will remain asserted and the completion status fields will remain cleared throughout the entire DMA transaction Once the DMA Controller is finished then the BSY field will be cleared and only one of the completion status fields will be asserted A functional interrupt will be sent to the Exception module whenever the BSY field transitions to the deasserted state The completion status fields are prioritized from left to right with the left most status field holding the highest priority For example if the DMA Controller incurs a simultaneous SMA error and an XBT error then the DSTA register will only reflect the SMA completion status In a similar fashion if the DMA Controller incurs an XBT error while attempting a commanded abort then the DSTA register will only reflect the XBT c
339. s an access port to the Outbound Free list and Post list FIFOs Reading this register will return the oldest MFA entry from the Outbound Post list FIFO If there are no entries in the FIFO or the I 0 Message Passing function is disabled then this register will return OXFFFF FFFF Writing this register will place the newest MFA entry into the Outbound Free list FIFO If the IO Message Passing function is disabled then the write will be discarded http www motorola com computer literature 3 105 Programming Model MP Generic Outbound Message 0 and 1 Registers Offset MGOMO PMEP 100 MGOM1 PMPP 104 esq5354535322315123233 949 3009 en Name MGOMx Generic BYTE3 BYTE2 BYTEI BYTEO Operation Reset The MP Generic Outbound Message Registers MGOMO and MGOM1 are used for receiving outbound messages from the processor to PCI A PCI master reads the MGOMO or MGOMI register to obtain the outbound message These registers are visible from within the XCSR Register Group allowing the processor to write a message to either MGOMO or MGOM I which will then generate a PCI interrupt if the MGMS register permits The interrupt associated with this register may be cleared from within the MGST register MP Generic Outbound Doorbell Register Function Generic Offset PMEP 108 Bit Name Operation Reset The MP Generic Outbound Doorbell
340. s can only be injected during cycles that the Harrier is sourcing PowerPC data The Harrier generates address parity whenever it is sourcing a PowerPC address This happens for all transactions where the Harrier is a bus master Valid address parity is presented when ABB is asserted Computer Group Literature Center Web Site Reset Signals The Harrier checks address parity for all PowerPC bus transactions If an address parity error is detected then address and attribute information will be latched within the EXAD and EXAT registers and an interrupt or machine check will be generated depending on the programming of the EEMA EEDE and EEMS registers The Harrier has a mechanism to purposely inject address parity errors for testability The APE field within the EPEI register can be used to purposely inject address parity errors on specific address parity lines Address parity errors can only be injected when the Harrier is sourcing a PowerPC address Reset Signals The Harrier has two reset signals PURST_ and RST The PURST signal should be asserted at power up and resets all of the Harrier s internal logic The PURST signal must be asserted for 50 us after the VDD2V5 and VDD3V3 power supplies are stable the CLK and PCLK signals are stable and the XAD signals used for configuration are stable During this time the Harrier synchronizes its internal clock generation logic When the PURST signal is removed the Harrier latches the hardware
341. s closing a collection before the PCI Master starts the next prefetch read Some general guidelines and characteristics associated with the inbound path are as follows a Select the smallest FIFO size that is still greater than the expected inbound transaction size 4 A continuous burst with a small FIFO size creates smaller groups of burst transfers on PowerPC The increase number of groups on PowerPC makes the overall transaction more susceptible to bandwidth degradation due to initial latencies on PowerPC and within the SDRAM Memory Controller 4 A continuous burst with a large FIFO size creates larger groups of burst transfers on PowerPC and is less susceptible to initial latency bandwidth degradation http www motorola com computer literature 2 43 Functional Descriptions a Selection of an empty threshold works well if the transactions are almost always smaller than the virtual FIFO size If the transaction size exceeds the FIFO size then the transaction bandwidth will be severely degraded since wait states will be incurred between when the FIFO goes empty and when the PPC Master can start filling the FIFO again 4 Boundary cases work exactly as expected The PCI bus explicitly indicates the completion of a burst read transaction This indication can propagate fast enough to the PPC Master to inhibit any additional prefetch reads Transaction Ordering 2 44 All transactions will be completed on the destination bus in th
342. s not the bus master then this bit will read as a 0 DDF DMA Descriptor Fetch This read only bit will be set to a 1 when the DMA error occurred during descriptor fetch and will be set to a 0 when the DMA error occurred during data movement Additionally this bit may only be set to a 1 if the error being captured is a PowerPC bus time out and the MID field of the error indicates the Harrier is the bus master and the error being captured is DMA If the 3 190 Computer Group Literature Center Web Site Error Diagnostics error being captured is not a PowerPC bus time out or the MID field of the error indicates the Harrier is not the bus master or the error being captured is not DMA then this bit will read as a 0 DDI DMA Direction This read only bit will be setto a 1 when the DMA error occurred during fifo fill and will be set to a 0 when the DMA error occurred during fifo empty Additionally this bit may only be set to a 1 if the error being captured is a PowerPC bus time out and the MID field of the error indicates the Harrier is the bus master and the error being captured is DMA If the error being captured is not a PowerPC bus time out or the MID field of the error indicates the Harrier is not the bus master or the error being captured is not DMA then this bit will read as a 0 TBST Transfer Burst This bit is cleared when the transfer in which the Error Exception occurred was a burst transfer T
343. s that is not contained within a natural word boundary causes an unpredictable operation For example an I O transfer of 4 bytes starting at address 80000010 is considered a valid transfer An I O transfer of 4 bytes starting at address 8000001 1 is considered an invalid transfer since it crosses the natural word boundary at address 80000013 80000014 Configuration Cycles The Harrier uses Configuration Mechanism 1 as defined in PCI Local Bus Specification 2 1 to generate configuration cycles Please refer to this specification for a complete description of this function Configuration Mechanism 1 uses an address register data register format Performing a configuration access is a two step process The first step is to place the address of the configuration cycle within the CONFIG ADDRESS register Note that this action does not generate any Computer Group Literature Center Web Site PowerPC to PCI Bridge cycles on the PCI bus The second step is to either read or write configuration data into the CONFIG DATA register If the CONFIG ADDRESS register has been set up correctly the Harrier passes this access on to the PCI bus as a configuration cycle Theaddressesofthe CONFIG ADDRESS and CONFIG DATA registers are actually embedded within PCI I O space If the CONFIG ADDRESS register has been set incorrectly or the access to either the CONFIG ADDRESS or CONFIG DATA register is not 1 2 or 4 bytes wide the Harrier passes the access
344. s to the PCI bus are under complete user control The user can specify the actual PCI command to be used during both read and write cycles This means that a DMA transfer can take place in either Memory IO or Configuration space The DMA PCI Master has been optimized for accesses to PCI Memory space Transfers to either IO or Configuration space may result in a protocol violation i e bursting into IO space is discouraged and in some cases IO addressing during single beat transfers may be incorrect It is the user s responsibility to select the appropriate command type for each transfer When accessing the PCI bus it is possible to fix the source and or destination address This option exists to support fixed address FIFO type devices The fixed address option has some limitations on transfer addresses and sizes Addressing and Transfer Sizes There are no restrictions on either addressing or transfer sizes There are no dependencies between the source address and the destination address The source address can be at any byte and the destination address can be at any other byte The transfer size can be as small as 1 byte and as large as 4GBytes http www motorola com computer literature 2 53 Functional Descriptions Data Patterns The DMA Controller has the option of writing data patterns to either PowerPC or PCI space Any size transfer may be used and there are no restrictions on the starting address A starting data pattern is
345. saction Profiles and Starting Offsets Start Offset Write Profile Read Profile Notes i e from 0x00 0x20 0x40 etc Ox 00 Ox 07 Burst 0x00 Burst 0x00 Most efficient Burst 0x20 Burst 0x20 Ox 08 gt Ox 0f Single 0x08 Burst 0x00 Discard read beat 0x00 Single 0x10 Burst 0x20 Single 0x18 Burst 0x20 Ox 10 gt Ox 17 Single 0x10 Burst 0x00 Discard read beat 0x00 Single 0x18 Burst 0x20 and 0x08 Burst 0x20 Ox 18 gt Ox 1f Single 0x18 Single 0x18 Burst 0x20 Burst 0x20 Write Posting 2 34 The Harrier has an optional write posting mode that may be enabled by the WPE field within the ITATx registers While the PCI Slave is filling the Inbound FIFO with write data the PPC Master can be moving previously posted write data onto the PowerPC bus In general the PowerPC bus is running at a higher clock rate than the PCI bus which means the PCI bus can transfer data in a continuous uninterrupted burst while the PowerPC bus transfers data in distributed multiple bursts The Harrier write posting function does not incorporate any programmable tuning options Please refer to the section titled FIFO Tuning on page 2 41 for more information Computer Group Literature Center Web Site Read Ahead PowerPC to PCI Bridge The Harrier has an optional read ahead mode controlled by the RAE bit in the ITATx registers that allows the PPC Master
346. sed from the Host to an IOP from an IOP to the Host and from an IOP to an IOP These messages called Message Frames are a minimum of 64 bytes long and reside within shared memory structures A Message Frame is identified by a Message Frame Address MFA The MFA points to the beginning address of a Message Frame within shared memory The MFA exists in one of two states A Free MFA is a pointer to an allocated Message Frame that is empty A Post MFA is a pointer to an allocated Message Frame that is full An IOP will allocate a set of free Inbound Message Frames and corresponding MFAs within it s shared local memory These are used to receive messages from the Host or other IOPs The IOP will also allocate a set of free Outbound Message Frames and corresponding MFAs within it s shared local memory These are used to send messages to the Host or other IOPs A message is passed from one agent to another by sending the recipient a post MFA The sequence for sending a post MFA is as follows a The sending agent retrieves a free MFA from the receiving agent This MFA points to an empty Message Frame in the receiving agents local memory Computer Group Literature Center Web Site Message Passing 4 The sending agent writes the Message Frame into the receiving agents local memory pointed to by the MFA a The MFA now represents a Message Frame that is full The sending agent sends the post MFA back to the receiving
347. set the PCI Arbiter is enabled and is acting as the system arbiter If cleared the PCI Arbiter is disabled and external logic is implementing the system arbiter Please refer to the previous section titled Hardware Configuration for more information on how this bit is set Computer Group Literature Center Web Site Arbiters PowerPC Arbiter Register Offset XCSR 094 44345344453384 4d4448 44444 7 ARB Arbiters Operation sE Reset The PowerPC Arbiter Register XARB provides control and status for the PowerPC Arbiter Please refer to the previous section titled PPC Arbiter for more information The fields within the XARB register are defined as follows FBR Flatten Burst Read This field is used by the PowerPC Arbiter to control how bus pipelining will be affected after all burst read cycles The encoding of this field is shown in the following table FSR Flatten Single Read This field is used by the PowerPC Arbiter to control how bus pipelining will be affected after all single beat read cycles The encoding of this field is shown in the following table FBW Flatten Burst Write This field is used by the PowerPC Arbiter to control how bus pipelining will be affected after all burst write cycles The encoding of this field is shown in the following table FSW Flatten Single Write This field is used by the
348. sfer characteristics of the DMA PPC Master The DMA PPC Master will attempt to transfer data in user programmable block sizes of 256 bytes 512 bytes 1024 bytes or continuous The DMA PPC Master relies on the Harrier latching request arbitration protocol A transfer will proceed with the PowerPC bus request asserted until the programmable transfer limit is reached Once this limit is reached the DMA PPC Master will remove its request and wait for two clock periods after the completion of the last address tenure This short back off time will allow other pending PowerPC masters a chance at obtaining the bus After the two clock period expires the DMA PPC Master will reassert its request if there is more data to be transferred http www motorola com computer literature 2 59 Functional Descriptions 2 Message Passing The Harrier incorporates hardware dedicated to supporting message passing There are two levels of support offered IO Message Passing and Generic Message Passing l0 Message Passing 2 60 The Intelligent I O LO Architecture Specification Version 1 5 describes a comprehensive hardware and software solution to managing the development of platform independent device drivers The specification advocates the use of distributed embedded I O processing and uses a system of message passing to move information between processes An IO system consists of a Host and at least one I O Platform IOP Predefined messages may be pas
349. sh a task priority level for a processor Two processors are supported with each processor owning a task priority register Priority levels from 0 lowest to 15 highest are supported Setting the current task priority register to 15 masks all interrupts to this processor Hardware will set the current task register to F when it is reset or when the Init bit associated with this processor PO or P1 in PINT register is written to a one The fields within the POCTP P1CTP registers are defined as follows TP Task Priority of processor Processor 0 Processor 1 Interrupt Acknowledge Registers Offset POIAC XMPI 200A0 P1IAC XMPI 210A0 Bit 5 o c dad j o N od o og Function Name POIAC P1IAC CPU 0 VECTOR d CPU 1 Operation R R R R Reset 00 00 00 FF The Processor 0 Processor 1 Interrupt Acknowledge Registers POIAC and P1IAC are used to declare an interrupt acknowledge Two processors are supported with each processor owning an interrupt acknowledge register On PowerPC based systems Interrupt Acknowledge is implemented as a read request to a memory mapped Interrupt Acknowledge register Reading the Interrupt Acknowledge register http www motorola com computer literature 3 129 Programming Model returns the interrupt vector corresponding to the highest priority pending interrupt Reading this register without a pending interrupt will return a value of FF hex Reading this register also has the
350. should be generated to abort the transfer after a software wait loop 100us 100KHz SCL has been expired Figure 2 20 Programming Sequence for I2C Current Address Read 2 88 Computer Group Literature Center Web Site I2C Interface Page Write The IC page write is initiated the same as the PC byte write but instead of sending a stop sequence after the first data word the C master controller will transmit more data words before a stop sequence is generated The first step in the programming sequence should be to test the CMP bit for the operation complete status The next step is to initiate a start sequence by first setting the STA and ENA bits in the I2COx Register and then writing the device address bits 24 30 and write bit bit 3120 to the I2TDx Register The CMP bit is automatically cleard with the write cycle to the IZTDx Register The I2STx Register must now be polled to test the CMP and ACKI bits The CMP bit becomes set when the device address and write bit have been transmitted and the ACKI bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the initial word address will be loaded into the I2TDx Register to be transmitted to the slave device Again CMP and ACKI bits must be tested for proper response After the initial word address is successfully transmitted the first data word loaded into the IZTDx Register will be transferred to the in
351. sistet iisssssicssscsassasassdssninaniaianiatsonin 3 99 MP 120 Inbound Free _ list Tail Registers eer essence rre bcd bra iei 3 100 MP I20 Inbound Post list Head Register issisissssssissursssescssessasusosiacsiaassans 3 100 MP 20 Inbound Post Bst Tail Baotster sceccee re ee ix sep tend tirs pesrenes 3 101 MP DO CODnOS PUN seem pese x pid PUN S tUe ep EUL hU ME QUII MALUM DE CI DM 3 102 MP 120 Querne Base unro 3 103 ENIBE Bagger GOUD esc R 3 103 MP 120 Interrupt Statis este siostre poto ei eid St bh intr in etie 3 103 MP I0 Interrupt Mask SP 1 seeeesetetupt Vnd pud iy kaana 3 104 MP PX Inbound Queue Register eaten tee teb RR PR Pop FH o tp S een Oo C eA 3 104 MP I20 Outbound Queue Register vsissscicssscsssssnnsaxasiassosransasascesaciaacssanssaants 3 105 MP Generic Outbound Message 0 and 1 Registers 3 106 MP Generic Outbound Doorbell Registers eise sssi epa sak cd t de depen 3 106 MP Generic Inbound Message 0 and 1 Registers 3 107 MP Generic Inbound Doorbell Register 12 rise ttbi deban b pe Ed adds 3 108 MP Generic Intectupt Staus BESISBE secara 3 109 MP Genenc Interrupt Mask Resisber ssiccccasssinssnsesasisssinsassassesaasciiadiardsseass 3 110 MP Generic Outbound Doorbell Mask Remister usesse mets 3 111 Multi Pr c ssor Interrupt Controller iiie ssspn RR MeL E CUIR A QULA E AMEDEO QA a 3 112 ACSR Auc gt
352. so generated This bit and the associated interrupt may be cleared by writing a one to this field OMIO Outbound Message Interrupt 0 If set an outbound message has been written by the processor into the MGOMO register If the MGMS register allowed it a PCI interrupt was also generated This bit and the associated interrupt may be cleared by writing a one to this field http www motorola com computer literature 3 109 Programming Model MP Generic Interrupt Mask Register Offset PMEP 124 fame GEG GEGEE GEGGEGEE EEEGEGEE GEERGGEE bias Name Generic Operation R R R Reset 00 00 00 adddddad The MP Generic Interrupt Mask Register MGMS is used for controlling the assertion of exceptions associated with outbound message passing registers MGOMO and MGOM1 The fields within the MGMS register are defined as follows OMIM1 Outbound Message Interrupt Mask 1 This bit controls the masking of the MGOM1 register interrupt If this bit is cleared a write to the XCSR MGOM1 register by the processor will generate a PCI interrupt If set no interrupt will be generated OMIMO Outbound Message Interrupt Mask 0 This bit controls the masking of the MGOMO register interrupt If this bit is cleared a write to the XCSR MGOMDO register by the processor will generate a PCI interrupt If set no interrupt will be generated 3 110 Computer Group Literature Center Web Site Message Passing MP Generic Ou
353. space The fields within the MBAR register are defined as follows MBAR MPIC Base Address Register This field holds the base address of the XMPI Register Group This group may be located anywhere in PowerPC address space on any 256KByte boundary ENA Enable This field controls the visibility of the XMPI Register Group Setting this field to a one will enable the XMPI Register Group to be seen starting at the base address specified by the MBAR field Computer Group Literature Center Web Site Multi Processor Interrupt Controller Clearing this bit makes the XMPI Register Group inaccessible This field powers up cleared meaning the XMPI Register Group is not visible until programmed by the processor MPIC Control and Status Interrupt Request Sample Registers Offset XCSR 0E4 Bit Name Function Reset Operation cad s a ecd ed ea az 00 g g i DE B B aqdqdad FFFF The MPIC Control and Status Register MCSR provides various control and status of the MPIC function The field within the MCSR register is defined as follows OPI OpenPIC Interrupt If set the Harrier generated interrupts will be passed on to the MPIC If cleared the Harrier generated interrupts will be passed on to the IRQO_ pin Note that the MPIC can only drive the IRQx_ lines therefore if this bit is cleared then MPIC is essentially disabled The MPIC Interrupt Request Sample Register MIRS is used t
354. ster EEINT provides an array of interrupt enable bits pertaining to the various Error Exceptions that the Harrier can generate The fields within the EEINT register are defined as follows PMA PCI Master Abort If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PMA bit is set If cleared an interrupt will not be generated 3 180 Computer Group Literature Center Web Site Exceptions PTA PCI Target Abort If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PTA bit is set If cleared an interrupt will not be generated PAP PCI Address Parity Error If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PAP bit is set If cleared an interrupt will not be generated PDP PCI Data Parity Error If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PDP bit is set If cleared an interrupt will not be generated PDT PCI Bus Delayed Transaction Time out If set an interrupt will be generated through the Harrier MPIC whenever the EEST PDT bit is set If cleared an interrupt will not be generated PSE PCI SERR If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PSE bit is set If cleared an interrupt will not be generated PPE PCI PERR If set an interrupt will be generated through the Harrier s MPIC whenever the EEST PPE bit is set If cleared an interrupt will not
355. t Bus One Beat Write Transaction in Hawk AU nis a No o M 2 106 Figure 2 34 Power Up Reset Timing Timing Group 1 sess 2 137 Figure 4 1 Timing Definitions Jor Table 4 1 a eaeaeeseseskkubes tinis b RH ph Kad t u eia ada q 4 3 List of Tables Table 2 1 PoswerPC PCT Clocking OQpEOfns eae entere rato pn respeta ttt ner no etna hai 2 2 Table 2 2 SDRAM Single and Multi Bit Error Reporting esse 2 0 Tobie 2 Map Decoder ale li soci ENS 2 29 Table 2 4 PPC Master Transaction Profiles and Starting Offsets 2 34 Table 2 5 Memory and VO AttriDMES a opripin FIDE t et tede tno sor h et enis 2 37 Tabla 2 6 Con prado Device Decode aes anl puente nS a UAE ht a 2 40 Tabla 2 7 Harrier Read Absad OPLOS Lacie egerunt ainia 2 42 Table 2 8 DMA Controller Linked List Descriptors eese 2 56 Table 2 9 Xport Bus Address Mapping Looeeeseecnisckusgrtikk iE rH EE HUE R E ttbi 2 107 Tabla 2 10 Xport Bus XAD Mapping Lee perpe niania tta Pha tS PER ER HAE aA 2 108 Table 2 11 Hawk Compatible Address Mapping 2 eene 2 109 Table 2 12 8 but Device Byte Lane Mappa uioeescnbietenibai eia ed eM nnda UE ME ERE IE 2 111 Tabla 2 13 16 bit Device Byte Lane Mappitfi iue ues een nus trn tt npa ania pinna EE stan 2 111 Table 2 14 Hawk Data Compatibility Byte Lane Mapping 2 111 Table 2 15
356. t IMbyte of the bank d Ifthetest fails disablethe bank clear its size to OMbytes disable it and then repeat steps a d with the next bank If the test passes go ahead and use the 1st 1M of the bank 2 Using the IC bus determine which memory banks are present Using the addressing scheme established by the board designer probe for SPDs to determine which banks of SDRAM are present SPD byte 0 could be used to determine SPD presence SPD Byte 5 indicates the number of SDRAM banks that belong to an SPD 3 Obtain the CAS latency information for all banks that are present to determine whether to set or to clear the XCSR SDTC CL3 bit For each SDRAM bank that is present a Check SPD byte 18 to determine which CAS latencies are supported http www motorola com computer literature 5 3 Programming Considerations 5 4 b IfaCAS_ latency of 2 is supported then go to step 3 Otherwise aCAS latency of 3 is all that is supported for this bank c IfaCAS latency of 2 is supported check SPD byte 23 to determine the CAS latency 2 cycle time If the CAS latency 2 cycle time is less than or equal to the period of the system clock then this bank can operate with a CAS latency of 2 Otherwise a CAS_ latency of 3 is all that is supported for this bank If any bank does not support a CAS latency of 2 then XCSR SDTC CL3 is to be set If all of the banks do support a CAS latency of 2 then the XCSR SDTC CL3 bit is to be cleared Do
357. t processor If the interrupt is programmed to be edge sensitive the IPR bit is cleared when the vector for that interrupt is returned when the Interrupt Acknowledge register is examined On the other hand if the interrupt is a direct multicast class interrupt there are two bits in the IPR associated with this interrupt One bit for each processor Computer Group Literature Center Web Site Multiprocessor Interrupt Controller MPIC Then one of these bits are delivered to each Interrupt Selector Since this interrupt source can be multicast each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor If one of the following sets of conditions are true the interrupt pin for processor 0 IRQO is driven active a Setl The source ID in IRR O is from an external source The destination bit for processor 1 is a O for this interrupt The priority from IRR O is greater than the highest priority in ISR 0 The priority from IRR O is greater than the contents of task register 0 a Set2 The source ID in IRR O is from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR O is not present is ISR 1 The priority from IRR O is greater than the highest priority in ISR 0 The priority from IRR O is greater than the Task Register O contents The contents of Task Register O is less than the
358. tbound Doorbell Mask Register Offset PMEP 128 Bit Name Function Generic The MP Generic Outbound Doorbell Mask Register MGODM is used for individually masking outbound doorbell interrupts from the processor to PCI The fields within the MGODM register are defined as follows ODBMx Outbound Doorbell Mask Writing a zero to a particular bit position will enable the generation of the associated outbound doorbell interrupt Writing a one will mask the interrupt http www motorola com computer literature 3 111 Programming Model Multi Processor Interrupt Controller The Multi Processor Interrupt Controller has registers located within two register groups A majority of the control and status registers are located within PowerPC address space as a part of the XMPI Register Group Some additional control and status including the relocation of the XMPI Register group is located within PowerPC address space as part of the XCSR Register Group XCSR Register Group The following subsections describe the registers in the XCSR Register Group MPIC Base Address Register Offset Bit Name XCSR 0E0 GEREEERE GEEEGEEE EEGEGGEGGGGEGGEE Maas MBAR 4 MPIC Operation Reset 0000 ad 00 00 3 112 The MPIC Base Address Register MBAR is used to control the mapping of the XMPI Register Group within PowerPC address
359. te of the prescaled UART crystal clock and the UART clock selection The fields within the UCTL register are defined as follows UOGRT UART 0 Gated Request To Send This bit when high indicates RTSO is active low and the UART 0 receiver FIFO contains less than 14 characters Used as Hardware Flow Control Request To Send signal U1GRTS UART 1 Gated Request To Send This bit when high indicates RTS1_ is active low and the UART 1 receiver FIFO contains less than 14 characters Used as Hardware Flow Control Request To Send signal UOTXP UART 0 Transmitter Pause When set the UART 0 will hold subsequent transmissions after the current character is completely transmitted Used as Hardware Flow Control signal from receiving device UITXP UART 1 Transmitter Pause When set the UART 1 will hold subsequent transmissions after the current character is completely transmitted Used as Hardware Flow Control signal from receiving device XTAL64 Prescaled UART Crystal Oscillator Output This bit represents the logic state of the external internal UART crystal clock divided by 64 http www motorola com computer literature 3 147 Programming Model 3 148 UCOS UART Clock Select This bit is used to select the clock source for both UARTS as shown in the following table Table 3 42 UART Clock Selection XAD 29 UCOS UART Clock 0 0 default external 0 1 internal 1 1 always internal The UART Clock Prescale
360. ted SSC SDRAM Memory Controller Single Bit Error Count Overflow If set a machine check to processor 0 will be generated whenever the EEST SSE bit is asserted If cleared a machine check to processor 0 will not be generated SMX SDRAM Memory Controller Multi Bit Error on PowerPC Access If set a machine check to processor 0 will be generated whenever the EEST SMX bit is asserted If cleared a machine check to processor 0 will not be generated SMS SDRAM Memory Controller Multi Bit Error on Scrub If set a machine check to processor 0 will be generated whenever the EEST SMS bit is asserted If cleared a machine check to processor 0 will not be generated XBT PowerPC Bus Time out If set a machine check to processor 0 will be generated whenever the EEST XBT bit is asserted If cleared a machine check to processor 0 will not be generated XAP PowerPC Bus Address Parity Error If set a machine check to processor 0 will be generated whenever the EEST XAP bit is asserted If cleared a machine check to processor 0 will not be generated Computer Group Literature Center Web Site Exceptions XDP PowerPC Bus Data Parity Error If set a machine check to processor 0 will be generated whenever the EEST XDP bit is asserted If cleared a machine check to processor 0 will not be generated XDT PowerPC Bus Delayed Transaction Time out If set a machine check to processor 0 will be generated whenever the EEST XDT bit is assert
361. ted by the PowerPC Arbiter In a multiprocessor environment these bits allow software to determine on which processor it is currently running Table 3 59 GCSR MID Encoding MID PowerPC Data Bus Master 00 CPUO 01 CPUI 10 EXTL 11 Harrier Computer Group Literature Center Web Site Miscellaneous Functions RAT Ratio This is a read only field that is used to indicate the PowerPC to PCI clock ratio that has been established by the Harrier at the release of reset The encoding of this field is show in the following table Table 3 60 GCSR RAT Encoding RAT PowerPC PCI clock ratio 000 Undefined 001 1 1 010 2 1 011 3 1 100 3 2 101 Undefined 110 5 2 111 Undefined PowerPC Clock Frequency Register Offset XCSR 014 Bit d moo i o OVO g i o ea oj o Function Name XCFR Control Operation R W R R R and Status Reset 64 00 00 00 The PowerPC Clock Frequency Register XCFR should be programmed with the hexadecimal value of the operating clock frequency in MHz e g 64 for 100 MHz When these bits are programmed this way the chip s prescale counter produces a 1 MHz approximate output The output of the chip prescale counter is used by the refresher scrubber and the 32 bit counter After power up this register is initialized to 64 for 100 MHz The formula is Counter Output Frequency Clock Frequency XCFR http
362. ted control and status registers see the section titled SDRAM Interface on page 3 25 The following sections describe the SDRAM interface s major blocks and functions PowerPC Bus Slave The PowerPC bus slave works closely with the SDRAM controller to provide low latency and high throughput access to SDRAM The slave responds to all transfer sizes and responds to most transfer types Responding to Address Transfers When the PowerPC slave responds to an address transfer it asserts AACK immediately if no previous data tenure is in process If a data transfer is in process the slave waits and asserts AACK when the transfer completes Completing Data Transfers If an address transfer has an associated data transfer the SDRAM controller starts an access to SDRAM as soon as it completes all previous SDRAM activity If the data transfer is a read the PowerPC slave starts transfering data to the PowerPC bus as soon as the SDRAM controller has data ready and the PowerPC data bus is available If the data transfer is a write the PowerPC slave starts latching data from the PowerPC bus as soon as any previously latched data is no longer needed and the PowerPC data bus is available Cache Coherency The PowerPC slave supports cache coherency to SDRAM by monitoring and responding to the ARTRY_ signal When ARTRY asserts if the access is an SDRAM read the PowerPC slave does not source the data for that access If the access is an SDRAM write
363. ter Upon reset this bit is set to a one indicating this resource is prefetchable BASE Base Address These bits define the memory space base address of the Inbound Translation Function Note that the actual number of writable bit positions depends on the size of the resource http www motorola com computer literature 3 63 Programming Model being offered The size of a resource can be changed using the ITSZx register Table 3 24 shows the relationship between resource size and the BASE field This field is accessible only when the ENA bit is set in the ITATx register The relationship of a writable and non writable bit is maintained regardless of whether an access is from within the PCFS or XCSR Register Groups Note that the BASE field is byte swapped when accessing from the XCSR Register Group For example programming a base address of 12345 within the PCFS Register Group is the same as programming 53412 within the XCSR Register Group Table 3 24 BASE Encoding and Resource Size Resource ITSZx Effects on BASE Field PCFS Register Group Size W gt Writable Bit Position 0 gt Fixed Zero Bit Position IRR S RRRS R R R R S S 5 8 8 X 2 9 4KB 00 WwW WwW WwW WwW WwW WwW WW w WW W ww ww w w ww 8KB 01 WwW wW WwW WwW WwW wW WwW wW w w Ww WW w ww w wwo 16KB 02 WwW wW WwW WwW wW wW WwW w www w w
364. the PARB register Parking can be programmed for any of the requestors last requestor or none The default setting for parking is park on the Harrier The following table describes all available settings for the PRK field Table 2 20 PRK Encoding PRK Function 0000 Park on last requestor 0001 Park on PARB6 0010 Park on PARB5 0011 Park on PARB4 0100 Park on PARB3 Computer Group Literature Center Web Site Arbiters Table 2 20 PRK Encoding Continued PRK Function 0101 Park on PARB2 0110 Park on PARBI 0111 Park on PARBO 1000 Park on HARR 1111 Parking disabled Notes 1 1000 is the default setting 2 Parking disabled is a testmode only and should not be used since nothing will drive the PCI bus when it is in the idle state 3 All combinations of PRK not specified in the table are invalid and should not be used A special function is added to the PCI Arbiter to hold the grant asserted through a lock cycle When the POL field in the PARB register is set the grant associated with the agent initiating the lock cycle is held asserted until the lock cycle is complete If this field is clear the PCI Arbiter does not distinguish between lock and non lock cycle http www motorola com computer literature 2 119 2 Functional Descriptions Watchdog Timers 2 120 The Harrier features two watchdog timers called Watchdog Timer 0 WTO and Watchdog Timer 1 WT
365. the inbound and outbound ports For example a write by a PCI master to the MIIQ register will automatically increment the Inbound Post list Head MIIPH register The automatic actions taken for each pointer register are designated by a symbol in the previous figure Those registers that do not have the symbol next to it must be manually maintained by the processor IMU Queue Structure In order for hardware to correctly maintain the pointers the FIFO sizes and locations must be known The Message Passing IO Queue Base Address MIQB register within the XCSR Register Group is used to specify the base address within PowerPC address space of the entire inbound and outbound queue structure This is a IMB structure locatable only on 1MB boundaries Within this structure is four FIFOs The base address of each FIFO is on one of four 256 KByte boundaries as shown in the following figure http www motorola com computer literature 2 63 Functional Descriptions Outbound Post list FIFO Allocation Outbound Free list FIFO Allocation Inbound Post list FIFO Allocation Inbound Free list FIFO Allocation IMU Enable 2 64 FIFO QSZ a QBA 768 KBytes FIFO QSZ l lt a QBA 512 KBytes FIFO QSZ i amp QBA 256 KBytes FIFO Queue Size QSZ a amp Queue Base Address QBA Figure 2 16 IMU Queue Structure Each FIFO is the same size The size of the FIFOs
366. the transaction and a new entry is not posted http www motorola com computer literature 2 31 Functional Descriptions Inbound FIFO 2 32 a The Harrier proceeds to service the delayed transaction to completion While doing so the PCI master is continuously re attempting the transaction Each time the transaction is re attempted the Harrier waits for the expiration of the initial latency period before issuing a disconnect retry a If another PCI master attempts a read from the Harrier while the Harrier is currently processing a delayed read transaction the Harrier does not wait for the expiration of the initial latency period but immediately issues a disconnect retry 4 The PPC Master is primarily responsible for completing the delayed transaction by filling the Inbound FIFO from the PowerPC bus a The PCI Slave is notified by the PPC Master upon completion of the transaction at which time the PCI Slave is ready to close out the delayed transaction The PCI Slave will wait for the PCI master to once again retry the transaction The PCI Slave will validate the address and attributes of the current PCI bus cycle with those of previously accepted delayed transaction bus cycle If there is a match then the PCI Slave will complete both the address tenure and the data tenure At this point a delayed transaction is considered complete The Harrier s delayed read mechanism only guarantees the completion of the first data beat
367. the signals named XA represent all XADR signals and any XAD signals that are configured as address signals only The first few examples are for the simplest case in which the Xport Bus master requires only one beat to transfer the requested data The following figure shows a one beat read with XCSR XPAT BAM cleared http www motorola com computer literature 2 97 Functional Descriptions AD inserts 0 15 CLK s here eK AVIS XCSx M a oh XA DX addres X XAD X address gt lt dat MALE ose Yelle c x X46 XWAIT __ A Data latching edge Figure 2 24 Xport Bus One Beat Read Transaction The following figure shows two back to back one beat write transactions with XCSR XPAT BAM cleared 2 98 Computer Group Literature Center Web Site XPORT m d AD inserts 0 15 CLK s here BT cuc DDO eee WES NEEM CIE ME M NE NEN AM DE XA 488 ss c i dios x XAD x lt aleress d gt was te X0 a eee ee mag CEIESET XWAIT JN Figure 2 25 Xport Bus Two One beat Write Transactions When multiple data beats need to transfer during a single transaction the Xport Bus master increments the address after each beat If writing the master also regenerates WE for each beat If bursting is off the master uses XCSR XPAT AD as the access time for all data beats If bursting is on the master uses XCSR XPAT B
368. three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel
369. tial retry attempts If this field is enabled and the maximum number of sequential retries is exceeded then an error exception is generated and the transaction is aborted If this field is cleared then there is no limit to the number of retry attempts Note that this field must remain cleared to be fully PCI Local Bus compliant DRQ Disregard REQ64_ Qualification This field is used to modify the qualifications that the PCI slave makes when determining whether or not a transaction is considered part of a previously disconnected delayed transaction If this field is set the PCI slave does not consider the latched state of REQ64_ as part of the qualification If the field is cleared then the state of REQ64_ must be matched exactly in order to be qualified as the continuation of a delayed transaction Note that this field must remain cleared to be fully PCI Local Bus compliant http www motorola com computer literature 3 39 Programming Model PIM PCI Interrupt Mapping These bits indicate which PCI interrupt signal line a Harrier generated PCI interrupt is routed to The options available are shown in follwing table Table 3 17 BPCS PIM Encoding PIM PCI Interrupt D 11 INTD_ CSM Configuration Space Mask This field controls the visibility of the Harrier s PCI configuration space located above the predefined 64 byte header Specifically visibility is affected from offset 40 to offset FF within the PCFS Register Group Ac
370. tion CSMA CD Access Method and Physical Layer Specifications Institute of Electrical and Electronics Engineers Inc http standards ieee org catalog Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 1 Specification PCI Special Interest Group http www pcisig com Interface Between Data Terminal Equipment and Data Circuit Terminating TIA EIA 232 Standard Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Alliance http www eia org PowerPC Reference Platform PRP Specification MPR PPC RPU 02 Third Edition Version 1 0 Volumes I and II International Business Machines Corporation http www ibm com A 4 Computer Group Literature Center Web Site Related Documentation Table A 3 Related Specifications Continued Document Title and Source PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR Morgan Kaufmann Publishers Inc Telephone 415 392 2665 Telephone 1 800 745 7323 http www mkp com books_catalog Publication Number ISBN 1 55860 394 8 VITA 32 199x Processor PMC Standard for Processor PMC Mezzanine Cards VITA Standards Organization http www vita
371. tributed Harrier Internal Error Interrupt The Harrier detected error exceptions are grouped together and sent to the MPIC interrupt logic as a singular interrupt source Harrier Internal Error Interrupt This Harrier internal error interrupt request is an active low level sensitive interrupt The interrupt delivery mode for this interrupt is distributed When the MCSR OPI bit is cleared the Harrier internal functional interrupt and the Harrier internal error interrupt are combined and directly passed on to IRQO pin For system implementations where the MPIC controller is not used the combined Harrier Internal Interrupt is made available by a signal that is external to Harrier Presumably this signal would be connected to an http www motorola com computer literature 2 71 Functional Descriptions Timers externally sourced interrupt input of an MPIC controller in a different device Since the MPIC specification defines external I O interrupts to operate in the distributed mode the delivery mode of this interrupt should be consistent A divide by eight pre scaler is synchronized to the PowerPC bus clock The output of the prescaler enables the decrement of the four timers The timers may be used for system timing or to generate periodic interrupts Each timer has four registers which are used for configuration and control They are a Current Count Register a Base Count Register 4 Vector Priority Register a Destination R
372. ture the address and attributes corresponding to the erroneous transaction in the EXAD register and EXAT register respectively If any PowerPC error is detected while any other PowerPC error status bit is already set the PowerPC overflow EEST XOF bit will be set in the EEST register and further logging of PowerPC errors is suspended until software clears the first error and the PowerPC overflow bit The PowerPC overflow bit in the EEST register is set to prevent the Harrier from updating EXAD and EXAT registers in the event of additional errors Thus the information related to the first erroneous transaction is latched until the error status bit is cleared by writing to EECL register Similarly in the event of a PCI master abort PCI target abort PCI address parity error PCI data parity error or PCI delayed transaction time out the corresponding PCI error status bit will be set in the EEST register if the corresponding error is enabled EEEN register any other PCI error status bit is not set In addition the Harrier will capture the PCI address and attributes corresponding to the erroneous transaction in the EPAD register and EPAT register respectively If any PCI error is detected while any other PCI error status bit is already set the PCI overflow EEST POF bit will be set in the EEST register and further logging of PCI errors is suspended until software clears the first error and the PCI overflow bit The PCI overflow bit in the EEST re
373. ty of the XCSR MPBAR register is unaffected by the ENA field GBL Global If set the GBL_ pin will be asserted for each PowerPC transaction indicating the transaction may be snooped by the processor If cleared the GBL_ pin is not asserted and the transaction is not snooped Inbound Translation Size Offset 0 1 2 and 3 Registers Perspective from the PCI Bus Offset ITSZO ITOFO PCFS 48 ITSZV ITOFI PCFS 50 ITSZ2 ITOF2 PCFS 58 ITSZ3 ITOF3 PCFS 60 Bit d ood c vu e o oq d AN od jl acl ss c Function Name ITOFx ITSZx Address Operation R W R R W Transla tion Reset 0000 00 00 http www motorola com computer literature 3 69 Programming Model Perspective from the PowerPC Bus Offset ITSZO ITOF0 XCSR 348 ITSZ1 ITOF1 XCSR 350 ITSZ2 ITOF2 XCSR 358 ITSZ3 ITOF3 XCSR 360 Bit Eum d M Name ITSZx ITOFx Operation R W R R W Reset 00 00 0000 Function Reflected PCI Configur ation Space The Inbound Translation Size Registers ITSZ0 ITSZ1 ITSZ2 and ITSZ3 establish the size of a resource offered by an Inbound Translation Function The value selected within this register determines the characteristics of the ITBARwx registers Valid selections for a resource size are shown in the table below Table 3 26 ITSZx Encoding ITSZx Resource ITSZx Size Resource Size 09 2MB 14 FF Reserved 0A 4
374. ub dbyR PPM ELEME A 4 xiv List of Figures Figure 1 1 Typical Harrier System Implementation erento 1 4 Peor 2 Hamer Block b ru n c 1 7 Figure 2 1 Block Diagram ot PLL Implementation 1er npe rar then attention 2 1 Figure 2 2 PowerPC and PCI Clock Relationships ssssccsssssvatesadeecssuisdeisinieieiidaiagaicine 2 3 Figure 2 3 SDRAM Interface Block Dinprami ccicevisissoosssecencstecscstarcdasssnsntssesnessniien 2 4 Figure 2 4 Harrier PowerPC PCI Data Flow Naming Convention 2 11 Figure 2 5 PowerPC to PCI Bridge Block Diagram suenan nha atto tine Ree SK Sinka 2 13 Figure 2 6 Outbound Address Decoding i ccscicsnsissinstispansssntsnane Ae ea eto US ROnE e tup r RA RR UE 2 15 Lungo 2 7 Ontbound Address Translatio iessen 2 16 Figure 2 8 Inbound Address DOING iui oense sienne Een eS ePPHEB E SHnEaRU MAE RN RUE pd p 2 27 Figure 2 9 Inbound Address Translation sais isiscstsaissasainnioucsreesdeonvasssasceasnsiniadaialeienss 2 29 Figure 2 10 Spread IAD Adqddpess Teste Ia wisccisastvncinriniimnaniesanasianiannicsercentectiasass 2 38 Figure 2 11 Big Endian Little Endian Data Swap euet iea toten tret ne Pai 2 46 Figure 2 12 DMA Controller Block DISErak 2222222 p rbtPbabbEhlt pli UU Roda DAP ad L MAL ptd 2 49 Figure 2 15 DMA Controller Operating MOdG BS iiissierien eterni raodo 2 51 Figure 2 14 Examples or Pattern WINES Loser imadikis rti obla teg cipe nuda 2 55 Fiene s13 AF C oo L AE 2 62 F
375. ull duplex serial ports to support communication with modems or other serial peripheral devices This interface is compatible with the standard National Semiconductor 16550 UART For detailed information on the functionality and programming model refer to the BM Universal Asynchronous Receiver Transmitter with FIFOs For SS SSE SA 12E and National Semiconductor PC16550D Universal Asynchronous Receiver Transmitter with FIFOs documents The UART control and status registers are described in the section titled UART Controller on page 3 136 The Xport is a bridge that interfaces the PowerPC bus to an expansion bus named Xport Bus Xport Bus is the set of signals the Harrier uses to control devices that have a simple static RAM style interface Such devices might include flash ROM control registers and FIFO s A PowerPC bus slave and an Xport Bus master constitute the most significant blocks that make up Xport The following figure shows a simplified block diagram Computer Group Literature Center Web Site XPORT Xport Bus Ctrl PowerPC Ctrl Xport Bus PowerPC Master Slave Xport Bus PowerPC Ado iea Xport Bus Addr Dec amp Latch Address Out PowerPC Data powerpc Xport Bus Data In Address amp R M Data Out Reg amp Mux Mux Reg PowerPC Xport Bus Data Out Data In Reg Reg Xport Bus Data Addr Figure 2 23 Xport Block Diagram The Po
376. upt Router 2 76 RWCB Read Write Checkbits SDRAM General Control Register SDGC 3 26 S SCCNT Scrub Counter SDRAM Scrub Control Register SDSC 3 32 SCON 2 132 SCPA Scrub Prescaler Adjust SDRAM Scrub Control Register SDSC 3 32 scrub cycles SDRAM Scrub Control 2 10 SCWE Scrub Write Enable SDRAM Scrub Control Register SDSC 3 32 SDER SDRAM External Registers or Buff ers SDRAM Timing Control Register SDTC 3 29 SDMEA SDRAM Multi bit Error Address SDRAM Multi bit Error Address Regis ter SDMEA 3 37 SDRAM control registers 5 1 initializing 5 1 interface characteristics 2 4 performance summary 4 1 refresh period 5 1 setting base address 5 2 size configuration 5 2 speed attributes 5 1 SDRAM accesses four beat Reads Writes 2 6 IN 6 single beat Reads Writes 2 6 SDRAM Bank Addressing Registers 3 30 SDRAM control registers initializing 5 3 SDRAM Controller operating characteristics 2 6 SDRAM ECC 2 7 SDRAM General Control Register SDGC 3 25 SDRAM interface function described 1 4 SDRAM Multi bit Error Address Register SDMEA 3 37 SDRAM Multi bit Error Status Register SDMES 3 36 SDRAM Scrub Address Counter SDSA 3 33 SDRAM Scrub Control Register SDSC 3 32 SDRAM Single bit Error Status Register SDSEA 3 36 SDRAM Single bit Error Status Register SDSES 3 34 SDRAM sizing optional method 5 3 5 9 SDRAM Timing Control Register 3 27 SDSA SDRAM Scrub Address SDRAM Scrub Address Counter SD SA
377. ush is caused by normal address or data flow events The following events are considered Mandatory Flush Events a An outbound read transfer size other than an aligned 32 bit word Q An outbound read from a non contiguous address including byte misalignment of an existing collection a An outbound write cycle a An outbound read of any size or address from a processor other than the one responsible for the current collection There are two Optional Flush Events the Read Ahead Backup Timer and the Read Ahead Sync Flush The Read Ahead Backup Timer is a programmable timer that watches for large gaps of time between contiguous address reads The timer is reset anytime a read is performed Computer Group Literature Center Web Site PowerPC to PCI Bridge on read ahead enabled mapped region If the next address read is not made before the timer times out the current read ahead command is closed and the Outbound FIFO is cleared The timer may be disabled if so desired The characteristics of the Read Ahead Timer apply globally to all applicable outbound traffic and is determined by the RBT field within the BXCS register The Read Ahead Sync Flush is an option that will close the read ahead command and clear the Outbound FIFO whenever the PPC Slave detects a Sync bus cycle from the processor responsible for the current read ahead This is also a globally programmable option and is controlled by the RSF field within the BXCS register
378. using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components h To prevent serious injury or death from dangerous voltages use extreme Flammability All Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers JN Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference EMI if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Disp
379. utbound MFA entries A Host may obtain interrupt status by reading the Message Passing IO Interrupt Status MIST register The Host may also control the masking of this interrupt through the Message Passing IO Mask MIMS register Both of these registers reside within the PMEP Register Group The IMU can also generate a processor interrupt This interrupt is routed to the MPIC and is asserted whenever there is a difference between the head and tail pointers for the Inbound Post list Queue This interrupt is an indication that the Host has placed a full MFA within the IOP s inbound queue The interrupt will remain asserted until the processor adjusts the head and tail pointers to match The processor may obtain interrupt status by reading the Functional Exception Status FEST register within the XCSR Register Group The processor can mask this interrupt through the Functional Exception Mask FEMA register IOP Agent Identification The IO specification has identified a special PCI class code for I 0 IOP Agents The class code is represented with the read only CLAS register within the PCFS Register Group The Harrier must present different class http www motorola com computer literature 2 65 Functional Descriptions codes depending on the level of IO participation The Harrier must present itself as a Bridge Device if not participating in I O or if it is participating as a IO Host If acting as an IOP then the Harrier must present
380. value The Device ID Register DEVI is a read only register that uniquely identifies this particular device The Harrier always returns 480B Command Status Registers Perspective from the PCI Bus Offset PCFS 04 puppis pep Name STAT CMMD Header ME 3 MEMSP Operation aye R W MSTR R V Reset So 9 9999 7 gqg79799909go9o9999999gqg9999974799g Perspective from the PowerPC Bus Offset XCSR 304 Bit Function Name Reflected PCI Configur ation Space Operation Reset 3 56 Computer Group Literature Center Web Site PowerPC to PCI Bridge The Command Register CMMD provides course control over the Harrier s ability to generate and respond to PCI cycles The fields within the CMMD register are defined as follows IOSP I O Space Enable If set the Harrier responds to PCI I O space accesses when appropriate If cleared the Harrier does not respond to PCI I O space accesses MEMSP Memory Space Enable If set the Harrier responds to PCI memory space accesses when appropriate If cleared the Harrier does not respond to PCI memory space accesses MSTR Bus Master Enable If set the Harrier may act as a master on PCI If cleared the Harrier may not act as a master PERR Parity Error Response This bit enables the PERR_ output pin
381. ver there is a corner case where this field affects the actions of the PPC Master during a cache line aligned referenced to the physical address in memory of the queue element PCI burst read from the MITQ MIOQ registers If this field is set the PPC Master performs a cache line read If this field is cleared the PPC Master performs a single beat read This field has little 1f any practical value since a majority of the MIIQ MIOQ reads from PPC memory are translated into single beat reads 3 68 Computer Group Literature Center Web Site PowerPC to PCI Bridge WPE Write Post Enable If set write posting is enabled on the PCI bus The Harrier will acknowledge a data transfer collect data from the PCI bus and forward that data on to local memory If cleared each write transaction is fully compelled The Harrier will write each PCI 32 bit or 64 bit beat as a single beat transaction on the PowerPC bus After each transaction a single acknowledge will be given to the PCI bus MEM Memory This read only field is hardwired to a one to indicate the PMEP Register Group may only be located within PCI memory space ENA Enable If set the Message Passing Function is enabled for read and write transactions Writes to the PCFS MPBAR register will be accepted and reads will return valid data If cleared the Message Passing Function is not enabled Writes to the PCFS MPBAR register will be discarded and reads will return all zeros The visibili
382. vity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set POL Polarity This bit sets the polarity for external interrupts Setting this bit to a zero enables active low or negative edge Setting this bit to a one enables active high or positive edge Only External Interrupt Source 0 uses this bit in this register For external interrupt sources through 15 this bit is hard wired to 0 SENSE Sense This bit sets the sense for external interrupts Setting this bit to a zero enables edge sensitive interrupts Setting this bit to a one enables level sensitive interrupts For external interrupt sources 1 Computer Group Literature Center Web Site Multi Processor Interrupt Controller through 15 setting this bit to a zero enables positive edge triggered interrupts Setting this bit to a one enables active low level triggered interrupts PRIOR Priority Interrupt priority O is the lowest and 15 is the highest Note that a priority level of O will not enable interrupts VECTOR Vector This vector is returned when the Interrupt Acknowledge register is examined when the interrupt associated with this vector is acknowledged External Source Destination 0 through 15 Registers Offset EXDEO XMPI 10010 EXDE1 XMPI 10030 efc EXDE14 XMPI 101D0 EXDE15 XMPI 101F0 Bit
383. w Operation Reset The Spurious Vector Register SPVE contains vector information for spurious interrupts The field within the SPVE register is defined as follows VECTOR Vector This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch Timer Frequency Register Offset XMPI 010F0 Function Name R W 00000000 Operation Reset The Timer Frequency Register TIFR is used to report the frequency in Hz of the clock source for the global timers Following reset this register contains zero System initialization code must initialize this register to one eighth the MPIC clock frequency PowerPC 60x bus clock frequency For the MPIC implementation of the Harrier a typical value would be BEBC20 which is 100 8 MHz or 12 5 MHz http www motorola com computer literature 3 119 Programming Model Timer Current Count 0 1 2 and 3 Registers Offset TICCO XMPI 01100 TICC1 XMPI 01140 TICC2 XMPI 01180 TICC3 XMPI 011C0 Bit Name Operation 4 R Reset Ss 00000000 The Timer Current Count Registers TICC0 TICC1 TICC2 and TICC3 are read only registers that return the current count value of the MPIC timers The fields within the TICCx registers are defined as follows T Toggle This bit toggles when ever the current count decrements to zero This bit is cleared when a value is written into th
384. w motorola com computer literature 2 61 Cc97C NS qo A 1931027 o1nje1ojrT dnour 1ojnduio yu eDessey dol Sr z enBiJ4 Bridge r Harrier r Outbound Queue Inbound Queue Port Delta PCI Interrupt Outbound Queue Post_list Pointers MIOPH Head Ki MIOQ Read MIOPT Tail Outbound Queue Free list Pointers MIOQ Write MIOFH Head MIOFT _ Tail Delta CPU Interrupt Inbound Queue Post_list Pointers MIIQ Write MIIPH Head MIIPT Tail Inbound Queue Free_list Pointers MIFH Head MIIQ Read MIIFT Tail Local Memory Post list FIFO z l ll Io ll ll ll Fog Tail Free list FIFO Post list FIFO I I I Tail Free list FIFO l l l l l l l l l l L as sea mts me i Message Frame Message Frame Message Frame Message Frame Message Frame Message Frame Message Frame Message Frame o uei er heel oer OS Weasel red ta a det inr uc vum uer ed e Eee a ee a reser ee er sed si suondiiosaq jeuonouny Message Passing All of the pointer registers are located within the XCSR Register Group These registers represent the head and tail pointers into PowerPC address space for the inbound and outbound Free list and Post list FIFOs Some of these registers are automatically updated by certain actions taken to
385. werPC bus slave has four address response ranges The Xport Bus master has four corresponding chip selects An address range with its corresponding chip select is referred to as a channel Each channel employs a combination of control registers and input signal pins to configure its address range and attributes The section titled Xport on page 3 150 details the control registers The section titled Hardware Configuration on page 2 133 explains the use of input signals The following two sections detail the PowerPC slave and Xport Bus master http www motorola com computer literature 2 95 Functional Descriptions PowerPC Slave The PowerPC slave provides an interface between the PowerPC bus and the Xport Bus master Each of the Xport s four channels is programmable with its own PowerPC bus address range and attributes The PowerPC slave uses a delayed transaction protocol for its response to PowerPC accesses For reads the PowerPC slave issues retry s until data is available For writes the PowerPC slave latches and acknowledges data immediately but issues retry s until the data is written The following paragraph gives more details about Xport Bus bound reads When an Xport Bus bound read begins the PowerPC slave responds with AACK and ARTRY and requests that the Xport Bus master obtain the data The slave continues to ARTRY_ Xport Bus bound accesses until data is obtained and the original PowerPC master comes back to get it
386. wledge cycles 2 41 PLL as part of clocking mechanism 2 1 operational characteristics 2 2 PMEP contents 3 23 PowerPC Address Bus Timer function described 1 6 PowerPC address bus timer 2 129 PowerPC Address Space role in inbound transactions 2 27 PowerPC bus internal arbiters 2 113 PowerPC bus masters 2 113 PowerPC Bus Slave relationship to SDRAM 2 5 PowerPC clock relation to PCI clock 2 2 http www motorola com computer literature PowerPC Control and Status Register Group 3 3 PowerPC Multi Processor Interrupt Control ler Register Group 3 14 PowerPC Parity function described 1 6 PowerPC to PCI Bridge 3 38 4 8 function described 1 4 inbound performance 4 9 operating characteristics 2 11 PowerPC to PCI Configuration Space XCFS Register Group 3 19 PPC Decode 2 14 PPC Master transfer modes role 2 33 PPC Slave as passive slave 2 23 delayed transaction protocol 2 17 role 2 16 PPMC signals 2 132 pre scaler use with timers 2 72 prescaler as part of watchdog timer 2 120 priority current task processor 2 69 priority scheme for PowerPC bus masters 2 114 PRK Encoding PCI bus 2 119 program visible registers 2 75 programming watchdog timers 2 120 programming considerations 5 1 R Random Read I2C 2 85 I2COx Register 2 85 read ahead mode 2 35 related documentation A 1 related specifications A 4 Xmuoz xmo z Index reset signals 2 131 reset state MPIC 2 79 resources Harrier 3 1 rule sets Interr
387. www motorola com computer literature 3 197 Programming Model For example if the Clock Frequency is 100 MHz and XCFR is 64 then the counter output frequency is 100 MHz 100 1 MHz When the CLK pin is operating slower than 100 MHz software should program XCFR to be at least as slow as the CLK pin s frequency as soon as possible after power up reset so that SDRAM refresh does not get behind It is okay for the software then to take some time to up XCFR to the correct value Refresh will get behind only when the actual CLK pin s frequency is lower than the value programmed into XCFR Count 32 bit Register Offset XCSR 018 Bit c d o ed o 9 i o cea ojo lt o od ogo o z Function Name CT32 Control Operation R W and Status Reset 00000000 The Count 32 bit Register CT32 is a 32 bit free running counter that increments once per microsecond if the XCFR register has been programmed properly CT32 is cleared by power up and local reset Note that when the system clock is a fractional frequency e g 66 67 MHz CTR32 will count at a fractional amount faster or slower than 1 MHz depending on the programming of the XCFR register 3 198 Computer Group Literature Center Web Site Miscellaneous Functions Miscellaneous Control and Status Register Offset XCSR 01c Bt 4 444444444d4sd343d32q4445 44485344834 7 Name MCSR Control and
388. y A non zero value on the outbound FIFO Outbound FIFO count is considered write posted activity If the read may not be accepted the PCI Slave will issue a disconnect retry to the PCI bus Endian Conversion The Harrier supports the natural Endian mode for each bus The PCI bus is inherently Little Endian and the PowerPC bus is inherently Big Endian All inbound and outbound data must be swapped such that all PCI resources appear as Big Endian from the perspective of the PowerPC bus http www motorola com computer literature 2 45 Functional Descriptions Conversely all PowerPC resources appear as Little Endian from the perspective of the PCI bus The figure below demonstrates this data swapping function E I e GN eS ie Xe Be A d d 4 A H E 5 8 3 Fn GB B amp B A BR 8 amp 8 B8 B po pi D2 D3 D4 Ds D6 D7 PowerPC Bus D7 D6 D5 D4 D3 D2 D1 DO 64 bit PCI Oo 00 0 c tT oO CO GD wv FT TF He 0 O QC Mo wr ax gk AP A AR ipn NO ww Fe cec He 3 QC A A A B8 8 8 RB R8 do x d d d d d d 9 8 9 3 8 9 8 a B 2 Q g DD A Q g amp 2 3 8 3 Ev An EI WEIN a 2 c Ter Tor Tos Ter vs Toe or PowerPC Bus 32 bit PCI tL oO Oo Pc N oO Pc z Ot PED LEE non A ODO G A a R8 z d 2 d Figure 2 11 Big Endian Little Endian Data Swap 2 46 Computer Group Literature Center Web Site PowerPC to PCI Bridge The Register
389. y Additional Clear Edge Status Status Level Error SDRAM Detection ofasingle EEST SSC SDSES EECL SSC Edge Memory bit error count XCSR Interface overflow Single Bit Error Overflow Error SDRAM Detection of a multi EEST SMX SDMES EECL SMX Edge Memory bit error during any SDMEA XCSR Interface PowerPC access Multi Bit Error on PowerPC Access Error SDRAM Detection of a multi EEST SMS SDMES EECL SMS Edge Memory bit error on a scrub SDMEA XCSR Interface Multi Bit Error on Scrub Error PCI Master Detection of a EEST PMA EPAD EPAT EECL PMA Edge Abort Master Abort with XCSR the Harrier as a PCI Bus Master Can be either a bridge or a DMA transaction Error PCI Target Detection of a EEST PTA EPAD EPAT EECL PTA Edge Abort Target Abort with XCSR the Harrier as a PCI Bus Master Can be either a bridge or a DMA transaction Error PCI Detection ofa parity EEST PAP EPAD EPAT EECL PAP Edge Address error during the XCSR Parity Error address phase of any PCI transfer involving any PCI bus master and target 2 124 Computer Group Literature Center Web Site Exceptions Table 2 22 Exception Summary Continued Category Exception Description Primary Additional Clear Edge Status Status Level Error PCI Data Detection ofa parity EEST PDP EPAD EPAT EECL PDP Edge Parity Error error during the data XCSR phase of any PCI transfer involving any PCI bus master and target Error
390. ze Resource PSSZ Effects on BASE Field XCSR Register Group Size W gt Writable Bit Position 0 gt Fixed Zero Bit Position ma HAIAIALASAlAlAlAlaAfafsalSjyslSlsSyA2yszyays 4KB 00 WwW wW WwW WwW WwW WwW www WwW WwW WwW WwW WwW Ww Ww www w 8KB 01 WwW wW WWW WW WW WWW W Ww w w www 0 WwW WwW WWW WW WW WWW WW ww w wd 0 WwW WwW WWW WW WW WWW ww ww w 0 0 0 ww www www we www WW ww do 0 04 0 WwW wW WWW www we www w w wo 07 0 04 0 WwW wwww www ww ww ww 0 0 07 0 04 0 www ww www ww ww wo 0 0 0 0 0 0 1MB 08 wW wW wW WW WW WW W IWIW 0 0 0 0 0 0 0 0 2MB 09 wW wW wW WW www ww wo 0 0 0 0 0 0 0 0 http www motorola com computer literature 3 49 Programming Model Table 3 21 BASE Encoding and Resource Size Continued Resource PSSZ Effects on BASE Field XCSR Register Group Size W gt Writable Bit Position 0 gt Fixed Zero Bit Position e N oo t No uv qT en N el e nN oo U No wv sT en N e en N N N N N N N N N 4MB sod w w w w ww w w w wlolojojojo ololo o o 8MB B w w W w w w ww wolololo lolojolojo lofo 16MB oc w w w w ww wwolojo lololololololo lolo 32MB oD w w w W WW wo oj ol 0 0 0 0 of o of of o o 64MB E w ww w wlwo

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