Home

USER`S MANUAL

1. 2 20 Skip COnditioMm Flags 9623 SG a 2 21 Cany ES 2 21 Chapter 3 Addressing Modes S S MERCIER Ir EY 3 1 Valles u ustusqa 3 3 Enable Bank Sell idis x ra ert ra ode deua REN E Eod 3 4 Select SB uuu umasa iit eic Coe MA aa aw DIR 3 5 DirecpandanhndirecPAddEessillg Ri tdi dent Dx ipsa Wa dara c Suqsu qa EUR DE 3 6 TeBIEJAOGIOSSIF Lbs tes Cu usui qasa E 3 6 AISI ametis eps a CREE tad Qe RM Eh Rr kei inpia UNDA ATEM ADU 3 8 9 SS SING D 3 10 S3C72N2 C72N4 P72N4 Table of Contents continued Chapter 4 Memory Map Sc TI 4 1 for Hardware Registers 4 1 mise 1 c 4 4 Chapter 5 SAM47 Instruction Set NEON site 5 1 5 1 Syrbols arid GomvellloflS sue E pede 5 6 ODecode De
2. Subsystem Clock Oscillator Characteristics Input OUTPUT CapacilanCe y aty tuya USO cae Electrical GralacteriSloS y u RAM Data Retention Supply Voltage in Stop Pin Descriptions Used to Read Write the Comparison of S3P72N4 and S3C72N2 C72N4 Features Operating Mode Selection 1 GC Electrical Characters UCS entener Power Selection Settings for TB72N2 4 Main clock Selection Settings for TB72N2 4 Sub clock Selection Settings for TB72N2 4 Using Single Header Pins as the Input Path for External Trigger Sources Page Number xvii List of Programming Tips Description Chapter 2 Address Spaces Denning vesrored usu f cau AERA REF e a Clearing Data Memory Banks 0 1 nemen mene menn nes Selecting the Working Register Initializirig Whe Stack Sub damus dota ska M OR Sha
3. 8 5 Chapter 10 Ports Gontang 10 3 Enabling and Disabling Port Pull Up 10 4 Chapter 11 and Timer Counters Basie TIMO T 11 6 JSng ihe VV 11 8 TCO signal Ourout TOS OO Pint 11 15 External TCLO Clock Output to the 11 16 Restano FSO Operat oM re 11 18 GO a wa 11 21 SING ANS ATTI D D IU 11 26 XX S3C72N2 C72N4 P72NA List of Register Descriptions Register Full Register Name Page Identifier Number BMOD Basic Timer Mode Register TE T T 4 6 CLMOD Clock Output Mode Register uuu uuu nuyu a REA 4 7 IEO IRQO INTO Interrupt Enable Request Flags 4 8 IE1 IRQ1 INT1 Interrupt Enable Request Flags Hm 4 8 IE2 IRQ2 INT2 Interrupt Enable Request Flags 4 9 IEB IRQB Interrupt Enable Request Flags 4 10 IETO IRQTO INTTO Interrupt Enable Request 05 4 11 IEW IRQW INTW Interrupt Enable Request 05 4 12 IMODO External Interrupt 0 INTO Mode
4. to Poms ELECTRONICS 5 15 SAM47 INSTRUCTION SET S3C72N2 C72N4 P72N4 Table 5 16 Program Control Instructions Binary Code Summary Continued operand T operand AR gt U gt A RRa aam A RRa 1 A Ra 5 16 Binary Code 11 8 SP 1 SP 7 0 lt SP 2 SP 3 EMB ERB SP 5 SP 4 SP lt 6 11 8 SP 1 SP PC7 0 SP 2 SP 3 PSW lt SP 4 SP 5 SP lt SP 6 11 8 lt SP 1 SP 7 0 lt SP 3 SP 2 EMB ERB lt SP 5 SP 4 SP lt SP 6 then skip A HL then L lt 1 1 skip if L OH lt gt HL then L L 1 skip if L OFH Operation Notation ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 17 Data Transfer Instructions Binary Code Summary Continued Operand Operation Notation Rain rene 1 ee oo 1 Fue ss uz as o 0 A HL HL 1 1 0 DA lt DA 1 a1 Ey EA lt RRb r1 lt ao 0 RRb lt EA Ex je B EA HL EA DA EA RRb JJ a T 3 HL A DA EA T gt gt T J RRb EA HL EA LDI
5. 7 1 7 2 151 and ISO Bit Manipulation for Multi Level Interrupt Handling 7 6 7 3 Standard Interrupt Priorities aa 7 7 7 4 Interrupt Priority Register 5 7 7 7 5 IMODO 1 and 2 7 8 7 6 Register Bil 1 as 7 10 7 7 Interrupt Enable and Interrupt Request Flag Addresses 7 12 7 8 Interrupt Request Flag Conditions and Priorities 00 02 7 13 8 1 Hardware Operation During Power Down Modes 8 2 8 2 Unused Pin Connections for Reducing Power Consumption 8 7 9 1 Hardware Register Values After 000 2 9 2 10 1 VO OVO VI DUIS 10 2 10 2 Port Pin Status During Instruction Execution 10 2 10 3 Port Mode Group P 0 Su 10 3 10 4 Pull Up Resistor Mode Register PUMOD 2 10 3 10 5 LMOD 7 and LMOD 6 Setting for Port 8 Output Control 10 4 10 6 Port 8 Pin Addresses and LCD Segment Correspondence 10 4 xvi S3C72N2 C72N4 P72NA Table Numbe
6. 1 4 1 3 Pim CMC UNE TYPE A c 1 7 1 4 PINAGIFCUIE Type AA PI 1 7 1 5 1 7 1 6 TYDE DP and ite sagu Eta S za 1 7 1 7 dGireui Type SEG COM 1 8 1 8 Pin Creu VDO Ts uy a AE 1 8 1 9 Pine Circuit iridis to oa oen Mie ea la Sas q on aac eA 1 8 2 1 ROM Address e iod sind esr os Gon iud eol isum 2 2 2 2 Vector Address truc acutae a 2 2 2 3 Data Memory RAMI Mab uad 2 6 2 4 WONO Register MaD RET 2 9 2 5 Register Pair s dom edu 2 10 2 6 1 Bit 4 Bit and S Bit Accumulator e ass 2 11 2 7 Stack 2 14 2 8 Pop Type Stack OperallOfls tU ette RD 2 15 3 1 RAM Address Gasotubi dus 3 2 3 2 SMB and SRB Values in the SB Register 3 5 4 1 mizeliiigiBI i re dien o ne eee E TE 4 5 6 1 Glocke Ie E DIA GIA
7. C Examples 1 Bit location 30H 2 in the RAM has a current value of logic one The following instruction clears the third bit in RAM location 30H bit 2 to logic zero BITR 30H 2 30H 2 lt 0 2 You can use in the same way to manipulate port address bit BITR P2 0 2 0 0 ELECTRONICS 5 31 SAM47 INSTRUCTION SET BITHR sit Reset BITR Continued Examples LD BP2 BITR INCS JR 53 72 2 72 4 72 4 Assuming that P2 2 P2 3 and P3 0 P3 3 are cleared to P1 L First P1 OAH P2 2 111100B 10B 10B OF2H 2 L BP2 4 If bank 0 location 0 is cleared and regardless of whether the EMB value is logic zero BITR has the following effect FLAG EQU LD BITR 0 H 0AH H FLAG Bank 0 0 0 lt NOTE Since the instruction is used for output functions the names used the examples above may change for different devices in the SAM47 product family 5 32 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET B Bit Set BITS dst b oet specified memory bit Description This instruction sets the specified bit within the destination without affecting any other bits in the destination BITS can manipulate any bit that is addressable using direct or indirect addressing modes DA b lt 1 a2 a1 ao memb L memb 7
8. aet adds ah A e UI UCD DIIMe Voltage E OL I IER ECD Voltage DIVIGING RESISIONS GON T aa ees ene ae aUe Chapter 13 Electrical Data BE V PRENNE EE AT Standard Electrical amp E Miscellaneous Timing Waveforms Stop Mode Characteristics And Timing dn NE T m T UU TETTE Chapter 14 Mechanical Data N A LE ED MILD AL ALD EEUU Chapter 15 S3P72N4 OTP ua pq db sal Operating MOSe OGHharacteris lOS atcur ted quede e Chapter 16 Development Tools FEN TB72N2 4 1 arger BONO s dti Cano atoms maso te pu quise Rr edo d wee Causis ETT 53C72N2 C72N4 P72NA List of Figures Figure Title Page Number Number 1 1 53 72 2 72 4 Simplified Block Diagram 1 3 1 2 S3C72N2 C72N4 64 QFP Pin Assignment
9. 0 M 5 12 a _ lt lt lt S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BINARY CODE SUMMARY This Chapter contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy to read tabular format It is intended to be used as a quick reference source for programmers who are experienced with the SAM47 instruction set The same binary values and notation are also included in the detailed descriptions of individual instructions later in Chapter 5 If you are reading this user s manual for the first time please just scan this very detailed information briefly Most of the general information you will need to write application programs can be found in the high level summary tables in the previous Chapter The following information is provided for each instruction Instruction name Operand s Binary values Operation notation The tables in this Chapter are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions ELECTRONICS 5 13 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Table 5 15 CPU Control Instructions Binary Code Summary Binary Code Operation Notation n n 0 1 15 a 1 SRB
10. 0 1 Load enable memory bank and the enable 2 2 ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location Description The VENT instruction loads the contents of the enable memory bank flag EMB and enable register bank flag ERB into the respective vector addresses It then points the interrupt service routine to the corresponding branching locations The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged Then when an interrupt is generated the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed After the return from interrupt IRET you do not need to set the EMB and ERB values again Instead use BITR and BITS to clear these values in your program routine The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction These addresses must be stored ROM locations 0000H 0FFFH Generally the VENTn instructions are coded starting at location OOOOH The format for VENT instructions is as follows VENIn d1 d2 ADDR lt d1 0 or 1 ERB lt 42 0 or 1 lt ADDR address to branch devic
11. c lt e x x s EXETETIET SEG21 lt gt 1F5H F6H n e Dep 99e iH e x x x Ecos e O e x x x J d per gig BE Figure 12 6 LCD Connection Example Static Mode ELECTRONICS 12 9 LCD CONTROLLER DRIVER 53C72N2 C72N4 P72NA 12 10 Vi cO Vl C1 2 Vss COMO Vi Vi C1 2 Vss 2 Vss VLCD 1 2 VLCD 0 1 2 V LCD VLCD VLCD 0 1 2V V LCD Figure 12 7 LCD Signal Waveforms at 1 2 Duty 1 2 Bias ELECTRONICS 53C72N2 C72N4 P72NA TIMING STROBE 1E1H 1E2H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1 1EBH 1ECH 1EDH 1EEH 1EFH 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH ELECTRONICS 2 S UJ xix pepe pe xix pe px n e xp e xn xp expe Lc fff x fff fa fx fff fo ffx fo ffx fo ff ef Pe fe fe LCD CONTROLLER DRIVER __ OPEN Figure 12 8 LCD Connection Example at 1 2 Duty 1 2 Bias 12 11 LCD CONTROLLER DRIVER 12 12 COMO 53C72N2 C72N4 P72NA SEG12 COMO SEG12 COM1 SEG12 COM2 SEG12 Figure 12 9 LCD Signal Waveforms at 1 3 Duty 1 2 Bias V CO Vic1 2 Vss ViCD 1 2 V LCD 0 1 2 V LCD
12. 100 pA Port 8 only Voit 4 5 V to 5 5 V 0 4 2 V lo 15 mA Ports 2 3 6 4 5 to 5 5 V 1 100 uA Port 8 only Output low voltage Input high leakage current Vin Vpp All input pins except those specified below for jo Vpp 20 and XI IN VN70V uA All input pins except and lino Vin OV 20 Xn and XT N Yout 3 All output pins All output pins lir Input low leakage current Output high leakage current r Output low leakage current 15 4 ELECTRONICS 53C72N2 C72N4 P72NA S3P72N4 OTP Table 15 4 D C Electrical Characteristics Continued 40 to 85 1 8 V to 5 54 Pull up Ri Vin 0 V Vpp 5 V resistor Ports 1 2 3 6 R Mem Vin 0 V Vpp 5 RESET LCD voltage dividing resistor COM output impedance SEG output impedance COM output 5 V VLC0 COMI voltage deviation SEG output 5 V VLC0 SEGi voltage deviation lo 15uA i 0 31 VLCO Output VLCO 225 C 0 6V DD 0 6VDD 0 6V DD voltage 0 2 0 2 lo 15uA i 0 3 VLC1 Output VLC1 TA 25 C 0 4V DD 0 4VDD 0 4V DD voltage 0 2 0 2 VLC2 Output VLC2 TA 25 C 0 2V DD 0 2VDD 0 2V DD voltage 0 2 0 2 ELECTRONICS 15 5 S3P72N4 OTP 53 72 2 72 4 72 4 Table 15 4 D C Ele
13. 7 1 Vectored ta ww tur t D RO 7 2 oolbware sGererated tha els n cn bandas 7 2 AR ed 7 5 Interripr Fronty Register IP EL uuu a panim Ra E Rat ER RUM Qux BYC ayy KM 7 7 External Interrupt 0 And 1 Mode Registers IMODO and 7 8 External Interrupt 0 And 1 Mode Registers Continued 7 9 External Interrupt 2 Mode Register Era anra read gei 7 10 rc EVE 7 12 53 72 2 72 4 72 4 Table of Contents continued Chapter 8 Power Down SI Cn a 8 1 lde Mode Timing DIAgrarmsu G 8 3 Mode Timing DIAG FANS uu u 8 4 Port Pin Configuration for Power Down rr Dues AM E 8 6 Recommended Connections for Unused enema 8 7 Chapter 9 RESET S T 9 1 Hardware Register Values after ESE 4 impe otis PERO EUR Expl 9 1 Chapter 10 I O Ports essen rat 8 handed 10 1 POR IMOGE
14. ERU Using the BSC Register to Output 16 Bit 2 2 1 0012 Setting ISx Flags for Interrupt Processing 0 Using the EMB Flag to Select Memory Banks 2 Using the ERB Flag to Select Register 22 222 Using the Carry as a 1 Bit Chapter 3 Addressing Modes Initializing the EMB and ERB Flags aisi ERE ee ee us 1 Bit Addressing 0065 Addressing WO GCS uuu a obe awe arae c ue 8 Bit Addressing Modes EB UU esu Chapter 5 SAM47 Instruction Set Example of the Instruction Redundancy Chapter 6 Oscillator Circuits Setting tbe PE ist ueni Switching Between Main System and Subsystem 2 OPU Glock Output to The CEO Pie nu ka Leu a ieee Chapter 7 Interrupts Setung INT S3C72N2 C72N4 P72N4 Page Number xix List of Programming Tips Description Page Number Chapter 8 Power Down Reducing Power Consumption for Key Input Interrupt Processing
15. TREFO the IRQTO flag 1 set to 1 and an interrupt request is generated 9 Output latch TOLO logic toggles high or low 10 TONTO is cleared to 00H and counting resumes 11 Programmable timer counter operation continues until TMODO 2 is cleared to O ELECTRONICS 11 13 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 TCO EVENT COUNTER FUNCTION Timer counter 0 can monitor or detect system events by using the external clock input at the TCLO pin as the counter source The TCO mode register selects rising or falling edge detection for incoming clock signals The counter register TCNTO is incremented each time the selected state transition of the external clock signal occurs With the exception of the different 4 6 settings the operation sequence for TCO s event counter function is identical to its programmable timer counter function To activate the TCO event counter function Set TMODO 2 to 1 to enable Clear TMODO 6 to 0 to select the external clock source at the TCLO pin Select TCLO edge detection for rising or falling signal edges by loading the appropriate values to TMODO 5 and TMODO A Table 11 5 TMODO Settings for TCLO Edge Detection TMODO 5 TMODO 4 TCLO Edge Detection 11 14 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS TCO CLOCK FREQUENCY OUTPUT Using timer counter 0 a modifiable clock frequency can be output to the TCO
16. lt 4 If P1 0 C 4 o 2 Assume the P1 address is FF1H and the value for register L is 9H 1001B The address memb 7 2 is 111100B L 3 2 is 10B The resulting address is 11110010B FF2H specifying P2 The bit value for the BAND instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD C P1 L P1 L 1 specified as P2 1 C AND P2 1 ELECTRONICS 5 29 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 BAND Bit Logical And BAND Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BAND instruction is 3 Therefore H FLAG 20 3 FLAG EQU 20H 3 LD H 2H BAND C H FLAG AND FLAG 20H 3 5 30 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BIT R sit Reset BITR dst b Operation Omerand Operation Summary Clear specified memory bit to logic zero 4 memab H DA b Description instruction clears to logic zero resets the specified bit within the destination operand No other bits in the destination are affected operand memb L 1 1 2 L3 2 L 1 0 lt 0 undi H DA b 1 1 1 0 H DA3 0 b ras Second Byte BitAddresses Addresses Ne ae
17. 3 8 3 4 8 Bit Direct and Indirect RAM Addressing 3 10 4 1 VO Map f r Memory Bank house Dudas eee NEM UR USE MAE 4 2 5 1 Valid 1 Byte Instruction Combinations for REF Look Ups 5 2 5 2 Bit Addressing Modes and Parameters 5 4 5 3 Skip Conditions for ADC and SBC Instructions 5 5 5 4 E 5 6 5 5 misil SM ra RIPE ENTRE SERE TIS 5 6 5 6 Instruction Operand Notation a a uode ded on Ces n dea 5 6 5 7 Opcode Delinillons Directies ta a a o pa a aE 5 7 5 8 Opcode Derinitions E t 5 7 5 9 CPU Control Instructions High Level 2 2 2 5 9 5 10 Program Control Instructions High Level Summary 5 9 5 11 Data Transfer Instructions High Level 2 2 0 00 0720 5 10 5 12 Logic Instructions High Level Summary 5 11 5 13 Arithmetic Instructions High Level Summary 5 11 5 14 Bit Manipulation Instructions High Level Summary 5
18. 34H HL EA 2 2 3 WX EA 1 EA 34H HL EA 2 YZ EA 3 WX EA Register bank 0 is selected since ERB 0 the SRB is configured to bank 0 BankO EA lt 34 Bank 0 HL EA Register bank 0 is selected Bank 0 YZ lt EA Register bank 0 is selected Bank 0 WX lt EA Register bank 1 is selected Bank 1 lt 84H Bank 1 HL lt Bank 1 EA Register bank 2 is selected Bank 2 YZ lt BANK2 EA Register bank 3 is selected Bank 3 WX lt 3 EA ELECTRONICS 53C72N2 C72N4 P72NA ADDRESS SPACES SKIP CONDITION FLAGS SC2 SC1 SCO The skip condition flags SC2 SC1 and SCO in the PSW indicate the current program skip conditions and are and reset automatically during program execution Skip condition flags can only be addressed by 8 bit read instructions Direct manipulation of the SC2 SC1 and SCO bits is not allowed CARRY FLAG C The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry ADC SBC The carry flag can also be used as a 1 bit accumulator for performing Boolean operations involving bit addressed data memory If an overflow or borrow condition occurs when executing arithmetic instructions with carry ADC SBC the carry flag is set to 1 Otherwise its value is 0 When a RESET occurs the current value of the carry flag is retained during power down mode but when normal operating mode resumes its va
19. Execute instruction 023H lt 1H If consecutive LD HL imm instructions load 8 bit immediate data to the 8 bit memory pointer pair HL are detected only the first LD is executed and the LDs which immediately follow are ignored For example LD HL 10H HL lt 10H LD HL 20H Ignore redundant instruction LD A 3H A 3H LD EA 35H Ignore redundant instruction LD HL A 10H lt If an instruction reference with a REF instruction has a redundancy effect the following conditions apply Ifthe instruction preceding the REF has a redundancy effect this effect is canceled and the referenced instruction is not skipped Ifthe instruction following the REF has a redundancy effect the instruction following the REF is skipped PROGRAMMING Example of the Instruction Redundancy Effect ORG 0020H ABC LD Stored in REF instruction reference area ORG 0080H LD EA 40H Redundancy effect is encountered REF ABC No skip EA lt 30 REF ABC EA 80H LD EA 50H Skip ELECTRONICS 5 3 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear the 47 instruction set can also perform bit tests bit transfers and bit Boolean operations Bits can also be addressed and manipulated by special bit addressing modes Three types of bit addressing are supported
20. _ Operation Summary Bytes Cycles ADR12 Call direct address 12 bits Description CALL calls a subroutine located at the destination address The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack decreasing the stack pointer by six The EMB and ERB are also pushed to the stack Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 14 Kbyte program memory address space Binary Code Operation Notation ADR12 1 4 1 1 1 SP 1 SP 2 lt ERB 5 3 SP 4 PC7 0 1 12 11 10 SP 5 5 6 lt 11 8 SP SP 6 rar as 5 we so at o AC Example The stack pointer value is and the label PLAY is assigned to program memory location OESFH Executing the instruction CALL PLAY at location 0123H will generate the following values SP OFFH OH EMB ERB OFDH 2H OFCH 6H OFBH OH OFAH 1H PC Data is written to stack locations as follows OFAH OFBH OFCH OFDH 0 ERB em ELECTRONICS 5 45 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 15 Procedure Short 5 Operation Description Example 5 46 dst ADR11 Call direct address within 2 K 11 bits The CALLS instruction uncon
21. 11 9 TOOF UNCION SUMINA EST E 11 9 Component Summa asses es n deat estatus edd ad 11 10 TCO Enable Disable e a E eE a saya Suaeda 11 12 TCO Programmable Timer Counter Function 11 13 I TU TIME 11 13 TCO Event Counter FUNCION misti aesthetics uti 11 14 TGO Clock Frequency a M hacer 11 15 TCO Extermial Input Signal uu t te 11 16 TCO Mode Register T MODO amira A a 11 17 Counter a R O 11 19 TOO Reference Register TREFO Da dc ndun tue uda 11 20 TCO Output Erable Flag TOE E a E M a eds 11 20 TOO Laten TOCO PED 11 20 WIEN UIME cec E 11 22 eu 11 22 Watch Timer Mode Register WMOD 11 25 viii 53 72 2 72 4 72 4 Table of Contents continued Chapter 12 LCD Controller Driver S MT EE CEBIT EE OUT LR OD BAN Address i r GD Gontrol Redister EG OIN uuu u LCD Mode Register EMO D iate an
22. memb L H DA b The parameters of these bit addressing modes are described in more detail in Table 5 2 Table 5 2 Bit Addressing Modes and Parameters Addressing Mode Addressable Peripherals Address Range mema b ERB 151 ISO IRQx FBOH FBFH MM NN 2 3 6 Co _ memb L Ports 1 2 3 6 and Ports 1 2 3 6 andBSC IFCOH FFFH 222222 FFFH H DA b All bit manipulable peripheral hardware All bits of the memory bank specified by EMB and SMB that are bit manipulable Instructions Which Have Skip Conditions The following instructions have a skip function when an overflow or borrow occurs XCHI INCS XCHD DECS LDI ADS LDD SBS If there is an overflow or borrow from the result of an increment or decrement a skip signal is generated and a skip is executed However the carry flag value is unaffected The instructions BTST BTSF and CPSE also generate a skip signal and execute a skip when they meet a skip condition and the carry flag value is also unaffected Instructions Which Affect the Carry Flag The only instructions which do not generate a skip signal but which do affect the carry flag are as follows ADC LDB C operand SBC BAND C operand SCF BOR C operand RCF BXOR C operand CCF 5 4 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET ADC and SBC Instruction Skip Conditions The instructions ADC A HL and A HL can generate skip signal and set or clear t
23. CPU clock fxx 64 INT1 9 Figure 10 1 Input Port 1 Circuit Diagram ELECTRONICS 10 5 PORTS 53C72N2 C72N4 P72NA PORT 2 CIRCUIT DIAGRAM VDD VDD VDD VDD OUTPUT LATCH NOTE When port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 2 Port 2 Circuit Diagram ELECTRONICS 10 6 53C72N2 C72N4 P72NA PORTS PORTS 3 AND 6 CIRCUIT DIAGRAM VDD PUMOD x ZEE port number 3 6 0 0 1 2 O Px 3 NOTE When port pin acts as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings to the pull up resistor mode register PUMOD Figure 10 3 Ports 3 and 6 Circuit Diagram ELECTRONICS PORTS 53C72N2 C72N4 P72NA NOTES ELECTRONICS 10 8 3C72N2 C72N4 P72N4 TIMERS and TIMER COUNTERS 1 1 TIMERS and TIMER COUNTERS OVERVIEW The S8C72N2 C72N4 microcontroller has three timer and timer counter modules 8 bit basic timer BT 8 bit timer counter TCO Watch timer WT The 8 bit basic timer BT is the microcontroller s main interval timer It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register The basic timer also functions as watchdog timer
24. ELECTRONICS 7 1 INTERRUPTS 53C72N2 C72N4 P72NA VECTORED INTERRUPTS Interrupt requests may be processed as vectored interrupts in hardware or they can be generated by program software A vectored interrupt is generated when the following flags and register settings corresponding to the specific interrupt INTn are set to logic one nterrupt enable flag IEx nterrupt master enable flag IME Interrupt request flag IRQx Interrupt status flags ISO 151 Interrupt priority register IPR If all conditions are satisfied for the execution of a requested service routine the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines The flags are stored at the beginning of the program with the VENT instruction The initial flag values determine the vectors for resets and interrupts Enable flag values are saved during the main routine as well as during service routines Any changes that are made to enable flag values during a service routine are not stored in the vector address When an interrupt occurs the enable flag values before the interrupt is initiated are saved along with the program status word PSW and the enable flag values for the interrupt is fetched from the respective vector add
25. F92H NOTE u means that the value is undetermined When you set the TOEO flag to 1 the contents of TOLO can be output to the TCLOO pin Whenever a RESET occurs TOEO is automatically set to logic zero disabling all TCO output TCO OUTPUT LATCH TOLO is the output latch for timer counter 0 When the 8 bit comparator detects a correspondence between the value of the counter register TCNTO and the reference value stored in the TREFO register the TOLO value is inverted the latch toggles high to low or low to high Whenever the state of TOLO is switched the TCO signal is output TCO output may be directed to the TCLOO pin Assuming TCO is enabled when bit 3 of the TMODO register is set to 1 the TOLO latch is cleared to logic zero along with the counter register TCNTO and the interrupt request flag IRQTO and counting resumes immediately When is disabled TMODO 2 0 the contents of the TOLO latch are retained and can be read if necessary 11 20 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS PROGRAMMING Setting a TCO Timer Interval To set a 30 ms timer interval for given fxx 4 19 MHz follow these steps 1 Select the timer counter 0 mode register with a maximum setup time of 62 5 ms assume the TCO counter clock 210 and TREFO is set to 2 Calculate the TREFO value TREFO value 1 4 09 kHz 30 ms 1
26. SEGO SEG2 CT lt gt Oe lt gt lt gt O lt gt O D gt lt gt AED O Wiring lt P lt O MI lt Pid 40 IL E MO MI lt gt lt gt m w w O O NN O Figure 12 13 LCD Connection Example at 1 4 Duty 1 3 Bias 53C72N2 C72N4 P72NA ELECTRONICS 53 72 2 72 4 72 4 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section information on S8C72N2 C72N4 electrical characteristics is presented as tables and graphics The information is arranged in the following order STANDARD ELECTRICAL CHARACTERISTICS Absolute maximum ratings electrical characteristics Main system clock oscillator characteristics Subsystem clock oscillator characteristics capacitance A C electrical characteristics Operating voltage range MISCELLANEOUS TIMING WAVEFORMS A C timing measurement point Clock timing measurement at Xy Clock timing measurement at XT timing Input timing for RESET Input timing for external interrupts STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONICS 13 1
27. 1 Bit 1 E Always logic zero NOTE SCMOD bits 3 and 0 cannot be modified simultaneously by 4 bit instruction they can only be modified by separate 1 bit instructions 4 24 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP TMODO rimer Counter 0 Mode Register F91H F90H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Bit Addressing 8 8 8 8 1 8 8 8 8 7 Bit 7 Always logic zero 6 4 Timer Counter 0 Input Clock Selection Bits EB External clock input at TCLO pin on rising edge External clock input at TCLO pin on falling edge ofo ofo _1 0 0 Select clock 6012710 4 09 kHz 49 MHz _1 0 1 Select clock to 16 4 KHz _1 1 0 select clock 4 2 655 o 3 Clear Counter and Resume Counting Control Bit 1 Clear IRQTO and TOLO and resume counting immediately This bit is cleared automatically when counting starts 2 Enable Disable Timer Counter 0 Bit Disable timer counter 0 retain TCNTO contents 1 Enable timer counter O 1 0 Bits 1 0 Always logic zero ELECTRONICS 4 25 MEMORY S3C72N2 C72N4 P72N4 TOE rimer Output Enable Flag Register F92H Bit 3 2 1 0 RESET Value 0 0 Read Write R W Bit Addressing 1 3 Bit3 TOEO Timer Counter 0 Output Enable Flag Disable timer counter 0 output the TCLOO Enable timer counter 0 output at the TCLOO pin 1 0 Bits 1 0
28. 1229 TREFO value 7AH 1 79H 3 Load the value 79H to the TREFO register BITS EMB SMB 15 LD 79 LD TREFO EA LD 4 LD TMODO EA ELECTRONICS 11 21 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 WATCH TIMER OVERVIEW The watch timer is a multi purpose timer which consists of three basic components 8 bit watch timer mode register WMOD Clock selector Frequency divider circuit Watch timer functions include real time and watch time measurement and interval timing for the main and subsystem clock It is also used as a clock source for the LCD controller and for generating buzzer BUZ output Real Time and Watch Time Measurement To start watch timer operation set bit 2 of the watch timer mode register WMOD 2 to logic one The watch timer starts the interrupt request flag IRQW is automatically set to logic one and interrupt requests commence in 0 5 second intervals oince the watch timer functions as a quasi interrupt instead of a vectored interrupt the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed Using a System or Subsystem Clock Source The watch timer can generate interrupts based on the system clock frequency or on the subsystem clock When the zero bit of the WMOD register is set to 1 the watch timer uses the subsystem clock signal fxt as its source if WMOD 0 0
29. ELECTRONICS 5 47 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Complement Accumulator COM Operation Description Example 5 48 A The accumulator value is complemented if the bit value of A is 1 it is changed to 0 and vice versa Binary Code Operation Notation jaca If the accumulator contains the value 4H 0100B the instruction COM leaves the value OBH 1011B in the accumulator ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET CPSE Compare and Skip if Equal CPSE dst src R im Compare and skip if register equals im 2 24S HL im Compare and skip if indirect data memory equals im Description CPSE compares the source operand subtracts it from the destination operand and skips the next instruction if the values are equal Neither operand is affected by the comparison Operation Notation R im KS Skip if R im ki al HL im Skip if HL uu Skip if A R a toto Skip if EA RR The extended accumulator contains the value 34H and register pair HL contains 56H The second instruction RET in the instruction sequence w 5 Q lt Be ale k 2 1 1 EJ o o CPSE EA HL HET is not skipped That is the subroutine returns since the result of the comparison is not equal ELEC
30. o1 1 Jew 16 4 o Je 262 NOTE selected system clock of 4 19 MHz PROGRAMMING Restarting TCO Counting Operation 1 Set TCO timer interval to 4 09 kHz BITS EMB SMB 15 LD 4 LD TMODO EA EI BITS IETO 2 Clear IRQTO and TOLO and restart TCO counting operation BITS EMB SMB 15 BITS TMODO 3 11 18 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS TCO COUNTER REGISTER TCNTO The 8 bit counter register for timer counter 0 TCNTO is read only and can be addressed by 8 bit RAM control instructions RESET sets all TCNTO register values to logic zero 00H Whenever is enabled is cleared to logic zero and counting resumes The TCNTO register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMODO register specifically TMODO 6 TMODO 5 and TMODO 4 Each time TCNTO is incremented the new value is compared to the reference value stored in the TCO reference buffer TREFO When TCNTO TREFO an overflow occurs in the TCNTO register the interrupt request flag IRQTO is set to logic one and an interrupt request is generated to indicate that the specified timer counter interval has elapsed PLU LU AS LL Ue REFERENCE VALUE n m of ol lt INTERVAL TIME
31. PC7 0 SP 2 SP 3 PSW lt EMB ERB SP lt SP 6 The stack pointer contains the value OFAH RAM locations OFAH OFBH OFCH and OFDH contain 1H OH 5H and 2H respectively The instruction RET leaves the stack pointer with the new value of OOH and program execution continues from location 0125H During a return from subroutine PC values are popped from stack locations as follows ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET RRC RRC Operation Description Example Rotate Accumulator Right Through Carry A The four bits in the accumulator and the carry flag are together rotated one bit to the right Bit O moves into the carry flag and the original carry value moves into the bit 3 accumulator position Binary Code Operation Notation A 1 1 lt A 0 C A n 1 lt A n n 1 2 3 The accumulator contains the value 5H 0101B and the carry flag is cleared to logic zero The instruction RRC A leaves the accumulator with the value 2H 0010B and the carry flag set to logic one ELECTRONICS 5 79 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 SBC Subtract With Carry SBC dst src Operation operand Operation Summary Byes Cycles Subtract indirect data memory from A with carry 1 EARR Subtract register pair tom EA wih cary 2 Subtract EA from register pair RRb with carry Description SBC subtracts the source and carry flag value
32. Resistor Mode Register FDDH FDCH Bit 7 6 5 4 3 2 1 0 Identifier ugs 0 o PUR2 PUR o RESET Value 0 0 0 0 0 0 0 0 Read Write W Bit Addressing 8 8 8 8 8 8 8 8 7 Bit 7 Always logic zero PUR6 Connect Disconnect Port 6 Pull Up Resistor Control Bit Disconnect port 6 pull up resistor Connect port 6 pull up resistor 5 4 Bits 5 4 Always logic zero Connect Disconnect Port 3 Pull Up Resistor Control Bit Disconnect port 3 pull up resistor Connect port 3 pull up resistor 1 PUR2 Connect Disconnect Port 2 Pull Up Resistor Control Bit Disconnect port 2 pull up resistor Connect port 2 pull up resistor 1 PUR1 Connect Disconnect Port 1 Pull Up Resistor Control Bit Disconnect port 1 pull up resistor Connect port 1 pull up resistor 1 0 Bit 0 Always logic zero NOTE Pull up resistors for all ports are automatically disabled when they are configured to output mode ELECTRONICS 4 2 MEMORY S3C72N2 C72N4 P72N4 SCMOD System Clock Mode Control Register FB7H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 1 1 1 3 2 and 0 CPU Clock Selection and Main System Clock Oscillation Control Bits Select main system clock fx enable main system clock Select main system clock fx disable sub system clock Select sub system clock fxt enable main system clock Select sub system clock fxt disable main system clock
33. Using the Carry Flag as 1 Bit Accumulator 1 Set the carry flag to logic one SCF Ce 1 LD EA 0C3H EA lt 0C3H LD HL lt 0AAH ADC EA HL EA lt 0C3H 0AAH 1H C lt 1 2 Logical AND bit 3 of address with P3 3 and output the result to P2 0 LD oet the upper four bits of the address to the register value LDB C H 0FH 3 bit 3 of BAND AND P3 3 LDB P2 0 C Output result from carry flag to P2 0 2 22 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESSING MODES ADDRESSING MODES OVERVIEW The enable memory bank flag EMB controls the two addressing modes for data memory When the flag is set to logic one you can address the entire RAM area when the EMB flag is cleared to logic zero the addressable area in the RAM 1 restricted to specific locations The EMB flag works in connection with the select memory bank instruction SMB n You will recall that the SMB n instruction is used to select RAM bank 0 1 or 15 The SMB setting is always contained in the upper four bits of a 12 bit RAM address For this reason both addressing modes EMB 0 and EMB 1 apply specifically to the memory bank indicated by the SMB instruction and any restrictions to the addressable area within banks 0 1 or 15 Direct and indirect 1 bit 4 bit and 8 bit addressing methods can be used Several RAM locations are addressable at all times re
34. rus uuu asua Racine Rua Gas DTE 93 xxiv 53 72 2 72 4 72 4 S3C72N2 C72N4 P72N4 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72N2 C72N4 single chip CMOS microcontroller has been designed for high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arrangeable Microcontrollers With features such as LCD direct drive capability 8 bit timer counter and watch timer the S3C72N2 C72NA4 offers an excellent design solution for a wide variety of applications that require LCD functions Up to 16 pins of the 64 pin QFP package it can be dedicated to I O Four vectored interrupts provide fast response to internal and external events In addition the 53C72N2 C72N4 s advanced CMOS technology provides for low power consumption and a wide operating voltage range OTP S3C72N2 C72N4 microcontroller is also available in One Time Programmable version S3P72N4 The S3P72N4 microcontroller has an on chip 4 Kbyte one time programmable EPROM instead of masked ROM The S3P72NA is comparable to 53C72N2 C72N4 both in function and in pin configuration ELECTRONK S 1 1 PRODUCT OVERVIEW FEATURES Memory 288 x 4 bit RAM 2048 x 8 bit ROM S3C72N2 4096 x 8 bit ROM S3C72N4 Pins Input only 4 pins 1 0 12 pins Output 8 pins sharing with segment driver outputs LCD Controller Driver Maximum 16 digit LCD direct drive capability
35. 0 1 2 3 11 0 memc7 4 memc3 0 1 0 1 7 6 lt 0 1 5 4 0 ADR n 3 0 PC11 8 n n 7 0 PC7 0 5 14 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 16 Program Control Instructions Binary Code Summary gt JJ Operand Binary Code Operation Notation Gee Rm pep p ENERENEREBKRER KIERES eer ES 0 Skip if A HL E HL 1 p EN ofofo 21014 ER Skip if EA RR ERHEBEN ESFXEN 0 ADR12 ofofo a5 a6 HL im s Bep A HL EA HL EA RR E ADR12 1 2 at 20 C BN JPS ADR12 E 0 lt ADR12 x PC11 0 lt ADR 15 to PC 16 0 PC11 8 WX 1 SP 1 SP 2 lt EMB ERB EX SP 3 lt PC7 0 Ct 1 SP 5 5 6 lt PC11 8 p lt SP 6 a2 PC11 0 lt ADR12 im WX 1 2 EA CALL ADR12 D D O CALLS ADR11 1 1 1 1 SP 1 SP 2 lt ERB 3 SP 4 lt 7 0 SP 5 5 6 lt 11 8 SP lt SP 6 PC11 lt 0 10 0 lt ADR11 First Byte Condition ju 5 sis
36. 5 4 Output Buzzer Frequency Selection Bits olo 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output 1 K 8 kHz buzzer BUZ signal output 16 kHz buzzer BUZ signal output 3 XTin Input Level Control Bit Input level to is low 1 bit read only addressable for tests 1 Input level to pin is high 1 bit read only addressable for tests 2 Enable Disable Watch Timer Bit Disable watch timer and clear frequency dividing circuits Enable watch timer 1 Watch Timer Speed Control Bit Normal speed set IRQW to 0 5 seconds 1 High speed operation set IRQW to 3 91 ms 0 Watch Timer Clock Selection Bit Select system clock fxx 128 as the watch timer clock 1 Select a subsystem clock as the watch timer clock NOTE RESET sets WMOD 3 to the current input level of the subsystem clock jn If the input level is high WMOD 3 is set to logic one if low WMOD 3 is cleared to zero along with all the other bits in the WMOD register ELECTRONICS 4 2 S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set includes 1 bit 4 bit and 8 bit instructions for data manipulation logical and arithmetic operations program control and CPU control I O instructions for peripheral hardware devices are flexible and easy to use Symbolic hardware names can be substituted as the instruction operand in place of the actual address Ot
37. DA b memb L Skip if memb 7 2 L 3 2 L 1 0 1 and clear H DA b BITS DA b mema b E RS 2 O memb L H DA b EERE H DA3 0 b 1 or as a2 40 a 5 20 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 20 Bit Manipulation Instructions Binary Code Summary Continued Operand Binary Code Operation Notation eo FREI lt 0 1 o memb 7 2 L3 2 L 1 0 0 1 o H DA3 0 b 0 o ERES P3 1 C AND mema b a2 lt AND H DA 3 0 b a2 a0 o bt oo Cr EST o bt bo o DA b mema b memb L H DA b O1 BAND C mema b D 0 C1 BE dd C memb L lt C AND memb 7 2 L 3 2 L 1 0 C H DA b C mema b C memb L C C OR memb 7 2 L 3 2 OR DA3 0 b 1 C XOR memab C C memb 7 2 L 3 2 1 XOR H DA3 0 b Bit Addresses FBOH FBFH FF1H FF9H C H DA b BXOR C mema b C memb L C H DA b ELECTRONICS 5 21 L Q Q CO SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 T
38. ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET STOP Stop Operation STOP Operation Description Example The STOP instruction stops the system clock by setting bit 3 of the power control register PCON to logic one When STOP executes all system operations are halted with the exception of some peripheral hardware with special power down mode operating conditions In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three NOP instructions are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus Binary Code Operation Notation C Rune Given that bit 3 of the PCON register is cleared to logic zero and all systems are operational the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one stopping all controller operations with the exception of some peripheral hardware The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 87 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Load ERB and Vector Address VENTn dst operation operand Operation Summary
39. u Unknown value NOTE means that the bit is unknown 4 26 S3C72N2 C72N4 P72N4 MEMORY MAP WDFLAG Watchdog Timer Counter Clear Flag Register F9AH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 4 1 4 1 4 1 4 WDTCF Watchdog Timer Counter Clear Flag Clears the watchdog timer counter 2 0 Bits 2 0 Always logic zero NOTE After watchdog timer is cleared by writing 1 this bit is cleared to 0 automatically Instruction that clear the watchdog timer BITS WDTCF should be executed at proper points in a program within a given period If not executed within a given period and watchdog timer overflows RESET signal is generated and system is restarted with reset status ELECTRONICS 4 27 MEMORY S3C72N2 C72N4 P72N4 WDMOD watchdog Timer Mode Register F99H F98H Bit 7 6 5 4 3 2 1 0 1 0 1 0 0 1 0 1 Read Write W W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 WDMOD Watchdog Timer Enable Disable Control 5AH Disable watchdog timer function Any other value Enable watchdog timer function 4 28 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP WMOD watch Timer Mode Register F89H F88H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 note 0 0 0 Read Write W W W W H W Bit Addressing 8 8 8 8 1 8 8 8 7 Enable Disable Buzzer Output Bit Disable buzzer BUZ signal output 1 Enable buzzer BUZ signal output 6 Bit 6 Always logic zero
40. 32 segment 4 common pins Display modes Static 1 2 duty 1 2 bias 1 3 duty 1 2 or 1 3 bias 1 4 duty 1 3 bias 8 Bit Basic Timer Programmable interval timer Watchdog timer 8 Bit Timer Counter Programmable 8 bit timer External event counter Arbitrary clock frequency output Watch Timer Real time and interval time measurement Four frequency outputs to BUZ pin Clock source generation for LCD Bit Sequential Carrier Support 16 bit serial data transfer in arbitrary format 1 2 S3C72N2 C72N4 P72N4 Interrupts Two internal vectored interrupts Two external vectored interrupts Two quasi interrupts Memory Mapped Structure Data memory bank 15 Two Power Down Modes Idle mode only CPU clock stops Stop mode main or sub system oscillation stops Oscillation Sources Crystal ceramic or RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency 4 19 MHz typical Subsystem clock frequency 32 768 kHz CPU clock divider circuit by 4 8 or 64 Instruction Execution Times 0 95 1 91 15 3 us at 4 19 MHz main 122 us at 32 768 kHz subsystem Operating Temperature 25 C to 85 C Operating Voltage Range 2 0V to 5 5 V at 4 19 MHz 1 8V to 5 5 V at 3 MHz Package Type 64 pin QFP ELECTRONK S S3C72N2 C72N4 P72N4 BLOCK DIAGRAM INTO INT1
41. Binary Code Operation Notation Him ER 11 0 lt ADR PC 15 to 16 QWX 1 1 1 0 lt 11 8 WX 1 0 1 11 0 PC11 8 EA First Byte Condition o soc eoo wm pone OOOHOO ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET J R Jump Relative Very Short JR Continued Examples 1 A short form for a relative jump to label is the instruction JR KK where must be within the allowed range of current PC 15 to current 16 The JR instruction has in this case the effect of an unconditional JP instruction 2 In the following instruction sequence if the instruction LD WX 02 were to be executed in place of LD WX 00H the program would jump to 0502H and JPS BBB would be executed If EA 04H were to be executed the jump would be to 0504H and JPS would be executed ORG 0500H JPS AAA JPS BBB JPS CCC JPS DDD LD WX 00H WX lt 00H LD EA WX ADS WX EA WX lt WX WX JR WX Current 11 8 05H WX 0500H Jump to address 0500H and execute JPS AAA 3 Here is another example ORG 0600H LD A 0H LD A 1H LD A 2H LD A 3H LD Address lt A JPS YYY LD 00 EA lt 00H JR EA Jump to address 0600H gt Address lt OH If LD EA 01H were to be executed in place of LD EA Z00H the program would jump to 0601H and address would contain
42. ELECTRICAL DATA S3C72N2 C72N4 P72N4 Table 13 1 Absolute Maximum Ratings All I O ports 0 3 to Vpp 0 3 mA One I O port active 15 All ports active 90 One port active 30 Peak value Total value for ports 2 and 3 Total value for port 6 otorage Temperature Tstg 65 to 150 NOTE The values for Output Current Low loj are calculated as Peak Value xy Duty Table 13 2 D C Electrical Characteristics 25 C to 85 1 8V to 5 5 V Input high Viri All input pins except those voltage specified below for Vin Vis Vino Ports 1 6 and RESET and XTN Vpp 0 1 Input low Ports 2 and 3 voltage Ports 1 6 and RESET Output high 4 5 V to 5 5 V voltage 1 mA Ports 2 3 6 and BIAS 4 5 V to 5 5 V IM ET 13 2 53 72 2 72 4 72 4 ELECTRICAL DATA Table 13 2 D C Electrical Characteristics Continued 25 C to 85 1 8V to 5 5 V Output low VoL Vpp 4 5 V to 5 5 V 0 4 2 V voltage lo 15 Ports 2 3 6 EN Vpp245V to 5 5V Input high 3 leakage All input pins except those current specified below for jo Vin and Input low V N 0 V leakage All input pins except XN and current XTN 0 and XT ny Output high Vpp leakage current All output
43. VLCD V I CD 0 1 2 V LCD V LCD V LCD 1 2 VLCD 0 1 2 V LCD V LCD ELECTRONICS S3C72N2 C72N4 P72N4 LCD CONTROLLER DRIVER COMO COM1 SEG12 Vl CD 1 3 V COMO po SEG12 1 3V VLCD VLCD 1 3 VLCD COM1 0 SEG12 1 3 VLCD cp Vl 1 3 V LCD COM2 0 SEG12 1 3 VLCD VLCD Figure 12 10 LCD Signal Waveforms at 1 3 Duty 1 3 Bias ELECTRONICS 12 13 LCD CONTROLLER DRIVER 12 14 Timina otrobe 1E1H 1E2H 1E4H 1E5H 1E6H 1E7H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH BitO Bit1 812 Figure 12 11 LCD Connection Example at 1 3 Duty 1 3 Bias 53C72N2 C72N4 P72NA ELECTRONICS 53C72N2 C72N4 P72NA LCD CONTROLLER DRIVER COMO 1 SEG13 Figure 12 12 LCD Signal Waveforms at 1 4 Duty 1 3 Bias ELECTRONICS LCO Vss V CD 1 3 VLCD 0 1 3 V LCD VLCD VLCD 1 5VLCD 0 1 3 Vi VLCD 12 15 LCD CONTROLLER DRIVER Timing otrobe 1E2H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1 1EBH 1ECH 1EDH 1EEH 1EFH 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH BitO 1 Bit2
44. 1 If EMB 0 compare bank 0 locations 040 046 with bank 0 locations 060 066 Non essential instruction since EMB 0 lt bank 0 040H 046H If bank 0 060 066 skip 0 exchange bank 0 locations 040 046 with bank 0 locations 060 066 ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL ZBDATA LD WX ADATA COMP LD A WL CPSE A HL SRET DECS L JR COMP RET 2 If EMB ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA TRANS LD A WL XCHD A HL JR TRANS ELECTRONICS Non essential instruction since EMB 0 lt bank 0 040H 046H Bank 0 060 066 lt gt A 3 9 ADDRESSING MODES 53 72 2 72 4 72 4 8 ADDRESSING Table 3 4 8 Direct and Indirect RAM Addressing Instruction Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank 4 Direct 8 bit address indicated 15 8 bit by the RAM address DA 000 addressable even number and memory 1E0H 1FFH peripherals bank selection SMB 15 Indirect the 8 bit address 4bit 0 OOOH OFFH indicated by the memory bank All 8 bit selection and register HL the addressable L register value must be an F8O0H FFFH Bank 15 peripherals even number SMB 15 3 10 ELECTRONICS 53C72N2 C72N4 P72NA ADDRESSING MODES PROGRAMMING 8 Bit Addressing Modes 8 Bit Direct A
45. 2 L 3 2 b L 1 0 lt 1 undi ofo H DA b H DA 3 0 b lt 1 ror Too fos Pa ar ao Bit Addresses 7 l el a o rmo Examples 1 Assuming that bit location 30H 2 in the RAM has a current value of 0 the following instruction sets the second bit of location 30H to 1 BITS 30H 2 2 lt 1 2 You can use BITS in the same way to manipulate a port address BITS P2 0d 2 0 lt 1 ELECTRONICS 5 33 53 72 2 72 4 72 4 SAM47 INSTRUCTION SET BITS Bit Set BITS Continued Examples LD BP2 BITS INCS JR Given that P2 2 P2 3 and P3 0 P3 3 are set to 1 P1 L First P1 OAH P2 2 111100B 10B 10B OF2H 2 L BP2 4 f bank 0 location 0 is set to 1 and the EMB 0 BITS has the following effect FLAG EQU LD BITS 0 H 0AH H FLAG 0 lt 1 NOTE Since the BITS instruction is used for output functions pin names used in the examples above may change for different devices in the SAM47 product family 5 34 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BOR Bit Logical OR BOR C src b Logical OR carry with specified memory bit C memb L C H DA b Description The specified bit of the source is logically ORed with the carry flag bit value The value of the source is unaffected Operand i
46. 26 P6 0 KS0 29 P6 1 KS1 C3 30 P6 2 KS2 CJ 31 P6 3 KS3 C4 32 Figure 1 2 S3C72N2 C72N4 64 QFP Pin Assignment 1 4 ELECTRONES S3C72N2 C72N4 P72N4 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 S3C72N2 C72N4 Pin Descriptions Pin Description Reset Circuit Type Value Type 4 bit input port 17 Input 4 1 bit or 4 bit read and test is possible 18 4 bit pull up resistors are software 19 assignable I O 4 bit I O port TCLOO Input CLO BUZ 1 bit and 4 bit read write and test 1 possible 4 bit pull up resistors are software 20 21 22 23 24 assignable 25 26 27 28 I O 4 bit I O port LCDCK Input 1 bit and 4 bit read write and test is LCDSY possible Each individual pin can be specified as input or output 4 bit pull up resistors are software assignable P6 0 P6 3 I O 4 bit I O ports Pins are individually 29 32 KSO KS3 Input software configurable as input or output 1 bit and 4 bit read write and test is possible 4 bit pull up resistors are software assignable Meal Output port for 1 5 data for use as Output CMOS driver only SEG31 O LCD common signal output 14 Output 6 8 Built in voltage dividing resistors BIAS LCD power control LCDCK I O LCD clock output for display expansion 25 P3 0 Input ELECTRONK S 1 5 PRODUCT OVERVIEW S3C72N2 C72N4 P72N4 Table 1 1 S3C72N2 C72N4 Pin Descriptions Conti
47. In this example the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A ORG 01FDH 01FDH LD WX 00H 01FFH LDC EA WX lt upper 4 bits of 0200 address lt lower 4 bits of 0200H address 4 Here is another example of page referencing with the LDC instruction ORG 0100 DB 67H SMB 0 LD HL Z30H Even number LD WX 00H LDC EA WX upper 4 bits of 0100H address lt lower 4 bits of 0100H address LD RAM 30H 7 81H 6 ELECTRONICS 5 67 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 LDD Load Data Memory and Decrement LDD Operation Description Example 5 68 dst A HL Load indirect data memory contents to A decrement 1 24 9 register L contents and skip on borrow The contents of a data memory location are loaded into the accumulator and the contents of the register L are decreased by one If a borrow occurs e g if the resulting value in register L is OFH the next instruction is skipped The contents of data memory and the carry flag value are not affected Binary Code Operation Notation A HL 1 1 1 1 A lt HL then L e LA skip if L In this example assume that register pair HL contains 20H and internal RAM location 20H contains the value LD HL 20H LDD A HL A lt HL and lt L 1 JPS XXX Skip JPS YYY 2H and L The instruct
48. L the address and bit location assignment is FC3H 3 Table 2 4 BSC Register Organization Name Address _ BSCO FCOH BSC1 FC1H BSC2 FC2H BSC3 2 PROGRAMMING Using the BSC Register to Output 16 Bit Data To use the bit sequential carrier BSC register to output 16 bit data 5937 to the P3 0 pin BITS EMB SMB 15 LD 3 7 LD BSCO EA BSCO lt 5 1 lt E LD 59 LD BSC2 EA BSC2 lt BSC3 lt E SMB 0 LD L 0H AGN LDB C BSCO L LDB P3 0 C P3 0 lt C INCS JR AGN RET 2 16 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES PROGRAM COUNTER PC A 12 bit program counter PC stores addresses for instruction fetches during program execution Whenever a reset operation or an interrupt occurs bits PC11 through PCO are set to the vector address Usually the PC is incremented by the number of bytes of the instruction being fetched One exception is the 1 byte REF instruction which is used to reference instructions stored in the ROM PROGRAM STATUS WORD PSW The program status word PSW is an 8 bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced PSW values are mapped as follows MSB LSB FBOH 151 150 SC1 SCO QD N The PSW can be manipulated by 1 bit or 4 bit read write and by 8 bit read instructions dep
49. MEMORY S3C72N2 C72N4 P72N4 PMG1 Port 1 0 Mode Flags Group 1 Ports 3 and 6 FE9H FE8H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM6 3 P6 3 I O Mode selection Flag Set P6 3 to input mode Set P6 3 to output mode PM6 2 P6 2 I O Mode Selection Flag Set P6 2 to input mode Set P6 2 to output mode 1 6 1 P6 1 I O Mode Selection Flag Set P6 1 to input mode Set P6 1 to output mode PM6 0 P6 0 Mode Selection Set P6 0 to input mode Set P6 0 to output mode 1 PM3 3 P3 3 Mode Selection Flag Set P3 3 to input mode Set P3 3 to output mode PM3 2 P3 2 I O Mode Selection Flag Set P3 2 to input mode Set P3 2 to output mode 1 P3 1 1 Mode Selection Flag Set P3 1 to input mode Set P3 1 to output mode PM3 0 P3 0 I O Mode Selection Flag Set P3 0 to input mode Set P3 0 to output mode 1 4 20 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP 2 Port 1 0 Mode Flags Group 2 Port 2 FEDH FECH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Bit Addressing 8 8 8 8 8 8 8 8 3 Bits 3 Always logic zero PM2 P2 I O Mode Selection Flag Set P2 to input mode 1 Set P2 to output mode 1 0 Bits 1 0 Always logic zero ELECTRONICS 4 2 L MEMORY S3C72N2 C72N4 P72N4 PSW Program Status Word FB1H FBOH Bit 7 6 5 4 3 2 1 0 RESET Value 1 0
50. Memory addressing area 00H 7FH F80H FFFH ELECTRONICS 2 13 ADDRESS SPACES 53 72 2 72 4 72 4 PUSH OPERATIONS Three kinds of push operations reference the stack pointer SP to write data from the source register to the stack PUSH instructions CALL instructions and interrupts In each case the SP is decreased by a number determined by the type of push operation and then points to the next available stack location PUSH Instructions A PUSH instruction references the SP to write two 4 bit data nibbles to the stack Two 4 bit stack addresses are referenced by the stack pointer one for the upper register value and another for the lower register After the PUSH has executed the SP is decreased by two and points to the next available stack location CALL Instructions When a subroutine call is issued the CALL instruction references the SP to write the PC s contents to six 4 bit stack locations Current values for the enable memory bank EMB flag and the enable register bank ERB flag are also pushed to the stack Since six 4 bit stack locations are used per CALL you may nest subroutine calls up to the number of levels permitted in the stack Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word PSW to the stack Six 4 bit stack locations are used to store this data After the interrupt has executed the SP is decreased by six and points to the next availab
51. TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 2 PROGRAMMING Using the Basic Timer 1 To read the basic timer count register BITS EMB SMB 15 BCNIR LD EA BONT LD 2 LD CPSE JR BCNTR 2 When stop mode is released by an interrupt set the oscillation stabilization interval to 31 3 ms BITS EMB SMB 15 LD A 0BH LD BMOD A gt time is 31 3 ms NOP STOP Set stop power down mode NOP NOP NOP NORMAL NORMAL CPU OPERATING MODE STOP MODE IDLE MODE OPERATING MODE OPERATION o S 31 3 ms STOP STOP MODE IS INSTRUCTION RELEASED BY INTERRUPT 3 To set the basic timer interrupt interval time to 1 95 ms at 4 19 MHz BITS EMB SMB 15 LD A 0FH LD BMOD A EI BITS IEB Basic timer interrupt enable flag is set to 1 4 Clear BCNT and the IRQB flag and restart the basic timer BITS EMB SMB 15 BITS BMOD 3 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS WATCHDOG TIMER MODE REGISTER WDMOD The watchdog timer mode register WDMOD is a 8 bit write only register located at RAM address F98H F99H WDMOD register controls to enable or disable the watchdog function WDMOD values are set to logic A5H following RESET and this value enables the watchdog timer and watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval WDMOD Watchdog Timer Enable Disable Control
52. either WX or EA The contents of the source are unaffected EA lt PC11 8 WX 1 T oro EC TNMEREREREREREREREREYS TER Examples 1 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator LD 00 CALL DISPLAY JPS MAIN ORG 0500H DB 66H DB 77H DB 88H DB 99H DISPLAY LDC EA lt address 0500H 66H RET If the instruction LD EA ZO1H is executed in place of 10 EA 00H The content of 0501H 77H is loaded to the EA register If LD EA 02H is executed the content of address 0502H 88H is loaded to EA 5 66 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET LDC Load Code Byte LDC Continued Examples 2 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator ORG 0500 DB 66H DB 77H DB 88H DB 99H DISPLAY LD WX 00H LDC EA WX gt EA lt address 0500H 66H RET If the instruction LD WX 01H is executed in place of LD WX 00H then EA lt address 0501H 77H If the instruction LD WX 02H is executed in place of LD WX 00H then EA address 0502H 88H Normally the LDC EA EA and the LDC EA OWX instructions reference the table data on the page on which the instruction is located If however the instruction is located at address it will reference table data on the next page
53. 0 0 0 0 0 0 Read Write R W R R R R W R W R W R W Bit Addressing 2 8 8 8 1 4 1 4 1 1 Carry Flag No overflow or borrow condition exists An overflow or borrow condition exists SC2 SCO Skip Condition Flags E No skip condition exists no direct manipulation of these bits is allowed A skip condition exists no direct manipulation of these bits is allowed 151 ISO Interrupt Status Flags olo Service all interrupt requests Service only the high priority interrupt s as determined in the interrupt priority register IPR 1 E Do not service any more interrupt requests Undefined EMB Enable Data Memory Bank Flag E Restrict program access to data memory to bank 15 and to the locations 000H 07FH in the bank 0 only 1 Enable full access to data memory banks 0 1 2 and 15 ERB Enable Register Bank Flag Select register bank 0 as working register area 1 Select register banks 0 1 2 or 3 as working register area in accordance with the select register bank SRB instruction operand NOTES 1 The value of the carry flag after aRESET occurs during normal operation is undefined If aRESET occurs during power down mode IDLE or STOP the current value of the carry flag is retained 2 Thecarry flag can only be addressed by a specific set of 1 bit manipulation instructions See Section 2 for detailed information 4 22 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP PUMOD
54. 12 5 15 CPU Control Instructions Binary Code Summary 5 14 5 16 Program Control Instructions Binary Code Summary 5 15 5 17 Data Transfer Instructions Binary Code 5 16 5 18 Logic Instructions Binary Code Summary 5 18 5 19 Arithmetic Instructions Binary Code Summary 5 19 5 20 Bit Manipulation Instructions Binary Code 5 20 S3C72N2 C72N4 P72N4 XV List of Tables Table Title Page Number Number 6 1 Power Control Register PCON Organization 6 5 6 2 Instruction Cycle Times for CPU Clock 6 6 6 3 System Clock Mode Register SCMOD Organization 6 7 6 4 Main Sub Oscillation Stop 6 8 6 5 System Operating Mode Comparison mme nenne 6 9 6 6 Elapsed Machine Cycles During CPU Clock Switch 6 11 6 7 Clock Output Mode Register CLMOD Organization 6 12 7 1 Interrupt Types and Corresponding Port Pin s
55. 3 1 EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS IMODO and IMOD1 The following components are used to process external interrupts at the INTO and INT1 pins Noise filtering circuit for INTO Edge detection circuit Two mode registers IMODO and IMOD1 The mode registers are used to control the triggering edge of the input signal IMODO and IMOD1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger Since INT2 is a quasi interrupt the interrupt request flag IRQ2 must be cleared by software IMODO 3 IMODO 1 IMODO O IMODO and IMOD1 are addressable by 4 bit write instructions RESET clears all IMOD values to logic zero selecting rising edges as the trigger for incoming interrupt requests Table 7 5 IMODO 1 and 2 Register Organization 779 effect ofiMODe Settings o Rising edge detecton wa 3 IMODO Both rising and falling edge detection IRQO flag cannot be set to 1 IMOD1i 0 Effect of IMOD1 Settings 00 Rising edge detection a Falling edge detection IMOD1 ELECTRONICS 7 8 53C72N2 C72N4 P72NA INTERRUPTS EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS Continued When a sampling clock rate of fxx 64 is used for INTO an interrupt request flag must be cleared before 16 machine cycles have elapsed
56. 5 56 dst operand Operation Summary Bytes Cycles ADR12 Jump to direct address 12 bits JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand The destination can be anywhere in the 4 Kbyte program memory address space Binary Code Operation Notation ime 1 s 1 5 9 3 4 Porroc 02 o o an eo rar ae ss c as ao The label SYSCON is assigned to the instruction at program location 07FFH The instruction JP SYSCON at location 0123H will load the program counter with the value O7FFH ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET JPS Jump Short JPS Operation Description Example dst Opeand Operation Summary Byes Cycles ADR12 Jump direct in page 12 bits JPS causes an unconditional branch to the indicated address with the 4 Kbyte program memory address space Bits 0 11 of the program counter are replaced with the directly specified address The destination address for this jump is specified to the assembler by a label or by an actual address in program memory Binary Code Operation Notation 3 an ato 29 as ar ae as at oo The label SUB is assigned to the instruction at program memory location OOFFH The instruction JPS SUB at location
57. 5AH Disable watchdog timer function Any other value Enable watchdog timer function WATCHDOG TIMER COUNTER WDCNT The watchdog timer counter WDCNT is a 3 bit counter WDCNT is automatically cleared to logic zero and restarts whenever the WDTCF register control bit is set to 1 RESET stop and wait signal clears the WDCNT to logic zero also WDONT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated When WDCNT has incremented to hexadecimal 07H it is cleared to OOH and an overflow is generated The overflow causes the system RESET When the interrupt request is generated BCNT immediately resumes counting incoming clock signals WATCHDOG TIMER COUNTER CLEAR FLAG WDTCF The watchdog timer counter clear flag WDTCF is a 1 bit write instruction When WDTCE is set to one it clears the WDONT to zero and restarts the WDCNT WDTCF register bits 2 0 are always logic zero Table 11 3 Watchdog Timer Interval Time BMOD BT Input Clock WDOCNT Input Clock WDT Interval Time Main Sub frequency frequency Clock Clock x000b fxx 212 x 28 212 x 28 x 23 Due pM fxx 29 fxx 29 x 28 29 x 28 x 23 fxx 218 7 250 28 32 Sec fxx 2 fxx 2 x 28 27 x 28 x 23 fxx 54 6 62 5 7 8 Sec fxx 29 fxx 29 x 28 25 x 28 x 23 fxx 13 6 15 6 1 75 2 ms Sec NOTES 1 Clock frequencies assume a system oscillator clock frequency fxx of 4 19 MHz Main clo
58. CYCLES 16 MACHINE CYCLES fx 4fxt 0 1 MACHINE CYCLE NOTES 1 Evenifoscillation is stopped by setting SCMOD 3 during main system clock operation the stop mode is not entered 2 Since the Xy input is connected internally to Ves to avoid current leakage due to the crystal oscillator in stop mode do not set SCMOD 3 to 1 or STOP instruction when an external clock is used as the main system clock 3 When the system clock is switched to the subsystem clock it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6 6 4 N A means not available 5 fx Main system clock Sub system clock M C Machine Cycle When fx is 4 19 MHz and fxt is 32 768 kHz 9 PROGRAMMING Switching Between Main System and Subsystem Clock 1 Switch from the main system clock to the subsystem clock MA2SUB BITS SCMOD 0 Switches to subsystem clock CALL DLY80 Delay 80 machine cycles BITS SCMOD 3 Stop the main system clock RET DLY80 LD A 0FH DEL1 NOP NOP DECS A JR DEL1 RET 2 Switch from the subsystem clock to the main system clock SUB2MA BITR SCMOD 3 Start main system clock oscillation CALL DLY80 Delay 80 machine cycles CALL DLY80 Delay 80 machine cycles BITR SCMOD 0 Switch to main system clock RET ELECTRONICS 6 11 OSCILLATOR CIRCUITS S3C72N2 C72N4 P72N4 CLOCK OUTPUT MODE REGISTER CLMOD The clock output mode register CLMOD is a 4 bit re
59. EA to indirect data memory LDI A HL Load indirect data memory to A increment register L contents and skip on carry 2 5 2 5 register L contents and skip on carry c EA EA Pop to register pair from stack Pop SMB and SRB values from stack 2 1 1 1 1 1 2 1 SB SB 4 2 2 T 10 S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 12 Logic Instructions High Level Summary i Bytes Logical AND A immediate data to A Logical AND A indirect data memory to A Logical AND register pair RR to EA Logical AND EA to register pair RRb Logical OR immediate data to A Logical OR indirect data memory contents to Logical OR double register to EA Logical OR to double register Exclusive OR immediate data to Exclusive OR indirect data memory to EA RR Exclusive OR register pair RR to EA RRb EA Exclusive OR register pair RRb to EA Complement accumulator A Table 5 13 Arithmetic Instructions High Level Summary Add indirect data memory to with carry Add register pair RR to EA with carry Add to register pair RRb with carry Add 4 bit immediate data to A and skip on carry Add 8 bit immediate data to EA and skip on carry A HL Add indirect data memory to A and skip on carry EA RR Add register pair RR contents to EA and skip on carry RRb EA Add EA to register pair RRb and skip on carry Subt
60. H X W Z Y to the A register Load 4 bit immediate data into the Ra register E L H X W Y Z Load 8 bit immediate data into the Ra register EA HL WX YZ There is a redundancy effect if the operation addresses the HL or EA registers Load contents of register A to direct data memory address Load contents of register A to 4 bit Ra register E L H X W Z Y ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET LD Load LD Concluded Examples Instruction Operation Description and Guidelines LD EA QHL Load data memory contents pointed to by 8 bit register HL to the A register and the contents of HL 1 to the E register The contents of register L must be an even number If the number is odd the LSB of register L is recognized as a logic zero an even number and it is not replaced with the true value For example 10 HL 36H loads immediate 36H to HL and the next instruction EA HL loads the contents of 36H to register A and the contents of 37H to register E LD EA DA Load direct data memory contents of DA to the A register and the next direct data memory contents of DA 1 to the E register The DA value must be an even number If it is an odd number the LSB of DA is recognized as a logic zero an even number and it is not replaced with the true value For example LD EA 37H loads the contents of 36H to the A register and the contents of 37H to the E register LD EA RRb Load 8 bit RRb regi
61. I O 4 0 3 3 4 bit I O port Port pins are individually software configurable as input or output 1 and 4 bit read write test is possible 4 bit pull up resistors are software assignable I O 4 6 0 6 3 FF6H 4 bit I O port Port 6 pins are individually software configurable as input or output 1 and 4 bit read write test is possible 4 bit pull up resistors are software assignable 8 0 8 7 1F8H 1FFH Output port for 1 bit data for use as CMOS driver only Table 10 2 Port Pin Status During Instruction Execution Instruction Type Example Input Mode Status Output Mode Status 1 bit test BIST 0 1 Input or test data at each pin Input or test data at output latch 1 bit input T C P1 3 4 bit input 1 1 bit output BITR P2 3 Output latch contents undefined Output pin status is modified 4 bit output P2 A Transfer accumulator data to the Transfer accumulator data to the output latch output pin ELECTRONICS 10 2 53C72N2 C72N4 P72NA PORTS PORT MODE FLAGS PM FLAGS Port mode flags PM are used to configure I O ports to input or output mode by setting or clearing the corresponding buffer For convenient program reference PM flags are organized into two groups PMG1 and 2 as shown in Table 10 3 They are addressable by 8 bit write instructions only When a PM flag is O the port is set to input mode when it is 1 the port is enabled for output RESET clears all por
62. Operation Notation C mema b C C OR memb 7 2 L 3 2 Examples 1 The carry flag is logically ORed with the P1 0 value 0 C P1 0 1 then C lt 1 if P1 0 0 then lt 2 The P1 address is FF1H and register L contains the value 1001B The address 7 2 is 111100B and 3 2 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD L 9H BOR C P1 L P1 L is specified as P2 1 C OR P2 1 ELECTRONICS 5 35 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 BOR Bit Logical OR BOR Examples 5 36 Continued 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BOR C H FLAG C OR FLAG 20H 3 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BISF Bit Test and Skip on False BTSF dst b Operation Operand Operation Summary Bytes Cycles Test specified memory bit and skip if bit equals O __ 2 aes 2 gt erbas as Description specified bit within the destination operand is tested If it is 0 the BTSF instruction skips the instruction which immediate
63. P72N4 EMB FLAG EMB ADDRESS SPACES The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12 bit data memory addresses In this way it controls the addressing mode for data memory banks 0 1 or 15 When the flag is 0 the data memory address space is restricted to bank 15 and addresses 000H 07FH of memory bank 0 regardless of the SMB register contents When the EMB flag is set to 1 the general purpose areas of bank 0 1 and 15 can be accessed by using the appropriate SMB value PROGRAMMING Using the EMB Flag to Select Memory Banks EMB flag settings for memory bank selection 1 When EMB 0 SMB LD LD LD SMB LD LD SMB LD LD 2 When EMB 1 SMB LD LD LD SMB LD LD SMB LD LD ELECTRONICS 9H 90H A 34H A 90H A 34H A 15 20H A 90H A A 9H OFOH A 90H A 34H A 20H A 90H A Non essential instruction since EMB 0 lt A bank 15 is selected 034 lt A bank 0 is selected Non essential instruction since EMB 0 lt A bank 15 is selected 034 A bank 0 is selected Non essential instruction since EMB 0 020 lt A bank 0 is selected lt A bank 15 is selected Select memory bank 1 1 lt A bank 1 is selected 1FOH lt A bank 1 is selected Select memory bank 0 090 lt A bank 0 is selected 034 A b
64. Vor OUI 15 8 16 1 SMDS Product Configuration 5 52 nene nnne 16 2 16 2 TB72N2 4 Target Board COnniguratiOn m a Quq Q s 16 3 16 3 40 Pin Connectors for TB72N2 4 16 6 16 4 TB72N2 4 Adapter Cable for 64 QFP Package S3C72N2 C72N4 P72N4 16 6 S3C72N2 C72N4 P72N4 xiii List of Tables Table Title Page Number Number 1 1 S3C72N2 C72N4 Pin Descriptions 1 5 2 1 Program Memory Address 2 1 2 2 Data Memory Organization and Addressing 2 8 2 3 Working Register Organization and Addressing 2 10 2 4 Hegister OrganizallOEI su os 2 16 2 5 Program Status Word Bit Descriptions 2 2 17 2 6 Interrupt Status Flag Bit Settings 2 22 4 2 18 2 7 Valid Carry Flag Manipulation Instructions 2 21 3 1 RAM Addressing Not Affected by the Value 3 4 3 2 1 Bit Direct and Indirect RAM Addressing 3 6 3 3 4 Bit Direct and Indirect RAM Addressing
65. after aRESET Clear Signal Bits Y Instruction Clock Request Selector 9 1 Bit R W gt Cpu Clock Start Signal By Interrupts Clock Input By RESET 1 pulse period BT input clock 21 2 duty 3 Bit Counter Overflo Generation Y WDTCF Wait Stop 4 NOTE WAIT means stabilization time Instruction after RESET or Stabilization time after STOP mode release Figure 11 1 Basic Timer Circuit Diagram ELECTRONICS TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 BASIC TIMER MODE REGISTER BMOD The basic timer mode register BMOD is a 4 bit write only register Bit 3 the basic timer start control bit is also 1 bit addressable All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval BT counter operation cannot be stopped BMOD settings have the following effects Restart the basic timer Control the frequency of clock signal input to the basic timer Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt By loading different values into the BMOD register you can dynamically modify the basic timer clock frequency during program execution Four BT frequencies ranging from fxx 2 to fxx 2 are selectable Since BMOD s reset value is logic zero the default clock frequency setting is fxx 21 The most significant
66. by any other instruction the memc and 1 instructions are executed Instructions referenced by REF occupy 2 bytes of memory space for two 1 byte instructions or one 2 byte instruction and must be written as an even number from 0020H to 007FH in ROM In addition the destination address of the TJP and TCALL instructions must be located with the OFFFH address TJP and TCALL are reference instructions for JP JPS and CALL CALLS If the instruction following a REF is subject to the redundancy effect the redundant instruction is skipped If however the REF follows a redundant instruction it is executed On the other hand the binary code of a REF instruction is 1 byte The upper 4 bits become the higher address bits of the referenced instruction and the lower 4 bits of the referenced instruction x 1 2 becomes the lower address producing a total of 8 bits or 1 byte see Example 3 below ELECTRONICS 5 75 SAM47 INSTRUCTION SET REF Reference Instruction 53 72 2 72 4 72 4 Continued Examples 1 Instructions can be executed efficiently using REF as shown in the following example ORG 0020H AAA LD HL 00H BBB LD EA FFH CCC TCALL SUB1 DDD SUB2 ORG 0080H LD HL 00H REF BBB LD EA FFH REF CCC CALL 081 REF DDD JP SUB2 3 2 The following example shows how the REF instruction is executed in relation to LD Instructions that have a redundancy effect AAA 5 7
67. byte sizes that are stored in addresses 0020H 007FH of program memory This 96 byte area is called the REF instruction reference area or look up table Locations in the REF look up table may contain two one byte instructions a single two byte instruction or three byte instruction such as a JP jump or CALL The starting address of the instruction you are referencing must always be an even number To reference a JP or CALL instruction it must be written to the reference area in a two byte format for JP this format is TJP for CALL it is TCALL By using REF instructions to execute instructions larger than one byte you can improve program execution time considerably by reducing the number of program steps In summary there are three ways you can use the REF instruction Using 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch instruction stored in the look up table Calling subroutines at any location by referencing a call instruction stored in the look up table PROGRAMMING Using the REF Look Up Table Here is one example of how to use the REF instruction look up table JMAIN KEYCK WATCH INCHL ABC MAIN 2 4 ORG BISF TCALL LD INCS LD ORG NOP NOP REF REF REF REF REF 0020H MAIN KEYFG CLOCK HL A HL EA 00H 0080H KEYCK JMAIN WATCH INCHL ABC 0 MAIN 1 KEYFG CHECK 2 CALL CLO
68. data to EA and skip on overflow o3 f A HL Add indirect data memory to A and skip on overflow EA RR Add register pair RR contents to EA and skip on 2 5 overflow RRBEA EA Add EA to register pair RRb and skip on overflow The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the skip signal is generated and a skip is executed but the carry flag value is unaffected If ADS follows an ADC A HL instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This skip condition is valid only for ADC A HL instructions however If an overflow occurs following an ADS instruction the next instruction is not skipped Fs x o az or im sp on overiow ENKA 1 1 of o 4 EA EA imm skip on overflow 1 1 ACA HG overtiow 1 1 0 0 EA EA RR skip on overflow o A S N ES EN 1 1 0 0 RRb lt RRb skip on overflow 1 The extended accumulator contains value register pair HL the value and the carry flag 0 ADS EA HL EA lt 6DH C lt 0 ADS skips on overflow but carry flag v
69. for Oscillation Stabilization After 2 9 1 10 1 Input OR ud daa DEUS Gema tS faxa ul 10 5 10 2 PORZ ei cid S EUN M 10 6 10 3 POMS ando GIFeilt DIAGK AM unasususeysapasqpaqauspskassspashusasaqunskia pupusa 10 7 11 1 Basie Got Diag 2 11 3 11 2 TC O 11 11 11 3 TOD TIE SAG KAN ux oven um e e 11 19 11 4 Watch Timer Circuit BI 11 24 12 1 12 1 12 2 LOD MANN 12 2 12 3 LCD Display Data RAM Organization 12 3 12 4 Voltage Dividing Resistor Circuit 12 7 12 5 LCD Signal Waveforms in Static 12 8 12 6 LCD Connection Example in Static Mode 12 9 12 7 LCD Signal Waveforms at 1 2 Duty 1 2 Bias 12 10 12 8 LCD Connection Example at 1 2 Duty 1 2 Bias 12 11 12 9 LCD Signal Waveforms at 1 3 Duty 1 2 Bias 12 12 12 10 LCD Signal Waveforms at 1 3 Duty 1 3 Bias 12 13 12 1
70. from the destination operand leaving the result in the destination SBC sets the carry flag if a borrow is needed for the most significant bit otherwise it clears the carry flag The contents of the source are unaffected If the carry flag was set before the SBC instruction was executed a borrow was needed for the previous step in multiple precision subtraction In this case the carry bit is subtracted from the destination along with the source operand operand Binary Code operation Notation T9 1 1 o o lt ajo o 5 1 The extended accumulator contains the value register pair HL the value and the carry flag is set to 1 SCF C e 1 SBC EA HL lt OAAH 1H lt 0 JPS XXX Jump to XXX no skip after SBC 2 If the extended accumulator contains the value register pair HL the value OAAH and the carry flag is cleared to O 0 SBC EA HL lt 19H C lt 0 JPS XXX Jump to XXX no skip after SBC 5 80 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET SBC Subtract With Carry SBC Examples Continued 3 If SBC A HL is followed by an ADS A im the SBC skips on no borrow to the instruction immediately after the ADS An ADS A im instruction immediately after the SBC A HL instruct
71. gt TIMER START INSTRUCTION IRQTO SET IRQTO SET TMODO 3 IS SET Figure 11 3 TCO Timing Diagram ELECTRONICS 11 19 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 TCO REFERENCE REGISTER TREFO The TCO reference register TREFO is an 8 bit write only register It is addressable by 8 bit RAM control instructions RESET initializes the TREFO value FFH TREFO is used to store a reference value to be compared to the incrementing TCNTO register in order to identify an elapsed time interval Reference values will differ depending upon the specific function that TCO is being used to perform as a programmable timer counter event counter clock signal divider or arbitrary frequency output source During timer counter operation the value loaded into the reference register is compared to the TCNTO value When TREFO the TCO output latch TOLO is inverted and an interrupt request is generated to signal the interval or event The TREFO value together with the TMODO clock frequency selection determines the specific TCO timer interval Use the following formula to calculate the correct value to load to the TREFO reference register 1 frequency setting TCO timer interval TREFO value 1 x TREFO value 0 TCO OUTPUT ENABLE FLAG TOEO The 1 bit timer counter O output enable flag TOEO controls output from timer counter 0 to the TCLOO pin TOEO is addressable by 1 bit write instructions
72. has executed the SP is incremented by six and points to the next free stack location IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET IRET references the SP to locate the six 4 bit stack addresses used for the interrupt and to write this data back to the PC and the PSW After the IRET has executed the SP is incremented by six and points to the next free stack location POP RET OR SRET IRET SP SP 2 SP lt SP 6 SP 4 5 6 Figure 2 8 Pop Type Stack Operations ELECTRONICS 2 15 ADDRESS SPACES 53 72 2 72 4 72 4 SEQUENTIAL CARRIER BSC The bit sequential carrier BSC is a 16 bit general register that can be manipulated using 1 4 and 8 bit RAM control instructions RESET clears all BSC bit values to logic zero Using the BSC you can specify sequential addresses and bit locations using 1 bit indirect addressing memb L Bit addressing is independent of the current EMB value In this way programs can process 16 bit data by moving the bit location sequentially and then incrementing or decreasing the value of the L register BSC data can also be manipulated using direct addressing For 8 bit manipulations the 4 bit register names BSCO and BSC2 must be specified and the upper and lower 8 bits manipulated separately If the values of the register are at BSCO L the address and bit location assignment is FCOH O If the L register content is at BSCO
73. instruction The tables in this Chapter are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions 5 8 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 9 CPU Control Instructions High Level Summary Draenen ooa e 2 Engage Pue m 2 2 Engage PU sopro 2 2 rra Select memory bank Select register bank EMB 0 1 Load enable memory bank flag EMB and the enable ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location n n Table 5 10 Program Control Instructions High Level Summary gt JJ T EA Return from subroutine and skip 349 ELECTRONICS 5 9 SAM47 INSTRUCTION SET S3C72N2 C72N4 P72NA Table 5 11 Data Transfer Instructions High Level Summary Name oporana Operation Description Bytes Cycles Exchange A and register Ra contents Exchange EA and register pair RRb contents 2 increment contents of register L and skip on carry decrement contents of register L and skip on carry HL A Load contents of A to indirect data memory DA EA Load contents of EA to data memory RRb EA Load contents of EA to register HL EA Load contents of
74. or during a power down mode most hardware register values are set to the reset values described in Table 9 1 The current status of several register values is however always retained when a RESET occurs during idle or stop mode If a RESET occurs during normal operating mode their values are undefined Current values that are retained in this case are as follows Carry flag Data memory values General purpose registers E A L H X W Z and Y OSCILLATION STABILIZATION 31 3 ms 4 19 MHz INPUT NORMAL MODE IDLE MODE OPERATING MODE OR e POWER DOWN MODE RESET OPERATION Figure 9 1 Timing for Oscillation Stabilization After RESET HARDWARE REGISTER VALUES AFTER RESET Table 9 1 gives you detailed information about hardware register values after a RESET occurs during power down mode or during normal operation ELECTRONICS 9 1 RESET S3C72N2 C72N4 P72N4 Table 9 1 Hardware Register Values After RESET Hardware Component If RESET Occurs During If RESET Occurs During or Subcomponent Power Down Mode Normal Operation Program counter PC Lower four bits of address 0000 Lower four bits of address 0000 are transferred to PC11 8 and the are transferred to 11 8 and the contents of 0001H to 7 0 contents of 0001H to 7 0 Program Status Word PSW Interrupt status flags 150 151 Bank enable flags EMB ERB Bit 6 of address 0000H in pr
75. pins Output low lt 0 leakage All output pins current Pull up 4 0 V Vpp 5 V resistor Ports 1 2 3 6 2 0 Vpp 5 V RESET V pp 3 V LCD voltage Ricp 25 120 dividing resistor COM output impedance COM output voc 5 V VLCO COMi voltage deviation lo 15uA 0 3 ELECTRONICS 13 3 ELECTRICAL DATA S3C72N2 C72N4 P72N4 Table 13 2 D C Electrical Characteristics Continued TA 25 C to 85 1 8V to 5 5 V SEG output V pp 5 V VLCO SEGi voltage lo 15uA i 0 31 deviation Output 25 C voltage VLC1 Output 25 C voltage VLC2 Output VLC2 25 C 0 2 DD 0 200 0 2VDD voltage 0 2 0 2 13 4 53 72 2 72 4 72 4 ELECTRICAL DATA Table 13 2 D C Electrical Characteristics Concluded 25 C to 85 Vpp 1 8V to 5 5 V Supply Current Ipp 2 operating 6 0 MHz 1 V pp 5 V 10 4 19 MHz CPU fx 4 SCMOD 0000B Crystal oscillator Vp 3 V 10 6 0 MHz 4 19 MHz m 2 Main idle mode 6 0 MHz Vpp 5 Vt 10 4 19 CPU fx 4 SCMOD 0000B Crystal oscillator Vpp 10 6 0 MHz 4 19 MHz 1503 Sub operating 10 CPU fxt 4 SCMOD 1001B 32 kHz crystal oscillator oub idle mode Vpp 3 V 10 CPU 4 SCMOD 1001B 32 kHz crystal oscillator IDD5 otop mode V4 25 C 5V 10 CPU f
76. s manual for the first time we recommend that you read Sections 1 3 carefully and just scan the detailed information in Sections 4 and 5 very briefly Later you can refer back to Sections 4 and 5 as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C72N2 C72N4 P72N4 microcontroller Also included in Part Il are electrical mechanical OTP and development tools Part has 11 sections Section 6 Oscillator Circuits Section 12 LCD Controller Driver Section 7 Interrupts Section 13 Electrical Data Section 8 Power Down Section 14 Mechanical Data Section 9 RESET Section 15 S3P72N4 OTP Section 10 I O Ports Section 16 Development Tools Section 11 Timers and Timer Counter Two order forms are included at the back of this manual to facilitate customer order for SSC72N2 C72N4 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative 53 72 2 72 4 72 4 Table of Contents Part Programming Model Chapter 1 Product Overview 1 1 Gp rem 1 1 KARINERENERERRRCRUROR PORE 1 2 DS CIMACT OC SS ai E E aL XE 1 2 eese Bites Fus ool Eva 1 3 1 4 898 9 ETE E 1 5 PIO reai
77. selects the input clock frequency and controls interrupt or stabilization intervals Interval Timer Function The measurement of elapsed time intervals is the basic timer s primary function The standard interval is 256 BT clock pulses To restart the basic timer set bit 3 of the mode register BMOD to logic one The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD 2 BMOD 0 The 8 bit counter register BCNT is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD continues incrementing as it counts BT clocks until an overflow occurs An overflow causes the BT interrupt request flag IRQB to be set to logic one to signal that the designated time interval has elapsed An interrupt request is then generated BCNT is cleared to logic zero and counting continues from Oscillation Stabilization Interval Control Bits 2 0 of the BMOD register are used to select the input clock frequency for the basic timer This setting also determines the time interval also referred to as wait time required to stabilize clock signal oscillation when power down mode is released by an interrupt When a RESET signal is generated the standard stabilization interval for system clock oscillation following a RESET is 31 3 ms at 4 19 MHz Watchdog Timer Function The basic timer can also be used as a watchdog timer to de
78. setting 13 8 ELECTRONICS 53 72 2 72 4 72 4 ELECTRICAL DATA CPU CLOCK Main OSC Freq 1 5 MHz 1 0475 MHz 790 KHz 500 kHz 250 kHz 15 6 kHz SUPPLY VOLTAGE V CPU CLOCK 1 n x oscillator frequency n 4 8 64 Figure 13 1 Standard Operating Voltage Range Table 13 7 RAM Data Retention Supply Voltage in Stop Mode TA 25 85 Data retention supply current VpppR 2 0 V Release signal set time Normal operation time 1 Oscillator stabilization wait Released by RESET Released by interrupt NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use the basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time ELECTRONICS 13 9 ELECTRICAL DATA S3C72N2 C72N4 P72N4 TIMING WAVEFORMS INTERNAL RESET OPERATION 8 STOP 474 DLE MODE OPERATING MODE lt DATA RETENTION MODE P gt 4 VDDDR EXECUTION OF STOP INSTRUCTION lt Figure 13 2 Stop Mode Release Timing When Initiated By RESET IDLE MODE NORMAL 448 31 STOP MODE lt OPERATING DATA RETENTION MODE gt MODE VDDDR EXECUTION OF STOP INSTRUCTION POWER DOWN MODE TERMINATING SIGNAL INTERRUPT REQUEST Figure 13 3 Stop Mode Release Timing When Initiated By Interrupt Reques
79. stores the values 2H and OH in RAM locations OF9H and OF8H respectively ELECTRONICS 5 73 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 RCF RCF Operation Description Example 5 74 Reset Carry Flag The carry flag is cleared to logic zero regardless of its previous value Binary Code Operation Notation Loc Assuming the carry is set to logic one the instruction RCF resets clears the carry flag to logic zero ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET REF REF Operation Description Reference Instruction dst The REF instruction for a 16K CALL instruction is 4 cycles The REF instruction is used to rewrite into 1 byte form arbitrary 2 byte or 3 byte instructions or two 1 byte instructions stored in the REF instruction reference area in program memory REF reduces the number of program memory accesses for a program Binary Code Operation Notation TJP and TCALL are 2 byte pseudo instructions that are used only to specify the reference area 1 When the reference area is specified by the TJP instruction 6 00 11 0 lt memc 3 0 memc 1 2 When the reference area is specified by the TCALL instruction memc 6 01 SP 4 SP 1 SP 2 lt 11 0 SP 3 EMB ERB 0 0 11 0 lt memc 3 0 memc 1 SP lt SP 4 When the reference area is specified
80. target Vcc SYSTEM system must have its own Vss gt power supply Table 16 2 Main clock Selection Settings for TB72N2 4 Set the XI switch to MDS EVA CHIP when the target board is KS57E2304 connected to the 4 5 052 5 052 X XOUT No connection 100 pin connector SMDS2 SMDS2 Set the XI switch to XTAL when the target board is used EVA CHIP as a standalone unit and is KS57E2304 not connected to the 4 SMDS2 SMDS2 1 XOUT TARGET BOARD 16 4 ELECTRONICS 53C72N2 C72N4 P72NA DEVELOPMENT TOOLS Table 16 3 Sub clock Selection Settings for TB72N2 4 Sub Clock Setting Operating Mode Set the switch to MDS EVA CHIP when the target board is KS57E2304 connected to the SMDS2 SMDS2 XOUT XN No connection 100 pin connector SMDS2 SMDS2 Set the XTI switch to XTAL when the target board is used EVA CHIP as a standalone unit and is KS57E2304 not connected to the 4 SMDS2 SMDS2 XI XTiN OUT XTAL TARGET BOARD Table 16 4 Using Single Header Pins as the Input Path for External Trigger Sources Connector from external trigger EXTERNAL sources of the TRIGGERS application system You can connect an external trigger source to one of the two external trigger channels CH1 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation chip KS57E2304 is in idle mode STOP LED
81. the system clock fxx is used as the signal source according to the following formula y lock fxx Watch timer clock fw 2 m XX 32 768 kHz 4 19 MHz This feature is useful for controlling timer related operations during stop mode When stop mode is engaged the main system clock fx is halted but the subsystem clock continues to oscillate By using the subsystem clock as the oscillation source during stop mode the watch timer can set the interrupt request flag IRQW to 1 thereby releasing stop mode Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller fj Therefore if the watch timer is disabled the LCD controller does not operate 11 22 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz 4 kHz 8 kHz or 16 kHz signal to the BUZ pin To select the desired BUZ frequency load the appropriate value to the WMOD register This output can then be used to actuate an external buzzer sound To generate a BUZ signal three conditions must be met WMOD 7 register bit is set to 1 The output latch for port 2 3 is cleared to 0 The port 2 3 output mode flag PM2 set to output mode Timing Tests in High Speed Mode By setting WMOD 1 to 1 the watch timer will function in high speed mode generating an interrupt every 3 91 ms At it
82. time is 1 256 x BT clock fx Reset Interrupt can t start the main oscillation Therefore the CPU operation can never be restarted BToverflow and reset After the overflow of basic timer 1 256 x BT clock fxt CPU operation and main oscillation automatically start Set SCMOD 3 to 0 or reset Set SCMOD 2 to 0 or reset 2 Oscillation stabilization time by interrupt is 1 256 x BT clocks Oscillation stabilization time by a reset is 31 3ms 4 19Mhz main oscillation clock 6 8 ELECTRONICS S3C72N2 C72N4 P72N4 Main operating mode Main Idle mode Main Stop mode Sub operating mode Sub Idle Mode Sub Stop mode Main Sub Stop mode OSCILLATOR CIRCUITS Table 6 5 System Operating Mode Comparison Mode Condtin STOP IDLE Mode Start Method Current Consumption Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main oscillator runs Sub oscillator runs stops System clock is the main oscillation clock Main oscillator runs Sub oscillator runs System clock is the main oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs oystem clock is the sub oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs oystem clock is the sub oscillation clock Main oscillator is stopped by SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Ma
83. 1 IRQxis set to request an interrupt when an interrupt meets the set condition for interrupt generation 2 1 is set to 1 by hardware and then cleared by hardware when the interrupt has been serviced with the exception of IRQW and 2 3 When IRQx is set to 1 by software an interrupt is generated Table 7 8 Interrupt Request Flag Conditions and Priorities Source External Priority Name E or taling edge detected at NTOpin 2 mo NW o Time interval of 0 5 secs or 3 19 msecs RW NOTE The quasi interrupt INT2 is only used for testing incoming signals ELECTRONICS 7 13 INTERRUPTS NOTES 53C72N2 C72N4 P72NA ELECTRONICS 53C72N2 C72N4 P72NA POWER DOWN POWER DOWN OVERVIEW The S38C72N2 C72N4 microcontroller has two power down modes to reduce power consumption idle and stop Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP Several NOP instructions must always follow an IDLE or STOP instruction in a program In idle mode the CPU clock stops while peripherals and the oscillation source continue to operate normally When RESET occurs during normal operation or during a power down mode a reset operation is initiated and the CPU enters idle mode When the standard oscillation stabilization time interval 31 3 ms at 4 19 MHz has elapsed normal CPU operation resumes In main stop mode main system clock oscillation is halted assuming main c
84. 1 LCD Connection Example at 1 3 Duty 1 3 Bias 12 14 12 12 LCD Signal Waveforms at 1 4 Duty 1 3 Bias 12 15 12 13 LCD Connection Example at 1 4 Duty 1 3 Bias 12 16 xii S3C72N2 C72N4 P72NA List of Figures Continued Figure Title Page Number Number 13 1 Standard Operating Voltage Range 13 9 13 2 Stop Mode Release Timing When Initiated By 13 10 13 3 Stop Mode Release Timing When Initiated By Interrupt Request 13 10 13 4 A C Timing Measurement Points Except for and 13 11 13 5 Clock Timing Measurement at nennen menn des 13 11 13 6 Clock Timing Measurement at AT iri iecore tak ur rut vx E Tr Parti uc mou a nee EA ed 13 11 13 7 REG EDEN oe EC 13 12 13 8 INET Timitig Tor RESET 13 12 13 9 Input Timing for External Interrupts and Quasi Interrupts 13 12 14 1 64 QFP 1420F Package Dimensions 14 1 15 1 S3P72N4 Pin Assignments 64 QFP 15 2 15 2 Standard Operating Voltage Range 15 7 15 3 le VS
85. 2 2 72 4 72 4 Table 13 4 Subsystem Clock Oscillator Characteristics TA 25 C 85 C 1 8V to 5 5 V Crystal Oscillation frequency Oscillator Stabilization time 2 4 5 V to 5 5 V Vpp 1 8 V to 4 5 V External XT input frequency Clock 1 XTiN input high and low level width 1 Oscillation frequency and frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs Table 13 5 Input Output Capacitance TA 25 C Vpg2 0 V Symbol CiN f 1 MHz Unmeasured pins are returned to Voc ELECTRICAL DATA capacitance Cio ELFCTRONICS 13 7 ELECTRICAL DATA S3C72N2 C72N4 P72N4 Table 13 6 A C Electrical Characteristics 25 C to 85 1 8 V to 5 5 V perons f MM MN MEE Instruction cycle Vpp 2 7 V to 5 5 V time 1 Vpp 18 V to 5 5 V With subsystem clock fxt frequency a 1 8 V to 5 5 V TCLO input high Uno 2 7 to 55V low width Vip 18 V to 5 5 V Interrupt input tinge tiri INTO high low width INT2 KS0 KS3 RESET Input Low trop Input 10 Width NOTES 1 Unless otherwise specified Instruction Cycle Time condition values assume a main system clock fx source 2 Minimum value for INTO is based on a clock of 2tcy or 128 fx as assigned by the IMODO register
86. 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 3 1 Bits 3 1 Always logic zero 0 External Interrupt 1 Edge Detection Control Bit Rising edge detection Falling edge detection 4 14 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP IMOD2 External Interrupt 2 INT2 Mode Register FB6H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 2 Bits 3 2 Always logic zero 1 0 External Interrupt 2 Edge Detection Selection Bit ELECTRONICS 4 15 MEMORY S3C72N2 C72N4 P72N4 IPR Interrupt Priority Register FB2H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 4 4 4 4 IME Interrupt Master Enable Bit Disable interrupt processing Enable processing for all interrupt service requests 2 0 Interrupt Priority Assignment Bits Normal interrupt handling according to default priority settings Process INTB interrupt at highest priority Process INTO interrupt at highest priority 1 Process INT1 interrupt at highest priority Process INTTO interrupt at highest priority 4 16 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP Lcp Output Control Register F8EH Bit 3 2 1 0 Identifier 2 ow lt o RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 2 1 Bit 1 Always logic zero 0 LCD Display Control Bit If LMOD 3 0 turn display off output port 8 latch content
87. 21 53 72 2 72 4 72 4 022000 USER S MANUAL S3C72N2 C72N4 P72N4 4 Bit CMOS Microcontroller Revision 1 ELECTRONICS 93C72N2 C72N4 P72NA 4 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C72N2 C72N4 P72N4 4 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 C72N2 C72N4 P72N4 022000 2000 Samsung Electronics Typical paramete
88. 3 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Lee Kiheung Eup Yongin City Kyungi Do Korea 37 Suwon 449 900 TEL 02 760 6530 0331 209 6530 02 760 6547 Home Page URL Http www samsungsemi com Printed in the Republic of Korea Preface The 53 72 2 72 4 Microcontroller User s Manual is designed for application designers and programmers who are using S8C72N2 C72N4 microcontroller for application development It is organized in two main parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Memory Map Chapter 2 Address Spaces Chapter 5 Instruction Set Chapter 3 Addressing Modes section 1 Product Overview is a high level introduction to the S8C70F2 C70F4 P70F4 ranging from a general product description to detailed information about pin characteristics and circuit types Section 2 Address 5 introduces you to the S3C70F2 C70F4 P70F4 programming model the program memory ROM and data memory RAM structures and how to address them Section 2 also includes information about stack operations CPU registers and the bit sequen
89. 32 768 kHz watch timer clock ELECTRONICS 12 5 LCD CONTROLLER DRIVER 53C72N2 C72N4 P72NA Table 12 5 LCD Clock Signal LCDCK Frame Frequency and LCD sync Signal LCDSY LCDCK Frequency Static 1 2 Duty 1 3 Duty 1 4 Duty fw 29 64 Hz 64 16 32 16 21 21 16 16 fw 28 128 Hz 128 32 64 32 43 43 32 32 fw 27 256 Hz 256 64 128 64 85 85 64 64 fw 26 512 Hz 512 128 256 128 171 171 128 128 NOTES 1 fw 32 768 kHz 2 number in parentheses is a frequency for LCDSY LCD DRIVE VOLTAGE LCD Power Supply Static Mode 1 2 Bias 1 3 Bias NOTE TheLCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistors for the LCD drive power supply can be configured by internal voltage dividing resistors Using these internal voltage dividing resistors you can drive either a 3 volt or a 5 volt LCD display using external bias Bias pins are connected externally to the cp pin so that it can handle the different LCD drive voltages To cut off the current supply to the voltage dividing resistors clear 0 when you turn the LCD display off COMMON COM SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle n 1 2 duty mode COMO COM pins are selecte
90. 3H 6EH e 1 JPS Jump to XXX no skip after ADC ELECTRONICS S3C72N2 C72N4 P72N4 ADC with Carry ADC Examples Continued 3 SAM47 INSTRUCTION SET lf ADC A HL is followed by an ADS A im the ADC skips on carry to the instruction immediately after the ADS An ADS instruction immediately after the ADC does not skip even if an overflow occurs This function is useful for decimal adjustment operations a 8 9 decimal addition the contents of the address specified by the HL register is 9H LD ADS ADC ADS JPS A 8H A 6H A HL J C lt 0 lt 8H lt 8H 6H OEH lt 1 okip this instruction because 1 after ADC result b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF LD ADS ADC ADS JPS ELECTRONICS A 3H A 6H A HL J J 3 C lt 0 A lt lt lt 4H C 0 No skip A lt 7H The skip function for ADS is inhibited after instruction even if an overflow occurs 5 25 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 ADS ADS Operation Description Examples 5 26 Add And Skip On Overflow dst src Add 4 bit immediate data to A and skip on overflow 1 Add 8 bit immediate
91. 4 Pin Circuit Type A 4 P1 ELECTRONK S PRODUCT OVERVIEW P CHANNEL OUT N CHANNEL OUTPUT DISABLE Figure 1 5 Pin Circuit Type C PULL UP RESISTOR RESISTOR ENABLE P CHANNEL DATA CIRCUIT OUTPUT DISABLE CIRCUIT TYPE A Figure 1 6 Pin Circuit Type D P2 P3 and P6 1 7 PRODUCT OVERVIEW S3C72N2 C72N4 P72N4 LCD SEGMENT COMMON DATA SCHMITT TRIGGER Figure 1 9 Pin Circuit Type B RESET LCD SEGMENT amp PORT 8 DATA Figure 1 8 Pin Circuit Type H 1 P8 1 8 ELECTRONES S3C72N2 C72N4 P72N4 ADDRESS SPACES ADDRESS SPACES PROGRAM MEMORY ROM OVERVIEW ROM maps for S8C72N2 C72N4 devices are mask programmable at the factory S3C72N2 has 2K x 8 bit program memory and S3C72N4 has 4K x 8 bit program memory aside from the differences in the ROM size the two products are identical in other features In its standard configuration the device s 4 096 x 8 bit program memory has four areas that are directly addressable by the program counter PC 12 byte area for vector addresses 96 byte instruction reference area 20 byte general purpose area 1920 byte general purpose area 53 72 2 3968 byte general purpose area 53 72 4 General Purpose Program Memory Two program memory areas are allocated for general purpose use One area is 20 bytes in size and the other is 1 920 bytes S3C72N2 3 968 bytes S3C72N4 Vector Addresses A 12 byte vector a
92. 6 ORG LD HEF HEF LD SHB 0020H LD 40 0100H 30 EA 50H 2 J 5 Not skipped Skipped ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Reference Instruction REF Concluded Examples In this example the binary code of REF at locations 20 21 is 20H for REF at locations 22H 23H it is 21H and for REF at 24 25 the binary code is 22H Opcode Symbol Instruction ORG 0020H 83 00 1 LD HL 00H 83 03 A2 LD HL 03H 83 05 A3 LD HL 05H 83 10 A4 LD HL 10H 83 26 A5 LD HL 26H 83 08 A6 LD HL 08H 83 OF 7 LD 83 FO A8 LD HL 0FOH 83 67 A9 LD HL 067H 41 OB A10 TCALL SUB1 01 00 A11 TJP SUB2 ORG 0100H 20 REF 1 LD HL 00H 21 REF A2 LD HL 03H 22 REF A3 LD 05 23 4 LD HL 10H 24 REF A5 LD HL 26H 25 LD HL 08H 26 REF 7 LD HL ZOFH 2 HEF A8 LD 30 9 LD HL 067H 31 REF A10 CALL 5081 32 11 JP SUB2 ELECTRONICS 5 77 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 RET Return From Subroutine RET Operation Description Example 5 78 RET pops the PC values successively from the stack incrementing the stack pointer by six Program execution continues from the resulting address generally the instruction immediately following a CALL or CALLS Binary Code Operation Notation PC11 8 lt SP 1 SP
93. 8 bit working registers Select register bank n Select memory bank n Carry flag Program status word Port n m th bit of port n Interrupt priority register Enable memory bank flag Enable register bank flag 5 6 3C72N2 C72N4 P72N4 Table 5 6 Instruction Operand Notation Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4 bit immediate data number 8 bit immediate data number Immediate data prefix 000H 1FFFH immediate address n bit address A E L H X W Z Y E L H X W Z Y EA HL WX YZ HL WX WL HL WX YZ WX WL Code direct addressing 0020 007 Select bank register 8 bits Logical exclusive OR Logical OR Logical AND Contents addressed by ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET OPCODE DEFINITIONS Table 5 7 Opcode Definitions Direct Table 5 8 Opcode Definitions Indirect resister 2 _ o HL 1 0 1 WX 1 1 0 WL 1 1 1 i Immediate data for indirect addressing eme eee Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock Three different clock rates can be selected using the PCON register In this document the letter S is used in tables when describing the number of add
94. A HL LDD A HL 1 lt HL then L L 1 skip if L A HL then L L 1 skip if L 0H HL A HL 1 E i lt encores EA EA EN ME A3 C A n 1 1 2 3 r2 rt 1 SP 1 2 lt SP lt 5 2 1 1 SP 1 lt SMB 5 2 5 SP lt 5 2 UJ D Q 0 27 ELECTRONICS 5 1 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Table 5 17 Data Transfer Instructions Binary Code Summary Concluded Name Operand Binary Code Operation Notation RRL lt SP lt SP 1 SRB lt SP SMB lt SP 1 SP lt SP 2 rs f o T ASA AND m o EA EA AND RR 0 nfo RRb lt RRb AND EA 1 OR im di do ESES EN EN 1 lt OR HL ES EA lt OR RR SS Eee TENER 1 4 lt XOR HL EA lt XOR RR 0 lt EA s a 5 18 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Table 5 19 Arithmetic Instructions Binary Code Summary Operand Binary Code Operation Notation ADC A HL C A lt A HL C 1 o 1 0 o RRb lt RRb gt A im sk
95. CK 3 HL 47 lt 00 BISF KEYFG 1 byte instruction KEYFG 1 jump to MAIN 1 byte instruction KEYFG 0 CALL CLOCK 1 byte instruction LD HL A INCS HL LD EA 00H 1 byte instruction ELECTRONICS 53C72N2 C72N4 P72NA ADDRESS SPACES DATA MEMORY RAM OVERVIEW In its standard configuration the 288 x 4 bit data memory has three areas 32 x 4 bit working register area in bank 0 224 x 4 bit general purpose area in bank 0 which is also used as the stack area 32 x 4 bit area for LCD data in bank 1 128 x 4 bit area in bank 15 for memory mapped I O addresses To make it easier to reference the data memory area has three memory banks bank 0 bank 1 and bank 15 The select memory bank instruction SMB is used to select the bank you want to select as working data memory Data stored in RAM locations are 1 4 and 8 bit addressable One exception is the LCD data register area which is 1 bit and 4 bit addressable only Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset However when RESET signal is generated in power down mode the data memory contents are held ELECTRONICS 2 5 ADDRESS SPACES 53 72 2 72 4 72 4 WORKING REGISTERS 32 x 4 Bits GENERAL PURPOSE REGISTERS AND STACK AREA 224 x 4 Bits LCD DATA REGISTERS 32 x4 Bits MEMORY MAPPED I O AEERESS REGIST
96. CTRONICS 12 1 LCD CONTROLLER DRIVER 53C72N2 C72N4 P72NA LCD CIRCUIT DIAGRAM H 1 8 7 ren SEG30 P8 6 SEG29 P8 5 _ Em SEG28 P8 4 SEG27 P8 3 SEG26 P8 2 SEG25 P8 1 SEG24PE0 E SEG23 1F4H 0 SEG22 SEG 1 SEG20 SEG19 1 0 SEGO ES 4 TIMING E 8 LMOD CONTROLLER CON COMO gt LCDSY d gt O LCDCK 1 0 0 4 Port 3 latch PMG1 Figure 12 2 LCD Circuit Diagram LCD O VLCO VOLTAGE O VLC1 LCON A CONTROL O 12 2 ELECTRONICS 53C72N2 C72N4 P72NA LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA addresses of bank 1 are used as LCD data memory These locations can be addressed by 1 bit 4 bit instructions When the bit value of a display segment is 1 the LCD display is turned on when the bit value is O the display is turned off Display RAM data are sent out through segment pins SEGO SEG31 using a direct memory access DMA method that is synchronized with the fj signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use COMS COM2 COMI COMO Figure 12 3 LCD Display Data RAM Organization Table 12 1 Common Signal Pins Used per Duty Cycle sac wo Sees Selected no NOTE connection is required ELECTRONICS 12 3 LCD CONTROLLER DRIVER 53C72N2 C72N4 P72NA LCD CONTROL REGISTER LC
97. CTRONICS 4 5 MEMORY S3C72N2 C72N4 P72N4 Basic Timer Mode Register F85H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 4 4 4 4 3 Basic Timer Restart Bit Restart basic timer then clear IRQB flag and BMOD 3 to logic zero 2 0 Input Clock Frequency and Signal Stabilization Interval Control Bits Input clock frequency fxx 21 1 02 kHz Signal stabilization interval 220 fxx 250 ms Input clock frequency fxx 29 8 18 kHz Signal stabilization interval 217 31 3 ms 1 1 Input clock frequency fxx 27 32 7 kHz Signal stabilization interval 215 fxx 7 82 ms 1 1 1 clock frequency fxx 29 131 kHz Signal stabilization interval 213 fxx 1 95 ms NOTES 1 Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt The stabilization interval can also be interpreted as Interrupt Interval Time 2 When a RESET occurs the oscillation stabilization time is 31 3 ms 217 fxx at 4 19 MHz 3 fxx is the system clock rate given a clock frequency of 4 19 MHz 4 6 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP CLMOD ciock Output Mode Register FDOH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 4 4 3 Enable Disable Clock Output Control Bit Disable clock output 1 Enable clock output 2 Bit 2 Always logic zero 1 0 C
98. D HL 20H RMCLO LD HL A INCS HL JR RMCLO 2 8 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES WORKING REGISTERS Working registers mapped to RAM address 000H 01FH in data memory bank 0 are used to temporarily store intermediate results during program execution as well as pointer values used for indirect addressing Unused registers may be used as general purpose memory Working register data can be manipulated as 1 bit units 4 bit units or using paired registers as 8 bit units 000H 001H 002H 003H WORKING 004H REGISTER BANK 0 005H DATA 6 MEMORY BANKO 007 008H REGISTER 00FH id BANK 1 REGISTER BANK 2 REGISTER 017H 018H 01FH Figure 2 4 Working Register Map ELECTRONICS 2 9 ADDRESS SPACES 53 72 2 72 4 72 4 Working Register Banks For addressing purposes the working register area is divided into four register banks bank 0 bank 1 bank 2 and bank 3 Any one of these banks can be selected as the working register bank by the register bank selection instruction SRB n and by setting the status of the register bank enable flag ERB Generally working register bank 0 is used for the main program and banks 1 2 and 3 for interrupt service routines Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing Table 2 3 Working Register Organization and Addressing ERB S
99. Diag aNG uuu umen aa Der E T T 1 7 Chapter 2 Address Spaces Program Memory ROMI uus dede hau denk Gs ade Eu aA 2 1 I 2 1 General Purpose Mernory 5 onu LR adu xd dona atuqtaq n EVI eu RE eb 2 2 VerlorrAddi6e 5 IL LOU TUTUP 2 2 INSWUCTION Reference ATO aski x buda Ro MR RN 2 4 Data Memory une iced Mata Hcr f de fea ea ut buta par V LA 2 5 UEC eee os 2 5 VVOFKING atelier 2 9 Ri dns 2 13 aaa au sa aa ayakuna uywata 2 13 FCT ua tu gaa 2 14 Pop Operations 2 15 Carrier BSC u Su yutu Q a kasus da rb tiae dite o e eda ta i diera 2 16 POr R T 2 17 Frogramestatus VV OI POW 2 17 Interrupt Status Flags 150 151 X 2 18 uoi iode haat aM Lind dod 2 19 gt
100. ERS 128 x 4 Bits Figure 2 3 Data Memory RAM Map 2 6 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES Memory Banks 0 1 and 15 Bank 0 The lowest 32 nibbles of bank 0 000H 01 FH are used as working registers the next 224 nibbles 020H OFFH can be used both as stack area and as general purpose data memory Use the stack area for implementing subroutine calls and returns and for interrupt processing Bank 1 1 EQH 1 FFH 32 nibbles of bank 1 are used as display registers or general purpose memory Bank 15 The microcontroller uses bank 15 for memory mapped peripheral I O Fixed locations for each peripheral hardware address are mapped into this area Data Memory Addressing Modes The enable memory bank EMB flag controls the addressing mode for data memory banks 0 1 or 15 When the EMB flag is logic zero the addressable area 15 restricted to specific locations depending on whether direct or indirect addressing is used With direct addressing you can access locations 000H 07FH of bank 0 and bank 15 With indirect addressing only bank 0 000H OFFH can be accessed When the flag is set to logic all three data memory banks can be accessed according to the current SMB value For 8 bit addressing two 4 bit registers are addressed as a register pair Also when using 8 bit instructions to address RAM locations remember to use the even numbered register address
101. ESSING STATUS 0 STATUS 1 HIGH LEVEL INTERRUPT PROCESSING INT DISABLE 3 STATUS 2 SET IPR INT ENABLE LOW OR HIGH LEVEL ___ HIGH LEVEL INTERRUPT INTERRUPT GENERATED GENERATED Figure 7 3 Two Level Interrupt Handling ELECTRONICS 7 5 INTERRUPTS 53C72N2 C72N4 P72NA Multi Level Interrupt Handling With multi level interrupt handling a lower priority interrupt request can be executed by manipulating the interrupt status flags 150 and 151 while a high priority interrupt is being serviced see Table 7 2 When an interrupt is requested during normal program execution interrupt status flags 150 and 151 are set to 1 and 0 respectively This setting allows only highest priority interrupts to be serviced When a high priority request is accepted both interrupt status flags are then cleared to 0 by software so that a request of any priority level can be serviced In this way the high and low priority requests can be serviced in parallel see Figure 7 4 Table 7 2 151 and 150 Bit Manipulation for Multi Level Interrupt Handling Process Status Before INT Effect of ISx Bit Setting After INT ACK ppt _150_ ist iso 0 Allinterupt requests are serviced o current settings in the IPR register are serviced 0 No additional interrupt requests wil ve serviced 1 Valueundefined NORMAL PROGRAM PROC
102. ESSING SINGLE STATUS 0 INTERRUPT 2 LEVEL INT DISABLE INTERRUPT 3 LEVEL SET IPR gt INT DISABLE STATUS 1 INTERRUPT INT ENABLE a MODIFY STATUS gt LOW OR INT ENABLE STAT S 0 HIGH LEVEL y INTERRUPT LOW OR HIGH aik HIGH LEVEL GENERATED LEVEL INTERRUPT STATUS 1 STATUS 2 INTERRUPT GENERATED GENERATED STATUS 0 Figure 7 4 Multi Level Interrupt Handling ELECTRONICS 7 6 53C72N2 C72N4 P72NA INTERRUPTS INTERRUPT PRIORITY REGISTER IPR The 4 bit interrupt priority register IPR is used to control multi level interrupt handling Its reset value is logic zero Before the IPR can be modified by 4 bit write instructions all interrupts must first be disabled by a DI instruction By manipulating the IPR settings you can choose to process all interrupt requests with the same priority level or you can select one type of interrupt for high priority processing A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source Table 7 3 Standard Interrupt Priorities interrupt Default Priority The MSB of the IPR the interrupt master enable flag IME enables and disables all interrupt processing Even if an interrupt request flag and its corresponding enable flag are set a service routine cannot be executed until the IME
103. FHandL L 1 HL lt 0 JPS XXX Skipped since a borrow occurred JPS YYY H lt 2H 0 YYY XCHD A HL 2 0FH lt 2 L lt L 1 OEH The JPS YYY instruction is executed since a skip occurs after the XCHD instruction ELECTRONICS 5 91 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Exchange and Increment XCHI dst src A HL Exchange A and data memory contents increment 1 2 5 contents of register L and skip on overflow Description The instruction exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L If the content of register L is OH a skip is executed The value of the carry flag is not affected Binary Code Operation Notation A HL 1 4 44 1 1 o HL then lt 1 1 skip if L OH Example Register pair HL contains the address 2FH and internal RAM location 2FH contains OFH LD HL 2FH LD A lt OFHandL lt L 1 0 HL lt 0 JPS XXX Skipped since an overflow occurred JPS YYY He 2H L lt YYY 20H lt OFH lt 20H lt L 1 1H JPS YYY instruction is executed since a skip occurs after the instruction 5 92 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET XOR Logical Exclusive OR XOR Operation Description Example dst src Opeand
104. FO registers match ELECTRONICS 4 1 MEMORY S3C72N2 C72N4 P72N4 IEW IRQW iNTW interrupt Enable Request Flags FBAH Bit 3 2 1 0 Identifier n Ew RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic zero IEW INTW Interrupt Enable Flag Disable INTW interrupt requests Enable INTW interrupt requests IROW INTW Interrupt Request Flag Generate INTW interrupt This bit is set when the timer interval is set to 0 5 seconds or 3 91 milliseconds NOTE Since INTW is a quasi interrupt the IRQW flag must be cleared by software 4 12 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP IMODO External Interrupt 0 INTO Mode Register Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 4 4 Interrupt Sampling Clock Selection Bit oelect CPU clock as a sampling clock 1 Select sampling clock frequency of the selected system clock fxx 64 2 Bit 2 Always logic zero 1 0 External Interrupt Mode Control Bits ojo Interrupt requests are triggered by a rising signal edge Po 1 Interrupt requests are triggered by a falling signal edge 1 EB Interrupt requests are triggered by both rising and falling signal edges Interrupt request flag IRQO cannot be set to logic one ELECTRONICS 4 13 MEMORY S3C72N2 C72N4 P72N4 IMOD 1 External Interrupt 1 INT1 Mode Register FB5H Bit 3
105. H 0AH BIST H FLAG If bank 0 0H O OAOH O 1 then skip RET ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BISTZ Bit Test and Skip on True Clear Bit BTSTZ dst b Test specified bit skip and clear if memory bit is set Description specified bit within the destination operand is tested If it is a 1 the instruction immediately following the BTSTZ instruction is skipped otherwise the instruction following the BTSTZ is executed The destination bit value is cleared Binary Code Operation Notation 1 and clear Skip if memb 7 2 L 3 2 L 1 0 1 and clear Bit Addresses FBOH FBFH FFOH FFFH Examples 1 Port pin P2 0 is toggled by checking the P2 0 value level BTSTZ P2 0 If P2 0 1 then P2 0 lt 0 and skip EIS P2 0 I P2 0 0 then P2 0 lt 1 JP LABEL3 2 Assume that port pins P2 2 P2 3 and P3 0 P3 3 are toggled LD 2 BTSTZ P1 QL First 1 P2 2 1111008 10B 10B OF2H 2 RET INCS 2 ELECTRONICS 5 41 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 BISTZ Bit Test and Skip on True Clear Bit BTSTZ Continued Examples 3 Bank 0 location is tested and EMB 0 FLAG EQU 0 LD H 0AH BTSTZ H FLAG Ifbank0 AH 0H 0 1 clear and skip BITS H FLAG IfOAOH 0 0 then lt 1 5 42 ELECTRONICS S3C72N2 C72N4
106. H FFFH 1 bit indirect addressing using the BSC I O BIST FC3H L L register BAND C P3 L 3 4 ELECTRONICS 53C72N2 C72N4 P72NA ADDRESSING MODES SELECT BANK REGISTER SB The select bank register SB is used to assign the memory bank and register bank The 8 bit SB register consists of the 4 bit select register bank register SRB and the 4 bit select memory bank register SMB as shown in Figure 3 2 During interrupts and subroutine calls SB register contents can be saved to stack in 8 bit units by the PUSH SB instruction You later restore the value to the SB using the POP SB instruction x SMB F83H sRB Figure 3 2 SMB and SRB Values in the SB Register Select Register Bank SRB Instruction The select register bank SRB value specifies which register bank is to be used as a working register bank The SHB value is set by the SRB n instruction where n 0 1 2 and 3 One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the SRB n instruction The current SRB value is retained until another register is requested by program software PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls RESET clears the 4 bit SRB value to logic zero Select Memory Bank SMB Instruction To select one of the four available data memory banks you must ex
107. INT2 P1 3 TCLO 8 Bit Timer P2 0 TCLOO CounterO P6 0 P6 3 KS0 KS3 Port 6 8 0 8 7 SEG24 SEG31 Output Port 8 PRODUCT OVERVIEW Watchdog Basic Watch Xin RESET XTin XTout Interrupt Control Block Interrupt Control Block Instruction Register LCD Driver Controller Program Internal Counter Interrupts Program Status Word Input Port 1 Instruction Decoder Arithmetic and Logic Unit Stack Pointer I O Port 2 2 4 KByte Program Memory 288 x 4 Bit Data Memory Port 3 Figure 1 1 53 72 2 72 4 Simplified Block Diagram ELECTRONK S BIAS VLCO VLC2 LCDCK P3 0 LCDSY P3 1 SEGO SEG23 P8 0 P8 7 SEG24 SEG31 P1 0 INTO 4 P1 1 INT1 P1 2 INT2 P1 3 TCLO P2 0 TCLOO P2 1 P2 3 BUZ P3 0 L CDCK P3 1 LCDSY E P3 2 PRODUCT OVERVIEW PIN ASSIGNMENTS COMO COMI CON BIAS VLCO VLC1 VDD 54 SEG10 53 1 11 52 12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 S3C72N2 C72N4 P72N4 Vss Xout Xin S3C72N4 E SEG23 Top View SEG24 P8 0 TEST SEG25 P8 1 XTin SEG26 P8 2 XTout SEG27 P8 3 RESET Co SEG28 P8 4 P1 0INTO SEG29 P8 5 Co SEG30 P8 6 P1 2 NT2 SEG31 P8 7 VLC2 P1 3 TCLO C4 20 P2 0 TCLOO 21 P2 2 CLO C4 23 P2 3 BUZ 24 P3 0 LCDCK 25 P3 1 LCDSY
108. LO pin may be summarized as follows 1 Disable clock output by clearing CLMOD 3 to logic zero 2 Set the clock output frequency CLMOD 1 CLMOD 0 3 Load O to the output latch of the CLO pin P2 2 4 Setthe P2 2 mode flag PM2 to output mode 5 Enable clock output by setting CLMOD 3 to logic one ELECTRONICS 6 13 OSCILLATOR CIRCUITS 5 PROGRAMMING TIP CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin BITS SMB LD LD BITR LD LD EMB 15 EA 04H PMG2 EA P2 2 A 9H CLMOD A J 5 P2 lt Output mode Clear P2 2 pin output latch S3C72N2 C72N4 P72N4 ELECTRONICS 53C72N2 C72N4 P72NA INTERRUPTS INTERRUPTS OVERVIEW The S3C72N2 C72NA interrupt control circuit has five functional components Interrupt enable flags Interrupt request flags IRQx Interrupt master enable register IME Interrupt priority register IPR Power down release signal circuit Three kinds of interrupts are supported Internal interrupts generated by on chip processes External interrupts generated by external peripheral devices Quasi interrupts used for edge detection and as clock sources Table 7 1 Interrupt Types and Corresponding Port Pin s Interrupt Type Interrupt Name Corresponding Port Pins External interrupts INTO INT1 P1 0 P1 1 Internal interrupts INTB INTTO Not applicable Quasi interrupts 2 KSO KS3 P1 2 P6 0 P6 3
109. NA LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is used to control display mode LCD clock segment or port output and display on off LMOD can be manipulated using 8 bit write instructions bit 3 LMOD 3 can be also written by 1 bit instructions F8CH LMOD 3 LMOD 2 LMOD 1 LMOD 0 F8DH LMOD 7 LMOD 6 LMOD 5 LMOD 4 The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on RESET clears the LMOD register values to logic zero The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD mode register LMOD controls the output mode of the 8 pins used for normal outputs P8 0 P8 7 Bits LMOD 7 6 define the segment output and normal bit output configuration Table 12 4 LCD Mode Register LMOD Organization o Segments 24 27 and 28 31 0 1 Segments 24 27 1 bit output at P8 4 P87 1 Segments 28 31 1 bit output at P8 0 P8 3 I I I 4 4 4 4 4 4 4 4 o jw O o dec tes SS C 9 o o o 1 o NOTE fw 2
110. OEABH will load the program counter with the value OOFFH ELECTRONICS 5 57 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 J H Jump Relative Very Short JR Operation Description 5 58 dst fe Branch to relative immediate address Branch relative to contents of WX register 2 83 Branch relative to contents of EA 2 83 causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC The range of the relative address is current PC 15 to current PC 16 The destination address for this jump is specified to the assembler by a label an actual address by immediate data using a plus sign or a minus sign For immediate addressing the range is from 2 to 16 and the range is from 1 to 15 If a O 1 or any other number that is outside these ranges are used the assembler interprets it as an error For JR WX and JR branch relative instructions the valid range for the relative address is OFFH The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256 byte block Normally the WxX JR EA instructions jump to the address in the page in which the instruction is located However if the first byte of the instruction code is located at address OXFEH or OxFFH the instruction will jump to the next page
111. ON The LCD control register LCON is used to turn the LCD display on and off to output LCD clock LCDCK and synchronizing signal LCDSY for LCD display expansion and to control the flow of current to dividing resistors in the LCD circuit Following a RESET all LCON values are cleared to 0 This turns the LCD display off and stops the flow of current to the dividing resistors The effect of the LCON O setting is dependent upon the current setting of bits LMOD 3 Table 12 2 LCD Control Register LCON Organization This bit is used for internal testing only always logic zero Disable LCDCK and LCDSY signal outputs Enable LCDCK and LCDSY signal outputs Always logic zero LCD output low display off cut off current to dividing resistor and output port 8 latch contents If LMOD 3 0 LCD display off output port 8 latch contents If LMOD 3 1 COM and SEG output in display mode LCD display on NOTE 3 register must be set to 0 Table 12 3 LCON 0 and LMOD 3 Bit Settings LCON 0 LMOD 3 SEGO SEG31 80 87 Output low LCD display off Output low Output latch Cut off current to LCD display off contents dividing resistors 1 LCD display off LCD display off Output latch LCD display off contents COM output corresponds to display SEG output Output latch LCD display on mode corresponds to contents display mode 12 4 ELECTRONICS 53C72N2 C72N4 P72
112. Operation Summary Cycles Exclusive OR immediate data to A A HL Exclusive OR indirect data memory to A ARR ExclusveOR register J e Exclusive OR register pair RRb to EA XOR performs a bit wise logical XOR operation between the source and destination variables and stores the result in the destination The source contents are unaffected Binary Code Operation Notation A Pt f 4 0 X08 m Cv es ae lt XOR RR hihi If the extended accumulator contains 1100001 1B and register HL contains 55H 01010101B the instruction EA HL leaves the value 96H 10010110B in the extended accumulator ELECTRONICS 5 93 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 5 5 94 ELECTRONICS S3C72N2 C72N4 P72N4 OSCILLATOR CIRCUITS OSCILLATOR CIRCUITS OVERVIEW S8C72N2 C72N4 microcontroller has two oscillator circuits a main system clock circuit a subsystem clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits Specifically a clock pulse is required by the following peripheral modules LCD controller Basic timer Timer counter 0 Watch timer Clock output circuit CPU Clock Notation In this document the following notation is used for descriptions of the CPU clo
113. P72N4 SAM47 INSTRUCTION SET BXOR Bit Exclusive BXOR C src b Exclusive OR carry with memory bit C memb L C H DA b Description specified bit of the source is logically XORed with the carry bit value The resultant bit is written to the carry flag The source value is unaffected l C memb L C XOR H DA3 0 b a C H DA b Examples 1 The carry flag is logically XORed with the P1 0 value RCF 0 BXOR C P1 0 If P1 0 1 then C lt 1 if P1 0 0 then C 0 2 The P1 address is FF1H and register L contains the value 9H 1001B The address memb 7 2 is 111100B and L 3 2 10B The resulting address is 11110010B or FF2H specifying P2 The bit value for the BXOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P2 1 LD C P1 L P1 L is specified as P2 1 C XOR P2 1 ELECTRONICS 5 43 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Bit Exclusive OR BXOR Examples 5 44 Continued 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BXOR C H FLAG C FLAG 20H 3 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET CALL Call Procedure CALL dst Operation
114. Program execution continues with the instruction immediately following the NOP Only the PC is affected At least three NOP instructions should follow a STOP or IDLE instruction Example Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power down mode is initiated STOP NOP NOP NOP 5 70 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Logical OR OR Operation Description Example dst src operand Operation Summary Byes 2 2 _ AG indirect data memory contensioA 1 1 EARR LogicarOR soubie regseroea J 2 mts Logica OR _ The source operand is logically ORed with the destination operand The result is stored in the destination The contents of the source are unaffected EB ES EB EA on PR ES 1 1 0 RRb lt RRb EA o o RRb EA If the accumulator contains the value 11000011B and register pair HL the value 55H 01010101B the instruction OR EA HL leaves the value OD7H 11010111B in the accumulator ELECTRONICS 5 71 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 POP Pop From Stack POP dst Operation Operation Summary IRR o Pop to register pair from
115. Register 4 13 IMOD1 External Interrupt 1 INT1 Mode 0 1 4 14 IMOD2 External Interrupt 2 INT2 Mode Register 4 15 IPR RANONI EE OS ES 4 16 LCON ECD Output Control 4 17 LMOD ECD MOGde I368IS COR EA 4 18 PCON GOO TRegliSle 4 19 1 Port I O Mode Flags Group 1 Ports and 6 4 20 PMG2 Port lO Mode Flags Group 2 Port 2 uy mu Seaton eee en alana 4 21 PSW Program Status Wor E 4 22 PUMOD Pull up Resistor Mode 4 23 SCMOD System Clock Mode Control 2 4 24 TMODO Timer Counter Mode 0 Register 4 25 TOE Timer Output Enable Flag 4 26 WDFLAG Watchdog Timer Counter Clear Flag Register 4 27 WDMOD Watchdog Timer Mode 4 28 WMOD Watch Timer Mode 4 29 S3C72N2 C72N4 P72N4 xxi Instruction Mnemonic ADC S3C72N2 C72N4 P72N4 List of Instruction Descripti
116. STEM OSCILLATOR CIRCUITS 32 768 kHz Figure 6 2 Crystal Ceramic Oscillator Figure 6 5 Crystal Ceramic Oscillator Xin EXTERNAL CLOCK Xout Figure 6 3 External Oscillator Figure 6 6 External Oscillator Xin H Xout Figure 6 4 RC Oscillator 6 4 ELECTRONICS S3C72N2 C72N4 P72N4 OSCILLATOR CIRCUITS POWER CONTROL REGISTER PCON The power control register PCON is a 4 bit register that is used to select the CPU clock frequency and to control CPU operating and power down modes The PCON can be addressed directly by 4 bit write instructions or indirectly by the instructions IDLE and STOP PCON 3 and PCON 2 can be addressed only by the STOP and IDLE instructions respectively to engage the idle and stop power down modes Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank EMB PCON bits 1 and 0 can be written only 4 bit RAM control instruction PCON is a write only register There are three basic choices Main system clock fx or subsystem clock fxt Divided fx clock frequency of 4 8 or 64 Divided fxt clock frequency of 4 PCON 1 and 0 settings are also connected with the system clock mode control register SCMOD If SCMOD 0 0 the main system clock is always selected by the PCON 1 and 0 setting if SCMOD O 1 the subsystem clock is selected RESET sets PCON register values and SCMOD to logic zero Ta
117. STOP BMOD SETTING INSTRUCTION MODE INT ACK 1 RELEASE SIGNAL NORMAL MODE STOP MODE IDLE MODE NORMAL MODE OSCILLATION CLOCK STOPS OSCILLATION RESUMES SIGNAL gt Figure 8 4 Timing When Main Stop Main Sub Stop Mode is Release by Interrupt ELECTRONICS 53C72N2 C72N4 P72NA POWER DOWN PROGRAMMING Reducing Power Consumption for Key Input Interrupt Processing The following code shows real time clock and interrupt processing for key inputs to reduce power consumption In this example the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on KEYCLK CLKS1 CIDLE DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS CALL BISTZ JR CALL EI HET IDLE NOP NOP NOP JPS MA2SUB 15 00 A 3H IMOD2 A 0 IRQW IRQ2 IEW IE2 WATDIS IRQ2 CIDLE SUB2MA CLKS1 Main system clock subsystem clock switch subroutine All key strobe outputs to low level Select 50 53 enable Execute clock and display changing subroutine Subsystem clock main system clock switch subroutine Engage idle mode NOTE You must execute three NOP instructions after IDLE and STOP instructions to avoid flowing of leakage current due to the floating state in the internal bus ELECTRONICS 8 5 POWER DOWN 53C72N2 C72N4 P72NA PORT PIN CONFIGURATION FOR POWER DOWN The f
118. Since the INTO pin has a clock driven noise filtering circuit built into it please take the following precautions when you use it trigger an interrupt the input signal width at INTO must be at least two times wider than the pulse width of the clock selected by IMODO Since the INTO input sampling clock is not operated during STOP or IDLE mode you cannot use INTO to release the power down mode NOISE FILTER EDGE DETECTION CLOCK SELECTOR CPU Clock 64 EDGE DETECTION Figure 7 5 Circuit Diagram for INTO and INT1 Pins When modifying the IMOD registers it is possible to accidentally set an interrupt request flag To avoid unwanted interrupts take these precautions when writing your programs Disable all interrupts with a DI instruction Modify the IMOD register Clear all relevant interrupt request flags Enable the interrupt by setting the appropriate IEx flag amp gt Enable interrupts with an El instructions ELECTRONICS 7 9 INTERRUPTS 53C72N2 C72N4 P72NA EXTERNAL INTERRUPT 2 MODE REGISTER IMOD2 The mode register for external interrupt 2 at the 50 53 pins IMOD2 is addressable only by 4 bit write instructions RESET clears all IMOD2 bits to logic zero FB6H ow wo IMOD2 1 IMOD2 0 If a rising or falling edge is detected at any one of the selected KS by the IMOD2 register the IRQ2 flag is set to logic one and a release signal for power d
119. T5 0 0 INTTO lt 0 ERB lt 0 Jump to INTTO address 2 When a specific vectored interrupt such as INTO and INTTO 1 not used the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations ORG 0000H VENTO 1 0 RESET lt 1 ERB lt 0 Jump to RESET address VENT1 0 0 INTB lt 0 ERB lt 0 Jump to address 0006H INTO interrupt not used VENT3 0 0 INT1 lt 0 ERB lt 0 Jump to INT1 address ORG 0010H 3 If an INTO interrupt is not used and if its corresponding vector interrupt area is not fully utilized or if it is not written by a ORG instruction as in Example 2 a CPU malfunction will occur ORG 0000H VENTO 1 0 RESET lt 1 ERB lt 0 Jump to RESET address VENT 1 0 0 INTB EMB lt 0 ERB lt 0 Jump to INTB address VENT3 0 0 INT1 0 ERB lt 0 Jump to INTO address VENT5 0 0 INTTO lt 0 ERB lt 0 Jump to address ORG 0010H General purpose ROM area In this example when an INT1 interrupt is generated the corresponding vector area is not VENTS but VENTS INTTO This causes an INT1 interrupt to jump incorrectly to the INTTO address and causes a CPU malfunction to occur ELECTRONICS 2 3 ADDRESS SPACES INSTRUCTION REFERENCE AREA S3C72N2 C72NA4 P72N4 Using 1 byte REF instructions you can easily reference instructions with larger
120. TCO reference register TREFO you can divide the incoming clock signal by the TREFO value and then output this modified clock frequency to the TCLOO pin The sequence of operations used to divide external clock input can be summarized as follows 1 Load a signal divider value to the TREFO register Clear TMODO 6 to 0 to enable external clock input at the TCLO pin oet TMODO 5 and TMODO 4 to desired TCLO signal edge detection oet port 2 0 mode flag PM2 to output 1 oet P2 0 output latch to O Set TOEO flag to 1 to enable output of the divided frequency to the TCLOO pin D OF PROGRAMMING External TCLO Clock Output to the TCLOO Pin Output external TCLO clock pulse to the TCLOO pin divided by four EXTERNAL TCLO CLOCK PULSE TCLOO OUTPUT PULSE BITS EMB SMB 15 LD EA 01H LD TREFO EA LD EA 0CH LD TMODO EA LD EA 04H LD PMG2 EA P2 0 lt output mode BITR P2 0 P2 0 clear BITS TOEO 11 16 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS MODE REGISTER TMODO TMODO is the 8 bit mode control register for timer counter O It is addressable by 8 bit write instructions One bit TMOD0 3 is also 1 bit writeable RESET clears all TMODO bits to logic zero and disables TCO operations F90H 0 3 TMODO0 2 F91H e 6 5 TMODO 4 TMODO0 2 is the enable disable bit for timer counter 0 When 0 3 is s
121. TERRUPTS MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways as two level interrupts where either all interrupt requests or only those of highest priority are serviced or as multi level interrupts when the interrupt service routine for a lower priority request is accepted during the execution of a higher priority routine Two Level Interrupt Handling Two level interrupt handling is the standard method for processing multiple interrupts When the 151 and 150 bits of the PSW and 2 respectively are both logic zero program execution mode is normal and all interrupt requests are serviced see Figure 7 3 Whenever an interrupt request is accepted 151 and ISO are incremented by and the values are stored in the stack along with the other PSW bits After the interrupt routine has been serviced the modified 151 and 150 values are automatically restored from the stack by an IRET instruction 150 and 151 can be manipulated directly by 1 bit write instructions regardless of the current value of the enable memory bank flag EMB Before you modify an interrupt service flag however you must first disable interrupt processing with a DI instruction When 151 0 and 150 1 all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register IPR NORMAL PROGRAM HIGH OR LOW LEVEL PROCESSING INTERRUPT PROC
122. TP programmer Gang are now available ELECTRONES 16 1 DEVELOPMENT TOOLS 16 2 IBM PC AT or Compatible HS 232C a j lt a lt q B PROM MTP WRITER UNIT RAM BREAK DISPLAY UNIT TRACE TIMER UNIT SAM4 BASE UNIT POWER SUPPLY UNIT 53C72N2 C72N4 P72NA SMDS2 TARGET APPLICATION SYSTEM PROBE ADAPTER TB72N2 4 TARGET BOARD Figure 16 1 SMDS Product Configuration SMDS2 ELECTRONICS S3C72N2 C72N4 P72N4 DEVELOPMENT TOOLS TB72N2 4 TARGET BOARD The TB72N2 4 target board is used for the S8C72N2 C72N4 P72N4 microcontroller It is supported by the SMDS2 development system TB 2N2 4 To User Vcc OFF ON BIAS Vict VLC2 IDLE STOP 21096 101 102 144 KS57E2304 EVA CHIP CONNECTOR LE O O LLI LLI Z Z Z Z O O O O z z n n EXTERNAL TRIGGERS 40 39 5 1256 Figure 16 2 72 2 4 Target Board Configuration ELECTRONICS 16 3 DEVELOPMENT TOOLS 53 72 2 72 4 72 4 Table 16 1 Power Selection Settings for TB72N2 4 User Vcc Settings Operating Mode The SMDS2 SMDS2 supplies To User Vcc Vcc to the target board P OFF 3 oN TB72N2 4 TARGET evaluation chip and the target system SYSTEM The SMDS2 SMDS2 supplies Vcc only to the target board e Ho TB72N2 4 eed dad CU OFF ON External TARGET evaluation chip The
123. TRONICS 5 49 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 DECS Decrement and Skip on Borrow DECS dst R Decrement register R skip on borrow RRO Decrement register pair RR skip on borrow Description destination is decremented by one An original value of will underflow to OFFH If a borrow occurs a skip is executed The carry flag value is unaffected Binary Code Operation Notation ri ro R lt R 1 skip borrow R 0 1 skip on borrow Examples 1 Register pair HL contains the value 7FH 01111111B The following instruction leaves the value 7EH in register pair HL DECS HL 2 Register A contains the value The following instruction sequence leaves the value OFFH in register A Since a borrow occurs the CALL PLAY1 instruction is skipped and the CALL 2 instruction is executed DECS A Borrow occurs CALL PLAY 1 Skipped CALL PLAY2 Executed 5 50 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET DI Disable Interrupts DI Description Bit 3 of the interrupt priority register IPR IME is cleared to logic zero disabling all interrupts Interrupts can still set their respective interrupt status latches but the CPU will not directly service them 1 1 If the IME bit bit 3 of the IPR is logic one e g all ins
124. TRUCTION SET 53 72 2 72 4 72 4 Logical And AND Operation Description Example 5 28 dst src The source operand is logically ANDed with the destination operand The result is stored in the destination The logical AND operation results in a 1 bit being stored whenever the corresponding bits in the two are both 1 otherwise O bit is stored The contents of the source are unaffected Operation Notation A HL 1 AND HL mE m 21419 If the extended accumulator contains the value 1100001 1B and register pair HL the value 55H 01010101B the instruction AND EA HL leaves the value 41H 01000001B in the extended accumulator EA ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BAND Bit Logical And BAND C src b C mema b Logical AND carry flag with memory bit EEEN C memb L C H DA b Description specified bit of the source is logically ANDed with the carry flag bit value If the Boolean value of the source bit is a logic zero the carry flag is cleared to 0 otherwise the current carry flag setting 5 left unaltered The bit value of the source operand is not affected Examples 1 The following instructions set the carry flag if P1 0 port 1 0 is equal to 1 and assuming the carry flag is already set to 1 SMB 15 1 C P1 0 If P1 0
125. This LED is ON when the evaluation chip KS57E2304 is in stop mode ELECTRONICS 16 5 DEVELOPMENT TOOLS 53 72 2 72 4 72 4 P8 7 SEG31 2 1 P8 6 SEG30 2 P8 5 SEG29 Q 4 P8 4 SEG28 5 P8 3 SEG27 6 P8 2 SEG26 Vict P8 1 SEG25 8 P8 0 SEG24 VDD 10 SEG22 12 SEG20 TEST 1431 SEG18 XTout 16 SEG16 P1 0 INTO P1 2 INT2 P2 0 TCLOO P2 2 CLO P3 0 LCDCK P3 2 P6 0 KSO P6 2 KS2 NC NC NC NC 18 1 SEG14 YOLOANNOD 07 YOLOANNOD 07 Figure 16 3 40 Connectors for TB72N2 4 TARGET BOARD TARGET SYSTEM J101 J102 J102 J101 1 2 1 2 1 2111 2 Target Cable for 40 Pin Connector Part Name AS40D A Order Code 5 6306 39 40139 40 39 40139 40 Figure 16 4 TB72N2 4 Adapter Cable for 64 QFP Package S3C72N2 C72N4 P72N4 OLONNOO 0 7 16 6 ELECTRONICS
126. able 5 20 Bit Manipulation Instructions Binary Code Concluded Operand Binary Code Operation Notation Notation momabo 1 1 t tj ojo 1 1 1 1 1 memb7 2 L32 IL1 0 ESESERESFIESEIES rir o fc lt mema b ERERESFIESEIES C H DAb 1 1 11 1 0 0 lt 3 0 46 Bit Addresses OO OoOO FBFH FFOH FFFH 5 22 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction of the SAM47 instruction set Information is arranged in a consistent format to improve readability and for use as a quick reference resource for application programmers If you are reading this user s manual for the first time please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set The information elements of the instruction description format are as follows Instruction name mnemonic Full instruction name Source destination format of the instruction operand Operation overview from the High Level Summary table Textual description of the instruction s effect Binary code overview from the Binary Code Summary table Programming example s to show how the ins
127. alue is not affected JPS XXX This instruction is skipped since ADS had an overflow JPS YYY Jump to YYY ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET ADS Add And Skip On Overflow ADS Examples Continued 2 If the extended accumulator contains the value register pair HL the value 12H and the carry flag 0 ADS EA HL EA lt 12H OD5H C lt 0 JPS XXX Jump to XXX no skip after ADS If ADC is followed by ADS the ADC skips on overflow to the instruction immediately after the ADS ADS A im instruction immediately after the ADC A HL does not skip even if overflow occurs This function is useful for decimal adjustment operations a 8 9 decimal addition the contents of the address specified by the HL register is C lt 0 LD A 8H A lt 8H ADS A 6H lt 8H ADC A HL 7 lt 1 ADS A 0AH Skip this instruction because 1 after ADC result JPS XXX b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF x ec spi LD A 3H ADS A 6H 3H 6H ADC A HL 9H 4H 0 ADS A 0AH No skip lt OAH 7H The skip function for ADS A im is inhibited after ADC A HL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 27 SAM47 INS
128. amically modify the basic frequency new values can be loaded into the TMODO register during program execution TCO FUNCTION SUMMARY 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency External event counter Counts various system events based on edge detection of external clock signals at the TCO input pin TCLO To start the event counting operation TMODO 2 is set to 1 and TMODO 6 is cleared to 0 Arbitrary frequency output Outputs selectable clock frequencies to the TCO output pin TCLOO External signal divider Divides the frequency of an incoming external clock signal according to a modifiable reference value TREFO and outputs the modified frequency to the TCLOO pin ELECTRONICS TIMERS and TIMER COUNTERS TCO COMPONENT SUMMARY Mode register TMODO Reference register TREFO Counter register TCNTO Clock selector circuit 8 bit comparator Output latch TOLO Output enable flag TOEO Interrupt request flag IRQTO Interrupt enable flag IETO 11 10 53C72N2 C72N4 P72NA Activates the timer counter and selects the internal clock frequency or the external clock source at the TCLO pin otores the reference value for the desired number of clock pulses between interrupt requests Counts internal or external clock pulses based on the bit settings in TMODO and TREFO Together with the mode register lets you select one of
129. ample real time clock processing method CLOCK BISTZ IRQW 0 5 second check RET return Yes 0 5 second interrupt generation Increment HOUR MINUTE SECOND 11 26 ELECTRONICS 53C72N2 C72N4 P72NA LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C72N2 C72N4 microcontroller can directly drive an up to 128 dot 32 segments x 4 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 32 segment output pins SEGO SEG31 4 common output pins COMO COMS3 LCD operating power supply pins co Vico The frame frequency duty and bias and the segment pins used for display output are determined by bit settings in the LCD mode register LMOD The LCD control register LCON is used to turn the LCD display on and off to switch current to the dividing resistors for the LCD display and to output LCD clock and synchronizing signal LCDSY for LCD display expansion Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during main clock stop and idle modes O VLCO VLC2 LCD O CONTROLLER DRIVER SEGO SEG23 gt gt UJ C 2 SEG24 SEG31 8 0 8 7 Figure 12 1 LCD Function Diagram ELE
130. an interrupt service routine a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values as shown in Example 2 below 2 When ERB 1 VENT2 INTO 1 1 INTO PUSH SRB SMB LD LD LD INCS LD LD POP IRET SB 2 0 00 80H EA 40 WX EA 2 SB lt 1 ERB lt 1 Jump to INTO address Store current SMB SRB Select register bank 2 because of ERB 1 Restore SMB SRB ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES STACK OPERATIONS STACK POINTER SP The stack pointer SP is an 8 bit register that stores the address used to access the stack an area of data memory set aside for temporary storage of data and addresses The SP can be read or written by 8 bit control instructions When addressing the SP bit 0 must always remain cleared to logic zero F80H SP3 SP2 F81H SP7 SP6 SP5 SP4 There are two basic stack operations writing to the top of the stack push and reading from the top of the stack pop A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack The program counter contents and program status word PSW are stored in the stack area prior to the execution of a CALL or a PUSH instruction or during interrupt service routines Stack operation is a LIFO Last In First Out type The stack area is located in general purpose da
131. and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET The 8 bit timer counter TCO is programmable timer counter that is used primarily for event counting and for clock frequency modification and output The watch timer WT module consists of an 8 bit watch timer mode register a clock selector and a frequency divider circuit Watch timer functions include real time and watch time measurement main and subsystem clock interval timing buzzer output generation It also generates a clock signal for the LCD controller ELECTRONICS TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 BASIC TIMER BT OVERVIEW The 8 bit basic timer BT has five functional components Clock selector logic 4 bit mode register BMOD 8 bit counter register BCNT 8 bit watchdog timer mode register WDMOD Watchdog timer counter clear flag WDTCF The basic timer generates interrupt requests at precise intervals based on the frequency of the system clock Basic timer s counter register outputs timer pulses to the watchdog timer s counter register WOTCNT when overflow occurs in BCNT You can use the basic timer as a watchdog timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET Bit settings in the basic timer mode register BMOD turns the BT on and off
132. ank 0 is selected Select memory bank 15 Program error but assembler does not detect it F90H lt A bank 15 is selected 2 19 ADDRESS SPACES ERB FLAG ERB S3C72N2 C72NA4 P72N4 The 1 bit register bank enable flag ERB determines the range of addressable working register area When the ERB flag is 1 the working register area from register banks 0 to 3 is selected according to the register bank selection register SRB When the ERB flag is 0 register bank 0 is the selected working register area regardless of the current value of the register bank selection register SRB When an internal reset is generated bit 6 of program memory address 0000H is written to the ERB flag This automatically initializes the flag When a vectored interrupt is generated bit 6 of the respective address table in program memory is written to the ERB flag setting the correct flag status before the interrupt service routine is executed During the interrupt routine the ERB value is automatically pushed to the stack area along with the other PSW bits Afterwards it is popped back to the FBOH O bit location The initial ERB flag settings for each vectored interrupt are defined using instructions 5 PROGRAMMING Using the ERB Flag to Select Register Banks ERB flag settings for register bank selection 1 When ERB 0 SHB LD LD SHB LD SHB LD 2 When ERB 1 SHB LD LD SHB LD SHB LD 2 20 1
133. ardless of the SRB value Operand Binary Code Operation Notation Operand pei ede e Example If the ERB flag is set the instruction SHB 3 selects register bank 018H 01FH as the working memory register bank ELECTRONICS 5 85 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Return From Subroutine and Skip SRET Operation Description Example 5 86 Return from subroutine and skip SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction SRET skips the resulting address which is generally the instruction immediately after the point at which the subroutine was called Then program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter Binary Code Operation Notation 1 1 1 1 1 PC11 8 lt SP 1 SP 7 0 lt SP 3 SP 2 EMB ERB lt SP 5 SP 4 SP 6 then skip If the stack pointer contains the value OFAH and RAM locations OFAH OFBH OFCH and OFDH contain the values 1H OH 5H and 2H respectively the instruction SRET leaves the stack pointer with the value OOH and the program returns to continue execution at location 0125H then skips unconditionally During a return from subroutine data is popped from the stack to the PC as follows
134. as the instruction operand Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks bank 0 1 2 and 3 Each register bank has eight 4 bit registers and paired 4 bit registers are 8 bit addressable Register is used as a 4 bit accumulator and register pair EA as an 8 bit extended accumulator The carry flag bit can also be used as a 1 bit accumulator Register pairs WX WL and HL are used as address pointers for indirect addressing To limit the possibility of data corruption due to incorrect register addressing it is advisable to use register bank 0 for the main program and banks 1 2 and 3 for interrupt service routines LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1 Register locations in this area that are not used to store LCD data can be assigned to general purpose use ELECTRONICS 2 7 ADDRESS SPACES 53 72 2 72 4 72 4 Table 2 2 Data Memory Organization and Addressing Register Areas Bank 0 EMB Value SMB Value 000H 01FH Working registers 0 1 020 otack and general purpose registers 1EOH 1FFH LCD Data registers PROGRAMMING TIP Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area BITS EMB RAMCLR SMB 1 RAM 1EOH 1FFH clear LD HL 0 LD A 0H RMCL1 LD HL A INCS HL JR RMCL1 SMB 0 RAM 020 clear L
135. ation Notation C Rune 1 The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one stopping the CPU clock The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 53 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 INCS Increment and Skip on Carry INCS dst Increment register R skip on carry LEN mb meemenregserparrmysiponay 1 1 8 Description The instruction INCS increments the value of the destination operand by one An original value of OFH will for example overflow to If a carry occurs the next instruction is skipped The carry flag value is unaffected lt DA 1 skip carry at a0 DA HL HL 1 skip carry RRb lt RRb 1 skip on carry Example Register pair HL contains the value 7EH 01111110B RAM location 7 contains The instruction sequence INCS HL lt 0 INCS HL Skip INCS HL lt 1 leaves the register pair HL with the value 7 and RAM location 7EH with the value 1H Since carry occurred the second instruction is skipped The carry flag value remains unchanged 5 54 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET IRET Return From Interrupt IRET Operation Description IRET is us
136. bit of the BMOD register BMOD 3 is used to restart the basic timer When BMOD 3 is set to logic one enabled by a 1 bit write instruction the contents of the BT counter register BCNT and the BT interrupt request flag IRQB are both cleared to logic zero and timer operation is restarted The combination of bit settings in the remaining three registers 2 BMOD 1 and BMOD 0 determines the clock input frequency and oscillation stabilization interval Table 11 2 Basic Timer Mode Register BMOD Organization Basic Timer Restart Bit Restart basic timer clear IRQB BCNT and BMOD 3 to 0 BMOD 2 BMOD 1 BMOD 0 Basic Timer Input Clock Interval Time 1 Clock frequencies and stabilization intervals assume a system oscillator clock frequency fxx of 4 19 MHz 2 fxx selected system clock frequency 3 Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released The data in the table column Oscillation Stabilization can also be interpreted as Interrupt Interval Time 4 standard stabilization time for system clock oscillation following aRESET is 31 3 ms at 4 19 MHz ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS BASIC TIMER COUNTER BCNT is an 8 bit counter for the basic timer It can be addressed by 8 bit read instructions RESET leaves the BCNT counter value undetermined BCNT is automat
137. ble 6 1 Power Control Register PCON Organization PCON Bit Settings Resulting CPU Clock Frequency PCON 1 0 SCMOD 0 0 SCMOD 0 1 fxt 4 PCON Bit Settings Resulting CPU Operating Mode PCON 3 PCON 2 O CPU operating mode _ 1 DLE STOP mode ELECTRONICS 6 5 OSCILLATOR CIRCUITS 5 PROGRAMMING TIP Setting the CPU Clock To set the CPU clock to 0 95 5 at 4 19 MHz BITS EMB SMB 15 LD A 3H LD INSTRUCTION CYCLE TIMES S3C72N2 C72N4 P72N4 The unit of time that equals one machine cycle varies depending on whether the main system clock fx or a subsystem clock fxt is used and on how the oscillator clock signal is divided by 4 8 or 64 Table 6 2 shows corresponding cycle times in microseconds Table 6 2 Instruction Cycle Times for CPU Clock Rates Oscillation Selected Resulting Cycle Time usec Source Clock E fx 2 4 19 MHz fxt 32 768 kHz fxt 4 8 19 kHz 122 0 6 6 ELECTRONICS 53C72N2 C72N4 P72NA OSCILLATOR CIRCUITS SYSTEM CLOCK MODE REGISTER SCMOD The system clock mode register SCMOD is a 4 bit register that is used to select the CPU clock and to control main and sub system clock oscillation SCMOD is mapped to the RAM address 7 When main system clock is used as clock source main system clock oscillation can be stopped by STOP instruction or setting SCMOD 3 not recommended When the clock source is
138. ble with the S8C72N2 C72N4 both in function and in pin configuration Because of its simple programming requirements the S3P72N4 is ideal for use as an evaluation chip for the S8C72N4 ELECTRONICS 15 1 S3P72N4 OTP 15 2 COMO COM1 2 BIAS VLCO SDAT VLC1 SCLK VLC2 VDD VDD Vss Vss Xout Xin VPP TEST XTin XTout RESETRESET P1 0 INTO P1 1 INT1 P1 2 INT2 Q N P1 3 TCLO 4 20 P2 0 TCLOO C4 21 P2 1 22 P2 2 CLO 23 53 72 4 Top View P2 3 BUZ 24 P3 0 LCDCK C4 25 P3 1 LCDSY 26 P3 2 CJ 27 P3 3 28 P6 0 KSO 29 P6 1 KS1 4 30 P6 2 KS2 31 52 12 P6 3 KS3 4 32 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 53C72N2 C72N4 P72NA SEG24 P8 0 SEG25 P8 1 SEG26 P8 2 SEG27 P8 3 SEG28 P8 4 SEG29 P8 5 SEG30 P8 6 SEG31 P8 7 Figure 15 1 S3P72N4 Pin Assignments 64 QFP ELECTRONICS 53C72N2 C72N4 P72NA S3P72N4 OTP Table 15 1 Pin Descriptions Used to Read Write the EPROM Main Chip During Programming Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port Serial clock pin Input only pin Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode O
139. ccumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction ELECTRONICS 2 11 ADDRESS SPACES S3C72N2 C72N4 P72N4 PROGRAMMING Selecting the Working Register Area The following examples show the correct programming method for selecting working register area 1 When ERB 0 VENT2 INTO 1 0 1 0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET SB 2 HL WX YZ EA 0 EA 00H 80H EA HL 40H HL WX EA YZ EA EA YZ WX HL SB lt 1 ERB lt 0 Jump to INTO address PUSH current SMB SRB Instruction does not execute because ERB 0 PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB SRB The POP instructions execute alternately with the PUSH instructions If an SMB n instruction is used in
140. ccumulator contains the value register pair HL contains the value and the carry flag is cleared to logic zero 0 585 EA lt 0 7 lt 0 SBS instruction skips on borrow but carry flag value is not affected JPS XXX Skip because a borrow occurred JPS YYY Jump to YYY is executed 2 The accumulator contains the value OAFH register pair HL contains the value and the carry flag is set to logic one SCF C 78 4 SBS EA HL EA lt 1 JPS Jump to XXX JPS was not skipped since no borrow occurred after SBS 5 82 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET SCF Set Carry Flag SCF Description The SCF instruction sets the carry flag to logic one regardless of its previous value Binary Code Operation Notation L 0 Example If the carry flag is cleared to logic zero the instruction SCF sets the carry flag to logic one ELECTRONICS 5 83 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 SMB SMB Operation Description Example 5 84 Select Memory Bank n The SMB instruction sets the upper four bits of a 12 bit data memory address to select a specific memory bank The constants 0 1 and 15 are usually used as the SMB operand to select the corresponding memory bank All references to data memory addresses fall within the following ad
141. ce registers as well as the stack pointer and port I O latches are not included in these descriptions More detailed information about how these registers are used is included in Part II of this manual Hardware Descriptions in the context of the corresponding peripheral hardware module descriptions 4 4 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP Register and bit IDs Name of individual used for bit addressing bit or related bits Associated Register location Register ID Register name hardware module in RAM bank 15 CLMOD Clock Output Mode Control Register CPU FDOH Bit 3 2 1 0 Identifier 9 RESET Value 0 0 3 Read Write W W Bit Addressing 4 4 4 4 CLMOD 3 Enable Disable Clock Output Control Bit 0 Disableclockouteut t Enableclockoutput J CLMOD 2 Bit 2 0 Always logic zero CLMOD 1 0 Clock Source and Frequency Selection Control B f o 1 Select system cock 624 0 Select system cock ovite af 4 oM _ 1 select system clock bores 665 4 oM 0 po R Read only Bit value immediately Bit number in W Write only following a RESET MSB to LSB order R W Read write Type of addressing Description of the Bit identifier used that must be used to effect of specific bit for bit addressing address the bit settings 1 bit 4 bit or 8 bit Figure 4 1 Register Description Format ELE
142. ced acknowledged INTO is acknowledged INTO is not serviced not serviced not serviced All CPU operations are disabled Mode release Interrupt request Only RESET input Interrupt request signals except INTO pre signal signals except INTO enabled by IEx or RESET input pre enabled by IEx or RESET input NOTES 1 Subclock stops by setting SCMOD 2 to 1 2 Main and sub clock oscillation continues ELECTRONICS 8 2 S3C72N2 C72N4 P72N4 POWER DOWN IDLE MODE TIMING DIAGRAMS OSCILLATION IDLE STABILIZATION INSTRUCTION 31 3 ms 4 19 MHz 4 NORMAL MODE IDLE MODE NORMAL MODE 2 4 465 CLOCK NORMAL OSCILLATION SIGNAL Figure 8 1 Timing When Idle Mode is Released by RESET IDLE INSTRUCTION MODE INTERRUPT ACKNOWLEDGE IME 1 RELEASE SIGNAL NORMAL MODE IDLE MODE NORMAL MODE EE CLOCK NORMAL OSCILLATION SIGNAL Figure 8 2 Timing When Idle Mode is Released by an Interrupt ELECTRONICS 8 3 POWER DOWN 53C72N2 C72N4 P72NA STOP MODE TIMING DIAGRAMS 8 4 OSCILLATION STOP STABILIZATION INSTRUCTION 31 3 ms 4 19 MHz NORMAL MODE STOP MODE IDLE MODE NORMAL MODE hp a a OSCILLATION CLOCK STOPS OSCILLATION RESUMES SIGNAL Figure 8 3 Timing When Stop Mode is Released by RESET OSCILLATION STABILIZATION
143. ck Main system clock fxt Subsystem clock fxx Selected system clock ELECTRONICS 6 1 OSCILLATOR CIRCUITS S3C72N2 C72N4 P72N4 Clock Control Registers When the system clock mode control register SCMOD and the power control register PCON are both cleared to zero after RESET the normal CPU operating mode is enabled a main system clock of fx 64 is selected and main system clock oscillation is initiated PCON is used to select normal CPU operating mode or one of two power down modes stop or idle Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power down mode The system clock mode control register SCMOD lets you select the main system clock fx subsystem clock fxt as the CPU clock and to start or stop main or sub system clock oscillation The resulting clock source either main system clock or subsystem clock is referred to as the CPU clock The main system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero By setting SCMOD 3 2 and SCMOD 0 to different values CPU can operate in a subsystem clock source and start or stop main or sub system clock oscillation To stop main system clock oscillation you must use the STOP instruction assuming the main system clock is selected or manipulate SCMOD 3 to 1 assuming the sub system clock is selected The main system clock frequencies can be divided by 4 8 o
144. ck or 32 768 kHz Sub clock 2 fxx system clock frequency WDMOD changes such as disable and enable you must set WDTCF flag to 1 for starting WDCNT from zero state ELECTRONICS TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 PROGRAMMING TIP Using the Watchdog Timer DI BITS EMB SMB 15 LD EA 00H LD SP EA LD A 0DH WDCNT input clock is 7 82 ms LD BMOD A MAIN BITS WDTCF Main routine operation period must be shorter than watchdog timer s period JP MAIN ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS 8 BIT TIMER COUNTER 0 TCO OVERVIEW Timer counter O TCO is used to count system events by identifying the transition high to low or low to high of incoming square wave signals To indicate that an event has occurred or that a specified time interval has elapsed TCO generates an interrupt request By counting signal transitions and comparing the current counter value with the reference register value TCO can be used to measure specific time intervals TCO has a reloadable counter that consists of two parts an 8 bit reference register TREFO into which you write the counter reference value and an 8 bit counter register TCNTO whose value is automatically incremented by counter logic An 8 bit mode register is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations To dyn
145. clock output pin TCLOO To select the clock frequency load the appropriate values to the TCO mode register TMODO The clock interval is selected by loading the desired reference value into the reference register TREFO To enable the output to the TCLOO pin the following conditions must be met TCO output enable TOEO must be set to 1 mode flag for P2 0 must be set to output mode 1 Output latch value for P2 0 must be set to 0 In summary the operational sequence required to output a TCO generated clock signal to the TCLOO pin is as follows 1 Loada reference value to TREFO Set the internal clock frequency in TMODO Initiate TCO clock output to TCLOO TMODO 2 1 Set P2 0 mode flag to 1 oet P2 0 output latch to O Set TOEO flag to 1 D amp Each time TCNTO overflows and an interrupt request is generated the state of the output latch is inverted and the TCO generated clock signal is output to the TCLOO pin PROGRAMMING TCO Signal Output to the TCLOO Pin Output a 30 ms pulse width signal to the TCLOO pin BITS EMB SMB 15 LD 79 LD TREFO EA LD EA 4CH LD TMODO EA LD EA 04H LD PMG2 EA P2 0 lt output mode BITR P2 0 P2 0 clear BITS TOEO ELECTRONICS 11 15 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 TCO EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the
146. clock to a subsystem clock and to stop the main system clock To do this you first need to set SCMOD 0 to 1 This switches the clock from fx to fxt but allows main system clock oscillation to continue Before the switch actually goes into effect a certain number of machine cycles must elapse After this time interval you can then disable main system clock oscillation by setting SCMOD 3 to 1 This same stepped approach must be taken to switch from a subsystem clock to the main system clock First clear SCMOD 3 to 0 to enable main system clock oscillation Until main osc is stabilized system clock must not be changed Then after a certain number of machine cycles has elapsed select the main system clock by clearing all SCMOD values to logic zero Following a RESET CPU operation starts with the lowest main system clock frequency of 15 3 usec at 4 19 MHz after the standard oscillation stabilization interval of 31 3 ms has elapsed Table 6 6 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect 6 10 ELECTRONICS 53C72N2 C72N4 P72NA OSCILLATOR CIRCUITS Table 6 6 Elapsed Machine Cycles During CPU Clock Switch SCMOD 0 0 SCMOD 0 1 BEFORE PCON 1 0 0 0 1 1 0 0 1 1 0 1 EE 120 1 MACHINE CYCLE 1 MACHINE CYCLE PCON 0 0 0 0 SCMOD 0 0 p 1 1 8 MACHINE CYCLES 8 MACHINE CYCLES ERE 0 0 1 1 16 MACHINE
147. ctrical Characteristics 40 to 85 C Vpp 1 8 V to 5 5 V Supply Current Ipp 2 Main operating 6 0 MHz 1 Vpp 5 V 10 4 19 MHz mA CO j 5 5 CPU fx 4 SCMOD 0000B Crystal oscillator C1 C2 22 4 19 MHz oos Main idle mode 6 0 MHz Vpp 5 V 10 4 19 MHz CPU fx 4 SCMOD 0000B Crystal oscillator C1 C2 22 pF 4 19 MHz 503 Sub operating Vpp 10 CPU fxt 4 SCMOD 1001B 32 kHz crystal oscillator oub idle mode Vpp 10 i CPU 4 SCMOD 1001B 32 kHz crystal oscillator IDD5 Stop mode VDD 5V 10 CPU fxt 4 SCMOD 1101B 2 Stop mode Vpp 5 V 10 CPU fx 4 SCMOD 0100 1 D C electrical values for supply current Ippi to Ippeg do not include current drawn through internal pull up resistors 3 gt co O and through LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation 3 When the system clock mode register SCMOD 1 set to 0100B the sub system clock oscillation stops The main system clock oscillation stops by the STOP instruction ELECTRONICS 15 6 53C72N2 C72N4 P72NA S3P72N4 OTP CPU CLOCK Main OSC Freq 1 5 MHz 1 0475 MHz 750 kHz 500 kHz 250 kHz 15 6 kHz SUPPLY VOLTAGE V CPU CLOCK 1 n x oscillator fre
148. d In 1 8 duty mode COMO CONWM 2 pins are selected n 1 4 duty mode pins are selected SEGMENT SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at bank 1 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 no select signal is sent to the corresponding segment pin ELECTRONICS 12 6 53C72N2 C72N4 P72NA LCD CONTROLLER DRIVER Static and 1 3 Bias V cp 3 Vat V 5 V 1 2 Bias V cp 2 5 Vat V pp 5 V Vi co Vict Vicp 3 V Vice Vi Static and 1 3 Bias V cp 5 Vat V 5 V Static and 1 3 Bias V cp 3 Vat V pp 3 V VDD LCON O Mo Vi Vict Vicp 5 V Vice Vi Voltage dividing resistor External resistor Figure 12 4 Voltage Dividing Resistor Circuit Diagrams ELECTRONICS 12 7 LCD CONTROLLER DRIVER 53C72N2 C72N4 P72NA Figure 12 5 LCD Signal Waveforms in Static Mode ELECTRONICS 12 8 53C72N2 C72N4 P72NA LCD CONTROLLER DRIVER TIMING COM2 Open STROBE Possible 0 1E1H XXI ew m 1E4H a 1E5H lt 0 iH x x oo em Eo D D D sea x lt lt x 8 1E9H Aa A lt gt
149. ddress area is used to store the vector addresses required to execute system resets and interrupts Start addresses for interrupt service routines are stored in this area along with the values of the enable memory bank EMB and enable register bank ERB flags that are used to set their initial value for the corresponding service routines The 12 byte area can be used alternately as general purpose ROM REF Instructions Locations 0020 007 are used as a reference area look up table for 1 byte REF instructions The REF instruction reduces the byte size of instruction operands REF can reference one 2 byte instruction two 1 byte instructions and 3 byte instructions which are stored in the look up table Unused look up table addresses can be used as general purpose ROM Table 2 1 Program Memory Address Ranges General purpose program memory instruction look up table area 0020H 007FH sid General purpose program memory 0080H 7FFH S3C72N2 1920 83C72N2 0080 S3C72N4 3968 53 72 4 ELECTRONICS 2 1 ADDRESS SPACES 53 72 2 72 4 72 4 GENERAL PURPOSE MEMORY AREAS The 20 byte area at ROM locations 000CH 001 FH and the 3 968 byte area at ROM locations OO80H OFFFH used as general purpose program memory Unused locations in the vector address area and REF instruction look up table areas can be used as general purpose program memory However care must be taken not to overwrite live data when writin
150. ddressing 1 If EMB 0 ADATA EQU 46H BDATA EQU LD EA SMB 0 LD ADATA EA 046H A 047H E LD BDATA EA lt A F8FH lt 2 1 ADATA EQU 46H EQU SMB 0 LD EA 0FFH LD ADATA EA 046H A 047H E LD BDATA EA lt A 08FH E 8 Bit Indirect Addressing 1 If EMB 0 ADATA EQU 46H SMB 1 Non essential instruction since EMB 0 LD HL ZADATA LD EA HL A lt 046 E lt 047 ELECTRONICS 3 11 ADDRESSING MODES 3C72N2 C72N4 P72N4 NOTES 3 12 ELECTRONICS S3C72N2 C72N4 P72N4 MEMORY MAP MEMORY MAP OVERVIEW To support program control of peripheral hardware addresses for peripherals are memory mapped to bank 15 of the RAM Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location Access to bank 15 is controlled by the select memory bank SMB instruction and by the enable memory bank flag EMB setting If the EMB flag is bank 15 can be addressed using direct addressing regardless of the current SMB value 1 bit direct and indirect addressing can be used for specific locations in bank 15 regardless of the current EMB value FOR HARDWARE REGISTERS Table 4 1 contains detailed information about I O mapping for peripheral hardware in bank 15 register locations F80H FFFH Use the I O map as quick reference source when w
151. ditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction Then it pushes the result onto the stack decreasing the stack pointer six times The higher bits of the PC with the exception of the lower 11 bits are cleared The subroutine call must therefore be located within the 2 Kbyte block 0000H 07FFH of program memory Binary Code Operation Notation ADR1 1 1 4 1 SP 1 SP 2 lt ERB SP 3 SP 4 lt PC7 0 SP 5 5 6 lt PC11 8 a a5 a4 SP lt SP 6 PC11 0 PC10 0 ADR11 The stack pointer value is 00H and the label PLAY is assigned to program memory location 0345H Executing the instruction CALLS PLAY at location 0123H will generate the following values SP OH OFDH 2H OFCH 5H OH 1H PC 0345H Data 1 written to stack locations OFFH OFAH as follows OFAH ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET CCF Complement Carry Flag CCF Description carry flag is complemented if C 1 it is changed to 0 and vice versa Binary Code Operation Notation gt r sjejrjo tjt o oec o Example If the carry flag is logic zero the instruction CCF changes the value to logic one
152. dress ranges Please note that since data memory spaces differ for various devices in the SAM47 product family the n value of the SMB instruction will also vary Register Areas sme Working registers otack and general purpose registers Display registers F80H FFFH hardware registers The enable memory bank EMB flag must always be set to 1 in order for the SMB instruction to execute successfully for memory banks 0 1 and 15 Binary Code Operation Notation om Binary Goa ie ap 11 If the flag is set the instruction SMB 0 selects the data memory address range for bank 0 000H OFFH as the working memory bank ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET SRB Select Register Bank SRB n Description The SRB instruction selects one of four register banks in the working register memory area The constant value used with SRB is 0 1 2 or 3 The following table shows the effect of SRB settings ERB Setting SRB Settings Selected Register Bank AlwayssettobankO set to bank O 2 ee os ae 1 mi 1 NOTE not applicable The enable register bank flag ERB must always be set for the SRB instruction to execute successlully for register banks 0 1 2 and 3 In addition if the ERB value is logic zero register bank 0 is always selected reg
153. e incoming clock pulses which are compared to the TREFO value as is incremented When there is a match TREFO an interrupt request is generated To program timer counter O to generate interrupt requests at specific intervals choose one of four internal clock frequencies divisions of the system clock and load a counter reference value into the TREFO register TCNTO is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMODO 4 TMODO 6 settings To generate an interrupt request the TCO interrupt request flag IRQTO is set to logic one the status of TOLO is inverted and the interrupt is generated The content of TCNTO is then cleared to 00H and TCO continues counting The interrupt request mechanism for TCO includes an interrupt enable flag IETO and an interrupt request flag IRQTO TCO OPERATION SEQUENCE The general sequence of operations for using TCO can be summarized as follows 1 Set TMODO 2 to 1 to enable TCO oet TMODO 6 to 1 to enable the system clock fxx input Set TMODO 5 and TMODO 4 bits to desired internal frequency fxx 2 Load a value to TREFO to specify the interval between interrupt requests Set the TCO interrupt enable flag IETO to 1 oet TMODO 3 bit to 1 to clear TCNTO IRQTO and and start counting increments with each internal clock pulse o e wW N When the comparator shows
154. e specific module address code 0 n BinryCode 000 Code Operation Notation EMB 0 1 ali a10 ROM 2 x n 7 6 EMB ERB ERB 0 1 ROM 2 x n 5 4 0 PC12 ADR ROM 2 x 3 0 lt 11 8 ROM 2 x n 1 7 0 lt PC7 0 n 0 1 2 3 4 5 6 7 rar as ac as 5 88 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET VENT Load EMB ERB and Vector Address VENTn Continued Example The instruction sequence ORG OOOOH VENTO 1 0 RESET VENT1 0 1 INTB VENT2 VENIS 0 1 INT1 ORG 000AH VENTS 0 1 INTTO causes the program sequence to branch to the RESET routine labeled setting to 1 and ERB to 0 when RESET is activated When a basic timer interrupt is generated VENT1 causes the program to branch to the basic timer s interrupt service routine INTB and to set the EMB value to 0 and the ERB value to 1 VENT2 then branches to INTO VENT3 INT1 and so on setting the appropriate EMB and ERB values ELECTRONICS 5 89 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Exchange or EA with Nibble or Byte XCH Operation Description Example 5 90 dst src A DA Exchange A and data memory contents Exchange A and register Ra contents A RRa Exchange A and indirect data memory EA DA Exchange EA and direct data memory contents EA RRb Exchange EA and register pair RRb conte
155. ectored interrupt is then initiated However when the release signal is caused by INT2 or INTW the operation is identical to the IME condition Assuming that both interrupt enable flag and interrupt request flag are set to 1 the release signal is generated when power down mode is entered ELECTRONICS 8 1 POWER DOWN 53C72N2 C72N4 P72NA Table 8 1 Hardware Operation During Power Down Modes __ Mode SubStop Main SubStop Idle System clock Main clock fx Sub clock fxt Main clock fx 1 Main fx or sub clock fxt STOP Setting SCMOD 2 to STOP IDLE 4 Clock oscillator Main clock oscillation Sub clock oscillation Main clock oscillation Only CPU clock Stops Stops stops stops 2 Basic timer stops Basic timer stops Basic timer stops Basic timer operates Timer counter 0 Operates only if TCLO Operates only if TCLO Operates only if TCLO Timer counter 0 is selected as counter is selected as counter is selected as counter operates clock clock clock Watch timer Operates only if sub Watch timer stops Watch timer stops Watch timer operates clock fxt is selected as counter clock LCD controller Operates only if sub LCD controller stops LCD controller stops LCD controller clock fxt is selected operates as LCD clock LCDCK External INT1 and INT2 are INTO INT1 and INT2 INT1 and INT2 are INT1 and INT2 are interrupts acknowledged INTO is is not servi
156. ecute an SMB n instruction specifying the number of the memory bank you want 0 1 or 15 For example the instruction SMB 1 selects bank 1 and SMB 15 selects bank 15 And remember to enable the selected memory bank by making the appropriate EMB flag setting The upper four bits of the 12 bit data memory address are stored in the SMB register If the SMB value is not specified by software or if a RESET does not occur the current value is retained RESET clears the 4 bit SMB value to logic zero The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls ELECTRONICS 3 5 ADDRESSING MODES 53 72 2 72 4 72 4 DIRECT AND INDIRECT ADDRESSING 1 bit 4 bit and 8 bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand Indirect addressing specifies a memory location that contains the required direct address The S307 instruction set supports 1 bit 4 bit and 8 bit indirect addressing For 8 bit indirect addressing an even numbered RAM address must always be used as the instruction operand 1 BIT ADDRESSING Table 3 2 1 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware 1 Notation Description Setting Area Bank Mapping DA b Direct bit is indicated by the RAM address DA memory All 1 bit bank selec
157. ed at the end of an interrupt service routine It pops the PC values successively from the Example stack and restores them to the program counter The stack pointer is incremented by six and the PSW enable memory bank EMB bit and enable register bank ERB bit are also automatically restored to their pre interrupt values Program execution continues from the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower level or same level interrupt was pending when the IRET was executed IRET will be executed before the pending interrupt is processed Operand w Code Operation Notation PC11 8 SP 1 SP PC7 0 lt SP 2 SP 3 PSW lt SP 4 SP 5 SP lt 6 The stack pointer contains the value An interrupt is detected in the instruction at location 0122H RAM locations OFDH OFCH and OFAH contain the values 2H 3H and 1H respectively The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 123H During a return from interrupt data is popped from the stack to the program counter The data in stack locations is organized as follows OFAH OFBH OFCH PCO OFDH 7 4 ELECTRONICS 5 55 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 JP Jump JP Operation Description Example
158. ed memory bit memb L C Load carry bit to a specified indirect memory bit H DA b C Load memory bit to a specified carry bit 8 4 Load indirect memory bit to a specified carry bit C H DA b The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand One of the operands must be the carry flag the other may be any directly or indirectly addressable bit The source is unaffected Code operation Notation mema b C memb L C I 0 H DA 3 0 b lt H DA b C lt memb 7 2 L 3 2 L 1 0 C memb L afo EREREJEIEIES 015 e at at Second Byte BitAddesss Addresses rope ao primero C H DA b 1 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET LDB Load LDB Continued Examples 1 The carry flag is set and the data value at input pin P1 0 is logic zero The following instruction clears the carry flag to logic zero LDB C P1 0 2 The P1 address is FF1H and the L register contains the value 9H 1001B The address memb 7 2 is 111100B and L 3 2 is 10B The resulting address is 11110010B or FF2H and P2 is addressed The bit value L 1 0 is specified as 01B bit 1 LD L 9H LDB C P1 L P1 L specifies P2 1 andC lt P2 1 3 The H register conta
159. elected Register Bank _0 Bak x O Paired Working Registers Each of the register banks is subdivided into eight 4 bit registers These registers named Y Z W X H L E and A can either be manipulated individually using 4 bit instructions or together as register pairs for 8 bit data manipulation The names of the 8 bit register pairs in each register bank are EA HL WX YZ and WL Registers A L X and Z always become the lower nibble when registers are addressed as 8 bit pairs This makes a total of eight 4 bit registers or four 8 bit double registers in each of the four working register banks Figure 2 5 Register Pair Configuration 2 10 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES Special Purpose Working Registers Register A is used as a 4 bit accumulator and double register EA as an 8 bit accumulator The carry flag can also be used as a 1 bit accumulator 8 bit double registers WX WL and HL are used as data pointers for indirect addressing When the HL register serves as a data pointer the instructions LDI LDD XCHI and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction 1 ACCUMULATOR 4 BIT ACCUMULATOR 8 BIT ACCUMULATOR Figure 2 6 1 Bit 4 Bit and 8 Bit A
160. en determined by the IPR When an interrupt occurs 150 and 151 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level Then when the interrupt service routine ends with an IRET instruction 150 and 151 values are restored to the PSW Table 2 6 shows the effects of 150 and 151 flag settings Table 2 6 Interrupt Status Flag Bit Settings IS1 150 Status of Currently Effect of ISO and 151 Settings Value Value Executing Process on Interrupt Request Control o 0 JAliterupt requests are serviced 1 1 Only high priority interrupt s as determined in the interrupt priority register IPR are serviced 4 Not applicable these bit settings are undefined Since interrupt status flags can be addressed by write instructions programs can exert direct control over interrupt processing status Before interrupt status flags can be addressed however you must first execute a DI instruction to inhibit additional interrupt routines When the bit manipulation has been completed execute an El instruction to re enable interrupt processing PROGRAMMING TIP Setting ISx Flags for Interrupt Processing The following instruction sequence shows how to use the ISO and 151 flags to control interrupt processing INTB DI Disable interrupt BITR 151 161 lt 0 BITS IS0 Allow interrupts according to IPR priority level Enable interrupt 2 18 ELECTRONICS S3C72N2 C72N4
161. ending on the specific bit or bits being addressed The PSW can be addressed during program execution regardless of the current value of the enable memory bank EMB Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt After the interrupt has been processed the PSW values are popped from the stack back to the PSW address When a RESET is generated the EMB and ERB values are set according to the RESET vector address and the carry flag is left undefined or the current value is retained PSW bits IS0 IS1 SC0 SC1 and SC2 are all cleared to logical zero Table 2 5 Program Status Word Bit Descriptions 1 c 501 800 5 ELECTRONICS 2 17 ADDRESS SPACES 53 72 2 72 4 72 4 INTERRUPT STATUS FLAGS 150 151 PSW bits 160 and 151 contain the current interrupt execution status values You can manipulate 150 and 151 flags directly using 1 bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register IPR you can process multiple interrupts by anticipating the next interrupt in an execution sequence The interrupt priority control circuit determines the 150 and 151 settings in order to control multiple interrupt processing When both interrupt status flags are set to O all interrupts are allowed The priority with which interrupts are processed is th
162. er functions Watch timer clock selection WMOD 0 Watch timer speed control WMOD 1 Enable disable watch timer WMOD 2 XI input level control WMOD 3 Buzzer frequency selection WMOD 4 and WMOD 5 Enable disable buzzer output WMOD 7 Table 11 8 Watch Timer Mode Register WMOD Organization Le we TC WMOD 7 0 Disable buzzer BUZ signal output F89H Enable buzzer BUZ signal output wan WMOD 5 4 2kHz buzzer BUZ signal output o 1 4 kHz buzzer BUZ signal output 8 kHz buzzer BUZ signal output a 16 kHz buzzer BUZ signal output Input level to XT ip pin is low Input level to XT pin is high Disable watch timer clear frequency dividing circuits Enable watch timer Normal mode sets IRQW to 0 5 seconds High speed mode sets IRQW to 3 91 ms Select fxx 128 the watch timer clock fw oelect subsystem clock as watch timer clock fw NOTE System clock frequency fxx is assumed to be 4 19 MHz subsystem clock fxt is assumed to be 32 768 kHz 7 ELECTRONICS 11 25 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 5 PROGRAMMING Using the Watch Timer 1 Select a subsystem clock as the LCD display clock 0 5 second interrupt and 2 kHz buzzer enable BITS EMB SMB 15 LD EA 04H LD PMG2 EA 2 3 lt output mode 2 3 LD 85 LD WMOD EA BITS IEW 2 S
163. eration Description Examples dst b Test specified bit and skip if memory bit is set 8 248 H DA b The specified bit within the destination operand is tested If it is 1 the instruction that immediately follows the BTST instruction is skipped otherwise the instruction following the BTST instruction is executed The destination bit value is not affected s i escasa okip if mema b 1 Skip if memb 7 2 L 3 2 0 1 Skip if H DA 3 0 b 1 82 at a0 Bit Addresses ofm a ee ai eo ORR 1 If RAM bit location 30H 2 1 set to logic zero the following instruction sequence will execute the RET instruction BIST 30H 2 If 2 1 then skip HET If 30H 2 0 return JP LABEL2 ELECTRONICS 5 39 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 BIST Bit Test and Skip on True BTST Examples 5 40 Continued 2 You can use BTST in the same way to manipulate a port pin address bit BIST P2 0 If P2 0 1 then skip RET f P2 0 0 then return JP LABEL3 Assume that P2 2 P2 3 and P3 0 P3 3 are cleared to 0 LD 2 BIST First P1 OAH P2 2 1111008 10B 10B 2 2 INCS JR BP2 Bank 0 location 0 is tested and regardless of the current EMB value BTST has the following effect FLAG EQU OAOH 0 BITR EMB LD
164. et to 1 the contents of TCNTO IRQTO and are cleared counting starts from TMOD0 3 is automatically reset to 0 for normal TCO operation When TCO operation stops TMODO 2 0 the contents of the TCO counter register TCNTO are retained until TCO is re enabled The TMODO 6 TMODO 5 and TMODO 4 bit settings are used together to select the TCO clock source This selection involves two variables Synchronization of timer counter operations with either the rising edge or the falling edge of the clock signal input at the TCLO pin and Selection of one of four frequencies based on division of the incoming system clock frequency for use in internal TCO operation Table 11 6 TCO Mode Register TMODO Organization TMODO 7 Always logic zero F91H TMODO 6 opecify input clock edge and internal frequency TMODO 5 TMODO 4 TMODO 2 Disable timer counter 0 retain TCNTO contents Enable timer counter 0 TMODO 1 0 Always logic zero TMODO0 0 O Always logic zero TMODO 3 1 Clear TCNTO IRQTO and TOLO and resume counting immediately This bit is automatically cleared to logic zero immediately after counting resumes ELECTRONICS 11 17 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 Table 11 7 TMODO 6 TMODO 5 and TMODO 4 Bit Settings 0 0 0 External clock input TCLO on rising edges 00 0 1 External clock input TCLO on falling edges __ o
165. et to logical one an interrupt will not be serviced until its corresponding flag is also enabled Interrupt enable flags can be read written or tested directly by 1 bit instructions IEx flags can be addressed directly at their specific RAM addresses despite the current value of the enable memory bank EMB flag Table 7 7 Interrupt Enable and Interrupt Request Flag Addresses ues _ IEW IRQW FBEH FBFH FBCH NOTES 1 IEx refers generally to all interrupt enable flags 2 IRQx refers generally to all interrupt request flags 3 IEx Ois interrupt disable mode 4 1 1 is interrupt enable mode ELECTRONICS 53C72N2 C72N4 P72NA INTERRUPTS Interrupt Request Flags IRQx Interrupt request flags are read write addressable by 1 bit or 4 bit instructions IRQx flags can be addressed directly at their specific RAM addresses regardless of the current value of the enable memory bank EMB flag When a specific IRQx flag is set to logic one the corresponding interrupt request is generated The flag is then automatically cleared to logic zero when the interrupt has been serviced Exceptions are the watch timer interrupt request flags IRQW and the external interrupt 2 flag IRQ2 which must be cleared by software after the interrupt service routine has executed IRQx flags are also used to execute interrupt requests from software In summary follow these guidelines for using IRQx flags
166. ference area specific combinations must be used for the first and second 1 byte instruction These combinations are described in Table5 Table 5 1 Valid 1 Byte Instruction Combinations for REF Look Ups First 1 Byte Instruction Second 1 Byte Instruction instruction Operand instruction Opermd RRb LD A RRq R RRb R LD HL A R RRb R NOTE Ifthe MSB value of the first one byte binary code in instruction is 0 the instruction cannot be referenced by REF instruction a 5 2 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET Reducing Instruction Redundancy When redundant instructions such as LD A im and LD EA imm are used consecutively in a program sequence only the first instruction is executed The redundant instructions which follow are ignored that is they are handled like a NOP instruction When LD HL imm instructions are used consecutively redundant instructions are also ignored In the following example only the LD A im instruction will be executed The 8 bit load instruction which follows it is interpreted as redundant and is ignored LD A im Load 4 bit immediate data im to accumulator LD EA imm Load 8 bit immediate data imm to extended accumulator In this example the statements LD A 2H 0 A 3H are ignored BITR EMB LD A 1H Execute instruction LD A 2H Ignore redundant instruction LD A 3H Ignore redundant instruction LD
167. flag is set to logic one The IME flag mapped FB2H 3 can be directly manipulated by El and DI instructions regardless of the current enable memory bank EMB value Table 7 4 Interrupt Priority Register Settings IPR2 PRO 7 ResutofIPRBitSeting 0 0 jNomaliterupt handling according to default priority settings x O o 1 INTB interrupt at highest 1 0 INTO interrupt highest priority x O 3 t Process INTI interrupt at highest priority o3 9 Reserve 0 x 1 1 Process INTTO interrupt at highest priority NOTE During normal interrupt processing interrupts are processed in the order in which they occur If two or more interrupt requests are received simultaneously the priority level is determined according to the standard interrupt priorities in Table 7 3 the default priority assigned by hardware when the lower three IPR bits 0 In this case the higher priority interrupt request is serviced and the other interrupt is inhibited Then when the high priority interrupt is returned from its service routine by an IRET instruction the inhibited service routine is started ELECTRONICS 7 7 INTERRUPTS 53C72N2 C72N4 P72NA 9 PROGRAMMING Setting the INT Interrupt Priority The following instruction sequence sets the INT1 interrupt to high priority BITS EMB SMB 15 DI IPR 3 lt 0 LD A 3H LD PR
168. four internal clock frequencies or an external clock Determines when to generate an interrupt by comparing the current value of the counter register TCNTO with the reference value previously programmed into the reference register TREFO Where a clock pulse is stored pending output to the TCO output pin TCLOO When the contents of the TCNTO and TREFO registers coincide the timer counter interrupt request flag IRQTO is set to 1 the status of TOLO is inverted and an interrupt is generated Must be set to logic one before the contents of the TOLO latch can be output to TCLOO Cleared when TCO operation starts and the TCO interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide Must be set to logic one before the interrupt requests generated by timer counter O can be processed ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS Table 11 4 TCO Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value TMODO Control Controls TCO enable disable bit 8 bit F90H F91H 8 bit write 2 clears and resumes counting only operation bit 3 sets input clock TMODO 3 is and clock frequency bits 6 4 also 1 bit writeable TONTO Counter Counts clock pulses matching 8 bit F94H F95H 8 bit the TMODO frequency setting read only TREFO Reference Stores reference value for the 8 bit F96H F97H 8 bit FFH timer counter O inte
169. g programs that use special purpose areas of the ROM VECTOR ADDRESS AREA The 12 byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts The starting addresses of interrupt service routines are stored in this area along with the enable memory bank EMB and enable register bank ERB flag values that are needed to initialize the service routines 12 byte vector addresses are organized as follows PC6 5 4 2 1 To set up the vector address area for specific programs use the instruction VENTn The programming tips on the next page explain how to do this VECTOR ADDRESS AREA 12 Bytes GENERAL PURPOSE AREA 20 Bytes INSTRUCTION REFERENCE AREA GENERAL PURPOSE AREA 1 920 Bytes 3 968 Bytes Figure 2 1 ROM Address Structure Figure 2 2 Vector Address Structure 2 2 ELECTRONICS 53C72N2 C72N4 P72NA ADDRESS SPACES PROGRAMMING Defining Vectored Interrupts The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory 1 When all vector interrupts are used ORG 0000H VENTO 1 0 RESET lt 1 ERB lt 0 Jump to RESET address VENT 1 0 0 INTB EMB lt 0 ERB lt 0 Jump to INTB address VENT2 0 0 INTO lt 0 ERB lt 0 Jump to INTO address VENT3 0 0 INT 1 lt 0 ERB lt 0 Jump to INT1 address ORG 000AH VEN
170. gardless of the current EMB flag setting Here are a few guidelines to keep in mind regarding data memory addressing When you address peripheral hardware locations in bank 15 the mnemonic for the memory mapped hardware component can be used as the operand in place of the actual address location Always use an even numbered RAM address as the operand in 8 bit direct and indirect addressing With direct addressing use the RAM address as the instruction operand with indirect addressing the instruction specifies a register which contains the operand s address ELECTRONICS 3 1 ADDRESSING MODES 3C72N2 C72N4 P72N4 q Bu b DA 0 on X AREAS EMB 0 EMB 0 EMB 1 x x 000H WORKING REGISTERS 020H 07FH 080H GENERAL REGISTERS AND STACK 1 1 DISPLAY SMB REGISTERS 1FFH F80H BANK 15 PERIPHERAL HARDWARE REGISTERS FFFH NOTES 1 X means don t care 2 Blank columns indicate RAM areas that are not addressable given the addressing method and enable memory bank EMB flag setting shown in the column headers Figure 3 1 RAM Address Structure 3 2 ELECTRONICS 53C72N2 C72N4 P72NA ADDRESSING MODES EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address When a RESET is generated internally bit 7 of program memory address 0000H is written to
171. gister that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency CLMOD is addressable by 4 bit write instructions only RESET clears CLMOD to logic zero which automatically selects the CPU clock as the clock source without initiating clock oscillation and disables clock output CLMOD 3 is the enable disable clock output control bit CLMOD 1 and CLMOD 0 are used to select one of four possible clock sources and frequencies normal CPU clock fxx 8 fxx 16 or fxx 64 Table 6 7 Clock Output Mode Register CLMOD Organization CLMOD Bit Settings Resulting Clock Output CLMOD 1 CLMOD 0 Clock Source Frequency o 0 CRU clock 64 fx 64 xt 4 1 05 MHz 524 kHz 65 5 kHz O 1 fxx 8 524 kHz fxx 16 262 kHz x64 65 5 kHz CLMOD 3 Result of CLMOD 3 Setting Clock output is disabled Clock output is enabled NOTE Assumes that fxx 4 19 MHz 6 12 ELECTRONICS 53C72N2 C72N4 P72NA OSCILLATOR CIRCUITS CLOCK OUTPUT CIRCUIT The clock output circuit used to output clock pulses to the CLO pin has the following components 4 bit clock output mode register CLMOD Clock selector Port mode flag CLO output pin P2 2 CLMOD 3 CLMOD 2 CLMOD 1 P2 2 OUTPUT LATCH CLMOD O clocks fxx 8 fxx 16 fxx 64 CPU clock Figure 6 7 CLO Output Pin Circuit Diagram CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the C
172. he carry flag when they are executed in combination with the instruction ADS A im If an ADS A im instruction immediately follows an ADC A HL or A HL instruction in a program sequence the ADS instruction does not skip the instruction following ADS even if it has a skip function If however an ADC A HL SBC A HL instruction is immediately followed by an ADS A im instruction the ADC SBC skips on overflow or if there is no borrow to the instruction immediately following the ADS and program execution continues Table 5 3 contains additional information and examples of the ADC and A HL skip feature Table 5 3 Skip Conditions for ADC and SBC Instructions Sample If the result of Then the execution Reason Instruction Sequences instruction 1 is sequence is ADC A HL Overflow ADS cannot skip ADS A im instruction 3 even if it has XXX No overflow a skip function XXX SBC A HL ADS A im XXX Borrow ADS cannot skip instruction 3 even if it has No borrow a skip function ELECTRONICS 5 5 SAM47 INSTRUCTION SET SYMBOLS and CONVENTIONS Table 5 4 Data Type Symbols Symbol Data Type 7 4 a Adress data ma iJ narctacaressing deta Table 5 5 Register Identifiers Full Register Name 4 bit accumulator A L H X W 21 8 bit extended accumulator EA 4 bit working registers 8 bit memory pointer HL
173. her important features of the SAM47 instruction set include 1 byte referencing of long instructions REF instruction Redundant instruction reduction string effect Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction Several instructions have multiple operand formats Predefined values or labels can be used as instruction operands when addressing immediate data Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA mema memb b and so on Using instruction labels can greatly simplify program writing and debugging tasks INSTRUCTION SET FEATURES In this Chapter the following SAM47 instruction set features are described in detail Instruction reference area Instruction redundancy reduction Flexible bit manipulation ADC and SBC instruction skip condition NOTE The ROM size accessed by instruction may change for S3C72N2 S3C72NA ELECTRONICS 5 1 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Instruction Reference Area Using the 1 byte REF Reference instruction you can reference instructions stored in addresses 0020 007 of program memory the REF instruction look up table The location referenced by REF may contain either two 1 byte instructions or a single 2 byte instruction The starting address of the instruction being referenced must always be an even n
174. ically cleared to logic zero whenever the BMOD register control bit BMOD 3 is set to 1 to restart the basic timer It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected When BCNT has incremented to hexadecimal FFH 255 clock pulses it is cleared to and an overflow is generated The overflow causes the interrupt request flag IRQB to be set to logic one When the interrupt request is generated BCNT immediately resumes counting with incoming clock signal NOTE Always execute a read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing If after two consecutive reads the BCNT values match you can select the latter value as valid data Until the results of the consecutive reads match however the read operation must be repeated until the validation condition is met BASIC TIMER OPERATION SEQUENCE The basic timer s sequence of operations may be summarized as follows Set counter buffer bit BMOD 3 to logic one to restart the basic timer is then incremented by one per each clock pulse corresponding to BMOD selection BONT overflows if 255 FFH When an overflow occurs the IRQB flag is set by hardware to logic one The interrupt request is generated is then cleared by hardware to logic zero Basic timer resumes counting clock pulses ELECTRONICS
175. in oscillator runs Sub oscillator is stopped by SCMOD 2 System clock is the main oscillation clock IDLE instruction STOP instruction IDLE instruction Setting SCMOD 2 to 1 This mode can be released only by an external reset STOP instruction This mode can be released by an interrupt and reset NOTE The current consumption 5 gt B gt gt ELECTRONICS 6 9 OSCILLATOR CIRCUITS S3C72N2 C72N4 P72N4 SWITCHING THE CPU CLOCK Together bit settings in the power control register PCON and the system clock mode register SCMOD determine whether a main system or a subsystem clock is selected as the CPU clock and also how this frequency is to be divided This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies SCMOD 3 scmod 2 and SCMOD 0 select the main system clock fx or a subsystem clock and start or stop main or sub system clock oscillation 1 and PCON O control the frequency divider circuit and divide the selected fx clock by 4 8 64 or fxt clock by 4 NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications the previously selected clock continues to run for a certain number of machine cycles For example you are using the default CPU clock normal operating mode and a main system clock of fx 64 and you want to switch from the fx
176. ins the value 2H and FLAG 20H 3 The address for H is 0010B and for FLAG 3 0 the address is 0000B The resulting address is 00100000B or 20H The bit value is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H LDB C H FLAG FLAG 20H 3 4 The following instruction sequence sets the carry flag and the loads the 1 data value to the output pin P2 0 setting it to output mode SCF 1 LDB P2 0 C 2 0 lt 1 5 The P1 address is FF1H and L 9H 1001B The address memb 7 2 is 111100B and L 3 2 is 10B The resulting address 11110010B specifies P2 The bit value L 1 0 is specified as 01B bit 1 Therefore P1 L P2 1 SCF Qe LD LDB P1 L C P1 L specifies P2 1 P231e 1 6 In this example H 2H and FLAG 20 3 and the address 20H is specified Since the bit value is 3 H FLAG 20H 3 FLAG EQU 20H 3 RCF LD H 2H LDB H FLAG C FLAG 20H 3 lt 0 NOTE Port pin names used examples 4 and 5 may vary with different SAM47 devices ELECTRONICS 5 65 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 LDC Load Code Byte LDC dst src EA WX Load code byte from WX to EA EA EA Load code byte from EA to EA Description This instruction is used to load byte from program memory into an extended accumulator The address of the byte fetched is the five highest bit values in the program counter and the contents of an 8 bit working register
177. ion JPS is skipped since a borrow occurred after the LDD A HL and instruction JPS YYY is executed ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET LDI Load Data Memory and Increment LDI Operation Description Example dst src A HL Load indirect data memory to A increment register L 1 2 5 contents and skip on overflow The contents of a data memory location are loaded into the accumulator and the contents of the register L are incremented by one If an overflow occurs e g if the resulting value in register L is OH the next instruction is skipped The contents of data memory and the carry flag value are not affected Binary Code Operation Notation A HL 1 1 1 lt HL then L lt L skip if L OH Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value OFH LD HL 2FH LDI A HL A lt L 1 JPS XXX Skip JPS YYY He 2H and L lt The instruction 5 is skipped since an overflow occurred after the LDI A HL and the instruction JPS YYY is executed ELECTRONICS 5 69 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 No Operation NOP o dor Description operation is performed NOP instruction It is typically used for timing delays One causes a 1 cycle delay with a 1 us cycle time five NOPs would therefore cause a 5 us delay
178. ion does not skip even if an overflow occurs This function is useful for decimal adjustment operations a 8 6 decimal addition the contents of the address specified by the HL register is 6H 0 LD A 8H A 8H SBC A HL A lt 6H C 0 2H lt 0 ADS A 0AH Skip this instruction because no borrow after SBC result JPS XXX b 3 4 decimal addition the contents of the address specified by the HL register is RCF 0 LD lt 3H SBC A HL A lt 3H 4H C 0 OFH C lt 1 ADS A 0AH No skip lt OFH OAH 9H The skip function of ADS A im is inhibited after a A QHL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 81 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 5 Subtract SBS dst src A HL Subtract indirect data memory from A skip on borrow EA RR Subtract register pair RR from EA skip on borrow RRb EA Subtract EA from register pair RRb skip on borrow Description The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected skip is executed if a borrow occurs The value of the carry flag is not affected 1 lt skip borrow EA EA skip on borrow 1 0 lt RRb EA skip on borrow Examples 1 The a
179. ip on carry 0 1 EA imm skip on carry skip on carry 0 EA EA skip RRb EA ADS A im A HL EA RR RRb EA 0 RRb RRb EA skip on carry EN 0 C A A HD C 0 lt EA RR C SBC A HL EA RR r1 C RRb lt EA C HL skip on borrow EA lt EA RR skip borrow nos 0 RRb lt RRb EA skip on borrow R R 1 skip on borrow 0 RR lt RR 1 skip on borrow 0 R R 1 skip on carry RRb EA SBS A HL EA RR RRb EA DECS INCS lt DA 1 skip carry HL HL 1 skip carry lt lt RRb lt RRb 1 skip on carry ELECTRONICS 5 1 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Table 5 20 Bit Manipulation Instructions Binary Code Summary Operand Binary Code Operation Notation BENS RAR ENES BEIDE m f DAD 1 46 5 a4 a2 at ofo ESES 1 a a fo 1 Skip if H DA 3 0 b 1 and clear Hx memb 7 2 L 3 2 b L 1 0 lt 1 FE BTST DA b mema b memb L H DA b BISF DA b mema b memb L m 25 Ea a4 _ 1 Sepe Skip if H DA 3 0 b 0 1
180. irect and indirect addressing modes The addressable RAM areas when 1 are as follows If SMB 0 000H OFFH If SMB 1 1EO0H 1FFH If SMB 15 F80H FFFH EMB 0 When the enable memory bank flag EMB is set to logic zero the addressable area is defined independently of the SMB value and is restricted to specific locations depending on whether a direct or indirect address mode is used If EMB 0 the addressable area is restricted to locations 000 07 in bank 0 and to locations in bank 15 for direct addressing For indirect addressing only locations OOOH OFFH in bank 0 are addressable regardless of SMB value To address the peripheral hardware register bank 15 using indirect addressing the EMB flag must first be set to 1 and the SMB value to 15 When a RESET occurs the EMB flag is set to the value contained in bit 7 of ROM address 0000H EMB Independent Addressing At any time several areas of the data memory can be addressed independent of the current status of the EMB flag These exceptions are described in Table 3 1 Table 3 1 RAM Addressing Not Affected by the EMB Value Addressing Method Affected Hardware Program Examples 4 bit indirect addressing using WX Not applicable LD A WX and WL register pairs 8 bit indirect addressing using SP PUSH EA POP EA 1 bit direct addressing PSW SCMOD BITS FFOH FFFH IRQx I O IE4 FCO
181. itional machine cycles required for an instruction to execute given that the instruction has a skip function S skip The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped whether it is a 1 byte 2 byte or 3 byte instruction A skip is also executed for SMB and SRB instructions The values in additional machine cycles for S for the three cases in which skip conditions occur are as follows Case 1 No skip o Ocycles Case 2 Skip is 1 byte or 2 byte instruction S 1 cycle Case 3 Skip is 3 byte instruction S 2 cycles NOTE REF instructions are skipped in one machine cycle ELECTRONICS 5 7 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 HIGH LEVEL SUMMARY This Chapter contains a high level summary of the SAM47 instruction set in table format The tables are designed to familiarize you with the range of instructions that are available in each instruction category These tables are a useful quick reference resource when writing application programs If you are reading this user s manual for the first time however you may want to scan this detailed information briefly and then return to it later on The following information is provided for each instruction Instruction name Operand s Brief operation description Number of bytes of the instruction and operand s Number of machine cycles required to execute the
182. le stack location During an interrupt sequence subroutines may be nested up to the number of levels which are permitted in the stack area INTERRUPT PUSH CALL When INT is acknowledged After PUSH SP lt SP 2 After CALL SP SP 6 SP 4 SP 6 11 PC8 LOWER REGISTER UPPER REGISTER Figure 2 7 Push Type Stack Operations 2 14 ELECTRONICS S3C72N2 C72N4 P72N4 ADDRESS SPACES POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers for the PUSH instruction it is the POP instruction for CALL the instruction RET or SRET for interrupts the instruction IRET When a pop operation occurs the SP is incremented by a number determined by the type of operation and points to the next free stack location POP Instructions A POP instruction references the SP to write data stored in two 4 bit stack locations back to the register pairs and SB register The value of the lower 4 bit register is popped first followed by the value of the upper 4 bit register After the POP has executed the SP is incremented by two and points to the next free stack location RET and SRET Instructions The end of a subroutine call is signaled by the return instruction RET or SRET The RET or SRET uses the SP to reference the six 4 bit stack locations used for the CALL and to write this data back to the PC the EMB and the ERB After the RET or SRET
183. lock Source and Frequency Selection Control Bits kHz or 8 192KHz 1 Select system clock fxx 8 524 kHz EB Select system clock fxx 16 262 kHz Select system clock fxx 64 65 5 kHz NOTE and is the system clock and the main clock respectively given a clock frequency of 4 19 MHz fxt is the sub clock given a clock frequency of 32 768KHz Select CPU clock source fx 4 fx 8 fx 64 fxt 4 1 05 MHz 524 kHz 65 5 o ELECTRONICS 4 7 3C72N2 C72N4 P72N4 1 IRQO 1 INTO 1 Interrupt Enable Request Flags FBEH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IE1 INT1 Interrupt Enable Flag Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag Generate INT1 interrupt This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin IEO INTO Interrupt Enable Flag Disable interrupt requests at the INTO Enable interrupt requests at the INTO pin IRQO INTO Interrupt Request Flag 4 8 Generate INTO interrupt This bit is set and cleared automatically by hardware when rising or falling edge detected at INTO pin S3C72N2 C72N4 P72N4 MEMORY MAP IE2 IRQ2 2 Interrupt Enable Request Flags FBFH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic
184. lock is selected as system clock and it 5 currently operating and peripheral hardware components are powered down In sub stop mode assuming sub clock is selected sub system clock oscillation is halted by setting SCMOD 2 to 1 The effect of stop mode on specific peripheral hardware components CPU basic timer timer counter 0 watch timer and LCD controller and on external interrupt requests is detailed in Table 8 1 NOTE Do not use stop mode if you are using an external clock source because X input must be restricted internally to to reduce current leakage Idle or main stop modes are terminated either by a RESET or by an interrupt which is enabled by the corresponding interrupt enable flag When power down mode is terminated by RESET a normal reset operation is executed Assuming that both the interrupt enable flag and the interrupt request flag are set to 1 power down mode is released immediately upon entering power down mode Sub stop mode can be terminated by RESET only When an interrupt is used to release power down mode the operation differs depending on the value of the interrupt master enable flag IME Ifthe IME flag 0 program execution starts immediately after the instruction issuing a request to enter power down mode is executed The interrupt request flag remains set to logical one Ifthe flag 1 two instructions are executed after the power down mode release and the v
185. los 5 7 Calculating Additional Machine Cycles for SKIDS nene 5 7 FIGS VEL SUPE Vedasti sene use C s teen mia c E 5 8 Pilar y COGS tacente d Ro talento i auc Ra ied una aed 5 13 Instruction Descriptions c aru ap 5 23 Chapter 6 Oscillator Circuits UCN e 6 1 Mee T T I um 6 1 Clock Control FeglSlels 6 2 Main Sy Stem Oscillator E Ve e fe Eau e tite bo Ct e p o ea nut cli Rd 6 4 oubsystem OScillator CIRCUITS 6 4 0 Dr 6 5 ASIPEICHOMN GY Cle RII CEREREM 6 6 Systemi Clock Mode Register OO MOD tic vat Ma b Lv DE 6 7 P E gt eaa e a 6 10 Clock Output Mode Register CEMOD Ear tea Dou 6 12 OUIDUL CIFOUL died da yuya thua UR bead dta PEN a ke uae neus 6 13 Clock OUMU PROCS CUMS CUR EET ev ou b 6 13 Chapter 7 Interrupts OC V OO aa yu yk NM
186. lt 0 and skip BITS CFLAG Else if OBAH O 0 lt 1 2 If EMB 1 AFLAG EQU 34H 3 EQU 85H 3 CFLAG EQU OBAH O SMB 0 LD H 0BH H lt 0BH BISTZ H CFLAG If OBAH O 1 OBAH O lt 0 and skip BITS CFLAG Else if OBAH 0 0 OBAH O lt 1 ELECTRONICS 3 7 ADDRESSING MODES 53 72 2 72 4 72 4 4 ADDRESSING Table 3 3 4 Bit Direct and Indirect RAM Addressing Notation Description Setting Area Bank Direct 4 bit address indicated 4 bit by the RAM address DA and addressable the memory bank selection peripherals SMB 15 indicated by the memory bank All 4 bit selection and register HL addressable F80H FFFH Bank 15 peripherals SMB 15 WX Indirect 4 bit address indicated X 000H OFFH Bank 0 by register WX WL Indirect 4 bit address indicated X 000H OFFH Bank 0 by register WL NOTE applicable 3 8 ELECTRONICS S3C72N2 C72N4 P72N4 PROGRAMMING TIP 4 Bit Addressing Modes 4 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD SMB 0 LD ADATA A LD BDATA A 2 1 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD SMB 0 LD ADATA A LD BDATA A 4 Bit Indirect Addressing ADDRESSING MODES Non essential instruction since EMB 0 lt P3 Non essential instruction since EMB 0 046 LCON A P3 046 lt gt gt
187. lue is undefined The carry flag can be directly manipulated by predefined set of 1 bit read write instructions independent of other bits in the PSW Only the ADC and SBC instructions and the instructions listed in Table 2 7 affect the carry flag Table 2 7 Valid Carry Flag Manipulation Instructions Operation Type Instructions Carry Flag Manipulation Direct manipulation Set carry flag to 1 Clear carry flag to 0 reset carry flag C Invert carry flag value complement carry flag BISTC Test carry and skip if C 1 Bit transfer LDB operand 1 Load carry flag value to the specified bit LDB 1 Load contents of the specified bit to carry flag Boolean manipulation BAND C operand 1 AND the specified bit with contents of carry flag and save the result to the carry flag BOR operand OR the specified bit with contents of carry flag and save the result to the carry flag BXOR C operand XOR the specified bit with contents of carry flag and save the result to the carry flag Interrupt routine INTn 2 Save carry flag to stack with other PSW bits Return from interrupt IRET Restore carry flag from stack with other PSW bits NOTES 1 The operand has three bit addressing formats mema a memb L and DA b 2 INTn refers to the specific interrupt being executed and is not an instruction ELECTRONICS 2 21 ADDRESS SPACES 53 72 2 72 4 72 4 PROGRAMMING TIP
188. ly follows it otherwise the instruction following the BTSF is executed The destination bit value is not affected sss Skip if DA b 0 e at ur seres Skip if memb 7 2 L 3 2 0 Skip if H DA 3 0 b 0 a2 a0 Bit Addresses 2 a o r Examples 1 If RAM bit location 30H 2 is set to logic zero the following instruction sequence will cause the program to continue execution from the instruction identified as LABEL2 BISF 30H 2 30H 2 0 then skip HET If 30H 2 1 return JP LABEL2 2 You can use BTSF in the same way to manipulate a port pin address bit BTSF P2 0 If P2 0 0 then skip RET lf P2 0 1 then return JP LABEL3 ELECTRONICS 5 37 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 5 Test and Skip on False BTSF Continued Examples P2 2 P2 3 and 0 are tested LD 2 BTSF 1 First 1 P2 2 1111008 10B 10B OF2H 2 RET INCS 2 4 Bank 0 location is tested and regardless of the current EMB value BTSF has the following effect FLAG EQU 0 BITR EMB LD H 0AH BISF H FLAG If bank 0 0H O OAOH O 0 then skip RET 5 38 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET BIST Bit Test and Skip on True BTST Op
189. notanda ent dicet 6 3 6 2 Giyslal Geramie OsGillal0r u uuu ik o bob dU eiu UAR 6 4 6 3 T 6 4 6 4 FC eie MT TEMERE 6 4 6 5 Grystal Geramic OSCIIIBEOE ud ecansuawts lup dc loa eed Ded au nan 6 4 6 6 EXIGIT 6 4 6 7 CLO Output Pin Circuit Diagram 6 13 7 1 Interf pt Execution Flowchart essiens e au tuta eee ek Se 7 3 7 2 Interrupt Control Circuit DIA OVA n Ra XR APRES 7 4 7 3 Interrupt Handling asses oie 7 7 4 Multi Level Interrupt Handling 7 6 7 5 Circuit Diagram for INTO and INT1 7 9 7 6 Circuit Diagram for INT2 and KS0 KS3 Pins 00 02 2 7 11 S3C72N2 C72N4 P72N4 xi List of Figures Continued Figure Title Page Number Number 8 1 Timing When Idle Mode is Released by 8 3 8 2 Timing When Idle Mode is Released by Interrupt 8 3 8 3 Timing When Stop Mode is Released by 8 4 8 4 Timing When Main Stop or Main Sub Stop Mode is Release by an Interrupt 8 4 9 1 Timing
190. nts EA HL Exchange EA and indirect data memory contents The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source Binary Code Operation Notation A DA A RRa EA DA EA RRb EA HL lt gt DAE lt gt DA 1 EA lt gt RRb A lt gt HL E e HL 1 Double register HL contains the address 20H The accumulator contains the value 3FH 00111111B and internal RAM location 20H the value 75H 01110101B The instruction a6 o EA HL leaves RAM location 20H with the value 3FH 00111111B and the extended accumulator with the value 75H 011101018 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET XCHD Exchange and Decrement XCHD dst src A HL Exchange A and data memory contents decrement 1 2 5 contents of register L and skip on borrow Description The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L If the content of register L is OFH the next instruction is skipped The value of the carry flag is not affected Binary Code Operation Notation A HL 11 1 1 HL then L lt L 1 skip if L OFH Example Register pair HL contains the address 20H and internal RAM location 20H contains the value OFH LD HL 20H LD A 0H XCHD A HL lt O
191. nued Pin Description Reset Circuit Type Value Type LCDSY I O LCD synchronization clock output for LCD Input display expansion External clock input for timer counterO clock input for timer counter 0 LL LIMEN eee INTO External interrupt The triggering edge for 17 P1 0 Input A 4 INT1 INTO and INT1 is selectable Only INTO is 18 P1 1 synchronized with the system clock INT2 Quasi nterrupt with detection of rising 19 P1 2 Input 4 edge signals KSO KS3 Quasiinterrupt input with falling edge 29 32 P6 0 P6 3 Input detection I O CPU clock output 23 2 2 Input I O 2 4 8 or 16 kHz frequency output for 24 P2 3 Input buzzer sound with 4 19 MHz main system clock or 32 768 kHz subsystem clock Xn XOUT Crystal ceramic or RC oscillator pins for 12 11 main system clock For external clock input use Xy and input Xs reverse phase to XTin Crystal oscillator pins for subsystem 14 15 clock For external clock input use XT i and input 5 reverse phase to XT our Me s sese TEST Test signal input must be connected to cT Vss NOTE Pull up resistors for all ports automatically disabled if they are configured to output mode 1 6 ELECTRONES S3C72N2 C72N4 P72N4 PIN CIRCUIT DIAGRAMS P CHANNEL N CHNNEL Figure 1 3 Pin Circuit TypeA PULL UP RESISTOR I RESISTOR P CHANNEL lt E SCHMITT TRIGGER Figure 1
192. ogram Bit 6 of address 0000H in program memory is transferred to the ERB memory is transferred to the ERB flag and bit 7 of the address to the flag and bit 7 of the address to the EMB flag EMB flag Stack pointer SP Undefined Undefined Data Memory RAM Working registers E A L H X W Z Y Values retained Undefined General purpose registers Values retained Undefined Bank selection registers SMB SRB BEES ONE BSC register BSCO BSC3 Clocks Power control register PCON Clock output mode register CLMOD System clock control reg SCMOD Interrupt request flags IRQx Interrupt enable flags IEX Interrupt priority IPR Interrupt master enable flag INTO mode register IMODO INT1 mode register IMOD1 INT2 mode register IMOD2 ELECTRONICS N 53C72N2 C72N4 P72NA RESET Table 9 1 Hardware Register Values After RESET Continued Hardware Component If RESET Occurs During If RESET Occurs During or Subcomponent Power Down Mode Normal Operation Ports Q O Output buffers Output latches Port mode flags PM Pull up resistor mode reg PUMOD Basic Timer Count register BCNT Undefined Undefined Timer Counter 0 Count registers TCNT0 Reference registers TREF0 Mode registers TMOD0 Output enable flags TOE0 FF FF Watchdog Timer WDT mode register WDMOD clear WDTCF 5H gt 5 Watch Time
193. ollowing method describes how to configure I O port pins to reduce power consumption during power down modes stop idle Condition 1 If the microcontroller is not configured to an external device 1 2 Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to Vpp or levels in order to check the current input option Reason If the input level of a port pin is set to Ves when a pull up resistor is enabled it will draw unnecessarily large current Condition 2 If the microcontroller is configured to an external device and the external device s Vpp source is 8 6 turned off in power down mode Connect unused port pins according to the information in Table 8 2 Disable pull up resistors for input pins configured to Vpp or Ves levels in order to check the current input option Reason If the input level of a port pin is set to Vss when a pull up resistor is enabled it will draw unnecessarily large current Disable the pull up resistors of input pins connected to the external devi ce by making the necessary modifications to the PUMOD register Configure the output pins that are connected to the external device to low level Reason When the external device s Vpp source is turned off and if the microcontroller s output pins are set to high level Vpp 0 7 V is supplied to the Vpp of the external device through its input pin This causes the device to o
194. ons Full Register Name Page Number AA WINO MEM TEN MEA 24 ANG SKID M 26 LOG EU RE ES 28 OE dH er LP 29 BIERO OTS ee cee ue P nce t 31 BILOG enor 33 DT MT tina 35 BIUTeSt and Skip False Lumu ian 37 Bit Test and TUS t RS 39 Bit Test and Skip on True Clear u u ul uuu 2 k a eani 41 EX CUS IVS OR Se T u uu TR 43 Calli 45 Call Procedure I ER 46 Complement Flag ux u u a URGE d UA UE Qa D 47 Complement Accumulator 48 Compare and aaa 49 Decrement and Skip on 50 use SUN EU EUR DEN 51 T X T 52 Idle OSL ANON stearate 5 INCFEMENT and SKIN VOM 54 MLS IUD k mE DOCU 95 56 JUMP 57 Jump Relative Very esie ou domat 58 xxiii List of Instruction Descripti
195. ons Continued Instruction Full Register Name Page Mnemonic Number LD onun MN TER RT ER 60 LDB LED 64 LDC Code Byle TP 66 LDD Load Data Memory and Decrement 68 LDI Load Data Memory and Increment 69 NOP 1 70 m TE 71 T 72 PUSH e RR 73 PASSE MEI 74 REF Relerence 222 225 c 75 Fron SUDFOULING 78 Rotate Accumulator Right Through Carry 79 SBC OAN Y C 80 SBS d HNIC 82 SCF 83 SMB Select Memory BGD uu u Out aset 84 Oelect HegiSIer BANK uuu Marea en HU 85 SRET Return From Subroutine and Skip 86 STOP SIOP OD Sra EL a E 87 VENT Load ENB ERB Vector ACCESS uro L Goes tin 88 XCH Exchange or EA with Nibble or 90 XCHD Exchange and Decremoellla25 u uuu cdd d anlar SOUL LI UE 91 XCHI Excharige and Ictermielit Doce iU ub SuSE 92 XOR kogical
196. own mode is generated Table 7 6 IMOD2 Register Bit Settings Effect of IMOD2 Settings Select rising edge at INT2 pin Select falling edge at KS2 KS3 Select falling edge at KS0 KS3 Co r 7 10 ELECTRONICS S3C72N2 C72N4 P72N4 INTERRUPTS Rising Edge Detection Circuit P6 2 KS2 P6 1 KS1 m 32 P6 0 KS0 Edge Detection Circuit Selector IMOD2 Figure 7 6 Circuit Diagram for 2 and KS0 KS3 Pins ELECTRONICS INTERRUPTS 53C72N2 C72N4 P72NA INTERRUPT FLAGS There are three types of interrupt flags interrupt request and interrupt enable flags that correspond to each interrupt the interrupt master enable flag which enables or disables all interrupt processing Interrupt Master Enable Flag IME The interrupt master enable flag IME enables or disables all interrupt processing Therefore even when an IRQx flag 5 set and its corresponding IEx flag is enabled the interrupt service routine is not executed until the IME flag is set to logic one The IME flag is located in the IPR register IPR 3 It can be directly be manipulated by El and DI instructions regardless of the current value of the enable memory bank flag EMB FB2H IPR2 IPRo Effect of Bit Settings Inhibit all interrupts Allow all interrupts Interrupt Enable Flags IEx IEx flags when set to logical one enable specific interrupt requests to be serviced When the interrupt request flag is s
197. own mode will be released by an interrupt request signal when the interrupt enable flag has been set In such cases the interrupt routine will not be executed since IME 0 ELECTRONICS 7 2 53C72N2 C72N4 P72NA INTERRUPTS Interrupt is generated INT xx Request flag IRQx lt 1 149 Retains value until 1 YES 4 Generates the corresponding vector interrupt and releases power down mode gt Retains value until IME 1 Retains until interrupt service routine is completed Y 151 0 0 1 151 0 1 0 Stores the contents of PC and PSW in stack area set PC contents to corresponding vector address Are both interrupt sources of shared vector address used NO IRQx flag value remains 1 Reset corresponding IRQx flag Jump to interrupt start address Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ instruction Figure 7 1 Interrupt Execution Flowchart ELECTRONICS 7 3 INTERRUPTS 53C72N2 C72N4 P72NA V V Y IE2 IEW IETO IE1 IEB T INTW NENNEN INT2 0 1 4 TOR KS0 KS30 POWER DOWN o RELEASE INTERRUPT CONTROL 5 NOISE FILTERING CIRCUIT EDGE DETECTION CIRCUIT VECTOR INTERRUPT GENERATOR Figure 7 2 Interrupt Control Circuit Diagram ELECTRONICS 7 4 53C72N2 C72N4 P72NA IN
198. perate at the level Vpp 0 7 V In this case total current consumption would not be reduced Determine the correct output pin state necessary to block current pass in according with the external transistors PNP NPN ELECTRONICS 53C72N2 C72N4 P72NA POWER DOWN RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption please configure unused pins according to the guidelines described in Table 8 2 Table 8 2 Unused Pin Connections for Reducing Power Consumption Pin Share Pin Names Recommended Connection P1 0 INTO Connect to Vpp 1 P1 1 INT1 P1 2 INT2 P1 3 TCLO P2 0 TCLOO Input mode Connect to Vpp P2 1 Output mode No connection P2 2 CLO P2 3 BUZ P3 2 P3 3 Input mode Connect to P3 1 LCDSY Output mode No connection P3 0 LCDCK SEGO SEG23 No connection COMO COM3 AL Connect XT to Ves and set SCMOD 2 to 1 In a Connect to Vss NOTES 1 Digital mode at P1 0 and P1 1 2 Used as segment ELECTRONICS 8 7 POWER DOWN 8 8 NOTES 53C72N2 C72N4 P72NA ELECTRONICS 53C72N2 C72N4 P72NA RESET RESET OVERVIEW When a RESET signal is input during normal operation or power down mode a hardware reset operation is initiated and the CPU enters idle mode Then when the standard oscillation stabilization interval of 31 3 ms at 4 19 MHz has elapsed normal system operation resumes Regardless of when the RESET occurs during normal operating mode
199. ption Chip initialization Logic power supply Vpp should be tied to 5 V during programming Table 15 2 Comparison of S3P72N4 and S3C72N2 C72N4 Features Characteristic 5 72 4 S3C72N2 C72N4 Program Memory 4 Kbyte EPROM 2 K 4 Kbyte mask ROM Operating Voltage V pp 2 0V to 5 5 4 19 MHz 2 0V to 5 5 4 19 MHz 1 8 V to 55 V at 3 MHz 1 8 V to 5 5 V at 3 MHz OTP Programming Mode 5 V Vpp TEST 12 5 V Pin Configuration 64 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the S8P72N4 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 15 3 below Table 15 3 Operating Mode Selection Criteria 15 0 OOH 0 jEPROMpogam 0 EPROM read protection NOTE 0 means low level 1 means high level 7 ELECTRONICS 15 3 S3P72N4 OTP 53 72 2 72 4 72 4 Table 15 4 D C Electrical Characteristics 40 to 85 1 8 V to 5 5 V Input high Vig All input pins except those 0 7 Vpp Vpp V voltage specified below for Vio 2 Your and XT v Yoo 9 Na Output high Vpp 4 5 to 5 5V V voltage lou 1mA Ports 2 3 6 and BIAS 4 5 to 55V Vpp 2 0
200. quency 4 8 64 Figure 15 2 Standard Operating Voltage Range ELECTRONICS 15 7 53C72N2 C72N4 P72NA S3P72N4 OTP a 4 5 3 VDD Bn E 3 500 div NEAL AL TA LI Figure 15 3 Port 2 lo vs Curve ELECTRONICS 15 8 S3C72N2 C72N4 P72N4 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S3C7 53 9 S3C8 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung A
201. r Watch timer mode register WMOD O LCD Driver Controller ELECTRONICS 9 RESET 9 4 NOTES 53C72N2 C72N4 P72NA ELECTRONICS 53C72N2 C72N4 P72NA PORTS PORTS OVERVIEW The S8C72N2 C72N4 has 5 ports There are total of 4 input pins 8 output pins and 12 configurable pins for a maximum number of 24 pins Pin addresses for all ports are mapped to bank 15 of the RAM The contents of port pin latches can be read written or tested at the corresponding address using bit manipulation instructions Port Mode Flags Port mode flags PM are used to configure I O ports to input or output mode by setting or clearing the corresponding buffer Pull Up Resistor Mode Register PUMOD The pull up mode registers PUMOD are used to assign internal pull up resistors by software to specific ports When a configurable port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting ELECTRONICS 10 1 PORTS 72 2 72 4 72 4 Table 10 1 I O Port Overview 1 0 1 3 4 bit input port 1 bit and 4 bit read and test is possible 4 bit pull up resistors are software assignable 2 0 2 3 FF2H 4 bit I O port 1 bit and 4 bit read write and test is possible 4 bit pull up resistors are software assignable 3
202. r 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 12 1 12 2 12 3 12 4 12 5 13 1 13 2 13 3 13 4 13 5 13 6 13 7 15 1 15 2 15 3 15 4 16 1 16 2 16 3 16 4 S3C72N2 C72N4 P72N4 List of Tables Title Basic Timer Register nemen Basic Timer Mode Register BMOD Organization Watchdog Timer Interval eese FOO REg ler OVerVIGW aet sit TMODO Settings for TCLO Edge Detection TCO Mode Register TMODO Organization TMODO 6 TMODO 5 and TMODO 4 Bit Settings Watch Timer Mode Register WMOD Organization Common Signal Pins Used per Duty Cycle LCD Control Register Organization LCON EMOD 3 Bit SelllngS yino iei ebbe anui dtc ua demde LCD Mode Register Organization LCD Clock Signal LCDCK Frame Frequency and LCD sync Signal LCDSY Absolute Maximi RAUNG cultibus Dune mE Electrical usto a a a Main System Clock Oscillator Characteristics
203. r 64 and a subsystem clock frequencies can only be divided by 4 By manipulating PCON bits 1 and O you select one of the following frequencies as CPU clock fx 4 fxt 4 fx 8 fx 64 Using a Subsystem Clock If a subsystem clock is being used as the selected system clock the idle power down mode can be initiated by executing an IDLE instruction The subsystem clock be stopped by setting SCMOD 2 to 1 The watch timer buzzer and LCD display operate normally with a subsystem clock source since they operate at very slow speeds 122 us at 32 768 kHz and with very low power consumption 6 2 ELECTRONICS S3C72N2 C72N4 P72N4 OSCILLATOR CIRCUITS Watch Timer Sub LCD Controller system Oscillator Main system Oscillator Circuit 1 8 1 4096 2 Basic Timer Oscillator stop Frequenc Timer Counter y Watch Timer Dividing LCD Controller Clock Output Circuit 1 2 1 16 5 12 16 fxt Yf Y I I I I I I I I I gt I I l gt Selector CPU clock CPU stop signal By IDLE or STOP instruction lt Watt release signal Oscillator Control Internal RESET signal Circuit 31 Power down release PCON 3 2 Clear fx Main system clock fxt Sub system clock fxx System clock Figure 6 1 Clock Circuit Diagram ELECTRONICS 6 3 OSCILLATOR CIRCUITS 53 72 2 72 4 72 4 MAIN SYSTEM OSCILLATOR CIRCUITS SUBSY
204. ract indirect data memory from A with carry Subtract register pair RR from EA with carry Subtract EA from register pair RRb with carry Subtract indirect data memory from A skip on borrow Subtract register pair RR from EA skip on borrow Subtract EA from register pair RRb skip on borrow Decrement register R skip on borrow Decrement register pair RR skip on borrow Increment register R skip on carry Increment direct data memory skip on carry Increment indirect data memory skip on carry Increment register pair RRb skip on carry ELECTRONICS 5 11 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Table 5 14 Bit Manipulation Instructions High Level Summary BIST Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set 2 24 9 memb L H DA b BISF DA b Test specified memory bit and skip if bit equals 0 mema b memb L H DA b BISTZ Test specified bit skip and clear if memory bit is set memb L H DA b BITS DA b mema b memb L H DA b BITR DA b mema b memb L H DA b oet specified memory bit Clear specified memory bit to logic zero BAND Logical AND carry flag with specified memory bit C memb L C H DA b BOR C mema b Logical OR carry with specified memory bit C memb L C H DA b BXOR Exclusive OR carry with specified memory bit C memb L C H DA b carry bit to a specified indirect memory bit Load specified indirect memory bit to carry bit
205. register E LD HL 30H HL lt 30H LD A HL 4H LD HL 40H HL lt 40H LD EA HL A lt OAH E lt LD HL A RAM 40H OAH ELECTRONICS 5 61 SAM47 INSTRUCTION SET S3C72N2 C72N4 P72N4 L D Load LD Continued Examples 2 If an instruction such as LD LD LD HL imm is written more than two times in succession only the first LD is executed the next instructions are treated as NOPs are two examples of this redundancy effect LD LD LD LD LD LD LD LD LD EA 2H A 3H 23H A HL 10H HL 20H A 3H 35 HL A gt A lt 23H 1H gt D HL 10H gt A lt 10H The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes Instruction LD LD LD LD LD LD LD LD 5 62 A im A RRa A DA A Ra Ra im Operation Description and Guidelines Since the redundancy effect occurs with instructions like LD EA imm if this instruction is used consecutively the second and additional instructions of the same type will be treated like NOPs Load the data memory contents pointed to by 8 bit RRa register pairs HL WX WL to the A register Load direct data memory contents to the A register Load 4 bit register Ra E L
206. ress Then if necessary you can modify the enable flags during the interrupt service routine When the interrupt service routine is returned to the main routine by the IRET instruction the original values saved in the stack are restored and the main program continues program execution with these values SOFTWARE GENERATED INTERRUPTS To generate an interrupt request from software the program manipulates the appropriate IRQx flag When the interrupt request flag value is set it is retained until all other conditions for the vectored interrupt have been met and the service routine can be initiated Multiple Interrupts By manipulating the two interrupt status flags ISO and IS1 you can control service routine initialization and thereby process multiple interrupts simultaneously If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction Power Down Mode Release An interrupt with the exception of INTO can be used to release power down mode stop or idle Interrupts for power down mode release are initiated by setting the corresponding interrupt enable flag Even if the IME flag is cleared to zero power d
207. riting application programs The I O map gives you the following information Register address Register name mnemonic for program addressing Bit values both addressable and non manipulable Read only write only or read and write addressability 1 bit 4 bit or 8 bit data manipulation characteristics ELECTRONICS 4 1 MEMORY S3C72N2 C72N4 P72N4 Table 4 1 Map for Memory Bank 15 Memory Bank 15 Lasse mee eno ene ont T oan 2 fA 2 e s 4 Locations F82H F84H are not mapped EL MEE BCNT 3 Yes FEH 6 7 Locations 8 are not mapped 8 NE Location F8FH is not mapped mw p pes per es e re Ls TCNTO 3 7 3 7 N Location F93H is not mapped 2 1 0 Yes TREFO F97H ww 3 2 mw s sw o K SE XE FB2H won 73 won w rem s 4 2 S3C72N2 C72N4 P72N4 MEMORY MAP Table 4 1 I O Map for Memory Bank 15 Continued aaaress Register eto oon nr w w mos mw ve ve No Location FB9H is not mapped v v ew mow ww ve ve Location FBBH is not mapped re wo v v ee maw ve No Location FBDH i
208. rrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung s S3C7 series microcontrollers The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM57 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code OBJ file by HEX2ROM the value is filled into the unused ROM area upto the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S3C7 series microcontrollers All required target system cables and adapters are included with the device specific target board OTPs One time programmable microcontroller OTP for the S8C72N2 C72N4 microcontroller and O
209. rs can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM2465
210. rval setting write only TOEO Flag Controls timer counter O output 1 bit F92H 2 1 bit to the TCLOO pin write only Clocks 210 28 2 6 2 4 Comparator lock 5 e Selector TMODO 4 D h TMODO 2 TMODO 1 Inverted TMODO 0 Clear Set Clear TOLO lt __ IROTO P2 0 LATCH Figure 11 2 TCO Circuit Diagram ELECTRONICS 41 11 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 TCO ENABLE DISABLE PROCEDURE Enable Timer Counter 0 Set TMODO 2 to logic one Set the TCO interrupt enable flag IETO to logic one Set 0 3 to logic one IRQTO and are cleared to logic zero and timer counter operation starts Disable Timer Counter 0 Set TMODO 2 to logic zero Clock signal input to the counter register TCNTO is halted The current TCNTO value is retained and can be read if necessary 11 12 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS PROGRAMMABLE TIMER COUNTER FUNCTION Timer counter O can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency Its 8 bit TCO mode register TMODO is used to activate the timer counter and to select the clock frequency The reference register TREFO stores the value for the number of clock pulses to be generated between interrupt requests The counter register TCNTO counts th
211. s PIN ADDRESSING FOR OUTPUT PORT 8 The addresses for the port 8 1 bit output pin buffers are located in bank 1 of data memory instead of bank 15 To address port 8 output pins use the settings EMB 1 and SMB 1 The LCD mode register LMOD is used to control whether the pin address is used for LCD data output or for normal data output Table 10 5 LMOD 7 and LMOD 6 Setting for Port 8 Output Control LMOD 7 LMOD 6 LCD Output Segments 1 Bit Output Pins Le 06 Le 1 0 E E _ C Each address in RAM bank 1 corresponds to a 4 bit register location The LSB bit 0 of the register location is used as the port buffer for either LCD segment output or normal 1 bit data output Locations that are unused for LCD or port I O be used as normal data memory After a RESET the values contained in the port 8 output buffer are left undetermined Table 10 6 shows port 8 pin addresses and also the corresponding LCD segment names if the pins are used to output LCD segment data Pin addresses that are not used for LCD segment output can be used for normal 1 bit output Table 10 6 Port 8 Pin Addresses and LCD Segment Correspondence PB SEG25 8 5 SEG29 10 4 ELECTRONICS 53C72N2 C72N4 P72NA PORTS PORT 1 CIRCUIT DIAGRAM VDD INTO INT1 INT2 TCLO PUMOD 1 gt P1 0 1 1 5 1 2 Pis INTO 9 NOISE FILTER I EDGE P1 0 lt CLOCK SELECTOR 7
212. s If LMOD 3 1 COM and SEG output in display mode LCD display on NOTES 1 You manipulate LCON O when you try to turn ON OFF LCD display internally If you want to control LCD ON OFF or LCD contrast externally you should set the LCON O to 0 refer to chapter 12 if you need more information 2 Toselect the LCD bias you must properly configure both LCON 0 and the external LCD bias circuit connection 3 The register must be set to 0 ELECTRONICS 4 17 MEMORY S3C72N2 C72N4 P72N4 LCD Mode Register F8DH F8CH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W 8 8 8 8 1 8 8 8 8 Bit Addressing 7 6 LCD Output Segment and Pin Configuration Bits 9 4 NOTE Watch timer frequency fw is assumed to be 32 768KHz ELECTRONICS 4 18 S3C72N2 C72N4 P72N4 MEMORY MAP PCON Power Contro Register FB3H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 4 4 4 4 3 2 CPU Operating Mode Control Bits Enable normal CPU operating mode 1 Initiate stop power down mode ofo O 1 initiate ide power downmode II alo 1 0 CPU Clock Frequency Selection Bits If SCMOD 0 0 fx 64 if SCMOD 0 1 fxt 4 1 EB If SCMOD 0 0 fx 8 if SCMOD 0 1 fxt 4 NOTE fx is the main system clock fxt is the subsystem clock If SCMOD 0 0 fx 4 if 5 1 fxt 4 ELECTRONICS 4 19
213. s normal speed WMOD 1 0 the watch timer generates an interrupt request every 0 5 seconds High speed mode is useful for timing events for program debugging sequences Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD 3 If WMOD 3 is 1 the input level at the XT pin is high if WMOD 3 is 0 the input level at the XT pin is low ELECTRONICS 11 23 TIMERS and TIMER COUNTERS 53 72 2 72 4 72 4 Enable DISABLE Selector Circuit noie pu 2 fw 214 2Hz Frequency Dividing Circuit _ Clock Selector 32 768 kHz fw 29 4096 Hz fx Main system clock fxt Subsystem clock fxt fxx 128 fw Watch timer frequency fxx 2 System clock Figure 11 4 Watch Timer Circuit Diagram 11 24 ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS WATCH TIMER MODE REGISTER WMOD The watch timer mode register WMOD is used to select specific watch timer operations It is 8 bit write only addressable An exception is WMOD bit 3 the XT input level control bit which is 1 bit read only addressable A RESET automatically sets WMOD 3 to the current input level of the subsystem clock XT high if logic one low if logic zero and all other WMOD bits to logic zero F88H WMOD 3 WMOD2 WMOD 1 WMOD O F89H WMOD 7 ups WMOD 5 WMOD 4 In summary WMOD settings control the following watch tim
214. s not mapped v v m Fw Be 3 2 a 0 a 2 o a 2 1 o rw awo s v w No ves Locations FD1H FDBH not mapped peel ov Locations FDEH FE7H are not mapped mer Locations are not mapped fo fo fo Locations FEEH FFOH are not mapped 2 n ve No 3 2 a 9 Ye Yes No mm Poa 3 2 9 nw Ye Ye No Locations are not mapped me pone 2 o sw ve No Locations are not mapped NOTES 1 Bit 3 inthe WMOD register is read only 2 flag can be read or written by specific bit manipulation instructions only The LCON 3 register must be set to 0 4 means that the value is undetermined ELECTRONICS 4 3 MEMORY S3C72N2 C72N4 P72N4 REGISTER DESCRIPTIONS In this section register descriptions are presented in a consistent format to familiarize you with the memory mapped I O locations in bank 15 of the RAM Figure 4 1 describes features of the register description format Register descriptions are arranged in alphabetical order Programmers can use this section as a quick reference source when writing application programs Counter registers and referen
215. sFlagsS Wii 2C T I 10 3 Pull Up Resistor Mode Register emen mnn nenne nnne nnne ni 10 3 Pin Adgressingd dor OBUtDIt FON B uyu Ca tiae un u T RUN su 10 4 ET ICHIED 212 DNE S So RP Re re Maen MM 10 5 FOR gi ii ou uu SEI D EP LOMA CDU 10 6 Fols SANG O Ci CHI DISSE SITE uu cada 10 7 53C72N2 C72N4 P72NA vii Table of Contents continued Chapter 11 Timers and Timer Counters VE V OW dI Leu d Leu TL Mp E UE 11 1 Basie Timer B M T M M 11 2 c A 11 2 Basic Timer Mode Register 11 4 Basie limer Counter BENT 11 5 Basic Timer Operation 11 5 Watchdog Timer Mode Register 11 7 Watchdog Timer Counter 11 7 Watchdog Timer Counter Clear 11 7 S Bit Tmercoumer RIO 11 9
216. stack ox SB Pop SMB and SRB values from stack 2 2 Description contents of the RAM location addressed by the stack pointer is read and the SP is incremented by two The value read is then transferred to the variable indicated by the destination operand Binary Code Operation Notation 1 r2 rl RR lt SP lt SP 1 SP lt SP 2 1 1 1 1 SRB SP SMB 5 1 lt SP 2 Example The SP value is equal to OEDH and RAM locations OEFH through OEDH contain the values 2H 3H and 4H respectively The instruction POP HL leaves the stack pointer set to OEFH and the data pointer pair HL set to 34H 5 72 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET PUSH push onto Stack PUSH src Operation Operation Summary RR o Push register pair onto stack i is SB Push SMB and SRB values onto stack 2 2 Description The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer thereby adding a new element to the top of the stack A Code Operation Notation SP 1 lt RR SP 2 lt RRL SP lt SP 2 1 lt SMB 5 2 lt SRB Hr lt SP 2 Example As an interrupt service routine begins the stack pointer contains the value OFAH and the data pointer register pair HL contains the value 20H The instruction PUSH HL leaves the stack pointer set to OF8H and
217. ster HL WX YZ to the EA register H W and Y register values are loaded into the E register and the L X and Z values into the A register LD HL A Load A register contents to data memory location pointed to by the 8 bit HL register value LD DA EA Load the A register contents to direct data memory and the E register contents to the next direct data memory location The DA value must be an even number If it is an odd number the LSB of the DA value is recognized as logic zero an even number and is not replaced with the true value LD RRb EA Load contents of EA to the 8 bit RRb register HL WX YZ The E register is loaded into the H W and Y register and the A register into the L X and Z register LD HL EA Load the A register to data memory location pointed to by the 8 bit HL register and the E register contents to the next location HL 1 The contents of the register must be an even number If the number is odd the LSB of the L register 5 recognized as logic zero an even number and is not replaced with the true value For example LD HL 36H loads immediate 36H to register HL the instruction HL EA loads the contents of A into address 36H and the contents of E into address 37H ELECTRONICS 5 63 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 LDB Load LDB LDB Operation Description 5 64 dst src b dst b src Open Operation Summary me oves Load carry bit to a specifi
218. subsystem clock main system clock oscillation is stopped by setting SCMOD 3 SCMOD 0 SCMOD 2 and SCMOD 3 cannot be simultaneously modified Sub oscillation goes into stop mode only by SCMOD 2 PCON which revokes stop mode cannot stop the sub oscillation The stop of sub oscillation is released only by reset RESET clears all SCMOD values to logic zero selecting the main system clock fx as the CPU clock and starting clock oscillation The reset value of the SCMOD is O SCMOD 3 SCMOD 2 SCMOD 0 bits can be manipulated by 1 bit write instructions In other words SCMOD 0 SCMOD 2 and SCMOD 3 cannot be modified simultaneously by a 4 bit write Bit 1 is always logic zero A subsystem clock fxt be selected as the system clock by manipulating the SCMOD 3 and SCMOD O bit settings If SCMOD 3 0 and SCMOD 0 1 the subsystem clock is selected and main system clock oscillation continues If SCMOD 3 1 and SCMOD 0 1 fxt is selected but main system clock oscillation stops If you have selected fx as the CPU clock setting SCMOD 3 to 1 will stop main system clock oscillation But this mode must not be used To stop main system clock oscillation safely main oscillation clock should be stopped only by a STOP instruction in main system clock mode Table 6 3 System Clock Mode Register SCMOD Organization SCMOD Register Bit Settings Resulting Clock Selection SCMOD 3 SCMOD 2 SCMOD 0 fx Oscillation Oscillation CPU Clock no
219. t 13 10 53 72 2 72 4 72 4 ELECTRICAL DATA 0 8 VDD wn MEASUREMENT POINTS 0 2 4 Figure 13 4 Timing Measurement Points Except for Xj and Figure 13 5 Clock Timing Measurement at Xin Figure 13 6 Clock Timing Measurement at XT in ELECTRONICS 13 11 ELECTRICAL DATA S3C72N2 C72N4 P72N4 Figure 13 7 TCLO Timing RSL RESET 0 2 Figure 13 8 Input Timing for RESET Signal INTO 1 2 4 KSO to KS3 Figure 13 9 Input Timing for External Interrupts and Quasi Interrupts 13 12 ELECTRONICS 53C72N2 C72N4 P72NA MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C72N2 C72N4 microcontroller is available in 64 pin QFP package Samsung 64 QFP 1420F Package dimensions are shown in Figure 14 1 23 90 0 3 0 15 1005 64 QFP 1420F 10 10 MAX 17 90 0 3 lt q 005 4 00 _ 0 0 15 FTA gt 40 90 0 20 0 20 FNEN x NOTE Dimensions are in millimeters Figure 14 1 64 QFP 1420F Package Dimensions ELECTRONICS MECHANICAL DATA 53C72N2 C72N4 P72NA NOTES 53C72N2 C72N4 P72NA S3P72N4 OTP S3P72N4 OTP OVERVIEW The S8P72N4 single chip CMOS microcontroller is the OTP One Time Programmable version of the 53 72 2 72 4 microcontroller It has an on chip EPROM instead of masked ROM The EPROM is accessed by a serial data format The S3P72N4 is fully compati
220. t mode flags to logical zero automatically configuring the corresponding ports to input mode Table 10 3 Port Mode Group Flags 8 FE9H PMG2 FECH FEDH 2 PROGRAMMING Configuring I O Ports to Input or Output Configure ports 3 and 6 as an output port BITS EMB SMB 15 LD EA 0FFH LD PMG1 EA and P6 lt Output PULL UP RESISTOR MODE REGISTER PUMOD The pull up resistor mode register PUMOD is used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting PUMOD is addressable by 8 bit write instructions only RESET clears PUMOD register values to logic zero automatically disconnecting all software assignable port pull up resistors Table 10 4 Pull Up Resistor Mode Register PUMOD Organization PUMODID Address Bto PUMOD FDCH PUR3 PUR PUR1 NOTE When bit 1 a pull up resistor is assigned to the corresponding port PUR3 for port PUR2 for port 2 and so on ELECTRONICS 10 3 PORTS 53C72N2 C72N4 P72NA 9 PROGRAMMING Enabling and Disabling I O Port Pull Up Resistors P2 and P3 are enabled to have pull up resistors BITS EMB SMB 15 LD LD PUMOD EA Enable P2 and P3 to have pull up resistor
221. ta memory bank 0 During an interrupt or a subroutine the PC value and the PSW are saved to the stack area When the routine has completed the stack pointer is referenced to restore the PC and PSW and the next instruction is executed The SP can address stack registers in bank 0 addresses 000 regardless of the current value of the enable memory bank EMB flag and the select memory bank SMB flag Although general purpose register areas can be used for stack operations be careful to avoid data loss due to simultaneous use of the same register s Since the reset value of the stack pointer is not defined in firmware we recommend that you initialize the stack pointer by program code to location This sets the first register of the stack area to OFFH NOTE A subroutine call occupies six nibbles in the stack an interrupt requires six When subroutine nesting or interrupt routines are used continuously the stack area should be set in accordance with the maximum number of subroutine levels To do this estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly PROGRAMMING Initializing the Stack Pointer To initialize the stack pointer SP 1 When 1 SMB 15 Select memory bank 15 LD EA 00H Bit 0 of SP is always cleared to 0 LD SP EA Stack area initial address OFFH lt SP 1 2 When EMB 0 LD EA 00H LD SP EA
222. te NOTE CPU clock is selected by register settings ELECTRONICS 6 7 OSCILLATOR CIRCUITS S3C72N2 C72N4 P72N4 Table 6 4 Main Sub Oscillation Stop Mode Main oscillator runs Sub oscillator runs stops System clock is the Main Oscillation STOP Mode main oscillation clock Main oscillator runs Sub oscillator runs System clock is the sub oscillation clock Sub Main oscillator runs oscillation Sub oscillator runs STOP Mode System clock is the main oscillation clock Main oscillator runs stops Sub oscillator runs System clock is the sub oscillation clock NOTES 1 This mode must not be used STOP instruction Main oscillator stops CPU is in idle mode Sub oscillator still runs stops Set SCMOD 3 to 1 1 Main oscillator stops halting the CPU operation Sub oscillator still runs stops STOP instruction 1 Main oscillator stops CPU is in idle mode Sub oscillator still runs oet SCMOD 3 to 1 Main oscillator stops CPU still operates Sub oscillator still runs Set SCMOD 2 to 1 Main oscillator still runs CPU operates Sub oscillator stops Set SCMOD 2 to 1 Main oscillator still runs stops Sub oscillator stops halting the CPU operation Interrupt and reset After releasing stop mode main oscillation starts and oscillation stabilization time is elapsed And then the CPU operates Oscillation stabilization
223. tect an inadvertent program loop that is system or program operation error For this purpose instruction that clears the watchdog timer BITS WDTCF within a given period should be executed at proper points in a program If an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows reset signal is generated and system is restarted with reset status An operation of watchdog timer is as follows Write some value except 5 to Watchdog Timer Mode register WDMOD Each time BCNT overflows an overflow signal is sent to the watchdog timer counter If WDTCNT overflows system reset will be generated ELECTRONICS 53 72 2 72 4 72 4 TIMERS and TIMER COUNTERS Table 11 1 Basic Timer Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value BMOD Control Controls the clock frequency mode 4 bit F85H 4 bit write only of the basic timer also the BMOD 3 1 bit oscillation stabilization interval after write only power down mode release or RESET BCNT Counter Counts clock pulses matching the 8 bit F86H F87H 8 bit read only u BMOD e setting ino WDMOD Control Controls Controls watchdog timer operation timer operation 8 F98H F99H F99H 8 bit write 8 bit write only ABH WDTCF Clear the watchdog timer s counter F9AH 3 1 bit write only NOTE means that the value is undetermined
224. the EMB flag initializing it automatically When a vectored interrupt is generated bit 7 of the respective vector address table is written to the EMB This automatically sets the EMB flag status for the interrupt service routine When the interrupt 5 serviced the EMB value is automatically saved to stack and then restored when the interrupt routine has completed At the beginning of a program the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction The EMB and ERB can be set or reset by bit manipulation instructions BITS BITR despite the current SMB setting PROGRAMMING Initializing the EMB and ERB Flags The following assembly instructions show how to initialize the EMB and ERB flag settings ORG 0000H ROM address assignment VENTO 1 0 RESET lt 1 ERB lt 0 branch RESET VENT1 0 1 INTB lt 0 ERB lt 1 branch INTB VENT2 0 1 INTO EMB 0 ERB 1 branch INTO VENT3 0 1 INT1 EMB 0 ERB 1 branch INT1 000AH ROM address assignment VENT5 0 1 INTTO EMB lt 0 ERB 1 branch INTTO RESET BITR EMB ELECTRONICS 3 3 ADDRESSING MODES 53 72 2 72 4 72 4 ENABLE MEMORY BANK SETTINGS 1 When the enable memory bank is to logic one you can address the data memory bank specified by the select memory bank SMB value 0 1 or 15 using 1 4 or 8 bit instructions You can use both d
225. the value 1H EA 02H were to be executed the jump would be to 0602H and address 30H would contain the value 2H ELECTRONICS 5 59 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 LD Load LD Operation Description 5 60 dst src Load contents of A to register Load 8 bit immediate data to register Load contents of A to direct data memory Load 4 bit immediate data to register DA EA Load contents of EA to data memory RRb EA Load contents of EA to register HL EA Load contents of EA to indirect data memory The contents of the source are loaded into the destination The source s contents are unaffected If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession only the first LD will be executed the other similar instructions that immediately follow the first LD will be treated like a NOP This is called the redundancy effect see examples below Binary Code Operation Notation A RRa Ra im d3 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET LD Load LD Continued Description 1 DA lt 1 lt CJEJEHEJERE 1 1 1 0 RRb lt EA lt Examples 1 RAM location 30H contains the value 4H The RAM location values are 40H 41H and OAH 3H respectively The following instruction sequence leaves the value 40H in point pair HL OAH in the accumulator and in RAM location 40H and 3H in
226. tial carrier BSC register Section Addressing Modes describes types of addressing supported by the SAMA instruction set direct indirect and bit manipulation and the addressing modes which are supported 1 bit 4 bit and 8 bit Numerous programming examples make the information practical and usable Section 4 Memory contains a detailed map of the addressable peripheral hardware registers in the memory mapped area of the RAM bank 15 Section 4 also contains detailed descriptions in standard format of the most commonly used hardware registers These easy to read register descriptions can be used as a quick reference source when writing programs Section 5 Instruction Set first introduces the basic features and conventions of the SAM4 instruction set Then two summary tables orient you to the individual instructions One table is a high level summary of the most important in formation about each instruction the other table is designed to give expert programmers a summary of binary code and instruction notation information The final part of Section 5 contains detailed descriptions of each instruction in a standard format Each instruction description includes one or more practical examples of how to use the instruction A basic familiarity with the information in Part will make it easier for you to understand the hardware descriptions in Part 1 If you are unfamiliar with the SAM4 product family and are reading this user
227. tion and specified 1 addressable bit number b peripherals Bank 15 SMB 15 mema b Direct bit is indicated by X FBOH FBFH Bank 15 150 151 addressable area and FFOH FFFH ERB IEx IRQx bit number b Pn n X FCOH FFFH Bank 15 memb L Indirect lower two bits of reg ister L as indicated by the up per 6 bits of RAM area memb and the upper two bits of register L Bao Indirect bit indicated by the lower four bits of the address 1 All 1 bit DA memory bank selection addressable and the H register identifier peripherals SMB 15 NOTE x not applicable 3 6 ELECTRONICS 53C72N2 C72N4 P72NA ADDRESSING MODES PROGRAMMING 1 Bit Addressing Modes 1 Bit Direct Addressing 1 I EMB 0 AFLAG EQU 34H 3 EQU 85H 3 CFLAG EQU OBAH O SMB 0 BITS AFLAG 34H 3 lt 1 BITS BFLAG F85H 3 lt 1 BIST CFLAG If FBAH O 1 skip BITS BFLAG Else if FBAH 0 0 F85H 3 BMOD 3 lt 1 BITS P3 0 FF3H 0 P3 0 1 2 1 AFLAG EQU 34H 3 EQU 85H 3 CFLAG EQU OBAH O SMB 0 BITS AFLAG 34H 3 1 BITS BFLAG 85H 3 lt 1 BIST CFLAG If OBAH O 1 skip BITS BFLAG Else if OBAH O 0 085H 3 lt 1 BITS P3 0 FF3H 0 P3 0 1 1 Bit Indirect Addressing 1 If EMB 0 AFLAG EQU 34H 3 EQU 85H 3 CFLAG EQU OBAH O SMB 0 LD lt 0BH BISTZ H CFLAG If OBAH O 1 OBAH O
228. truction is used ELECTRONICS 5 23 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 ADC ADC Operation Description Examples 5 24 Add With Carry dst src A HL Add indirect data memory to A with carry EA RR Add register pair RR to EA with carry RRb EA Add EA to register pair RRb with carry The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the carry flag is set otherwise the carry flag is cleared If ADC A HL is followed by an ADS A im instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This condition is valid only for ADC A HL instructions If an overflow occurs following an ADS A im instruction the next instruction will not be skipped tala EA lt EA 1 The extended accumulator contains value register pair HL the value and the carry flag is set to 1 SCF C lt 4 ADC EA lt 1H 6EH C lt 1 JPS XXX Jump to XXX no skip after ADC 2 If the extended accumulator contains the value register pair HL the value OAAH and the carry flag is cleared to O RCF C 0 ADC EA HL EA lt 0C
229. tructions are enabled the instruction DI sets the IME bit to logic zero disabling all interrupts ELECTRONICS 5 51 SAM47 INSTRUCTION SET 53 72 2 72 4 72 4 Enable Interrupts Description Bit 3 of the interrupt priority register IPR is to logic one This allows all interrupts to be serviced when they occur assuming they are enabled If an interrupt s status latch was previously enabled by an interrupt this interrupt can also be serviced Pin ins Example If the IME bit bit 3 of the IPR is logic zero e g all instructions are disabled the instruction sets the IME bit to logic one enabling all interrupts 5 52 ELECTRONICS S3C72N2 C72N4 P72N4 SAM47 INSTRUCTION SET L E Idle Operation IDLE Operation Description Example IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register PCON After an IDLE instruction has been executed peripheral hardware remains operative In application programs an IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three NOP instructions are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Binary Code Oper
230. umber 3 byte instructions such as JP or CALL may also be referenced using REF To reference these 3 byte instructions the 2 byte pseudo commands TJP and TCALL must be written in the reference The is not incremented when a instruction is executed After it executes the program s instruction execution sequence resumes at the address immediately following the REF instruction By using REF instructions to execute instructions larger than one byte as well as branches and subroutines you can reduce the program size To summarize the REF instruction can be used in three ways Using 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch address that is stored in the look up table Calling subroutines at any location by referencing a call address that is stored in the look up table If necessary a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence In addition the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions Two byte instructions can be referenced by using a REF instruction An exception is XCH A DA If the MSB value of the first 1 byte instruction in the reference area is 0 the instruction cannot be referenced by a REF instruction Therefore if you use REF to reference two 1 byte instructions stored in the re
231. xt 4 SCMOD 1101B 3 Stop mode VA 25 C 5 V 10 CPU fx 4 SCMOD 01008 1 D C electrical values for supply current Ipp to do not include current drawn through internal pull up resistors and through LCD voltage dividing resistors 2 Data includes the power consumption for sub system clock oscillation 3 When the system clock mode register SCMOD is set to 0100B the sub system clock oscillation stops The main system clock oscillation stops by the S TOP instruction ELECTRONICS 13 5 ELECTRICAL DATA S3C72N2 C72N4 P72N4 Table 13 3 Main System Clock Oscillator Characteristics Clock Parameter Test Condition Typ Configuration Ceramic Oscillation frequency Oscillator 1 Stabilization time 2 Stabilization occurs Crystal XIN Oscillation frequency Oscillator 1 when is equal to the minimum oscillator voltage range Stabilization time 2 Vpp 4 5 V to 5 5 V P External XIN Xy input frequency 1 0 4 Clock 83 3 input high and low level width RC m Frequency 1 Vpp 5 V Oscillator R 20 5 39 Vpp 3 V 1 Oscillation frequency and frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated 13 6 ELECTRONICS 53 7
232. zero IE2 INT2 Interrupt Enable Flag Disable INT2 interrupt requests at the INT2 pin 1 Enable INT2 interrupt requests at the INT2 pin IRQ2 INT2 Interrupt Request Flag Generate INT2 quasi interrupt This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2 Since INT2 is a quasi interrupt IRQ2 flag must be cleared by software ELECTRONICS 4 9 MEMORY S3C72N2 C72N4 P72N4 IRQB iNTB interrupt Enable Request Flags Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic zero IEB INTB Interrupt Enable Flag Disable INTB interrupt requests 1 Enable INTB interrupt requests IROB INTB Interrupt Request Flag Generate INTB interrupt This bit is set and cleared automatically by hardware when reference interval signal received from basic timer 4 10 S3C72N2 C72N4 P72N4 MEMORY MAP IRQTO Interrupt Enable Request Flags FBCH Bit 3 2 1 0 Identifier 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Always logic zero IETO INTTO Interrupt Enable Flag EN Disable INTTO interrupt requests Enable INTTO interrupt requests IRQTO INTTO Interrupt Request Flag Generate INTTO interrupt This bit is set and cleared automatically by hardware when contents of TCNTO and TRE

USER`S MANUAL

Contents

Download Pdf Manuals

Related Search

Related Contents