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1. AvnetAvenue Xilinx Spartan 8EEvaluation Kit User Manual T 3AVNE T electronics marketing A AvnetAvenue Table of Contents 1 0 Moo CUC TOM EEE EE EE EE S 4 1 1 PEN 4 1 2 FRU 4 1 3 BE S PPI CAIO EE E E E N E nenedeoeegneeeeces 5 1 4 Tel 6 2 0 NI E cu cc pene ces nee desis rence E E css ens esas E ee a E E A A am anne gato en A ee cine EE E A A 7 2 1 TT EN T 2 2 Connon SE 8 2 3 ee 10 2 4 PNAN 11 2 5 MEAN 11 2 6 JAN A E N E E A E AE E sigue aoe E E E scieecennetoouseeaosn ees 13 2 7 OC SSR EEE EEE EE 15 2 8 On board Display 2 Character Alphanumeric LED rrrronnnnrnnrnnnnnrnrrnnnnnevrrnnnnnennrnnnnnennnnnnnrennrnnnnrennnnnnnsrnnnnnssnennnnnsnsennnnnsnee 16 2 9 DP amp Pusm button STEG 16 2 10 2 EEE EE E E 17 2 11 METT e see nee pace cane E ected enedstae syedeet so S E E E E A 17 2 11 1 Pi 17 2 12 Communication SE gt 0 EE EE EE EE 18 2 12 1 Sp EEE RENEE ENE EE EE EE 18 2 12 2 EE EEE NER EEE cen secesusanesssieadeeeas 18 218 ORG 1191 10 10 EE EE EEE EEE EEE 20 2 14 PT NN 22 3 0 NT PP 22 3 1 ge ds ae o EEE EE EEE EEE EE EN NE 22 4 0 LEO PN foe cetes a cescengtetat ese E te veanetaquest E eben te lt atesaseqncudeemenneuesee eae E cece 23 Figures Figure 1 Virtex 4 FX Evaluation Board PICtUre cccccsssccccseeecceeseecseseecsaueeecsueeeeseeeeesaeeecsaueeeseeeessaueeeseaeeeeseaeeessaueeessueeeessaeeesssseesseaes 5 Figure 2 Spartan 3E Evaluation Board Picture ccccccccccsssesecceeeeccee2. All other brands are property of their respective owners Avnet Design Services Released Rev 1 0 08 09 2005 Literature ADS 005604 A AvnetAvenue Two momentary closure push buttons have been installed on the board and attached to the FPGA These buttons can be programmed by the user and are ideal for logic reset and similar functions Pull down resistors hold the signals low 0 until the switch closure pulls it high 1 Silkscreen Part Signal Name FPGA pin SWITCH PB1 SW2 SWITCH PB2 P66 Table 9 Push button FPGA Pin out 2 10 LEDs Eight discrete LEDs are installed on the board and can be used to display the status of the internal logic These LEDs are attached as shown below and are lit by forcing the associated FPGA I O pin to a logic 1 and are off when the pin is Low 0 These pins are shared with the General Purpose bus as indicated below LED Signal Name FPGA pin po S GENIO P9 D6 GENIOS P4 D8 GENIO7 P D9 GENIOS PTA Table 10 LED FPGA Pin out 2 11 Memory The Spartan 3E Evaluation Board is populated with a 4Mbit low voltage serial flash memory from ST Microelectronics This memory may be used to configure the SSE FPGA or to store user data 2 11 1 SPI Flash Manufacturer ST Microelectronics Part M25P40 VMN6P Attributes of the Serial Flash memory 4Mbit Up to 40MHz SPI compatible serial interface 2 7V to 3 6V operation Since the FPGA
3. and programming over USB These functions are not supported by Avnet on other platforms but source code is included as a reference for customers who want to add it The operation of the utility is described in section 2 5 of this manual Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Jof 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue 2 3 Creating a HEX file Configuration via SPI requires that a HEX file be generated from a working BIT configuration file Due to the time and complexity involved with creating this file and programming the SPI FLASH device it is recommended that the BIT file be tested prior to committing it to FLASH NOTE When creating the HEX file be sure to use a BIT which was generated with the startup clock option set for CCLK typically the default The screen shots that follow show the step by step procedures of creating a HEX file using iMPACT 7 1 This procedure may need to be modified when using a different version of the tool ps Immediately after opening IMPACT it is necessary to either select a preexisting Brovse project or create a new one This process assumes that a new project will be T Load most recent project file when iMPACT starts created The project can be saved after comp
4. of Avnet Inc All other brands are property of their respective owners Avnet Design Services 40f 23 Rev 1 0 08 09 2005 Released Literature 4 ADS 005604 A Avnet Avenue br ed cg or df 9 US co gt hd JP1 JP4 HODEDALDELADDEEAELDLAAELADATALT KJENN LMS o ANE o EN c HI ER 100 IS O MHz J6 JP8 JPY SW3 LETT S JP5 ici Figure 1 Virtex 4 FX Evaluation Board Picture 1 3 Demo Applications The Spartan 3E Evaluation Kit from Avnet Design Services comes with example projects designed in Xilinx ISE The example projects help the user get started by leveraging already tested and functional designs The example projects that will be discussed in detail later in this document are listed below Note There may be additional demos which were developed after the printing of this document For additional demo applications please contact your local Avnet FAE Segment Test Project Display count value on segment display Provide test message over RS232 Source Code Included Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 5of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 AvnetAvenue 1 4 The following table lists the evaluation kit part numbers and available so
5. pinout A straight through serial cable should be used to plug J3 into a standard PC serial port male DB9 Signal Name FPGA pin Xevr pin Note from FPGA perspective Transmit RS232_TX1 Out to DB9 2 Receive RS232 RX1 In from DB9 3 CTS RS232 CTS Out to DB9 8 RTS RS232_ RTS In from DB9 7 Table 12 RS 232 FPGA Pin out Signal Name DB9J3 Xcvr pin TX 2 17 Table 13 RS 232 Connector Pin out 2 122 USB 2 0 Manufacturer Cypress Part CY7C68013 100AC The Spartan 3E Evaluation Board includes a Cypress EZ USB FX2 USB Microcontroller part number CY7C68013 100AC The EZ USB FX2 device is a single chip integrated USB 2 0 transceiver Serial Interface Engine SIE and 8051 microcontroller This device supports full speed 12 Mbps and high speed 480 Mbps modes but does not support low speed mode 1 5 Mbps The FX2 interface to the Spartan 3E FPGA is a programmable state machine that supports 8 or 16 bit parallel data transfers This interface is called the General Programmable Interface GPIF The GPIF is controlled by Waveform Descriptors that are created with the Cypress GPIFTool utility and downloaded to the FX2 over the USB cable The GPIF descriptors are stored in internal RAM and are loaded by the firmware during initialization The GPIF interface is made up of the signals in the following table which are connected to Spartan 3E FPGA Some of the additional GPIF pins are connected to the confi
6. 204 A AvnetAvenue 1 0 Introduction The purpose of this manual is to describe the functionality and contents of the Spartan 3E Evaluation Kit from Avnet Design Services This document includes instructions for operating the board descriptions of the hardware features and explanations of the example projects 1 1 Description The Spartan 3E Evaluation Kit provides a platform for engineers designing with the Xilinx Spartan 3E FPGA The board provides the necessary hardware to not only evaluate the features of the Spartan 3E but also to implement user applications with a basic set of peripherals Example projects are provided to help the user understand the design tool flow and leverage from known functional designs 1 2 Features FPGA Xilinx XC3S100E TQ144 Spartan 3E FPGA Board I O Connectors 50 pin header for user I O 8 discrete LEDs 2 push buttons 4 position DIP switch Dual character aloha numeric display Memory ST Microelectronics SPI serial FLASH Communication USB 2 0 RS 232 serial port Power USB or 5V wall mount not included Texas Instruments TPS75003 triple supply Configuration SPI serial FLASH to FPGA USB download utility Support for Xilinx Parallel Cable IV Fly wire support for and Xilinx or compatible cable Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks
7. 5604 A AvnetAvenue The following instructions and screen shot are an overview of the procedure They assume that the driver and utility version 3 0 or later has been properly installed Consult the USB Utility User Manual as needed for this procedure ra ca Ne Connect a USB cable from the host PC to the Spartan3E Eval board Note The board will draw it s power from the USB port so there is no need to apply power to the optional barrel power input Wait It will take a few seconds to scan the USB bus and show the available Avnet Boards Select Spartan 3E Eval in the Board drop down menu Select the desired mode from the Mode drop down menu Browse to or enter a filename appropriate for the selected mode a ConfigFPGA requires a BIT file b Write SPI Configuration requires a HEX file and must start at address 00000 For other options reference the Utility User Guide Click the Execute button the operation doesn t start until this button is selected Wait After a few seconds a progress bar will track the progress A window will pop up when the process completes or if it errors out Available Devices xX Device Spartan 3E Eval Board 1006 FT Device f Device f FT Device 3 f Device 4 fed iy Device 5 fed ty f Device E fed ty Device 7 fed cy f Device 8 hl FT Device 5 f Figure 7 Select Target Board Copyright O 2005 Avnet Inc AVNET and the AV logo
8. 6 is given in the following table J6 pin NE name SPI Function FPGA Pin 4 VOG 8SM M G 1 o a GE FPGA CS O 3 MISO 5 FPGA CCLK FPGA_MOSI Table 5 J6 Header SPI Pin out This method of programming is allowed but it is not supported by Avnet Programming with FPGA Since the configuration pins of the FPGA are available as I O the user could create IP to read write the SPI Flash At the time of this publication an example project for doing so was not available The task of creating such a project is left to the user Check with your local Avnet FAE to see if such projects or cores are currently available through Avnet or Xilinx 2 5 Avnet USB Utility The Avnet USB Utility may be used to configure the FPGA and program the SPI Flash memory as mentioned in the previous section This section will describe the basic operation of the Avnet USB utility more detailed information is available in the utility user manual Whether configuring the FPGA or programming the FLASH make sure that the BIT file is configured with the startup clock set to CCLK and that there is a shunt on JP4 enabling the USB controller to drive the CCLK signal Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services ll of 23 Rev 10 08 09 2005 Released Literature ADS 00
9. INT4 USBINT4 1 JSPQPIN sd INTSt gt USBINT5 JSPYPINZ sd TIMER2 USB TIMER gt JPQ PING gt TIMER1 USB TIMER gt JPS PINT Cs TIMERO USB TIMERO gt DPS PINS gt PEO USBPEO JSPQPINE o y o PEH USBPEL JSPQPIN y PER USBPE2 O OJPBPNS Y PES USBPES O OJPBPN8 se Cs PE4 USB PE4 JP3 PIN10 pes USB PES vPaPN2 PEG USBPE6 1 JPSPINA4 gt PE7 USB PE7 JP3 PIN16 wa USB_WR nn Veapnmg Oo RD USBRDH JSPQ PINS BKPT USB BKPT me JP3 PIN17 Table 14 USB Interface FPGA Pin out 2 13 I O Connectors The Spartan 3E Evaluation Board may be populated with a 50 pin 2x25 header for access to lOs 2 13 1 Header J1 The 50 pin header labeled J1 on the Spartan 3E Evaluation Board is connected to 47 I O pins on the Spartan 3E FPGA Pin 48 on the header provides either 3 3V or 5 0V depending on the jumper pad installation on JT9 3 3V is the default Note that the pins of header JP1 are shared with several other peripherals including LEDs and LED segment display Please see the schematic and or other sections of this document for details The following table shows the pin out for the header connector Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respectiv
10. SB device to drive the configuration clock of the FPGA Default Open the FPGA provides the configuration clock JP5 Display Enable Jumper position 1 2 to enable the 2 character led segment display JP6 Force JTAG Mode Use this jumper to enable JTAG mode When installed FPGA is in boundary scan mode When uninstalled the FPGA will be in SPI mode Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 13 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue JP7 JTAG Par IV This is actually a connector Use this connector when programming the device over JTAG with a ribbon as used with the Xilinx Parallel IV cable JP8 SPI Flash WP A jumper on JP8 forces the devices WP signal low and places the device in write protect mode For normal operation writes enabled leave this jumper uninstalled JP9 FPGA Prog A jumper at this position will force the FPGA Prog signal low This jumper may be used to place the FPGA s pins in tri state condition Note that if HSWAP is enabled the FPGA will have internal pull ups on the pins Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Av
11. are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Released 12 of 23 Rev 1 0 08 09 2005 Literature ADS 005604 A AvnetAvenue ADS USB 7 0 Utility v3 03 x Control Mode Filename Device No Board Execute write SFI 1 Spartan 3E Eval Config FPGA Read SFI Browse Board Select Wi rite SP XILINX Esi Data Direction SFI Er File Status LEDs so Ready g Enumerated DK High Speed ie Bue Achy ity Design Services Figure 8 USB Utility GUI 2 6 Jumper Settings This section provides a description of the jumper settings for the Evaluation Board The jumpers are listed in order by JP number The board is ready to use out of the box with the default jumper settings JP1 USB RESET Jumper installed forces Cypress USB device into reset JP2 USB EEPROM WC Serial EEPROM write protect install a shunt at position 1 2 to protect data in the upper quadrant For normal operation leave shunts off or place at position 2 3 Pin is internally pulled low Default Open read write enabled JP3 USB EEPROM Unused Pins JP3 is actually a 10x2 header which allows user access to the Cypress EZUSBFX2 part which are not otherwise connected on this board JP4 USB CCLK ENABLE USB CCLK Enable when installed enables the U
12. dering Information Table 2 Spartan 3E Attributes DY Des Lungene nedi F Table 3 FPGA Configuration from PROM JTAG Jumper Setting rrrrrrnnnrrrrrrnnnrrorrrnnnnnvrnrnnnnnvrnrnnnnnrnnrnnnnrennnnnnsennnnnnneennnnneneennnnnensenn 8 Table 4 JTAG Headers Par 3 amp Par 4 Pin Out rornernnnnronnnnnnorrnnnronnnnrennnnnnennnnnsennnnnennnnnnennansennnnnennnnnsennnnssennannsnnnunsennnnsennnnnennnnnsennnnnssene 8 Table 5 J6 Header SPI PiN 0Ul scssi Ea r a ara E dined ce edda be Ea A a Eaa EE aa NAE EOSS 11 FEE 15 TE EET NN eee ee eee eee ee Ree eee ee ene eee eee eee See eee ese eee ee 16 TEPPE Ne en 16 Table 9 Push button FPGA Pin Out ccccccccccceeecccceececeeeeeeceeeceeceeeceseuaeeeesueeeeeaecessaeeeceaeceeseaecessuuecessaeceeseecessueeeseueeseesseeeeesseeeesaeees 17 Tabe O LED PN 17 Table T1 IRP Purvis 17 FEE 18 Table R9232 Connector PINOUT sesinin ae A N RRE ERE erT RIR EAEEREN AE AERE ENA ENE RNE RER AS 18 Table 14 USB Interface FPGA POUL Losing enakane enaa Ea aE Earn a ERNE tos si salir dearbnuiilCuinitaleican ouleellveaipaneuireaiimctelduoaeahinnteaninnalechesiuas 20 Toe 15 Header II PINOUT E LES reset 21 Copyright O 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 3 of 23 Rev 10 08 09 2005 Released Literature ADS 005
13. e owners Avnet Design Services 20 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue J1 Header 25x2 FPGA Signal P91 GEN 1010 GENTOO P7 9 Pes GEN 1012 GENJIONM P8 11 28 P76 GEN 1028 GEN 1027 P23 27 30 32 P74 GEN 1032 GEN 1031 P10 31 34 36 38 40 42 44 P31 GEN 1044 GEN 1043 P142 43 46 48 P17 GENIO CLK 8 3v5 0Vv 4 50 Ground Ground 49 Table 15 Header J1 Pin out Copyright O 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 21 of 23 Rev 10 08 09 2005 Released Literature ADS 005604 A AvnetAvenue 2 14 Power The Spartan 3E Evaluation Kit may be powered from an external 5V AC DC Adapter not supplied with the kit or the USB interface 2 14 1 External AC DC Adapter J5 An AC DC adapter is not provided with the kit To power the board with an external supply the user will provide 5V at the barrel connector labeled J5 The barrel connector dimensions are given in the figure below Note that the connection is center positive IMPORTANT Note that there is no protection for reverse power supply polarity so take necessary precautions to ensure that the center pin is 5V and the ring is ground 0 098 in 2 49 mm Aaya pin diam
14. eeeceeeeeeaaeeseceeeeeeseeeeeeeeeeeseeeeeceeeeeseeeaeseeeeeesseeaeseeeeeeeseaaaeeeeeeeeeeesaaas 6 Figure 3 Spartan 3E Evaluation Kit Block DiaQram cccccccceccccccceecceeeeeeceeeeeeaaeeseceeeeeeeeeeeeeeeeeseeeeseeceeeesseeeaeseeeeeesssaeeseeeeeessseaaeeeeeeeeseaaaas 7 Figure 4 Boundary Scan Mode Selection via JP6 cccccccceeeeeeccceeeceeeeeeceeeeeeaaeeesceceeeeeseeeeeeeeeeueesseceeeesseeeeseeeeeeesssaeeeeeeeeessaeeeeeeeeeeseeaaas 8 FOUG 5 Conigutaton COMING CONS ANS serena E ad 9 Figure 6 Configuration Connections Par IV ccccccccccccccccseseecceeeeceeeeseeeeeeeeeseeeeeeeeeeeesseeeeeeeesseeesseeeeeeeseeseeeceeeesseaeeeceeeeessaaaaeeeeeeeeeesaaas 9 Figure 7 Select Target Board ccccccccccsssseececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeesaeeeeeeeeeeeseaeeeeeeeeeeeeseeeesceeeeeeseeeeseeeeeeeeesssaeaseeeeeeesssaaaeeeeeeees 12 ge Ps ee SE AEG EE EEE EE EE EE EN 13 Figure 9 Default Jumper PI temeN Lundanes ye nave detivedivstie Sercepweliebeaseinsie ieaaesixawislewedibe ii surceseddswedlesisancs eanicemceuseennesadeessadeceuieoedbeteanca ds 15 ROET T TEST ee 22 Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 2 of 23 Rev 10 08 09 2005 Released Literature ADS 005204 A AvnetAvenue Tables Table 1 Or
15. eter housing diameter 5 Volts GND Figure 10 Barrel Power Connector J5 2 14 2 USB Power The Spartan 3E Evaluation kit may be powered from the USB port To do so use a standard USB cable plugged into a PC or standard USB host and plug the peripheral side of the cable in to JR1 This will supply 5V to the TI voltage regulator 2 14 3 TITPS75003 For voltage regulation the Spartan 3E Evaluation kit uses a Texas Instruments TPS75003 This is a triple supply power management IC and is designed for use with FPGAs and ASICs It features two 95 efficient buck regulators and an LDO In this application it uses the 5V input from the barrel or USB connectors to provide the 3 3V 2 5V and 1 2V required by the Spartan 3E device 3 0 Software BSP This section of the manual describes the example projects included in the kit 3 1 What is included All of the example projects included in the Spartan 3E Evaluation Kit were created using the Xilinx Integrated Software Environment ISE 7 1 ISE Example Projects o Segment Test Project 3 1 1 Segment Test Project This example is intended to provide a test count on the segment display as well as blinking LEDs and a terminal output The user may connect to the DB9 connector with a standard RS232 straight through non nullmodem type cable A terminal program such as Hyperterm may be used to view the output at 9600 8 N 1 Copyright 2005 Avnet Inc AVNET and the AV logo are regis
16. ftware options For more information visit the Internet link at http www em avnet com ads or www em avnet com spartan3e evl Ordering Information Part Number 99 MELLEL 3 ED nso R Miles MP C48 C55 R45 cag Sane JP4 acao i ms 9 o gj rk 2 END minimiin R6 Le INL J13 AL TARIE cit a G HAHA RP2 RPS APA RP5 9000 0000 0000 000 Figure 2 Spartan 3E Evaluation Board Picture Hardware ADS XLX SP3E EVL100 Xilinx Spartan 3E Evaluation Kit with an XC3S100E ADS BASEX BUNDLE ISE BaseX only available with purchase of the above part number Table 1 Ordering Information Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Released 60f 23 Rev 1 0 08 09 2005 Literature ADS 005604 A AvnetAvenue 2 0 Hardware This section of the manual describes the hardware of the Spartan 3E Evaluation Board The hardware was designed with the Spartan 3E FPGA as the focal point The block diagram is shown in Figure 8 ee Configuration SPI Serial EEPROM Switches Dip 4 P B 2 8 LEDs 2x Alpha Display Clock 100MHz Figure 3 Spartan 3E Evaluation Kit Block Diagram 2 1 Spartan 3E FPGA The Spartan 3E Evaluation Board was des
17. guration port on the Spartan 3E FPGA This provides for the development of a FPGA configuration tool which may be created by Avnet at a later date The pins which will affect FPGA configuration are shaded in the following table The USB FX2 device can also be used in a slave mode where the FPGA accesses the FX2 like a FIFO For more information about the FX2 modes of operation see the EZ USB FX2 Technical Reference Manual and the FX2 datasheet available on Cypress Semiconductor s web site http www cypress com Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Released 18 of 23 Rev 1 0 08 09 2005 Literature ADS 005604 A AvnetAvenue FX2 Signal Board net name FPGA pin Description CTL 0 USB CTLO P141 Programmable control outputs CTL 1 USB CTL1 USB CTL2 CTL 3 CTL3_PROG Output enable for FRGA_PROG driver A low on this pin will drive the FPGA PROG net CTL 4 CTL4 IFC EN Allows FX2 to drive the FPGA CCLK see schematic pg4 Requires R16 Formerly connected to FPGA CS on other Avnet Boards Affected by JP4 GPIFADR 0 and IFCLK Sample able ready inputs RDY 1 USB_RDY1 P140 RDY S USB_RDYS Sample able ready input connected to JP3 15 Bidirectional FIFO data bus also SMAP data FDO connected to USB
18. igned to support the Spartan 3E FPGA in the 144 pin package TQ144 This package supports two densities 35100E and 35250E though initially only the 3S100E will be offered in a product Table 2 describes the attributes of the Spartan 3E device based on density Spartan System Logic BlockRAM Dedicated Max Gates Cells bits Multipliers User I O 144 package XC3S100E XC3S250E 5 508 Table 2 Spartan 3E Attributes by Density Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Tof 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue 2 2 Configuration The Spartan 3E Evaluation Board supports Boundary scan JTAG and SPI programming methods In addition the user may use the Avnet USB utility to configure the FPGA and or SPI flash device SPI Configuration Mode USB CCLK En Mode Select M2 M1 MO JP6 DEFAULT DEFAULT 0 0 1 FPGA provides SPI protocol to read from the Flash Boundary Scan FPGA will not attempt 1 0 1 configuration over SPI or other means It may be programmed directly over the JTAG interface In this mode the FPGA is configured over USB from a Host PC A Windows utility is provided Table 3 FPGA Configuration from PROM JTAG Jumper Setting 2 2 1 Boundary Scan Pr
19. leting the process to save steps on Subsequent passes In the next 2 screens select Prepare Configuration Files and PROM File and senest clicking Next after each Prepare PROM Files x I want to target a Xiling PROM C Generic Parallel PROM The following screen shown at the left is where the properties of the file to be generated are set Even though the SPI PROM on the board is not manufactured by Xilinx select Xilinx PROM as the target and HEX for the format PROM File Format C MOS TEK UFP C format C EXO HEX OC BIN ISC The Checksum Fill Value is the expected value in FLASH after it has been erased Eo FF for this device Checksum Fill Value 2 Hex Digit mm EE The PROM File Name is the name of the file to be generated HEX will be added Location c my_projects sp3e_proj Browse by the tool and location is the path to where it is to be saved These can be any valid windows expressions but avoid spaces as the Xilinx tools sometime have trouble with spaces in file names and pathways In the next window check Auto Select PROM and then next twice coct_ Heb x Data Stream 0 Starting Address Max 8 Hex Digits fo The next step is to add the BIT file to be converted Now start adding device file s Add File NOTE The BIT file must be created with CCLK selected as the start up clock or the resulting HEX file wi
20. ll not configure the FPGA Multiple file are not supported so select NO when asked if a second file is to be added Then Finish and Yes to generate the file Cancel Help Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 10 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 AvnetAvenue 2 4 Programming SPI FLASH An FPGA configuration file should first be tested by programming the BIT format directly into the FPGA via boundary scan See the appropriate section of this document for boundary scan JTAG programming When a bit file has been tested to the point where it is ready for non volatile storage IMPACT should be used to convert the BIT to a HEX format as described in Section 2 3 When creating the HEX file be sure to use a BIT which was generated with the startup clock option set for CCLK typically the default The primary purpose of the SPI FLASH on this board is to store the configuration file for the FPGA but the unused portion of the FLASH or the entire FLASH if an alternate configuration method is used can be used to store user data or code require by the FPGA application The programming methods below can be used to write configuration and or data to the device NOTE JP8 provides write p
21. net Inc All other brands are property of their respective owners Avnet Design Services 14 of 23 Rev 10 08 09 2005 Released Literature ADS 005604 A AvnetAvenue The following figure illustrates the default placement of the jumpers installed on the Spartan 3E Evaluation Board TP2 TES J JV 2 5V Edr or df br 9 GND TMS Hck Broo Bro g US O p STA LMS o cMS oO JP1 JP4 DONADA AMAUO UA 00000000 AA EN am Hil 100 v O MHz o TUE o JPE JPS SW3 C ep Figure 9 Default Jumper Placement JIx Resistor Jumpers Additional flexibility has been designed into the circuit in the form of resistor jumpers JTx and series resistors that can be moved or removed to alter the functionality of the board The purpose of some of these components may be discussed in other sections of this manual others may not be discussed at all The position of these components should not be altered without careful review of the schematics and associated component data sheets to prevent damage to the board 2 7 Clocks The Spartan 3E Evaluation Board uses a 100MHz system clock If other frequencies are desired a DCM may be used in the FPGA to obtain the target frequency Freq GCLK Input FPGA pin 100MHz P129 Use internal DCM to obtain other frequencies Table 6 Available GCLK Sources Copyright 2005 Avnet Inc AVNET and the AV logo are regis
22. ogramming the Spartan 3E FPGA via Boundary scan requires a JTAG download cable not included in the kit The Spartan 3E Evaluation Board has connectors to support both the flying leads connection of the Parallel Cable Ill and the ribbon cable connection of the Parallel Cable IV These connectors are labeled J4 and JP7 respectively When programming the FPGA via the JTAG interface it is good practice to place the device in Boundary Scan mode This may be accomplished using the Mode select jumper JP6 With JP6 off the mode pins M 2 0 will be 001 which enables SPI programming mode With JP6 installed the mode pins M 2 0 will be 101 which enables boundary scan mode Note that power should be removed when changing the programming Mode For Boundary Scan mode place a jumper at JP6 Figure 4 Boundary Scan Mode Selection via JP6 JTAG Header J4 J4 is a 6x1 standard 0 1 header and is intended for use with flying leads such as those of the Xilinx Parallel Cable 3 PC3 downloading debugging cable Connect the leads as indicated in Table 4 below for J4 as demonstrated in Figure 5 Table 4 JTAG Headers Par 3 amp Par 4 Pin Out Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Released 8 of 23 Rev 1 0 08 09 2005 Literat
23. pins 34 and 62 DIN FD1 amp FD2 determined by JT10 amp JT12 Bidirectional FIFO data bus Optional FPGA CCLK out See schematic sheet 4 Affected by JP4 CTL4 IFC EN and IFCLK Connection determined by JT11 GPIFADR 3 FPGA MO P59 P62 SelectMAP port mode MO MOL PU PEPE connection asermined by JTB Ko Kl MOSI Kol Eat FPGA Master Out Slave In input to SPI Flash May be used to write data to SPI Biel DIN MISO Programming input to FPGA Data out from SPI Flash May be used to program FPGA or read data from SPI Also connected to USB _ FDO apr FPGAUSK PI OS pin or SF Fash Pat GPIFADR 7 No Connect s ean US ET rs opt mess Jes Copyright O 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 19 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue FX2 Signal Board net name FPGA pin Description PA7 SLCS USB_SLCS Port A I O or slave FIFO enable RESET USB _RESET Not connected to FPGA May use JP1 to force USB device active low reset CLKOUT USB CLKOUT Clock output from USB Serial prom clock SDA OSDA gt Seralpromdata gt WAKEUP USB WAKEUPfH gt USBwakeupsignal USB UART TXO USB UART Transmit o ose o a SESA TXD1 USBTXDI JP PINE gt
24. programming pins are available to the user after configuration it is possible to use memory for external data storage The following table illustrates the pin outs of the FPGA to SPI flash memory SPI Flash Pin SPI Flash Pin Name FPGA Signal Name FPGA pintt 1 Q 1 DNMSO l Holdt 2 O C FPGA_CCLK FPGA_MOSI Table 11 SPI FPGA Pin out Please see also the configuration section of this document for information on configuring the FPGA with SPI NOTE JP8 provides write protection for the SPI FLASH device so this shunt must be removed before programming Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 17 of 23 Rev 10 08 09 2005 Released Literature ADS 005604 A AvnetAvenue 2 12 Communication RS 232 USB 2 0 For communication the Spartan 3E FPGA has access to an RS232 transceiver and a USB2 0 transceiver 2 12 1 RS 232 Manufacturer Harris Intersil Part ICL3222CA The RS232 transceiver is a 3222 available from Harris Intersil ICL3222CA and Analog Devices ADM3222 This transceiver is operating at 3 3V for VCC The internal charge pump creates the RS232 compatible output levels The standard RX and TX lines pin3 and pin2 are connected to the FPGA by way of the 3222 Please see the table below for the FPGA
25. rotection for the SPI FLASH device so this shunt must be removed before programming External Programming There are many programmers on the market which are capable of programming the SPI device To program the device with this method it would likely require the device be removed from the PCB While external programming may be ideal for a production environment prior to mounting the components it is obviously not for development Thus a method of in circuit programming is desirable In Circuit Programming In Circuit programming of the SPI FLASH can be accomplished on this board from a host PCI via USB with the provided utility or with an external controller via the interface provided by the header J6 Programming via USB The Avnet USB utility may be used to write data to the SPI Flash device The Avnet USB utility will accept a HEX file as an input and program it into the SPI Flash The HEX is actually an ASCII file so there is a conversion going on in the background which is transparent to the user For additional information on the Avnet USB utility please see the included documentation Programming with J6 The SPI Flash pins have been made available at J6 This will allow the user to program the part via an external custom method It may be necessary when programming the SPI in this mode to place a shunt on JP9 to hold the Spartan3E PROG pin low tri stating the FPGA pins to avoid contention on the programming signals The pinout for J
26. tered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 15 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 A AvnetAvenue 2 8 On board Display 2 Character Alphanumeric LED Manufacturer Lite On Part LTP 3786E 03 ss I E amp The Spartan 3E Evaluation board uses a dual digit 14 segment alphanumeric display from Lite On To enable the display place a jumper at JP5 position 1 2 Each segment may be controlled by the FPGA General Purpose I O bus as listed below The GEN 10 9 and 10 nets are used to drive the segment anodes while a logic low on GEN 1011 25 enables the individual segments 2 9 DIP amp Push button Switches Display Pin Display Pin Name E 11 CharzAnode PI 1 9 8 DP P8 11 Table 7 Ethernet PHY Modes A four position dipswitch SPST has been installed on the board and attached to the FPGA These switches provide digital inputs to user logic as needed The signals are pulled low 0 by 4 7K ohm resistors when the switch is open and tied to 3 3V 1 when the switch is closed SWITGHO P107 SWITCH Pitt SWITCH2 P114 SWITCH3 P119 Table 8 DIP switch FPGA Pin out Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc
27. tered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services 22 of 23 Rev 1 0 08 09 2005 Released Literature ADS 005604 AvnetAvenue 4 0 List of Partners YZ Aiz TEXAS INSTRUMENTS gt XILINX Copyright 2005 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc AVNET AVENUE and AVNET AVENUE amp Design are trademarks of Avnet Inc All other brands are property of their respective owners Avnet Design Services Released 23 0f 23 Rev 1 0 08 09 2005 Literature ADS 005604
28. ure ADS 005604 A AvnetAvenue Flying Leads 4 JP7 Connector Such as used with Parallel Cable Shown here for reference only Figure 5 Configuration Connections Par3 Parallel Cable IV MultiPro Ribbon JP7 JP7 is intended for connection to a 14 pin ribbon as supplied with a Xilinx Parallel Cable IV or MultiPro Desktop Tool Connect the ribbon cable to JP7 as shown below Note that the ribbon and connector are keyed to ensure proper installation Keyed Connection Only Plugs in One Figure 6 Configuration Connections Par IV For further information regarding Xilinx configuration solutions please visit http www xilinx com products design resources config sol index htm 2 2 2 Configuring FPGA with SPI FLASH default When the configuration mode is set to SPI the Spartan3E will attempt to configure after power up by sequentially loading data from the SPI FLASH starting at address 0x0 SPI mode is selected by removing the jumper at JP6 which is the factory default The SPI FLASH is programmed via the methods discussed in section 2 4 of this manual using a HEX file as generated according to the instructions in section 2 3 2 2 3 Configuring FPGA over USB The FPGA pins required for configuration are attached to the CY68013 USB controller allowing a host controller to initialize the Spartan3E FPGA and download a new BIT configuration file This kit includes a Windows utility for configuration
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