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PC-DIO-24/PnP User Manual

1. Symbol MSM82C55A 2 Parameter ymo Min Max Unit Remarks Setup Time of address to the falling edge of RD tAR 20 Hold Time of address to the rising edge of RD tRA o RD Pulse Width tRR 100 ns Delay Time from the falling edge of RD to the 120 output of defined data RD ns To Delay Time from the rising edge of RD to the 1 floating of data bus tDF 9 2S os Time from the rising edge of RD or WA to the next 200 i ni falling edge of RD or WR RV T Setup Time of address before the falling edge of WR taw 0 ns Hold Time of address after the rising edge or WR twa 20 ns WR Pulse Width tww 150 ns Setup Time of bus data before the rising edge of WR tow 50 ns al Holt Time of bus data after the rising edge of WR two 30 ns Delay Time from the rising edge of WR to the output of defined data wB 209 ns _ Setup Time of port data before the falling edge of tR 20 ns RD p Time of port data after the rising edge of RD tHR 10 ns Faire ACK Pulse Width tak 100 ns STE Pulse Width tST 100 ns Load Setup Time af port data before the rising edge of 20 150pF L tps ns STB Hold Time of port data after the rising edge of STB tPH 50 ns Delay Time from the failing edge of ACK to the i 150 ns Output of defined data AD Delay Time from the rising edge of ACK to the fl
2. t 1 W2 2 W3 3 U9 4 Product Name Figure D 1 PC DIO 24 Parts Locator Diagram Base 1 0 Address Settings The base I O address for the PC DIO 24 is determined by the switches at position U9 see Figure 2 1 The switches are set at the factory for the I O address hex 210 With this default setting the PC DIO 24 uses the I O address space hex 210 through 213 Note Verify that this space is not already used by other equipment installed in your computer If any equipment in your computer uses this I O address space you must change the base I O address for the PC DIO 24 or for the other device Each switch in U9 corresponds to one of the address lines A9 through A2 For space reasons not all address lines are separately labeled on the board The range for possible base I O address settings is hex 000 through 3FC Base I O address values hex 000 through OFF are reserved for system use Base I O values hex 100 through 3FF are available on the I O channel A1 and AO are used by the PC DIO 24 to decode the onboard registers On the U9 DIP switches press the side marked OFF to select a binary value of 1 for the corresponding address bit Press the other side of the switch to select a binary value of 0 for the corresponding address bit Figure D 2 shows two possible switch settings National Instruments Corporation D 3 PC DIO 24 PnP User Manual Appendix D Using Your
3. DAQ Click here to comment on this document via the National Instruments website at www natinst com documentation daq PC DIO 24 PnP User Manual 24 bit Digital 1 0 Board for ISA Computers February 1998 Edition Part Number 320288C 01 Copyright 1989 1998 National Instruments Corporation All rights reserved Internet Support E mail support natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 Fax on Demand Support 5124181111 Telephone Support USA Tel 512 795 8248 Fax 512 794 5678 International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 288 3336 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin Texas 78730 5039 USA Tel 512 794 0100 Important Information Warranty Copyright Trademarks The PC DIO 24 and PC DIO 24PnP boards are warrante
4. Set PC6 to enable interrupts from 82C55A Set IRQO to enable port A interrupts Set INTEN bit EXAMPLE 6 Set up interrupts for mode 2 input transfers Enable the appropriate interrupt bits outp cnfg OxD0 cnfg 0x09 iregl 0x01 outp outp outp ireg2 0x04 Mode 2 input Set PC4 to enable interrupts from 82C55A Set IRQO to enable port A interrupts Set INTEN bit Interrupt Handling iz Note This section applies only to the PC DIO 24PnP The PC DIO 24 non PnP does not implement the IRQ1 IRQ2 or INTEN bits To enable and disable interrupts on the non PnP board see Appendix D Using Your PC DIO 24 Non PnP Board PC DIO 24 PnP User Manual On the PC DIO 24PnP the INTEN bit of Interrupt Register 2 must be set to enable interrupts This bit must first be cleared to disable unwanted interrupts After all sources of interrupts have been disabled or placed in an inactive state you can set INTEN To interrupt the host computer program the selected 82C55A port for the I O mode desired In mode 1 set either the INTEA or the INTEB bit to enable interrupts from port A or port B respectively In mode 2 set either INTE1 or INTE2 for interrupts on output or input transfers respectively The INTEI and INTE2 interrupt outputs are cascaded into a single interrupt output for port A After enabling interrupts from the 82C55A set t
5. No pullups or pulldowns Jumper for pullup factory default or pulldown Jumper for pullup factory default or pulldown Configuration The PC DIO 24 contains one DIP switch and two jumpers to configure the base I O address interrupt level and interrupt enable signal Figure D 1 shows the location of DIP switch U9 and jumper sets W2 and W3 The PC DIO 24 is configured at the factory to a base I O address of hex 210 to use interrupt enable line PC4 and to use interrupt level 5 These settings shown in Table D 2 are suitable for most systems However if your system has other hardware at this base I O address interrupt enable line or interrupt level you need to change these settings on the PC DIO 24 as described in the following pages or on the other hardware Record your settings in the PC DIO 24 PnP Hardware and Software Configuration Form in Appendix E Customer Communication Table D 2 PC DIO 24 Factory Set Jumper and Switch Settings Base I O Address Interrupt Enable Line Interrupt Level Hex 210 factory setting PC4 factory setting Interrupt level 5 selected factory setting W2 Row PC4 W3 IRQ5 O Tr LI sb CO QW L IL amp amp 1 2 3 4 5 6 7 8 U9 PC DIO 24 PnP User Manual D 2 National Instruments Corporation Appendix D Using Your PC DIO 24 Non PnP Board
6. D7 D6 D5 D4 D3 D2 D1 DO 1 0 1 0 1 0 X X X D Port C bits PC4 and PC5 1 input 0 output The control word written to the CNFG Register to configure port B for output in mode 1 is shown as follows Notice that port B does not have extra input or output lines left from port C when ports A and B are both enabled for handshaking D7 D6 D5 D4 D3 D2 D1 DO During a mode 1 data write transfer the status of the handshaking lines and interrupt signals can be obtained by reading port C Notice that the bit definitions are different for a write and a read transfer C 14 National Instruments Corporation D7 D6 Appendix C Register Level Programming Port C status word bit definitions for output port A and port B D5 D4 OBFA INTEA 1 0 1 0 INTRA INTEB OBFB INTRB Bit Name OBFA INTEA I O INTRA INTEB OBFB INTRB Description Output Buffer for Port A A low setting indicates that the CPU has written data to port A Interrupt Enable Bit for Port A Setting this bit enables interrupts from port A of the 82C55A This bit is controlled by setting resetting PC6 Input Output These bits can be used for general purpose I O when port A is in mode 1 output If these bits are configured for output the port C bit set reset function must be used to manipulate them Interrupt Request Status for Port A W
7. NE RS Port gt Data Bus Port B gt Data Bus Port C Data Bus Data Bus gt Port A Data Bus gt Port 8 read and write etc are as shown in the table below Data Bus gt Port C Operation o input 0 Fa M role 0 0 Output 0 1 EE aa Data Bus Control Register Setting of Control Word Hfegal Condition EREBERERES Data bus is in the high impedance status The contro register is composed of 7 bit latch circuit and 1 bit flag as shown below Es A Control Bits Group 8 Control Bits Definition of input output of low order 1 4 bits of port C Definition of input output of 8 bits of port B Mode definition of group B Definition of input output of 8 bits of port A Control word identification flag Be sure to set 1 for the control word to define a mode and input output When set to 0 it becomes the control word for bit set resat Precaution for mode selection The output registers for ports A and C are cleared to each time data is written in the command register and the mode is changed but the port B state is un defined 198 PC DIO 24 PnP User Manual Bit Set Reset Function When port C is defined as output port it is possible to set set output to 1 or reset set output to O any one of 8 bits without affecting other bits as shown next page B 10 Definit
8. Appendix D Register Level Programming Differences between the PC DIO 24PnP and the PC DIO 24 sees D 1 Configuration e RIP nant ere etes tie os dds titles D 2 Base I O Address Settings D 3 Interrupt Selection tereti ree e EP et ps D 5 Interrupt Enable Settings D 6 Interrupt Level Settings D 6 Installation eund UR URP eget eee UU UR IR D 7 Appendix E Customer Communication Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware esee ene 1 4 Figure 2 1 Jumper W1 Location ss 2 1 Figure 3 1 Digital I O Connector Pin Assignments essere 3 2 Figure 3 2 Digital I O Connections 3 6 Figure 3 3 DIO Channel Configured for High DIO Power up State with External Load aie iere eget tn 3 8 Figure 3 4 DIO Channel Configured for Low DIO Power up State with External Load ettet eerta t wie ied 3 9 Figure 3 5 Mode 1 Timing Specification for Input Transfers 3 12 Figure 3 6 Mode 1 Timing Specification for Output Transfers 3 13 National Instruments Corporation Vii PC DIO 24 PnP User Manual Contents Figure 3 7 Mode 2 Timing Specification for Bidirectional Transfers 3 14 Figure 4 1 PC DIO 24 PnP Block Diagram eene 4 1 Figure C 1 Control Word Formats f
9. Table 3 3 Timing Signal Descriptions Continued National Instruments Corporation Signal Name Direction Description INTR Output Interrupt Request This signal becomes high when the 82C554 is requesting service during a data transfer The appropriate interrupt enable bits must be set to generate this signal RD Internal Read Signal This signal is the read signal generated from the control lines of the PC WR Internal Write Signal This signal is the write signal generated from the control lines of the PC DATA Bidirectional Data Lines at the Selected Port This signal indicates when the data on the data lines at a selected port is available output or should be available input 3 11 PC DIO 24 PnP User Manual Chapter 3 Signal Connections Mode 1 Input Timing The following figure illustrates the timing specifications for an input transfer in mode 1 ete 1 T4 STB Fe PUN or i RiL NIR Po RD DATA Name Description Minimum Maximum TI STB pulse width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds Figure 3 5 Mode 1 Timing Specification for Input Transfers PC DIO 24 PnP User Manual 3 12 Natio
10. INTR interrupt request output This is the interrupt request signal for the CPU of the data fetched into the input latch it is in dicated by high level only when the internal INTE flip flop is set This signal turns to high level at the rising edge of the STB IBF 1 at this time Mods 1 Input Group A Note Although belonging to group B PC operates as the control signal of group A functionally 200 PC DIO 24 PnP User Manual B 12 and low level at the falling edge of the RD when the INTE is set INTE of group A is set when the bit for PC is set while INTEg of group B is set when the bit for PC is set Following is a description of the output opera tion of mode 1 OBF Output buffer full flag output This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU This sig nal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK ACK Acknowledge input This signal when turned to tow level indicates that the terminal has received data INTR Interrupt request output Thisis the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSMB82C554A 5 It indicates the occurrence of the interrupt in high level only when the inter nal INTE flip flop is set This signal turns to high level at the rising edge of the ACK OBF 1 at this time and low level at the falli
11. NI DAQ and Your Hardware Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using National Instruments application software to program your National Instruments DAQ hardware Using the National Instruments application software is easier than and as flexible as register level programming and can save weeks of development time PC DIO 24 PnP User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with your PC DIO 24 PnP board including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon e Connector blocks shielded and unshielded 50 pin screw terminals e SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue o
12. kilo the standard metric prefix for 1 000 or 103 used with units of measure such as volts hertz and meters PC DIO 24 PnP User Manual Glossary K kbytes kbytes s L LabVIEW LSB MB MSB NI DAQ 0 operating system PPI PC DIO 24 PnP User Manual kilo the prefix for 1 024 or 210 used with B in quantifying data or computer memory 1 024 bytes a unit for data transfer that means 1 000 or 10 bytes s laboratory virtual instrument engineering workbench least significant bit meters 1 Mega the standard metric prefix for 1 million or 106 when used with units of measure such as volts and hertz 2 mega the prefix for 1 048 576 or 220 when used with B to quantify data or computer memory megabytes of memory most significant bit National Instruments driver software for DAQ hardware base level software that controls a computer runs programs interacts with users and communicates with installed hardware or peripheral devices programmable peripheral interface G 4 National Instruments Corporation PnP port R RAM resolution Rexr SCXI signal conditioning S s SSR National Instruments Corporation G 5 Glossary PnP Plug and Play refers to a device that is fully compatible with the industry standard Plug and Play ISA Specification All bus related configuration is performed through software freeing you from manually configuring jumpers or switches
13. Digital 1 0 Signal Connections The following specifications and ratings apply to the digital I O lines The maximum input logic high and output logic high voltages assume a Vcc supply voltage of 5 0 V The absolute maximum voltage rating is 0 5 to 5 5 V with respect to GND Digital input specifications referenced to GND Input logic high voltage 2 2 V min 5 3 V max Input logic low voltage 0 3 V min 0 8 V max Input high current Vin 5 V WI set to pullup 11 0 pA max Input high current Vin 5 V WI set to pulldown 65 LA max Input logic low current Vin 0 V W1 set to pullup 65 LA max Input logic low current Vin 0 V WI set to pulldown 11 LA max PC DIO 24 PnP User Manual 3 4 National Instruments Corporation Chapter 3 Signal Connections Digital output specifications referenced to GND Output logic high voltage Io 2 5 mA Output logic high voltage oh 4 mA Output logic low voltage Ig 2 5 mA Output logic low voltage Io 4 mA 3 7 V min 2 7 V min 0 V min 0 V min 5 0 V max 5 0 V max 0 4 V 0 5 V Figure 3 2 depicts signal connections for three typical digital I O applications National Instruments Corporation PC DIO 24 PnP User Manual Chapter 3 Signal Connections 5 V um r o A EN ER LED Jumper pour 1 Selectable W1 100ko 100
14. e T amp B Ansley Corporation part number 622 5041 The standard ribbon cables 50 conductor 28 AWG stranded that can be used with these connectors are as follows e Electronic Products Division 3M part number 3365 50 e T amp B Ansley Corporation part number 171 50 Recommended manufacturer part numbers for the 50 pin edge connector for connecting to a module rack with an edge connector are as follows e Electronic Products Division 3M part number 3415 0001 e T amp B Ansley Corporation part number 622 5015 A polarizing key can be plugged into these edge connectors to prevent inadvertent upside down connection to the I O module rack The location of this key varies from rack to rack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key are as follows e Electronic Products Division 3M part number 3439 2 e T amp B Ansley Corporation part number 622 0005 PC DIO 24 PnP User Manual 1 6 National Instruments Corporation Chapter 1 Introduction Unpacking Your PC DIO 24 PnP board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic pack
15. Connector ineine pere trente enter 4 3 Appendix A Specifications Appendix B OKI 82C55A Data Sheet Appendix C Register Level Programming Introduction epu te e eO EE DEDE D USD RE C 1 Register Map x5 ei o ee eee Neb en teda nes C 3 Register Description for the 82C55A C 3 Register Description for the Interrupt Control Registers C 5 Interrupt Control Register 1 PnP Board Only C 6 Interrupt Control Register 2 PnP Board Only C 7 Programming Considerations for the 82C55A ceceessesecsseseeecseeeseseseeeessseeeeessnenes C 8 Modes of Operation for the 82C55A oo cece ceceseeesceseceeeeeeeeeeeeeeeneseeeeneeeaes C 8 Mode 0 5 Sts Abn Sia ai el ene ehe C 8 Mode oie tei etel eee Meni aee ur eerte tn C 8 Modernes Dhs ni nes SR nn SE mt C 9 Single Bit Set Reset Feature C 9 Mode 0 Basic VO sosie C 9 Mode 0 Programming Example C 10 PC DIO 24 PnP User Manual vi National Instruments Corporation Contents Mode 1 Strobed Input ss C 11 Mode 1 Input Programming Example sse C 13 Mode 1 Strobed Output ss C 14 Mode 1 Output Programming Example sss C 16 Mode 2 Bidirectional Bus C 17 Mode 2 Programming Example esse C 19 Interrupt Programming Examples for the 82C55A C 20 Interrupt Handling reote he E ESEE ETE petes C 22
16. OFJ 191 National Instruments Corporation B 3 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet a 1 0 MSM82C55A 2RS GS VJS ABSOLUTE MAXIMUM RATINGS Limits Parameter Conditions Unit MSMB2C55A 2RS MSM82C55A 2GS M M82C55A 2v JS Ssupply Voltage Ta 25 C 00 O o ote Bto 7 v with Input Voltage respect 0 5 to Veg 0 5 Output Voltage to GND 0 5 to Voc 0 5 Storage Temperature 55 to 150 Power Dissipation OPERATING RANGE Symbol Supply Voltage Vcc 3to6 Operating Temperature Top 40to 85 RECOMMENDED OPERATING RANGE EE HER NN SENE ET EX Operating Temperature c t Input Voltage 0 3 0 8 H Input Voltage v Vec 0 3 v DC CHARACTERISTICS MSMB2C55A 2 in Typ Max Parameter Conditions LL Output Voltage lou 2 5mA loH 40 LA H Output Voltage kel EEE IOH 25mA Voc 4 5V to Input Leak Current 4j O lt VINSVec 55V Output Leak Current ILo OXVourEVcc Ta 40 C to 85 C CS 2 Vcc 0 2V CL OpF RERO em Vn Yeg 02v Y Vit S 02V Average Supply VO wire cycle Current active S3C85A 2 BMHzCPU ming 192 PC DIO 24 PnP User Manual B 4 National Instruments Corporation Appendix B OKI 82C55A Data Sheet a O MSM82C55A 2RS GS VJS AC CHARACTERISTICS Vcc 4 5 to 5 5V Ta 40 to 80 C
17. PC DIO 24 Non PnP Board rs A8 EI A7 fi A6 m A5 Lye A4 q A3 ic A2 o Es 1 U9 a Switches Set to Base I O Address Hex 210 Default Setting o lt x AT b Switches Set to Base I O Address Hex 278 4 F1 AB oe a7 a A5 Foe 2 Figure D 2 Example Base 1 0 Address Switch Settings Table D 3 shows some examples of switch settings and their corresponding address ranges PC DIO 24 PnP User Manual D 4 National Instruments Corporation Appendix D Using Your PC DIO 24 Non PnP Board Table D 3 Example Switch Settings with Corresponding Base 1 0 Address and 1 0 Address Space Switesetans Base I O I O Address A9 A8 A7 A6 A5 A4 A3 A2 Address hex Space Used hex 0 1 0 0 0 0 0 0 100 100 103 0 1 0 0 1 0 0 0 120 120 123 0 1 0 1 0 0 0 0 140 140 143 0 1 0 1 1 0 0 0 160 160 163 0 1 1 0 0 0 0 0 180 180 183 0 1 1 0 1 0 0 0 1A0 1A0 1A3 0 1 1 1 0 0 0 0 100 1C0 1C3 0 1 1 1 1 0 0 0 1E0 1E0 1E3 1 0 0 0 0 0 0 0 200 200 203 1 0 0 O 1 0 0 0 220 220 223 1 0 O 1 O 0 0 0 240 240 243 1 0 O 1 1 0 0 0 260 260 263 1 0 1 0 0 0 0 0 280 280 283 1 O 1 O 1 0 0 0 2A0 2A0 2A3 1 O 1 1 0 0 0 0 2C0 2C0 2C3 1 0 1 1 1 0 0 O0 2E0 2E0 2E3 1 1 0 0 0 0 0 0 300 300 303 Note Base I O address values 000 through OFF hex are reserved for system use Base I O address values 100 through 3FF hex are available on the I O channel Interr
18. Sheet a 1 O0 MSM82C55A 2RS GS VJS u 4 When Group A is Different in Mode from Group B possible to set the one not defined as a control pin Group A and group B can be used by setting them in port C to both input and output as a port which in different modes each other at the same time operates in mode O at the 3rd and Oth bits of the When either group is set to modet or mode 2 it is control word Mode combinations that define no control bit at port C Mode 1 input SPERTA SERRO Mode 0 output Mode 1 output Mode 1 output Mode 1 output Controtled at the 3rd bit D3 Controlled at the Oth bit DO of the control word of the control word When the 1 0 bit is set to input in this case it is pos The bit sat reset function can be used for ail of sible to access data by the normal port C read PC3 PCO bits Note that the status of port C operation 3 varies according to the combination of modes like When set to output PC7 PC4 bits can be ac this cessed by the bit set reset function only Meanwhile 3 bits from PC2 to PCO can be accessed by normal write operation 204 PC DIO 24 PnP User Manual B 16 National Instruments Corporation Appendix B OKI 82C55A Data Sheet a 1 O MSM82C55A 2RS GS VJS 5 Port C Status Read bus status signal can be read out by reading the When port C is used for the control signal that is contant of port C in either mode 1 or mode 2
19. Strobe bidirectional bus O operation STB Strobe input In mode 2 it is possible to transfer data in 2 direc When this signal turns to low level the data out tions through a single 8 bit port This operation is put to the port from the pin is fetched into the akin to a combination between input and output internal input latch The data is output to the operations Port C waits for tha control signal in this data bus upon receipt of the RD signal from the case too Mode 2 is available only for group A CPU but it remains in the high impedance sta however tus until then Next a description is made on mode 2 IBF Input buffer full flag output OBF Output buffer full flag output This signal when tumed to high level indicates PC DIO 24 PnP User Manual 202 This signal when turned to low level indicates that data has been written to the internal out put latch upon receipt of the WR signal from the CPU At this time port A is still in the high im pedance status and the data is not yet output to the outside This signal turns to low level at the r sing edge of the WR and high level at the failing edge of the ACK ACK Acknowledge input When a low level signal is input to this pin the high impedance status of port A is cleared the buffer is enabled and the data written to the in ternal output latch is output to port A When the input returns to high level port A is made into the high impedance status B 14 that
20. V on the DIO line at power up You can substitute smaller resistor values but they will draw more current leaving less sink current for other circuitry connected to this line The 5 6 KQ resistor will reduce the amount of a logic low sink current by 0 8 mA with a 0 4 V output Timing Specifications This section lists the timing specifications for handshaking with the PC DIO 24 PnP The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers The signals in Table 3 3 are used in the timing diagrams on the subsequent pages Table 3 3 Timing Signal Descriptions Signal Name Direction Description STB Input Strobe Input A low signal on this handshaking line loads data into the input latch IBF Output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This is an input acknowledge signal ACK Input Acknowledge Input A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the PC DIO 24 PnP OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written to the selected port PC DIO 24 PnP User Manual 3 10 National Instruments Corporation Chapter 3 Signal Connections
21. document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or neglige
22. each control signal and The status read out is as follows Status read on the data bus Da D3 vo Mode 1 vo input Mode 1 Vo Vo yo 1 0 output Mode 1 input VO IBFA INTE Mode 1 output Mode 1 Mode 1 output output INTRA INTEBg Mode 1 output 6 Reset of MSM82C55A becomes the input mode at a high level pulse above Be sure to keep the RESET signal at power ON in 500 ns the high level at least for 50 us Subsequently it Note Comparison of MSM82C55A 5 and MSMB2C55A 2 MSM82C55A 5 After a write command is executed to the command register the internal latch is cleared in PORTA PORTC For instance OOH is output at the beginning of a write command when the output Port is assigned However if PORTB is not cleared at this time PORTB is unstable In other words PORTB only outputs ineffective data unstable value according to the device during the period from after a write command is executed till the first data is written to PORTB MSM82C55A 2 After a write command is executed to the command register the internal latch is cleared in All Ports PORTA PORTB PORTC OOH is ontput at the beginning of a write command when the output port is assigned 205 National Instruments Corporation B 17 PC DIO 24 PnP User Manual Appendix Register Level Programming This appendix describes in detail the address and function of each of the PC DIO 24
23. interference at his own expense Notice to User Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules If necessary consult National Instruments or an experienced radio television technician for additional suggestions The following booklet prepared by the FCC may also be helpful Interference to Home Electronic Entertainment Equipment Handbook This booklet is available from the U S Government Printing Office Washington DC 20402 Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Contents About This Manual Organization of This Manual ettet tee ipee ix Conventions Used in This Manual x National Instruments Documentation sesesssseseseeee eene ener xii Related Documentation xiii Customer Communication sise xiii Chapter 1 Introduction About the PC DIO 24 PnP siennes 1 1 What You Need to Get Started 1 2 Software Programming Choices ss 1 2 National Instruments Application Software 1 2 NI DAQ Driver Software 1 3 Register Level Programming ss 1 4 Optional Equipment ss 1 5 Custom Cables ie eie eroe test eeu dee ttti 1 5 Unpacking opea Revo an he CEE I Ae ee ed 1 7 Cha
24. parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FIP Support To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation E 1 PC DIO 24 PnP User Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512418 1111 E Mail Support Currently USA Only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Country Australia Austria Belgium Brazil Canada Ontario Canada Qu bec Denmark Finland France Germany Hong Kong Israel Italy
25. register has a master interrupt enable bit When writing to these registers set all reserved bits to zero The bit maps and signal definitions are listed as follows National Instruments Corporation C 5 PC DIO 24 PnP User Manual Appendix C Register Level Programming Interrupt Control Register 1 PnP Board Only D7 D6 DS D4 D3 D2 DI DO x x x x x x IRQI IRQO Bit Name Description 2 7 X Reserved bit 1 IRQI PPI Interrupt Request for Port B If this bit and the INTEN bit in Interrupt Control Register 2 are both set the PPI can send an interrupt INTRB to the host computer If this bit is cleared the PPI does not send the interrupt INTRB to the host computer regardless of the setting of INTEN 0 IRQO PPI Interrupt Request for Port A If this bit and the INTEN bit in Interrupt Control Register 2 are both set the PPI can send an interrupt INTRA to the host computer If this bit is cleared the PPI does not send the interrupt INTRA to the host computer regardless of the setting of INTEN PC DIO 24 PnP User Manual C 6 National Instruments Corporation Appendix C Register Level Programming Interrupt Control Register 2 PnP Board Only D7 D6 D5 D4 D3 D2 DI DO X X X X X INTEN X X Bit Name Description 1 0 3 7 X Reserved Bit 2 INTEN Global Interrupt Enable Bit If this bit is set the National Instruments Corporation PC DIO 24PnP can in
26. synchronize data transfers Refer to Chapter 4 Theory of Operation or to Appendix B OKI 82C55A Data Sheet for more detailed information 4 2 National Instruments Corporation Chapter 4 Theory of Operation Digital 1 0 Connector All digital I O is transmitted through a standard 50 pin male connector Pin 49 is connected to 5 V through a resettable protection fuse You can use this 5 V supply to operate I O module mounting racks Even numbered pins are connected to ground See the Optional Equipment section in Chapter 1 Introduction as well as Chapter 3 Signal Connections for additional information National Instruments Corporation 4 3 PC DIO 24 PnP User Manual Specifications Digital 1 0 Appendix This appendix lists the specifications for the PC DIO 24 PnP board These specifications are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C Number of channels 24 I O Compatibility seen TTL Absolute max voltage input rating Vcc SO V stem aie e 0 5 to 45 5 V with respect to GND Handshaking Requires one port Power on state Configured as inputs pulled high or low jumper selectable Data transfers Interrupts programmed I O Digital Logic Levels Input Signals The maximum input logic high
27. to set the device base address and interrupt level PnP systems automatically arbitrate and assign system resources to a PnP product 1 a communications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output random access memory the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale external resistance seconds samples Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ boards in the noisy PC environment the manipulation of signals to prepare them for digitizing samples per second used to express the rate at which a DAQ board samples an analog signal solid state relay PC DIO 24 PnP User Manual Glossary V V volts Vcc Supply voltage for example the voltage a computer supplies to its plug in devices VDC volts direct current Vext external volt VI virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel us
28. 6 to 9096 noncondensing Max with NI DAQ software 50 kbytes s Constant sustainable rate typ 1 to 10 kbytes s Transfer rates are a function of the speed with which your program reads data from or writes data to the board and therefore vary with your system software and application The following primary factors control PC DIO 24 PnP transfer rates e Computer system performance Programming environment register level programming or NI DAQ e Programming language and code efficiency e Execution mode foreground or background with background execution typically using interrupts e Other operations in progress e Application For example you can obtain higher transfer rates in a handshaking or data transfer application requiring an average rate than in a pattern generation data acquisition or waveform generation application requiring a constant sustainable rate The maximum rate shown was obtained using a 233 MHz Pentium computer running NI DAQ and LabWindows CVI software with interrupt based execution and with no other high speed operations in progress National Instruments Corporation A 3 PC DIO 24 PnP User Manual Appendix OKI 82C55A Data Sheet This appendix contains the manufacturer data sheet for the OKI Semiconductor 82C55A CMOS PPI This interface is used on the PC DIO 24 PnP board Copyright OKI Semiconductor 1995 Reprinted with permission of copyright owne
29. 94 5678 Austin TX 78730 5039 Glossary Prefix Meanings Value u micro 106 m milli 10 k kilo 10 M mega 106 Symbols o degrees negative of or minus Q ohms per percent positive of or plus A ampere AC alternating current address character code that identifies a specific location or series of locations in memory AWG American Wire Gauge National Instruments Corporation G 1 PC DIO 24 PnP User Manual Glossary base address BCD C C channel D A DC digital port DIO DMA PC DIO 24 PnP User Manual bit one binary digit either 0 or 1 byte eight related bits of data an eight bit binary number Also used to denote the amount of memory required to store one byte of data a memory address that serves as the starting address for programmable registers busthe group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the ISA and PCI bus All other addresses are located by adding to the base address binary coded decimal Celsius pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels digital to anal
30. BFA Input Buffer for Port A A high setting indicates that data has been loaded into the input latch of port A INTE2 Interrupt Enable Bit for Port A Input Interrupts Setting this bit enables input interrupts from port A of the 82C554A This bit is controlled by setting resetting PCA INTRA Interrupt Request Status for Port A If INTEI and IBFA are high then this bit is high indicating that an interrupt request is pending for port A input transfers If INTE2 and OBFA are high then this bit is high indicating that an interrupt request is pending for port A output transfers IO Input Output These bits can be used for general purpose I O lines if group B is configured for mode 0 If group B is configured for mode 1 refer to the bit explanations shown in the preceding mode 1 sections C 18 National Instruments Corporation Appendix C Register Level Programming At the digital I O connector port C has the following pin assignments when in mode 2 Notice that the status of STBA and the status of ACKA are not included in the port C status word A PC7 PC6 Group A PCS PC4 y PC3 A PC2 Group B PC1 PCO The three port C lines associated with group B function are based on the mode selected for group B that is if group B is configured for mode 0 PC2 PCO function as general purpose input output but if group B is configured for mode 1 input or output PC2 PCO function as handsha
31. Corporation B 7 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet a O MSM82C55A 2RS GS VJS 8 OUTPUT CHARACTERISTICS REFERENCE VALUE 1 Output H Voltage Voj4 vs Output Current 194 Ta 40 85 C Vee 5 0V E o gt o 2 m 2 a 5 6 1 2 3 4 5 Output current lOH mA 2 Output L Voltage VOL vs Output Current 194 Vee 5 0V Ta 40 85 C Output L voltage VOL V Output current Io mA Note The direction of flowing into the device is taken as positive for the output current 196 PC DIO 24 PnP User Manual B 8 National Instruments Corporation Appendix B OKI 82C55A Data Sheet a O MSM82C55A 2RS GS VJS FUNCTIONAL DESCRIPTION OF PIN PA7 PAO P87 PBO Input Output Bidirectional data bus Input and output Function These are three state 8 bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set reset data are trans ferred from CPU to MSMB2C55A Reset input Chip select input Read input Write input This signal is used to reset the control register and al internal registers when it is in high level At this time ports are ail made into the input mode high impedance status ail port latches are cleared to O and all ports groups are set to mode O When the CS is in low level data transmission is
32. Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan United Kingdom United States Telephone 03 9879 5166 0662 45 79 90 0 02 757 00 20 011 288 3336 905 785 0085 514 694 8521 45 76 26 00 09 725 725 11 01 48 14 24 24 089 741 31 30 2645 3186 03 6120092 02 413091 03 5472 29770 02 596 7456 5 520 2635 0348 433466 32 84 84 00 2265886 9 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 512 795 8248 Fax 03 9879 6277 0662 45 79 90 19 02 757 03 11 011 288 8528 905 785 0086 514 694 4399 45 76 26 02 09 725 725 55 01 48 14 24 14 089 714 60 35 2686 8505 03 6120095 02 41309215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 730 43 70 056 200 51 55 02 737 4644 01635 523154 512 794 5678 Click here to comment on this document via the National Instruments website at www natinst com documentation daq Click here to comment on this document via the National Instruments website at Technical Support Form www natinst com documentation daq Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardwar
33. P User Manual l 2 F fax and telephone number support E 2 Fax on Demand support E 2 FTP support E 1 fuse self resetting for 5 V signal 3 7 G GND signal table 3 2 IBF signal description table 3 10 mode 1 input timing 3 12 mode 2 bidirectional timing 3 14 Port C signal assignments table 3 4 IBFA bit Port C C 12 C 18 IBFB bit Port C C 12 installation See also configuration jumper W1 location figure 2 1 PC DIO 24 non PnP D 7 PC DIO 24 PnP 2 1 to 2 2 unpacking the PC DIO 24 PnP 1 7 INTE1 bit Port C C 18 INTE2 bit Port C C 18 INTEA bit Port C C 12 C 15 INTEB bit Port C C 12 C 15 INTEN bit C 7 interrupt control circuitry 4 2 Interrupt Control Register 1 C 6 Interrupt Control Register 2 C 7 interrupt enable PC DIO 24 non PnP factory settings table D 2 jumper settings figure D 6 setting D 6 PC DIO 24 PnP C 1 interrupt handling C 22 to C 23 National Instruments Corporation interrupt level PC DIO 24 non PnP factory settings table D 2 jumper setting figure D 6 setting D 6 to D 7 PC DIO 24 PnP 2 3 interrupt programming examples C 20 to C 22 INTR signal description table 3 11 mode input timing 3 12 mode output timing 3 13 mode 2 bidirectional timing 3 14 Port C signal assignments table 3 4 INTRA bit Port C C 12 C 15 C 18 INTRB bit Port C C 13 C 15 T O bit Port C C 12 C 15 C 18 I O connector digital I O connector 4 3 pin assig
34. PC DIO 24 PnP is a member of the National Instruments family of I O channel expansion boards for ISA computers These boards are designed for high performance low cost data acquisition and control for applications in laboratory testing production testing and industrial process monitoring and control This manual applies to the PC DIO 24PnP and to the PC DIO 24 a non Plug and Play device The boards are identical except for the differences listed in Appendix D Using Your PC DIO 24 Non PnP Board Organization of This Manual The PC DIO 24 PnP User Manual is organized as follows e Chapter 1 Introduction describes the PC DIO 24 PnP lists what you need to get started describes software programming choices optional equipment and custom cables and explains how to unpack the PC DIO 24 PnP e Chapter 2 Installation and Configuration describes how to install and configure the PC DIO 24 PnP e Chapter 3 Signal Connections includes timing specifications and signal connection instructions for the PC DIO 24 PnP I O connector e Chapter 4 Theory of Operation contains a functional overview of the PC DIO 24 PnP board and explains the operation of each functional unit making up the PC DIO 24 PnP e Appendix A Specifications lists the specifications for the PC DIO 24 PnP board e Appendix B OKI 82C55A Data Sheet contains the manufacturer data sheet for the OKI Semiconductor 82C55A CMOS PPI National Instruments Corpor
35. PnP control and status registers This appendix also includes important information about register level programming on the PC DIO 24 PnP along with program examples written in C and assembly language re Note If you plan to do application level programming using software such as LabVIEW LabWindows CVI or NI DAQ with your PC DIO 24 PnP board you need not read this appendix Introduction You can configure your PC DIO 24PnP board to use base addresses in the range of 100 to 3E0 hex Your PC DIO 24PnP board occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3E0 hex The base I O address is software configured and does not require you to manually change any board settings For more information on configuring the PC DIO 24PnP see Chapter 2 Installation and Configuration The PC DIO 24 non PnP board occupies four bytes of address space and must be located on a four byte boundary For more information on configuring the PC DIO 24 see Appendix D Using Your PC DIO 24 Non PnP Board In addition to the 82C554 device the PC DIO 24PnP has two registers that select which interrupt sources are capable of generating interrupts Individual enable bits select whether port A or port B interrupt signals from the 82C55A device generate interrupt requests A master interrupt enable bit determines whether the board can actually send interrupt requests to the host compu
36. Power up State Selection You can power up the PC DIO 24 PnP digital I O lines in a user defined state The PC DIO 24 PnP facilitates user configurable pull up or pull down Each DIO channel is connected to a 100 KQ resistor and can be pulled high or low using jumper W1 You can use W1 to pull all 24 DIO lines high or low However you may want to pull individual lines in different directions To do this properly you must understand the nature of the drive current on those lines and adhere to TTL logic levels High DIO Power up State If you select the pulled high mode each DIO line will be pulled to Vcc approximately 5 VDC with a 100 KQ resistor If you want to pull a specific line low connect between that line and ground a pull down resistor Ry whose value will give you a maximum of 0 4 VDC Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull down task and that the DIO can still drive the line The DIO lines provide a maximum of 2 5 mA at 3 7 V in the high state Also make sure the resistor value is not so large that leakage current from the DIO line along with the current from the 100 kQ pull up resistor drives the voltage at the resistor above a TTL low level of 0 4 VDC National Instruments Corporation 3 7 PC DIO 24 PnP User Manual Chapter 3 Signal Connections PC DIO 24 PnP User Manual PC DIO 24 PnP 45V 100 kQ 82C55A Digital I O Line
37. RL Figure 3 3 DIO Channel Configured for High DIO Power up State with External Load Example At power up the board is configured for input and by default all DIO lines are high To pull one channel low follow these steps 1 Install a load Rj Remember that the smaller the resistance the greater the current consumption and the lower the voltage 2 Using the following formula calculate the largest possible load to maintain a logic low level of 0 4 V with a minimum reduction to the DIO drive current V I R gt R V I where V 0 4 V Voltage across Ry I 46 HA 11HA 34 6 V across the 100 KQ pull up resistor and 11 LA max leakage current Therefore RL 7 0 kQ 0 4 V 57 A This resistor value 7 0 KQ provides a maximum of 0 4 V on the DIO line at power up You can substitute smaller resistor values to lower the voltage or to provide a margin for Vcc variations and other factors However smaller values will draw more current leaving less drive current for other circuitry connected to this line The 7 0 kQ resistor reduces the amount of logic high source current by 0 4 mA with a 2 8 V output 3 8 National Instruments Corporation Chapter 3 Signal Connections Low DIO Power up State If you select pulled low mode each DIO line will be pulled to GND 0 VDC using a 100 kQ resistor To pull a specific line high connect a pull up resistor that will give you a minimum of 2 8 VDC Using the largest pos
38. able in examples 1 5 or 6 because these configurations use PC4 for handshaking C 20 National Instruments Corporation g iregl Appendix C Register Level Programming Board located at address 180 Offset Offset Offset Offset Offset Offset for for for for for for ireg2 port A port B port C CNFG Interrupt Reg 1 Interrupt Reg 2 Variable to store data read from a port Main define BASE ADDRESS 0x180 define PORTAoffset 0x00 define PORTBoffset 0x01 define PORTCoffset 0x02 define CNFGoffset 0x03 define IREGloffset 0x14 define IREG2offset 0x15 unsigned int porta portb portc cnf char valread Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE ADDRESS CNFGoffset iregl BASE_ADDRESS IREGloffset ireg2 BASE ADDRESS IREG2offset EXAMPLE 1 Set up interrupts for mode 1 input for port A Enable the outp cnfg 0xBO outp outp ireg2 0x04 outp cnfg 0x09 ireg1 0x01 appropriate interrupt bits Port A is an input in mode 1 Set PC4 to enable interrupts from 82C55A Set IRQO to enable port A interrupts EN bit Set INTI EXAMPLE 2 Set up interrupts f
39. age to a metal part of your PC chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer e Never touch exposed connector pins National Instruments Corporation 1 7 PC DIO 24 PnP User Manual Chapter Installation and Configuration This chapter describes how to install and configure the PC DIO 24 PnP Installation ir Note Install your driver software before installing your hardware Refer to your NI DAQ release notes for software installation instructions Li ri z 4 i Bof E N faf T eee a o us E PC DID 24 PNP we W1 Figure 2 1 Jumper W1 Location Note The PC DIO 24 PnP uses 100 kQ resistors for polarity selection at power up You can use jumper Wl to select whether data signals are pulled up to Vcc 5 VDC factory default or pulled down to GND Figure 2 1 shows jumper W1 For more information see the Digital I O Power up State Selection section in Chapter 3 Signal Connections You can install the PC DIO 24 PnP in any unused 8 or 16 bit expansion slot in your computer The following are general install
40. als in the 3 bit port The control word written to the CNFG Register to configure port A for input in mode is shown as follows Use bits PC6 and PC7 of port C as extra input or output lines D7 D6 D5 D4 D3 D2 D1 DO 1 0 1 1 1 0 X X X u Port C bits PC6 and PC7 1 input 0 output National Instruments Corporation C 11 PC DIO 24 PnP User Manual Appendix C Register Level Programming The control word written to the CNFG Register to configure port B for input in mode 1 is shown as follows Notice that port B does not have extra input or output lines left from port C when ports A and B are both enabled for handshaking During a mode 1 data read transfer the status of the handshaking lines and interrupt signals can be obtained by reading port C The port C status word bit definitions for an input transfer are shown as follows Port C status word bit definitions for input port A and port B D7 D6 D5 D4 D3 D2 DI DO 1 0 1 0 IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7 6 I O Input Output These bits can be used for general purpose I O when port A is in mode 1 input If these bits are configured for output the port C bit set reset function must be used to manipulate them 5 IBFA Input Buffer for Port A A high setting indicates that data has been loaded into the input latch for port A 4 INTEA Interrupt Enable Bit for Port A Setting this bit enables interrupts fro
41. and output logic high voltages assume a Vcc supply voltage of 5 0 V Level Min Max Input logic high voltage 2 2V 5 3 V Input logic low voltage 0 3 V 0 8 V Input high current 11 0 HA Vin 2 5 V WI set to pullup National Instruments Corporation A 1 PC DIO 24 PnP User Manual Appendix A Specifications Level Min Max Input high current 65 uA Vi 2 5 V WI set to pulldown Input logic low current 65 HA Vin 0 V WI set to pullup Input logic low current 11 LA Vin 0 V W1 set to pulldown Output Signals Pin 49 at 4 65 to 5 25 VDC 1 0 A max Level Min Max Output logic high voltage 3 7 V 5 0 V Igi 2 5 mA Output logic high voltage 2 7 V 5 0 V Ioh 4 mA Output logic low voltage OV 0 4 V 1 2 5 mA Output logic low voltage OV 0 5 V Igj 4 mA Power Requirement 5 VDC 410 sane 0 45 A typ 1 A max Physical Dimensions 11 7 by 10 6 cm 4 6 by 4 2 in I O connector 000 cece eee cece eeeeeeeeeees 50 pin male ribbon cable connector PC DIO 24 PnP User Manual A 2 National Instruments Corporation Environment Transfer Rates Appendix A Specifications Operating temperature 0 to 70 C Storage temperature 55 to 150 C Relative humidity 59
42. ation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings National Instruments Corporation 2 1 PC DIO 24 PnP User Manual Chapter 2 Installation and Configuration Turn off and unplug your computer Remove the I O channel top cover or access port Remove the expansion slot cover on the computer back panel Insert the PC DIO 24 PnP into any 8 or 16 bit slot It may be a tight fit but do not force the board into place oM es 5 Screw the PC DIO 24 PnP mounting bracket to the computer back panel rail Visually verify the installation Replace the computer cover 8 Plugin and turn on your computer The PC DIO 24 PnP board is now installed Hardware Configuration Plug and Play PC DIO 24 PnP User Manual The PC DIO 24PnP is fully compatible with the industry standard Intel Microsoft Plug and Play Specification A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the PC DIO 24PnP base I O address and interrupt channel The Configuration Manager receives all of the resource requests at startup compares the available resources to those requested and assigns the available resources as efficiently as possible to the Plug and Play boards Application software can query the Configuration Manager to determine the resources assigned to each board without y
43. ation ix PC DIO 24 PnP User Manual About This Manual e Appendix C Register Level Programming describes in detail the address and function of each of the PC DIO 24 PnP control and status registers e Appendix D Using Your PC DIO 24 Non PnP Board describes the differences between the PC DIO 24 and PC DIO 24PnP boards the PC DIO 24 board configuration and the PC DIO 24 installation into your computer e Appendix E Customer Communication contains forms you can use to request help from National Instruments or to comment on our products e The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics symbols and terms e The Index alphabetically lists the topics in this manual including the page where you can find each one Conventions Used in This Manual JN 82C55A lt gt bold bold italic italic PC DIO 24 PnP User Manual The following conventions are used in this manual This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash 82C55A refers to the OKI Semiconductor 82C55A CMOS PPI Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for examp
44. c cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE ADDRESS PORTCoffset BASE ADDRESS CNFGoffset cnfg EXAMPLE 1 outp cnfg 0x80 Ports A B and C are outputs outp porta 0x12 Write data to port A outp portb 0x34 Write data to port B PC DIO 24 PnP User Manual C 10 National Instruments Corporation Appendix C Register Level Programming outp port 0x56 Write data to port C EXAMPLE 2 outp cnfg 0x90 Port A is input ports B and C are outputs outp portb 0x22 Write data to port B outp portc 0x55 Write data to port C valread inp porta Read data from port A EXAMPLE 3 outp cnfg 0x82 Ports A and C are outputs port B is an input EXAMPLE 4 outp cnfg 0x89 Ports A and B are outputs port C is an input Mode 1 Strobed Input In mode 1 the digital I O bits are divided into two groups group A and group B Each of these groups contains one 8 bit port and one 3 bit control data port The 8 bit port can be either an input or an output port and the 3 bit port is used for control and status information for the 8 bit port The transfer of data is synchronized by handshaking sign
45. ctory set jumper and switch settings table D 2 interrupt selection D 5 to D 7 parts locator diagram D 3 PC DIO 24 PnP base I O address and interrupt selection 2 3 general requirements C 1 Plug and Play configuration 2 2 Configuration Manager 2 2 control words control word formats figure C 4 mode strobed input figure C 11 to C 12 PC DIO 24 PnP User Manual Index mode 1 strobed output figure C 13 mode 2 bidirectional bus figure C 17 Port C set reset control words table C 5 custom cables 1 5 to 1 6 customer communication xiii E 1 to E 2 D DATA signal description table 3 11 mode 1 input timing 3 12 mode 1 output timing 3 13 mode 2 bidirectional timing 3 14 digital I O connector 4 3 digital I O power up state selection 3 7 to 3 10 high DIO power up state 3 7 to 3 8 low DIO power up state 3 9 to 3 10 digital I O signal connections 3 4 to 3 6 input specifications referenced to GND 3 4 output specifications referenced to GND 3 5 typical digital I O applications figure 3 6 digital I O specifications A 1 digital logic level specifications input signals table A 1 to A 2 output signals table A 2 documentation conventions used in manual x xi National Instruments documentation xii organization of manual ix x related documentation xiii E electronic support services E 1 e mail support E 2 environment specifications A 3 equipment optional 1 5 to 1 6 PC DIO 24 Pn
46. d against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this
47. data from the pin has been fetched into the input latch This signal turns to high level at the falling edge of the STB and low level at the ris ing edge of the RD INTR interrupt request output This signal is used to interrupt the CPU and its operation in the same as in mode 1 There are two INTE flip flops internally available for input and output to select either interrupt of input or output operation The INTE1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6 INTE2 is used to control the interrupt request for the in put operation and it can be set by the bit set for PCA National Instruments Corporation Appendix B OKI 82C55A Data Sheet a 1 0 MSM82C55A 2RS GS VJS Mode 2 1 0 Operation Port C Function Allocation in Mode 2 Following is an example of the relation between the control word and the pin when used in mode 2 When input in mode 2 for group A and in mode 1 for group B As all of 8 bits of port C be come control pins in this case D3 and DO bits are treated as Don t Care When group A is set to mode 2 this bit is treated as Don t Care PE No 1 0 specification is required for mode 2 since it is a bidirec tional operation This bit is therefore treated as Don t Care Group mode 2 Group B mode 1 input 203 National Instruments Corporation B 15 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data
48. dex software programming choices 1 2 to 1 4 See also register level programming ComponentWorks 1 2 LabVIEW and LabWindows CVI application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 VirtualBench 1 3 specifications digital I O A 1 digital logic levels A 1 to A 2 environment A 3 physical A 2 power requirements A 2 transfer rates A 3 STB signal description table 3 10 mode input timing 3 12 mode 2 bidirectional timing 3 14 Port C signal assignments table 3 4 switch settings See jumper and switch settings T technical support E 1 to E 2 telephone and fax number support E 2 theory of operation 4 1 to 4 3 82C55A Programmable Peripheral Interface 4 2 PC DIO 24 PnP User Manual 1 6 block diagram 4 1 bus interface 4 2 bus transceivers 4 2 digital I O connector 4 3 interrupt control circuitry 4 2 PC I O channel control circuitry 4 1 to 4 2 timing specifications 3 10 to 3 14 mode 1 input timing 3 12 mode 1 output timing 3 13 mode 2 bidirectional timing 3 14 signals table 3 10 to 3 11 transfer rate specifications A 3 U unpacking the PC DIO 24 PnP 1 7 V VirtualBench software 1 3 W WR signal description table 3 11 mode 1 output timing 3 13 mode 2 bidirectional timing 3 14 National Instruments Corporation
49. e by setting a jumper on W2 To use the interrupt capability of the board select an interrupt line and place the jumper in the appropriate position The default interrupt line is IRQ5 To change to another line remove the jumper from IRQ5 and place it on the pins for another request line Figure D 4 shows the default factory setting for IRQS W2 Figure D 4 Interrupt Jumper Setting for IRQ5 Factory Setting D 6 National Instruments Corporation Appendix D Using Your PC DIO 24 Non PnP Board The PC DIO 24 uses a tristate driver to drive its selected interrupt line The PC DIO 24 can therefore share an interrupt line if your system and your other devices allow Installation Install the PC DIO 24 as described in Chapter 2 Installation and Configuration If you have an ISA class computer and you are using a configurable software package such as NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings If you have an EISA class computer you need to update the computer resource allocation or configuration table by reconfiguring your computer See your computer user manual for information about updating the configuration table National Instruments Corporation D 7 PC DIO 24 PnP User Manual Click here to comment on this document via the National Instruments website at www natinst com documentation daq Appendix Customer Communication For your conven
50. e or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem PC DIO 24 PnP Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products DAQ hardware Interrupt level of hardware Base I O address of hardware Programming choice National Instruments application software version Other boards in system Base I O addresses of other boards DMA chan
51. enabled with CPU When it is in high level the data bus is made into the high impedance status where no write nor read operation is performed internal registers hold their previous status however When RD is in low level data is transferred from MSM82C55A to CPU When WR is in tow level data or control words are transferred from CPU to MSMB2C55A Port select input address Input and output Input and output PC PCO BASIC FUNCTIONAL DESCRIPTION Input and output By combination of AO and At either one is selected from among port A port B port C and control register These pins are usually connected to low order 2 bits of the address bus These are universal 8 bit I O ports The direction of inputs out puts can be determined by writing a control word Especially port can be used as a bidirectional port when it is set to mode 2 These are universal 8 bit 1 0 ports The direction of inputs out puts can be determined by writing a control word These are universal 8 bit 1 0 ports The direction of inputs out puts can be determined by writing a control word as 2 ports with 4 bits each When port A or port B is used in mode 1 or mode 2 port A only they becoma control pins Especially whan port C is used as an output port each bit can be set reset independently Group A and Group 8 5 V power supply When used in mode 1 or mode 2 however port C has bits to be defined as ports f
52. ench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data to extended memory NI DAQ also internally addresses many of the complex issues between the computer and the plug in device such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Figure 1 1 illustrates the relationship between NI DAQ and your National Instruments application software National Instruments Corporation 1 3 PC DIO 24 PnP User Manual Chapter 1 Introduction ComponentWorks Conventional LabVIEW Programming Environment LabWindows CVI or VirtualBench NI DAQ Driver Software Personal rie a Computer or Broware Workstation Figure 1 1 The Relationship between the Programming Environment
53. ents Corporation 3 1 PC DIO 24 PnP User Manual Chapter 3 Signal Connections PC DIO 24 PnP User Manual PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 5 V O AJN 8 OO Ny A j 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Figure 3 1 Digital 1 0 Connector Pin Assignments 3 2 National Instruments Corporation Chapter 3 Signal Connections Signal Descriptions Table 3 1 describes the PC DIO 24 PnP signals Table 3 1 Signal Descriptions Signal Pin Name Description 1 3 5 7 9 11 PC lt 7 0 gt Port C Bidirectional data lines for 13 15 port C PC7 is the MSB PCO the LSB 17 19 21 23 25 PB lt 7 0 gt Port B Bidirectional data lines for 27 29 31 port B PB7 is the MSB PBO the LSB 33 35 37 39 41 PA lt 7 0 gt Port A Bidirectional data lines for 43 45 47 port B PA7 is the MSB PAO the LSB 49 5 V 5 Volts This pin is fused for up to 1 A at 4 65 to 5 25 V All even numbe
54. er interface and a block diagram program PC DIO 24 PnP User Manual G 6 National Instruments Corporation Special Characters 5 V signal connection to ground or other voltage source caution 3 7 description table 3 3 power connections 3 7 self resetting fuse 3 7 82C55A Programmable Peripheral Interface capabilities 1 1 data sheet B 1 to B 17 modes of operation See modes of operation 82C55A overview 4 2 register description C 3 to C 5 control word formats figure C 4 Port C set reset control words table C 5 A ACK signal description table 3 10 mode 1 output timing 3 13 mode 2 bidirectional timing 3 14 Port C signal assignments table 3 4 address setting See base I O address settings application software descriptions 1 2 to 1 3 base I O address settings PC DIO 24 non PnP D 3 to D 5 example settings figure D 4 National Instruments Corporation Index example settings with corresponding base I O address and address space table D 5 factory settings table D 2 in use by other equipment note D 3 PC DIO 24 PnP selecting 2 3 valid addresses C 1 block diagram of PC DIO 24 PnP 4 1 board configuration See configuration bulletin board support E 1 bus interface 4 2 bus transceivers 4 2 C cables custom 1 5 to 1 6 ComponentWorks software 1 2 configuration See also installation PC DIO 24 non PnP D 2 to D 7 base I O address settings D 3 to D 5 fa
55. figure C 14 Port C pin assignments figure C 16 Port C status word bit definitions C 15 programming example C 16 to C 17 mode 2 bidirectional bus C 17 to C 20 control word written to CNFG Register figure C 17 Port C pin assignments figure C 19 Port C status word bit definitions C 18 programming example C 19 to C 20 National Instruments Corporation Index overview C 1 to C 2 register descriptions C 3 to C 7 82C55A C 3 to C 5 control word formats figure C 4 interrupt control registers C 5 to C 7 Port C set reset control words table C 5 register map C 3 requirements for getting started 1 2 S self resetting fuse for 5 V signal 3 7 signal connections digital I O power up state selection 3 7 to 3 10 high DIO power up state 3 7 to 3 8 low DIO power up state 3 9 to 3 10 digital I O signal connections 3 4 to 3 6 input specifications referenced to GND 3 4 output specifications referenced to GND 3 5 typical digital I O applications figure 3 6 I O connector pin assignments figure 3 2 Port C pin assignments description 3 3 signal assignments table 3 4 power connections 3 7 signal descriptions table 3 3 timing specifications 3 10 to 3 14 mode 1 input timing 3 12 mode 1 output timing 3 13 mode 2 bidirectional timing 3 14 signals table 3 10 to 3 11 single bit set reset feature overview C 9 Port C set reset control words table C 5 PC DIO 24 PnP User Manual In
56. he appropriate enable bit in Interrupt Control Register 1 for example if you selected both mode 2 interrupts for port A you would set IRQO in order to interrupt the host computer External signals can be used to interrupt the PC DIO 24 PnP when port A or port B is in mode 0 and the low nibble of port C is configured for input If port A is in mode 0 use PC3 to generate an interrupt if C 22 National Instruments Corporation Appendix C Register Level Programming port B is in mode 0 use PCO to generate an interrupt Once you have configured the 82C55A set the corresponding interrupt enable bit in Interrupt Control Register 1 If you are using PC3 set IRQO if you are using PCO set IRQ1 When the external signal becomes logic high an interrupt request occurs Although the host computer s interrupt monitoring circuitry is triggered by the positive going edge of the interrupt signal the signal must remain high until the interrupt routine has been entered and interrupts have been masked out Make sure your external interrupt signal meets these qualifications To disable the external interrupt clear the appropriate IRQ bit or clear the INTEN bit National Instruments Corporation C 23 PC DIO 24 PnP User Manual Appendix Using Your PC DIO 24 Non PnP Board This appendix describes the differences between the PC DIO 24 and PC DIO 24PnP boards the PC DIO 24 board configuration and the PC DIO 24 installation into you
57. hen INTEA and OBFA are high this bit is high indicating that an interrupt request is pending for port A Interrupt Enable Bit for Port B Setting this bit enables interrupts from port B of the 82C55A This bit is controlled by setting resetting PC2 Output Buffer for Port B A low setting indicates that the CPU has written data to port B Interrupt Request Status for Port B When INTEB and OBFB are high this bit is high indicating that an interrupt request is pending for port B At the digital I O connector port C has the following pin assignments when in mode 1 output Notice that the status of ACKA and the status of ACKB are not included when port C is read National Instruments Corporation C 15 PC DIO 24 PnP User Manual Appendix C Register Level Programming Main define define define define define ESS BASE_ADDR PORTAoffset PORTBoffset PORTCoffset CNFGoffset unsigned int porta char valread pc7 o ra nr PC6 ACKA 4 Group A PC5 O PC4 O HM PC3 INTRA 1 PC2 ACKB Group B PC1 OBFB y eco INTRO Figure C 3 Port C Pin Assignments Mode 1 Output Mode 1 Output Programming Example The following example shows how to configure PPI A for various combinations of mode 1 output This code is strictly an example and is not intended to be used without modificati
58. ich are latched e The 3 bit ports are used for control and status of the 8 bit data ports e Interrupt generation and enable disable functions are available C 8 National Instruments Corporation Mode 0 Basic 1 0 Appendix C Register Level Programming Mode 2 Use this mode for communication over a bidirectional 8 bit bus Handshaking signals are used in a manner similar to mode 1 Mode 2 is available for use in group A only port A and the upper portion of port C Other features of this mode include the following e One 8 bit bidirectional port port A and a 5 bit control status port port C e Latched inputs and outputs e Interrupt generation and enable disable functions Single Bit Set Reset Feature You can set or reset any of the eight bits of port C with one control word This feature generates control signals for port A and port B when these ports are operating in mode 1 or mode 2 Use mode 0 for simple I O functions no handshaking for each of the three ports You can assign each port as an input or an output port The 16 possible I O configurations are shown in Table C 3 Notice that bit 7 of the control word is set when programming the mode of operation for each port Table C 3 Mode 0 1 0 Configurations Control Word Group A Group B Bit Number 76543210 Port A Port C Port B Port C 0 10000000 Output Output Output Output 1 10000001 O
59. idth 100 T8 ACK 0 to output 150 T9 ACK 1 to output float 20 250 T10 RD 1 to IBF 0 mE 150 AII timing values are in nanoseconds PC DIO 24 PnP User Manual Figure 3 7 Mode 2 Timing Specification for Bidirectional Transfers 3 14 National Instruments Corporation Chapter Theory of Operation This chapter contains a functional overview of the PC DIO 24 PnP board and explains the operation of each functional unit making up the PC DIO 24 PnP Functional Overview The block diagram in Figure 4 1 illustrates the key functional components of the PC DIO 24 PnP board XN N EN M 8 Bus PB E Transceivers 82C55A 7 2 PPI 8 o S Bus Interface 8 5 Plug and Play PC 9o pow T Oo Address Interrupt 8 B Decode Circuitry PC3 B Interrupt PCO e Control Circuitry 5V Pus gt N A 1AFuse 7 Figure 4 1 PC DIO 24 PnP Block Diagram The PC I O channel consists of an address bus a data bus interrupt lines and several control and support signals Control and data transfers to the system microprocessor are asynchronous National Instruments Corporation 4 1 PC DIO 24 PnP User Manual Chapter 4 Theory of Operation Bus Transceivers Bus Interface The bus transceivers send and receive data lines and other signals to and from the PC I O channel The PC DIO 24PnP Pl
60. ience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no
61. ion of input output of high order 4 bits of port C O Output Input 0 Output 1 Input 0 Mode 0 1 Mode 1 0 Output 1 Input 0 Output 1 Input Mode definition of group A National Instruments Corporation Don t Care Contro word identification flag Be sure to set to 0 for bit set reset When set to 1 it becomes the control word to define a mode and input output Interrupt Control Function When the MSM82C55A is used in mode 1 or mode 2 the interrupt signal for the CPU is provided The interrupt request signal is output from port C When the internai flip flop INTE is set beforehand at this time the desired interrupt request signal is output When it is reset beforehand however the interrupt request sig nal is not output The set reset of the internal flip flop is made by the bit set reset operation for port C virtually Bit set gt INTE is set gt Interrupt allowed Bit reset gt INTE is reset gt Interrupt inhibited Appendix B OKI 82C55A Data Sheet Definition of set reset for a desired bit Definition of bit wanted to be set or reset Operational Description by Mode m O MSM82C55A 2RS GS VJS 0 Rest 1 Mode 0 Basic input output operation Mode 0 makes the MSM82C55A operate as a bas ic input port or output port No control signals such as interrupt request etc are required in this mode All 24 bits can be used as two 8 b
62. it ports and two 4 bit ports Sixteen combinations are then possible for inputs outputs The inputs are not latched but the outputs are High Order 4 Bits of Port C Control Word Group A Group B Low Order 4 Bits of Port C Output input Output o Note When used in mode 0 for both groups A and B National Instruments Corporation B 11 input 199 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet 1 0 MSM82C55A 2RS GS VJS 2 Mode 1 Strobe input output operation in mode 1 the strobe interrupt and other controt signals are used when input output operations are made from a specified port This mode is available for both groups A and B In group A at this time port A is used as the data line and port C as the con troi signal Following is a descrption of the input operation in mode 1 STB Strobe inpet When this signal is low level the data output from terminal to port is fetched into the internal latch of the port This can be made independent from the CPU and the data is not output to the data bus until the RD signal arrives from the CPU IBF Input buffer full flag output This is the response signal for the STB This signal when turned to high level indicates that data is fetched into the input latch This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD
63. king lines as shown in the preceding mode 1 sections Figure C 5 Port C Pin Assignments Mode 2 Mode 2 Programming Example The following example shows how to configure PPI A for mode 2 input and output and how to use the handshaking signals to control data flow This code is strictly an example and is not intended to be used without modification in a practical situation Main define BASE ADDRESS 0x180 Board located at address 180 define PORTAoffset 0x00 Offset for port A define PORTBoffset 0x01 Offset for port B define PORTCoffset 0x02 Offset for port C define CNFGoffset 0x03 Offset for CNFG unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE ADDRESS PORTCoffset National Instruments Corporation C 19 PC DIO 24 PnP User Manual Appendix C Register Level Programming cnfg BASE ADDR EXAMPLE 1 outp cnfg 0xC0 while inp portc outp porta 0x67 while inp portc ESS CNFGoffset Port A is in mode 2 amp 0x80 Wait until OBFA is set indicating that the data last written to port A has been read ey Write the data to port A amp 0x20 Wait until IBFA is set indicating that da
64. ko 100 ka 3100 ko WW 1 143 PPI Port A o 145 PA lt 3 0 gt Oo 47 e 100 ka 3 00 ka 3 00 ka E 00 ka Jill Lr o 69 PPI TTL Signal 71 Port B d PB 7 4 45V MW 73 Switch 50 100 GND 1 0 Connector PC DIO 24 PnP Figure 3 2 Digital 1 0 Connections In Figure 3 2 port A is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 3 2 Digital output applications include sending TTL signals and driving external devices such as the LED shown in this figure PC DIO 24 PnP User Manual 3 6 National Instruments Corporation Chapter 3 Signal Connections Power Connections AN Caution Pin 49 of the I O connector is connected to the 5 V supply from the PC power supply This pin is referenced to GND and can be used to power external digital circuitry This 5 V supply has a 1 A self resetting protection fuse in series Simply remove the circuit causing the heavy current load and the fuse will reset itself Power rating 1 A at 4 65 to 5 25 V Under no circumstances should this 5 V power pin be connected directly to ground or to any other voltage source on the PC DIO 24 PnP or any other device Doing so may damage the PC DIO 24 PnP and the PC National Instruments is NOT liable for damage resulting from such a connection Digital 1 0
65. lanation If you have the non PnP version of the PC DIO 24 PnP see Appendix D Using Your PC DIO 24 Non PnP Board for the differences between the PnP version and the non PnP version You can use the PC DIO 24 PnP in a wide range of digital I O applications With the PC DIO 24 PnP you can use your PC as a digital I O system controller for laboratory testing production testing and industrial process monitoring and control Detailed specifications of the PC DIO 24 PnP are in Appendix A Specifications National Instruments Corporation 1 1 PC DIO 24 PnP User Manual Chapter 1 Introduction What You Need to Get Started To set up and use your PC DIO 24 PnP you will need the following CL PC DIO 24PnP or PC DIO 24 board Q PC DIO 24 PnP User Manual C One of the following software packages and documentation BridgeVIEW ComponentWorks LabVIEW for Windows LabWindows CVI Measure NI DAQ for PC compatibles VirtualBench Q Your computer Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Application Software PC DIO 24 PnP User Manual ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building
66. le PB lt 7 0 gt Bold text denotes the names of menus menu items parameters dialog boxes dialog box buttons or options icons windows Windows 95 tabs or LEDs Bold italic text denotes a note caution or warning Italic text denotes emphasis a cross reference or an introduction to a key concept X National Instruments Corporation monospace NI DAQ PC PC DIO 24 PnP PC DIO 24PnP PC DIO 24 PnP non PnP PPI SCXI About This Manual Text in this font denotes text or characters that you should enter literally from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from programs NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted PC refers to the IBM PC XT the IBM PC AT and compatible ISA bus computers unless otherwise noted PC DIO 24 PnP refers to both the Plug and Play and non Plug and Play compatible versions of the board PC DIO 24PnP refers to the Plug and Play version of the board PC DIO 24 refers to the non Plug and Play version of the board PnP Plug and Play refers to a device that is fully compatible with the industry standard Plug and Play ISA Specification Non PnP refers to a device that requires yo
67. m port A of the 82C55A This bit is controlled by setting resetting PC4 3 INTRA Interrupt Request Status for Port A When INTEA and IBFA are high this bit is high indicating that an interrupt request is pending for port A 2 INTEB Interrupt Enable Bit for Port B Setting this bit enables interrupts from port B of the 82C55A This bit is controlled by setting resetting PC2 1 IBFB Input Buffer for Port B A high setting indicates that data has been loaded into the input latch for port B PC DIO 24 PnP User Manual C 12 National Instruments Corporation Main define define define define define INTRB Appendix C Register Level Programming Interrupt Request Status for Port B When INTEB and IBFB are high this bit is high indicating that an interrupt request is pending for port B At the digital I O connector port C has the following pin assignments when in mode 1 input Notice that the status of STBA and the status of STBB are not included in the port C status word Group A A Group B gt lt v Figure C 2 Port C Pin Assignments Mode 1 Input Mode 1 Input Programming Example The following example shows how to configure PPI A for various combinations of mode 1 input This code is strictly an example and is not intended to be used without modification in a practical situation BASE ESS PORT PORI PORI _ADDR TAoffse
68. nal Instruments Corporation Mode 1 Output Timing The following figure illustrates the timing specifications for an output transfer in mode 1 Chapter 3 Signal Connections Tg WR Rm i T4 i f e oar LE ne INTR o T5 i ACK H DATA X mo Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK pulse width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds Figure 3 6 Mode 1 Timing Specification for Output Transfers National Instruments Corporation PC DIO 24 PnP User Manual Chapter 3 Signal Connections Mode 2 Bidirection al Timing The following figure illustrates the timing specifications for bidirectional transfers in mode 2 WR a oOo OBF NN INTR 4 O T7 i ACK i T3 l STB lt gt 1 TAF Piu lt gt i 1 1 i IBF 0 RD T2 1 TS T8 11 To lt gt A to oe ES Name Description Minimum Maximum Tl WR 1 to OBF 0 mE 150 T2 Data before STB 1 20 T3 STB pulse width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 mE 150 T7 ACK pulse w
69. nels of other boards Interrupt levels of other boards Other Products Computer make and model Microprocessor Clock frequency or speed Type of video board installed Operating system version Operating system mode Programming language Programming language version Other boards in system Base I O addresses of other boards Interrupt enable lines of other boards Interrupt levels of other boards Click here to comment on this document via the National Instruments website at www natinst com documentation daq Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title PC DIO 24 PnP User Manual Click here to comment on this document via the Edition Date National Instruments website at February 1998 5 www natinst com documentation daq Part Number 320288C 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Fax Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 7
70. ng edge of WR when the INTEg is set INTEA of group A is set when the bit for PC is set while INTEg of group B is set when the bit for PC is set Mode 1 output National Instruments Corporation Appendix B OKI 82C55A Data Sheet O MSM82C55A 2RS GS VJS Port C Function Allocation in Mode 1 Combination of Input Output Group A Input Group A Input Group A Output Group A Output Group B Input Group B Output Group B Input Group B Output Note 1 0 is a bit not used as the control signal but it is available as a port of mode 0 Examples of the relation between the control Words and pins when used in mode 1 is shown below a When group A is mode 1 output and group B is mode 1 input Control word As all of PCo PC4 bits become a control Selection of 1 0 pin in this case this of PC4 and PCs bit is Don t Care when not defined as a control pin 12 Input 0 Output OBFA ACKA INTRA vo Group A Mode 1 output Group B Mode 1 input STBg IBFp INTRg 201 National Instruments Corporation B 13 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet a 1 0 MSM amp 2C55A 2RS GS VJS a b When group A is mode 1 input and group B is mode 1 output Selection of 1 O of PC6 and PC7 when not de fined as a control pin 1 Input 0 Output STBA IBFA INTRA 2 1 input 1 0 Group A Mode 1 inp Group B Mode 1 output OBFg ACKg INTRE 3 Mode 2
71. njury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment FCC DOC Radio Frequency Interference Class A Compliance This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC This equipment has been tested and found to comply with the following two regulatory agencies Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the
72. nments figure 3 2 I O signal Port C signal assignments table 3 4 IRQO bit C 6 IRQI bit C 6 J jumper and switch settings base I O address settings D 3 to D 5 example settings figure D 4 example settings with corresponding base I O address and address space table D 5 in use by other equipment note D 3 factory settings table D 2 interrupt enable settings D 6 interrupt level settings D 6 to D 7 jumper W1 data signal settings note 2 1 location of figure 2 1 National Instruments Corporation I 3 Index jumper W2 location figure D 3 settings table D 2 jumper W3 location figure D 3 settings table D 2 L LabVIEW and LabWindows CVI application software 1 2 to 1 3 manual See documentation modes of operation 82C55A mode 0 basic I O C 9 to C 11 configurations table C 9 to C 10 overview C 8 programming example C 10 to C 11 purpose and use C 8 mode 1 input timing 3 12 mode 1 output timing 3 13 mode 1 strobed input C 11 to C 14 control words written to CNFG register figures C 11 to C 12 Port C pin assignments figure C 13 Port C status word bit definitions C 12 to C 13 programming example C 13 to C 14 purpose and use C 8 mode 1 strobed output C 14 to C 17 control words written to CNFG register figure C 14 Port C pin assignments figure C 16 Port C status word bit definitions C 15 programming example C 16 to C 17 purpose and use C 8 mode 2 bidirecti
73. nt acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation BridgeVIEWTM ComponentWorks CVITM LabVIEW MeasureTM NI DAQ and VirtualBench are trademarks of National Instruments Corporation Product and company names referred to in this document are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious i
74. o or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI manual sets and the NI DAQ documentation After you set up your hardware system use either the application software documentation or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides or accessory board user manuals They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI Chassis Manual Read this manual for maintenance information on the chassis and for installation instructions Xii National Instruments Corporation About This Manual Related Documentation The following documents contain information that you may find helpful as you read this manual e Your computer technical reference manual e Plug and Play ISA Specification Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applica
75. oating of port Port A in mode 2 KD 20 250 i E Lea Detay Time from the rising edge of WR to the failing edge of OBF wos 150 ens Delay Time from the fatling edge of ACK to the rising edge of OBF ta0B 150 ng Detay Time from the falling edge of STB to the i 150 ns a rising edge of IBF SIB 7 Delay Time from the rising edge of RD to the falling 150 edge of IBF RIB s Delay Time from the falling edge of RD to the 200 FE fatling edge of INTR RIT e dd auda Delay Time from the rising edge of STB to the 7 150 as rising edge of INTR iE SIT Delay Time from the rising edge of ACK to the x 150 ng rising edge of INTR AIT Delay Time from the falling edge of WR to the T 250 falling edge of INTR WIT s Note Timing is measured at V_ 0 8 V and V 22 V far both input and outputs 193 National Instruments Corporation B 5 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet m 1 O MSM82C55A 2RS GS VJS 18 AAA aii Basic input Operation Mode 0 Port input CS A1 Ao Basic Output Operation Mode 0 WR D5 Do CS A1 Ao Port output Strobe Input Operation Mode 1 Port input 194 PC DIO 24 PnP User Manual B 6 National Instruments Corporation Appendix B OKI 82C55A Data Sheet m O MSM82C55A 2RS GS VJS Strobe Output Operation Mode 1 ACK Port output Bidirectional Bus Operation Mode 2 195 National Instruments
76. og data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer direct current See port digital input output direct memory access G 2 National Instruments Corporation ft H h handshaked digital I O hardware hex in lin Tout interrupt interrupt level I O IRQ National Instruments Corporation G 3 Glossary feet hour a type of digital acquisition generation where a device or module accepts or transfers data after a digital pulse has been received Also called latched digital I O the physical components of a computer system such as the circuit boards plug in boards chassis enclosures peripherals and cables hexadecimal hertz the number of scans read or updates written per second inches input current output current a computer signal indicating that the CPU should suspend its current task to service a designated activity the relative priority at which a device can interrupt input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces interrupt request
77. on in a practical situation 0x180 0x00 0x01 0x02 0x03 portb portc cnfg 35 Board located at address 180 Offset Offset Offset Offset for port A for port B for port for CNFG Variable to store data read from a port addresses Calculate regist porta BASE ADDRESS portb BASE ADDRESS portc BASE ADDRESS cnfg BASE ADDRESS EXAMPLE outp cnfg 0xA0 while inp portc outp porta 0x12 PC DIO 24 PnP User Manual amp PORTAoffset PORTBoffset PORTCoffset CNFGoffset l port A output 0x80 C 16 Port A is an output in mode 1 Wait until OBFA is set indicating that the data last written to port A has been read Write data to port A National Instruments Corporation Appendix C Register Level Programming EXAMPLE 2 port B output outp cnfg 0x84 while inp portc outp portb 0x34 Port B is an output in mode 1 amp 0x02 Wait until OBFB is set indicating that the data last written to port B has been read Write the data to port B Mode 2 Bidirectional Bus Mode 2 has an 8 bit bus that can transfer both input and output data without changing the configuration The data transfers are synchronized with handshaking lines in port C This mode uses only port A however po
78. onal bus C 17 to C 20 PC DIO 24 PnP User Manual Index control word written to CNFG Register figure C 17 Port C pin assignments figure C 19 Port C status word bit definitions C 18 programming example C 19 to C 20 purpose and use C 9 mode 2 bidirectional timing 3 14 single bit set reset feature C 9 NI DAQ driver software 1 3 to 1 4 0 OBF signal description table 3 10 mode output timing 3 13 mode 2 bidirectional timing 3 14 Port C signal assignments table 3 4 OBFA bit Port C C 15 C 18 OBFB bit Port C C 15 OKI 82C55A Programmable Peripheral Interface See 82C55A Programmable Peripheral Interface optional equipment for PC DIO 24 PnP 1 5 to 1 6 P PA lt 7 0 gt signal table 3 3 parts locator diagram PC DIO 24 non PnP board D 3 PB lt 7 0 gt signal table 3 3 PC I O channel control circuitry 4 1 to 4 2 PC lt 7 0 gt signal table 3 3 PC DIO 24 non PnP board configuration D 2 to D 7 base I O address settings D 3 to D 5 PC DIO 24 PnP User Manual l 4 factory set jumper and switch settings table D 2 interrupt selection D 5 to D 7 parts locator diagram D 3 differences between PC DIO 24 PnP and D 1 to D 2 comparison of characteristics table D 1 to D 2 installation D 7 PC DIO 24 PnP block diagram 4 1 configuration 2 2 to 2 3 custom cables 1 5 to 1 6 installation 2 1 to 2 2 optional equipment 1 5 to 1 6 overview 1 1 requirements for getting started 1 2
79. or control signal for operation ports port A for group A and port 8 for When setting a mode to a port having 24 bits set it by dividing it into two groups of 12 bits each Group A Port A 8 bits and high order 4 bits of port C PC7 PC4 Group B Port B 8 bits and low order 4 bits of port C PC3 PCO Mode 0 1 2 There are 3 types of modes to be set by grouping as follows Mode O0 Basic input operation output operation Available for both groups A and B Mode 1 Strobe input operation output opera tion Available for both groups A and B Mode 2 Bidirectional bus operation Available for group A oniy National Instruments Corporation B 9 group B of their respective groups PortA B C The internal structure of 3 ports is as follows Port A One 8 bit data output latch buffer and one 8 bit data input latch Port B One 8 bit data input output latch buf fer and one 8 bit data input buffer Port C One amp bit data output latch buffer and one amp bit data input buffer no latch for input Single bit set reset function for port C When port C is defined as an output port it is pos sible to set to turn to high level or reset to turn to low level any one of 8 bits individually without affect ing other bits 197 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet O MSM82C55A 2RS GS VJS m OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals e g
80. or mode 1 input for port B Enable the outp cnfg 0x86 outp outp outp ireg2 0x04 cnfg 0x05 iregl 0x02 appropriate interrupt bits Port B is an input in mode 1 Set PC2 to enable interrupts from 82C55A Set IRQ1 to enable port B interrupts EN bit Set INTI EXAMPLE 3 Set up interrupts for mode 1 output for port A Enable the outp cnfg 0xA0 outp outp outp ireg2 0x04 cnfg 0x0D iregl 0x01 appropriate interrupt bits Port A is an output in mode 1 Set PC6 to enable interrupts from 82C55A Set IRQO to enable port A interrupts EN bit Set INTI EXAMPLE 4 Set up interrupts for mode 1 output for port B Enable the outp cnfg 0x84 outp cnfg 0x05 National Instruments Corporation appropriate interrupt bits Port B is an output in mode 1 Set PC2 to enable interrupts from 82C55A C 21 PC DIO 24 PnP User Manual Appendix C Register Level Programming outp ireg1 0x02 outp ireg2 0x04 Set IRQ1 to enable port B interrupts Set INTEN bit EXAMPLE 5 Set up interrupts for mode 2 output transfers Enable the outp cnfg 0xCO cnfg 0xO0D ireg1 0x01 outp outp outp ireg2 0x04 appropriate interrupt bits Mode 2 output
81. or the 82C55A sse C 4 Figure C 2 Port C Pin Assignments Mode 1 Input C 13 Figure C 3 Port C Pin Assignments Mode 1 Output C 16 Figure C 4 Port A Configured as a Bidirectional Data Bus in Mode 2 C 17 Figure C 5 Port C Pin Assignments Mode 2 serene C 19 Figure D 1 PC DIO 24 Parts Locator Diagram seen D 3 Figure D 2 Example Base I O Address Switch Settings D 4 Figure D 3 Interrupt Enable Jumper Settings eee D 6 Figure D 4 Interrupt Jumper Setting for IRQS Factory Setting D 6 Tables Table 3 1 Signal Descriptions 3 3 Table 3 2 Port C Signal Assignments nennen 3 4 Table 3 3 Timing Signal Descriptions 3 10 Table C 1 PC DIO 24 PnP Address Map seen C 3 Table C 2 Port C Set Reset Control Words C 5 Table C 3 Mode 0 I O Configurations ss C 9 Table D 1 Comparison of Characteristics ss D 1 Table D 2 PC DIO 24 Factory Set Jumper and Switch Settings D 2 Table D 3 Example Switch Settings with Corresponding Base I O Address and l O Address Spaces tins ssl he pesstees esse D 5 PC DIO 24 PnP User Manual viii National Instruments Corporation This manual describes the mechanical and electrical aspects of the PC DIO 24 PnP and contains information concerning its operation and programming The
82. our involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS 2 2 National Instruments Corporation Chapter 2 Installation and Configuration Base 1 0 Address and Interrupt Selection To change base I O address or interrupt selection refer to the NI DAQ Configuration Utility Help file You can configure the PC DIO 24PnP to use base addresses in the range of 100 to 3E0 hex Each board occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3E0 hex The PC DIO 24PnP can use interrupt channel 3 4 5 7 or 9 Note To configure the non Plug and Play PC DIO 24 board refer to Appendix D Using Your PC DIO 24 Non PnP Board National Instruments Corporation 2 3 PC DIO 24 PnP User Manual Chapter Signal Connections This chapter includes timing specifications and signal connection instructions for the PC DIO 24 PnP I O connector Ji Caution Connections that exceed any of the maximum ratings of input or output signals on the PC DIO 24 PnP can damage the board and the PC National Instruments is NOT liable for any damages resulting from any such signal connections Maximum ratings for each signal are given in this chapter under the discussion of that signal 1 0 Connector Figure 3 1 shows the pin assignments for the PC DIO 24 PnP digital I O connector National Instrum
83. pter 2 Installation and Configuration Installation eee o oat eee er ei e eet eoi ie o e i et 2 1 Hardware Configuration etse ie deett tre ire tiere aethere eerie debere 2 2 Plug and Play coves ert RR REO FEE eer EDEN 2 2 Base I O Address and Interrupt Selection 2 3 Chapter 3 Signal Connections I O Connector ege dude pio ieu eei turpem eue OR HE 3 1 signal Descriptors s ertt te ERES EH RE nn RUE QU RU te e PE rires 3 3 Port C Pin Assignments seirene 3 3 Digital I O Signal Connections 3 4 Power Connections ie ie ete ihre eet ote nieder ed bys 3 7 National Instruments Corporation V PC DIO 24 PnP User Manual Contents Digital I O Power up State Selection 3 7 High DIO Power up State ses s sesusesitenssoses sosuecsenessovesbvbescbeed 3 7 Low DIO Power up State ss 3 9 Timing Specifications eire neret neget e e ER E E iip nn es 3 10 Mode 1 Input Timing eie tete ertet tuba sheet oet 3 12 Mode 1 Output Timing seine int Liane Cte AE 3 13 Mode 2 Bidirectional Timing enne 3 14 Chapter 4 Theory of Operation Functional Overview essere reete heer eret eene eee Vere ele ee eoe ee Re Re EE ER eere ER HT 4 1 B s FransCelVels ec eee eee eret terere trente 4 2 Bus Interface eee erede ee dui aei ea 4 2 Interrupt Control Circuitry sin i eto e dee 4 2 82C55A Programmable Peripheral Interface 4 2 Digital TO
84. r All rights reserved OKI Semiconductor Data Book Microprocessor Eighth Edition January 1995 National Instruments Corporation B 1 PC DIO 24 PnP User Manual Appendix B OKI 82C55A Data Sheet OKI semiconductor MSM82C55A 2RS GS VJS CMOS PROGRAMMABLE PERIPHERAL INTERFACE GENERAL DESCRIPTION The MSM82C55A is a programmable universal I O interface device which operates as high speed and on low power consumption due to 3 x silicon gate CMOS technology it is the best fit as an VO port in a system which employs the 8 bit parallel processing MSMB80C85A CPU This device has 24 bit I O pins equivalent to three 8 bit 1 O ports and all inputs outputs are TTL interface compatible FEATURES High speed and low power consumption due to 34 e Bit set reset function Port C silicon gate CMOS technology TTL compatible 3V to 6V single power supply e Compatible with 8255A 5 Full static operation 40 pin Plastic DIP DIP40 P 600 Programmable 24 bit 1 O ports MSM82C55A 2RS Bidirectional bus operation Port A 44 pin Plastic QFJ QFJ44 P S650 MSMB82C55A 2JS 944 pin Plastic QFP QFP44 P 910 2K MSMB82C55A 2GS 2K CIRCUIT CONFIGURATION w Ej 5 a 2 8 4 X z x ul iz z 190 PC DIO 24 PnP User Manual B 2 National Instruments Corporation Appendix B OKI 82C55A Data Sheet a O MSM82C55A 2RS GS VJS PIN CONFIGURATION Top View 40 pin Plastic DIP 44 pin Plastic QFP 44 pin Plastic
85. r call the office nearest you Note The PC DIO 24 PnP can drive the SSR ODC 5 output module and all SSR input modules available from National Instruments but cannot reliably sink sufficient current to drive the SSR OAC 5 and SSR OAC 5A output modules To drive a SSR OAC 5 or SSR OAC SA you can either use a non inverting digital buffer chip between the PC DIO 24 PnP and the SSR backplane or use another National Instruments board with higher drive current Custom Cables National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful The PC DIO 24 PnP I O connector is a 50 pin male ribbon cable header The manufacturer part numbers used by National Instruments for this header are as follows e Electronic Products Division 3M part number 2550 5002 e T amp B Ansley Corporation part number 609 5007 National Instruments Corporation 1 5 PC DIO 24 PnP User Manual Chapter 1 Introduction The mating connector for the PC DIO 24 PnP is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the PC DIO 24 PnP Recommended manufacturer part numbers for this mating connector are as follows e Electronic Products Division 3M part number 3425 7650
86. r computer Read this appendix only if you do not have the Plug and Play version of the board Differences between the PC DIO 24PnP and the PC DIO 24 The PC DIO 24PnP is a Plug and Play upgrade from a legacy board the PC DIO 24 Legacy board refers to a board with switches and jumpers used to set the addresses and interrupt levels The original legacy board was replaced with a backwards compatible revised PC DIO 24 that has many of the new features of the Plug and Play version The following list compares the specifications and functionality of the newer boards with the original legacy board This document applies only to the revised PC DIO 24 PnP board Table D 1 Comparison of Characteristics Specification Original PC DIO 24 Revised PC DIO 24 PC DIO 24PnP I O base address Uses switches Uses switches Plug and Play selection compatible Interrupt request Uses jumpers Uses jumpers Plug and Play selection compatible Interrupt request Uses one port C line Uses one port C line Software controlled enable jumper selectable jumper selectable uses interrupt control registers National Instruments Corporation D 1 PC DIO 24 PnP User Manual Appendix D Using Your PC DIO 24 Non PnP Board Table D 1 Comparison of Characteristics Continued Specification Revised PC DIO 24 PC DIO 24PnP Original PC DIO 24 5 V supply fuse Nonresettable Self resetting Self resetting Power up state
87. ramming Register Map The following table lists the address map for the PC DIO 24 PnP Table C 1 PC DIO 24 PnP Address Map Offset Address Register Name Hex Size Type 82C55A Register Group PORTA Register 00 8 bit Read and write PORTB Register 01 8 bit Read and write PORTC Register 02 8 bit Read and write CNFG Register 03 8 bit Write only Interrupt Control Register Group PC DIO 24PnP only Register 1 14 8 bit Write only Register 2 15 8 bit Write only Register Description for the 82C55A Figure C 1 shows the two control word formats used to completely program the 82C55A The control word flag determines which control word format is being programmed When the control word flag is 1 bits 6 through 0 select the I O characteristics of the 82C55A ports These bits also select the mode in which the ports are operating that is mode 0 mode 1 or mode 2 When the control word flag is 0 bits 3 through 0 select the bit set reset format of port C National Instruments Corporation C 3 PC DIO 24 PnP User Manual Appendix C Register Level Programming Control Word Flag 1 mode set Mode Selection 00 mode 0 01 mode 1 1X mode 2 PortA 1 input 0 output Port C high nibble 1 input 0 output Control Word Flag 0 bit set reset Unused GroupA Group B lt q gt lt gt D7 D6 D5 D4 D3 D2 D1 DO A A A Por
88. red GND Ground These signals are pins connected to the computer ground reference The absolute maximum voltage input rating is 0 5 to 5 5 V with respect to GND Port C Pin Assignments The signals assigned to port C depend on the mode in which the 82C55A is programmed In mode 0 port C is treated as one 8 bit I O port If port A or B is in mode 1 or 2 then some or all of the port C lines are used for status and handshaking signals Any unused lines are available for general purpose input and output Table 3 2 summarizes the signal assignments of port C for each programmable mode Ports A and B can be in different modes the table does not show every possible combination See Appendix C Register Level Programming for register level programming information National Instruments Corporation 3 3 PC DIO 24 PnP User Manual Chapter 3 Signal Connections ji Caution During programming note that each time you configure any port output ports A and C are reset to 0 and output port B is undefined Table 3 2 Port C Signal Assignments Group A Group B Programming Mode PC7 PC6 PC5 PC4 PC3 PC2 PCI PCO Mode 0 IO IO IO IO IO IO IO IO Mode 1 Input 1 0 IO IBF STBA INTRA STBg IBFBg INTRg Mode 1 Output OBFA ACK VO W O INTR ACKg OBFg INTRg Mode 2 OBF ACK IBF STBA INTRA I O IO 1 0 Indicates that the signal is active low
89. rt B can be used in either mode 0 or mode 1 while port A is configured for mode 2 The control word written to the CNFG Register to configure port A as a bidirectional data bus in mode 2 is shown as follows If port B is configured for mode 0 then PC2 PCI and PCO of port C can be used as extra input or output lines D7 D6 D5 D4 D3 D2 D1 DO 1 1 X X X 1 0 1 0 1 0 UL Port C PC2 PCO 1 input 0 output Port B 1 input 0 output Group B Mode 0 mode 0 1 mode 1 Figure C 4 Port A Configured as a Bidirectional Data Bus in Mode 2 National Instruments Corporation C 17 PC DIO 24 PnP User Manual Appendix C Register Level Programming D7 D6 During a mode 2 data transfer the status of the handshaking lines and interrupt signals can be obtained by reading port C The port C status word bit definitions for a mode 2 transfer are shown as follows Port C status word bit definitions for bidirectional data path port A only D5 D4 D3 D2 DI DO OBFA INTEI IBFA INTE2 INTRA 1 0 1 0 Uo PC DIO 24 PnP User Manual Bit 2 0 Name Description OBFA Output Buffer for Port A A low setting indicates that the CPU has written data to port A INTE1 Interrupt Enable Bit for Port A Output Interrupts Setting this bit enables output interrupts from port A of the 82C55A This bit is controlled by setting resetting PC6 I
90. sible resistance value ensures that you do not to use more current than necessary to perform the pull up task and that the DIO can still drive the line The DIO lines are capable of sinking a maximum of 2 5 mA at 0 4 V in the low state Also make sure the pull up resistor value is not so large that leakage current from the DIO line along with the current from the 100 kQ pull down resistor brings the voltage at the resistor below a TTL high level of 2 8 VDC PC DIO 24 PnP 45V R 82C55A Digital 1 0 Line 100ko eee GND Figure 3 4 DIO Channel Configured for Low DIO Power up State with External Load Example At power up the board is configured for input and jumper W1 is set in the low DIO power up state which means all DIO lines are pulled low If you want to pull one channel high follow these steps 1 Install a load Rj Remember that the smaller the resistance the greater the current consumption and the higher the voltage 2 Using the following formula calculate the largest possible load to maintain a logic high level of 2 8 V and supply the maximum sink current V I R gt R V I where V 2 2 V voltage across R I 28 uA 11 uA 2 8 V across the 100 KQ pull up resistor and 11 uA max leakage current National Instruments Corporation 3 9 PC DIO 24 PnP User Manual Chapter 3 Signal Connections Therefore RL 5 6 KQ 2 2 V 39 LA This resistor value 5 6 kQ provides a minimum of 2 8
91. software programming choices 1 2 to 1 4 National Instruments application software 1 2 to 1 3 NI DAQ driver software 1 3 to 1 4 register level programming 1 4 specifications A 1 to A 3 theory of operation 4 1 to 4 3 unpacking 1 7 physical specifications A 2 pin assignments See I O connector Port C Plug and Play configuration 2 2 Port C pin assignments description 3 3 mode 1 input figure C 13 mode 1 output figure C 16 mode 2 bidirectional bus figure C 19 signal assignments table 3 4 set reset control words table C 5 status word bit definitions mode 1 strobed input C 12 to C 13 mode 1 strobed output C 15 power connections 3 7 National Instruments Corporation power requirements A 2 programming See register level R programming RD signal description table 3 11 mode input timing 3 12 mode 2 bidirectional timing 3 14 register level programming C 1 to C 23 82C55A operation C 2 compared with other software options 1 4 interrupt handling C 22 to C 23 interrupt programming examples C 20 to C 22 mode 0 basic I O C 9 to C 11 configurations table C 9 to C 10 overview C 8 programming example C 10 to C 11 mode 1 strobed input C 11 to C 14 control words figures C 11 to C 12 Port C pin assignments figure C 13 Port C status word bit definitions C 12 to C 13 programming example C 13 to C 14 mode 1 strobed output C 14 to C 17 control words written to CNFG register
92. t TBoffset Coffset CNFGoffset unsigned in t porta char valread Calculat porte portb porte cnfg BASE BASE BASE BASE 0x180 0x00 0x01 0x02 0x03 portb portc cnfg Board located at address 180 Offset Offset Offset Offset for for for for port A port B port C CNFG Variable to store data read from a port addresses register ADDR ADDR ADDR ESS ESS ESS _ADDR National Instruments Corporation ESS PORTAoffset PORTBoffset PORTCoffset CNFGoffset C 13 PC DIO 24 PnP User Manual Appendix C Register Level Programming EXAMPLE l port A input outp cnfg 0xBO Port A is an input in mode 1 while inp portc amp 0x20 Wait until IBFA is set indicating that data has been loaded in port A valread inp porta Read the data from port A EXAMPLE 2 Port B input outp cnfg 0x86 while inp portc Port B is an input in mode 1 amp 0x02 Wait until IBFB is set indicating that data has been loaded in port B valread inp portb Mode 1 Strobed Output PC DIO 24 PnP User Manual The control word written to the CNFG Register to configure port A for output in mode 1 is shown as follows Bits PC4 and PC5 of port C can be used as extra input or output lines
93. t C low nibble 1 input 0 output Port B 1 input 0 output Mode Selection 0 mode 0 1 mode 1 a Mode Set Word Format D7 D6 D5 D4 D3 D2 D1 DO Bit Set Reset 1 set 0 reset Bit Select b Bit Set Reset Word Format 000 001 010 111 A Caution Figure C 1 Control Word Formats for the 82C55A During programming note that each time any port is configured output ports A and C are reset to 0 and output port B is undefined PC DIO 24 PnP User Manual C 4 National Instruments Corporation Appendix C Register Level Programming Table C 2 shows the control words for setting or resetting each bit in port C Notice that bit 7 of the control word is cleared when programming the set reset option for the bits of port C Table C 2 Port C Set Reset Control Words Bit Set Control Bit Reset The Bit Set or Bit Number Word Control Word Reset in Port C 0 Oxxx0001 Oxxx0000 xxxxxxxb 1 Oxxx0011 Oxxx0010 XXXXXXDX 2 Oxxx0101 Oxxx0100 XXxxxbxx 3 Oxxx0111 Oxxx0110 XXXXDXXX 4 Oxxx1001 Oxxx1000 XXXDXXXX 5 Oxxx1011 Oxxx1010 XXDXXXXX 6 Oxxx1101 Oxxx1100 XDXXXXXX 7 Oxxx1111 Oxxx1110 DXXXXXXX Register Description for the Interrupt Control Registers There are two interrupt control registers on the PC DIO 24PnP One of these registers has individual enable bits for the two interrupt lines from the 82C55A device The other
94. ta is available in port A to be read A valread inp porta Read data from port A Interrupt Programming Examples for the 82C55A The following examples show the process required to enable interrupts for several different operating modes The interrupt handling routines and interrupt installation routines for the 82C55A are not included Consult your computer technical reference manual for additional information Also if you generate interrupts with the PC3 or PCO lines of the 82C55A devices you must maintain the active high level until the interrupt service routine is entered Otherwise the host computer considers the interrupt a spurious interrupt and routes the request to the channel responsible for handling spurious interrupts To prevent this problem try using some other I O bit to send feedback to the device generating the interrupt In this way the interrupting device can be signaled that the interrupt service routine has been entered For further information on using PC3 and PCO for interrupts see the Interrupt Handling section later in this appendix iz Note The following code applies to the PC DIO 24PnP To adapt this code to the PC DIO 24 non PnP remove the outp ireg1 instructions and replace outp ireg2 0x04 with the following assuming you use PC4 as your interrupt enable outp cnfg 0x08 PC DIO 24 PnP User Manual Clear PC4 to enable interrupts You cannot use PC4 as your interrupt en
95. ter The configuration bits for these registers are defined in the Register Description for the Interrupt Control Registers section in this appendix National Instruments Corporation C 1 PC DIO 24 PnP User Manual Appendix C Register Level Programming PC DIO 24 PnP User Manual The PC DIO 24 non PnP does not have interrupt control registers Instead it uses one of the port C lines to enable or disable interrupts See Appendix D Using Your PC DIO 24 Non PnP Board for more information The three 8 bit ports of the 82C55A are divided into two groups of 12 signals each group A and group B One 8 bit control word selects the modes of operation for both groups The group A control bits configure port A A7 through AO and the upper 4 bits nibble of port C C7 through C4 The group B control bits configure port B B7 through BO and the lower nibble of port C C3 through CO These configuration bits are defined in the Register Description for the 62C55A section later in this appendix The 82C554 potentially requires up to 200 ns recovery time between consecutive read or write cycles Certain computers may provide slightly less time than this between two back to back assembly language reads or writes If you are programming in assembly language it is therefore recommended that you separate two 82C554 reads or writes with at least one other instruction C 2 National Instruments Corporation Appendix C Register Level Prog
96. terrupt the host computer If this bit is cleared the board cannot interrupt the host computer C 7 PC DIO 24 PnP User Manual Appendix C Register Level Programming Programming Considerations for the 82C55A Modes of Operation for the 82C55A PC DIO 24 PnP User Manual The three basic modes of operation for the 82C55A are as follows e Mode 0 Basic I O e Mode 1 Strobed I O e Mode 2 Bidirectional bus The 82C55A also has a single bit set reset feature for port C which is programmed by the 8 bit control word For additional information refer to Appendix B OKI 52C55A Data Sheet Mode 0 Use this mode for simple input and output operations for each of the ports No handshaking is required simply write data to or read data from a specified port Mode 0 has the following features e Two 8 bit ports A and B and two 4 bit ports upper and lower nibbles of port C e Any port can be input or output e Outputs are latched but inputs are not latched Mode 1 This mode transfers data that is synchronized by handshaking signals Ports A and B use the eight lines of port C to generate or receive the handshake signals This mode divides the ports into two groups group A and group B and includes the following features e Each group contains one 8 bit data port port A or port B and one 3 bit control status port upper or lower portion of port C e The 8 bit data ports can be either input or output both of wh
97. tions you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix E Customer Communication at the end of this manual National Instruments Corporation xiii PC DIO 24 PnP User Manual Chapter Introduction This chapter describes the PC DIO 24 PnP lists what you need to get started describes software programming choices optional equipment and custom cables and explains how to unpack the PC DIO 24 PnP About the PC DIO 24 PnP Thank you for purchasing the National Instruments PC DIO 24 PnP The PC DIO 24 PnP is a low cost 24 bit parallel digital I O interface for ISA computers An OKI 82C55A programmable peripheral interface PPI chip controls the 24 bits of digital I O The 82C55A chip is very flexible and powerful when interfacing with peripheral equipment can operate in either a unidirectional or bidirectional bus mode and can generate interrupt requests to the host computer You can program the 82C554 chip for numerous 8 bit 16 bit or 24 bit digital I O applications All digital I O communication is through a standard 50 pin male connector The pin assignments for this connector are compatible with standard 24 channel digital I O applications PnP refers to the Plug and Play technology used in this board See the definition in the Glossary for an exp
98. u to configure the device base address and interrupt level with switches and jumpers You must perform this configuration before installing the product in the computer PPI programmable peripheral interface is the DIO chip on the PC DIO 24 PnP board SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards National Instruments Corporation Xi PC DIO 24 PnP User Manual About This Manual National Instruments Documentation The PC DIO 24 PnP User Manual is one piece of the documentation set for your data acquisition DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the different types of manuals you have as follows PC DIO 24 PnP User Manual Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs int
99. ug and Play circuitry automatically arbitrates and assigns system resources Software performs all bus related configuration such as setting the board base address and interrupt level On the PC DIO 24 non PnP switches and jumpers set the board base address and interrupt level Interrupt Control Circuitry The PC DIO 24PnP interrupt channel is selected by the Plug and Play circuitry Two software controlled registers determine what sources if any can generate interrupts The 82C55A device has two interrupt lines PC3 and PCO connected to the interrupt circuitry The PC DIO 24 non PnP uses one of the extra PC lines jumper selectable as an interrupt enable 82C55A Programmable Peripheral Interface PC DIO 24 PnP User Manual The 82C55A PPI chip is the heart of the PC DIO 24 PnP This chip has 24 programmable I O pins that represent three 8 bit ports PA PB and PC You can program each port as an input or an output port The 82C55A has three modes of operation simple I O mode 0 strobed I O mode 1 and bidirectional I O mode 2 In mode 1 the three ports are divided into two groups group A and group B Each group has eight data bits and three control and status bits from port C PC Group A can also use mode 2 In mode 2 group A has one 8 bit bidirectional data port and five control and status bits from port C You can use port and port B in two different modes Modes 1 and 2 use handshaking signals from port C to
100. upt Selection There are two sets of jumpers for interrupt selection on the PC DIO 24 board W3 is used for selecting the interrupt enable line W2 is for selecting the interrupt level The location of these jumpers is shown in Figure D 1 National Instruments Corporation D 5 PC DIO 24 PnP User Manual Appendix D Using Your PC DIO 24 Non PnP Board PC DIO 24 PnP User Manual Interrupt Enable Settings To enable interrupt requests from the PC DIO 24 you must set jumper W3 to select PC2 PC4 or PC6 as the active low interrupt enable line When the interrupt enable line is logic low interrupts are enabled from the PC DIO 24 board Refer to Chapter 4 Theory of Operation for the suggested interrupt enable line setting for each digital I O mode of operation If W3 is set to N C all interrupt requests from the PC DIO 24 are disabled Figure D 3 shows the possible jumper settings for W3 The board ships with this jumper set to PC4 therefore interrupt requests from the board are enabled and controlled by PC4 W3 W3 W3 W3 PC6 PC6 PC6 PC6 PC4 PC4 PC4 PC4 PC2 PC2 PC2 PC2 N C N C N C N C INT INT INT INT PC6 Selected PCA Selected PC2 Selected Interrupt Default Factory Disabled Setting Figure D 3 Interrupt Enable Jumper Settings Interrupt Level Settings The PC DIO 24 board can connect to any one of the six interrupt lines of the PC I O Channel IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 or IRQ9 You select the interrupt lin
101. utput Output Output Input 2 10000010 Output Output Input Output 3 10000011 Output Output Input Input 4 10001000 Output Input Output Output 5 10001001 Output Input Output Input 6 10001010 Output Input Input Output 7 10001011 Output Input Input Input 8 10010000 Input Output Output Output National Instruments Corporation C 9 PC DIO 24 PnP User Manual Appendix C Register Level Programming Table C 3 Mode 0 1 0 Configurations Continued Control Word Group A Group B Bit Number 76543210 Port A Port C Port B Port C 9 10010001 Input Output Output Input 10 10010010 Input Output Input Output 11 10010011 Input Output Input Input 12 10011000 Input Input Output Output 13 10011001 Input Input Output Input 14 10011010 Input Input Input Output 15 10011011 Input Input Input Input Upper nibble of port C Lower nibble of port C Mode 0 Programming Example The following example shows how to configure the 82C55A for various combinations of mode 0 input and output This code is strictly an example and is not intended to be used without modification in a practical situation Main define BASE ADDRESS 0x180 Board located at address 180 define PORTAoffset 0x00 Offset for port A define PORTBoffset 0x01 Offset for port B define PORTCoffset 0x02 Offset for port C fdefine CNFGoffset 0x03 Offset for CNFG unsigned int porta portb port
102. virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ LabVIEW features interactive graphics and a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software 1 2 National Instruments Corporation Chapter 1 Introduction LabWindows CVI features interactive graphics and a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using ComponentWorks LabVIEW LabWindows CVI or VirtualB

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