Ece 209 - Clemson University
Contents
1. All pins each of these rows are connected together so one can use for a 5 Volt bus and for O Volt Ground bus Note Some board buses are divided at the center of the board If the board is not marked as this one is then it should be checked Chips should be placed across the center groove of the breadboard as shown below Compiled by Dr W J Reid Spring 2002 14 209 Lab Kit Notes Resistors and Capacitor Codes 123MT 12M T 0 T Tolerance Black Brown Red Orange Yellow Green Blue Violet Black Brown Red Orange Yellow Green Blue Violet Black Brown Red Orange Yellow Green Blue Violet Brown Red Orange Yellow Green Blue Brown 1 NOOB WN NOOB WON 0 1 2 3 4 5 6 7 White White White Capacitors come in many shapes sizes and types Some large electrolytic capacitors have the explicit value printed on them Some capacitors use the following code shown below where M is a multiplier and T is the tolerance The table below shows the values for the given code numbers and letters 12x10 T 1 151 1510 150 pF 759 750 1 7 5 pF Sometimes the letter may be used to signify a decimal point 0 1 0 25 0 5 1 0 2 0 anona oz 1 22. 8E m b E E amp B E E E ES E M E CH amp B B B B q 9 m m m B B oW m m pitta B B OH P m m B ij m B mH W NH H NW EH M m w m mw m mmu m cr mw amp mw mH 4 Wow E m mm m All pins on each of these rows are connected together one can use for a 5 Volt bus and for 0 Volt Ground bus Note Some board buses are divided at the center of the board If the board is not marked as this one is then it should be checked Figure 1 Protoboard Connections Usually the top row is connected to the 45V power supply and is called the power bus The bottom row is connected to an external ground and is called the ground bus Figure 2 shows how the power and ground pins of IC1 and IC2 can be connected together by the red wires and black wires It also shows how the output of pin 3 on IC1 can be connected to the input pin 1 of IC2 with a green wire Figure 2 Connecting Wires Special care is needed when using the protoboard If a wire which 1 too large is forced into one of the holes that particular contact point most probably will be damaged As a result the next time the protoboard is used
3. Trigger Time Div Slope Immediate Source Level V TRIG 200 ms Instrument Control Device Acquisition Mode ELVIS III Continuously Help Display Measurements E Auboscale Cursors Settings CursorsOn cil CHO cal Figure 7 MI ELVISmx Oscilloscope The ELVIS II 15 a powerful and expensive design aid Do not abuse it Any questions you may have should be directed to the instructor Integrated Circuits IC s The IC s supplied with the kit are used in a variety of experiments Each looks similar to the one shown below Not the dot but part of mold Figure 8 IC Pin Numbering 10 Note the numbering system which progresses counter clockwise from pin 1 Pin 1 15 designated by a dot or a notch Usually on TTL logic the type of chips supplied with the kit the last pin is to be connected to the 5 V supply and the pin diagonally opposite is connected to ground These are pins 14 and 7 respectively for 14 pin IC s and 16 and 8 for 16 pin IC s There are some exceptions to this rule so always check Special caution should be taken when inserting and removing IC s from the protoboard When shipped from the factory the leads legs of the IC s are slightly bent apart to aid in machine insertion It is necessary to straighten the legs pri
4. 2R2 2 2 pF or uF Compiled by Dr W J Reid Spring 2002 15 209 Lab Kit Chip Pin Outs 7400 7447 7400 Quad 2 Input 7402 Quad 2 Input 7404 Hex NAND Gate NOR Gate Inverter B4 A4 Y4 Y4 B4 A4 A6 A5 Y5 4 Y4 A1 B1 Y1 A2 B2 Y2 GND YT A1 B1 Y2 A2 B2 GND A1 V1 A2 Y2 GND Input Output 7408 Quad 2 Input 7409 Quad 2 Input 7410 Triple 3 Input AND Gate AND Gate Open Collector NAND Gate A4 Y4 B3 B4 A4 Y4 Veo C1 Y1 C3 B3 Y3 A1 B1 Y1 A2 B2 Y2 GND A1 B1 Y1 A2 B2 Y2 GND 7420 Dual 4 Input 7432 Quad 7447 Binary to BCD NAND Gate 2 Input OR Gate Converter 02 C2 NC 2 72 B4 A4 Y4 V f b d e B CITRBRBD A Out In A1 B1 NC C1 D1 Y1 GND y ABCD A1 81 Y1 A2 B2 Y2 GND B C Lamp A GND es n ASGD Y 8 M MOTOROLA Ere FAIRCHILD RAI ONIO IMT OD TEXAS INSTRUMENTS Compiled by Dr W J Reid Spring 2002 16 209 Lab Kit Chip Pin Outs 7473 7495 7473 Dual 7476 Dual 7486 Quad 2 Input J K Flip Flop J K Flip Flop XOR Gate Q1 GND K2 Q2 02 K1 01 GND K2 92 Q2 J2 V 4 4 4 Ck1 K1 V Ck2 Cr2 J2 Ck1 PR1 J
5. 47 Now connect the following circuit d b Serial Seven d Comm Segment 8 Display 9 UP DOWN COUNT COUNT LOAD CLEAR CLOCK 5 Use NI ELVIS Function Generator Pulse Signal Figure 6 Parallel to Serial Communication WARNING Do not wire any pin of the seven segment display to ground You can destroy it Also be sure that the bare leads of the resistors do not touch before turning on power To operate wire the inputs to the 74151 as appropriate to light the proper segments for the number 5 Set the pulse square waveform clock on 1 Hz and check that the proper segments light Once all segments light or remain dark as they should it will take 8 seconds for the number to be displayed speed the clock up by increasing the frequency of the pulse and observe the effect at each speed At I kHz the display will appear constant though a bit dimmer You can also use sweep settings of the function generator to increase the frequency automatically e Questions to turn in with the lab report 1 Explain why the circuit connection on page 2 acts like a 1 8 demultiplexer 2 If this circuit were being used to transmit data over a single wire which connection on the final circuit page 3 corresponds to the data wire Ignore timing problems with the counter 3 How do you think the phone company uses multiplexing to put many conversations over a single line 48 4 What other type
6. To deal with this problem cost effectively a memory hierarchy has been created The basic concept is that data a processor needs most often will be kept in a small fast but expensive memory and less frequently used data will be kept in progressively larger slower and cheaper memories The fastest memory are registers on the CPU constructed of very fast transistors the so called on chip or Level 1 cache The second level of the hierarchy is typically an off chip or L2 cache made up of a fast static RAM The third level is main memory generally made up of slower less expensive dynamic RAMs and the fourth level is the very large slow and inexpensive secondary storage such as a disk drive When the computer needs to read a byte of memory it generates an address The next step 1s to figure out where the data associated with that address is currently residing is it in one of the caches main memory or on disk The first thing to check is the L1 cache If the location desired is there this is known as a cache hit and the value can be read immediately If the location is not there a cache miss occurs and the memory hierarchy must be searched through until the data and that around it 1s located and brought into the L1 cache Caches The purpose of this project is to build the logic that determines if the data located at a given address is or isn t in the cache The output of your circuit will be a signal indicating whether we have a
7. A z x y lt z Therefore we can implement P with a three variable XNOR gate Of course we don t have a three input XNOR gate in our lab kits but we can easily build one from two XOR gates 7486 and single inverter Recall that is associative like AND or OR so that x CV 7 x 9 y 9 7 Use Logisim to create a sub circuit of your parity generator circuit Refer to guide at Logisim Documentation _ Wire up the circuit on your breadboard and test its function 32 Section 2 Parity Detector Next we need to implement a Parity Detector circuit It will have four inputs the three information bits x y and z and the newly created parity bit P It will have one output bit the error E which will be high whenever there is a parity error Fill in the value for 1n the truth table for this circuit below Remember will be I whenever P is not the correct odd parity bit for the values of x y and z E E tg 0 1 Now find MSOP equation for using the Karnaugh map below L 00 01 11 10 AN Once again you ll notice that this equation would be a nuisance to wire up since we cannot form any groups on the map And once again we notice the familiar checkerboard pattern
8. If we look back at our truth table we ll notice that E is true whenever there is an even number of 1 s in the four input variables just as P was whenever there was an even number of 1 s in the input in the table for our generator circuit Once again we can implement this function as an XNOR of the four input variables x 9 V C 2 33 Because of this property XNOR 1 also known as even function 1 also known as the odd function we changed our truth table so that our output was true whenever there was an odd number of 1 the resulting function would be an and the Karnaugh map would still look like a checkerboard but the first one would be in square 0001 instead of OOOO Create your parity detection circuit using the equation for E above as a subcircuit in Logisim with four inputs and I output and verify its function To test your simulation embed your generator and detector subcircuits in the same circuit as shown in the figure below LED for P LED for Switches Parity Parity Generator Detector Figure 1 Parity Generator and Detector _ Wire up your circuit on your breadboard This will require three more XOR gates and one more inverter You should have two 7486 chips in your kit Connect your parity generator to your parity detector and verify that it works correctly 9 How might you change the circuit above to simulate a communication where a single bit e
9. appropriate tag from your memory Then you will compare the tag you got from the memory to the tag in your address using a 4 bit comparator you are expected to design a 4 bit comparator macro see below You will have one output hit which will be a I if the tags are equal and the valid bit is 1 and a otherwise Connect eight switches to the inputs of your simulation corresponding to address bits 8 15 so your instructor can enter addresses to test the design Wire the hit signal to an LED erem Bring an electronic copy of your design to lab with you and be prepared to demonstrate the operation of your functional memory cache Add appropriate input switches and an output light so that you can input the eight high order bits of the 16 bit address consisting of a 4 bit tag and 4 bit cache line and see your LED output A cache hit is lit and a cache miss 1 unlit A Note on Comparators Recall that the XNOR function is also called equivalence where x y xy x y Also recall that two binary numbers would be equivalent if the first bits were equivalent and the second bits were equivalent and the third bits were equivalent and so on 58 ECE 209 Lab 9 Sequential Design Three Bit Counter PURPOSE To understand the design and restrictions of Sequential Circuits EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II Simulation Software REQUIREMENTS e Electronic copy of your design e Schematic of final de
10. diode glows If your lab kits contains a common cathode display the common point is ground instead of 5 V as shown below To light these segments a logic high must be supplied LED Segment Inputs a D C dp Common GND Figure 4 Common Cathode Seven Segment Display Circuitry These LED circuits can be used in the last lab as a logic indicator to troubleshoot circuits Consider verifying the operation of the XOR gate of Lab I using a logic indicator shown below The LED functions as a logic test probe which lights up when the test point is a logic zero and does not light up when the test point is at a logic one 5 Voc WAS gt 2200 2 2 Figure 5 LED used as Logic Test Probe NOTE You can use the LED s built into the NI ELVIS for trouble shooting as discussed above Consider that they more appropriately turn on with a logic one instead of a logic zero 26 Now consider how the ten decimal numerals be formed using the seven segment display The figure below shows these digits 0 through 9 LI ILL LI Figure 7 Seven Segment Display Decimal Representations Section 2 The BCD to Seven Segment Converter What we wish to do 18 input BCD 4 bit binary number to some combinational circuit which causes the appropriate segments of the display to light up For example if a 0000 is input to the circuit all of the LED pins on the seven segment display should go
11. to see if you have a cache hit you can ignore the offset and simply compare the tag to the tag currently stored in the appropriate line of the cache To make this easier associated with the cache there is a tag memory a small memory that stores the tag of each block currently stored in the cache line There is also one additional valid with each tag entry which indicates if any valid block is stored at that cache line at power on for instance none of the lines are filled yet there are several other cases when cache lines are invalid that we won t go into For the cache described above a 16x5 memory would be needed to store the 16 4 bit tags plus their corresponding valid bits PROCEDURE You are to design and simulate a circuit which determines if a cache hit or a miss is made for the system described above You will have a 16x5 tag memory which you will implement using a ROM or RAM since they re exactly the same in Logisim You will initialize the tag memory according to the table below Address Valid Tag 0000 1 0001 0001 1 0001 0010 1 1111 0011 1 1110 0100 0 0001 0101 0 0101 0110 1010 0111 1010 1000 1 0000 1001 1 0000 1010 1 0000 1011 1 0111 1100 0000 1101 1111 1110 1 0010 1111 1 0011 The most significant bit in each word will be the valid bit and other four bits will be the tag You will receive as input a 16 bit address You will use the cache line address bits to retrieve the 57
12. 1010 Now make up a truth table for all seven segments and find a function MSOP for each You need not make a separate truth table for each segment just list the inputs once and have seven output columns as shown below D Fa Fs Fc Fe Fr Fc 0 0 0 0 0 01 1111 X X X X X XX We need not build all of these individual circuits with separate IC s however in order to use the seven segment display Because this function 1 so common to electronics a single chip has been standardized to perform this conversion This chip which you have in your lab kit is the 7447 and is called a BCD to seven segment display A block diagram for this chip 1s show below 28 5 Voc POOO D O 0 O Figure 8 7447 BCD to Seven Segment Display The 7447 has common collector outputs which can sink much more current than they can source supply Therefore the 7447 1s designed for a common anode type display which needs a logic low to turn on the segments If you have a common cathode display then you must use an inverter on each input The inverter should be able to supply enough current to light a segment Now using the 4 switches of the ELVIS as the BCD input connect the following circuit and verify that it functions properly Be sure to include a description of the circuit operation in your report 5 Voc tO Voc gt D d I Figure 9 Using the 7447
13. BCD to Seven Segment Display 29 Remember to be very careful wiring this circuit making sure that resistor leads shorted anywhere and that the power to the seven segment display is connected to the correct pin Do Not connect any pin of the common anode seven segment display directly to ground This will short out the segment forever Likewise do not connect any pin of the common cathode display to 5 V or it to will be shorted out forever Check the six unused input combinations 1010 through 1111 and report which segments light up Does this match what you would expect from the seven equations you got for the decoder If not can you think of one reason why the output might not match your equations 30 ECE 209 Lab 3 Combinational Circuits Parity Generation and Detection PURPOSE To familiarize the student with combination circuits by studying methods of parity generation and detection EQUIPMENT ECE 209 Lab Kit amp NI ELVIS I Simulation Software REQUIREMENTS Karnaugh Map for Parity Generator and Detector Truth Table for Parity Detector e Verbal description of the function of the Parity Generator Detector simulation of functional Parity Generator Detector PROCEDURE Section 1 Parity Generator In this part of the lab we will design and build circuits to generate and detect odd parity for three bit words Our parity generator circuit will take three input bits
14. Fy as Fr 21 A circuit for this function be drawn in the following manner F To lighting control gt gt VEO Figure 2 Circuit Diagram for Note that the circuit above would not switch the light on directly The Binary signal that is 5 Volts DC from the output would need to go to a device say a relay which could switch on the 120 Volt AC power to the lights In lab however we will wire the output directly to a light LED since these require only 5 Volts DC If you use the red LED provided to you use a 220 ohm resistor along with it Connect the anode terminal long terminal of the red LED to the output of the circuit through the resistor and connect the cathode terminal short terminal to the GND Note also that the wall switches in lab are only switching 5 Volts in this case not the 120 Volts AC as would be found the actual home One immediate problem of implementing this lab is there is no 3 input OR gate your lab kit Recall that the OR operation is associative allowing you to make a 3 input OR from two 2 input OR gates AORBORC A 4 B C A B C A B C AAA A Now connect this circuit and check to see that it works properly Use the switch 0 and 1 for and A respectively Switch 2 for P switch 3 for M and switch 4 for B Verify the functioning of the circuit Now instead of using a switch for B use the function generator to generate pulse or
15. input AND gates and one 4 input OR gate All you have available however are 2 input AND and OR gates thus you must discover how to make e A 3 input AND from two 2 input AND s and A 4 input OR from three 2 input OR s Remember that both the AND and OR operations are associative AA Wire this circuit and have the lab instructor verify its proper function 23 209 Lab 2 Encoding Decoding The Seven Segment Display PURPOSE To familiarize the student with the seven segment LED display and the process of converting one type of binary information to another encoding decoding A good understanding of BCD Binary Coded Decimal should also result EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II Simulation Software REQUIREMENTS e Circuit diagrams with pin numbers labeled e Verbal description of the function of the final circuits Truth Table for all seven segments and all seven functions in MSOP e Simulation of functional seven segment display circuit PROCEDURE Section 1 About the Seven Segment Display Improper connections to the seven segment display can destroy it Double check your connections before applying power The seven segment LED Light Emitting Diode display is a common device in consumer electronics from calculators to clocks to microwave ovens this lab you will learn the basic principles of operation of the seven segment display and the process
16. it which gives the chip s manufacturer function and performance As shown above the chip DV74LS374N is 74374 logic chip which is an octal D type tri state flip flop The LS means it is a Low power Schottky The Breadboard contains a grid of holes in which wires can be inserted to make an electrical connection with the pins legs of the IC The diagram below shows how contacts are connected internally Each of these contacts are tied together _ ennon um E T C gt 2 0 __ __ __ __ _ ___ _ _ amp amp 5 B B E M E 5 M M Ee BOE B 5B MEME b m amp E E E s mu 33 34358 5 ES NIS NOM amp NE E B B B P cq ss5595832535 9 3 3 5 55 a a s 4 amp E 5 d E b E 9 5 5 5 4 3 4 B E M E B E OEREEASBSEEEESSSISESYSES S CE LE 555955239 a _ ensce onana 88888 ABARES zanas
17. numbers and a carry bit from the bits immediately to the right Note also that each addition produces 2 bits the result bit S and the carry bit C Now let s make a truth table for this addition process The truth table will have three variables one bit from each of the numbers A and B and a carry in bit Cin which represents the carry from the previous position The two outputs are the sum bit and the carry out bit Coyt Which will be used in the next position Cin Cout S 0 00 0 0 0 1 0 1 0 10 0 1 0 1 1 1 0 100 0 1 101 1 0 1 1 0 1 0 1 1 1 1 1 We ll use Karnaugh maps to simplify the two functions in the table above into MSOP form 5 C A aut 00 01 11 10 Figure 1 Full Adder Karnaugh Maps As shown above the MSOP functions for S and Cout are Sum AB C 4 A BC ABC Cout AB AC 8C We can implement the function for Cout in a straightforward manner as shown below Or gt Figure 2 Full Adder Carry Circuit 36 The MSOP form is a bit more complex however If we examine this function a bit more closely though we will see the now familiar checkerboard pattern in the K map and notice that S is only equal to 1 when an odd number of the input variables are I the truth table The function for S can therefore be easily implemented with an XOR function as shown below Sum 8 C 0 3 Figure 3 Full Adder Sum Cir
18. of converting BCD values to the proper signals to drive this display The display has seven separate bar shaped LED s arranged as shown In addition many seven segment displays have one or two circular LED used as a decimal point Figure 1 A Seven Segment Display 24 Inside the seven segment display one end of each LED is connected to a common point This common point is tied either to ground or to the positive supply depending on the specific device If your seven segment display is designed to have the common connection tied to the positive supply 5V it is called a common anode configuration as shown below To light these LED segments the inputs must be a logic low Common 5 Voc LED Segment Inputs Figure 2 Common Anode Seven Segment Display Circuitry To actually light up a single LED segment a resistor must be added to limit the current through the LED This resistor is critical If you connect the LED between 5V and ground without the resistor the LED will momentarily glow bright and then never glow again For this display use a 220 9 resistor as Shown below 5 Voc 2200 Fb Fi Figure 3 Resistors used with a Common Anode Seven Segment Display 25 If Fa etc 5 V there is no voltage drop across the LED and resister resulting in no current flow through them and the LED remains dark If the inputs are 0 Volts a current 1s produced and the
19. pair of adders and used them to add two 2 bit numbers In this lab le will use an MSI chip containing four full adders to add and subtract two 4 bit signed numbers using one s complement arithmetic All of the chips used thus far have been SSI Small Scale Integration chips which consist of single gates MSI chips combine dozens of gates into a single function on a chip in this case a 4 bit full adder the 7483 LSI Large Scale Integration and VLSI Very Large Scale Integration combine hundreds or thousands of gates into very complex devices on a single chip Microprocessors and related components fit into these categories Remember that by using one s complement arithmetic we can both add and subtract with the same circuitry The problem remains of how to complement a number so that subtraction can be performed 39 Section 2 Adder Subtractor Part I Let us recall the operation of an XOR gate Note that if one input is 0 the output equals the other input On the other hand if one input is 1 then the output equals the complement of the other input 1 d X X A X Figure 1 Using an XOR Gate as an Inverter We can thus use XOR gates to perform a one s complement on command In 1 In 2 In 3 In 4 Complement Out 1 Out 2 Out 3 Out 4 Figure 2 Using XOR Gates as a One s Complementor In block diagram form the 7483 would appear as shown B 8 C Figure 3 Block Diagram of 7483 40 N
20. 0 C OUO 4 Di With only two input AND and OR gates the decoding for D3 alone would require four packages thus the NI ELVIS is not large enough Leaving that for the moment you move on to D9 This looks bad superficially but after a moment s reflection you realize that can be implemented with dual 2 input XOR gates Dq must have Q 4 but this is available on the 74175 Well two out of three implemented and less than two full chips used isn t bad for a start If you could implement the remaining bit with three or fewer chips plus two XOR gates you ll have the rest of the semester off You next try using a J K flip flop for bit three You decide trying to figure out how to use some XOR s to implement D3 would take too long and might not work anyway As it turns out the J and inputs for can be realized using one 7408 and one OR gate Determine the appropriate circuitry for J and and connect the whole mess using a switch for the control bit In addition connect one of the switches to the clear inputs of the 7476 and the 74175 to allow presetting of the counter to 000 This should be the switch that goes low when the button is pressed you can use pushbutton PB switch provided on the NI ELVIS board These switches are pre configured for active low operations Note that the preset pin of the 7476 must be tied to 5V Use three lights for the output Which bit goes to the left most light Initially
21. 1 V PR2 Cr2 A1 B1 Y1 A2 B2 Y2 GND inputs Outputs ck JTK a B AB X 7490 Decade and Binary 7495 4 Bit Shift Register Counter V 0 0 Q Q A NC QA QD GND QC iat A B GND RO ROQ NC 291 892 Operating Outputs _ s OS Tex Outputs R1 R2 R1 R2 J H L L L LIL x L X L 00 LIL x MI X I M Qo L L X Load n x MI6 0 61 2 X EE L No Change L L L X X No Change L Mode LI H L No Change X Change H L X X Undetermined L L H X X Undetermined T L H X X No Change L H H X X Undetermined 7483 4 Bit Full Adder with Fast Carry BA 54 C4 GND B1 A1 21 4 A3 B3 V 22 82 2 L L LI L LI L LI L LI L LI L LI L LI Ti Le 0 TLI r Ta code bak LL rur LL LL I LL LL I I rr L IL II LI IL IL LL Irr gt LL LL I LI LL IL IL IL IL II LI LL Compiled by Dr W J Reid Spring 2002 17 209 Lab Kit Chip Pin Outs 74151 74193 74151 8 0 1 74153 Dual 4 to 1 74175 Quad Select
22. LABORATORY MANUAL ECE 209 Logic and Computing Devices Clemson University Department of Electrical and Computer Engineering Clemson SC 29634 Compiled August 2015 Table of Contents I Lab Read lab introduction before coming to your first ECE 209 lab II Lab Kit III Labs Lab KitHandoUU Chip Pinouts 7400 7447 eee enn Chip Pinouts 7403 dace DEDI M rin eT ua EE bos Chip Pinouts 74151 74193 Data Sheet Resources Lab I Logic Gates A Smart Lighting System Lab 2 Encoding Decoding Seven Segment LED Display Lab 3 Combinational Circuits Parity Generation amp Detection Lab 4 Binary Arithmetic Adders 1 Lab 5 MSI Circuits Adders _ Lab 6 Multiplexers and Serial Communications Lab7 Mul pliers ee Lab 8 Memory Cache Lab9 Sequential Design 1 209 Lab Introduction PURPOSE To familiarize students with the basis of safety lab procedures and the equipment to be used throughout the course EQUIPMENT ECE 209 Lab Kit REQUIREMENTS Each student should read and understand this introduction prior to the first lab meeting SAFETY Whenever electricity is used in an experi
23. NC OUT hole on the NI ELVIS board You can adjust the frequency using the GUI You can also use the Sweep Settings to vary the frequency automatically with a predetermined step For instance if you want to start a waveform with a frequency of 100 Hz increment the frequency by 100 Hz after every 10 seconds and stop the waveform generation when the frequency reaches 1 kHz you can use the sweep settings as shown in Figure 6 Press the Sweep button and you will get the desired waveform on FUNC OUT hole on the board USING OSCILLOSCOPE Additionally you can use the oscilloscope tool to watch the waveform that you generated using the Function Generator Connect a wire from FUNC OUT hole to one of the positive Analog inputs for example and connect ACHO to the GND hole on the board Press the Scope button on the NI ELVISmx Instrument Launcher oscilloscope GUI will pop up Select the channel and the source and press the Run button you should see the waveform output of the FUNC OUT as shown in Figure 7 gt NI ELVISmx Oscilloscope 1 E a xl Channel 0 Settings Source Channel 1 Settings Source SCOPE 1 Enabled Probe Coupling 1 9 Dc Sample Rate 1 5 5 Enabled Probe Coupling Lx Do Scale vertical Scale vertical voltsi Div Position Volts Div Position gt Z Vertical Position 0 1 9 o2 Timebase
24. a square waveform for input B Adjust the frequency 1 Hz for the pulse so that the LED LL lights on and off when the pulse goes high and low respectively Then have your instructor verify the count Section 2 Implementing a Function with Different Gates It s possible to implement this same function using only AND OR and NOT gates by using the definition of the XOR function Using Boolean Algebra B 9 B M 2 B M 2 2 22 gt 3 a diagram for this circuit showing how to use 2 input AND gates to make the 3 input AND s Wiring and checking this circuit is optional Section 3 Realizing an Arbitrary Boolean Function Now that we have looked at a real life example let s look at an arbitrary function to see how we might realize it Rather than specifying the logic with words as in the previous example we will use a truth table This will be a function of four variables A B C D giving the truth table will have 16 entries ABCD F ABCD 0000 1 1000 1 0001 O0 1001 0 0010 1 1010 1 0011 1 1011 0 0100 0 1100 0 0101 0 1101 0 0110 1 1110 1 0111 0 1111 1 Using your Boolean algebra skills you can write an equation for this expression and simplify it to Minimal Sum Of Products form MSOP which gives you F B D A B C CD Das a circuit for this function using only AND OR and NOT gates The function calls for two 3
25. all switches already found in the room Assuming that the room has two doors then a three way switch at each door would be convenient In this configuration the light 15 off if both switches up or both are down and it is on if one switch is up and the other is down This allows for the light to be switched no matter what the state of the switches 1s 20 Switch Switch Common Figure 1 Wiring of a Three Way Switch For the lights to come on in our design not only must one switch be up and one down but a person must also be detected unless one of the other conditions Burglar Alarm or Master Switch turns them on Note that the person detector would probably have a timer which keeps the output high for a designated time after a person 15 detected Basically what we need is a circuit which will switch the lights on if and only if The Burglar Alarm is On OR The Master Switch is On OR A person is detected AND one but not both auxiliary switches is up Now let s assign some variable names to the various switches inputs so that we can write an equation to describe the desired binary function Let B Burglar Alarm M Master Switch P Person Detector A Auxiliary Switch 1 and 2 Auxiliary Switch 2 Note that the necessary condition of A4 and A to activate the lights 1s an Exclusive OR function one but not both Using XOR symbol 8 we can write the desired lighting function
26. and a wire is inserted into that hole the wire may not make contact with the internal connection strip and the circuit will not operate properly An even more aggravating situation is when the wire makes contact only part of the time This is called an intermittent fault Since the circuit will operate correctly part of the time then mysteriously fail this type of fault is very hard to find A good rule to follow is if the wire doesn t go in easily find another wire Pay particular attention to components such as resistors capacitors etc since many have lead with diameters which allow insertion into the protoboard but still cause damage to the contacts To avoid damage do not insert wires too far You will have to strip the wire leads before using them to interconnect circuits on your protoboards The proper way to do this is to use a pair of wire cutters to carefully strip inch of insulation off of each end of the wire taking care not to nick the copper wire If you take more than a quarter inch off you risk having wire exposed above the protoboard which will cause a short if it touches another lead or IC pin If you cut less that a quarter off the wire may not make a good connection within the protoboard hole It also helps to cut the ends of the wire at an angle which produces a point on the end of the wire The wire will then slide into the protoboard easier NI ELVIS II You will be using NI ELVIS II works
27. cache hit miss We will be looking at a scheme known as direct mapped caching So before we can get started we need to examine how a direct mapped cache works A cache is divided into a number of lines A line is a contiguous block of bytes in the memory that are stored at a single cache address We will be designing circuits for a fictional computer which has a 16 bit address bus and a cache made up of 16 lines containing 256 Bytes each This means our computer will be able to address a total of 64 KB of RAM and at time a maximum 16 256 4096 or 4 KB of this memory will be in the cache To use our direct mapped cache we will break the address into three fields Since the 256 bytes that make up a line block are contiguous the last 8 bits 9 256 of any address 15 the offset into the cache line Since there are 16 lines in the cache we need four bits of the address to determine which line in the cache the address will be in The upper four bits of the address are the cache tag telling us which block is present The decomposition of the address into fields is shown in the following figure 55 Tag Cache Line Other Address Figure 1 Fields of a Memory Address For example an address of 1111001000110010 0xF 232 has a tag of OxF a line address of 0 2 and an offset of 0x32 This type of cache is called direct mapped because there is
28. cuit These two circuits together are called a full adder Section 2 Building a 2 bit Full Adder r rs ss You are going to build a device which will add two unsigned 2 bit numbers Use pair of switches for each input value The results will be displayed on LEDs You will need to build two copies of the full adder The carry input to the right most adder will be tied to GND The carry in of the left adder will be tied to the carry out of the right adder What happens to the carry out of the left adder In block diagram form the 2 bit Full Adder looks like 54 52 ale A B C Full Adder Full Adder LED for LED for LED for SUMI SUM Sum Figure 4 Full Adder Circuit 37 You will need one 7486 two 7408 s and two 743279 to build the above circuit gt In this simulation you will build some simple circuits with gates and then use multiple copies of those circuits to build a larger more complicated device This is typical of how system design is done We use this same kind of procedure with Computer Aided Design CAD tools like your Logisim Ideally you would like to enter the circuit for a full adder once test and debug it then turn it into a part we can use over and over again Then you could simply use two of those parts and draw the connections between them to build your two bit adder This is called a hierarchichal design In Logisim it s known as subcircuiting In Logisim hi
29. e simulator software Logisim can be downloaded from http www cburch com logisim download html Also the documentation that goes with the software is available from http www cburch com logisim docs html or under Help menu in the software itself A collection of 74 IC s are available as precompiled library at http www cburch com logisim download 7400 lib zip which are designed by Ben Oztalay CONCLUSION The labs you are going to perform are fun Take your time Ask lots of questions so that you can learn as much as possible You ve paid for it Understand everything that an experiment can show you Try variations of circuits The amount of information you learn from these labs 1s directly proportional to the amount of thought and effort you put into them If you have any suggestions on how you could make this lab more informative or interesting please see the professor in charge Bill Reid Dan Stanzione and Nitendra Nath Updated by Dr Robert Schalkoff and Anjan Rayamajhi 2015 13 209 Lab Kit Notes To interconnect your Integrated Circuits IC s properly the pin numbers must be known Each chip has an orientation notch which defines where pin 1 is located When the notch is on the left pin one is on the bottom left The pins are numbered counterclockwise from 1 6 _ 9 DV74LS 374N ETE AVG9Z21DDi Orientation Notch Each chip has a part number stamped on
30. edure BACKGROUND Memory A computer s memory is organized as a linear collection of storage locations Each location has an address Typical computer memories are byte addressable meaning that each byte in the memory has its own unique address even though you usually read the memory a word at a time and a word 1 typically greater than a byte The size of the address limits the amount of memory the computer can see Most computers use at least a 32 bit address bus meaning they can address j Bytes or 4 GB of memory Naturally the first Byte of memory is located at address 0000000046 and the last one is located at FFFFFFFF16 One of the most fundamental things a computer has to do 15 retrieve information from memory The main memory of a computer stores both the programs the computer will run and the data the programs need During operation a computer s processor continuously generates a stream of addresses first to get instructions out of the memory and then to fetch the data operands that those instructions need Memory Hierarchy Unfortunately memory is relatively slow and expensive when compared to processors As a result a CPU can spend a lot of its time doing nothing while it waits for a memory request to complete In fact 54 bandwidth the amount of data you can transmit in a given time interval to memory is one of the primary limiting factors in a computer s efficiency It is called the von Neumann bottleneck
31. ent carefully Don t drop anything e Put all components back where they are supposed to be e Before leaving the lab check that your bench position is neat and orderly and check the floor for wires Report any defective equipment to the instructor Turn off all equipment and make sure the bench power is off EQUIPMENT The proper care of the equipment used in this lab is essential If handled improperly many of the devices used to perform the experiments will give erroneous readings or fail to operate altogether Protoboard Your kit includes a plastic board used to wire together electric circuits This is called a breadboard or a protoboard since it is used to prototype circuits Figure below shows how the terminals are connected internally inside the board The horizontal connections X and Y are called buses and are usually for power and ground Each of these contacts are tied together m I POM MM s m m m mH N i PRR HM B s m m m m B B B H E TERE J a ERE I Be m i E T m s sx ee
32. erarchy is achieved by using subcircuits You used a subcircuit in the previous lab for the 7447 driver chip This week you will want to create your own subcircuit for the full adder circuit See the online Logisim Getting Started guide for details on how Once your subcircuit is created you will create another schematic that uses two copies of the subcircuit and adding the switches and lights Your resulting schematic should look like the block diagram of the circuit shown above HINT It will probably be easier if you use one 7408 and one 7432 for each carry generator rather than using one chip for parts of both full adders This way the two carry circuits can have identical pin assignments and also be physically separate to help avoid confusion This also makes 1t possible for you to label the pins correctly inside your full adder subcircuit You are to turn in copies of the schematic for you full adder subcircuit as well as your final circuit in lab 38 ECE 209 5 MSI Circuits Four Bit Adder Subtractor with Decimal Output PURPOSE To familiarize students with Medium Scale Integration MSI technology specifically adders The student should also become familiar with 1 s complement arithmetic EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II Simulation Software REQUIREMENTS e Simulation of functional Full Adder e Functional Full Adder Circuit PROCEDURE Section 1 Adders In the last experiment we built a
33. even segment Display 555555 ab I oeven Segment Display Figure 5 Adder Subtractor with Display Construct and test the operation of the circuit above 42 The XOR s above may not be necessary depending on the type of seven segment display udi i you using If the seven segment display is a common anode design then the sum 94 So must be inverted by XOR s because the segments are lit by sending segment inputs a through g low 0 instead of high This might seem strange but it will make perfect sense once you have studied the internal structure of TTL gates If you are using a common cathode type device then these gates are not necessary BS C514RD S403 11HDB GF AB A 5 G C LI C D 3 14 3 8 Cathode 113108 72119 6 AIBICIDI EI FI H 7642 19105 Figure 6 Common Anode Common Cathode Displays Remember that the seven segment display must use resistors to limit the current through the LED s Be careful not to short the resistor leads together This may result in a decrease in resistance and an thus an increase in current through the led segment causing it to quickly burn out and never shine again You need only to disconnect the wires to the lights in the first circuit The rest can be left intact 9 Questions to turn in with the lab report Do you
34. hat we ve already figured out how to do After that it s up to you 50 BACKGROUND The first thing you need to know about multiplication is that the AND operation works just like decimal multiplication 1 1 1 and 0 0 0 1 1 0 0 The AND operator even has the same symbol as decimal multiplication So if you need to multiply a number by a single bit you can simply use AND gates Consider the example below 1011 1011 X 1 X 0 1011 0000 1 0 1 1 1 0 1 1 1 0 1 0 1 1 0 0 0 0 Things get a little more complicated when your multiplier has more than one bit The Boolean AND operator functions only with Boolean variables so we can only AND bits together not binary integers So how do we multiply multi bit numbers together One way is to do things the same way we would perform the multiplication on paper multiply the first number by the least significant bit of the second number then add that result to the one you get by multiplying by the next bit and so on as shown in the example below 10 11 11 X 1101 13 10 ii 33 0000 11 1011 1011 10001111 128 15 143 Note that we get an eight bit number from multiplying two four bit numbers 51 In the general case we can rewrite the problem symbolically below where P is the product AND of bit i of the multiplicand top number with bit j of the multiplier and S 1 the sum of the column of numbers above it A2 1 Ao X B2 P30 P20 P
35. io Poo P31 P21 Pii Poi P32 P22 Pi2 Poo P33 P23 1 57 56 55 54 53 52 51 So That s pretty close to something we can build We can multiply by single numbers and we can add numbers together The only complication is the adders we know how to build can only add two numbers at a time In this case we need to add up to five bits at a time so we might want to create some partial sums to make use of the adders we have A possible way to do this 1 shown below A2 Ao X Bo 80 P30 P20 Pio Poo P31 21 Pii Poi 505 502 501 Soo P32 P22 12 516 S15 S14 513 512 511 Soo P33 P23 57 56 55 S4 53 52 51 50 where 5 represents the r output of the i adder Notice that 505 is the carry of the first adder 516 is the carry of the second adder and 57 is the carry of the third adder Also note that Soo is simply Poo 511 15 equal to 501 and 52 1 512 Therefore we need only three four bit adders which we have already built in lab 22 PROCEDURE 55555555 Bring an electronic copy of your design to lab with you and be prepared to demonstrate the operation of your functional multiplier Add appropriate switches and lights so that you can input two 4 bit numbers and see your 8 bit output lus in a printout of your final schematic plus printouts of any macros you used in your designs as well 1 mami 7 Y Turn in a brief report describing your c
36. ircuit design In your report consider if and how well this circuit design would scale up to multiplying bigger numbers Answer the following questions in your report e What would be the strengths and weaknesses of a large multiplier built in this fashion e What would the propagation delay be for the circuit in your simulation assuming a 1 ns delay for each gate A Note on Multipliers The multiplier you just built is pretty close to the kind used in high end arithmetic circuits a kind of multiplier known as an array multiplier Real array multipliers pass the carry through the adders to the last one rather than using ripple or look ahead adders to add the partial sums A special look ahead adder is designed for the last stage to speed up the process Multipliers built in this way are produce about the highest performance possible Many multipliers however are not built in this fashion A typical chip will use a much smaller slower but more complicated multiplier design based on registers which will be discussed 1n class 53 ECE 209 Lab 8 Logic Design for a Direct Mapped Cache PURPOSE To understand the function and design of a direct mapped memory cache EQUIPMENT Simulation Software REQUIREMENTS e Electronic copy of your design e Schematic of final design e Printout s of any macro s you used in your design e Brief report describing your circuit design and answering questions asked in the proc
37. l as this will allow you to manually switch between HI and LO for a specific line or input Hit the green arrow button to run the GUI Now you can manually switch between HI and LO inputs for any number of input lines you selected 0 7 For instance if you select to write 0 7 lines and make all the 8 inputs HI DI 0 DI 7 circled as number 4 on Figure 3 will be set to HI or logic 1 on the NI ELVIS board A particular point on the protoboard connected to any of these DIs will receive a HI input USING FUNCTION GENERATOR To generate a square or pulse waveform press the FGEN button on the NI ELVISmx Instrument Launcher A GUI as shown in Figure 6 will pop up 3 ELVISmz Function Generator Waveform Settings Frequency Amplitude DC Offset P I E gt 2 0 0 10 0 5 0 5 0 1 00 0 00 200m Duty Cycle Modulation Type 100 Hz 50 eus Mone d Sweep Settings Stark Frequency Stop Frequency Step Step Interval 100 H 1 0k Hz 100 00 Hz 1000 ms Instrument Control Device Signal Route Dew MI ELVIS IT Prototyping board Sweep Stop Help Manual Mode ES ve E e Figure 6 NI ELVISmx Function Generator Press the square waveform button third button given in blue under Waveform Settings Set the Amplitude to 5 Vpp and keep DC Offset as zero Press the Run button and you will get the desired waveform on the FU
38. les on your protoboard all of the top row will be energized to 5V We will use only 5V and Ground in this lab Digital inputs used to provide either 5 V or GRD to the associated tie points You could move a wire between 5 V and GRD to provide the same function but it is much easier to use the switches when a lot of changes are going to be required These switches can be programmed In this lab we will program these switches using NI ELVIS software as shown later to give digital inputs to the protoboard A wire from one of the holes of the switch in use is connected to the specific point on the protoboard How to control these switches will be shown later Function Generator Inputs LED s that can be used to indicate ground Cam nw pe ner You can i arie ED d ha mud de other end into a specific point on Function Generator FUNC GEN 15 used different waveforms to the specific pone on the poen ug a square ofa deed dici ency This waveform can be described as a 5 V to ground to 5 V sequence or vice versa on a wire You could do the same thing by moving a switch described then back However the switch is a echanical device and does not make each transition smoothly The switch actually bounces on its contacts causing a senes of FUNC GEN wire from one of the holes of the FUNC OUT is connected to the specific point on the protoboard How to generate a wavefo
39. low to light the segments except the pin connected to the center horizontal LED That is segments a through f See Figure 1 What we need to do now 1s determine the appropriate combinational circuit to light each segment That is the each segment is turned on by certain Boolean function For example segment 1 lit for 0 2 3 5 6 7 8 and 9 Therefore the circuit must produce a logic zero for these numbers to light segment a That is it must produce a logic one for the numbers 1 and 4 Remember that BCD numbers use only ten of the sixteen possible combinations of four bits 0 9 Therefore we do not care what comes out of the circuit for the last six inputs through 1111 since these inputs should never occur The resulting symbol for these inputs should be whatever it takes to produce the least complicated circuit 21 For the function of segment a we have the following truth table DCBA Fa 000 0 0 1000 0 0001 1 1001 0 0010 0 1010 X 0011 0 1011 7 0100 1 1100 X 0101 0 1101 x 0110 0 1110 x 0111 0 1111 X The X s in the truth table above indicate the don t care conditions that 1 rows the table where we do not care what the output of the function 1s Using Boolean algebra we can write the minimum sum of products MSOP expression for as F D C B A CB A 9 What comes out of this circuit for each of the six invalid inputs For example what would be if the input were
40. ment some danger exits This should always be on your mind Most of the experiments in this course will use only low voltages which are not inherently dangerous However it 1s possible to incorrectly wire almost any experiment such that dangerous voltage levels result Subsequent lab courses require the use of high voltages There is only one way to prevent accidents THINK Plan what you are going to do Understand what you are being asked to do Ask questions Never turn the power on until you are confident that everything is safe The careless use of electricity can have two results It can hurt you It can hurt equipment Obviously you want to avoid hurting anything To project yourself always treat electricity with respect Don t handle hot lead wires Don t leave wire dangling about in space An old rule of thumb is to keep one hand in your pocket at all times This hopefully prevents the flow of electricity from one hand to another potentially causing the heart to stop Keeping one hand in your pocket also causes cramps and decreases efficiency so no one does it But keep in mind that when you touch a wire that is electrified the electricity will always want to flow and it is to your advantage to keep it from flowing through you Don t hold electrified wire and make sure that no part of your body inadvertently comes into contact with a wire To protect equipment make sure that all of the hookups between power supplies oscill
41. only one place in the cache where each address in memory may reside However since the cache 15 only 4 kB and the whole memory is 64 kB only 16 of the possible 256 lines can be in the cache at any one time The mapping of 256 bytes of memory to the cache lines is shown below Only memory addresses whose cache line address field matches can be in a particular cache line Therefore if you are looking at cache line address 3 only memory addresses who have the bits 0011 in bits b11 bg can go into that cache line That is the only 256 byte blocks whose addresses start at 0 0300 0 1300 0x2300 OxF300 can go into cache line 3 Blocks that fit into a particular cache line are shown across a row in the figure below Cache Main Memory Line Tag Content Valid Blocks each block contains 256 B 0000 0 I 0001 1 D 001 0010 2 010200 1 0011 8 1 0100 4 6154000 0101 5 mmg 500 1 2500 35 0110 6 010600 1 50 0 60 0111 7 ojo7oo o 2700 1000 8 7 7800 o 7 TEIE 80 1001 9 8 8900 0 290 900 2900 F90 1010 Loof O s FA00 1011 8 00 00 1 1100 C T Seno rcoo coo 5200 P 666 666 1101 D 0 1 I 1110 1 1 1111 1 56 Note that for every address that goes into a single cache line the line address is always the same and there is exactly one block possible for each of the 16 tags Therefore
42. or MUX Multiplexer D type Flip Flop ba 04 D5 06 07 rd 5 CA2 CA1 V Q4 Q4 D4 D3 03 Q3 Clock 15 14 13 12 11 Selects Inputs ae 2 3 4 5 6 7 8 1 D3 D2 D1 DO W Strobe GND Stobe B 1 YB GND Clear Q1 01 01 02 02 Q2 GND e Oupus Gir Clock D a X H XI X X X X H L E d L L 5 L L X E I E H L L L L H L H L L L LI L L L H H L H L H L L H L L L 5 HL H L H oe 1 H X L 1 H Hj H L H H L H 74155 Decoders 74193 Dual Sync Counter Demultiplexers w separate UP Down Clocks V CA GA Seect 2 YA1 YAO A Clear Borow Cary Load GD 16 15 14 13 12 111 _ I rae 2 3 4 5 6 18 Data Strobe YB2 YB1 GND Data QB QA Count Count QC QD GND Select B Down Up GB 3 to 8 Decoder or 1 to 8 Demultiplexer Seven Segment Displays _____ Outputs Selects Strobe 0 0 2 3 4 5 6 D BS C5 14RD YB2 V83 yao 1 2 YA3 1 I HDB GF AB X X X H H H H H H H L L L L L H H H H H H H L L H L L H H H H H H A 5 L H L L H L H H H H H F B L H H L L H H H H H L L L H H H H L H H H T H L H L H H H L H H G H H L L H H H H H L H C H H H L H H H H H L 3 0 8 Decoder 1 to 8 Demultiplexer C D Inputs Out
43. or to insertion into the protoboards This can be done easily by flattening the legs on a table top as shown below Ask you instructor to show you how this is done if you need help From factory Bend one side then the other till legs are parallel Figure 9 Straightening IC Legs When you remove a chip IC from the protoboard it 1s very easy to bend the legs by not exercising caution You should not simply pull on the chip with two fingers to remove it 11 One end will invariably rise before the other causing the legs on the other end to bend It may even result in a puncture wound to one of your fingers because the legs of the IC s are very sharp Be careful If an IC extractor is not available you should use the tip of a pen or pencil to gently pry up the legs on one end of the chip and then the other as shown below Figure 10 An IC Extractor Figure 10 Removing an IC 12 Again ask your instructor to show you if you need some help Usually if a leg is bent twice it will break off easily and the IC is virtually useless so LAB REPORTS Each report should as a minimum include e Objectives e Circuit diagram Simulation e Explanation of circuit operation e Results Conclusions and suggestions Failure to include these lab sections will rult in a reduced report grade WORKING WITH THE SIMULATOR See the User manual for an introduction to the simulator software before your first lab Th
44. oscopes volt ohm meters light emitting diodes LED s protoboards chips etc are as you want them to be Double check all wiring prior to turning on the power One way to destroy an Integrated Circuit 1 is to reverse power leads You can tell because the abused I C will start smoking or will get so hot you cannot touch it Then throw away the LC When probing a circuit with test lead make absolutely certain that you are making contact with the exact points you wish to test and ONLY those points When using a particular piece of test equipment understand the limitations of the equipment Don t try to use it to test something it wasn t designed to test Read the manual In summary the way to keep yourself and the equipment from being damaged 15 to do everything slowly cautiously and carefully GOOD LAB PROCEDURES In order to make your experiments go easier there are some procedures which should be followed Most are generally common sense e Before wiring a circuit a circuit diagram should be drawn and simulated This diagram should include pin numbers as shown below You can then check off each connection as it is wired For example after the top AND gate is connected to the OR gate on the right the line connecting them in the diagram should be checked off as having been wired Without some system like this it is very easy to forget which gate 1s which within a system f you don t have a properly labeled circ
45. ote that the carries are already interconnected within the chip The right most carry in Co and left most carry out C4 are available for cascading to other 748375 or other uses The A s and B s are the inputs addends and the S s are the outputs sum Label the pin numbers on the following circuit construct it and verify that it both adds and subtracts A and B correctly Check pin numbers for power and ground A Add Subtract Figure 4 Using the 7483 for Addition and Subtraction If only four switches are present you can use these for the bits of A and simply plug the B s into either 5 V or ground to produce B e g For 3 let GND GND 5 5 V 9 What happens if we add 0011 and 0111 Is the result correct Why or why not 9 Why 15 C4 connected to Co Be sure both chips are at one end of the breadboard to facilitate the further expansion of o the circuit 4 Part Il It would be handy if we could display our results in a more easily readable form Using another XOR package a seven segment display a few resistors to limit current so the seven segment display won t smoke and a BCD to seven segment decoder an extension of your second Lab this goal may be achieved by means of the following circuit How are the XOR s used to switch between Addition and Subtraction B SW1 B SW2 B SW3 8 SW4 Add Subtract BC D to S
46. puts __ Inputs Outpts Common 14 ED CH cA vao var va2 vas 280 vB 82 _ ated 113108 7 2 1196 AI BI CIDI El F 164219105 Compiled by Dr W J Reid Spring 2002 18 Lab Kit Other resources Fairchild Data Sheets on the Web Texas Instruments Data Sheets on the Web 19 209 Lab 1 Logic Gates A Smart Lighting System PURPOSE In this experiment you will explore the notion of combinational circuits and basic combinational design EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II REQUIREMENTS e Circuit diagrams for all three circuits with pin numbers clearly labeled e Verbal description of the function of the final circuit Truth table for the first function the light controller PROCEDURE Section 1 Designing and Building a Digital Light Control Consider the problem of constructing a light controller for a certain room in a house It 1s desirable for the light to be switched on if 1 A Burglar Alarm detects an intruder 2 A Master Light Switch is on or 3 An Auxiliary Switching system is active and a person s is are present in the room Item 3 requires further consideration First of all how is the system going to know if a person is in the room A motion and or sound detector could be used to produce a logic 1 Boolean True person 15 detected The auxiliary switches mentioned above could be the w
47. rm will be shown later Analog inputs holes are used to give inputs to an oscilloscope These inputs will be used only if you intend to see the generated square waveform on the MI USING DIGITAL INPUTS SWITCHES AS LOGIC INPUTS As mentioned above digital inputs are used to provide either 5 V or GRD to the associated tie points The NI ELVIS board allows you to control these switches using NI ELVISmx Instrument software Open the NI ELVISmx Instrument Launcher on the PC connected to the NI ELVIS board You will see a GUI as shown in Figure 4 NI ELVISmx Instrument Launcher E E ma Lr VPS Bode 55 ARB _ I DMM Scope DigIn Digut Imped 3 Wire Figure 4 ELVISmx Instrument Launcher Click on the DigOut button Another GUI NI ELVISmx Digital Writer will pop up as shown in Figure 5 MI ELVISmx Digital Writer Configuration Settings Lines to Write 7 gt Pattern Manual Manual Pattern A f n f HI Ww Lines 7 5 4 3 e 1 LI Action Direction Toggle Rotate Shift Left Instrument Contral Device Generation Mode Devi ELVIS ID Run Continuously Run Stop Help 9 e Figure 5 NI ELVISmx Digital Writer You can now select the lines you wish to write using the drop down menu under Configuration Settings Leave the Pattern as Manua
48. rror may be introduced to one of the four inputs to the parity detector 34 209 Lab 4 Binary Arithmetic Adders PURPOSE The student should demonstrate knowledge of simple binary arithmetic and the mechanics of its use Each student is required to design simulate build and test a two bit full adder EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II Simulation Software REQUIREMENTS Simulation of functional Full Adder Functional Full Adder Circuit PROCEDURE Section 1 Adders Consider the problem of adding two single bit numbers A and B resulting in a single two bit answer The truth table for this operation is shown below AB 5 0 0 0 O 11 0 1 01 0 1 10 1 The two output functions are labeled and where S stands for sum is the low order bit of the output The C stands for carry and 1s the high order bit of the output The functions for S and C can be written as the two MSOP equations below C AB S A B A circuit that implements these two functions is known as a half adder This adder 1s referred to as a half adder because it only solves half the general problem of adding numbers with more than one bit Let s take a look at an example of what happens when we add two 8 bit numbers Carry 10111000 A 10111001 B 10101100 Sum 01100101 35 Note that except for the right most column we are actually adding three bits a bit from each of the 2
49. ry Switch By now you may be wondering what this has to do with multiplexers which are little electronic gizmos having no actual switch contacts no knob to turn or lever to position or anything of the sort It 44 is helpful to think of a multiplexer as a rotary switch whose position is controlled by a binary number input to the device How many control bits would we need to select one of sixteen positions The control inputs will henceforth be called select lines since they are used to select one and only one input to be routed to the output We can redraw our rotary switch as follows In 1 In 3 2 Out In 4 S S Control Selectors Inputs Em Figure 2 4 to 1 Multiplexer The selectors S and So determine which position the switch is in Note that the order of S and So is important S 15 the most significant bit whereas So is the least significant bit If we want to be slightly more technical we can formulate the Boolean equation for the output function of a four input multiplexer as f S S I 5 5 1 5 5 1 5 5 1 Note that when a binary zero 00 15 on the select lines the output 1s equal to Ip when a binary three 11 is on the select lines equals etc Section 2 Application Serial Communication Some notes before we get started in this section in addition to using multiplexers and demultiplexers
50. s of multiplexing you think of Some notes on the simulation of this lab Your simulation package does not have 74151 and 74193 chip models Therefore you will have to make them from smaller parts that do exist The 74151 MUX can be made in one of two ways One approach would be to simply draw the AND OR diagram of an 8 1 MUX It s pretty simple you just need eight 4 input AND s each of which AND s the appropriate input line with the correct Minterm of the three select lines and an 8 input OR function Hint Once you place a gate in Logisim you can use the properties panel on the lower right column to change the number of inputs Another approach would be to take advantage of the 4 1 MUX you made for Section 1 of this lab Two 4 1 MUXes can easily be connected to form an 8 to 1 MUX as shown below 1 Enables E mm gt Output 72727222 Figure 7 8 to 1MUX from two 4 10 1 MUXes Logisim does supply a 4 bit counter subcircuit which could be used for the 74193 it 1s available in the external library but none of the pins are labeled making it hard to use Since we haven t covered counters yet a counter macro is supplied to you on the lab web page You will also find a macro for an 8 1 DEMUX on the lab page It is not exactly like the 74155 which can also be used as two 4 1 DEMUXes but it does ha
51. sign e State Transition Tables e Karnaugh Maps with Boolean reductions for each variable Brief report describing your circuit design and answering questions asked in the procedure PROCEDURE Assume that you have just designed and built a sequential circuit for a robot which will complete the remainder of your engineering classes for you All you need to complete it is an up down three bit counter It is Sunday night and you have three tests on Monday Unfortunately Radio Shack is closed so you will have to make do with your 209 Lab Kit or you will have to take those tests yourself Looking in your parts bag you find the following parts left 1 7476 Dual J K Flip flop 1 74175 Quad p Flip flop With several of each of the following 7408 Quad 2 input AND 7432 Quad 2 input OR 7486 Quad 2 input XOR Next you realize that the only thing remaining for you to construct the counter on is your NI ELVIS II board which limits you to only five chips 59 It is immediately obvious that the 7476 is insufficient since you need three flip flops thus you start by choosing the 7415 which contains four flip flops Next you do a quick design and using c as the control bit variable C 0 means count up c 1 means count down and 30201 as the counter bits you obtain the following equations for the three inputs to the D flip flop BO ud 204 po 055i 030 2 TOJO F 03020 1 D3 De 60 0 6050 me D 5
52. splay appears continuous to the human eye only slightly dimmer The battery is then required to supply a much smaller average current than when all the segments are displayed continuously Since LED s use a lot of current around 10mA all digits 8 this can greatly prolong battery life Time Multiplexing is also often used communication systems where independent data streams must be sent over a single line or channel The phone company does this on its lines 46 We are going to time multiplex the seven segments of a 7 segment display The 74193 counter will be used again where the three least significant bits driving both the Multiplexer and the Demultiplexer The Demultiplexer is essentially a backwards multiplexer one input and 2 outputs which are selected by select lines We will construct 1 8 demultiplexer from the 74155 Dual 1 to 4 demultiplexer The 74155 has two 1 10 4 demultiplexers one of which has an inverting input just to make life more difficult A functional diagram of the 74155 is shown below Enable 2 Enable 1 L STRB G2 ovg 2 Y 1 SIRBG1 4V0 1Y1 Input 1 Q DATA C1 1Y2 Input 2 DATA C2 gt N Figure 4 74155 Functional Diagram To use as a 1 to 8 demultiplexer connect as shown below G Inputs 1G and 2G connected together C Inputs 1C and 2C connected together 52 51 50 Figure 5 74155 Used as 1 to 8 Demultiplexer
53. tation equipped with Freescale board during this lab Each Freescale board has two protoboards in the middle It is recommended that you place your protoboard on top of the one that is connected to ELVIS II Freescale board This way you can use all of the functions provided by the ELVIS II and still be able to pick up your protoboard when the lab is finished with all connections intact Also you should pre wire the circuit called for by each lab in order to save valuable lab tme LE sd EE EL IE lt n ERI Figure 3 NI ELVIS Il There are several features of the NI ELVIS II workstation and Freescale board however we will just list and explain only those features that are required for this lab These features are numbered I through 7 on Figure 3 and are briefly explained as follows PROTOTYPING BOARD On Off Switch READY ACTIVE VOLTAGE oe PWR_SEL Jumper Power Supply Logic Inputs Turns the power to the ELVIS board on and off The power LED lights up when the switch 15 turned ON This allows to set the power input to the board by USB or Power Supply We will set this jumper as shown in the adjacent figure to input 5V power to the board using the power supply Provides 45V and ground to the tie points associated with them Therefore if you connect a wire from one of the 5V holes on the NI ELVIS Freescale board to the top row of ho
54. think the 7447 is classed as SSI MSI or LSI e In both circuits why are Co and C4 connected together e Why is the D input of the 7447 always 0 e What is the purpose of the 3 XOR s connected to the A B and C inputs of the 7447 Explain fully in your own words Explain how to convert the above circuit to perform two s complement arithmetic Draw the circuit and explain its use Hint Co can be used to form two s complement 43 209 Lab 6 Multiplexers and Serial Communication PURPOSE To familiarize students with the internal realization of multiplexers and to show an application of multiplexers and demultiplexers for use in serial communications EQUIPMENT ECE 209 Lab Kit amp NI ELVIS II Simulation Software REQUIREMENTS e Circuit diagram with pin numbers labeled e Verbal description of the function of the final circuit e Simulation of functional seven segment display circuit PROCEDURE Section 1 The Realization of a 4 bit Multiplexer A 4 to 1 multiplexer functions like a four position switch such as the one shown below The switch contact can be moved to any one of the four positions The switch can not be moved anywhere else 1 0 it must be in contact with one of the four inputs at any time The output signal of the rotary switch equals the signal on the input to which the switch rotor has been positioned Input 1 Input 2 Input 3 Output Input 4 Figure 1 Four Position Rota
55. uit diagram prior to the beginning of lab your instructor will give you a zero for lab performance While wiring rewiring etc turn off the power This prevents the application of power to the circuit in unwanted places Violation of this rule will result in decreased lab performance grades The voltages used in this lab are generally on detrimental to the chips not students But it is very important to learn proper safety techniques before you enter the higher voltage experiments of other classes e Try to avoid messy rat s nest wiring It is almost impossible to trouble shoot a messy wiring job It is also hard to make changes to a disorganized board Keep lead wires as short as possible and make neat flat bends It 1s also smart not to wire across the top of the IC s Wire the power leads of chips first using a color scheme if possible Traditionally in DC applications RED 5 Volts and BLACK Ground Notice that this is different from AC applications where black is hot white is neutral and green is ground You can expand on this e g use yellow wires for inputs and green for outputs This makes trouble shooting much easier e Wire circuits carefully It is easier to wire it right than to spend hours tracking down an error Make certain fragile leads are not bent excessively They will break off after being bent back and forth several times e Observe polarity markings on equipment and components Handle equipm
56. use the generated pulse or Square waveform at 1 Hz to clock the circuit 60 HINTS e out the complete state transition table to get J and This is not absolutely necessary but may avoid confusion and errors Compare the equations for J and K IL you don t immediately see how to implement with two XOR s factor out the and terms to recognize the XOR e Use an extra to invert c as you did for the adder subtractor circuit Verify that the circuit counts up if c is 0 and down if c is 1 Also verify that the active low switch clears the counter Note The clock of the 74175 must be inverted relative to that of the 7476 invert the clock with an XOR e Watch the power connections on the 7476 If you hook up pin 13 to 5V and pin 5 to Ground You will destroy the chip e Isit possible to implement within the stated limitations If so how 61
57. ve the low active outputs for this lab 49 ECE 209 Lab 7 Four Bit Combinational Multiplier PURPOSE To practice the combinational design process through the design of a 4 bit multiplier EQUIPMENT Simulation Software REQUIREMENTS e Electronic copy of your design e Schematic of final design e Printout s of any macro s you used in your design Brief report describing your circuit design and answering questions asked in the procedure INTRODUCTION This lab will be unlike previous labs in two very significant ways First we re going to design circuits that are too complex to fit on our breadboard with the parts in the lab kit so this lab will be done entirely with the simulator Second though this lab procedure will provide some insights into a possible design of a multiplier no circuit diagrams will be provided you will do the design completely on your own The circuit you will be designing is a four bit multiplier that is a circuit which inputs two 4 bit numbers and outputs their 8 bit product A truth table for this circuit would have eight inputs eight outputs and 256 rows You would need eight 8 variable Karnaugh maps to directly produce Boolean equations Since 8 variable Karnaugh maps would be quite unwieldy and we have not learned the Quine McCluskey algorithm we re going to have to think some about this one The following section describes the multiplication process in detail using steps t
58. we will use a 74193 counter chip You probably have not seen counters yet in your 201 lecture Don t worry you don t have to know how counters work in order to complete this lab You just have to know what they do they count in binary Connect the counter as shown at the end of this lab procedure 45 and it will count repeatedly through the numbers 000 to 111 on the outputs incrementing once each clock cycle toggle We ll discuss counter design after introducing sequential logic circuits You ll also need to make use of your 74151 8 to 1 multiplexer chip and your 74155 chip Strobe 2 Br uL Output G1 d j 1YO Data 1 D Output 1 gt 1V1 Output Select 3 Sc gt 1 1Y2 2 for 5 Output 1V3 gt Output Select 13 gt 2V0 D Output LL 2Y 1 Data 19 dn 1 output C2 d c 2 Strobe 14 E 2 C2 a 2Y3 Figure 3 74155 Logic Diagram Time multiplexing 1s often used with LED displays on calculators to reduce the amount of current the battery must supply to light the LED s Rather than lighting all of the segments at once one segment or groups of segments for multiple digits will be lit for a short time perhaps I ms Then the next segment or group will be lit for an equal time and so forth until all the segments have been lit Then the cycle repeats making each segment of display flash on and off so quickly that the di
59. x y and z and produce one output bit P The truth table for this parity generator 1 shown below 0 C0 CC C0 CC 0 OrFOoOrFOFrFO OF 111 0 Use Karnaugh to produce MSOP representation of this function by grouping the L s of the function 31 9 How many 2 input AND and OR gates and how many inverters would be required to implement the equation for P above Remember it takes two 2 input gates to make one 3 input gate ANDs ORS NOTS This circuit be implemented with the chips in your lab kit but it would leave only one OR gate and no AND gates to implement our entire parity detection circuit Not to mention that it would be a pain to wire up Can we simplify this function in order to simplify the hardware This is one of those examples where you see why engineers can t be replaced by computers yet The K map guarantees us MSOP form but that s not the simplest form for this problem Neither is the MPOS form we d get from grouping the zeroes Try it and see Notice that the Karnaugh map shows a checkerboard pattern every other square When this pattern exists the function can be implemented in either an XOR or XNOR operation The equation obtained for P can be simplified using the properties of Boolean algebra as follows P x y xy z x y xy z x9 y z x gt If we let A x y then we have A z Az
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