User Manual - Hytec Electronics Ltd
Contents
1. NAME PIN NO FUNCTION INPUTS CAT 2 Await Trigger stop after Jump conditioned OVF link 3 Pointer Overflow flag input STOP 4 Ext STOP Input ERR 5 Overall OR of possible ERRORS TIMEOUT 6 imer Expired CJNQ Fi Jump if No Q Response conditioned TCODE1 8 Trigger Code Binary value 1 TCODE2 9 Trigger Code Binary value 2 GO 20 Start doing Instructions B16 21 STOP or JUMP Instruction B15 22 JUMP Instruction or Q Ignore LOOPEND 23 Done all Loops NOT USED COSTAT 24 Q State This Instruction conditioned XSTAT 25 X State This Instruction BUSYFF 26 CAMAC Cycle started OK TCODE4 27 Trigger Code Binary value 4 Doc UM1341 Issue K Date 12 5 99 Page 15 20 Author PJM that the signal has been processed by the Jump Logic PAL Ic44 which looks at the Jump Condition Specifiers and the outputs of the comparator to OUTPUTS CKINST 10 Advance Pointer s FINISH Jd Set FINISHED LAM Status NO X 12 Set NO X LAM Status NO Q 1 3 Set NO Q LAM Status START T5 Do a CAMAC Cycle JUMP 16 Ready to load Jump Address SJUMP 17 Load Jump Address RGO 18 Reset Internal GO Flags Conditioned means decide whether to jump or not see below 7 Handy Hints and Conditional Jumping a Always remember to read the LAM Status things did not go as planned Look at the STOP condition ab see what happened and look at the Inst2. F HE RIGG will not GO P1341 AS A STANDARD ECTION 5 F LIST PROCESSO FOR THE D R Write Instruction Pointer F 17 ETAILS OF HOW TO US A 0 instructions you are going to write into the Ins F THE S ry EV EN ERS S To poin t to the s truction S S BE ri OF re ta CO he list of Doc UM1341 Issue K Date 12 5 99 Page 8 20 Author PJM Write Instruction Store F 16 A 0 Write a sequence of NAFs into the Store at incrementing addresses this happens automatically not necessary of course if they are already programmed in and you are just going to execute them again Finish with either a STOP instruction or a JUMP instruction Don t forget to add the Q IGNORE bit to any command where the module in question will valid circumstances If you do not do this the LP1341 will repeat the command for about 10 uSec and then STOP setting the NO Q status bit Write Instruction Pointer again to point to List trigger operation this must be at zero since that is where instructions should be loaded For normal operation with you can start anywhere only give X but not Q in Start Remember that for seven the bootstrap jump dataway GO or Trigger 1 Write Write Data Pointer F 17 A 1 Point to the beginning of an area of data memory into which you are going to put Write
3. familiar with the basic CAMAC Crates Those who do not this manual very carefully is to a lot work to operate this module t i here Section 7 contains n setting this device to ation about how the hardware actually works 1 Introduction This manual is really aimed at people who have already used the LP1340 List Processor or the T7 seven trigger variant and are principles of operation of Auxiliary Controllers in have that experience should read the data sheet and before making a start The best way to find out how start with th xample given and then progress from of valuable information about the possible pitfalls and some more detailed infor Users of the LP1340 T7 will find that this unit will unit except tha commands F 1 A 12 13 14 so they should be masked After you have s differs from its predecessor the LP 1340 t bits 5 8 of the LAM registers will always be read as 1 by tudied the data sheet on the module basic principles of operation of the unit what options are available and how that the run the same software as off by software the it this manual will outline The major differences between this unit and the LP 1340 are as follows a Larger Memories Data Store is 128K x 24 bits optionally 256K Instruction Store is 8K x 16 bits and can be EEPROM Both memories are battery backed b
4. HYTEC EL ECTRONICS LTD LP 1341 LIST PROCESSOR 128K OR 256K 7 TRIGGER VERSION AND PROGRAMMING INSTRUCTIONS F F F F TECHNICAL MANUAL 5 CRADOCK ROAD READING RG2 OJT U K Doc Issue Date UM1341 K Author 12 5 99 PJM August 1993 T ERING NOTIC Gl ENGIN IMPORTANT ENHANCEMENTS TO LP 1341 LIST PROCESSOR From serial number 516 onwards the LP 1341 is constructed using a new PCB issue 3 which incorporates a number of corrections and improvements The PCB issue number can be found on the component side of the board just below the wiring for the front panel Cannon connector The improvements are as follows a Incorrect Jump Address It has been found that a valid slave write command to the module can corrupt Jump Addresses This error has been corrected in the new artwork b Unwanted Pointer Incrementing In earlier models when a Jump instruction was not obeyed unwanted incrementing of either data pointer could occur dependi
5. The GO state of the List Processor is the logical OR of the following a he output of the GO flip flop set by a 0 to 1 transition on bit 4 of the LAM Status Register and b The output of the Triggered flip flop set by a 1 to 0 transition on a trigger signal if triggers are enabled When the List Processor s state machine detects a Stop condition and in this case we are thinking primarily of a Pointer Overflow condition it resets both of the above flip flops and then sets the appropriate LAM Status Register bits to show why it stopped After it has done this and if Triggers are Enabled the reception of another trigger will cause the LP1341 to examine the state of the Overflow flag and if it is set it will go through the routine of stopping on overflow that is setting the relevant bits in the status register and resetting the GO flag It is recommended therefore that an interrupt routine written to handle Stopped LAMS from an LP1341 working in triggered mode should Disable Triggers ON ENTRY to prevent this action interfering with the unloading of the list processor Doc UM1341 Issue K Date 12 5 99 Page 12 20 Author PJM 4 Operating Example 4 1 The following Program written in CATY shows a typical sequence being performe
6. FOR I 1 TO 100 100 Reads 440 FO LP 2 X Fetch Data 450 PRINT DATA ELEMENT 1 X 460 NEXT I 470 F25 LP 15 Reset finished with Engines 480 STOP 1000 PRINT LIST PROCESSOR NOT FREE 1010 STOP Doc UM1341 Issue K Date 12 5 99 Page 13 20 Author PJM 5 Seven Trigger Operation The Trigger Input connector on the front panel a 9 way Cannon socket pinout in section 8 brings in seven active low TTL trigger signals each pulled up by an internal 1Kohm resistor The trigger inputs are LEVEL sensitive and must be held low for a minimum of 300 nSec More than one trigger may be true at a time since they are prioritised and latched before presentation to the Main Logic Sequencer If one or more triggers ar present when a list completes then the highest numerical value trigger will then be serviced trigger 7 is highest The maximum delay between setting a trigger input true and the The trigger should b execute again be executed as soon as start of remov rent the A diffe Before any t riggers can be d befor ignored when disabled list execution is just under 2 microseconds for trigger 7 trigger 1 takes just 500 nSec Triggers ar the list in question completes or it will trigger MAY be present at this time however which will Logic Sequencer gets back to the reset state handled apart from th
7. 12 5 99 Page 17 20 Author PJM POWER CONSUMPTION Basic Module 2300 mA Typ 256K Memory option 100 mA Note Due to the high power consumption of this module we recommend that forced air cooling be used SIGNAL STANDARDS All inputs and outputs are at standard TTL signal levels all open collector CONNECTOR PINOUTS Rear ACB Connector 40 way header pin 1 bottom right 40 39 AL23 38 37 AL22 AL21 36 B85 AL20 AL19 34 33 AL18 AL17 32 31 AL16 AL15 30 29 AL14 AL13 28 27 AL12 AL11 26 25 AL10 ALO9 24 23 ALO8 ALO7 22 221 ALOG AL05 20 19 ALO4 ALO3 18 17 ALO2 ALO1 i ose GND Request Inhibit 14 13 GND Request 12 11 GND 10 09 GND ACL 08 07 GND EN16 06 05 EN 8 EN 4 04 03 EN 2 EN 1 02 01 GND All signals on the ACB are ACTIVE LOW Trigger Input Connector 9 way Cannon Socket Pin Function rigger Input 1 Standard Trigger rigger Input 2 rigger Input 3 rigger Input 4 rigger Input 5 rigger Input 6 rigger Input 7 ROUND OAD OBPWNE QHHAHHHHH Doc UM1341 Issue K Date 12 5 99 Page 18 20 Author PJM Parts list for LP1341 ISSUE 4 Part Type Outline Manufacturer TE 74622 74LS622 DIL20 IC2 74622 74LS622 DIL20 IC3 74622 74LS622 DIL20 IC4 74642 LS642 1 DIL20 ICS 74642 LS642 1 DIL20 IC6 74642 LS642 1 DIL20 IC7 74652 LS652 DIL24 3 IC8 74652 LS652 DIL24 3 TC9 7405 7405 DIL14 IC10 PLS100 PLS100 1341P10 DIL28 IC11 74245 HCT24
8. 341 fitted in t Greater Tha derived fro n type instructions a bit in the control ntrol Register is NOT fit used to work wi and is rep Multiple Trigger Inputs LP 1341 has seven trigger inputs via a front panel 9 way Cannon h invoke a bootstrap program which results in an he chosen list As we shall s connector jump to the start internal in the same way as the old LP1340 trigger also the L ks can still be used as T rigger 7 ted th the LP register Instruction Format as seen above 2 Configuring Before the List Processor can be assembled into a CAMAC system must be decided and its internal links set accordingly These are as follows JP1 JP23 Links to pe Input fron triggers a connects in Note All t Standard Setting same time is LP1341 this re wired in as TRIGGER 7 JP1 wire ORed t panel inadvisable trigger input and LAM1 and so on Fit later one of the triggers rmit the appearance of a given to start execution of a list of ins that this is with the and that use of both at the In the case of the level sensitive Trigger 1 may be rigger input with EMO 1340 s loop counter comparato is not sa a laced by a data comparator permitting JUMP if The Jump and Await Trigger function is taken over by bits in the new Jump formerly its operating mode LAM tructions EMO Trigg
9. 5 DIL20 IC12 74245 HCT245 DIL20 IC13 74245 HCT245 DIL20 IC14 74682 LS682 DIL20 ICIS 74682 LS682 DIL20 IC16 PAL22V10 1341P16V DIL24 3 IC17 PAL22V10 1341P17v DIL24 3 IC18 PAL22V10 1341P18V DIL24 3 ICL9 74593 LS593 DIL20 IC20 74593 LS593 DIL20 Ic21 74593 LS593 DIL20 EC22 74245 HCT245 DIL20 IC23 74245 HCT245 DIL20 IC24 74593 LS593 DIL20 IC25 74593 LS593 DIL20 IC26 74593 LS593 DIL20 IC27 74245 HCT245 DIL20 IC28 74245 HCT245 DIL20 IC29 7414 74LS14 DIL14 IC30 7475 74LS75 DIL16 Ic31 7408 74LS08 DIL14 IC32 628128 628128 DIL32 IC33 628128 628128 DIL32 IC34 628128 628128 DIL32 IC35 74593 LS593 DIL20 IC36 74593 LS593 DIL20 IC37 7474 74LS74 DIL14 IC38 7404 74LS04 DIL14 IC39 74047 74LS04 DIL14 IC40 74374 HCT374 DIL20 IC41 74374 HCT374 DIL20 IC42 74622 ALS622 DIL20 IC43 74622 ALS622 DIL20 IC44 PAL22V10 1341P44V DIL24 3 IC45 628128 628128 DIL32 IC46 628128 628128 DIL32 IC47 628128 628128 DIL32 IC48 6264 6264 DIL28 IC49 6264 6264 DIL28 IC50 PLS105 BRAINV9F DIL28 KER 256K Memory only Doc UM1341 Issue K Date 12 5 99 Page 19 20 Author PJM Parts list for LP1341 ISSUE 4 Part Type Outline Manufacturer Ic51 74174 74LS174 DIL16 Ic52 75452 75452 DIL8 IC53 PLS100 1341P53 DIL28 IC54 7475 74LS75 DIL16 Tc55 7408 74LS08 DIL14 IC56 7408 74LS08 DIL14 ICc57 7405 7405 DIL14 IC58 7430
10. 74LS30 DIL14 IC59 PAL18P8 LPPALV3 DIL20 IC60 PAL18P8 LPPALV3 DIL20 IC61 PAL16V8 LPTRIG2C DIL20 IC62 74374 LS374 DIL20 IC63 Not fitted IC64 Not fitted IC65 74132 74S132 DIL14 IC66 74747 74LS74 DIL14 IC67 7400 74LS00 DIL14 IC68 74123 74LS123 DIL16 IC69 7432 74LS32 DIL14 IC70 Not fitted D1 1N5401 1N5401 DDCMC D2 1N4148 1N4148 DO35 D3 1N4001 1N4001 DO41 D5 1N4148 1N4148 DO35 D6 1N4148 1N4148 DO35 D7 1N4148 1N4148 DO35 D8 1N4148 1N4148 DO35 D9 1N4148 1N4148 DO35 D10 1N4148 1N4148 DO35 D11 1N4148 1N4148 DO35 D12 1N4148 1N4148 DO35 XT1 HC18S 10MHz HC18U R1 RESA8 3K3 RESA8 R2 RESA8 2K2 RESA8 R3 RESA8 100K RESA8 R8 RESA8 560R RESA8 R9 RESA8 10K RESA8 R10 RESA8 10K RESA8 R11 RESA8 10K RESA8 R12 RESA8 1KO RESA8 R13 RESA8 680R RESA8 R14 RESA8 100K RESA8 R15 RESA8 100K RESA8 R16 RESA8 10K RESA8 R17 RESA8 1KO RESA8 R18 RESA8 3K9 RESA8 Onl CAPR4D4E 47U 16V CAPR4D4E C2 CAPR4D4E 47U 16V CAPR4D4E C3 CAPR4D4E 10uF16V CAPR4D4E Doc UM1341 Issue K Date 12 5 99 Page 20 20 Author PJM Parts list for LP1341 ISSUE 4 Part Type Outline Manufacturer C4 CAPR2W2 56pf CAPR2W2 CS CAPR2W2 3N3 CAPR2W2 C6 C36 inc 100nF CER CAPR2W2 C3 CAPR2W2 56pf CAPR2W2 C38 CAPR2W2 470pF CAPR2W2 C41 CAPR2W2 1n0 CAPR2W2 C42
11. CAPR2W2 2n2 CAPR2W2 RN1 RN8COM 1K SIL9 RN2 RN8COM 10K SIL9 RN3 RN8COM 10K SIL9 RN4 RN8COM 1K SIL9 RN5 RN8COM 470R SIL9 CO1 PL40 01 IDC40 ACB CO2 SK9D D9SK 9WCANBD FS1 FUSECMC 3A FUSECMC BT1 Not fitted JP1 34 JUMPER JP JP LD1 EDTOMM N ED5H RED LD2 EDT SMM RUN ED5H GREEN LD3 EDT5MM TRIG CODE 4 ED5H RED LD4 EDT5MM TRIG CODE 2 ED5H RED LD5 EDT5MM TRIG CODE 1 ED5H RED M1 MSP TRIGGER IN LMSP M2 MSP FINISHED OUT LMSP M3 MSP STOP VETO LMSP M4 MSP REQUEST LMSP M5 MSP GRANT IN LMSP M6 MSP GRANT OUT LMSP
12. D Flag Reset all Reset Trigger ET F 25 A 15 LAM Status and Mask bits Enable Triggered Flag and GO Flag xpires The Time out nally by a capacitor C5 whose standard value is 3n3 Apart from to get a good Q response from a module ther which is the failure of the List Processor to gain control of is hogging the bus or a wrong connection other way in which a f a Time out is to stop the LP1341 which resets its GO flag and sets he NO Q Status bit hed check that the finishing conditions are if you wish check that the right number of cycles of each if any To do this you must A 2 and then read auto increment the pointer his will 1 that you cannot do any w data out faster than it r because it will be sha Reset Main Logic Sequencer and Trigger Input Logic Z S2 does all Reset all Pointers to zero the above plus Power on Reset has the same effect as Z S2 The List Processor is now free to accept another Test Booked Command ist processor is running ected Note that the act of reading this data out concurrently wi by using the ites with the is being ill reduce the ing use of the his you can either perform another sequence with the List so that another computer can use it if it wishes The which does the following Doc UM1341 Issue K Date 12 5 99 Page 11 20 Author PJM IMPORTANT NOTE Stopping in Triggered Mode
13. Data to be used by the LP1341 when it executes a command involving F16 and not F8 Write Data Memory using Write Pointer F 16 A 1 Writes into Memory Write Write Data Pointer again to point at the start pointer auto increments a sequence of data words Write Read Data Pointer F 17 A 2 To point to the start of the area of data memory to be used to store data read from modules during valid instructions which had neither F16 nor F8 present AND which gave a TRU E Q Response Clear LAM Status Register All bits F 23 A 12 data F HEX to clear the GO bit and any other status bits set by the previous sequence Clear LAM Mask Register All bits F 23 A 13 data F Selective Set LAM Mask Register F 19 A 13 status conditions to generate an Interrupt via LAM Starting HEX again then using appropriate bits to allow End The List Processor is now ready to be started In the STANDARD mode we are discussing now this can be done in two ways either by sel bit bit 4 ctively setting the GO in the LAM Status Register F 19 A 12 or by Enabling Trigger F 26 A 0 and giving the module an active LOW TIL trigger pulse on TRIGGER 1 via the front panel 9 way Cannon Trigger Input socket Note the LP1341 to look at the instruction it is pointing at and instruction Compatible it will start executing commands as usual In t with exist
14. Doc UM1341 Issue K Date 12 5 99 Page 14 20 Author PJM If it is required that one and only one of the lists include writing data then this should be loaded into memory preferably at the top for obvious reasons and the Write Pointer left pointing to many times as it will be needed unl Pointer feature available from serial no 516 onwards The way that the bootstrap works is as follows it Remember to load the set of write data as less you use the new Jump and Restore Write a The Main Logic Sequencer MLS sees the GO bit true which comes from either the Dataway GO or the Trigger input logic b The Trigger Input Logic will have generated a 3 bit code which is presented to the MLS G If the 3 bit code is greater than one the MLS uses the code to skip through the bootstrap program to the jump instruction corresponding to the trigger d If the trigger code was zero or one then the instruction being pointed to is checked to see if it is a Jump if not execution starts there and then e List execution proceeds as normal finishing with a jump to zero and await trigger 6 The MAIN LOGIC SEQUENCER This is a PLS 105 formerly 82S105 Programmable Logic Sequencer which is clocked by the 10M signal the output of the 10 MHz oscillator This also clocks the CAMAC Cycle Generator The Main Logic Sequencer s inputs and outputs are as follows
15. New Jump Instruction Format The new Jump Instruction Format is as follows 16 15 14 13 12 11 10 9 1 1 JC2 JC1 JCO A11 Al Noh X JUMP DESTINATION ADDRESS JUMP CONDITION SPECIFIERS The Jump Condition Specifiers operate as follows JC2 JC1l JCO ACTION 0 0 0 Unconditional Jump 0 0 1 Jump if No Q response during last CAMAC cycle 0 T 0 Jump if data read greater than stored value 0 1 1 Jump if data read less than stored value 1 0 0 Jump unconditionally and await trigger 1 0 1 Jump if No Q and await trigger i 1 0 Jump if data read equal to stored value 1 1 Jump uncond and restore Write Data Pointer Th Stored value referred Doc UM1341 Issue K Date 12 5 99 Page 5 20 Author PJM to above means the data written into the LP 1341 s Comparator Register which can then be compared with actual Read Data obtained by the LP 1341 during the last dataway READ command A modification has been inco it performed The List Processor may now read its own Instruction Pointer rporated to allow the LP1341 to read its own Instruction Pointer so that blocks of read data from different triggers can be distinguished by incorporating a Read Instruction Pointer command as the first in each list The Q response to F 1 A 0 has been changed to Q 1 for this command so that the data read is retained d The whic of t used its LAM lin e The Co This register which he LP 1
16. d reading data from an input module in the crat 10 LP 7 1 16 In Branch 7 Crate 1 stn 16 with CCA2 20 MOD 8 Module to be read in Stn 8 100 F27 LP O Test Booked F 27 subaddress 0 110 IF NOTQ GOTO 1000 Not free error 120 F24 LP O Disable Trigger just in case 130 F17 LP O 0 Set Instruction Pointer to zero 140 LET X MOD 512 Generate NAF for N8 AO FO 150 FOR I 1 TO 100 100 cycles 160 F16 LP O X Write NAF F 16 sub 0 data X 170 NEXT I 180 F16 LP O 100000 Stop Instruction bit 16 set 190 F17 LP 0 0 Inst Pointer to zero again 200 F17 LP 1 0 Write Pointer to zero 210 F17 LP 2 0 Read Pointer to zero 220 F17 LP 3 0 Comp Reg 0 comparator not used 230 F23 LP 12 15 Reset all LAM Status bits 240 F23 LP 13 15 Reset all LAM Mask bits 250 PRINT LIST PROCESSOR READY TO GO HIT RETURN 260 WAIT 270 F19 LP 12 8 Set GO bit 280 F27 LP 1 Test GO Enabled 290 IF CAMQ GOTO 280 Still going Wait 300 Fl LP 12 X Fetch LAM Status 310 IF X 12 GOTO 330 Status correct Expect GO FIN 320 PRINT FINISHED STATUS WRONG EXP 12 GOT X 330 F1 LP 0O X Fetch Inst Pointer 340 IF X 100 GOTO 360 As expected 350 PRINT EXPECTED 100 INSTRUCTIONS GOT X 360 F1 LP 1 X Fetch Write Pointer 370 IF X 0 GOTO 390 Should be none 380 PRINT EXPECTED 0 WRITES GOT X 390 F1 LP 2 X Fetch Read Pointer 400 IF X 100 GOTO 420 Exp 100 Reads 410 PRINT EXPECTED 100 READS GOT X 420 F17 LP 2 0 Reset Read Pointer 430
17. e straightforward use of trigger 1 as we saw above the Instruction store must be loaded with the Bootstrap Jump Instructions and the lists themselves The Bootstrap looks like this Address Contents Function 0006H 11000XXXXXXXXXXX Jump to List 7 Start 0005H 11000XXXXXXXXXXX Jump to List 6 Start 0004H 11000XXXXXXXXXXX Jump to List 5 Start 0003H 11000XXXXXXXXXXX Jump to List 4 Start 0002H 11000XXXXXXXXXXX Jump to List 3 Start 0001H 11000XXXXXXXXXXX Jump to List 2 Start 0000H 11000xxxxxxxxxxx Jump to List 1 Start Where x is part of the 11 bit jump address and list 1 is triggered by Trigger 1 and so on H means HEXADECIMAL Starting from the Start Address of each list the Instructions are then loaded finishing with a Jump to Zero and await trigger which is 16 15 14 13 12 11 10 Notice that bit 14 is a 0 0 0 0 ee A Os BB AE 6 SB 2d lt 3 2 21 0 00 0 00 0 0 0 to denote re trigger After all the lists have been loaded th zero The Read Pointer shoul each list wil top 8 bits al ld also b Instruction Pointer should be res t to zero then read data coll LINTAS Bits 17 24 Loned above bu due to t remember that this read will the internal bus pull ups reset to lected by ll accumulate upwards tagged if needed by Reads of the LP1341 s own Instruction Pointer as menti give the
18. er Note also the LAM only one Sect 5 riggers ar All OUT Doc Issue Date Page Author PJM K JP24 25 26 OVERFLOW S If any of soon as t pointer r will stop so This th See also Sec ELECT these three links is fit he TOP 8 or 16 BITS of th aches the all ones sta setting NO X and FINISH refore represents OVE tion 7 b ted then as e corresponding te the LP1341 ED as it does REFLOW WARNING ul JP24 its of the Instruction Pointer he top 8 bi t overflow is on all 16 bits not just ts of the real counter selects t Note tha the 13 bi JP25 since both although Thus selects the Read Data Pointe Note that the data memory is now 128K or even 256K read and write data pointers are 24 bits only 17 or 18 bits have any real meaning overflow is on bits 9 24 JP26 selects the Write Data Pointer Standard Setting All OUT JP27 JP28 STOP VETO This determines the function of the Stop Veto input as follows JP27 STOP If the front panel input is taken low the List Processor will stop after the current instruction and set FINISHED and NO Q Status F H JP28 VETO If the input is low at the time that the LP1341 advances to the next instruction the relevant Data Memory Pointer will not be incremented data will be ignored Clearly this only applies if reads are being p
19. erformed and some external module is looking at data patterns and issuing VETO accordingly To b ffective the VETO input must be taken low no more than 500nS after the beginning of the LP1341 s CAMAC Cycle and should be held low until the end of that CAMAC cycle Standard Setting JP 27 IN Note that in order to satisfy a number of applications where the abs UM1341 12 5 99 6 20 of Q means No Data Ready this condition has been made an internal source of VI ignore data The effect of this will be to prevent th which will mean that data will simply b Ignore Mode either Reading or Writing Status g Selective Set LAM Mask nc ETO i e incrementing of pointers ignored when performing commands in Q Read LAM ist will If therefore your without expecting Q 1 for details of the required modification Doc UM1341 Issue K Date 12 5 99 Page 7 20 Author PJM include instructions involving reading or writing and you want the pointer s to increment please contact Hytec UR Master JP29 Self Trigger Select NOT USED Contact Hytec for details of use if desired JP 31 128K 256K Memory Select JP31 IN 256K Memory JP31 OUT 128K Memory 128K memory mapped twice over 256K area to allow proper overflow JP32 512K memory chip use only do not fit JP33 128K memory chip use only must be fitted JP34 512K memory chip
20. erminated Stop Instruc The bottom 3 bits 1 if you set the it to start End condition bits this should all be zero bit 4 does not happen if the LP is bits 5 to 8 will all be read as 1 and they should be ignored ng See also number of ways in whic as follows tion An instruc The LP1341 stops resets its Register and sets the Finished bit bit 3 Pointer will be pointing to will be pointing to the location ABOVE the Overflow When the top 16 bits of the Read the Instruction Pointer selected by one of ones state the LP1341 wi stop pointers will not be incremented fol therefore pointing to the either of the two Data Pointers Thi External Stop If JP 27 is IN and t end of the current instruction the LP1341 will stop reset its GO flag NO X Abort If t sampled at S1 time it will stop the IMPORTANT NOTE Page 11 an tion was encountered with bit 16 set and bit 15 internal GO flag not the GO bit in the Status in the Status Register The Inst the Stop Instruction and the Read and Write Pointers last one used or Write Pointer set Fi h execution of a list of instructions can be not set ruction or the top 8 bits of links 24 25 and 26 has reached the all reset its GO flag and se t Finished and NO X The lowing the last instruction The LP1341 stops last instruction executed and not i
21. ing LP1340 units Having been placed that Trigger 1 causes if it is NOT a jump his way it can be made in the GO condition by either of these means the LP1341 will start doing CAMAC cycles at high speed about 1 5 uSec each if unopposed until it reaches a Stop condit ion he command rocessor is computer t to GO by st isters o implies tha do not gene t is runni Execution is Test GO Trig Enb F 27 Running or Awaiting Trigger In to attempt to access the LP1341 s internal registers at this time Note hat because the List Processor runs so fast setting bit 4 ng it in progress ate Q anyway Doc UM1341 Issue K Date 12 5 99 Page 9 20 Author PJM A 1 can be used to t st whether the List d be disastrous for woul ither case it it is quite po some of th be to give NO X This is thought to be at best misleading commands to be so that the only way to signal their nonacceptance would ssible that if you tell in the Status Register then by the time you come back to will have finished it is in fact possible to access all the internal f the LP1341 and some users successfully do this although the data sheet t this is not so This is becaus excluded Reading the LP1341 s LAM Status Register whilst execution is under way will show 8 bits of data should be a Triggered 3 2 Stoppi There are a t
22. ng on certain Jump Address bits Hardware modifications have been included to avoid this C Jump and Restore Pointer One customer requested enhancement to the Jump conditions has been incorporated as a standard feature Users at Argonne wanted a Jump and Restore Write Pointer feature so that one set of constant output data could be used repeatedly for a set up task This has now been included in the standard set as Jump Condition Code 7 This is an unconditional Jump which restores the value of the write pointer to its last loaded value Existing users should find no difference in the behaviour of the new units and field upgrade of old units is possible contact Hytec for details P Marshall 27 August 1993 ENGINEERING NOTIC Gl August 1995 FURTHER IMPORTANT ENHANCEMENTS TO LP 1341 LIST PROCESSOR As the result of continuing improvement of Hytec s products another new artwork for the LP1341 has been produced Issue 4 The aims of this revision are as follows a To incorporate minor correcti which have no effect on the charact b To make two distinct changes customer requests for enhancements ons to the Issue 3 artwork eristics of the unit to the design in line with namely i More data memory the unit can now accept bigger memory chips so that it may have up to 1 megaword by 24 bits of data memory ii P
23. rogrammable self trigger rat user two internal trigger frequenci The old scheme gave the s selected by jumpers which were virtually useless These have been deleted and replaced by a divided crystal oscillator capabl e of outputting a variety of frequencies from 0 001 Hz to 100 kHz The LP 1341 is still produced by Hy the smaller memory chips giving 12 memory and without any self trigge A new unit called the LP 1342 is he new programmable self trigger s tec using this board with 8K or 256K words of data r facility now offered by Hytec using this board which has larger memories of 512 or 1024K words and cheme However the self he desired frequency value which annot use both functions just one t trigger feature makes use of the co t C This manual concerns itself ONLY wi 1341 mparator register to store neans that operationally you at a time th the board built as an LP CONTENTS 1 Introduction 2 Configuring Module Data Sheet 3 Detailed Operational Description 3 1 Starting FeZ Stopping 4 Operating Example 5 Seven Trigger Operation 6 Main Logic Sequencer 7 Handy Hints and Conditional Jumping 8 Physical and Electrical 9 Parts List Page 2 3 Doc UM1341 Issue K Date 12 5 99 Page 1 20 Author PJM Doc UM1341 Issue K Date 12 5 99 Page 4 20 Author PJM
24. ruction composed the Instructions properly with bits and bits 10 14 are Station Number Subaddress INST Fo A 32 N 512 b When using pointer ove physical pointers are alla bits to address the 256K wo lot rds The top 6 bits do nothing and the memory jus bit boundary but for overflow a unit with 256K words the top as address 000000 Overflow is so for these pointers this is HEX FFFFOO wider than of the data the top 6 b address is on the top 1 W top 6 bits and for the instruc 64K 255 If you wish to reach take that number away from the example to stop after 200 000 F 17 A 2 at HEX FFFFOO 30D4 LP 1341s will have JP31 removed so that their memory and bottom halves of the area tion ove over reads 0 200 000 i pointer rflow af flow value and s instal Pointer as well 16384 if Q ignore i H 6 bits o hich is at 256K 2 ter a cer tart at t 1 JP25 and start n HEX W overflow on top 8 bits tain number of cycles hich is H rflow to stop the List Processor remember that t hey need to be that is you only emory but there is a 24 bit poi wraps round if you count past ts are considered and MUST be EX O3FFFF and address 040000 is the read write data poi ignori it is H 55 words hat address so they will set thei above the 128K boundary in the last 256K page Register after stopping e
25. s is true of all stop co ted re on having incremen nditions from he he Stop Veto input is pulled low then at the nished and NO Q and he LP1341 does not get an X response during a CAMAC cycle set NO X and reset its GO flag Q Repea Igno inst t Fail or Ti bit 15 tion until e re bit ruc ne out ither it does get Q or period is set inter failing Time out can occur the Crate through t within 10 uSec H ne ct When the List Processor has Finis reading the LAM S hat the pointers ar cor t type took place effect o rect by he ACB someone tatus Register obviously reset the out It overall execution rate of the lis is possible to read out data wi Write Data Pointer but clea LP1341 and also that you must no coll then read out t the data sequentially wi cted i he data co nter to its ori as exp Read Poi Doc UM1341 Issue K Date 12 5 99 Page 10 20 Author PJM the 10 uSec timer If the LP1341 does not get Q to a Command and the Q is not set in the instruction then it will repeat that is on F 1 A 12 then llected ginal va ue F 17 th F 0 A 2 T hilst the hat means t read the rly t L processo CAMAC Dataway with the read out controller Having accomplished all t or un book i command to do this is R Processor ES Reset BOOKE
26. specially if le on the data sheet to Check that you have 1 5 Function Code bits 6 9 are and bit 15 is Q Ignore Thus he need 18 nter the 18 1 So on the same nters ng the EX FFOO just For the Read Data Pointer EX FCF1CO Users of 128K is duplicated over the top r start address to somewhere Doc UM1341 Issue K Date 12 5 99 Page 16 20 Author PJM On the subject of pointers and addressing remember that the instruction store is 8K words but jump addresses are still restricted to the bottom 2K of that store because there are only 11 address bits in the jump instruction Thus if you wish to return to the start of a list of commands this must be below the 2K boundary On the front panel there are 5 LEDs one for N stretched to 10mSec one for RUN or GO which comes on when the LP1341 is executing a list and three showing which trigger is active H These Trigger Code LEDs come on when a non zero trigger is received and will go off when the list is completed f a trigger is Early units of 8 Physical and The module is a received when triggers are not enabled it will simply be ignored this type did not do this Electrical single width CAMAC unit with rear mounted 40 way ACB header front panel 9 way Cannon socket Trigger Input connector six LEMO sockets and five LEDs Doc UM1341 Issue K Date
27. use only do not fit 3 Detailed Operational Description The List Processor LP1341 is an ACB Auxiliary Controller in accordance with E 6500 As such it must reside in a CAMAC Crate connected to an ACB Controller in stations 24 and 25 by a rear panel 40 way ACB cable and a set of Request Grant cables at the front T the highest priority controller and on the next lowest priority device a orde of desired operating speed and impor capable of accepting and responding he user must co then Grant Out nd so on It is r of priority of the controllers bearing in mi tance of controlling actio to ACL but can Having configured the LP1341 assembled the modules the ACB etc the user can now switc commands and Write Data if any Test Booked F 27 A 0 This tells you if the List Processo nnect Request to on that co ntroller to G Grant In on rant In left to the us nd their relativ r to decide th needs in terms ns T he LP1341 is not generate it itself in the crate and connected up h on and progral as follows n the LP1341 with its list s of r is available or not If you get Q OK to proceed The List Processor is now booked to you and will give NOT Q to all subsequent Tests by o unless it has been BOOKED ther potential users a F ARE GOING TO CONSID FROM NOW ON WI ER F TH PROGRAMMING OF The LP 1341
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