Microcontrollers XC800 Family Power Saving Features
Contents
1. Figure 4 Graphical representation of the X and Y series in Table 7 Application Note 12 V1 1 2007 07 Cinfir AP08056 Infi neon Power Saving Features Power Down of the Entire System Power Down Mode 4 Power Down of the Entire System Power Down Mode Power down of the entire system can be achieved by setting the device in power down mode In this mode all functions of the microcontroller are stopped and only the contents of the FLASH on chip RAM XRAM and the SFRs are maintained The port pins hold the logical state they had when the power down mode was activated For the digital ports the user should ensure that the ports are not left floating Floating input port pins should enable pull down or set as output Output pins that are pulled up should be set to high For the analog Port 2 the user should disable the input driver of the port by setting the port direction to output In power down mode the clock is turned off Hence it cannot be awakened by an interrupt or by the WDT It is awakened only when it receives an external wake up signal or reset signal 4 1 Entering Power Down Mode Software requests power down mode by setting the bit PMCONO PD protected bit to 1 Two NOP instructions must be inserted after the bit PMCONO PD is set to 1 The device will not enter power down mode immediately after executing the instruction to set PMCONO PD and therefore the two NOPs is to ensure the first instruction after two NOP instructi2. 0x01 Open SCU page 1 to access PMCONO and PASSWD PASSWD 0x98 Open access to writing of all protected bits PMCONO 0x17 Enable power down with wake up source RXD or EXINTO selected and select wake up with reset nop 2 NOPs necessary for proper execution of _nop_ code upon wakeup Function is defined in ffAMerinS ih Note Some IRAM locations will be corrupted after a reset The stack and the constant variable location must avoid these locations Please refer to the respective product s Errata Sheet for the detailed locations Note START_XC A517 will clear IRAM locations ranging from 0 to the number defined in the symbol IDATALEN It is therefore necessary to redefine the data assigned to this symbol to avoid destroying the stack and the constant variable data 4 2 Exiting Power Down Mode Power down mode can be exited in two ways 1 Hardware reset The device is put into the hardware reset state 2 The EXINTO pin the RXD pin or either of these two pins detects a falling edge The wake up source s must be selected prior to entering power down mode When a wake up source is selected the device will wake up from power down mode upon detecting a falling edge trigger at that source In power down mode EXINTO pin RXD pin must be held at high level Power down mode is exited when EXINTO pin RXD pin goes low for at least 100 ns The device can wake up with or without reset depending on the setting of the PMC
3. Frequency MHz X Idle Y X Y Application Note 25 V1 1 2007 07 AP08056 Power Saving Features Cinfineon A Timer 2 Example Table 17 Current consumed by XC866 4FR device when timer 2 is active fsys 79 8 MHz re Current mA 1 Negative value indicates that slow down idle mode current gt slow down mode current Table 18 Current consumed by XC888 device when timer 2 is active fsys 96 5 MHz ee Current mA Peripheral CLKREL Difference Frequency MHz X Idle Y X Y 1 Negative value indicates that slow down idle mode current gt slow down mode current It can be noticed that by reducing the clock frequency of the CPU and peripheral the devices will require less current to run 8 3 Prescaler Mode Current The program is now programmed to run in prescaler mode with slow down mode and slow down idle mode The timer reload value for every measurement was changed such that the timer will overflow in every 20 ms Application Note 26 V1 1 2007 07 le AP08056 C Infineon Power Saving Features A Timer 2 Example Table 19 Current consumed by XC866 4FR device when timer 2 is active fsys 5 0 MHz Current mA Peripheral CLKREL Slow Down Slow Down Difference Frequency KHz X Idle Y X Y 1663 3 0000 3 40 0 18 831 7 0001 3 13 0 04 415 8 0010 2 98 0 03 104 0 0100 2 87 0 09 Table 20 Current consumed by XC888 device when timer 2 is active fsys 4 8 MHz Current mA ee Peripheral Difference Fre
4. le AP08056 C Infineon Power Saving Features Reducing Clock Speed Slow Down Mode Table 4 Current comparison between slow down mode and slow down idle mode of a XC866 1FR device fsys 80 4 MHz Current mA O Peripheral Difference 2 Frequency MHz X Idle Y X Y 0 052 4 56 0 26 0 026 4 55 0 27 0 013 4 54 0 26 1 Peripheral frequency fgys CLKREL Fixed divider of 3 refer to user s manual on Clock System 2 Negative value indicates that slow down idle mode current gt slow down mode current a D 5 S 3 4 Td 0 4 0 2 0 1 0 1 Peripheral Clock Frequency MHz XC866 1FR Figure 1 Graphical representation of the X and Y series in Table 4 Application Note 9 V1 1 2007 07 le AP08056 C Infineon Power Saving Features Reducing Clock Speed Slow Down Mode Table 5 Current comparison between slow down mode and slow down idle mode of a XC866 4FR device fsys 79 8 MHz Current mA SS Peripheral Difference 2 Frequency MHz X Idle Y X Y 0 052 5 48 0 08 0 026 5 47 0 08 0 013 5 47 0 09 1 Peripheral frequency fsys CLKREL Fixed divider of 3 refer to user s manual on Clock System 2 Negative value indicates that slow down idle mode current gt slow down mode current lt E 5 O 1 7 0 8 0 4 0 2 0 1 0 1 Peripheral Clock Frequency MHz XC866 4FR Figur
5. CAN and 77 COS ULC SCU PAGE 0x03 Open SCU page 3 to access PMCON2 PMCON2 0x03 Disable T21 and UARTI For XC866 only ADC CCU SSC and T2 can be disabled by setting the corresponding bits in PMCON 1 Table 9 Current consumption by the peripherals of a XC866 1FR device at different peripheral clock PCLK frequencies Current mA Peripheral Frequency 6 0 84 0 013 MHz CLKREL 0000 0010 0101 1011 CCU 1 45 0 02 0 SSC 0 51 0 01 All 2 95 0 03 1 lt 10 pA T Application Note 16 V1 1 2007 07 Cinfir AP08056 Infi neon Power Saving Features Stopping the Clocks of Individual System Components Table 10 Current consumption by the peripherals of a XC866 4FR device at different peripheral clock PCLK frequencies Current mA Peripheral Frequency 38 e7 f os ono 0 013 MHz 1 lt 10 uA Table 11 Current consumption by the peripherals of a XC888 device at different peripheral clock PCLK frequencies Current mA Peripheral Frequency m g a 0 75 0 13 MHz 1 lt 10 pA Application Note 17 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency 6 Operating on a Lower Clock Frequency The normal system clock runs in PLL Mode The system frequency fsys is defined as fsys fosc The N factor is selected by the bitfield PLL_CON NDIV The P factor is fixed to 1 The K factor is fixed at 2 for XC866 It can be selected by the bit CMCON KDIV protected bit for
6. XC886 888 The internal oscillator frequency fosc for XC866 is 10 MHz The internal oscillator frequency for XC886 888 is 9 6 MHZ This system frequency is further divided to derive the CPU clock peripheral clock and flash clock By selecting a different clock mode the system frequency will be changed and thus affecting all the other clocks of the entire system The PLL Base Mode and the Prescaler Mode are two of the other clock modes that can be used to derive the system frequency It is important to take note that PLL Base mode and Prescaler are not the normal recommended mode of operations and have their limitations However these two modes may offer potential power saving capabilities for applications where the limitations are not critical More details of these two clock modes and its limitations will be discussed in the following sections Application Note 18 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency 6 1 Device Clock in PLL Base Mode In the PLL base mode the oscillator is disconnected from the PLL and the system frequency is derived from the VCO base free running frequency clock divided by the K factor f 1 sys g f VCObase The ranges of the VCO base frequency is shown in Table 12 Table 12 VCO base fycobase and system frequency fsys ranges Device VCOSEL fycopase Range MHZ fsys Range fsys Range whenK 1 when K 2 MHz The VCO base freq
7. express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered oae AP08056 Infineon Power Saving Features XC800 Family Revision History V1 1 2007 07 Previous Version s V1 0 Section Subjects major changes since last revision Section 3 Included Section 3 1 to highlight the lower limit of slow down frequency that guarantees flash programming and erasing operations in slow down mode Section 4 Error in the WKSEL value in Table 8 It has been swapped Section 6 Section 6 1 and Section 6 2 updated with the main limitations of PLL Base mode and Prescaler mode Example code in Section 6 2 1 to restore PLL mode from prescaler mode included an instruction to open SCU page 1 We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com gt lt Application Note V1 1 2007 0
8. restore the clock to PLL mode the oscillator has to be re locked to the PLL This require quite a number of instruction cycles to carry out the task see example in Section 6 1 1 and the recovery time will depend on the frequency of the CPU operating in PLL Base mode The slow recovery time may render it unsuitable for applications where events require a fast response time 4 Flash Programming and Erasing Operations are not Supported The flash clocks will not meet the required frequency to guarantee flash programming and erasing operations when the device operates in PLL Base mode As such user has to restore the clock to PLL mode before flash programming and erasing operations can be carried out Table 13 are some results showing the current consumption by a XC866 1FR device a XC866 4FR device and a XC886 device operating in PLL base mode Table 13 Current consumption in PLL base mode XC866 1FR XC866 4FR XC886 We GSE EEEN EN 1 fvcotase MHZ 22 5 36 2 212 fsys MHZ with K 2 11 24 19 47 11 00 18 85 18 11 10 62 SYS PLL base mode 2 14 4 25 3 07 4 15 5 12 3 37 current mA down mode enabled PLL base mode 1 23 mA current with slow 1 CLKREL 1011 for XC886 and CLKREL 1111 for XC886 6 1 1 Software Example for PLL Base Mode In order to disconnect the oscillator the VCO bypass mode must be selected first by setting the bit PLL_ CON VCOBYP This is to prevent the system from detecting a PLL Application Note 2
9. the maximum bandwidth is not required User must also consider the response time of the system to interrupt events When the system frequency is reduced the interrupt latency will increase accordingly thus making it unsuitable for applications that require quick response time Application Note 29 V1 1 2007 07
10. 0 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency loss of lock condition which sets the NMICON NMIPLL bit The internal oscillator can be powered down in PLL base mode to save power by setting bit OSC_CON OSCPD The following example shows how the PLL base mode is selected SCU PAGE 0x01 Open SCU page 1 PLL CON 0x08 Select VCO Bypass Mode This step is to prevent PLL loss of lock bit from being set PLL CON 0x04 Disconnect the oscillator OSC CON 0x10 Power down the oscillator device is running in PLL Base Mode The next example will show how to restore the clock in PLL mode from PLL base mode fl PLu CONsVCOBYP 1 SCU PAGE 0x01 Open SCU page 1 OSC CON amp OxEF Power up the oscillator OSC CON 0x02 Reset and restart oscillator detection logic while OSC CON amp 0x01 Wait for oscillator to run PLL CON amp OxFB Connect oscillator to PLL PLE CON Ox027 7ReStart PLL Lock detection while PLL_ CON amp 0x01 Wait for PLL lock bit to set PLL CON amp OxF7 Deselect VCO bypass mode device is running in PLL Mode 6 2 Device Clock in Prescaler Mode In this mode the system clock is derived from the oscillator clock divided by the P and K factor l fsys p K fosc The oscillator frequency is close to its designated frequency 10 MHz for XC866 and 9 6 MHz for XC886 888 after it has been trimmed by the f
11. 7 le AP08056 C Infineon Power Saving Features Overview 1 Overview This application note describes the various power saving features in the XC800 architecture It is intended to provide users of the XC866 and XC886 888 with information and guidelines on how to apply these features to achieve low power consumption on applications via a combination of techniques which include e Stopping the CPU clock Idle Mode e Reducing clock speed slow down Mode e Power down of the entire system Power Down Mode e Stopping the clocks of individual system components Peripheral Management e Operating on a lower clock frequency In this document users can find measurements of the current consumed by the XC866 and XC886 888 devices operating in different power modes There is also a breakdown of the current consumed by the peripherals at different clock speeds With these measurements the users will have a better understanding of how the different power saving features can affect the power consumption of the devices and therefore apply the power saving features effectively However these results were meant to serve as a reference only as the measurements will vary from device to device The power consumption can be affected by various factors such as the type of instructions used in the code program flow peripheral settings measuring equipment power supply temperature and frequency of the oscillator etc The measurements in this document were t
12. 9 mA 2 89 mA current 1 fy 1 P K f where P 1 and K 2 sys Sc 2 CLKREL 1011 for XC866 and CLKREL 1111 for XC886 888 The current consumption is much lower than the device operating in slow down mode in Section 3 3 The combination of slow down and idle mode may not be as efficient as slow down alone at low frequencies For example for the XC888 device it will draw 3 35 mA of current for the combined slow down and idle mode compared to 2 89 mA for slow down mode alone when bitfield CMCON CLKREL 1111p 6 2 1 Software Example for Prescaler Mode The system clock can operate in prescaler mode by setting the bit PLL_CON VCOBYP The following example shows how the prescaler mode is selected SCU PAGE 0x01 Open SCU page 1 PLL CON 0x08 Select VCO Bypass Mode Application Note 22 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency PLL mode can be restored from prescaler mode simply by clearing the bit PLL_CON VCOBYP SCU PAGE 0x01 Open SCU page 1 PLL CON amp OxF7 Deselect VCO bypass mode Application Note 23 V1 1 2007 07 ie AP08056 C Infineon Power Saving Features Reset Current T Reset Current This section describes the current consumption by the devices in reset state i e when the reset pin is held low All the port pins are left floating except the reset pin which is grounded Table 15 Current drawn by devices in reset state Devices Curren
13. Application Note V1 1 Jul 2007 APO08056 XC800 Family Power Saving Features Achieving Low Power Requirements on Applications Microcontrollers _ Cafineon Never stop thinking Edition 2007 07 Published by Infineon Technologies AG 81726 Munchen Germany Infineon Technologies AG 2007 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the
14. Idle Mode Idle mode can be entered by setting the bit PCON IDLE PCON 0x01 Table 1 look at the savings in current consumption between active mode and idle mode of the different devices Table 1 Active and Idle mode current measurements Current mA Products CPUClock Active Savings MHz XC866 1FR 15 50 11 87 3 63 XC866 4FR 17 84 14 16 3 72 XC886 23 46 20 02 3 44 XC888 23 22 19 82 3 40 1 Program waits in a continuos loop i e while 1 Consider a program that is constantly waiting to service a Timer interrupt The program can a wait in an endless loop for the interrupt event to occur or b wait for the interrupt event to occur while the CPU is disabled idle mode and then enable the CPU to service the interrupt routine when an interrupt occurs Method b will consume less power as indicated in Table 1 and Table 16 Application Note 5 V1 1 2007 07 Cinfir AP08056 Infineon Power Saving Features Stopping the CPU Clock Idle Mode The device in idle mode can be exited to active mode on the occurrence of any of the two conditions 1 Hardware reset The device is put into the hardware reset state 2 An interrupt has occurred from an enabled interrupt source The device will service the interrupt routine and continue its operation from the next instruction after the instruction that sets the PCON IDLE bit to 1 2 2 Ineffective Idle Mode Idle mode may not always be useful in reducing power consumpt
15. ONO WKSEL bit If the WKSEL bit was set to 1 prior to entering power down mode the system will execute a reset sequence similar to the power on reset sequence Therefore all port pins and SFRs are put into their reset state and will remain in this state until they are affected by program execution The only exception is that hardware will set the wake up indication bit PMCONO WKRS to indicate that the device is woken up from power down reset Application Note 14 V1 1 2007 07 Cinfir AP08056 Infi neon Power Saving Features Power Down of the Entire System Power Down Mode If bit WKSEL was cleared to 0 before entering power down mode a fast wake up sequence is used The port pins continue to hold their state which was valid during power down mode until they are affected by program execution The example below shows how the previous example can restore the port 3 status after exiting the power down mode with reset li cue alter ANGI alizacion SCU PAGE 0x01 Open SCU page 1 to access PMCONO if PMCONO amp 0x20 Check PMCONO WKRS for wakeup indication SP STACKSP Restore stack pointer SP 0x42 PORT PAGE 0x00 Open port page 0 to access Px DATA Jpop Ps DATA Restore P3 from Stack IJ esa CONTINUG 4 Table 8 illustrates the timing for a device to wake up from power down mode to active mode for both wake up with without reset Table 8 Wakeup timing from power down mode XC886 888 Reset Sequence WKSEL 1 EVR is
16. U is always active Application Note 6 V1 1 2007 07 Cinfir AP08056 nrineon Power Saving Features Reducing Clock Speed Slow Down Mode 3 Reducing Clock Speed Slow Down Mode The slow down mode is used to reduce the power consumption by dividing the CPU clock and the peripherals clock with a programmable factor The slow down mode is activated by setting the bit PMCONO SD after the programmable factor in the bitfield CMCON CLKREL has been selected The programmable factors may differ for different XC800 products The slow down mode is terminated by clearing bit PMCONO SD which is a protected bit It cannot be written directly when the protection scheme is activated An example below shows a software example of a XC866 device entering slow down mode with system clock reduced by a factor of 32 SYSCONO amp OxFE Access standard SFR region RMAP 0 SCU PAGE 0x01 Open SCU page 1 CMCON amp OxFO Clear CLKREL CMCON 0x06 Select clock divider fsys 32 PASSWD 0x98 Open access to writing of all protected bits PMCONO 0x08 Set SD to enter slow down mode PASSWD 0xA8 Close access to writing of all protected bits Similarly to exit the slow down mode SYSCONO amp OxFE Access standard SFR region RMAP 0 SCU PAGE 0x01 Open SCU page 1 PASSWD 0x98 Open access to writing of all protected bits PMCONO amp OxF7 Clear SD to exit slow down mode PASSWD 0xA8 Close access to writing of al
17. actory The main limitations of the Prescaler Mode are as follow 1 No Oscillator Fail Safe Mechanism In Prescaler Mode the clock is derived directly from the oscillator clock If the oscillator clock breaks down during the operation the device will stall It will not be able to operate on the free running frequency as the PLL is bypassed Application Note 21 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency 2 Long Recovery Time The recovery time will depend on the CPU speed Although it requires less instruction cycles to recover to PLL mode as compared to PLL Base mode the significance still lies in the speed of the CPU operating in prescaler mode 3 Flash Programming and Erasing Operations are not Supported The flash clocks will not meet the required frequency to guarantee flash programming and erasing operations when the device operates in Prescaler mode As such user has to restore the clock to PLL mode before Flash programming and Erasing operations can be carried out Below are some results showing the current consumption by the four devices operating in prescaler mode Table 14 Current consumption in prescaler mode XC866 1FR XC866 4 FR XC886 XC888 Internal oscillator 10 5 MHz 10 0 MHz 9 8 MHz 9 MHz frequency fosc system frequency 5 3 MHz 5 0 MHz 4 9 MHz 4 8 MHz fys Active mode current 3 13 mA 3 53 MA 3 85 MA 3 84 mA Slow down mode 2 28 MA 2 0 mA 2 8
18. aken from four different devices XC866 1FR XC866 4FR XC886 and XC888 The XC866 4FR results can be used as a reference for XC866 2FR Unless otherwise stated all the results were measured under the following conditions Power supply of 5 V Room temperature of approximately 25 C Port 2 of the devices were set to output to disable the analog driver All the other port pins were configured with internal pull down enabled Peripherals were not programmed to perform any operations ON ee 1 a Application Note 4 V1 1 2007 07 Cinfir AP08056 nrineon Power Saving Features Stopping the CPU Clock Idle Mode 2 Stopping the CPU Clock Idle Mode The microcontroller can reduce power consumption by stopping the CPU s clock This can be achieved by putting the device in idle mode In this mode the oscillator continues to run but the CPU is stopped with its clock disabled Peripherals whose input clocks are not disabled are still functional Note If the watchdog timer WDT is still active when the device goes into idle mode it will generate an internal reset when an overflow occurs It is therefore necessary to disable the WDT before entering idle mode The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The port pins hold the logical state they had at the time the idle mode was activated 2 1 Entering and Exiting
19. e 2 Graphical representation of the X and Y series in Table 5 Application Note 10 V1 1 2007 07 le AP08056 C Infineon Power Saving Features Reducing Clock Speed Slow Down Mode Table 6 Current comparison between slow down mode and slow down idle aT of a XC886 device fsys 97 5 MHz Current mA Peripheral Difference Frequency MHz x idle Y X Y 1 Peripheral frequency fgyo CLKREL Fixed divider of 2 refer to user s manual on Clock System x E eZ O 6 1 3 0 1 5 0 8 0 4 Peripheral Clock Frequency MHz XC886 Figure 3 Graphical representation of the X and Y series in Table 6 Application Note 11 V1 1 2007 07 le AP08056 C Infineon Power Saving Features Reducing Clock Speed Slow Down Mode Table 7 Current comparison between slow down mode and slow down idle mode of a XC888 device fsys 96 5 MHz Current mA Peripheral CLKREL Slow Down Difference Frequency MHz X Idle Y X Y 24 1 0000 19 82 3 40 12 1 0010 12 91 1 87 6 0 0100 9 36 0 97 3 0 0110 7 58 0 54 1 5 1000p 6 68 0 33 0 75 1010 6 24 0 21 0 38 1100p 6 01 0 16 0 19 1110p 5 90 0 13 0 13 1111 5 86 0 12 1 Peripheral frequency fgyo CLKREL Fixed divider of 2 refer to user s manual on Clock System NO O1 NO oO x E c O O1 24 1 12 1 6 0 3 0 1 5 0 8 0 4 Peripheral Clock Frequency MHz XC888
20. ion If interrupt events keep occurring the device will not be able to stay in idle mode and therefore is unable to reduce power consumption In the below example the peripherals of the devices were configured to operate as follows e Timers 0 1 2 21 in autoreload mode to overflow after OXxFFFF counts e ADC to perform 10 bit parallel conversion in autoscan mode e CCU to generate PWM output upon every period match e UARTO and UART 1 to transmit data at 19 2 kBaud upon each UART interrupt e SSC to transmit at 3 MBaud upon each SSC interrupt e CORDIC to start computation in circular rotation mode upon each CORDIC interrupt e MDU to perform unsigned multiplication upon each MDU interrupt e MCAN to start 8 bytes transmission in loopback mode upon each MCAN interrupt Note UART1 CORDIC MDU and MCAN were configured for XC886 888 only The current consumption of the devices is as follow Table 2 Current consumed by devices with peripheral activities Current mA Product CPU Clock Active MHz XC866 1FR 15 89 0 01 XC866 4FR 18 53 0 01 XC886 25 07 0 06 XC888 24 89 0 07 1 Negative value indicates that Idle mode current gt Active mode current Savings Looking at the amount of actives the devices will be too busy serving the interrupt routines that they may never be able to stay in idle mode i e turn off the CPU It can be observed from Table 2 that idle mode has no effect on the current consumption since the CP
21. l on the CLKOUT pin e In prescaler mode the system frequency is operating at half or equivalent of the oscillator frequency depending on the K factor e PLL Base mode and Prescaler may offer potential power saving capabilities for applications but users must be aware of their limitations e Unused peripheral can be disabled by gating off it s clock input to save power Application Note 28 V1 1 2007 07 Cinfir AP08056 Infineon Power Saving Features Power Saving Checklist 10 Power Saving Checklist e Disable the unused analog pins Port 2 by setting them as output pins e Input port pins should not be left floating Floating port pins should enable pull down or set as output port Output pins that are pulled up should be set to high or have the pull up disabled e The analog part of the ADC module can be disabled by resetting the bit GLOBCTR ANON This feature causes the generation of fapc to be stopped and allows a reduction in power consumption when no conversion is needed e When the on chip oscillator is used XTAL should be powered down by setting bit OSC_CON XPD this bit is set by default When the external oscillator is used the on chip oscillator should be powered down by setting bit OSC_CON OSCPD e Disable peripherals that are not used e Use idle mode instead of polling loops see Section 3 3 e Reduce the operating frequency of the system CPU or peripherals via the selection of power saving modes and clock modes when
22. l protected bits 3 1 Flash Programming and Erasing in Slow Down Mode In slow down mode flash programming and erasing operations are guaranteed only if the Clock Divider CLKREL value does not exceed the slow down factor listed in Table 3 If application runs at a lower frequency user should exit the slow down mode before performing any flash programming or erasing operations Flash reading can be performed at any frequency even below the described limit Table 3 Maximum Clock Divider Value to Guarantee Flash Programming or Erasing Operations Product System CLKREL CPU Clock Frequency in Frequency Slow Down Mode XC866 80 MHz 0100 1 7 MHz XC886 888 96 MHz 1000 1 5 MHz Application Note T V1 1 2007 07 Cinfir AP08056 Infi neon Power Saving Features Reducing Clock Speed Slow Down Mode 1 System frequency of 80 MHz divided by the slow down factor of 16 and then a fixed divider of 3 2 System frequency of 96 MHz divided by the slow down factor of 32 and then a fixed divider of 2 3 2 Combining slow down Mode with Idle Mode The slow down mode can be combined with the idle mode slow down idle mode This can be done by performing the following sequence 1 Select the slow down frequency in the bitfield CMCON CLKREL 2 Enter the slow down mode by setting the bit PMCONO SD 3 Activate idle mode by setting the PCON IDLE mode The slow down idle mode can be terminated by first exiting from idle mode and then followed by c
23. learing the bit PMCONO SD It will also be terminated by a hardware reset 3 3 Slow Down Mode vs Slow Down lIdle Mode Current Measurements This section illustrates the current measurements taken from XC866 1FR XC866 4FR XC886 and XC888 and shows the effect of the slow down mode and slow down idle mode The measurements are tabulated in Table 4 Table 5 Table 6 and Table 7 respectively From the tables it can be observed that the amount of current that can be saved in slow down mode reduces with the peripheral frequency This can be seen in the graphical representations of each table The peripherals require less power to operate when the peripheral clock is reduced in slow down mode At low frequencies the current drawn by the peripherals become relatively constant and therefore less current can be saved when the peripheral clock speed is further reduced In any case the devices draw the least current at the lowest possible frequency The slow down idle mode does not necessary draw the least current at the lowest possible frequency This can be observed in Table 4 Table 5 Table 17 XC866 and Table 18 XC888 The effectiveness of the slow down idle mode will depend on factors such as peripheral activities and the operating frequency It is therefore necessary to perform measurements manually to determine whether slow down idle mode is more effective than slow down mode in reducing current consumption Application Note 8 V1 1 2007 07
24. ons is executed correctly after wake up from power down mode If the external wake up from power down is used software must select the EXINTO pin the RXD pin or either of these two pins as the wake up source by selecting the WS bit of the PMCONO register Exit from power down mode can be achieved when a falling edge trigger is detected at the selected source s Bit MODPISEL URRIS is used to select one of the two RXD inputs and bit MODPISEL EXINTOIS is used to select one of the two EXINTO inputs The wake up with reset or without reset is selected by bit PMCONO WKSEL The wake up source and wake up type must be selected before the system enters the power down mode In order for the program to resume its operation from where it was stopped after the reset it is necessary to save the contents of the relevant registers to the stack including the current stack pointer The example below shows how the power down mode can be entered correctly with the port status stored to stack SP was initialized as 0x41 PORT PAGE 0x00 Open port page 0 to access Px DATA push P3 DATA Save port 3 current SP 0x42 I push Tunction 15 defined in antrins A Application Note 13 V1 1 2007 07 le AP08056 C Infineon Power Saving Features Power Down of the Entire System Power Down Mode STACKSP SP Save current stack pointer at an absolute memory location SoG unsigned char idata STACKSP at Oxe0 iram location 0xe0 0x42 SCU PAGE
25. quency KHz X Idle Y X Y The current consumed by the devices were even lower than those measured in Table 17 and Table 18 This is because the system frequency is much lower in prescaler mode than in PLL mode Application Note 2 V1 1 2007 07 le AP08056 C Infineon Power Saving Features Summary 9 Summary e Idle mode slow down mode and power down mode are the three power saving modes offered in the XC800 product family e A combination of idle and slow down mode can help to reduce power consumption further but it is not a certainty It will depend on factors such as the peripheral activities and the operating frequency e One of main factors that affects the power consumption of a device is the system frequency Reducing the system frequency will reduce the power consumption of the device e Slow down mode can be used to reduce the system frequency that is supplied to the CPU and the peripherals thus reducing the power consumption of the devices when maximum bandwidth is not required Users need to take note of the lower limit of the slow down frequency that guarantees the flash programming and erasing operations e In PLL base mode the system frequency can range between 5 MHz and 80 MHz depending on the setting of CMCON VCOSEL and the K factor At the lower range the system frequency is very much reduced thus lowering the power consumption of the device The system frequency can be determined by outputting the system clock signa
26. stable 150 us Typical PLL is locked 200 us Maximum Flash ready to read state BROM execution 215 us 250 us Typical Typical Total wake up time 350 us 725 Us 350 us 760 us 1 Timing is based on the system frequency of the devices XC866 operates at 80 MHz while XC886 888 operates at 96 MHz In power down mode the typical amount of current drawn by the devices will be approximately 1 uA at 25 C Application Note 15 V1 1 2007 07 infir AP08056 Infi neon Power Saving Features Stopping the Clocks of Individual System Components 5 Stopping the Clocks of Individual System Components Peripheral Management Peripherals which are not required for a particular functionality can be disabled by programming the assigned register bits in PMCON1 and PMCON2 which would gate off clock inputs This further reduces overall power consumption of the device Table 9 Table 10 and Table 11 shows the amount of current that can be saved when each all of the peripheral module s are disabled in a XC866 1FR XC866 4FR and a XC886 device at different peripheral clock frequency fpc It can be observed that when the peripheral clock is reduced the power consumed by the peripherals will also reduce which means that less current can be saved when the peripheral is disabled Software example to disable all peripherals on a XC886 888 device SCU PAGE 0x01 Open SCU page 1 to access PMCON1 PMCON1 0x7F Disable ADC CCU SSC T2 MDU
27. t uA XC866 1FR 750 to 900 XC866 4FR 850 to 1000 XC886 1050 1150 XC888 1200 1350 Application Note 24 V1 1 2007 07 le AP08056 C Infineon Power Saving Features A Timer 2 Example 8 A Timer 2 Example In this section the XC866 4FR device and the XC888 device were configured to start timer 2 in auto reload mode which generates an overflow in every 20 ms The overflow will trigger an interrupt service routine that will toggle port 3 0 The current drawn by the devices in active idle slow down slow down idle and prescaler mode were measured 8 1 Active and Idle Mode Current The current drawn by the devices in active mode i e device wait in an endless loop for the interrupt event and idle is shown in the table below It can be observed that the savings Difference that can be achieved by putting the device in idle mode is comparable to Table 1 Table 16 Current consumed by devices when timer 2 is active Product CPU Clock Active mA Idle mA Difference MHz mA XC866 4FR 18 04 14 23 3 64 XC888 24 00 20 01 3 59 8 2 Slow Down and Slow Down Idle Current The program is now programmed to run in slow down mode and slow down idle mode For every different slow down factor the timer reload value was changed accordingly such that the timer will overflow in every 20 ms Table 17 Current consumed by XC866 4FR device when timer 2 is active fsys 79 8 MHz ee Current mA Peripheral CLKREL Difference
28. uency of different devices will range between 10 MHz to 80 MHz depending on the VCOSEL setting The main limitations of the PLL Base Mode are as follow 1 PLL Base Frequency may vary between devices Users will need to manually check the system frequency of each device by outputting the device s system clock at the CLKOUT pin The code example to output the system clock is as follows SCU PAGE 0x01 open SCU page 1 to access COCON COCON 0x37 select clock output frequency 10 PORT PAGE 0x02 open port page 2 to access Px ALTSELx PO ALTSELO 0x01 select clock out function for P0 0 PO ALTSEL1 0x00 PORT PAGE 0x00 open port page 0 to access Px DIR PO DIR 0x01 set P0 0 as output port At the output of PO 0 the clock output frequency is half of the frequency that is chosen by the bitfield COCON COREL In the above example the system clock output at P0 0 has been divided by a factor of 10 based on the setting of the bitfield COCON COREL The system frequency can hence be obtained by multiplying the measured frequency by a factor of 20 Application Note 19 V1 1 2007 07 infir AP08056 Infineon Power Saving Features Operating on a Lower Clock Frequency 2 VCO Base Frequency Deviation The VCO base frequency that was determined could vary approximately up to 10 depending on the stability of the power supply to the PLL i e power supply from EVR and the temperature 3 Long Recovery Time In order to
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