RHF1401KSO-01V - STMicroelectronics
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1. DoclD13317 Rev 9 11 38 Electrical characteristics RHF1401 2 2 Timing characteristics Table 5 Timing characteristics Symbol Parameter Test conditions Min Typ EE Unit DC Clock duty cycle F 20 Msps 50 65 Data output delay fall of Tod clock to data valid 1 10 pF load capacitance 7 5 13 Tpa Data pipeline delay Duty cycle 50 7 5 cycles T Falling edge of OEB to 4 on digital output valid data T Rising edge of OEB to 4 off digital output tri state Tip Data rising time 10 pF load capacitance Tip Data falling time 10 pF load capacitance lal 1 As per Figure 11 2 If the duty cycle does not equal 50 Tpq 7 cycles CLK pulse width Figure 11 Timing diagram Analog input CLK Tpd Tod OEB Data output OR 1 The input signal is sampled on the rising edge of the clock while the digital outputs are synchronized on the falling edge of the clock The duty cycles on DR and CLK are the same AM06120 The rising and falling edges of the OR pin are synchronized with the falling edge of the DR pin 12 38 DoclD13317 Rev 9 Ly RHF1401 Electrical characteristics 2 3 Electrical characteristics after 300 kRad Unless otherwise specified the test conditions in the following tables are AVCC DVCC VCCBI VCCBE 2 5 V F 20 Msps Fiy 15 MHz Vin at 1 dBFS VREFP 1 V INCM 0 5 V VREFM 0 V Tamb 25 C Table 6 Analog inputs2. BR 35 Document revision history lille 36 d DoclD13317 Rev 9 RHF 1401 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 d RHF1401 block diagram 0 er 6 Pin connections top view Hu 7 Analog Inputs 4 24 cac44 deh a ESPERE Ee PRU dale de debeo E dne ick ud 9 OUI UL DUETS cocina eiat Ea RUP RS Oe ee det Fate ca ense Ea UR UR rs 9 Clock Input ou eee ad Pek baka PROC UESPGCUPRIUES GERNE De Cy PEAS ee qs 9 Data format input 0 000 cece s 9 Reference mode control input es 9 Output enable input 00 0 rn 9 VREFP and INCM input output aaan 10 siii P ofa td ere Me Se ee as Deh ee ee 10 TIMING diagram ea Choa eee da eee ea ee be ee eee 12 Rpo Values iz NR 15 Power consumption values vs Fs with internal references disabled 16 RHF1401 in recommended differential mode 0 0 0 cee eee 18 RHF 1401 in recommended single ended mode 00 e eee eee 20 Equivalent Vin Vinb differential input 0 0 0 cee ee 22 Example 2 Vpp differential input 223344 Kaka meo RT e 9 YR DUREE at ees 23 Differential implementation using a balun lil
3. 0 9Vxsin ot 2 Then CMinput is maximum when sin wt 1 that gives CMinputmax 1 15 V which is far beyond the limit of 0 65 V previously calculated The range of Vin allowed is 0 2 V to 0 65 V that is even below the half scale requested initially A solution to this problem would be to increase the CMref value which is done by increasing Vrefm and Vrefp Let s take Vrefm 0 5 V and calculate Vrefp to have CMref 0 2 V 1 15 V The solution is Vrefp 1 4 V that is 0 1 V higher than the maximum allowed in Table 4 So the only way is to reduce the input swing in accordance with the maximum Vrefp and Vrefm allowed With Vrefp 1 3 V Vrefm 0 5 V CMref 0 2 V 1 1 V CMinput maximum 1 1 V that gives Vbias 1 1 V A 2 With A 0 8 V Vbias 0 7 V gt Vinpp 1 6 V A Vbias 1 5 V Vbias A 0 1 V By reducing the input amplitude by 200 mVpp we are able to find a solution that fits the limits given in Table 4 With this example we can see that the main limitation in single ended mode on the condition to maximize the full digital swing 0 to 21 will come from the CMinput maxinum vs Vrefp and Vrefm allowed We can see also with the previous example to fit the large full swing requested you need three different biasing values Vrefp Vrefm Vbias INCM or four if the Vbias value is not compatible with the INCM range allowed More generally if the number of different biasing values is a problem its possib
4. DoclD13317 Rev 9 RHF1401 Revision history Table 18 Document revision history continued Date Revision Changes Added Table 1 Device summary on cover page Updated curves in Section 2 3 Electrical characteristics after 300 kRad Modified Section 3 1 Optimizing the power consumption Modified Section 3 2 Driving the analog input How to correctly bias the RHF1401 Modified Section 3 5 1 Internal voltage reference Modified Section 3 5 2 External voltage reference Modified Section 3 9 PCB layout precautions Updated Table 1 Modified Figure 1 RHF1401 block diagram Modified Figure 4 Output buffers Modified Table 4 Table 7 and Table 8 Modified Section 2 4 Results for differential input Modified Section 2 5 Results for single ended input Added comments and changed layout of Section 3 2 Driving the analog input How to correctly bias the RHF1401 Modified Table 12 Modified Figure 19 Added Table 13 Added comments to Section 3 5 Reference connections Modified Section 3 8 1 Digital inputs Modified Figure 3 Modified Table 4 Modified Table 6 Modified Table 8 Added OE and GE in Table 9 Rewording and new Section 3 1 Optimizing the power consumption Section 3 2 Driving the analog input How to correctly bias the RHF1401 Section 3 3 Output code vs analog input and mode usage Section 3 4 Design examples Section 3 5 Reference connections Section 3 6 Clock input Section 3 7 Reset of
5. External voltage reference setting DC source to the ADC pins VREFP VCCA VIN REFMODE VREFM AM04575 Figure 23 Example with zeners As close as possible to the ADC pins VCCA VREFP AM04576 Note The use of ceramic technology is preferable to ensure large bandwidth stability of the capacitor In multi channel applications the high impedance input when REFMODE 1 of the references allows one to drive several ADCs with only two voltage reference devices In differential mode the voltage of the analog input common mode INCM should be around Vpepp 2 Higher levels introduce more distortion d DoclD13317 Rev 9 27 38 User manual RHF1401 3 6 3 7 28 38 Clock input The quality of the converter very much depends on the accuracy of the clock input in terms of jitter The use of a low jitter crystal controlled oscillator is recommended The following points should also be considered e Theclock s power supplies must be independent of the ADC s output supplies to avoid digital noise modulation at the output e When powered on the circuit needs several clock periods to reach its normal operating conditions e The square clock must respect Table 5 and Table 10 The signal applied to the CLK pin is critical to obtain full performance from the RHF1401 It is recommended to use a square signal with fast transition times and to place proper termination res
6. Symbol Parameter Test conditions Min VREFP 1 V forced Full scale reference voltage FS Zin Input impedance vs INCM F 20 Msps ERB Effective resolution bandwidth Pf 70 MHz 1 See Section 4 Definitions of specified parameters for more information 2 Zin 1 Fs x C with C 2 4 pF Vin ViNB Table 7 Internal reference voltage Symbol Parameter Test conditions REFMODE 0 internal reference Output resistance of internal on Rout reference REFMODE 1 internal reference off Vrerp lop internal reference voltage REFMODE 0 Vincm _ Input common mode voltage REFMODE 0 1 Refer to Section 3 2 Driving the analog input How to correctly bias the RHF 1407 for correct biasing of RHF 1401 Table 8 External reference voltage Symbol Parameter Test conditions Mi T Max Unit in yp Forced top reference voltage REFMODE 1 0 5 Le 8 Forced bottom ref voltage REFMODE 1 fo os v Vin Feed ommon node ago REFWODE 1 oz lv 1 See Figure 22 amp Figure 23 Refer to Section 3 2 Driving the analog input How to correctly bias the RHF 1407 for correct biasing of RHF 1401 d DoclD13317 Rev 9 13 38 Electrical characteristics RHF1401 Table 9 Static accuracy Parameter Test conditions Unit DNL Differential non linearity Fi 1 5 Msps Vin at 1 dBFS INL Integral non linearity F 1 5 Msps Monotonicity and no missi
7. components from External references common mode on page 16 Updated Figure 1 RHF1401 block diagram Added explanation on Figure 3 Timing diagram Added introduction to Section 6 Typical performance characteristics Updated Section 7 2 Clock signal requirements and Section 7 3 Power consumption optimization Added Section 7 4 Low sampling rate recommendations Updated information on Data Ready signal in Section 7 5 Digital inputs outputs Added Figure 24 Impact of clock frequency on RHF1401 performance and Figure 25 CLK signal derivation 29 Jun 2007 29 Oct 2007 Changed input clock features in Table 10 09 Nov 2009 3 Modified Table 14 Added Figure 24 to Figure 42 Modified Figure 1 RHF1401 block diagram Added details for Tdr and changed values for Tpd in Table 5 Timing characteristics Modified Figure 11 Timing diagram Changed values for VREFP in Table 4 Changed Vin operating conditions in Table 4 Figure 42 and Figure 19 Changed values for DNL in Table 9 26 Feb 2010 4 Modified Figure 1 on page 6 and Figure 9 on page 10 Added note 2 on page 12 Modified Cj typ value in Table 6 Analog inputs as per Figure 3 13 Sep 2010 5 Modified Figure 11 Timing diagram Replaced Figure 18 Added Table 12 Output codes for DFSB 1 Modified Figure 17 Example 2 Vp differential input 29 Jul 2011 6 Added Note on page 31 and in the Pin connections diagram on the cover page 3
8. converter goes on sampling When OEB is set to a low level again the data arrives on the output with a very short To delay This feature enables the chip select of the device Figure 11 Timing diagram summarizes this functionality Reference mode control REFMODE this allows the internal or external settings of the voltage references VREFP and INCM REFMODE 0 for internal references REFMODE 1 for external references and disables both references VREFP and INCM 3 8 2 Digital outputs Out of range OR this function is implemented on the output stage in order to set an out of range flag whenever the digital data is over the full scale range Typically there is a detection of all data at 0 or all data at 1 It sets an output signal OR which is in a low level state VoL when the data stays within the range or in a high level state V4 when the data read by the ADC is out of range Data ready DR the Data Ready output is an image of the clock being synchronized on the output data DO to D13 This is a very helpful signal that simplifies the synchronization of the measurement equipment of the controlling DSP Like all other digital outputs DR goes into high impedance when OEB is set to a high level as shown in Figure 11 Timing diagram d DoclD13317 Rev 9 29 38 User manual 3 8 3 Fall time nS 3 9 30 38 RHF 1401 Digital output load considerations The features of the internal output buffers
9. impedance A die gt b pad A DoclD13317 Rev 9 AGND AM04564 AM04563 d RHF1401 Electrical characteristics 2 Electrical characteristics 2 1 Absolute maximum ratings and operating conditions Table 3 Absolute maximum ratings Symbol Parameter Values Unit VCCBI Digital buffer supply voltage VccBE Digital buffer supply voltage 3 6 gt IN Analog inputs bottom limit gt top limit 0 6 V gt AVcc 0 6 V INB ME External references bottom limit gt top limit 0 6 V gt AVcc 0 6 V V INCM IDout Digital output current 100 to 100 Tstg Storage temperature 65 to 150 Rinic Thermal resistance junction to case 22 Rthja Thermal resistance junction to ambient ESD HBM human body model 1 Human body model a 100 pF capacitor is charged to the specified voltage then discharged through a 1 5 kW resistor between two pins of the device This is done for all couples of connected pin combinations while the other pins are floating Table 4 Operating conditions Max Unit Analog supply voltage 2 7 V Digital supply voltage i 2 7 Digital internal buffer supply 2 7 V V ECO omnes os V Bottom external reference voltage 0 0 0 5 Difference between external reference voltage 0 3 V Forced common mode voltage 0 2 0 5 1 1 V Max voltage versus GND MEA 1 6 V Min voltage versus GND V REFMODE Digital inputs Vecpe V OEB
10. limit the maximum load on the digital data output In particular the shape and amplitude of the Data Ready signal toggling at the clock frequency can be weakened by a higher equivalent load In applications that impose higher load conditions it is recommended to use the falling edge of the master clock instead of the Data Ready signal This is possible because the output transitions are internally synchronized with the falling edge of the clock Figure 24 Output buffer fall time Figure 25 Output buffer rise time VCCBE 2 5V mm VCCBE 2 5V VCCBE 3 3V VCCBE 3 3V a Rise time nS 20 30 40 50 0 10 20 30 40 50 load capacitor pF load capacitor pF PCB layout precautions A ground plane on each layer of the PCB with multiple vias dedicated for inter connexion is recommended for high speed circuit applications to provide low parasitic inductance and resistance The goal is to have a common ground plane where AGND and DGND are connected with the lowest DC resistance and lowest AC impedance To minimize the transition current when the output changes the capacitive load at the digital outputs must be reduced as much as possible by using the shortest possible routing tracks One way to reduce the capacitive load is to remove the ground plane under the output digital pins and layers at high sampling frequencies The separation of the analog signal from the c
11. proper matching with a 50 Q generator The tracks between the secondary and Vin and Vinb pins must be as short as possible DoclD13317 Rev 9 23 38 User manual RHF1401 Figure 18 Differential implementation using a balun ADT1 1 C 50 Q track 1 1 Analog input signal 50 Q output Short track External INCM 470 nF ceramic 100 nF ceramic K as close as possible as close as optional to the transformer possible to INCM pin the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04571 The input common mode voltage of the ADC INCM is connected to the center tap of the transformer s secondary in order to bias the input signal around the common voltage see Table 7 Internal reference voltage The INCM is decoupled to maintain a low noise level on this node Ceramic technology for decoupling provides good capacitor stability across a wide bandwidth Single ended mode Note 24 38 Figure 19 shows an example of how to drive the RHF 1401 in single ended and DC coupled This is the optimized configuration recommended For more explanations see Chapter 3 2 Driving the analog input How to correctly bias the RHF1401 Figure 19 Optimized single ended configuration DC coupling 2 3V to 2 7V Internal or External DC value VREFP 2 VREFP 2 10uF 100nF ceramic AGND as close as possible to VINB pin T GND GND The use o
12. 0 4 V to 1 V Output code vs analog input and mode usage Whatever the configuration chosen differential or single ended the two following equations are always true for RHF1401 e The full scale of the analog input is defined by Full scale 2 x Vrefp Vrefm e The output code is defined also as Output code f Vin Vinb vs Full scale Finally we got for DFSB 1 _ 8FFF x Vin VinB Output code 14 bits 2 x Vrefp Vrefm 1FFF and for DFSB 0 _ 8FFF x Vin VinB Output code 14 bits 2 x Vrefp Vrefm 1FFF 2000 DoclD13317 Rev 9 21 38 User manual 3 3 1 3 3 2 22 38 Differential mode output code RHF 1401 In this mode the DC component of Vin and Vinb is naturally subtracted We get the following table Table 12 Differential mode output codes Vin Vinb DFSB 1 DFSB 0 VREFP VREFM 3FFF 1FFF 0 1FFF 3FFF VREFP VREFM 0000 2000 If INCM Vbias we have Figure 16 Figure 16 Equivalent Vin Vinb differential input FS full scale 2 VREFP VREFM VIN VINB Single ended mode output code level FS code 16383 INCM level 0 code 8191 level FS code 0 AM04567 In single ended mode Vin or Vinb is constant and equal to Vbias If Vin Vbias A sin ot and Vinb Vbias with A peak of input signal then Vin Vinb A sin ot and A Vrefp Vrefm for maximum swing on input Table 13 Single ended
13. 01 17 3 2 1 Differential mode biasing llle 17 3 2 2 Single ended mode biasing llis 18 3 2 3 INCM biasing i RR RR ERR ERR y REX YE GRE ee 21 3 3 Output code vs analog input and mode usage 21 3 3 1 Differential mode output code 000 eee ees 22 3 3 2 Single ended mode output code 0 cee te 22 3 4 Design examples i usce eu Rh RT RR Seed ok a ete hae Bae 23 Differential mode 00000 eee eee 23 Single ended mode 0 eee 24 3 5 Reference connections cee 26 3 5 1 Internal voltage reference ee 26 3 5 2 External voltage reference lille 26 3 6 CIOCK IDDUL s icu eee de ae dob E ac n A OE Qt cavata dr C RR 28 3 7 Reset of RHF1401 2 20 000 ees 28 3 8 Operating modes ua eacus 173 ene nen des ROI OE oo cde BRUN TR Inc TR 29 3 8 1 Digital Inputs ase nd a eed be alee bose eR RE 29 3 8 2 Digital outputs exsules UR dba eo vedere ede eg awe ss 29 3 8 3 Digital output load considerations 22020 eee eee 30 3 9 PCB layout precautions 0 000 ees 30 2 38 DoclD13317 Rev 9 Ly RHF 1401 4 d Contents Definitions of specified parameters 31 4 1 Static parameters 2 0 cee 31 4 2 Dynamic parameters 20 220 AA AA eee eee 31 Package information esee rre rn ed bebe ences 32 Ordering information 6060scecece shee see ecndeedeee seen
14. 12 as the optimum DoclD13317 Rev 9 15 38 User manual RHF1401 Figure 13 Power consumption values vs F with internal references disabled 80 o e e n e Ww e N e Power consumption mW D a e e T T T T T 0 5 25 45 6 5 85 105 125 145 165 185 Sampling frequency MHz d 16 38 DoclD13317 Rev 9 RHF 1401 3 2 3 2 1 a User manual Driving the analog input How to correctly bias the RHF1401 It s mandatory to follow some simple biasing rules to reach optimal performance when driving the RHF1401 DC biasing and the AC swing must be considered in order to keep the analog input in the correct range Let s define some parameters Definition 1 The common mode of the input signal is CMinput Vin Vinb 2 Definition 2 The common mode of reference voltage is CMref Vrefp Vrefm 2 To have correct biasing of RHF1401 this condition must be respected at all times CMinput x CMref 0 2V Please note that the INCM value is not a parameter of the previous equations INCM is an input output that s used to bias internal OTA amplifiers So INCM can be any value from Table 4 However if the INCM value is used to bias analog inputs Vin and Vinb Cminput becomes dependent of INCM In this case the setting of INCM must be chosen to respect the equation CMinput lt CMref 0 2V Now let s see what happens when the RH
15. 34 Other information 15 2 00 isda weds esses este een edn dedewes es wn 35 7 1 Date code uisa BAKAL nanan awe eee ae ew ala Paes 35 7 2 Documentation 24 545 6 04 0444 eR aor po tee eta NOCERE NA eS 35 REVISION history 2 4 ccc o5 oe eed Seb week ieee des ieee RR 36 DoclD13317 Rev 9 3 38 List of tables RHF1401 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 4 38 Devic SUMMA edat eee Leda c pia ved er Du Run pee PRO ee Se P ec ds 1 PIN descriptio iS ass ye ker Ex on dcn spe e tx aia air Ria BE re RU RER BT COEUR nn 8 Absolute maximum ratings eee eae 11 Operating conditions 0 eR eee 11 Timing characteristics 0 mh 12 Analog Inputs tente eee NAG ad m ee eee de ee 13 Internal reference voltage 1 eee tae 13 External reference voltage liiis 13 Otatic accuracy cse Seanad x peu be ped peg a s pe eu Sack Mian vend tak d 14 Digital inputs and outputs 0 00 0000 cee 14 Dynamic characteristics rrasa riiai ebeit iania a 14 Differential mode output codes 0 00 ee 22 Single ended mode output codes with Vinb Vbias and A Vrefp Vrefm 22 RHF1401 operating modes ne 29 Ceramic SO 48 package mechanical data llle 33 eTio Tresor 34 Documentation provided for QMLV flight
16. BE 23 DR Digital ou Data ready output Digital buffer power supply Digital buffer ground put LSB CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V 2 5 V 3 3 V 44 45 DGND 46 CLK Digital power supply Digital ground Clock input Digital ground 2 5 V compatible CMOS input 24 Digital buffer power supply 47 DGND 48 DGND 1 See load considerations in Section 2 2 Timing characteristics 8 38 DoclD13317 Rev 9 Digital ground d RHF 1401 Description 1 4 Equivalent circuits Figure 3 Analog inputs Figure 4 Output buffers VCCBE AVCC OEB VIN or VINB Zin 1 Cs Fs ira 4 DO D13 IN Ga S NAR VCCBE INCM AGND GNDBE AM04558 Figure 5 Clock input Figure 6 Data format input DVCC VCCBE CLK DFSB E Lo gt 7 pF 7 pF pad pad d DGND GNDBE AM04559 AM04560 Figure 7 Reference mode control input Figure 8 Output enable input VCCBE VCCBE REFMODE OEB gt CI Do 7pF pad b GNDBE GNDBE AM04561 DoclD13317 Rev 9 AM04562 9 38 Description 10 38 RHF1401 Figure 9 VREFP and INCM input output AVCC AVCC VREFP INCM A Jes ryf 7 pF A s REFMODE pad REFMODE AGND Figure 10 VREFM input AVCC 9 VREFM High input
17. F1401 is driven in differential mode and single ended mode We will use a sinusoidal input signal for ease of computation but the results presented after can be easily extrapolated to another kind of signal shape Differential mode biasing In differential mode we have e Vin Vbias A sin ot and Vinb Vbias A sin ot with A peak of input signal e Vbias can be provided by the source signal or by INCM It s the DC biasing of the sinusoidal input signal As by definition AC components are in opposite phase for Vin and Vinb at any time on the signal we have CMinput Vbias In differential mode to keep a safe operation of RHF 1401 analog inputs we have to respect Vbias lt CMref 0 2V and referring to Table 4 for the maximum input signal allowed we have A Vbias x 1 6V and Vbias Az 0 2V DoclD13317 Rev 9 17 38 User manual RHF1401 3 2 2 18 38 Figure 14 RHF1401 in recommended differential mode 2 3V to 2 7V Internal or External AVCC VREFP INCM Internal or External Maximum DC value VREFP VREFM 2 0 2V N AGND External GND Single ended mode biasing In single ended mode the biasing consideration is different because as we will see CMinput is no longer constant but dependent on the amplitude of the input signal This dependency limits considerably the possibilities of single ended use Please note also that in the demonstration below Vin is variable an
18. RHF1401 Section 3 9 PCB layout precautions Added footnote 7 to Table 6 Added Section 7 Other information 06 Apr 2012 24 Oct 2012 22 July 2014 3 DoclD13317 Rev 9 37 38 RHF 1401 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2014 STMicroelectronics All rights reserved d 38 38 DoclD13317 Rev 9
19. d Vinb is fixed but the opposite is possible simply by exchanging Vin and Vinb in the equations Let s take a typical situation with Vin Vbias A sin t and Vinb Vbias with A peak of input signal Vbias can be provided by the source signal or by INCM which is the DC biasing of sinusoidal input signal In this case CMinput smol Vbias and CMinput is totally dependent on the amplitude of the input signal In addition as the following relationship is still true CMinput lt CMref 0 2V now we have GAL Vbias lt CMref 0 2V and of course and referring to Table 4 for the maximum input signal allowed we have A Vbias x 1 6V 3 DoclD13317 Rev 9 RHF 1401 a User manual and Vbias A 2 0 2V So depending on the settings of Vrefp Vrefm the following condition AM Vbias lt CMref 0 2V can occur very soon before reaching the full scale input of RHF1401 Example you have an input signal in single ended that maximizes the full swing authorized for RHF1401 input 0 2 V to 1 6 V which gives 1 8 Vpp in single ended The biasing settings are as follows e As the full scale of ADC is defined by Vrefp Vrefm x2 if Vrefm 0 V we have 2xVrefp 31 8 V then Vrefp 0 9 V e Vbias 1 6 V 1 8V 2 0 7 V then Vin 0 7 V 1 8V 2 xsin ot 0 7 V 0 9Vxsin ot then A 0 9 V e Vinb Vbias Vin 0 7 V With these setttings we can calculate CMref 0 2 V 0 65 V and CMinput 0 7 V
20. ed to the dice Not connected to the dice 26 OEB 29 Output enable input Data format select input Analog power supply alog power supply 2 5 V 3 3 V CMOS input 2 5 V 3 3 V CMOS input OR Out of range output CMOS output 2 5 V 3 3 V 30 log ground D13 MSB Most significant bit output CMOS output 2 5 V 3 3 V 31 og bias current input D12 D11 D10 Digital outp ut Digital output Digital output Digital output CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V 32 33 34 AGND 35 VIN VREFM Top voltage reference Bottom voltage reference Analog ground Analog input Can be external or internal Digital output CMOS output 2 5 V 3 3 V Analog ground Digital output CMOS output 2 5 V 3 3 V 37 Inverted analog input D5 D4 Digital outp ut Digital output Digital ou put put Digital ou CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V CMOS output 2 5 V 3 3 V CMOS output 2 5V 3 3 V 38 39 40 AGND 41 INCM Analog ground Input common mode Analog ground Analog power supply Can be external or internal 18 D2 Digital output CMOS output 2 5 V 3 3 V 42 Analog power supply 19 D1 Digital output CMOS output 2 5 V 3 3 V 43 Digital power supply 20 DO LSB 21 22 VCC
21. ents in the Nyquist band F 2 excluding DC fundamental and the first five harmonics Expressed in dB Signal to noise and distortion ratio SINAD A similar ratio to the SNR but that includes the harmonic distortion components in the noise figure not the DC signal Expressed in dB From SINAD the effective number of bits ENOB can easily be deduced using the formula SINAD 6 02x ENOB 1 76 dB When the analog input signal is not full scale FS but has an Ag amplitude the SINAD expression becomes SINAD 6 02x ENOB 1 76 dB 20 log Ag FS Analog input bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 dB Higher values can be achieved with smaller input levels Pipeline delay The delay between the initial sample of the analog input and the availability of the corresponding digital data output on the output bus Also called data latency Expressed as a number of clock cycles DoclD13317 Rev 9 31 38 Package information RHF1401 5 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark a 32 38 DoclD13317 Rev 9 RHF 1401 Note Package information Figure 26 Ceramic SO 48 package mechanica
22. f ceramic technology is preferable to ensure large bandwidth stability of the capacitor DoclD13317 Rev 9 Ly RHF 1401 d User manual As some applications may require a single ended input it can be easily done with the configuration shown in Figure 19 for DC coupling and Figure 20 for AC coupling However with this type of configuration a degradation in the rated performance of the RHF1401 may occur compared with a differential configuration You should expect a degradation of ENOB of about 2 bits compared to differential mode A sufficiently decoupled DC reference should be used to bias the RHF1401 inputs An AC coupled analog input can also be used and the DC analog level set with a high value resistor R 10 kQ connected to a proper DC source Cin and R behave like a high pass filter and are calculated to set the lowest possible cut off frequency Figure 20 AC coupling single ended input configuration 50 Q track Analog input signal 50 Q output 50 Q Short track 470pF 1 100 nF ceramic C ceramic External INCM optional TI 100 nF ceramic as close as possible to INCM pin the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor AM04572 DoclD13317 Rev 9 25 38 User manual RHF1401 3 5 3 5 1 3 5 2 26 38 Reference connections Internal voltage reference In standard configuration the ADC is biased with two internal volta
23. ge references VREFP and INCM They must be decoupled to minimize low and high frequency noise When the REFMODE pin is set to O both internal voltage references are enabled and they can drive external components The VREFM pin has no internal reference and must be connected to a voltage reference It is usually connected to the analog ground for differential mode and to Vrefp 2 for single ended mode Figure 21 Internal voltage reference setting As close as possible to the ADC pins 470 nF 100 nF 470 nF y o the use of a ceramic technology is preferable for a large bandwidth stability of the capacitor REFMODE VREFM AM04574 External voltage reference External voltage references can be used for specific applications requiring better linearity enhanced temperature behavior or different voltage values see Table 7 Internal reference voltage Internal voltage references are disabled when the REFMODE pin is equal to 1 In this case external voltage references must be applied to the device When internal voltage reference are disabled ADC consumption is about 13 mA less than when they are enabled The external voltage references with the configuration shown in Figure 22 and Figure 23 can be used to obtain optimum performance Decoupling is achieved by using ceramic capacitors which provide optimum linearity versus frequency d DoclD13317 Rev 9 RHF 1401 User manual Figure 22
24. iis 24 Optimized single ended configuration DC coupling llle 24 AC coupling single ended input configuration aaau 25 Internal voltage reference setting llle 26 External voltage reference setting lille 27 Example with zeners 0000 eects 27 Output buffer fall time 2 0 0 0 0 0 eee 30 Output buffer rise time 000 cc tenes 30 Ceramic SO 48 package mechanical drawing 0 0 eee eee 33 DoclD13317 Rev 9 5 38 Description 1 1 6 38 Description Block diagram Figure 1 RHF1401 block diagram RHF 1401 VIN INCM VINB CLK GND Digital data correction VREFP VCCBI Biasing current setup VCCBE AM04556 DoclD13317 Rev 9 d RHF 1401 1 2 d Pin connections Figure 2 Pin connections top view GNDBI DGND GNDBE DGND VCCBE CLK NC DGND NC DVCC OR 6 DVCC MSB D13 AVCC D12 AVCC D11 9 AGND D10 INCM D9 AGND D8 VINB D7 AGND D6 VIN D5 AGND D4 VREFM D3 VREFP D2 IPOL D1 AGND LSB DO AVCC DR AVCC VCCBE DFSB GNDBE OEB DoclD13317 Rev 9 REFMODE Description 7 38 Description 1 3 1 Digital buffer ground Pin descriptions Table 2 Pin descriptions Observations 0v REFMODE Ref mode control input RHF 1401 Observations 2 5 V 3 3 V CMOS input 2 3 VCCBE Digital buffer ground Digital buffer power supply NC 0v 2 5 V 3 3 V Not connect
25. irst Let s take a typical example for differential mode Vrefp 1 V Vrefm 0 V Vbias INCM 0 5 V This safe configuration gives a full scale at 2 Vpp 1 Vpp on each input with Vbias 0 5 V and A 0 5 V Here you can use all digital output codes from 0 to 2 4 Now let s go to single ended mode by keeping Vrefp 1 V Vrefm 0 V Vbias INCM Vinb 0 5 V What would be the maximum swing allowed on Vin and what would be the resulting code So Full scale 2 x Vrefp Vrefm 2 V 3 DoclD13317 Rev 9 RHF 1401 3 2 3 3 3 User manual CMref 0 5 V and CMref 0 2V 20 7 V By definition the limitation on the lower side is 0 2 V The limitation of Vin on the upper side is given by this equation OD x Vbias 207V So Vinmax 0 9 V Finally 0 2V x Vin x 0 9V that gives 5734 lt Output Code decimal lt 11468 Here the full scale is not usable but a limited range only INCM biasing As previously discussed INCM is an input output that s used to bias the internal OTA amplifiers of the RHF1401 So INCM can be any value from Table 4 However depending on the INCM value the performance can change slightly For RHF 1401 and for INCM from 0 4 V to 1 V no impact on performances can be observed For INCM from 0 2 V to 0 4 V and 1 V to 1 1 V it s possible to have under boundary conditions a typical loss of one bit of ENOB So if you have the choice keep the value of INCM in the range
26. istors as close as possible to the device Reset of RHF1401 To reset the RHF1401 it s mandatory to apply several clock periods At power up without any clock signal applied to RHF1401 the device is not reset In this case parameters like Vrefp Incm and Rout will not be in line with values in Table 7 d DoclD13317 Rev 9 RHF1401 User manual 3 8 Operating modes Extra functionalities are provided to simplify the application board as much as possible The operating modes offered by the RHF1401 are described in Table 14 Table 14 RHF1401 operating modes Inputs Outputs Analog input differential nBsp 0EB Most significant bit MSB amplitude H Vin Ving above maximum range L D13 complemented Vi Via bel NN H D13 elow minimum range Ho L D13 complemented H D13 Vin Vinp within range TE CIN L CLK D13 complemented X X H uz uz HZ all digital outputs are in high impedance 1 High impedance 3 8 1 Digital inputs Data format select bit DFSB when set to low level Vi the digital input DFSB provides a two s complement digital output MSB This can be of interest when performing some further signal processing When set to high level Vi DFSB provides standard binary output coding see Table 12 Output enable bit OEB when set to low level Vi all digital outputs remain active When set to high level Vj all digital output buffers are in a high impedance state while the
27. k SA life augmented RHF1401 Rad hard 14 bit 20 Msps A D converter Ceramic SO 48 package ma mmmmmmmmm The upper metallic lid is not electrically connected to any pins nor to the IC die inside the package Features e Qml V qualified smd 5962 06260 e Rad hard 300 kRad Si TID e Failure immune SEFI and latch up immune SEL up to 120 MeV cm mg at 2 7 V and 125 C e Hermetic package e Tested at F 20 Msps e Low power 85 mW at 20 Msps e Optimized for 2 Vpp differential input e High linearity and dynamic performances e 2 5 V 3 3 V compatible digital I O e Internal reference voltage with external reference option Datasheet production data Applications e Digital communication satellites e Space data acquisition systems e Aerospace instrumentation e Nuclear and high energy physics Description The RHF 1401 is a 14 bit analog to digital converter that uses pure ELDRS free CMOS 0 25 um technology combining high performance radiation robustness and very low power consumption The RHF1401 is based on a pipeline structure and digital error correction to provide excellent static linearity Specifically designed to optimize power consumption the device only dissipates 85 mW at 20 Msps while maintaining a high level of performance The device also integrates a proprietary track and hold structure to ensure a large effective resolution bandwidth Voltage references are integrated in the circ
28. l drawing N 2 Places b N Places The upper metallic lid is not electrically connected to any pins nor to the IC die inside the package Connecting unused pins or metal lid to ground or to the power supply will not affect the electrical characteristics Table 15 Ceramic SO 48 package mechanical data Dimensions Ref Millimeters Inches Min Typ Max Min Typ Max b 0 20 0 254 0 30 0 008 0 010 0 012 C 0 12 0 15 0 18 0 005 0 006 0 007 D 15 57 15 75 15 92 0 613 0 620 0 627 E 9 52 9 65 9 78 0 375 0 380 0 385 E1 10 90 0 429 E2 6 22 6 35 6 48 0 245 0 250 0 255 E3 1 52 1 65 1 78 0 060 0 065 0 070 e 0 635 0 025 f 0 20 0 008 L 12 28 12 58 12 88 0 483 0 495 0 507 P 1 30 1 45 1 60 0 051 0 057 0 063 Q 0 66 0 79 0 92 0 026 0 031 0 036 S1 0 25 0 43 0 61 0 010 0 017 0 024 DoclD13317 Rev 9 33 38 Ordering information RHF1401 6 Ordering information Table 16 Order codes RHF1401KSO1 Engineering model RHF1401KSO1 55 C to 125 C SO 48 Strip pack RHF1401KSO 01V QML V flight 5962F0626001VXC 1 Specific marking only Complete marking includes the following SMD pin for QML flight only ST logo Date code date the package was sealed in YYWWA year week and lot index of week QML logo Q or V Country of origin FR France Note Contact your ST sales office for information regarding the specific c
29. le to work in single ended with two different biasing values By setting INCM Vrefm Vbias Vinb Vrefp 2 you can have a simple single ended as represented in Figure 15 DoclD13317 Rev 9 19 38 User manual RHF1401 20 38 Figure 15 RHF1401 in recommended single ended mode 2 3V to 2 7V Internal or External DC value VREFP 2 VREFP 2 AGND GND External However we can calculate that the main limitation will come from the Vrefm maximum value 0 5 V Let s take Vrefm INCM Vbias Vinb 0 5 V and Vrefp 1 V gt the input swing allowed on Vin is 1 Vpp centered at 0 5 V gt A 0 5 V Here CMref 0 75 V and CMinput maximum 0 75 V So for an input voltage Vin from 0 V to 1 V the output code will vary from 0 to 214 Now let s see how much the maximum input amplitude Vin can be to go in saturation mode bit OR set to 1 As CMref 0 2 V 0 95 V the theoretical input voltage Vin allowed can be Vin 0 5 V 0 9 V sin ot Here CMinput maximum 0 95 V but A Vbias 1 4 V and Vbias A 0 4 V The 0 4 V is a problem because only 0 2 V is allowed Finally the practical input voltage Vin is Vin 0 5 V 0 7 V sin ot gt CMinput maximum 0 85 V A Vbias 1 2 V and Vbias A 0 2 V Particular case where Vrefm 0 V and cannot be changed In some applications a dual mode can be requested differential mode and single ended mode with a preference for differential mode f
30. lock signal and digital outputs is mandatory to prevent noise from coupling onto the input signal Power supply bypass capacitors must be placed as close as possible to the IC pins to improve high frequency bypassing and reduce harmonic distortion All leads must be as short as possible especially for the analog input so as to decrease parasitic capacitance and inductance Choose the smallest possible component sizes SMD 3 DoclD13317 Rev 9 RHF 1401 4 4 1 4 2 3 Definitions of specified parameters Definitions of specified parameters Static parameters Differential non linearity DNL The average deviation of any output code width from the ideal code width of 1 LSB Integral non linearity INL An ideal converter exhibits a transfer function that is a straight line from the starting code to the ending code The INL is the deviation from this ideal line for each transition Dynamic parameters Spurious free dynamic range SFDR The ratio between the power of the worst spurious signal not always a harmonic and the amplitude of the fundamental tone signal power over the full Nyquist band Expressed in dBc Total harmonic distortion THD The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line Expressed in dB Signal to noise ratio SNR The ratio of the rms value of the fundamental component to the rms sum of all other spectral compon
31. mode output codes with Vinb Vbias and A Vrefp Vrefm Vin Vbias VREFP VREFM Vbias Vbias VREFP VREFM DFSB 1 3FFF 1FFF 0000 DFSB 0 1FFF 3FFF 2000 DoclD13317 Rev 9 d RHF 1401 3 4 User manual Design examples The RHF 1401 is designed to obtain optimum performance when driven on differential inputs with a differential amplitude of two volts peak to peak 2 Vpp This is the result of 1 Vpp on the Vin and Vinb inputs in phase opposition Figure 17 For all input frequencies it is mandatory to add a capacitor on the PCB between Vin and Vinb to cut the HF noise The lower the frequency the higher the capacitor The RHF1401 is specifically designed to meet sampling requirements for intermediate frequency IF input signals In particular the track and hold in the first stage of the pipeline is designed to minimize the linearity limitations as the analog frequency increases Differential mode d Figure 17 shows an example of how to drive the RHF1401 in differential and DC coupled Figure 17 Example 2 Vp differential input REFP 2 5V REFMODE 1 Vp p 1Vp p 7 Ground VIN VINB 2 Vp p AM04570 Figure 18 shows an isolated differential input solution The input signal is fed to the transformer s primary while the secondary drives both ADC inputs The transformer must be matched with the generator output impedance 50 Q in this case for
32. ng codes OE Offset Error Fs 5Msps GE Gain Error Fs 5Msps 1393 Table 10 Digital inputs and outputs Symbol Parameter Test conditions Min Typ Max Unit Clock input CT Clock threshold DVcc 2 5 V 1 25 V Square clock amplitude i CA DC component 1 25 V DVcc 2 5 V 0 8 2 5 Vpp Digital inputs a 0 25 x V Logic 0 voltage V 2 5V 0 V IL g g CCBE Veaue Vin Logic mq voltage VccBE 2 5V dia VccBE V VccBE Digital outputs VoL Logic 0 voltage lo 10 pA 0 0 25 V Logic 1 voltage lon 10 pA V High impedance leakage OEB set to Vy 45 UA current Output load capacitance High eK 15 pF frequencies Table 11 Dynamic characteristics Symbol Parameter Test conditions Min Typ Max Unit Spurious free dynamic range dBFS Signal to noise ratio Fin 15 MHz dB Total harmonic distortion Fs 20 Msps dB Vin at 1 dBFS Signal to noise and distortion internal references dB ratio C 6 pF Effective number of bits j bits Higher values of SNR SINAD and ENOB can be obtained by increasing the full scale range of the analog input if the sampling frequency and the biasing of RHF1401 allow it 14 38 DoclD13317 Rev 9 Ly RHF 1401 3 3 1 d User manual User manual Optimizing the power consumption The polarization current in the input stage is set by an external resistor R55 When selecting the resistor value it is possible to optimize the power cons
33. onditions for products in die form and QML Q versions a 34 38 DoclD13317 Rev 9 RHF 1401 7 7 1 7 2 Other information Other information Date code The date code is structured as shown below e Engineering model EM xyywwz e QML flight model FM yywwz Where x EM only 3 assembly location Rennes France yy last two digits year ww week digits z lot index in the week Documentation Table 17 Documentation provided for QMLV flight Quality level Documentation Engineering model Certificate of conformance with Group C reliability test and group D package qualification reference Precap report PIND test summary test method conformance certificate SEM report X ray report Screening summary Failed component list list of components that have failed during screening Group A summary QCI electrical test Group B summary QCI mechanical test Group E QC wafer lot radiation test QML V flight 1 PIND particle impact noise detection 2 SEM scanning electron microscope 3 QCI quality conformance inspection DoclD13317 Rev 9 35 38 Revision history RHF1401 8 36 38 Revision history Table 18 Document revision history Date Revision Changes First public release Failure immune and latchup immune value increased to 120 MeV cm2 mg Updated package mechanical information Removed reference to non rad hard
34. uit to simplify the design and minimize external components A tri state capability is available on the outputs to allow common bus sharing A data ready signal which is raised when the data is valid on the output can be used for synchronization purposes The RHF1401 has an operating temperature range of 55 C to 125 C and is available in a small 48 pin ceramic SO 48 package Table 1 Device summary level RHF1401KSO1 Engineering model RHF1401KSO 01V 5962F0626001VXC QMLV Flight Lead 1 Package EDS EPPL Temp range 55 C to 125 C 1 EPPL ESA preferred part list July 2014 This is information on a product in full production DoclD13317 Rev 9 1 38 www st com Contents RHF1401 Contents 1 DGSCPUGN sse Ka ignite esterase se bo ha NA ERKEREMR AER NE bee d cane 6 1 1 BOCK CHAO AN MCCC 6 1 2 Pin connections ccc nes 7 1 3 Pin d scriptions i usce bte D Ce Re Ce hee KANG ee NANG 8 1 4 Equivalent circuits llle 9 2 Electrical characteristics 0000 e eee eee 11 2 1 Absolute maximum ratings and operating conditions 11 2 2 Timing characteristics s du pem a KAR eia KAKA o3 gau X LANG KKK 12 2 3 Electrical characteristics after 300 kRad 13 3 User Manpal asasesuaesh e eRPRSERA RE RR RM EAR PES RE EE ERE 15 3 1 Optimizing the power consumption a 15 3 2 Driving the analog input How to correctly bias the RHF14
35. umption according to the sampling frequency of the application For this purpose an external Rpg resistor is placed between the IPOL pin and the analog ground The values in Figure 12 are achieved with VREFP 1 V VREFM 0 V INCM 0 5 V and the input signal is 2 Vpp with a differential DC connection If the conditions are changed the Roo resistor varies slightly but remains in the domain described in Figure 12 Figure 12 shows the optimum Rpa resistor value to obtain the best ENOB value It also shows the minimum and maximum values to get good results ENOB decreases by approximately 0 2 dB when you change Rpg from optimum to maximum or minimum If Roo is higher than the maximum value there is not enough polarization current in the analog stage to obtain good results If Rp is below the minimum THD increases significantly Therefore the total dissipation can be adjusted across the entire sampling range to fulfill the requirements of applications where power saving is critical For sampling frequencies below 2 MHz the optimum resistor value is approximately 80 kOhms Figure 12 Ry values vs Fs 10000 Rpol max kOhms Rpol kOHms Rpol min kOhms Average Rpol kOhms 10 0 5 1 2 4 8 16 Sample Frequency MHz The power consumption depends on the Rp value and the sampling frequency In Figure 13 it is shown with the internal references disabled REFMODE 1 and Rpg defined in Figure
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